The present disclosure relates to methods of forming semiconductor structures, and particularly to methods of forming a shallow trench isolation structure on a semiconductor substrate after formation of gate stacks, and structures formed by the same.
Shallow trench isolation structures are employed to provide lateral electrical isolation among semiconductor devices in a semiconductor substrate. However, methods of forming shallow trench isolation structures as known in the art generate many undesirable effects on device performance and reliability. For example, it has been well known that divots around boundaries of shallow trench isolation structures can expand in preclean or wet etch steps, and subsequently provide a leakage path when a conductive material is deposited therein.
When embedded source and drain regions are formed in a structure including shallow trench isolation structures, additional complications to device performance can arise due to interaction between the embedded source and drain regions and the shallow trench isolation structures. For example, embedded Si:C source and drain regions in an n-type field effect transistor (NFET) can increase the on-current of the NFET, but facets are formed at the interface between the embedded Si:C source and drain regions and the shallow trench isolation structures. Similar facets are also formed between embedded silicon-germanium alloy source and drain regions in a p-type field effect transistor (PFET) and the shallow trench isolation regions in contact with the embedded silicon-germanium alloy source and drain regions.
Such facets introduce strong variability of the device threshold voltage as well as increased variability of the device threshold voltage as a function of the width of the device because of stress loss and additional threshold voltage-width effect. In addition, the facets also cause gate lines to develop a significant topography, resulting in wavy vertical gate stack profiles.
In addition, the methods of forming shallow trench isolation structures as known in the art introduces variability in the printed lithographic images for gate lines as a function of the density of underlying shallow trench isolation regions. Further, since the shallow trench isolation structures are subjected to subsequent thermal anneals including dopant activation anneals performed at temperatures greater than 700° C., dopants diffuse to the boundaries of the shallow trench isolation structures and increase leakage current between neighboring devices.
The above discussed phenomena adversely impacts performance of devices laterally isolated by shallow trench isolation structures as known in the art.