1. Field of the Invention
The invention relates to memory controllers used with computers, and more particularly to memory controllers that dynamically predict the relative chance of a page miss after certain cycles and precharge DRAMs in response to that prediction.
2. Description of the Related Art
Microprocessor-based computer systems have been increasing in performance at a tremendous rate. Much of this increase has been based on the improvements in the microprocessor itself. For example, clock speeds are reaching those previously used only by mainframe computers. However, affordable memory device performance has not been increasing at the same rate. Indeed, dynamic random access memory (DRAM) performance has flattened out recently, with the majority of the effort being concentrated on increasing device storage size. Thus main memory has become a bottleneck.
Cache memory systems, where a small amount of very fast, expensive static random access memory (RAM) is used to store copies of the data, have made the problem somewhat less severe, but the designs are very complicated and expensive. Further, the poor memory performance returns when access must be made to main memory. So there still is a need to improve the performance of the main memory system.
Page mode memory devices provide one way to increase memory system performance. If consecutive accesses are made to the same row address, referred to as the same page, only column addresses need be provided. This allows a dramatic reduction in cycle time for those cases, referred to as page hits. This is a quick gain and relatively easily made by itself, but more performance is always desired.
If a consecutive access is not made to the same row address (a page miss), then both the row address and the column address must be provided to the memory device. This is done consecutively, and obviously takes longer than simply providing a column address. The performance penalty of a page miss, however, is even more severe, as before the row address strobe, or RAS*, signal can be provided, that signal must be taken high for a relatively long fixed amount of time known as the precharge time (the physical line, RAS* is driven high during the precharge period). For example, an 80 nanosecond DRAM will typically require 60 nanoseconds of precharge before the RAS signal can be driven low. Further, once this precharge is begun, it cannot be aborted. Throughout this disclosure, an asterisk (*) at the end of the signal name indicates the physical signal is active low; the logical state of the corresponding logical signal without an asterisk is active high. Therefore, RAS* is the active low physical signal that corresponds to the active high logical signal RAS. Additionally, a signal with the asterisk indicates the inverse of the signal without the asterisk.
Thus, RAS precharge time can significantly degrade the performance of a system on a memory page miss. It would be desirable to lessen the performance penalty associated with RAS precharge time on page misses.
Prior memory controllers address this problem to some extent by keeping the RAS, signal low after a cycle is completed, effectively betting that a page hit will occur next, thus gaining performance by not having to do a full cycle. But if the bet is wrong, even further delay is induced as the miss determination takes some time and that time must then be added to the precharge time to determine effective access time. Generally holding RAS, low provides an improvement, but because of the increased penalty for miss cases, there still is room for improvement, and improvement is always desirable.