It is well known in the art to generate a high voltage from a low voltage to program and erase programmable elements. A high voltage charge pump is utilized to generate a high voltage on-chip while a high voltage switch is connected to the high voltage charge pump and is utilized to apply a positive and negative voltage. The high voltage switch may be utilized to apply the high voltage signal to a memory cell, for example an EEPROM or Flash EEPROM, or another type of destination circuit.
High voltage charge pumps according to the Dickson design known to the art pump charges from node to node from the supply node to the output node. Complementary clock signals may control charging and discharging of capacitors which produce the pumping of the electric charges. The voltage increases from node to node until reaching the final voltage on the output node. Unfortunately, this style of charge pump does not work well with low input voltages and is inefficient.
High voltage switches known to the art are subject to several limitations. First, high voltage switches known to the art are subject to latch-up hazards. Some high voltage switches utilize both NMOS and PMOS elements. As a result, these high voltage switches may be subject to latch-up hazards. Other high voltage switches known to the art may incur a voltage drop due to the threshold of the switching element. This problem may be solved by increasing the input voltage signal and/or adjusting the characteristics of the components, however, the chip may conduct to ground as the chip may not be capable of supporting the higher input voltage.
Consequently, it would be advantageous if a method and system existed for generating and applying a high voltage signal without latch-up hazards and without incurring a voltage drop due to the threshold of the switching element. It would also be advantageous if a method and system existed for switching a high voltage signal while providing a continuous output drive on multiple clock phases.