1. Field of the Invention
The present invention relates to a solid-state imaging device represented by a CMOS image sensor, a method for driving the same, and a camera system.
2. Description of the Related Art
In recent years, CMOS image sensors have captured attention as a solid-state imaging device (image sensor) that replaces CCDs. CCD pixels typically require dedicated processes in manufacture and using a plurality of power source voltages and combining a plurality of peripheral ICs in operation. The various problems, such as a significantly complicated system, associated with a CCD can be overcome by using a CMOS image sensor.
A CMOS image sensor can be manufactured by using processes similar to those used to manufacture a typical CMOS integrated circuit. Further, a CMOS image sensor can be driven by a single power source and mixed with analog and logic circuits manufactured by using CMOS processes into a single chip. A CMOS image sensor therefore has a plurality of significant advantages, such as decrease in the number of peripheral ICs.
An output circuit dominantly used with a CCD is a single-channel (ch) output circuit using an FD amplifier including a floating diffusion (FD) layer. In contrast, a CMOS image sensor inherently includes an FD amplifier on a pixel basis. A dominantly used FD amplifier is a vertical row parallel output amplifier, in which a single horizontal row in a pixel array is selected and the entire horizontal row is read all together in the vertical row direction. It is difficult for an in-pixel FD amplifier to provide a sufficient drive capability and therefore necessary to reduce the data rate. This is a reason why a CMOS image sensor is advantageously operated in a parallel processing scheme.
Not only in CCD and CMOS image sensors but also in any imagers, different multiple color pixels, which is a minimum unit repeated in a color layout, forms a pixel unit, and the color layout of the pixel unit is determined by arranging the set of multiple pixels in a horizontal row-vertical row matrix or a checkered pattern. A minimum unit to which a single color is assigned in the pixel unit is called a sub-pixel, and a set of different color sub-pixels is called a pixel in some cases. In the following description, however, a minimum unit to which a single color is assigned is called a pixel, and a set of different color pixels, which is repeated to form a color layout, is called a pixel unit.
In general, in a vertical row parallel output-type CMOS image sensor, a parallel processed unit in the pixel unit, which is called a column, is a vertical pixel-unit row, and a processing circuit is provided for each vertical row of pixels or column. The processing circuit for each vertical row of pixels or column includes a noise removal circuit using CDS or any other suitable method or, when what is called a column-AD scheme is used, a single-bit ADC (analog-digital converter).
In a vertical row parallel output-type CMOS image sensor, entire pixel signals can be read, as in the other output-type image sensors. Further, thinning-out reading, in which the frame rate is increased by limiting the pixels to be read to reduce the number of data (the number of pixel signals) to be outputted from the pixel unit, can be carried out.
In the thinning-out reading, the amount of information decreases because one out of n (at least two) pixel signals is read and the other pixel signals are discarded. It is therefore a typical practice to sum a plurality of pixel signals before reading. In the following description, a method for simply selecting and reading one of the n pixel signals is referred to as thinning-out reading and a thinning-out method along with summing is referred to as summing and reading.
FIG. 1 is a diagrammatic view showing a pixel unit formed in what is called a Bayer layout with a column processing circuit disposed on a column basis.
In a Bayer layout, red (R) and green (Gr) are alternately arranged in a first-color pixel horizontal row, which is what is called an R horizontal row, and green (Gb) and blue (B) are alternately arranged in a second-color pixel horizontal row, which is what is called a B horizontal row. A pixel unit is formed of red (R), green (Gr), green (Gb), and blue (B) four pixels in two horizontal rows and two vertical rows.
Each of the triangular blocks shown in FIG. 1 is a first-stage processing unit in the corresponding column processing circuit, and corresponds to, for example, a comparator in an ADC that operates in a column-AD scheme. In FIG. 1, the column processing circuits are arranged in the respective columns, that is, one per vertical row of pixel units.
FIGS. 2A and 2B shows exemplary operations in which a first-color pixel horizontal row (R horizontal row) and a second-color pixel horizontal row (B horizontal row) are processed by using different column processing circuits. In FIGS. 2A and 2B, each of the reference characters “17R” denotes a first stage (comparator, for example) of the corresponding column processing circuit for R horizontal rows, and each of the reference characters “17B” denotes a first stage (comparator, for example) of the corresponding column processing circuit for B horizontal rows. In FIGS. 2A and 2B, only the pixels to be summed are labeled with their color codes (R, Gr, Gb, and B).
In a first summing and reading operation shown in FIG. 2A, three green (Gb) pixel signals from a first horizontal row B1 are summed and read to the first stage 17B of the corresponding column processor. Similarly, three red (R) pixel signals from a first horizontal row R1 are summed and read to the first stage 17R of the adjacent column processor.
In the following summing and reading operation shown in FIG. 2B, three blue (B) pixel signals from the first horizontal row B1 are summed and read to the corresponding first stage 17B, and three green (Gr) pixel signals from the first horizontal row R1 are summed and read to the corresponding first stage 17R.
The drive method described above is a known method in which when an R horizontal row is read in a horizontal summing or thinning-out operation, the column located at the summing center in the R horizontal row is used, and when a B horizontal row is read, the column located at the summing center in the B horizontal row is used. In this case, the column used for the R horizontal row differs from the column used for the B horizontal row.