Non-volatile memory devices are currently in widespread use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read-only-memory (ROM), programmable-read-only memory (PROM), erasable-programmable-read-only-memory (EPROM), and electrically-erasable-programmable-read-only-memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash memory devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, flash memory devices enable the erasing of all memory cells in the device using a single current pulse.
During flash memory device fabrication, memory cells are typically formed on a silicon substrate. The memory cells can be, for example, Silicon-Oxide-Nitride-Oxide-Silicon (“SONOS”) memory cells, such as Advanced Micro Devices' (“AMD”) MirrorBit™ memory cell, or floating gate memory cells. After the memory cells have been formed, various dielectric layers, such as an interlayer dielectric (“ILD”) layer, are typically formed over the memory cells. Contact holes can be etched into the ILD and oxide cap layers and filled with metal, such as tungsten, to form contacts over active doped regions in the substrate or in a polysilicon layer. Additional dielectric layers, such as an etch stop layer and a second ILD layer, can be formed over the contacts. During backend processing, such as copper back-end-of-line (“BEOL”) processing, trenches and vias can be formed over the contacts in the second ILD layer and the trenches and vias can be filled with a metal, such as copper. Interconnect metal lines can then be appropriately formed over the metal-filled trenches and vias to provide electrical connections to the active regions.
However, backend processing utilized to form metal-filled trenches and vias, interconnect metal lines, and dielectric layers, typically includes processes such as plasma etching and chemical vapor deposition (“CVD”), which produce ultraviolet (“UV”) radiation. The UV radiation produced during the above back end processes can alter the memory cells and cause UV radiation damage to the flash memory device, which decreases memory cell reliability. The UV radiation can also cause UV radiation-induced charging in dielectric layers in and adjacent to the memory cells, such as gate spacers and Oxide-Nitride-Oxide (“ONO”) stack layers, which can reduce data retention. The UV radiation-induced charging can degrade data retention and can undesirably increase threshold voltage (“Vt”) in the flash memory cell, which decreases memory cell performance. In floating gate flash memory cells, UV radiation-induced charging can be reduced by performing a UV erase step after appropriate back end processes. However, the UV erase steps undesirably increase manufacturing cost. In the case of MirrorBit™ memory cells, adding additional UV erase steps can not reduce charging because its program/erase mechanisms used in devices are different from floating gate memory cells. UV erase steps can only charge up MirrorBit™ memory cells even more, not reduce the UV charging damage or lower Vt.
Thus, there is a need in the art for an effective structure and method to prevent UV radiation produced during backend processing from deleteriously affecting memory cells, such as SONOS or floating gate flash memory cells.