Clock signals can be used to coordinate data transmission between components in an electronic system, for example, between circuits in an integrated circuit (“IC” or “chip”), or between chips on a printed circuit board (PCB). In a synchronous system, components of the system are synchronized to a system-wide clock. The components perform data processing and transmission in cadence with the system-wide clock at a particular time period during the clock cycle of the system-wide clock. For example, the components can be synchronized with the system-wide clock when the clock signal is “high” (e.g., at a supply voltage), or when the clock signal is “low” (e.g., at a reference voltage). As another example, the components can be synchronized with the system-wide clock at a clock “edge,” for example, when the clock signal transitions from low to high (“rising edge”), or from high to low (“falling edge”).
A latch circuit can be used for storing data. For example, a latch can store a single bit (“0” or “1”) or multiple bits. Data can be provided to an input of a latch to be stored in the latch. Data stored in a latch can be read out from an output of the latch. Some latches can selectively operate in an enabled (“transparent”) state or in a disabled (“hold”) state based on the state of a control signal. When the latch is in the transparent state, the latch is ready to receive new data at the input, and the output of the latch is operable to reflect the input of the latch. When in the transparent state, the latch may not be ready for providing (transmitting) data to another circuit as the output of the latch may not be stable (e.g., depending on the state of the input data). When the latch is in the hold state, data previously stored in the latch is stable (e.g., ready for read-out), and can be transmitted to another circuit coupled to the output of the latch. A latch performs “positive latching” if the latch enters the hold state when the enabling signal is high. A latch performs “negative latching” if the latch enters the hold state when the enabling signal is low.