1. Field of the Invention
The present invention relates to a method for controlling memory data access, and more particularly, to an apparatus and related method for adjusting a pulse width to generate a control signal for controlling a switch module on a data transmission path in a memory by detecting a frequency of a specific clock signal in the memory.
2. Description of the Prior Art
In general, when accessing a sum of data, a microprocessor will send an input instruction signal (e.g. a data read instruction signal or a data write instruction signal) to a memory (e.g. a DRAM {Dynamic Random Access Memory}) for informing the memory a data access operation will be performed. It is also necessary for the microprocessor to send an input address signal corresponding to the sum of data to the memory such that the memory can access the sum of data according to the input address signal correctly. Before the sum of data is accessed, a decoder performs a decoding operation upon the input address signal and the input instruction signal simultaneously to output a control signal for controlling a turn-on period of a switch module in the memory so memory data can be accessed through the switch module. For example, data in memory cells within a specific memory bank in the memory can be accessed through the switch module when the switch module is turned on. Additionally, since the input instruction signal or the input address signal is usually inputted into the memory in the form of a voltage signal, the memory needs to use corresponding pins to receive the above-mentioned voltage signals. As mentioned above, the voltage signal has a high voltage level (e.g. five Volts) or a low voltage level (e.g. zero Volts). The memory also needs an operating clock signal (i.e. a memory clock). The operating clock signal is utilized for estimating the voltage level corresponding to the input address signal in order to obtain information of the input address signal for performing a memory data access operation. For example, a voltage level of the voltage signal corresponding to the input address signal can be estimated on a rising edge or a falling edge of the operating clock signal.
In practice, however, because high frequency variations of the above-mentioned voltage signals will become non-ideal while the operating clock signal in the memory operates at a higher frequency, errors may occur when the memory performs instructions for estimating the voltage level of the voltage signal representative of the input address signal. Please refer to FIG. 1. FIG. 1 shows a timing diagram controlling a switch module in a prior art memory for data access. A signal CTRL is utilized for controlling the switch module to be turned on or turned off and also for controlling the turn-on period of the switch module. As shown in FIG. 1, a signal CLK represents the operating clock signal in the memory, and a signal ADDR represents the input address signal. A signal COM represents an input instruction signal (e.g. a data read instruction signal or a data write instruction signal), and a data access operation will be performed when a voltage level of the input instruction signal COM arrives at a high voltage level. For example, when the operating clock signal CLK in the memory remains in an ideal frequency range (i.e. it is assumed that, in this frequency range, high frequency variations of the input address signal ADDR are still ideal), it is only necessary for a pulse width PW2 of the input instruction signal COM to be shorter than a pulse width PW1 of the input address signal ADDR. A setup time taken by a rising edge of the input address signal ADDR and a hold time taken by a falling edge of the input address signal ADDR are not considered. Otherwise, when the operating clock signal CLK in the memory arrives at a higher frequency (i.e. it is assumed that, at this frequency, high frequency variations of the input address signal ADDR are not ideal), in order for there to be no errors, the setup time taken by the rising edge of the input address signal ADDR and the hold time taken by the falling edge of the input address signal ADDR have to be considered for preventing the decoder from accessing other addresses. Therefore, it is necessary for the pulse width PW2 of the input instruction signal COM to not only be smaller than the pulse width PW1 of the input address signal ADDR, but also a fixed pulse width is needed to be reserved for the setup/hold time taken by the rising/falling edge of the input address signal ADDR. For example, in FIG. 1, the pulse width PW2 is much shorter than the pulse width PW1. Since the pulse width PW3 of the control signal CTRL is determined by the pulse width PW2 of the input instruction signal COM, however, this method of reserving a fixed pulse width will result in a shorter turn-on period of the switch module when using the control signal CTRL outputted from the decoder to control the switch module. The shorter turn-on period of the switch module will cause a shorter data access time. This shorter data access time will become more serious if the reserved pulse width is longer.