Chemical-mechanical polishing ("CMP") processes are widely used to remove material from the surface of semiconductor wafers, and they are particularly useful for planarizing wafers, and layers thereof, in the production of ultra-high density integrated circuits. In a typical CMP process, a wafer is pressed against a polishing pad in the presence of a slurry under controlled chemical, pressure, velocity, and temperature conditions. The slurry generally contains small, abrasive particles that abrade the surface of the wafer, and chemicals that etch and/or oxidize the newly formed surface of the wafer. The polishing pad is generally a planar pad made from a continuous phase matrix material such as polyurethane. Thus, when the pad and/or the wafer moves with respect to the other, material is removed from the surface of the wafer mechanically by the abrasive particles and chemically by the etchants and/or oxidants in the slurry.
FIG. 1 schematically illustrates a polishing machine 10, often called a planarizer, used in a conventional CMP process. The polishing machine 10 has a platen 20, a wafer carrier 30, a polishing pad 40, and a slurry 44 on the polishing pad. An under-pad 25 is typically attached to the upper surface 22 of platen 20, and the polishing pad 40 is positioned on the under-pad 25. In conventional CMP machines, a drive assembly 26 rotates the platen 20 as indicated by arrow A. In other existing CMP machines, the drive assembly 26 reciprocates the platen 20 back and forth as indicated by arrow B. The motion of the platen 20 is imparted to the pad 40 through the under-pad 25 because the polishing pad 40 frictionally engages the under-pad 25. The wafer carrier 30 has a lower surface 32 to which a wafer 12 may be attached, or the wafer 12 may be attached to a resilient pad 34 positioned between the wafer 12 and the lower surface 32. The wafer carrier 30 may be a weighted, free-floating wafer carrier, or an actuator assembly 36 may be attached to the wafer carrier 30 to impart axial and rotational motion, as indicated by arrows C and D, respectively.
In the operation of the conventional polishing machine 10, the wafer 12 is positioned face-downward against the polishing pad 40, and then the platen 20 and the wafer carrier 30 move relative to one another. As the face of the wafer 12 moves across the planarizing surface 42 of the polishing pad 40, the polishing pad 40 and the slurry 44 remove material from the wafer 12.
CMP processes must consistently and accurately produce a uniform, planar surface on the wafer because such a surface is needed in order to accurately focus optical or electromagnetic circuit patterns on the surface of the wafer. As the density of integrated circuits increases, it is often necessary to accurately focus the critical dimensions of the circuit-pattern to achieve a resolution of approximately 0.35-0.5 .mu.m. Focusing the circuit-patterns to such small tolerances, however, is very difficult when the distance between the emission source and the surface of the wafer varies because the surface of the wafer is not uniformly planar. In fact, several devices may be defective on a wafer having a non-uniform planar surface. Thus, CMP processes must create a highly uniform, planar surface.
In the competitive semiconductor industry, it is also desirable to maximize the throughput of finished wafers. The throughput of wafers in a CMP process is a function of several factors, one of which is the rate at which the thickness of the wafer decreases as it is being planarized (the "polishing rate"). Because the polishing period per wafer (the time needed to achieve a desired wafer planarity and end-point) generally decreases with increasing polishing rate, it is desirable to maximize the polishing rate within controlled limits to increase the number of finished wafers that are produced in a given period of time.
The polishing rate of a wafer is often retarded by surface groups which form when freshly exposed surface comes into contact with the CMP slurry. The CMP processing of silicon oxide illustrates this problem. During CMP of a silicon oxide wafer, there is a continuous formation of surface Si--OH groups. These Si--OH groups can be very difficult to dislodge from the underlying bulk silicon oxide, and thus their presence retards the polishing rate of the CMP process. To increase the polishing rate of a silicon oxide wafer, conventional CMP processes use aggressive mechanical polishing techniques (e.g., high down-forces and high pad velocities) to physically remove the Si--OH groups and some of the underlying silicon oxide from the wafer.
Aggressive mechanical polishing techniques, however, tend to reduce the uniformity of the polished surface on the wafer. A high pad velocity, for example, exacerbates the center-to-edge gradient in the polishing rate so that the polishing rate at the edge of the wafer is greater than that at the center of the wafer. Similarly, high down-forces worsen dishing over large area features formed on the wafer and reduce the ability to control the planarization process. Therefore, in order to produce a desirably uniform planar surface on a wafer, the polishing rate is limited to a relatively low rate that is not overly aggressive.
Accordingly, there is a strongly-felt need in the art for improved chemical-mechanical polishing slurries that afford an increased polishing rate for semiconductor wafers and layers present thereon. The present invention fulfills this need, and provides other related advantages.