The present invention relates to buffer circuits. More particularly, the present invention relates to buffer circuits that are capable of receiving and producing reduced voltage signals.
Buffer circuits are typically employed in integrated circuits (ICs). In conventional buffer circuits, the upper power rail is at VDD and the lower power rail at ground. VDD is the voltage level at which the majority of the logic in the IC operate. The input and output signals of the buffer circuit swing between 0V (for a logic 0) and VDD (for a logic 1).
The power consumption of the IC is related to the value of VDD. Power consumption, in some instances, is a concern for IC designers. For example, it is desirable to design ICs which consume less power for portable applications, thereby enabling longer operation without recharging. Thus, it is desirable to provide a buffer circuit which decreases power consumption.
The invention relates to a buffer circuit that receives and generates signals having a reduced voltage range from VSS to VRED. In accordance with the invention, VRED comprises a voltage level less than VDD, where VDD is the voltage used to operate a majority of the logic in the integrated circuit, VDD is about 3.3 volts or less. In one embodiment, the buffer circuit comprises input and output stages. The output stage comprises pull-up and pull-down transistors coupled in series between VRED and VSS. The output node is coupled between common terminals of the pull-up and pull-down transistors. The pull-up and pull-down transistors operate in a push-pull configuration. When the pull-up transistor is switched on and the pull-down transistor is switched off, the output stage generates a logic 1 output signal equal to about VRED. On the other hand, when the pull-up transistor is switched off and the pull-down transistor is switched on, the output stage generates a logic 0 output signal equal to about VSS.