The present invention relates generally to integrated circuits, and more specifically to the storage of nonvolatile data in integrated circuits.
Many battery-powered portable electronic devices, such as laptop computers, Portable Digital Assistants, digital cameras, cell phones and the like, require memory devices that provide large storage capacity and low power consumption. One type of memory device that is well-suited to use in such portable devices is flash memory, which is a type of semiconductor memory that provides relatively large and nonvolatile storage of data. The nonvolatile nature of the storage means that the flash memory does not require power to maintain the data, as will be appreciated by those skilled in the art.
A typical flash memory includes a memory-cell array having a large number of memory cells arranged in rows and columns and grouped into blocks. FIG. 1A illustrates a simplified cross-sectional view of a conventional flash memory cell 100. The flash memory cell 100 is formed by a field-effect transistor 101 including an N+ source region 102 and an N+ drain region 104 formed in an isolated p-well 106 in a semiconductor substrate (not shown). A P+ region 107 is formed in the p-well 106 and is coupled to a p-well drive PWDRV that receives a voltage to bias the p-well at a required level during various modes of operation of the memory-cell 100, as will be discussed in more detail below. A channel region 108 is defined in the p-well 106 between the source region 102 and drain region 104. In the memory-cell array containing the flash memory cell 100, the source region 102 is coupled to an array source AS, with all memory cells 100 in a given block in the flash memory being coupled to the same array source. The drain region 104 of each memory cell 100 is coupled to a bit line BL of the memory-cell array.
The memory cell 100 further includes a floating gate 110 formed on an oxide layer 112 over the channel region 108, with the floating gate being capable of holding a charge from electrons that are transferred either to or from the channel region 108 through the oxide layer 112. A control gate 114 is formed over the floating gate 110 with a dielectric layer 116 being disposed between the two gates to isolate the control gate from the floating gate. The control gate 114 of each memory cell 100 is coupled to a word line WL of the memory-cell array.
In operation, during a programming mode charge is stored on the floating gate 110 and during an erase mode charge is removed from the floating gate. The presence or absence of charge on the floating gate 110 determines a threshold voltage VT of the field effect transistor 101 so that when the word line WL is activated (i.e., applies active voltage to the control gate) the transistor either turns ON or stays OFF depending on whether charge is or isn""t stored on the floating gate, as will be discussed in more detail below. In this way, the memory cell 100 stores a first logic state when the floating gate 110 stores charge and a second logic state when the floating gate does not store charge.
FIG. 1B illustrates the operation of the memory cell 100 of FIG. 1A during a write mode. To write data to the memory cell 100, which means to store a charge on the floating gate 110 and, in turn, store the corresponding logic state in the memory cell, a positive programming voltage VPP is applied through the word line WL to the control gate 114. This positive programming voltage VPP on the control gate 114 attracts electrons 120 from the p-well 106 and causes them to accumulate toward the surface of the channel region 108. During a write, a drain voltage VD is applied through the bit line BL to the drain 104, and the array source AS and p-well drive PWDRV are coupled to ground to thereby couple the source 102 and p-well 106 to ground, respectively. The value of VD depends upon the process technology, and is typically 3 to 5 volts. As the drain-to-source voltage increases, electrons 120 begin to flow through the channel 108 from source 102 to drain 104, and in the process some electrons acquire a large kinetic energy. The voltage difference between control gate 114 and the drain 104 creates an electric field through the oxide layer 116, and this electric field attracts the electrons 120. Some of the electrons 120 having enough kinetic energy to overcome the barrier presented by the oxide 112. These electrons 120 are attracted to and accumulate on the floating gate 110, which charges the floating gate. The write operation continues for a required time, and the programming voltages VPP, VD and ground applied to the word line WL, drain 104, and source 102, respectively, are thereafter removed.
The charged floating gate 110 raises the threshold voltage VT of the field effect transistor 101 above the active voltage applied on the word line WL during subsequent read operations. As a result, when the word line WL goes active during a read, the memory cell 100 does not turn ON and sense amplifiers (not shown) coupled to the bit line BL sense and amplify the current through the memory cell 100 and drive an output signal to a first logic state. Thus, in this situation, the sense amplifiers drive the output signal to the first logic state stored by the memory cell 100 that was previously written to or programmed. Note that during a write operation, a particular memory cell 100 in the memory-cell array is programmed to the first logic state, in contrast to an erase operation in which the data stored in a block of memory cells in the array are erased or programmed to a second logic state that is the complement of the first logic state, as will now be discussed in more detail.
FIG. 1C illustrates the operation of the memory cell 100 of FIG. 1B during an erase mode. During the erase mode, the memory cell 100 is erased by discharging the floating gate 110. To erase the memory cell 100, the voltage VPP, which is developed on a high voltage bus HVBUS in the flash memory containing the memory cell 100, is applied through the array source AS and p-well drive PWDRV to the source 102 and p-well 106, respectively. A negative programming voltage xe2x88x92VPP is applied through the word line WL to the control gate 114, and the drain 104 is floated or electrically isolated. In response to these applied voltages, electrons 120 stored on the floating gate 110 are attracted to the source 102 through the oxide layer 116 until the floating gate is discharged. The discharged floating gate 110 results in the threshold voltage VT of the transistor 101 being returned to a value below the active voltage applied on the word line WL during subsequent read operations. As a result, when the word line WL goes active during a read, the memory cell 100 turns ON and sense amplifiers (not shown) coupled to the bit line BL sense and amplify the current through the memory cell 100 and drive the output signal to the second logic state. Thus, in this situation, the sense amplifiers drive the output signal to the second logic state stored by the memory cell 100 that was previously erased and not thereafter written to or programmed. As previously mentioned, during the erase mode, all memory cells in a given block are erased and thus store the second logic state. The array sources AS of all memory cells 100 in a given block are coupled together. As will be understood by those skilled in the art, the HVBUS bus is a bus in the flash memory on which required voltages, including the voltage VPP, are developed, and when the voltage on the bus is to be applied to a component in the flash memory the component is simply coupled to the bus.
After erasing the memory cell 100 but prior to reading data from the memory cell, the voltages on the word line WL, array source AS, and p-well drive PWDRV must be discharged to approximately zero volts. Ideally, these voltages are discharged quickly so that a write or read operation may be performed as soon as possible after a block of memory cells 100 is erased. In a conventional flash memory, however, the physical structure of the memory-cell array and the memory cells 100 results in capacitive coupling between the word line WL and the p-well 106 and between the word line and the array source AS as represented by the capacitors CWP and CWA, respectively, in FIG. 1C. As a result of this capacitive coupling, the discharge of the negative voltage xe2x88x92VPP on the word line WL affects the rate at which the voltages VPP on the array source AS and p-well drive PWDRV discharge. The converse is also true, namely the discharge of the positive voltages VPP on the arrays source AS and p-well drive PWDRV affect the rate at which the word line WL discharges.
FIG. 2 illustrates a conventional discharge cycle and the affect of the capacitive coupling between the word line WL and the array source AS and p-well drive PWDRV. At a time T0, discharge circuitry (not shown in FIG. 1) in the flash memory begins discharging the voltage VPP on the HVBUS which, in turn, starts discharging the array source AS and drive PWDRV. At the same time, the discharge circuitry begins discharging the voltage xe2x88x92VPP on the word line WL. As a result of the capacitive couplings CWP and CWA, the discharge of word line WL towards ground causes the voltages on the array source AS and p-well drive PWDRV to increase above the voltage VPP, as indicated in FIG. 2 just after the time T0. Similarly, the capacitive couplings CWP and CWA result in the discharge of the array source AS and drive PWDRV towards ground causing the voltage on the word line WL to increase below the voltage xe2x88x92VPP, as also indicated in FIG. 2 just after the time T0. The voltage on the word line WL going more negative than xe2x88x92VPP and the voltages on the array source and drive PWDRV becoming more positive than VPP results in the discharge of these voltages taking a longer time since the increased magnitudes take longer to discharge to ground.
As illustrated in FIG. 2, the array source AS and p-well drive PWDRV are initially discharged not to ground but to a verify voltage VHC, which is typically approximately 5 volts. As will be appreciated by those skilled in the art, the HVBUS is discharged to VHC so that the voltage VHC on the bus may be used during a subsequent verify operation to apply VHC on the word lines WL and access the memory cells 100 to verify each memory cell in the corresponding block was properly erased. At a time T1, the array source AS and p-well drive PWDRV are disconnected from the HVBUS bus and coupled to ground, resulting in the voltages on the array source and p-well drive discharging rapidly to ground as illustrated. This rapid discharge of the voltages on the array source AS and p-well drive PWDRV is once again coupled to the word line WL due to the capacitive couplings CWA and CWP. As seen in FIG. 2 at just after the time T2, the voltage on the word line WL dips negative to an even greater extent than before due to the rapid rate of the discharge of the array source AS and p-well drive PWDRV. Once again, this capacitive coupling results in the discharge of the word line WL taking longer since the increased magnitude takes longer to discharge to ground.
The capacitive couplings CWA and CWP can result in a total discharge time TD, which is the time to discharge the word line WL, array source AS, and p-well drive PWDRV to ground, being undesirably long. A longer discharge time TD slows the overall operation of the flash memory since after a block of memory cells 100 is erased, data cannot be read from or written to cells in the block until after the time TD. Furthermore, the capacitive coupling can also have other undesirable affects on components in the flash memory. For example, if coupling results in magnitude of the voltages on the word line WL, array source AS, or p-well drive PWDRV becoming too great, junctions in the memory-cell array could become forward biased or break down, possibly damaging or stressing such junctions and possibly leading to reliability problems or xe2x80x9clatchupxe2x80x9d of the flash memory, as will be appreciated by those skilled in the art. A specific example is the PN junction formed by the p-well 106 and source 102. If this PN junction was to become forward biased, which could occur when the capacitive coupling CWP between the word line WL and the p-well 106 is stronger than the coupling CWA between the word line and the array source AS, then latchup could occur.
There is a need in flash memories for a circuit and method for reducing the coupling between the negative voltage on the word line and the positive voltages on the array source and p-well drive to reduce the time required to discharge the word line, array source, and p-well drive after erasing a block of memory cells, and to prevent stressing or damaging components in the flash memory during a discharge cycle.
According to one aspect of the present invention, an voltage discharge circuit is adapted to be coupled to a first node and a second node and is adapted to receive first and second discharge signals. The voltage discharge circuit operates in a first mode in response to the first discharge signal to couple the first node to the second node and to discharge voltages on the first and second nodes at a first rate. The voltage discharge circuit operates in a second mode in response to the second discharge signal to couple the first node to the second node to discharge the voltages on the first and second nodes at a second rate. The voltage discharge circuit may be an erase discharge circuit in a flash memory wherein the first and second nodes correspond to an array source and a p-well drive, respectively.
According to another aspect of the present invention, a method of discharging first and second voltages on first and second nodes, respectively, includes coupling the first node to the second node, discharging the voltages on the first and second nodes at a first rate, and discharging the first and second voltages at a second rate.