1. Field of the Invention
The present invention relates to a method and apparatus for forming a silicon oxide film on a target substrate, such as a silicon wafer.
2. Description of the Related Art
In manufacturing semiconductor devices for constituting semiconductor integrated circuits, a target substrate, such as a semiconductor wafer, is subjected to various processes, such as film formation, oxidation, diffusion, reformation, annealing, and etching. Films of various kinds used in semiconductor devices need to be made thinner, as semiconductor devices have become smaller and more highly integrated. Accordingly, a silicon oxide film (typically an SiO2 film) commonly used as an insulating film needs to be made thinner, where the film is formed as a filler or gate insulating film by a film-formation process.
A silicon oxide film may be formed to fill a recess having a high aspect ratio, such as a trench, formed in the surface of a wafer. Where a silicon oxide film used as a filler of this kind is formed, a film-formation method with good step coverage is employed to fully fill the recess. One example of this is a CVD (Chemical Vapor Deposition) process of forming a silicon oxide film, using an Si-containing organic material, such as TOES (Tetra Ethyl Ortho Silicate). Jpn. Pat. Appln. KOKAI Publication No. 2001-77105 discloses a CVD process of this kind.
FIGS. 8A to 8C are sectional views showing sequential steps of a conventional CVD process using TOES. As shown in FIG. 8A, recesses 2 and projections 4 are alternately formed at the surface of a target substrate or silicon wafer (semiconductor wafer) W. For example, each recess 2 is a trench for device isolation, while each projection 4 is a device region for forming therein a device, such as a transistor or capacitor. This semiconductor wafer W is subjected to a CVD process using TOES to deposit a silicon oxide film 6 on the entire substrate surface, as shown in FIG. 8B. As shown in FIG. 8C, the silicon oxide film 6 formed by the CVD process entirely fills the recesses 2 and entirely covers the projections 4.
The surface of the silicon oxide film 6 deposited by the CVD process becomes slightly wavy due to reflection of the shape of the recesses 2. A planarizing process, such as CMP (Chemical Mechanical Polishing), is performed, to remove the wavy portions and planarize the surface of the silicon oxide film 6. Then, contact holes are formed in the silicon oxide film 6 to make electrical contacts to the underlying layer. After the contact holes are formed, an etching process (cleaning process) is performed, using an etching solution, such as hydrogen fluoride solution. This is to clean the bottom of the contact holes or the like, to reduce the contact resistance. Then, metal wiring layers are respectively disposed within the contact holes.