In the production process of integrated circuits devices are tested to estimate the device yields and possible yield-detracting processing problems. Since the production of integrated circuits comprises many processing steps and different technologies, the technological sources of electrical failure such as short circuits within the integrated circuits or open contacts are investigated using test structures in order to estimate a suitable process window and to improve the device quality as well as the processing yield.
It is therefore desirable to detect, quantify and avoid yield detracting factors in integrated circuits. To achieve this quantification and detect corrupt device structures, test devices, hereinafter also called devices under test or, in short DUTs, are fabricated. Such test devices may comprise, for instance, contact or via chains, polycrystalline semiconductor lines or metal lines, and/or poly crystalline semiconductor combs or metal combs.
In known prior-art solutions each device under test has its respective test contact pads, and each device has to be tested sequentially by placing probe contact needles on the respective contact pads. This mechanical movement is very time-consuming, and due to the large number of test contact pads a correspondingly large area of the substrate is consumed. Additionally, the testing equipment needed for this testing operation needs complex control circuitry to enable a precise movement of the probe contact needles from one pair of test contact pads to the next. It is therefore desirable to reduce the number of test contact pads.
US2006/0022695 discloses arranging several devices under test in a matrix. Individual devices are addressed by selecting the row and the column of the device. Thus less connection pads have to be used. However, a switching step is required to address the specific device under test. Testing still involves sequentially probing all DUTs of the test structure.
U.S. Pat. No. 6,392,251 discloses a test structure for identifying defect vias, which form open contacts in a network of vias. Via pairs are respectively connected in parallel to two common test contact pads through respective series test resistors that have known electrical resistances and known locations. Defect vias forming open contacts can be identified with a single resistance measurement between the two test contact pads, because the respective serial test resistor adjacent to each via has a known electrical test resistance. However, identifying an open of a via as in U.S. Pat. No. 6,392,251 requires a repetitive “trial-and-error” calculation of different test resistor combinations and a subsequent comparison with the measured total electrical resistance.
It would be desirable to test other DUTs than vias with a single measurement. It is also desirable to detect other defect states than undesired contact openings. Since other critical processing steps than the formation of the vias have to be undertaken during the production of an electrical device, it is desirable to obtain a view on achieved device quality, which is for instance indicated by a number of defect devices comprised in a test structure. It is also desirable to be able to investigate a process window, which may include determining the limitation of the technologically achievable accuracy.