A common flash memory device is a device making the most use of electrically programmable and erasable characteristics of an electrically erasable programmable read-only memory (EEPROM). This flash memory device utilizes a structure having a tunnel oxide layer of a thin layer on a silicon substrate, a floating gate stacked on the tunnel oxide layer, an insulation layer stacked on the floating gate, a control gate stacked above the floating gate on the insulation layer, and source and drain regions in a substrate at sides of the floating gate. One transistor is used to indicate a state of a stored 1 bit and performs a programming or erasing operation electrically.
The flash memory device typically includes a source connection layer for connecting a source of each unit cell in order to form a source line. The source connection layer may be formed through a metal contact method for forming a contact on a source of each unit for connection. However, the metal contact method tends to be inappropriate for a highly integrated device because its contact margin must be considered. Accordingly, a common source line of an impurity diffusion layer formed through a Self Aligned Source (SAS) process is typically applied to realize the highly integrated device.
The flash memory device uses a first metal layer to form a bit line. The first metal layer connects drains of each unit cell through the metal contact method.
However, according to this metal contact method, the first metal layer is used only for selecting a memory cell.