The present invention relates to electronic devices and a heterojunction FET (Field Effect Transistor) suitable particularly for a GaN heterojunction FET.
Conventionally, as an electronic device, there has been a GaN heterojunction FET shown in FIG. 11 (refer to, for example, a first reference: Zhang, n.-Q. and five others, “High Breakdown GaN HEMT with Overlapping Gate Structure”, IEEE, Electron Device Letters, Vol. 21, p. 373-375 and p. 421-423 September 2000). FIG. 11 shows a sectional view of the GaN heterojunction FET. As shown in FIG. 11, the GaN heterojunction FET is formed by successively forming a GaN layer 1102 that is made of undoped GaN and has a thickness of about 3 μm and an Al0.5Ga0.5N layer 1103 that is made of undoped Al0.5Ga0.5N and has a thickness of 20 nm on a sapphire substrate 1101 and successively forming a source ohmic electrode 1105 made of Ti/Al/Ni/Au, a gate Schottky electrode 1106 made of Ni/Au and a drain ohmic electrode 1107 made of Ti/Al/Ni/Au on the Al0.5Ga0.5N layer 1103. A 2DEG (Two-Dimensional Electron Gas) 1104 is generated in a region at a boundary between the GaN layer 1102 and the Al0.5Ga0.5N layer 1103. The 2DEG has a concentration of 8×1012 cm−2. Moreover, an isolation mesa 1112 for element isolation is formed.
In the conventional GaN heterojunction FET, when an electric field located between the gate Schottky electrode 1106 and the drain ohmic electrode 1107 exceeds the breakdown electric field of the semiconductor, the dielectric breakdown of the device occurs. When the semiconductor is GaN, the breakdown electric field Emax is about 5 MV/cm. In this case, given that an interval between the drain ohmic electrode 1107 and the gate Schottky electrode 1106 is Ldg and a drain-gate voltage is Vdg, then an average electric field is expressed as Vdg/Ldg. However, the electric field distribution is generally nonuniform, and the electric field is maximized in the vicinity of the gate Schottky electrode 1106. Since the maximum electric field is normally higher than the average electric field, the normal device has a withstand voltage lower than (Ldg·Emax).
The device structure of the GaN heterojunction FET shown in FIG. 12 is the same as the structure of the conventional GaN heterojunction FET shown in FIG. 11. FIG. 12 shows electrical potentials together with the device structure. The electrical potentials are calculated by simulation. A problem that the present invention intends to solve will now be described in detail below referring to the sectional view of the heterojunction FET shown in FIG. 12.
A 3-μm thick GaN layer 1202 made of undoped GaN and a 20-nm thick Al0.5Ga0.5N layer 1203 made of undoped Al0.5Ga0.5N are formed on a sapphire substrate 1201, and a source ohmic electrode 1205, a gate Schottky electrode 1206 and a drain ohmic electrode 1207 are formed on the Al0.5Ga0.5N layer 1203. A 2DEG 1204 is generated in a region at a boundary between the GaN layer 1202 and the Al0.5Ga0.5N layer 1203. The 2DEG has a concentration of 8×1012 cm−2 in this case. In this case, the interval Ldg between the drain ohmic electrode 1207 and the gate Schottky electrode 1206 is 3 μm, a drain-source voltage Vds is 400 V, and a gate-source voltage Vgs is −10 V. In the case of the bias conditions, the device is in the off state (state in which the channel is depleted and no current flows).
Each portion where the electrical potential interval is narrow in FIG. 12 indicates that the electric field is high. As is apparent from FIG. 12, it can be understood that the electric field is raised in the neighborhood of the gate Schottky electrode 1206. It can be understood that the maximum electric field reaches up to 9.48 MV/cm on the bias conditions, which largely exceeds the breakdown electric field Emax (about 5 MV/cm) according to the simulation results. If voltages of the same bias conditions are applied to the actual GaN heterojunction FET, dielectric breakdown occurs.
The degree of concentration of the electrical potential in a region near the gate electrode depends on the concentration of fixed charge concentration located in the vicinity of the channel of the device. In a practical GaN heterojunction FET, the fixed charge concentration can be controlled to some extent by the composition or impurity doping of the AlGaN layer. The 2DEG concentration Ns is high and the on-state resistance is low when the device is in the on state in the case where the fixed charge concentration is high. Therefore, the degree of electric field concentration in the off state is high, and the withstand voltage becomes low. However, it is desirable that the on-state resistance is low and the off-state withstand voltage is high.
The gate electrode and the drain electrode of the GaN heterojunction FET are located on the identical surface of the semiconductor layer, and a voltage applied across the gate electrode and the drain electrode is high. The field plate structure is not effective for the GaN heterojunction FET unlike the FET of GaAs or Si. When a field plate is used for such a GaN heterojunction FET, there is a problem that the dielectric breakdown occurs in the insulator since the electric field of the insulator on the lower side of the field plate is high although the maximum electric field of the semiconductor layer is low (The breakdown electric field of a normal insulator is higher than that of the breakdown electric field of GaAs or Si but on the same level as that of GaN.).