1. Field of the Invention
The present invention relates to an integrated circuit and a resonance circuit.
2. Description of the Related Art
Following rapid development of mobile communication, radio waves of an extremely wide range of frequencies are required in recent years, and the frequencies of the radio waves employed for mobile communication are now shifting to the microwave band. Therefore, an amplifier employed for a portable terminal is formed by a monolithic microwave integrated circuit (MMIC) or a modularized microwave integrated circuit (MIC).
An amplifier for amplifying a signal of a desired frequency employs a bias circuit f or applying a prescribed dc bias to the gate or the drain of a field-effect transistor (FET) The amplifier is further provided with a feedback circuit for preventing the FET from oscillating in a low-frequency domain and improving the stability of the amplifier.
FIG. 23 is a circuit diagram showing an exemplary conventional bias circuit which is provided on an amplifier formed by an FET 200.
The bias circuit shown in FIG. 23 comprises a parallel resonance circuit 300 formed by an inductor L1 and a capacitor C1, which are connected in parallel with each other. This parallel resonance circuit 300 can apply a dc drain bias Vd to the drain of the FET 200 from a bias supply by adjusting the inductance value of the inductor L1 and the capacitance value of the capacitor C1, without passing a signal of a desired frequency.
When the amplifier is employed in the 1.5 GHz band, for example, the parallel resonance circuit 300 can apply the drain bias Vd to the drain of the FET 200 with no signal loss at the frequency of 1.5 GHz by setting the inductance value of the inductor L1 and the capacitance value of the capacitor Cl at 0.4 nH and 28 pF respectively.
FIG. 24 is a circuit diagram showing another exemplary bias circuit provided on an amplifier which is formed by an FET 200.
The bias circuit shown in FIG. 24 is formed by amicrostrip line MSL. This microstrip line MSL can apply a dc drain bias Vd to the drain of the FET 200 by setting its length at 1/4 the wavelength corresponding to a desired frequency, without passing a signal of the frequency.
FIG. 25 is a circuit diagram showing an exemplary conventional feedback circuit provided on an amplifier which is formed by an FET 200.
The feedback circuit shown in FIG. 25 is formed by a capacitor C2 and a resistor R1, which are serially connected between the drain and the gate of the FET 200. This feedback circuit feeds back a part of a high-frequency signal appearing on the drain of the FET 200 to the gate in a negative phase. Thus, the feedback circuit suppresses the gain mainly at a low frequency and prevents the FET 200 from oscillation. The capacitor C2 is so provided as to feed back no dc component to the gate of the FET 200.
The bias circuit shown in FIG. 23 formed by the parallel resonance circuit 300 requires at least two types of elements, i.e., the inductor L1 and the capacitor C1. When the amplifier is designed, therefore, a space for mounting the inductor L1 and the capacitor C1 must be provided on a substrate.
Particularly in case of an MMIC operating in a high-frequency region, a spiral inductor having a large occupied area is employed as the inductor L1. Therefore, the area of the parallel resonance circuit formed on a dielectric substrate is extremely increased.
On the other hand, a modularized MIC requires external parts called a chip capacitor and a chip inductor as the capacitor C1 and the inductor L1 respectively. In this case, it is necessary to consider a method of adjacently mounting the chip capacitor and the chip inductor in the vicinity of each other. Thus, the bias circuit occupies an extremely large area on a substrate, and exerts bad influence on the characteristics of the modularized MIC. Further, the chip inductor is considerably high-priced as compared with the chip capacitor.
In addition, a wire having a finite length is present for connecting the drain of the FET 200 with the bias supply. This wire is formed by a microstrip line on a dielectric substrate. Thus, the calculative resonance frequency of the parallel resonance circuit 300 deviates from the actual one due to the presence of the microstrip line. Therefore, the parallel resonance circuit 300 must be designed in consideration of the microstrip line.
In the bias circuit formed by the microstrip line MSL shown in FIG. 24, the length of the microstrip line MSL is disadvantageously increased. Assuming that a dielectric substrate has a thickness of 0.8 mm and a dielectric constant of 9 in case of employing the bias circuit at a frequency of 1.5 GHz, for example, the length equal to 1/4 the wavelength is about 20 mm.
The feedback circuit shown in FIG. 25 formed by the resistor R1 and the capacitor C2 requires at least two types of elements. If the resistance value of the resistor R1 is reduced in order to improve stability in this feedback circuit, the feedback amount is increased to disadvantageously reduce the gain. If the resistance value of the resistor Ri is increased, on the other hand, the feedback effect is reduced and the stability cannot be improved.
To this end, the feedback circuit may be provided with a parallel resonance circuit formed by an inductor and a capacitor, to be capable of feeding back only a signal of a frequency other than the desired frequency. Thus, reduction of the gain can be suppressed with respect to the signal of the desired frequency while reducing the resistance value of the resistor R1.
However, such provision of the parallel resonance circuit formed by the inductor and the capacitor results in a problem absolutely similar to that in the bias circuit shown in FIG. 23, and allows no miniaturization. Further, a wire having a finite length is necessarily present, in order to connect the drain and the gate of the FET 200. This wire is formed by a microstrip line on a dielectric substrate as hereinabove described, and hence the calculative resonance frequency of the parallel resonance circuit disadvantageously deviates from the actual one.