According to an increase in memory capacity of a semiconductor memory device, it becomes indispensable to use an on-chip error recovery circuit which recovers or relieves error of defective memory cells. Typical error recovery circuits include a redundancy cell type error recovery circuit and an ECC type (or an ECC cell type) error recovery circuit.
The semiconductor memory device with a redundancy cell type error recovery circuit has normal memory cells and spare or redundant memory cells. When an address sent to a memory device is for a line, that is, a digit line or a word line, on which faulty cell or cells reside, the address decoder for the redundant line activates the redundant line in place of the line on which the faulty cell or cells reside. Thereby, the faulty cell or cells can be replaced by the spare memory cell or cells by the digit line or the word line, and data for the faulty cell or cells can be written into or read from the spare memory cell or cells. The redundancy cell type error recovery circuit is often used in a random access memory (RAM) type semiconductor memory device in which cell data can be written into the memory device after manufacturing the semiconductor memory device.
On the other hand, the semiconductor memory device with the ECC type error recovery circuit has normal memory cells for storing data bits and parity cells or ECC cells for storing check bits. In the ECC type error recovery circuit, check data stored in the ECC cells is previously adjusted by the ECC operation or ECC logic such that the result of exclusive OR operation (EOR), that is, ECC operation, of output data from the normal cells and output data from the ECC cells always becomes a previously determined value. For example, the previously determined value may be “1” in case of odd parity system or “0” in case of even parity system. The number of bits of the ECC cells is selected depending on the required error check and correction performance. When data is read out from the memory device, the ECC logic performs ECC operation to check the result of ECC operation. If the result of ECC operation becomes a value other than the previously determined value, the ECC logic corrects the faulty data and the ECC word as corrected is outputted, for example, to a processor. The ECC type error recovery circuit is often used in a read only memory (ROM) type semiconductor memory device in which cell data is written into the memory device when manufacturing the semiconductor memory device.
In this way, among these error recovery circuits, the redundancy cell type error recovery circuit is often used in a RAM device, and the ECC type error recovery circuit is often used in a ROM device. This is because, when the ECC type error recovery circuit is used in a RAM device, a circuit scale of the RAM device becomes very large. In the RAM device, the content of data written and stored in the normal cells may vary depending on the situation the RAM device is used. Therefore, it is necessary to use an operation circuit which changes the content of the ECC cells depending on the content of data in the normal cells.
On the other hand, when the redundancy cell type error recovery circuit is used in a ROM device, the chip size of the ROM device becomes large. In the ROM device, cell data is written into the ROM device during a manufacturing stage of the chip thereof. Therefore, in order for a memory manufacturer to ship memory devices in which all the defective cells are replaced by the redundancy cells, the redundancy cells for replacing the normal cells should have at least the same capacity as that of the normal cells. Therefore, the chip size becomes large.
In the conventional memory device which uses the ECC type error recovery circuit, there is a disadvantage as follows. That is, the conventional memory device having an ECC type error recovery circuit has a structure in which ECC cells are disposed at far end of word lines from an X decoder. In such conventional memory device, it is impossible to correctly measure from outside the worst value of reading out speed of cell data.
The reasons for this are as follows. First, with respect to memory devices such as ROM devices and the like which use the ECC type error recovery circuits, when the memory devices having various memory capacities are to be developed, the structure of each memory cell array unit is not changed but the number of memory cell array units is changed depending on the required memory capacities, in order to develop the memory devices in a short period. For example, memory capacities of memory devices to be developed are determined to be 128 Mbits, 64 Mbits, 32 Mbits and the like. In this case, a memory device having a memory capacity of 64 Mbits uses twice the number of memory cell array units of that of a memory device having a memory capacity of 32 Mbits. A memory device having a memory capacity of 128 Mbits uses twice the number of memory cell array units of that of a memory device having a memory capacity of 64 Mbits. Also, the peripheral circuits having the same circuit structure are commonly used for the memory devices having various memory capacities.
In such case, in a memory device having a relatively small memory capacity, the ECC type error recovery circuit is often omitted. This is because, in a memory device having a small memory capacity, a circuit area including memory cells and circuits which relate to an error recovery circuit becomes relatively large, when compared with a total chip area of the memory device. Therefore, when taking the number of effective pellets within a semiconductor wafer and the rate of error recovery by the ECC type error recovery circuit into consideration, a larger manufacturing yield is sometimes obtained when the ECC type error recovery circuit is not included in the memory chip, than when the ECC type error recovery circuit is included in the memory chip. Thus, in the conventional memory device, the ECC cells are disposed at the outermost portions of a memory cell array such that the ECC cells can be easily omitted from the memory cell array in a memory device which does not need the ECC cells. However, in recent memory devices, memory capacities have become larger than before, and, therefore, error recovery circuits such as the above-mentioned ECC type error recovery circuits have become essential for the memory devices. Therefore, the necessity of disposing the ECC cells at the outermost portion of the memory cell array becomes smaller than before.
In a memory device having an ECC type error recovery circuit, a read out speed of each memory cell is limited by a speed of a normal cell or an ECC cell which has lower read out speed. This is because, data read out from a normal cell and data read out from an ECC cell is operated and checked by an ECC operation circuit.
Also, a rising (or falling) time of a word select signal becomes slow at the far end portion of a word line when compared with that at the near end portion on the side of an X address decoder, and, therefore, a read out speed of cell data becomes slow at the far end portion of a word line.
FIG. 3 is a block diagram showing a schematic structure of a conventional memory device having an ECC type error recovery circuit. The memory device of FIG. 3 comprises a memory cell array 10c having a large number of memory cells (not shown in the drawing) which are disposed in a matrix and each of which is disposed at an intersection of a word line 6 and a digit line 8. The memory device of FIG. 3 further comprises an input circuit 1, a Y address decoder (or Y address decoding circuit: YDC) 2, an X address decoder (or X address decoding circuit: XDC) 3, an ECC operation circuit 4, sense amplifier blocks (SA) 5, and an output circuit 7.
The memory cell array 10c comprises normal cell array portions D0 and D1 and an ECC cell array portion P1. The ECC cell array portion P1 is disposed at the far end portion from the X decoder 3. The input circuit 1 comprises, for example, a plurality of buffer circuits, and receives input address data signals specifying memory cells from which data is to be retrieved. The input address data signals are divided into X address data signals and Y address data signals which are supplied to the X decoder 3 and Y decoder 2, respectively. The X address decoder 3 decodes the X address data signal supplied from the input circuit 1, and produces a word line selecting signal which is supplied to a selected word line. The Y address decoder 2 decodes the Y address data signal supplied from the input circuit 1, and produces digit line selecting signals for selecting digit lines. An ECC operation circuit 4 includes logic circuits such as exclusive OR circuits and the like, and performs error check and correction as known in the art.
In the memory device shown in FIG. 3, when a word line 6 is selected by the X decoder 3 and memory cells, for example, B, C and A, of normal cell array portions D0 and D1 and an ECC cell array portion P1 are selected by the Y decoder 2, a time required until a cell is selected becomes long as the location of the selected cell becomes far from the X address decoder 3. Therefore, in FIG. 3, the time required for selecting the cell A, that is, an ECC cell, and for sending data of the selected cell A to the ECC operating circuit 4 becomes longer than the time required for selecting each of the cells B and C, that is, each normal cell, and for sending data of each of the selected cells B and C to the ECC operating circuit 4. Thus, the time the data from the selected word is outputted is determined or limited by the time the data is outputted from the memory cell A, that is, the ECC cell.
Also, in case the read out speed of cell data is to be inspected or measured, it is possible to measure the read out speed of the normal cells by disabling the ECC error recovery circuit. However, it is impossible to measure the read out speed of the ECC cells. This is because, it is usually impossible to output cell data from the ECC cells. Also, data stored in the ECC cells corresponds to an operation result determined depending on the contents of the normal cells. Therefore, it is impossible to easily know or determine the content of data of the ECC cells from outside.
That is, when the ECC cells are disposed at far end portions of word lines, it is impossible to measure the worst data read out speed of a memory device, in order to perform production test of memory devices, to analyze the cause of a defect in operation speed and the like.
FIG. 4 is a block diagram showing another example of a conventional memory device having an ECC type error recovery circuit. The memory device of FIG. 4 comprises a memory cell array 10d having a large number of normal memory cells (not shown in the drawing) which are disposed in a matrix and each of which is disposed at an intersection of a word line 6 and a digit line not shown in the drawing. That is, the memory cell array 10d comprises normal cell array portions D0 and D1. The memory device of FIG. 4 also comprises a memory cell array 10e which is composed of an ECC cell array portion P1. The memory device of FIG. 3 further comprises an input circuit 1, Y address decoders (YDC) 2a and 2b, X address decoders (XDC) 3a and 3b, an ECC operation circuit 4, sense amplifier blocks (SA) 5, and an output circuit 7. The X address decoders 3a and 3b may have the same structure.
The input circuit 1 comprises, for example, a plurality of buffer circuits, and receives input address data signals specifying memory cells from which data is to be retrieved. The input address data signals are divided into X address data signals and Y address data signals which are supplied to the X address decoders 3a and 3b and Y address decoders 2a and 2b, respectively. The X address decoders 3a and 3b decodes the X address data signal supplied from the input circuit 1, and produces word line selecting signals each of which is supplied to a selected word line of the normal memory cell array 10d and the ECC memory cell array 10e. The Y address decoders 2a and 2b decode the Y address data signal supplied from the input circuit 1, and produce digit line selecting signals for selecting digit lines in the normal memory cell array 10d and the ECC memory cell array 10e. An ECC operation circuit 4 includes logic circuits such as exclusive OR circuits and the like, and performs error checking and correction as known in the art.
In the memory device shown in FIG. 4, a word line 6 in the normal memory cell array 10d is selected by the X decoder 3a and a corresponding word line (not shown in the drawing) in the ECC memory cell array 10e is selected by the X decoder 3b. Also, memory cells in the selected word line of the normal cell array 10d and memory cells in the selected word line of the ECC cell array 10e are selected by the Y decoders 2a and 2b, respectively. Thereby, data of the selected cells in the normal memory cell array portions D0 and D1 and data of the selected cells in the ECC memory cell array portion P1 are sent to the ECC operating circuit 4. The ECC operating circuit 4 performs error check and correction based on the data from the selected cells in the normal memory cell array portions D0 and D1 and the data from the selected cells, that is, ECC cells, in the ECC memory cell array portion P1, and produces corrected read out data which is supplied to outside via the output circuit 7.
In the memory device shown in FIG. 4, the ECC cell array portion P1 and the normal cell array portions D0 and D1 are provided as separate memory cell arrays, and operation of these cell array portions is independently performed. Therefore, a read out speed of cell data becomes slowest at a cell disposed at the far end portion of a word line, that is, at a normal memory cell disposed at the far end portion of a word line in the normal memory cell array 10d. Thus, it is possible to measure the worst read out speed of cell data.
However, as apparent from FIG. 4, this memory structure requires at least twice the number of word lines and the X address decoders to select the normal memory cells and the ECC memory cells. Therefore, a circuit scale of peripheral circuits becomes large and a chip size of the memory device becomes large.
FIG. 5 shows a conventional circuit including an ECC operation circuit 4 and a logic circuit for enabling and/or disabling the ECC error recovery. The circuit shown in FIG. 5 includes a NAND logic circuit NAND1 which receives an output data bit from a sense amplifier SA for ECC cell and a test enable signal from a test input terminal. The output of the NAND logic circuit NAND1 and an output of a sense amplifier SA for normal cell are both supplied to the ECC operation circuit 4 to perform error checking and correction.
In the circuit shown in FIG. 5, when the ECC error recovery is to be enabled, the test enable signal at the test input terminal is driven to a logically high potential, for example, to a power supply voltage VCC. Therefore, the output of the NAND1 depends on the output of the sense amplifier SA for ECC cell and is supplied to the ECC operation circuit 4, so that ECC error recovery operation can be performed. On the other hand, when the ECC error recovery is to be disabled, the test enable signal at the test input terminal is driven to a logically low potential, for example, to the ground. Therefore, the output of the NAND1 always becomes logically high, so that ECC error recovery operation is disabled and only normal cell data from the sense amplifier SA for normal cell is read out via the ECC operation circuit 4.
That is, in the circuit shown in FIG. 5, when the ECC error recovery is disabled, it is possible to read out the data from normal cells without being influenced by ECC cells and to measure the read out speed of the normal cell data from outside. However, the data of the ECC cells are used only for ECC operation and can not be outputted to outside. Therefore, it is impossible to measure the read out speed of the ECC cell data from outside. Although it is possible to build in a memory device an additional circuit for outputting the ECC cell data to outside, the circuit scale of such memory device becomes large.
In summary, in the conventional memory device having an ECC type error recovery circuit, when the ECC cells are disposed at far end portions of word lines, it is impossible to measure the worst data read out speed of a memory device, in order to perform production test of memory devices, to analyze the cause of a defect in operation speed and the like. This is because, it is impossible to read the ECC cell data from outside. When an additional circuit is built in a memory device for outputting ECC cell data to outside, the circuit scale of such memory device becomes too large.