The escalating requirements for high density and performance associated with ultra large scale integration semiconductor wiring require responsive changes in interconnection technology. Such escalating requirements have been found difficult to satisfy in terms of providing a low RC (resistance capacitance) interconnection pattern, particularly wherein submicron vias, contacts and trenches have high aspect ratios due to miniaturization.
Conventional semiconductor devices typically comprise a semiconductor substrate, such as undoped monocrystalline silicon, and a plurality of sequentially formed inter-layer dielectrics and patterned metal layers. An integrated circuit is formed containing a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Typically, the conductive patterns on different layers, i.e., upper and lower layers, are electrically connected by a conductive plug filling a via opening, while a conductive plug filling a contact opening establishes electrical contact with an active region on a semiconductor substrate, such as a source/drain region. Conductive lines are formed in trenches which typically extend substantially horizontal with respect to the semiconductor substrate. Semiconductor "chips" comprising five or more levels of metallization are becoming more prevalent as device geometries shrink into the deep submicron range.
A conductive plug filling a via opening is typically formed by depositing an inter-layer dielectric on a patterned conductive (metal) layer comprising at least one metal feature, forming an opening in the inter-layer dielectric by conventional photolithographic and etching techniques, and filling the opening with a conductive material, such as tungsten (W). Excess conductive material on the surface of the inter-layer dielectric is removed, as by chemical-mechanical polishing (CMP). One such method is known as damascene and basically involves the formation of an opening which is filled in with a metal. Dual damascene techniques involve the formation of an opening comprising a lower contact or via opening section in communication with an upper trench opening section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with a conductive line.
High performance microprocessor applications require rapid speed of semiconductor circuitry. The speed of semiconductor circuitry varies inversely with the resistance and capacitance of the interconnection pattern. As integrated circuits become more complex and feature sizes and spacings become smaller, the integrated circuit speed becomes less dependent upon the transistor itself and more dependent upon the interconnection pattern. Miniaturization demands long interconnects having small contacts and small cross-sections. As the length of metal interconnects increases and cross-sectional areas and distances between interconnects decrease, the RC delay caused by the interconnect wiring increases. If the interconnection node is routed over a considerable distance, e.g., hundreds of microns or more, as in submicron technologies, the interconnection capacitance limits the circuit node capacitance loading and, hence, the circuit speed. As design rules are reduced to about 0.18 micron and below, e.g., about 0.15 micron and below, the rejection rate due to integrated circuit speed delays severely limits production throughput and significantly increases manufacturing costs. Moreover, as line widths decrease, electrical conductivity and electromigration resistance become increasingly important.
As device geometries shrink and functional density increases, it becomes increasingly imperative to reduce the capacitance between metal lines. Line -to- line capacitance can build up to a point where delay time and cross talk may hinder device performance. Reducing the capacitance within multi-level metallization systems will reduce the RC constant, cross talk voltage, and power dissipation between the lines.
One way to increase the speed of semiconductor circuitry is to reduce the resistance of a conductive pattern. Conventional metallization patterns are typically formed by depositing a layer of conductive material, notable aluminum or an alloy thereof, and etching, or by damascene techniques wherein trenches are formed in dielectric layers and filled with conductive material. The use of metals having a lower resistivity than aluminum, such as copper, engenders various problems which limit their utility. For example, copper readily diffuses through silicon dioxide, the typical dielectric material employed in the manufacture of semiconductor devices, and adversely affects the devices. In addition, copper does not form a passivation film, as does aluminum. Hence, a separate passivation layer is required to protect copper from corrosion.
The dielectric constant of materials currently employed in the manufacture of semiconductor devices for an inter-layer dielectric (ILD) spans from about 3.9 for dense silicon dioxide to over 8 for deposited silicon nitride. The value of the dielectric constants expressed herein is based upon a value of 1 for a vacuum. Prior attempts have been made to reduce the interconnect capacitance and, hence, increase the integrated circuit speed, by developing dielectric materials having a lower dielectric constant than that of silicon dioxide. Materials which may offer promise for use as ILDs include various carbon-containing low dielectric constant materials, typically having a dielectric constant of about 2.0 to about 3.8. Such carbon-containing dielectric materials include various polymers with carbon occupying a position in the backbone in an amount of about 0.5 to about 8 mol %, e.g., about 4 to about 8 mol %. Typical of such carbon-containing polymers are benzocyclobutene (BZB), methyl silsesquioxane (MSQ), FLARE.RTM.R, Silk.RTM., JSR and Black Diamond.RTM..
However, in attempting to employ such carbon-containing dielectric materials in interconnect technology, as for gap filling or as an ILD, it was found that their dielectric constant became undesirably elevated as a result of subsequent processing. For example, with BCB, the dielectric constant was found to increase from about 2.6 to greater than about 4. It is believed that such an increase occurs as a result of exposure to an oxide photoresist stripping technique used to remove photoresist material after formation of an opening in a dielectric layer, as, for example, a plug or dual damascene opening for interconnection of metal features on different metal levels.
The dry process of removing photoresist typically uses oxygen to strip organic resists. Plasma excitation results in atomic oxygen, which oxidizes photoresist into gases such as CO, CO.sub.2, and H.sub.2 O that are then removed from the chamber by a pump. A plasma chemistry weaker than O.sub.2 is desired for stripping resist on sensitive films. Organic lo-k dielectrics are the most sensitive of all since they are of similar make-up to photoresist and, thus, must be protected during striping. It has been found that the organic lo-k materials are chemically altered so that the dielectric constant is higher, and the oxygen plasma may also strip a portion of the lo-k material as well.
For example, when forming a via, a photoresist mask is deposited on the ILD and an opening is formed therein, as by anisotropic etching, to expose an underlying metal feature along with portions of the ILD. The photoresist mask is then stripped, typically employing an oxygen-containing plasma. Upon employing a carbon-containing dielectric material, such as BCB, as the ILD, the exposed portions thereof are subjected to the oxygen-containing plasma causing an increase in the dielectric constant of the carbon-containing dielectric material along with the photoresist mask, thereby adversely impacting capacitance and device reliability.
Recent attempts have also resulted in the use of low-density materials, such as an aerogel, which has a lower dielectric constant than dense silicon oxide. The dielectric constant of a porous silicon dioxide, such as an aerogel, can be as low as 1.2, thereby potentially enabling a reduction in the RC delay time. However, conventional practices for producing an aerogel require a super critical drying step, which increases the cost and degree of complexity for semiconductor manufacturing. Moreover, the use of an aerogel results in a semiconductor device which lacks sufficient structural integrity.
In view of the potential advantages of employing relatively low dielectric constant carbon-containing dielectric materials in high density, multi-level interconnection patterns, there exists a need for methodology enabling the removal of a photoresist mask without increasing the dielectric constant or causing removal, of such carbon-containing dielectric materials.