Q:

More detail about new AVR instructions LAC, LAS, LAT and XCH

Looking at the AVR instruction set there are four instructions added in 2010
LAC load and clear
LAS load and set
LAT load and toggle
XCH load and exchange

Does anyone know what chips have these instructions
What tools support these instructions
More information on what they do  
(Z) <- Rd v (Z), Rd <- (Z)

does that imply that Rd and (Z) get the same value or does Rd get the pre-modified value of what was pointed to by Z?

A:

These are probably not around in current (as of initial question) chips, but all have a common theme - atomic memory operations. Their purpose is typically for synchronisation between threads, and their inclusion at an instruction set level probably indicates that Atmel are planning to launch a multi-core AVR chip. Since they're specified now tool vendors can add them to assemblers already, but they won't make a big deal of that until chips have the instructions. (Edit: As it turns out, the other core is the USB peripheral, not a CPU. Thanks to avakar for that information.)
The behaviour, as I read it from the Atmel AVR 8-bit Instruction Set Manual:
LAC - Load and Clear, loads memory contents *Z into register Rd while simultaneously clearing bits in *Z that were set in Rd. 
LAS - Load And Set simultaneously sets bits in a memory location that were set in a register, and loads the register with the prior contents of the memory location. Very useful for single-bit mutexes, for instance.
LAT - Load And Toggle; like LAS, but instead of bitwise or, it uses bitwise xor, thus toggling bits. 
XCH - Exchange; simply exchanges memory and register contents. 
All of them are RAM access instructions (07/2014 reference states they take two cycles), which combine operations so they could also make code that needs RAM faster than it currently is. 

