1. Field of the Invention
The present invention relates to electronic devices and, in particular, relates to devices and methods of forming capacitors for integrated circuitry.
2. Description of the Related Art
Since the introduction of the digital computer, electronic storage devices have been a vital resource for the retention of binary data. Conventional semiconductor electronic storage devices typically incorporate capacitor and transistor type structures, which are referred to as Dynamic Random Access Memory (DRAM), that temporarily store binary data based on the charged state of the capacitor structure. In general, this type of semiconductor Random Access Memory (RAM) often requires densely packed capacitor structures that are easily accessible for electrical interconnection therewith. Many of these capacitor structures are fabricated with layers of material including semiconductor, dielectric, and metal.
Some conventional capacitor structures have lower electrodes that are fabricated by first forming sacrificial spacers within a recessed substrate such that the capacitor occupies less than the width of the recess formed in the substrate. Conventional fabrication techniques of the lower electrode are complex and often requires many process steps. Typical process steps often require etching of a recess in a substrate, contiguous deposition of a sacrificial material layer on the substrate and within the recess, and etching of the sacrificial material layer so as to form sacrificial spacers on the sidewalls of the recess. Unfortunately, these sacrificial spacers reduce the width of the recess, which also reduces the effective width of the capacitor structure. Further processing steps require contiguous deposition of conductive material on the substrate and within the recess so as to overlie the sacrificial spacers, planar etching of the conductive layer to the substrate surface so as to form the lower electrode, and etching away of the sacrificial spacers so as to form cavities between the lower electrode and the substrate. Then, to form the rest of the capacitor structure, the dielectric layer followed by the top conductive layer can be deposited on the lower electrode.
Due to the excessive process steps involved with the use and formation of sacrificial spacers, inefficiencies can arise through the use of sacrificial spacers, which can inadvertently increase fabrication costs due the excessive process times, procedures, and materials. Another problem with using sacrificial spacers is that the capacitor structure including the lower electrode cannot use the full width of the recess, which can adversely affect the performance of the capacitor structure. Hence, there currently exists a need to reduce manufacturing costs associated with fabricating capacitor structures by simplifying inefficient procedures. To this end, there also exists a need to increase fabrication efficiency by improving the processing techniques associated with fabricating capacitor structures.