In general, an amount of electrical power dissipated by a processor during operation is directly proportional to the frequency of a clock signal used to synchronize internal processor activities. As processor clock signal frequencies continue to increase, processor power dissipation remains an important system design consideration. This is particularly true for battery powered electronic devices including processors such as portable computers and cellular telephones. A charged battery typically stores a fixed amount of electrical energy, and reducing power dissipation is essential to extending battery life.
In systems where a processor spends a significant amount of time waiting (e.g., for input or for another device to be ready to accept data), processor power dissipation may be reduced without significantly impacting performance by either reducing the frequency of the clock signal or putting the processor in a lower power dissipation state during the waiting periods.
Several processors implement a normal operating mode and at least one lower power dissipation operating mode. For example, some processors implement the normal mode and an idle mode and/or a halt mode. The processor normally operates in the Normal mode, and can be placed in the idle or halt mode (typically under software control). In both the idle and halt modes the state of the microcontroller may be maintained; that is, the contents of memory elements (e.g., registers) and the states of any output signals may be maintained. Normal mode operation is typically restored via a wakeup routine executed in response to external stimulus (e.g., an interrupt signal or assertion of a RESET signal).
For example, in the idle mode, all processor activities may substantially be stopped except clock signal generating circuitry and timer/counter circuitry. The timer/counter circuitry may be configured to generate an interrupt signal at regular time intervals, effectively “waking up” the processor at the regular time intervals. As a result, the processor dissipates significantly less power in the idle mode than in the normal mode.
One extremely useful application of such an idle mode is unattended data logging. For example, the timer/counter circuitry may be configured to generate an interrupt at the regular time intervals, and the processor may be placed in the Idle mode. In response to the interrupts, the processor may transition from the Idle mode to the normal mode, acquire and store data, and then transition from the normal mode to the idle mode. As a result, overall processor power dissipation is reduced.
In the halt mode, for example, all activities within the processor may be stopped including any timer/counter circuitry. As a result, the processor dissipates significantly less power in the halt mode than in the normal mode. An interrupt signal from an external device (such as via an input/output port) or assertion of the RESET signal may trigger a wake up routine that restores normal mode operation.
One example of an application of halt mode is in a computer system including a separate keyboard processor. For reduced power dissipation, the keyboard processor may be kept in the halt mode until an interrupt signal, generated in response to a keystroke, wakes up the keyboard processor. In response to the interrupt signal, the keyboard processor may transition from the halt mode to the normal mode, decode and send the keystroke to a host computer, and then transition from the normal mode to the halt mode.
A typical processor has a RESET terminal to receive the externally generated RESET signal mentioned above. A computer system including the processor typically asserts the RESET signal to put the processor in a known state (i.e., a reset state). For example, the computer system may assert the RESET signal when the processor is in an unknown state (e.g., when electrical power is first applied) or when the processor is in an undesired state (e.g., when the processor is operating in the idle or halt mode with interrupts disabled). In response to the RESET signal, the processor typically loads predetermined values into specific registers. This action may, for example, cause the processor to subsequently fetch and execute instructions of system initialization code stored in read only memory (e.g., a bootstrap program).
As used herein, the term “interrupt signal” refers to a control signal which indicates a high-priority request for service. For example, a peripheral device connected to a processor may assert an interrupt signal when ready to transmit data to the processor, or to receive data from the processor. It is noted that an interrupt signal generated external to a processor may not be synchronized with a clock signal of the processor.
The two general categories of types of interrupt signals are “non-maskable” and “maskable.” The typical processor described above also has a non-maskable interrupt (NMI) terminal for receiving an NMI signal, and a maskable interrupt (IRQ) terminal for receiving an IRQ signal. The NMI signal is typically asserted when a catastrophic event has occurred or is about to occur. Examples of non-maskable interrupts include bus parity error, failure of a critical hardware component such as a timer, and imminent loss of electrical power.
In general, maskable interrupts are lower-priority requests for service that need not be tended to immediately. Maskable interrupts may be ignored by the processor under program control. A request for service from a peripheral device which is ready to transmit data to a processor, or receive data from the processor, is an example of a maskable interrupt. An interrupt controller (e.g., a programmable interrupt controller or PIC) connected to the processor typically receives maskable interrupt requests from devices connected to the processor, prioritizes the interrupt requests.
When a processor receives an interrupt, application program execution stops, the contents of certain critical registers are saved (i.e., the internal state of the processor is saved), and internal control is transferred to an interrupt service routine (i.e., an interrupt handler) which corresponds to the type of interrupt received. In the case of a maskable or non-maskable interrupt, the interrupt controller typically identifies the interrupt to be serviced.
In a vectored interrupt system, the interrupt controller typically provides a number or instruction address assigned to the interrupt to an instruction sequencing module of the processor (e.g., during an interrupt acknowledge operation). A non-maskable interrupt is typically assigned a specific interrupt number. The processor uses the interrupt number as an index into the interrupt vector table to obtain the address of the appropriate interrupt service routine. When the interrupt service routine is completed, the saved contents of the critical registers are restored (i.e., the state of the processor is restored), and the processor resumes application program execution at the point where execution was interrupted.
Many modeen processors employ a technique called pipelining to execute more software program instructions (instructions) per unit of time. In general, processor execution of an instruction involves fetching the instruction (e.g., from a memory system), decoding the instruction, obtaining needed operands, using the operands to perform an operation specified by the instruction, and saving a result. In a pipelined processor, the various steps of instruction execution are performed by independent units called pipeline stages. In the pipeline stages, corresponding steps of instruction execution are performed on different instructions independently, and intermediate results are passed to successive stages. By permitting the processor to overlap the executions of multiple instructions, pipelining allows the processor to execute more instructions per unit of time.
In general, a “scalar” processor issues instructions for execution one at a time, and a “superscalar” processor is capable of issuing multiple instructions for execution at the same time. A pipelined scalar processor concurrently executes multiple instructions in different pipeline stages; the executions of the multiple instructions are overlapped as described above. A pipelined superscalar processor, on the other hand, concurrently executes multiple instructions in different pipeline stages, and is also capable of concurrently executing multiple instructions in the same pipeline stage.