Increasing processing speeds of devices such as graphics processors, hard disks, network cards, and other high speed I/O devices have created a need for an increased bandwidth for communicating between devices. One way to increase bandwidth between the bridge circuit and the I/O device is to use a differential communication link such as PCI Express™, HyperTransport™, SATA, USB, or other suitable differential communication links. Such interfaces are a flexible, hybrid serial-parallel interface format that uses multiple differential communication links often referred to as lanes. Each link includes transmit lanes to transmit information and receive lanes to receive information.
A transmitter circuit is typically coupled to one or more of the transmit lanes to transmit information over the transmit lane(s). In order to reduce power consumption, complementary current mode logic (CML) drivers can be used in transmitter circuits rather than conventional uni-polar CML drivers. For example, a complementary CML driver will typically consume approximately 12 mA of current in order provide a 1.2V differential swing via a transmit lane. Conversely, a uni-polar CML driver will typically consume approximately 24 mA of current (i.e., approximately twice as much as the complementary CML driver). However, due to the bi-polar current sources used in complementary CML drivers, current calibration and biasing can be difficult due to dual bias loops.
One known method to bias a complementary CML driver is to use a current mirror circuit to copy a calibrated current to the bi-polar current sources of the complementary CML driver. However, this method requires a substantial number of circuit components, which increases the size of the circuit and additionally increases power consumption of the complementary CML driver. In addition, this method can have a current mismatch of 30-40%, which is undesirable.
Accordingly, a need exists for a current biasing circuit for a complementary CML driver that requires less components, consumes less power than known biasing circuits, and has an improved current mismatch.