In silicon-on-chip (SOC) designs, flip-flop circuits such as D-type flip-flops (DFFs) or scan DFFs (SDFFs and also referred to as scan flip-flops) are used to perform desired functions of a circuit design. For example, scan chains that comprise a plurality of interconnected scan flip-flops are used to obtain access to internal nodes of an integrated circuit (IC) to simplify testing of the IC by passing test data through the scan flip-flops. The scan flip-flop is configured to operate in one of two modes, data mode and scan mode. When a scan enable signal (assumed active high) of a scan flip-flop is set to a low logical value, the scan flip-flop is in the data mode. When the scan enable signal of the scan flip-flop is set to a high logical value, the scan flip-flop is in scan mode. For a full scan design, during scan testing, all of the flip-flops and all of the combinational logic connected to the flip-flops, may be toggling at the same time, causing relatively high power consumption. This high power consumption may exceed the circuit's power rating as IC chip density and speed increase.