Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), and non-volatile memory. The trend in the semiconductor industry is toward smaller memory devices that may be used to fabricate high density circuits on a single chip. The miniaturization of transistor devices and circuits may be achieved by reducing the size of all the features of surface-oriented devices so that the resultant devices occupy a smaller surface area of a wafer.
FIG. 1 illustrates a conventional DRAM array 10 including an array of access devices 12 formed on a semiconductor substrate 14. Each of the access devices 12 includes a planar transistor 16 and a capacitor cell 13. Gate electrodes 18 and 19 for the transistors 16 are separated from a channel region 20 of the transistor 16 by an insulator, such as an oxide. The channel region 20 of the transistor 16 separates a source region 26 from a drain region 24. The drain regions 24 may each be electrically coupled to the capacitor cell by a first contact 28. A second contact 30 may be coupled to a voltage source. During operation, current flow between source region 26 and the drain region 24 is parallel to a major surface of the semiconductor substrate 14. Since the source and drain regions are formed in the semiconductor substrate 14, coupling of the access devices 12 of the DRAM array 10 requires that sufficient space remain between the transistors 16 such that the first contact 28 and the second contact 30 may be formed. Spacers 32 are formed on sidewalls of each of the transistors 16. The access devices 12 are isolated by shallow trench isolation (“STI”) features 25 in the substrate 14. With the STI features isolating the cell, the conventional DRAM array 10 consumes excessive real estate (i.e., surface area) on the substrate 14. Furthermore, conventional access devices 12 of DRAM arrays 10 such as that shown in FIG. 1 occupy an area of greater than or equal to 6F2.
In order to achieve devices with higher packing density, it is possible to shrink the length and width of the channel region 20 of the transistors 16. However, there are several drawbacks to shrinking planar transistors 16 in access devices 12 of DRAM arrays 10, such as threshold voltage variation, short-channel effect (“SCE”), increase of substrate-bias effect due to impurity concentration enhancement in the channel region, and reliability degradation by hot-carriers. The narrow width transistors also cause decrease of current drivability and reliability degradation. The high parasitic resistance-capacitance (“RC”) and inefficient interconnections of the narrow width transistors results in high external resistance.
Devices including vertical transistors have been proposed to overcome the limit in area of planar transistors 16 used in conventional DRAM arrays 10. Such vertical transistors include a channel region generally perpendicular to a major surface of a semiconductor substrate such that current flow between source and drain regions of transistors is substantially orthogonal to a major surface of a semiconductor substrate. However, conventional methods of manufacturing devices that include vertical transistors are complicated. For example, numerous masks are conventionally used to define elements of devices including vertical transistors, contacts to the source regions and drain regions and metal interconnects. Forming each of these masks is a time and cost intensive process. Therefore, conventional methods of forming memory devices including vertical transistors are not desirable due to high process costs and complexity.