I. Field of the invention
This invention relates generally to electrical connector devices, and more particularly to the design of a zero insertion force connector especially adapted for joining the terminal pins of pin grid array semiconductor devices to mating spring pins on a printed wiring board.
II. Discussion of the Prior Art
In the past, a common packaging arrangement for integrated circuits has been the so-called dual inline package (DIP) in which the active semiconductor devices are encased in a housing having a generally rectangular configuration with leads exiting the opposed longitudinal edges in an aligned row of pins. When electrically connecting such IC packages to other circuit components via a printed wiring board, the practice has been to either position the IC directly on the printed circuit board with its dual inline terminals directly entering correspondingly aligned plated-through holes on the printed circuit board and held in place in a wave soldering operation or to first install an integrated circuit socket onto the board and then plugging the terminals of the IC device into the socket. Each of the above approaches has been found to be workable when the number of terminal pins involved is less than 40, which is typical for LSI technology.
With the advent of very large scale integrated circuit technology (VLSI), a substantially increased number of active devices are included on a single VLSI chip and, accordingly, a need exists for an increased number of terminal pins so that electrical signals and power can be interfaced with the device. To keep the speed of the circuit high, short path lengths on the device are necessary. One approach in obtaining an increased number of pin-outs and short path lengths has been to encase the VLSI chip in a generally square housing whose dimensions are typically 1.1".times.1.1" for a 12.times.12 pin array and then having a plurality of terminal pins exiting the base of the package rather than its side edges, the pins being arranged in a grid-like pattern of uniformly spaced rows and columns. Typically, such a VLSI pin grid array (PGA) package may include in excess of 100 such pins laid out in a grid pattern on 0.100 inch centers.
While IC sockets have proved workable for DIP packages having comparatively few pin-out terminals, the same approach cannot effectively be used for PGA devices because of the high insertion forces associated with that large number of terminal pins to be accommodated. Similarly, direct insertion of PGA device terminal pins directly into a matching pattern of plated-through holes on the printed circuit board creates significant problems in inspecting and correcting any soldering faults that may arise during the wave soldering operation used to join the device to the associated PC board. The same is true for the normal PGA socket mounted directly on the board. Because the device or socket necessarily must rest directly upon the surface of the PC board with the terminal pins being soldered into the grid pattern of plated-through holes on the PC board, it is practically impossible to effectively visually inspect each of the connections on both sidese of the board to ensure that a good solder joint has been created and that the board surfaces have been effectively cleaned to remove any corrosive soldering flux that might later lead to a fault. Furthermore, it is not possible using this technique to obtain a conformal coating on both sides of the board about the terminal pins following their insertion into the printed board for electrically insulating the closely spaced terminal pins from one another.
It should be pointed out that the prior art does contain one technique which overcomes the above difficulties. This technique is the use of individual pin sockets separately installed in the individual plated-thru-holes. Such pin sockets come in two forms, each of which is subject to certain restrictions which limits their use in high density packaging. The first type consists of a large diameter socket body (typically greater than 0.050 inch diameter) which sits above the board surface. Appended to the bottom of the socket portion is a smaller diameter solder tail (typically 0.020 inch diameter--comparable to the diameter of the PGA device pins). The solder tail is soldered into the plated-thru-hole and the socket body sits above the board. This form of pin socket has the advantage of requiring only a normal sized plated-thru-hole, thus allowing space between holes for routing traces on the various layers of the laminated printed wiring board, but it has the major disadvantage of adding considerably to the vertical height above the board (typically increasing the component height by 0.200 to 0.250 inch). The latter disadvantage frequently obviates the use of such pin sockets in high density electronic packaging where desired low board-to-board spacing restricts the maximum component height which may be accommodated.
The second type of pin socket consists only of the large diameter socket portion which is inserted totally into large diameter plated-thru-holes. This construction adds little to component height (typically only a 0.020 inch flange sits above the board), but the large diameter plated-thru-hole severely restricts the space left between holes for routing traces. Thus, this design cannot be used for PGA devices where multiple traces between holes are frequently necessary. This is particularly the case in high reliability circuits where the design rules governing hole size tolerances and trace width tolerances are more restrictive.
In addition to the above-mentioned problems associated with directly joining a PGA device to a printed wiring board, a further significant problem exists when it is determined that there has been a solder defect and it becomes necessary to repair the board prior to its use. Those skilled in the art will recognize that, when using VLSI, it is necessary to also use multi-layer printed circuit boards to accommodate the necessary number of interconnects between the ICs and other components that may populate the PC board. These multi-layer PC boards commonly include one or more ground planes which tend to be generally continuous layers of unetched copper. Still other layers include patterns of fine printed wiring joining small terminal pad areas to one another. When the foregoing is considered, it becomes readily apparent that significant differences exist in the thermal capacity of each of the plated-through holes and, hence, the problem of unsoldering such a large number of terminal pins from the plated-through holes becomes very difficult and often results in the need to totally scrap the entire board. Naturally, depending upon the complexity of the active and passive devices populating the board, this can be exceedingly costly.
While many of the desirable features of this prevent invention are available separately in other devices, the features are normally mutually exclusive, e.g., zero insertion force sockets have high "real estate", that is, board area requirements and add considerably to component height. The present invention is unique in that such features as zero insertion force, high retention force, low "real estate" requirement, low additional component height, normal plated-thru-hole size requirement, complete removability from the board permitting cleaning, inspection and conformal coating plus individual solder joint repair or individual pin replacement, as well as low parts cost and low non-recurring tooling costs are all present in a single device.
The device of the present invention obviates all of the foregoing problems. More particularly, it provides an inexpensive device for joining PGA devices to PC boards while allowing inspection of the solder joints on both sides of the board and the necessary access whereby the board can be cleaned free of contaminants following the wave soldering operation. In addition, the connector device of the present invention permits the application of conformal coatings and exhibits zero insertion force or very low insertion force characteristics. The connector of the present invention also does not waste "real estate" on the PC board to the extent that other prior art zero insertion force sockets are likely to do.
Of particular importance is the fact that the device of the present invention adds very little to the vertical dimension of the mounted component, i.e., the total component height increase can be held to less than 0.100 inch. As already mentioned, this feature is significant, particularly in high density packaging because the close board spacing severely limits maximum component height.