1. Technical Field
The present disclosure relates to a driving circuit of an OLED diode (organic light emission diode), and more particularly, but not exclusively, relates to a driving circuit for display applications of the AM-OLED type, and the following description is made with reference to this field of application by way of illustration only.
2. Description of the Related Art
As is known, visualization devices or displays using organic light emission diodes, also indicated as OLED display, acronym from the English: “Organic Light Emitting Diode”, have found greater use in recent years.
These OLED displays are generally used in place of the displays with liquid crystals, differently from those that do not require additional components for being illuminated. It is in fact known that the displays with liquid crystals do not produce light, but are illuminated by an external light source, while the OLED devices produce their own light due to the presence of at least one layer of organic material enclosed by suitable metallic layers with the functions of cathode and anode. In particular, due to the monopolar nature of this layer of organic material, the OLED devices conduct current only in one direction, thus behaving similarly to a diode; herefrom the name of O-LED, by way of similitude with LED (acronym from the English: “Light Emitting Diode”, i.e., light emission diode).
It is thus possible, by using these OLED diodes, to realize much thinner displays, even flexible and rollable, and requiring smaller amounts of energy to operate.
In its most general form, an OLED display is made of several overlapped layers. In particular, on a first transparent layer, which has protective functions, a transparent conductive layer is deposited serving as an anode; subsequently at least three organic layers are generally added: one for the injection of the holes, one for the transport of electrons, and, between them, the three electroluminescent materials (red, green and blue), arranged to form a single layer made of many elements, each of them being substantially realized by three colored microdisplays. Finally, a reflecting layer is deposited that serves as a cathode.
In spite of the multiple layers, the total thickness, without considering the transparent layer, is of about 300 nanometers, making these OLED displays particularly useful in miniaturized applications.
In general, to form a display, the OLED diodes are organized in a matrix of pixels and are connected to a driving circuit suitable for supplying each OLED diode of this matrix with a current value necessary to obtain the luminescence of the diode itself according to a suitable addressing scheme.
Driving circuits realized in TFT technology (acronym from the English “Thin Film Transistor”, i.e., a thin film transistor) are widely used. In this case they are OLED displays with active matrix or AM-OLED, acronym from the English: “Active Matrix—Organic Light Emitting Diode”.
In such a driving circuit, a TFT transistor is connected to each OLED diode of the matrix so that, by driving with a suitable voltage the control or gate terminal of this TFT transistor, it is possible to modulate the current supplying the OLED diode, thus obtaining colors of different gradation (generally indicated with the English words grey-level scale or several color scale).
In its most simple form, a driving circuit for an OLED diode is schematically shown in FIG. 1, globally indicated with 1.
This driving circuit 1 has an input terminal IN1 receiving an input voltage signal Vdata and an output terminal OUT1 connected to an OLED diode, indicated as OL, in turn connected to a first voltage reference, in particular a supply voltage reference VDD.
The driving circuit 1 essentially includes a first TFT driver transistor T1, inserted between the output terminal OUT1 and a second voltage reference, in particular a ground GND, and a second TFT selection transistor T2, inserted between a control terminal or gate of the first TFT driver transistor T1 and the input terminal IN1 and having in turn a control or gate terminal receiving a select voltage signal Vsel.
The driving circuit 1 finally includes a storage capacitor Cs inserted between the gate terminal of the first TFT driver transistor T1 and the ground GND.
Essentially, the first TFT driver transistor T1 serves for driving the OLED diode OL, enabled by the second TFT selection transistor T2, which is essentially a switch driven by the select voltage signal Vsel. Moreover, the storage capacitor Cs preserves a piece of electric information (under the form of charge) for the gate terminal of the first TFT driver transistor T1, during the scanning of the other rows of the matrix of pixels, i.e., the so called frame time where the refresh of the whole image occurs.
In the embodiment shown in FIG. 1, the TFT transistors T1 and T2 are N-channel transistors or nTFT.
When the select voltage signal Vsel enables the transmission of the datum, i.e., of the input voltage signal Vdata, through the second TFT selection transistor T2, this input voltage signal Vdata is transferred to the gate terminal of the first TFT driver transistor T1, thus imposing that the current flowing to the OLED diode OL is given by the relation:
                              I          DS                =                              μ            0                    ⁢                      C            ox                    ⁢                                    W              L                        ·                                                            (                                                            V                                              GS                        ⁢                                                                                                  ⁢                        1                                                              -                                          V                                              t                        ⁢                                                                                                  ⁢                        1                                                                              )                                2                            2                                                          (        1        )            being
IDS the drain current value of the first TFT driver transistor T1 transferred to the OLED diode OL; and
VGS1, Vt1, COX, μ0, W and L are, respectively, the voltage value between the gate and source terminals, the threshold voltage value, the capacity by surface unit, the mobility of the charge carriers, the gate width and length of the first TFT driver transistor T1.
At the end of the so called timing diagram, i.e., of the temporal window wherein the driving signals of the single pixel are applied, the select voltage signal Vsel disables the transfer through the second TFT selection transistor T2, and the datum is maintained between the electrodes of the storage capacitor Cs.
From the equation (1), it is noted how the current IDS that the OLED diode OL is supplied with quadratically depends on the threshold voltage value Vt1 of the first TFT driver transistor T1.
Unfortunately, it is well known that in the TFT transistors a considerable variation of the threshold voltage can be registered, which is strongly correlated and sensitive to certain process parameters that are to be controlled in an accurate way. With the input voltage signal Vdata identical, a non uniformity follows of the luminosity of the pixels of the matrix of a same AM-OLED display, the driving circuit 1 not succeeding in supplying the OLED diodes of the matrix of pixels with a stable current value.
FIG. 2 shows the simulated progress of the current IDS flowing through the OLED diode OL for three topologically identical circuits, but different as regards the threshold voltage value Vt1 of the TFT driver transistor T1 comprised therein. The simulations have been carried out with the software AIM-Spice 3.2, using, for the TFT transistors, the level 12.
Moreover, a form ratio (W/L) of the two TFT transistors, T1 and T2, has been considered, fixed at a value equal to (W/L)1=(10 μm)/(5 μm), and (W/L)2=(2 μm)/(2 μm), respectively, with values of the parameters μ0 and Vt1, relative to the surface mobility of the carriers and to e threshold voltage, respectively fixed equal to 100 cm2/(Vs) and 2.0 V, with a value of the storage capacitor Cs equal to 1 pF.
From the simulations carried out, it has been verified that, by a variation of ±10% of the threshold voltage value Vt1 of the first TFT driver transistor T1, a considerable difference is revealed in the values of the current IDS that the OLED diode OL is supplied with. In particular, in correspondence with a variation of +10% (Vt1=2.2 V, curve F−), a current difference is revealed equal to 10.4% (indicated in the figure as DI−); in correspondence with a variation of −10% (Vt1=1.8 V, curve F+), it occurs instead that the current has a variation equal to 10.2% (indicated in the figure as DI+).
To overcome the above discussed problem of the luminosity variation between the pixels, different circuit solutions have been proposed using a greater number of devices, in particular TFT transistors.
A first known solution, proposed by S. H. Jung, W. J. Nam, and M. K. Han in the article entitled: “A New Voltage Modulated AMOLED Pixel Design Compensating Threshold Voltage Variation of Poly-Si TFTs”, School of Electrical Engineering, Seoul National University, Seoul, KOREA ISSN/0002-0966X/02/3 622•SID 02 DIGEST 301-0622-$1.00+0.00© 2002 SID, is a driving circuit realized with four TFT transistors with p channel or p-TFT and a storage capacitor, schematically shown in FIG. 3 and globally indicated with 3.
This driving circuit 3 has an input terminal IN3 receiving an input voltage signal Vdata and an output terminal OUT3 connected to an OLED diode, always indicated as OL, in turn connected to a first voltage reference, in particular a ground GND.
As previously seen, the driving circuit 3 comprises a first TFT driver transistor T1, inserted between the output terminal OUT3 and a second voltage reference, in particular a supply voltage reference VDD, and a second TFT selection transistor T2 connected to the input terminal IN3 and having in turn a control or gate terminal receiving a select voltage signal Vsel.
The driving circuit 3 also comprises first and second TFT discharge transistors, respectively T3 and T4, diode-wise connected and inserted, in parallel to each other, between the second TFT selection transistor T2 and the gate terminal of the first TFT driver transistor T1.
The driving circuit 3 further includes a storage capacitor Cs inserted between the supply voltage reference VDD and the gate terminal of the first TFT driver transistor T1.
As previously, the TFT transistors T1 and T2 operate, respectively, as driver and as switch, while the block formed by the transistors T3 and T4 allows to discharge the storage capacitor Cs for the refresh of the information and enhance the voltage value at the gate terminal of the first TFT driver transistor T1 by an amount equal to the threshold voltage Vt3 of the second TFT discharge transistor T3.
In fact, when the select voltage signal Vsel turns on the second TFT selection transistor T2, the datum is transferred to the gate terminal of the first TFT driver transistor T1 through the second TFT discharge transistor T3 which is diode-wise connected. The current transferred to the OLED diode OL is given, therefore, by the relation:
                                                                                                          I                  DS                                                            =                                                μ                  0                                ⁢                                  C                  ox                                ⁢                                                      W                    L                                    ·                                                                                    (                                                                                                                                        V                                                              GS                                ⁢                                                                                                                                  ⁢                                1                                                                                                                                          -                                                                                                                V                                                              t                                ⁢                                                                                                                                  ⁢                                1                                                                                                                                                                )                                            2                                        2                                                                                                                          =                                                μ                  0                                ⁢                                  C                  ox                                ⁢                                                      W                    L                                    ·                                                                                    (                                                                              V                            DD                                                    -                                                      V                            data                                                    +                                                                                                                V                                                              t                                ⁢                                                                                                                                  ⁢                                3                                                                                                                                          -                                                                                                                V                                                              t                                ⁢                                                                                                                                  ⁢                                1                                                                                                                                                                )                                            2                                        2                                                                                                          (        2        )            wherein:
IDS is the drain current value of the first TFT driver transistor T1 transferred to the OLED diode OL;
Vdata is the input voltage signal or datum; and
VGS1, Vt1, COX, μ0, W and L are, respectively, the voltage value between the gate and source terminals, the threshold voltage values, the capacity by surface unit, the mobility of the charge carriers, the gate width and length of the first TFT driver transistor T1; and
Vt3 is the threshold voltage value of the second TFT discharge transistor T3.
If the electric characteristics of the first TFT driver transistor T1 and of the second TFT discharge transistor T3 are rather similar, |Vt1|≈|Vt3| can be supposed; the drain current IDS will thus have the form:
                                                    I            DS                                    =                              μ            0                    ⁢                      C            ox                    ⁢                                    W              L                        ·                                                            (                                                            V                      DD                                        -                                          V                      data                                                        )                                2                            2                                                          (        3        )            
From the equation (3) it thus emerges that the driving circuit 3 allows to obtain a drain current value IDS independent from the threshold voltage Vt1 of the first TFT driver transistor T1.
However, the correct operation of the circuit is based on the assumption that the transistors T1 and T3 have the same threshold voltage, condition, which can be hardly obtained in the practice.
J. C. Goh, H. J. Chung, J. Jang and C. H. Han in the article entitled: “A New Pixel Circuit for Active Matrix Organic Light Emitting Diodes”, IEEE ELECTRON DEVICE LETTERS, VOL. 23, NO. 9, September 2002 thus have proposed a further driving circuit able to solve this problem. This driving circuit is schematically shown in FIG. 4, globally indicated with 4, using four TFT N-channel transistors, or n-TFT and two capacitors.
The driving circuit 4 has an input terminal IN4 receiving an input voltage signal Vdata and an output terminal OUT4 connected to a OLED diode, always indicated as OL, in turn connected to a first voltage reference, in particular a ground GND.
As previously seen, the driving circuit 4 comprises a first TFT driver transistor T1, inserted between the output terminal OUT4 and a second voltage reference, in particular a supply voltage reference VDD, and a second TFT selection transistor T2, inserted between a control or gate terminal of the first TFT driver transistor T1 and the input terminal IN4 and having in turn a control or gate terminal receiving a first select voltage signal Vsel1.
The driving circuit 4 also includes a third TFT selection transistor and a fourth TFT selection transistor, respectively T3 and T4, inserted, in series with each other, between the output terminal OUT4 and the input terminal IN4 and having respective control or gate terminals, the first receiving a signal Vsel1 and the second receiving a select voltage signal Vsel2.
The driving circuit 4 further includes a storage capacitor Cs inserted between an inner circuit node X4 of interconnection between the third and fourth TFT selection transistors, T3 and T4, and the supply voltage reference VDD, as well as a bootstrap capacitor Cb, inserted between the gate terminal of the first TFT driver transistor T1 and the inner circuit node X4.
The driving circuit 4 provides a Timing diagram divided into three periods:
(1) a first initialization period;
(2) a second compensation period, and
(3) a third data-input period.
The waveforms relative to this Timing diagram are shown in FIG. 5.
In the initialization period, the first and the second select voltage signals, Vsel 1 and Vsel2, are led to a first voltage value or high value, enabling all the three TFT selection transistors T2, T3 and T4 and thus realizing the discharge of the bootstrap capacitor Cb.
In the compensation period, while the first select voltage signal Vsel1 is maintained at the high level, the second select voltage signal Vsel2 is led to a second value or low value causing the opening of the fourth TFT selection transistor T4. Moreover, thanks to the modulation of the input voltage signal Vdata which is led to an intermediate value, next to the value of the threshold voltage of the first TFT driver transistor T1, the operation of the first TFT driver transistor T1 is forced to the underthreshold region. In this way, the voltage value between the gate and source terminals of this first TFT driver transistor T1, equal to Vt1, is applied to the electrodes of the bootstrap capacitor Cb and preserved for the last fraction of the frame time, i.e., the data-input period.
In particular, in this data-input period, the first select voltage signal Vsel1 is led to the low value, while the second select voltage signal Vsel2 is led to the high value, causing the opening of the second and third TFT selection transistors, T2 and T3 and the closing of the fourth TFT selection transistor T4. Moreover, the electric information is applied to the input voltage signal Vdata on the basis of the changes introduced.
In this way, the voltage at the gate terminal of the first TFT driver transistor T1 is equal to Vdata+Vt1, and the drain current IDS is given by the relation:
                                                                        I                DS                            =                                                μ                  0                                ⁢                                  C                  ox                                ⁢                                                      W                    L                                    ·                                                                                    (                                                                              V                                                          GS                              ⁢                                                                                                                          ⁢                              1                                                                                -                                                      V                                                          t                              ⁢                                                                                                                          ⁢                              1                                                                                                      )                                            2                                        2                                                                                                                          =                                                μ                  0                                ⁢                                  C                  ox                                ⁢                                                      W                    L                                    ·                                                                                    (                                                                              V                            data                                                    +                                                      V                                                          t                              ⁢                                                                                                                          ⁢                              1                                                                                -                                                      V                                                          t                              ⁢                                                                                                                          ⁢                              1                                                                                                      )                                            2                                        2                                                                                                                          =                                                μ                  0                                ⁢                                  C                  ox                                ⁢                                                      W                    L                                    ·                                                            V                      data                      2                                        2                                                                                                          (        4        )            
From the equation (4), it occurs that the driving circuit 4 obtains a drain current value IDS independent from the threshold voltage Vt1 of the first TFT driver transistor T1.
This solution, however, shows an important limit, due to the fact that its correct operation is tied to the application, during the second compensation period, of such a voltage intermediate value as to put the first TFT driver transistor T1 in the underthreshold region. Given the impossibility to realize all the TFT transistors present in the driving circuit of a matrix of pixels with the same electric characteristics, it is thus difficult that the voltage intermediate value applied in this period can ensure, for all the driver transistors, a correct operation under the underthreshold condition.
The technical problem underlying the present disclosure is that of devising a driving circuit for a display of the AM-OLED type, having such structural and functional characteristics as to obtain a driving current value independent from the threshold voltage variations of the TFT transistors contained therein, overcoming the limits and the drawbacks still affecting the circuits realized according to the prior solutions.