In the semiconductor fabrication technology, the capability and effectiveness of performing a failure analysis on a semiconductor chip package are very important. When an integrated circuit (IC) chip fails in service, the nature and the cause for such failure must be determined in order to prevent the reoccurrence of such failure in similar products.
An IC chip is normally built on a silicon base substrate with many layers of insulating materials and metal interconnections. This type of multi-layer structure becomes more important in modern IC devices such as high density memory chips where, in order to save chip real estate, the active device is built upwards in many layers forming transistors, capacitors and other logic components.
When an IC device is found defective during a quality control test, various failure analysis techniques can be used to determine the cause of such failure. Two of the more recently developed techniques for performing failure analysis are the infrared light emission microscopy and the light-induced voltage alteration (LIVA) imaging technique. In the infrared light emission light analysis, an infrared light transmitted through a substrate silicon material is used to observe from the backside of an IC the failure mode of the circuit. For instance, at a magnification ratio of 100x, a failure point in the circuitry can be located. The LIVA imaging technique can be used to locate open-circuited and damaged junctions and to image transistor logic states. The LIVA images are produced by monitoring the voltage fluctuation of a constant current power supply when a laser beam is scanned over an IC. A high selectivity for locating defects is possible with the LIVA technique.
Another method that has become more common in failure analysis of IC chips is the scanning optical microscopy (SOM). The high focusing capability of SOM provides improved image resolution and depth comparable to conventional optical microscopy. It is a useful tool based on the laser beam's interaction with the IC. The SOM technique enables the localization of photocurrents to produce optical beam induced current image that show junction regions and transistor logic states. Several major benefits are made possible by the SOM method when compared to a conventional scanning electron microscopy analysis. For instance, the benefits include the relative ease of making IC electrical connection, the no longer required vacuum system and the absence of ionizing radiation effects.
Regardless which one of the failure analysis techniques is adopted, an IC chip package must be properly prepared with a suitable surface for performing a failure analysis. Since most modern IC chips utilize at least two or more layers of metal thin films as interconnect layers, the active components of the chip on which the failure analysis is to be performed are usually shielded by the metal interconnect layers. Great difficulties are encountered in performing any of the failure analysis techniques, i.e. the infrared light emission microscopy, the LIVA imaging technique or the SOM technique, which cannot penetrate the layers of metals to detect the failure mode in the circuit. In another more recently developed package for IC chips, the lead-on-chip (LOC) package, both the lead frame and the bounding wires are positioned on top of the IC circuit. The LOC package has been used in modern high density memory devices wherein a plurality of finger leads are disposed on and attached to an active surface of an IC chip. The benefits of using a LOC package is that the ratio between the size of an IC chip and the size of a package (which encapsulates the chip) is significantly higher than conventional packages since the mounting area (die pad) is no longer required in a LOC package. A high ratio between the chip size and the package size is very desirable in the ever increasing miniaturization of IC devices. Since a metal lead frame is used in a LOC package which substantially covers the active device, it would not be possible to perform a failure analysis on the top surface of a LOC package.
Attempts have been made by others to perform failure analysis on the back surface of an IC chip package. For instance, the back surface of an IC chip package can be polished away to remove the encapsulating material and to expose the die back. A problem in such an approach is that the pin leads connecting the IC circuit can be easily damaged during the polishing process. As a result, the damaged pin leads cannot be electrically connected by soldering to a printed circuit board or by clamping to a test socket. As a consequence, a bias voltage which is required for performing the failure analysis cannot be applied to the circuit. The problem of making an electrical connection to the circuit to be tested therefore renders the performance of a failure analysis impossible.
It is therefore an object of the present invention to provide a method and apparatus for conducting a failure analysis on an IC chip package that do not have the drawbacks and shortcomings of the conventional method and apparatus for performing failure analysis.
It is another object of the present invention to provide a method and apparatus for conducting a failure analysis on an IC chip package that is capable of performing such test on a chip which has multiple layers of metal films built on the chip as interconnect layers shielding the active components.
It is a further object of the present invention to provide a method and apparatus for conducting a failure analysis on an IC chip package that can be performed on packages wherein a lead frame and a multiplicity of bonding wires are positioned on top of the active components.
It is another further object of the present invention to provide a method and apparatus for conducting a failure analysis on an IC chip package wherein the package can be mounted in a printed circuit board equipped with a recess or an aperture.
It is yet another object of the present invention to provide a method and apparatus for conducting a failure analysis on an IC chip package wherein electrical connections can be made between the IC chip and a printed circuit board prior to a surface preparation process.
It is still another object of the present invention to provide a method and apparatus for conducting a failure analysis on an IC chip package wherein the backside surface of the package can be removed by mechanical means without substantially damaging the electrical connections between the chip and the printed circuit board on which the chip is mounted.
It is yet another further object of the present invention to provide a method and apparatus for conducting a failure analysis on an IC chip package wherein the backside of the package can be prepared for failure analysis by an infrared light emission microscopy technique, a light-induced voltage alteration imaging technique or a scanning optical microscopy technique.
It is still another further object of the present invention to provide a method and apparatus for conducting a failure analysis on an IC chip package wherein a surface layer on the backside of the package can be removed for failure analysis by a light emitting or laser emitting technique.
It is still another further object of the present invention to provide a method of conducting a failure analysis on an IC chip package wherein pin leads on the chip are first connected to terminals on a printed circuit board such that a bias voltage can be applied to the chip after a surface layer on the backside of the package is removed.