The present invention generally relates to semiconductor devices and more particularly to a ultra-fast semiconductor device including a CMOS circuit.
A CMOS circuit is a fundamental device element of high-speed logic circuits and is used in various ultra-fast processors of these days.
A CMOS circuit has a construction of connecting a p-channel MOS transistor and an n-channel MOS transistor in series, and thus, it is necessary that both the p-channel MOS transistor and the n-channel MOS transistor operate at high speed for realizing the desired high-speed operation of the CMOS circuit.
In ultra-fast semiconductor devices of these days, the p-channel MOS transistor and n-channel MOS transistor constituting the CMOS circuit are both subjected to miniaturization to have a gate length of 0.1 μm or less. In fact, MOS transistors having the gate length of 90 nm or 50 nm are already fabricated.
With the semiconductor integrated circuit device that includes such ultra-miniaturized transistors, it is generally practiced in the art to use a so-called STI (shallow trench isolation) structure for device isolation, wherein an STI structure is formed by a process of forming a device isolation trench in a silicon substrate, followed by filling the device isolation trench by a silicon oxide film.
FIG. 1 shows the construction of a typical conventional CMOS device 10 that uses an STI structure.
Referring to FIG. 1, there is formed an n-type well 11N and a p-type well 11P in a silicon substrate 11 having a (100) surface orientation by an STI structure 11S respectively as the device region of the p-channel MOS transistor and the device region of the n-channel MOS transistor, wherein there is formed a gate electrode 13P on the surface of the silicon substrate 11 in the region of the n-type well 11N in correspondence to a channel of the p-channel MOS transistor via a gate oxide film 12P, such that the gate electrode 13P extends in the <110> direction. Further, there are formed a pair of p-type diffusion regions 11p constituting the p-channel MOS transistor in the n-type well 11N at respective sides of the gate electrode 13P.
Similarly, there is formed a gate electrode 13N on the surface of the silicon substrate 11 in the region of the p-type well 11P in correspondence to a channel region of the n-channel MOS transistor via a gate oxide film 12N, such that the gate electrode 13N extends in the <110> direction. Further, there are formed a pair of n-type diffusion regions 11n constituting the n-channel MOS transistor in the p-type well 11P at respective sides of the gate electrode 13N.