For a resistive random access memory (RRAM) or a phase change random access memory (PCRAM), 1T1R (i.e., a transistor and a resistive memory/a phase change memory) array architecture is a common array architecture. Comparing to the array architecture of 1T1R, 2D1R (i.e., two diodes and one resistive random access memory) can have a higher working current, a lower leakage current, and a higher array density.
In the 2D/1R array architecture, the first diode of the two diodes includes a P+ doped region and an n-well. PN junction is formed at the interface between the P+ doped region and the n-well. The second diode of the two diodes includes an N+ doped region and a p-well. PN junction is formed at the interface between the N+ doped region and a p-well. In the 2D/1R array architecture, the n-well of the first diode is used as a bit line, and the p-well of the second diode is used a reset line.
Problems arise, however, the set current and the reset current of the 2D/1R array architecture described above are small.
Therefore, there is a need to provide array architecture of a 2D/1R in which the reset current and the reset current may be increased.
The disclosed devices and methods are directed to at least partially alleviate one or more problems set forth above and to solve other problems in the art.