A bit error rate, also known as a bit error ratio (BER), is a ratio of bits received, processed, and/or transmitted with errors to a total number of bits received, processed, and/or transmitted over a given period of time. A BER is typically expressed as ten to a negative power. If, for example, a transmission has 1 million bits and one of these bits is in error (e.g., a bit is in a first logic state instead of a second logic state), the transmission has a BER of 10−6. The BER is useful because it provides one measurement of the ability of a device to receive, process, and/or transmit bits.
Many devices are designed to receive, process, and then transmit a plurality of bits. An optoelectronic transceiver, for example, receives a plurality of bits in an electrical form and then transforms and transmits the bits in an optical form and/or receives a plurality of bits in an optical form and then transforms and transmits the bits in an electrical form.
To derive a BER for a device under test (DUT), bits transmitted to the DUT are compared to corresponding bits transmitted by the DUT or to corresponding bits in a pattern used to generate the bits transmitted to the DUT. In some applications, the BER of a DUT must be below a defined threshold for the DUT to pass a test.
A Bit Error Rate Test or Tester (“BERT”) is a procedure or device that establishes a BER for a DUT or to otherwise quantify a DUT's ability to receive, process, and/or transmit bits. More specifically, a BERT measures the BER of a transmission (e.g., bits transmitted, received, or processed) over a given period of time by a DUT. An example of a BERT includes, among other components, a serializer/deserializer (“SerDes”) and a clock source fixed to a host board, such as a printed circuit board (PCB), etc. SerDes devices convert parallel bit streams into serial bit streams that change at a multiple of the input, parallel data rate. They may also perform the reverse function of deserializing serial bit streams, by converting them into parallel bit streams that change at a fraction of the serial data rates. Typically, the SerDes produces serial encoded data (e.g., the bits) used to establish a BER for a DUT. More specifically, serial encoded data is transmitted from a SerDes to a DUT, which attempts to transmit the serial encoded data back to the SerDes. The SerDes compares the output of the DUT to the input to the DUT (or what the input should have been), to establish a BER.
High-speed input/output (I/O) interfaces embedded in communication devices approach Terabit bandwidth. The architecture allowing this bandwidth boost is based on a parallel arrangement of SerDes cells running at data rates of several Gigabit per second and performing an independent serial data transmission on each lane in parallel (SerDes multilane interface). Gigahertz SerDes devices have gained more and more applications. They are being implemented in devices from high end microprocessors, to high volume low end wireless base bands.
However, economic production testing of such interfaces and SerDes devices imposes a significant challenge. Instrument based solutions are typically costly and slow and the test approach of using a simple loop back between transmit and receive portion of the SerDes typically does not cover faults resulting from data signals exposed to intersymbol interference (ISI) while being transmitted via transmission lines or cables.
A SerDes lane is generally comprised of a Transmit-Receive (Tx-Rx) pair. Nearly all lanes have Built In Self Test (BIST) designs for looping back Tx to Rx with pseudo-random binary sequence (PRBS) and other repetitive patterns for production testing. However, internal or external loop back alone is typically not enough to screen poor performing devices. External signal conditioning, such as ISI injection, is typically required to verify Rx input eye and equalization.
The ability to inject ISI into the data stream is key to characterization and test of SerDes devices. ISI happens due to the low pass nature of transmission line. When alternate 1's and 0's are present in data, the received signal has a shorter time to reach the maximum level, as compared with the consecutive 1β or 0's, in which the received signal pattern can reach higher voltage levels. These changes of signal amplitudes may cause the Phase Lock Loop (PLL) to vary in frequency. Further, harmonics travel with different speeds over transmission line due to their frequencies and so reach the receiver at different moments. This is why pre-emphasis at driver and equalization at receiver is helpful to reduce ISI.
Timing jitter injection has been used by some Automatic Test Equipment (ATE) manufacturers to evaluate the ability of a device to compensate for the interconnect bandwidth, but the effects are typically totally different from using ISI injection. Proper shaping of the frequency response of input buffers can compensate for rolloff in interconnect but not for random jitter. Even if variable timing is induced to emulate the effects of interconnect rolloff, the effect is different from inducing both the phase and amplitude characteristics of the ISI filter.
One method for ISI injection is to use a set of traces in transmission line (such as FR4) and provide a means to select the desired length with a multiplexer. The market requirement is increments of 6 inches. The approach using FR4 transmission line requires considerable space, and it is typically prone to crosstalk and typically requires a large fan-out and multiplexer to realize. The varactor only approach reasonably covers only about 20 to 40 inches of FR4, and thus typically has a limited range of emulation.