1. Field of the Invention
This invention relates generally to electronic circuitry and, more particularly, to translation of electronic signaling levels in integrated circuits.
2. Description of the Related Art
The following descriptions and examples are given as background information only.
The transmission of data involves sending and receiving data over a transmission path, or transmission medium. The transmission medium is generally coupled between a pair of transceivers, each of which preferably has a receiver and a transmitter. The receiver receives data from the transmission medium, and the transmitter drives data onto the transmission medium.
Numerous transmission protocols have been established for sending and receiving data across a transmission medium. For example, IEEE Std. 1596 specifies a protocol for sending differential signals across a transmission path to achieve a relatively high transfer rate, yet maintaining the benefits of common-mode rejection. The universal serial bus, or USB, is specified by the USB Revision 2.0 Specification available from, for example, “www.usb.org/developers/docs.” Both of these standards utilize differential signals, alternatively known as low voltage differential signals (LVDS). In many instances, LVDS signals have voltage swings that are as low as 100 mV.
Although LVDS transmission can utilize small voltage swings and good noise cancellation characteristics useable for applications over long transmission media, the differential signals must be translated at the receiver so that the voltage levels are recognizable to the logic circuitry at the target location. In many instances, the target circuitry operates at MOS, BiCMOS, and Bipolar voltage levels, all of which are at a much higher voltage level than the differential signal voltage swing. The LVDS must, therefore, be converted or “translated” to the higher voltage swings of the core circuitry in order for the destination device to operate on the incoming data. While bipolar and BiCMOS technologies are often used, CMOS active devices in the destination core can save considerable power over other technologies.
It would be desirable to translate the differential signals to CMOS levels at the receiver, but would be even more desirable to perform the translation without significant jitter at the transitional edges of the incoming data stream. As used herein, jitter is generally referred to as an inconsistent, temporarily displaced transitional edge of a signal. For example, if a translator imparts greater delay when converting a rising edge of a differential signal to a rising edge of a CMOS signal than to a falling edge, the translator output will experience jitter. Essentially, jitter appears whenever the delay between rising and falling edges of a translated signal is inconsistent, or momentarily fluctuates over time. Descriptions of the effects of jitter on the duty cycle of a CMOS-translated signal is best illustrated in the examples of FIGS. 1 and 2.
FIG. 1 illustrates a receiver 10 coupled to receive differential signals sent over a transmission media 12. The differential signals can be fed into a termination resistor 14, for example. Termination resistor 14 produces the appropriate voltage differential at, for example, the output of amplifier 16. Amplifier 16 can therefore produce the appropriate output voltage levels into core logic 18. As data is being received by core logic 18, the data may have certain transitional edges from which a clock can be recovered by clock recovery circuitry 20. In order to accurately recover the data and clock transitions, it is imperative that the translation functions within receiver 10 be consistent for all transitions illustrated in FIG. 2.
FIG. 2 illustrates the incoming differential signal 20 and the translated signal 22. The LVDS can be amplified to a much higher voltage swing, as shown. In the case where the differential signals follow the USB specification, the time lapse between transitions (t1) can be as low as 1.2 ns. In order for the translated signal 22 to avoid jitter and duty cycle distortion, the time lapse (t2) between transitions of signal 22 must consistently match t1 for all transferred data. Conventional translator circuitry introduce inconsistent time delay at td1 across differing transitional edges of signal 22. The inconsistency is due, in part to changes in temperature and voltage at which the translator operates. Inconsistency can also be caused by changes in processing, i.e., fabrication of one translator from that of another—each made from differing wafers processed slightly different from one another.
Recognizing that the translator will impart delay between a transition of the incoming differential signal to the amplified output signal, to avoid jitter and ensuing duty cycle distortion, the amount of delay on both the rising and falling edges must be consistent and equal. In other words, td1 must equal td2 for each transition.
An unfortunate aspect of conventional differential-to-full rail translators is that jitter and duty cycle distortion occurs during translation. A common method of implementing differential-to-full rail translation involves a standard single-ended output operational amplifier differential pair. The operational amplifier typically uses positive feedback to maximize gain, followed by an optional level shifting stage. The level shifter stage will then feed the level shifted voltage into an inverter to “square-off” the incoming signal. Unfortunately, however, the translating inverter, or the square-off inverter, has a trip point that is a strong function of process, voltage and temperature. Thus, a conventional translator will then introduce jitter at td1 and td2, causing duty cycle distortion when tested across process, voltage, and temperature variances.
When describing duty cycle distortion, it is often helpful to think of distortion as the outcome of jitter at four different points in time. First, jitter can occur between the positive edge of the differential signal to the positive edge of the translated true signal. Second, jitter can occur from the positive edge of the differential signal to the negative edge of the translated complementary signal. Third, jitter can occur from the negative edge of the differential signal to the negative edge of the translated true signal. Fourth, jitter can occur from the negative edge of the differential signal to a positive edge of the translated complementary signal. As the delay varies during data transfer in either of these four instances, jitter will occur and be recognized as a duty cycle distortion on the output signal.
A more idealized translator is needed that can achieve differential-to-full rail translation without duty cycle distortion. Moreover, it would be desirable to implement a translator that can achieve full rail output recognizable to CMOS core logic. A distortion-less duty cycle that is desirable is therefore one which can have the same delay over all four instances, consistent across all types of data and clock signals being transferred. Moreover, the distortion-less duty cycle that is desired must also be one that can be reliably achieved even though manufacturing process change, or operating temperature and voltage change over time.