1. Technical Field
The present invention relates in general to data storage systems, and more specifically, to data storage systems having a cache unit either within or without a processing unit. Additionally, the present invention relates specifically to a data storage system having a cache unit with memory coherency maintained by an improved snooping scheme.
2. Description of the Related Art
Many computer systems today include several levels of memory storage that attempt to fill the conflicting needs of the computer system. For example, computer systems are designed to operate very fast and memory is needed to operate at the same speed as the processing unit used within the computer system. Unfortunately, the cost of fast memory elements approach those of the cost of the microprocessor itself, thus, driving up the cost of the system overall if the fastest memory available is to be used. A compromise is to use slower but less expensive memory units for specific applications. One such application is to use slower dynamic ram memory for holding information temporarily before the processor unit needs to use it. Another alternative is to use a fast, but small and expensive, caching unit that operates at the same speed as the processing unit. Since this caching unit is small in comparison to the larger short-term memory, it is inexpensive to add with respect to the overall cost of the computer system. Lastly, a very large long-term storage unit is usually supplied, such as a hard disk drive, which is relatively inexpensive compared with the other types of memory.
Unfortunately, having different types of memory and different sorts of memory locations causes management problems for the memory controller to maintain the most current and accurate data needed or processed by the processing unit or any other resource connected to the computing system, such as a peripheral device. Accordingly, the processing system must maintain memory coherency among the various types of memory units used.
The primary objective of a coherent memory system is to provide the same image of memory to all devices using the system. Coherency allows synchronization and cooperative use of shared resources, otherwise, multiple copies of a memory location, some containing stale values, could exist in a system resulting in errors when the stale values are used. Each potential bus master within the system must follow rules for managing the state of its cache.
One type of cache coherency protocol is a coherent subset of the standard MESI four-state protocol that omits the shared state. Since data cannot be shared, the processor signals all cache block fills as if they were write misses (read-with-intent-to-modify), which flushes the corresponding copies of the data in all caches external to the processor prior to the processor's cache block fill operation. Following the cache block load, the processor is the exclusive owner of the data and may write to it without a bus broadcast transaction.
To maintain this coherency, all global reads observed on the bus by the processor are snooped as if they were writes, causing the processor to write a modified cache block back to memory and invalidate the cache block, or simply invalidate the cache block if it is unmodified.
One problem when there is a multiplex bus is that no snoop cycles can be performed during a read transaction. For example, in a dual bus architecture, having a system memory controller, the system memory controller has to wait for the completion of the current read transaction of a master one bus. Then, the memory controller allows another master connected to the second bus to access system memory to ensure memory consistency or coherency.
Accordingly, what is needed is a bus protocol for a processing system having a multiplexed bus and more than one bus master or a dual bus memory controller that controls coherency by providing snoop operations during a data phase or read transaction.