1. Field of the Invention
The present invention generally relates to a system for detecting and reporting defects in a chip. Specifically, the present invention provides a chip having a set of functional chiplets and an operational chiplet that are designed to detect and report errors and/or hang conditions to a host processor.
2. Background Art
In current computer chip designs, defects (e.g., error or hang conditions) found during validation of the chip design are extremely difficult to diagnose and fix. In cases where a defect is found, it can typically be debugged only by analyzing signals from within the chip itself after the signals have been gated to the input/outputs (I/Os) of the chip or through a host processor. However, since only a limited number of I/Os are used for the debug process, a limited number of signals are available to the designers to diagnose the defect. The signals that are present are analyzed by connecting either a scope or logic analyzer to the chip and rerunning the failing operations repeatedly to determine (if possible) the cause of the defect. In cases where the chip hangs, it is significantly difficult to analyze the problem since the internal logic of the chip often becomes unresponsive and therefore limits the ability to check internal register values.
These problems are compounded by the fact that any one chip could have been designed by several designers. For example, a chip can include one or more “functional” chiplets that each performs several functions. To this extent, each functional chiplet could have been designed by multiple designers. To debug a defect, each designer must look at the signals generated by his design, and determine whether it is causing the defect. For example, assume there were twelve signals generated for debugging a defect. Further assume that signals 1-4 pertain to designer “A's” design, signals 5-8 pertain to designer “B's” design, while signals 9-12 pertain to designer “C's” design. Typically, each designer must individually analyze their own set of signals to determine whether his design is causing the defect. That is, designer “A” cannot usually analyze designer “B's” signals or vice versa. Also, designers cannot usually analyze their respective signals concurrently. Thus, debugging of a defect could not only be hampered by the limited amount of information available, but also by the availability of the designers.
In view of the foregoing, there exists a need for a system for detecting and reporting defects in a chip. Specifically, a need exists for each functional chiplet within a chip to include a design that allows defects to be efficiently detected. A further need exists for the chip to include an operational chiplet that communicates with the functional chiplets. Still yet, a need exists for the operational chiplet to analyze signals, and report any defects in the functional chiplets to a host processor.