A serial data system consists of a transmit circuit for transmitting data bits on a serial link to a receive circuit. Most receive circuits include a Clock-Data Recovery (“CDR”) circuit to synchronize the receive sampling clock with the incoming serial data. A CDR actively looks for transitions in the incoming serial data stream and phase aligns sampling clock edges with respect to the incoming data transitions to provide maximum setup-hold timing margins.
An objective of a receive circuit in a serial link system is to capture the incoming data stream without any errors. In a synchronous system, the incoming data can be broken up into discrete bits with respect to time (see ‘din’ in FIG. 2) with each bit contained within the same period (i.e. bit time). To receive the data in an accurate manner, it is desirable to sample each data bit in the center of each bit's respective bit time. These sample points can be represented as rising and falling edges from a periodic waveform or clock signal (see ‘dClk’ in FIG. 2). Assuming that this data sampling clock has the same (or close to the same) transition or bit time as the data (i.e. frequency), a circuit is needed to time or phase shift the edges of the sampling clocks to the center of the data's bit time since this relationship between data and sampling clock edges is unknown. Hence the need for a CDR unit which recovers the sampling clock from the incoming data transitions to place the rising and falling edges of a clock signal in the middle of a bit time. By placing the edges of a clock signal in the middle of a bit time, the maximum amount of timing margin (or setup/hold margin) is developed for each bit and a CDR is considered ‘phase locked’ to the incoming data.
At the same time, the receive circuit may also have a circuit to provide a Built-in-Self-Test (“BIST”) as described in the above-referenced patent application. A BIST circuit may sample the serial data in order to obtain representations of incoming signals or waveforms for system margining purposes. The timing requirements, however, of the sampling clock edges for obtaining waveforms by a BIST circuit conflict with the timing requirements to synchronize the clock edges with the incoming serial data.
To perform a system margining test as described in the related patent application, it may be necessary to phase shift the sampling clock edges with respect to the received data stream. However, as the sampling clock is shifted off the ‘phase locked’ position, the CDR loop will not get the proper phase information from the data samples leading to erroneous tracking information for the receive circuit.
Therefore, it is desirable to provide a circuit, an apparatus and a method that can synchronize the sampling clock edges with the incoming serial data while at the same time capture representations of waveforms of the incoming serial data. In particular, it is desirable to provide methods with different circuits and setups to allow a CDR to track relative to the incoming data stream; while at the same time allow system margining to take place in the receive circuit.