Memory cells are characterized, inter alia, by their cell size, volatility of the stored information and reading reliability. In this case, there is a desire to develop memory cells which occupy a smaller volume, in order to achieve an increased integration density with the generally known advantages; to replace conventional volatile memory cells such as DRAMs by non-volatile memory cells, and to improve the reading reliability by increasing the signal difference between the binary states (high, low).
Although the present invention is described with reference to phase change memory cells (PC-RAM, phase change RAM), which are also referred to as ovonic unified memory (OUM) cells, the present invention is not restricted to them but relates in general to memory apparatuses and production methods.
One concept of memory cells which is superior in terms of the characteristics mentioned above to conventional memory cells in DRAM, SRAM or flash memory cells, is so-called OUM memory cells, which are also referred to as phase change random access memory (PCRAM). The configuration of a PC-RAM will be described schematically with reference to FIG. 1. A memory cell 4 which is formed from Ge2Sb2Te5 (GST) is arranged between two contact areas 5 and 6. The information in this memory cell 4 is coded in the form of the electrical resistance, with a high resistance corresponding, for example, to a logic zero and a correspondingly low resistance corresponding to a logic 1. The resistivity of GST in the amorphous phase is higher than in the crystalline phase. By heating GST to a crystallization temperature of about 420° C., the GST changes from the amorphous phase state to the crystalline phase state. The reverse process is achieved by heating GST to above its melting temperature of about 620° C., with the amorphous state phase being formed when it is cooled down rapidly. GST is expediently stable for more than 10 years both in the glass phase and in the crystalline phase up to temperatures of 100° C. Memory cells composed of GST are thus suitable for non-volatile memory components which can be read in a simple manner by determination of their resistance. The heat power required to change between the two phases is expediently provided by means of a heating current which flows through the memory cell and is controlled by means of a transistor. In order to achieve the required melting temperature, the transistor must be designed such that it can switch the heating current that is required for this purpose. In this case, it has been found that the dimensions of the corresponding transistor limit the integration density of a memory component.
The heating of the memory cell up to the melting temperature does not take place homogeneously across the memory cell 4. GST is less thermally conductive than the materials surrounding the memory cell in the contact-making areas and in the embedding 2. This means that the edge areas of the memory cell are cooled down by the thermal contact with the embedding 2, while the thermal balance within the memory cell is only to a limited extent, owing to the low thermal conductivity. This means that, if a relatively small current pulse is used for heating, the melting temperature is reached only in an inner area of the memory cell 4. The outer radial edge areas which are in contact with the embedding 2 do not reach the temperature which is required to change to the amorphous phase. This reduces the maximum achievable resistance of the memory cell, since there are low-resistance crystalline edge areas in parallel with the high-resistance inner area that is in the form of glass. This disadvantageously results in a decreased signal difference between the two resistance values of the memory cell, and thus in reduced reading reliability. Because of the problems that have already been explained relating to the integration density of the transistor that controls the heating current, the heating current cannot be increased indefinitely in order to heat the outer areas above the melting temperature.