1. Field of the Invention
The present invention relates generally to a bit clock signal reproducing circuit, and is directed more particularly to a digital bit clock signal reproducing circuit which can stably reproduce a bit clock.
2. Description of the Prior Art
Upon recording or transmitting digital data, if a self-clock modulation system such as PM (pulse modulation), MFM (modified frequency modulation), M.sup.2 FM (modified double frequency modulation) or the like is employed, it is necessary that at a reproducing or receiving site that a bit clock be reproduced at the transition point between 0.fwdarw.1 or 1.fwdarw.0 in a data stream and data is obtained based upon the reproduced bit clock signal.
In the art, a bit clock signal reproducing circuit of analog PLL (phase locked loop) form and of digital PLL form have been used as the above bit clock reproducing circuits.
According to the prior art in bit clock reproducing circuits of the analog PLL type, a bit clock is produced by a voltage controlled oscillator, and the data edge and the bit clock signal are phase-compared with a phase comparator and the compared output voltage is fed through a low pass filter to the oscillator to phase-correct the bit clock output.
According to the prior art bit clock reproducing circuit of the digital PLL form, a master clock with a high frequency is applied to the clock terminal of a counter, and it is then frequency-divided to produce a bit clock signal, and a data edge detecting pulse is applied to the load terminal of the counter to load the counter to a constant value at the data edge, so as to phase correct the bit clock signal.
However, in analog PLL type bit clock reproducing circuits, the free running frequency of the voltage controlled oscillator is astable due to variations of temperature and humidity and hence the phase locked state of the PLL is apt to be released. Also, when reproduction is carried out while the speed thereof is varied, it is necessary that the free running frequency of the voltage controlled oscillator be accurately tracked to the varying speed. However, in practice, this is presently impossible.
The digital PLL type bit clock reproducing circuit is stable for variations of temperature and humidity and other variations. Also, when reproduction is carried out while the speed is varied, the frequency of the master clock can be varied in response to the speed variation, which can be easily accomplished.
According to the analog PLL type bit clock reproducing circuit, the phase of the bit clock depends on the average phase of the data edges, while according to the digital PLL type bit clock reproducing circuit, the phase of the bit clock depends on the instant phase of the data edge. Accordingly, in the digital bit clock reproducing circuit, if fine jitter exists in the data edge due to a peak shift or the like, jitter will be generated in the bit clock signal which has an extremely short or long period.