A nonvolatile memory maintains stored data even though the memory is not powered for a period of time. A read only memory is a memory which contains data that cannot change. Nonvolatile read only memories (often called ROMs) are very useful in computers because they can provide a computer with initial instructions or data when the computer is first powered up. The usefulness of these memories is limited however because the data in a ROM memory can only be programmed once. This means that the entire ROM memory must be discarded when the initial instruction set or data is changed.
Nonvolatile programmable memories (often called PROMs) are memories in which the stored instructions or data can be changed without discarding the entire memory. Typical prior art PROMs electrically store charge in the gate structure of a field effect transistor (FET) device, which has the effect of turning "on" or "off" the FET and, in turn, programming the memory. The stored charge is usually removed from the FET gate structure by shining ultra-violet light on the gate structure. The removal of the charge in this manner erases the programming without physically damaging the memory so that it can be reprogrammed. This type of programming and erasing of the PROM is a time consuming and difficult process, so it is impractical to erase and reprogram such a device frequently.
However, PROMs which are both electrically erasable as well as programmable are practical to erase and reprogram frequently, and as a result, are very useful in computers or electrical devices where power is frequently interrupted. This is because the data and instructions the computer was processing can be stored when the power is interrupted and recalled when power is restored.
Electrically erasable programmable memories (often called EEPROMs) were developed in response to the need for a nonvolatile memory which could have the stored data changed on a frequent basis. FIG. 1a illustrates an example of a prior art EEPROM cell in cross-section. The EEPROM cell is a conventional FET having a source region 14, a drain region 16, a channel region 4 and a control gate region 10 separated from the source, drain and channel by an oxide layer 8, but an additional gate region 6 has been added (a floating gate) as well as an additional oxide region 12 between the floating gate and the channel region.
An additional transistor is required together with this or a group (block) of these transistors in order to isolate this or the block of memory elements from others that are being read or written. FIG. 1b illustrates a prior art read and write circuit for the EEPROM shown in FIG. 1a. An array is organized into columns of devices connected to individual bit lines 18, 18' and rows of devices connected to individual word lines 20. A Write operation involves injecting carriers (either electrons or holes) into the floating gate region. This is accomplished by biasing the control gate positively (or negatively for a P channel device) and grounding the source and the drain. This injects electrons (or holes for a P channel device) from the channel into the floating gate region. Negative charge in the floating gate region of an N channel device raises the threshold voltage of the N channel device, while holes in the floating gate region of a P channel device raises the threshold of the P channel device.
An Erase operation involves removing electrons (or holes for a P channel device) from the floating gate and requires positive voltage (or negative voltage for a P channel device) to be applied to the drain, a floating source, and a grounded control gate and substrate. By using a thick enough tunnelling oxide, Read operation, which involves small voltages, does not disturb the threshold voltage of a device.
The problem with these prior art EEPROM devices is that there are limitations as to how many times a charge can be injected and removed from the floating gate. This is because of hot carrier induced reliability problems. To maintain nonvolatility, relatively thick oxides (about 100 Angstroms) are required for the tunnelling oxides. This requires large voltages to be applied for injection, by Fowler-Nordheim tunnelling, of electrons or holes. This produces hot carriers, and hot carriers cause degradation of the oxide due to formation of traps, reactions at interfaces, and diffusion of species released during relaxation of hot carriers at interfaces. Large voltages, exceeding 10 volts, are currently required to charge and discharge the floating gate region through the tunnelling oxide. This requires on-chip generation of these voltages or an additional power supply. Additionally, charging and discharging times are still in milli-seconds because of the small currents flowing through the insulating tunnelling oxide.
An alternate prior art method for increasing the retention time of data in an EEPROM without raising the charging voltage is to replace the floating gate with a charge trapping layer. In particular, charge trapping layers have been formed of silicon nitride and silicon clusters, a plurality of silicon dioxide layers interposed between a plurality of silicon nitride layers, silicon nitride, or non-stoichiometric silicon oxide. The trapping layers are intended to retain the charge injected into the trapping layers. The problem with this particular technique is that carriers are injected into the trapping layers again by Fowler-Nordheim tunnelling through the oxide covering the channel region due to the applied electric field. Controlling the thickness and stoichiometry such that these characteristics are met is a difficult process. The number of times one can charge and discharge, the slowness of the charging and discharging process, and the large powers needed (because of large voltages required) places constraints on the use of all these devices in a vast variety of memory applications.