A programmable logic device (PLD) is an integrated circuit that is purchased by a user in an unprogrammed state, and then programmed by the user to implement the user's circuit design. PLDs typically include blocks of logic elements and interconnect resources that are programmably controlled by associated memory cells. PLDs are typically programmed using a device programmer and place-and-route software installed in a personal computer or workstation. The user enters the circuit design and information regarding a target PLD into the computer/workstation. The place-and-route software then "maps" the user's circuit design by assigning portions of the circuit design to selected logic element blocks of the target PLD, and assigning signal paths (nets) linking the portions to selected interconnect resources. A mapping solution is then generated that contains information regarding the on/off states of all memory cells of the target PLD. Some PLD types are programmed with the mapping solution by being placed on the device programmer and transmitting the mapping solution into the PLD from a computer/workstation through the device programmer. In other PLD types, the mapping solution is downloaded to a read-only-memory (ROM) that is accessed by configuration logic of the PLD during start-up. In addition, some PLDs are in-system programmable (ISP) in that they are programmed via serial interface after, for example, being soldered to a printed circuit board (PCB). In each PLD type, the mapping solution is utilized to configure the memory cells of the target PLD such that the target PLD implements the user's circuit design.
Several types of PLDs are currently available, including field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs). FPGAs typically include logic element blocks that are arranged in a matrix and separated by rows and columns of interconnect lines. In contrast, CPLDs typically include logic element blocks that receive input signals from a central interconnect matrix. The present application is primarily directed to CPLDs, but may also utilized in FPGAs and other types of PLDs.
FIG. 1 is a simplified block diagram showing circuitry utilized in some known CPLDs. In particular, FIG. 1 shows an interconnect matrix 100, a blank check circuit 150 and a multi-level voltage source 200.
Interconnect matrix 100 includes columns of first conductors (referred to as wordlines) 110 that are driven by wordline drivers 115, rows of second conductors (referred to as bitlines) 120 that are connected to sense amplifiers 125, and an array of memory cells 130 located between adjacent wordlines 110 and bitlines 120. Wordlines 110 transmit device input signals and feedback signals into interconnect matrix 100. The voltage level of high voltage signals transmitted on wordlines 110 is determined by multi-level voltage source 200. Bitlines 120 are normally maintained at less than system voltage (&lt;Vcc) using relatively weak pull-up devices, and are pulled down when an associated memory cell 130 is turned on. An associated sense amplifier 125 amplifies the voltage level on each bitline 120 (which may vary by tens of millivolts). Each sense amplifier 125 generates a full logic level output signal in accordance with the sensed voltage level. The sense amplifier output signals are transmitted to associated PLD logic, and are also transmitted to blank check circuit 150. Memory cells 130 are typically implemented by re-writable read-only memories (ROMs), such as EPROMs, EEPROMs, flash EPROMs, or flash EEPROMs. Each memory cell 130 includes a control gate connected to a wordline 110, a source connected to a bitline 120, and a drain tied to ground. Each memory cell 130 also includes a floating gate that is programmed/erased by charging/discharging the floating gate using, for example, hot electron injection or electron tunneling. When erased, a memory cell 130 is turned on/off by an associated high/low wordline voltage. Conversely, when programmed, a memory cell 130 is not turned on (i.e., remains turned off) in response to high and low wordline voltage. For example, when memory cell 130(11) is erased, a high voltage on wordline 110(1) turns on memory cell 130(11), thereby connecting the source of memory cell 130(11) to ground and pulling down the voltage on associated bitline 120(1). In contrast, when programmed, memory cell 130(11) remains turned off even if a high wordline voltage signal is generated on wordline 110(1), and associated bitline 120(1) remains high.
Wordlines 110 must be driven at different voltage levels during different operation modes of interconnect matrix 100. By way of example, a voltage level of 10 to 12 volts may be required on wordline 110(1) to program memory cell 130(11), a voltage level of approximately 0 volts may be required to erase memory cell 130(11), and a voltage level of 5 volts may be required during normal operation. In addition, a voltage level of 7 to 8 volts may be used to verify that memory cell 130(11) is programmed, and a voltage level of 3 volts may be used to verify that memory cell 130(11) is erased. These various voltage levels are provided by multi-level voltage source 200.
Memory cell erase verification is performed after all of memory cells 130 of a PLD are erased, which is necessary before the PLD is programmed with a user's circuit design. The PLD may be erased by exposing it to ultraviolet light (e.g. standard UV EPROMs), or may be erased electrically (e.g. flash EPROMs and EEPROMs). With either method, a memory cell erase verification process (referred to herein as a blank check operation) is required to ensure that the erase cycle was successful in completely erasing all of the memory cells 130. A blank check operation is performed, for example, by sequentially applying a reference voltage of 3 volts to each wordline 110, and monitoring the resulting voltage levels on bitlines 120 using blank check circuit 150 in the manner described below. The reference voltage is selected to turn on fully-erased memory cells 130, but insufficient to turn on memory cells 130 that are not fully erased. For example, if the 3 volt reference voltage is applied to wordline 110(1) and memory cells 130(11), 130(21) . . . 130(n1) are fully erased, then all of the bitlines 120(1) through 120(n) will be pulled low. Conversely, if, for example, memory cell 130(11) is not fully erased, then bitline 120(1) will remain high when the reference voltage is applied to wordline 110(1). During the blank check operation, the high and low voltages on bitlines 120(1) through 120(n) are transmitted through sense amplifiers 125(1) through 125(n) to the blank check circuit 150.
As shown in FIG. 1, blank check circuit 150 includes a PMOS device P1 and parallel-connected NMOS devices N(1) through N(n). PMOS device P1 has a drain connected to a common node 155, a source connected to Vcc, a gate connected to ground, and is sized to provide a weak pull-up on common node 155. Each NMOS device N(1) through N(n) has a drain connected to common node 155 and a source connected to ground. In addition, each NMOS device N(1) through N(n) has a control gate connected to the output of an associated sense amplifier 125(1) through 125(n).
During a blank check operation, NMOS devices N(1) through N(n) remain turned off (common node 155 remains at a high voltage level) unless one or more of memory cells 130 are not fully erased, in which case at least one of NMOS devices N(1) through N(n) is turned on (common node 155 is pulled down). For example, if the reference voltage is applied to wordline 110(1) and memory cell 130(11) is not fully erased, then bitline 120(1) remains at a high voltage level. The high voltage level on bitline 120(1) is transmitted through sense amplifier 125(1) to the control gate of NMOS device N(1), thereby turning on NMOS device N(1) and pulling down common node 155. The low voltage level on common node 155 is detected by monitoring circuit 170, which notifies the user that the PLD is not fully erased. Therefore, blank check circuit 150 allows a simultaneous blank check of all memory cells 130 associated with a wordline 110 of interconnect matrix 100 by bringing the wordline 110 under test to the predetermined reference voltage while keeping all other wordlines at a low voltage.
FIG. 2 is a simplified block diagram showing an example of multi-level voltage source 200 that is connected to wordlines 110 through wordline drivers 115. Multi-level voltage source 200 includes a power multiplexer (power MUX) 210 that receives reference voltages from a 12 volt source 220, an 8 volt source 230, a 5 volt source 240, and a 3 volt reference voltage source 300, and also receives two or more control signals 260. In response to control signals 260, power MUX 210 transmits either a 12 volt signal, an 8 volt signal, a 5 volt signal, a 3 volt signal, or a 0 volt signal to wordline drivers 115 via output line 270. Reference voltages (such as the 3 volt reference voltage) are transmitted through a pass transistor in power MUX 210, and are therefore subjected to a threshold voltage drop of approximately 0.7 volts, and up to 2 volts (depending on body effect). Therefore, the voltage sources providing these reference voltages must transmit an input voltage that is approximately one threshold voltage drop above the required reference voltage.
In order to account for the voltage drop introduced by power MUX 210, reference voltage source 300 generates an output voltage of 3.5 to 4 volts. If the output voltage generated by reference voltage source 300 falls below the range of 3.5 to 4 volts, then the reference voltage applied to wordlines 110 may not be sufficient to turn on memory cells 130 (FIG. 1), even if they are properly erased. As a result, blank check circuit 150 may incorrectly indicate that a CPLD is not fully erased, thereby causing the user to repeat the erase procedure or incorrectly assume the PLD has a defective memory cell. For example, a typical memory cell 130 may have an erased threshold voltage Vth(er) of 2.5 volts. If reference voltage source 300 generates an output voltage of, for example, 3 volts, then the reference voltage applied to the memory cell will be approximately 2.3 volts. Because the reference voltage is below Vth(er), the memory cell may not turn on during a blank check operation, and the blank check operation may incorrectly indicate that one or more memory cells 130 are not erased. Incorrect blank check results may frustrate users, which can result in a loss of sales by the CPLD manufacturer. Therefore, it is important for reference voltage source 300 to adjust to variations in Vcc to produce a reliable 3.5 to 4 volt reference voltage.
FIG. 3 is a circuit diagram illustrating prior art reference voltage source 300 that includes programmable circuitry used to adjust for variations in process parameters such that a reliable 3.5 to 4 volt output voltage is generated for use during the blank check operation. Such variations in process parameters commonly arise during the production of CPLDS. For example, if a CPLD is designed to operate on a nominal Vcc of 5 volts (within a 4.5 to 5.5 volt range), then differences in fabrication process parameters may produce a reference voltage from source 300 in the range of 3.0 to 4.5 volts. To adjust for these variations, reference voltage source 300 is provided with programmable circuitry that is selectively utilized to "trim" the output voltage to the required 3.5 to 4 volt level.
Referring to FIG. 3, reference voltage source 300 includes a PMOS device P(31) that connects node 310 to Vcc, and programmable circuitry including several resistance paths that are controlled by control signals 320 to selectively connect node 310 to ground. An associated NMOS device N(31) through N(34) selectively controls each resistance path, and has a different resistance value that is determined by the particular NMOS resistance elements NR(31) through NR(37) located on that path. The resistance paths are selectively connected to node 310 NMOS devices N(31) through N(34), which are controlled by memory cells (not shown) that generate control signals transmitted on lines 320(1) through 320(4). For example, a first resistance path including resistance element NR(31) is connected between node 310 and ground by control signal 320(1) that is applied to the gate of NMOS device N(31). NMOS device N(32) is selectively turned on by control signal 320(2) to connect node 310 to ground along a second path including resistance element NR(32). NMOS device N(33) is selectively turned on by control signal 320(3) to connect node 310 to ground along a third path including serially-connected resistance elements NR(33) and NR(34). Finally, NMOS device N(34) is selectively turned on by control signal 320(4) to connect node 310 to ground along a fourth path including serially-connected resistance elements NR(35), NR(36) and NR(37). Each resistance element NR(31) through NR(37) is an NMOS device having a commonly-connected source and gate, and has a resistance value determined by the size (width and length) of the NMOS device. By controlling the size of each resistance element, the resistance paths provide a variety of resistances that allow adjustment of the voltage level at node 310. For example, if resistance element NR(31) has a width-to-length ratio of 8/4 and resistance element NR(32) has a width-to-length ratio of 2.4/4 (assuming Vcc is 4.5 volts), then the voltage level at node 310 is 2.52 volts if NMOS device N(31) is selected, or 2.70 volts if NMOS device N(32) is selected. Similarly, the resistance elements of the other paths are formed to provide a variety of resistance values for a given Vcc level.
Reference voltage source 300 is typically programmed during tests performed by the CPLD manufacturer before the CPLDs are sold to a user. During these tests, an acceptable range for source 300 is determined, a resistance path is selected, and memory cells (not shown) are programmed to produce control signals necessary to connect the selected resistance path between node 310 and ground, thereby adjusting the output voltage to 3.5 to 4 volts (if possible). Because this adjustment is performed before the CPLD is purchased, this adjustment is typically "transparent" to the user.
A problem with reference voltage source 300 arises when the Vcc power supply of a CPLD is at its minimum value (e.g., at 4.5 volts). When Vcc is at this minimum value, the voltage drop across PMOS device P(31) generates an output voltage that drops below the required 3.5 volts, thereby generating a reference voltage on wordlines 110 that is significantly less that the required 3 volt reference voltage. Specifically, the reference voltage is equal to Vcc-(Vtn+Vtp), where Vtn is the voltage drop introduced by power MUX 210, and Vtp is the voltage drop across PMOS device P(31). Therefore, if Vcc is at 4.5 volts or less, then the resulting output voltage drops below 3 volts, thereby generating incorrect blank check operation results, as described above. This results is an unreliable device that the CPLD manufacturer cannot sell, thereby reducing profit.
Another problem with reference voltage source 300 arises when the CPLD is subjected Vcc fluctuations during use. Typically, the reference voltage is set for a certain Vcc at a particular temperature and process corner. When Vcc fluctuates during use, the trip voltage of the sense amplifiers 125 changes with Vcc. As Vcc drifts upward, the reference voltage must also track Vcc to prevent blank check circuit 150 from incorrectly indicating programmed memory cells.