The present invention relates to a clock-synchronization type logic circuit and more specifically to a precharging type logic circuit containing bipolar transistors and field-effect transistors.
Complementary field-effect transistors (or CMOS) have conventionally been utilizied to realize high-density integrated circuits with low power consumption. The CMOS circuits may be grouped into two categories: static type and dynamic type. Many very large scale integrated circuits use the dynamic type with smaller number of devices.
FIG. 2 shows a circuit configuration of a 2-input NAND circuit, an example of the conventional dynamic logic circuit. In the figure, reference numeral 201 denotes a PMOS transistor, and 202 to 204 NMOS transistors. To the PMOS transistor 201 and NMOS transistor 204 is supplied a clock signal CK and to the NMOS transistors 202, 203 are supplied logic signals A and B, respectively. The output signal OUT is taken from the common connection of the drains of the PMOS transistor 201 and NMOS transistor 202. The capacitance CL to which the output OUT is connected includes the capacitance of wiring and the gate capacitance of the load.
When the clock signal CK is at a "0" level, the PMOS transistor 201 is on and NMOS transistor 204 is off. The output OUT is then precharged to the supply voltage Vcc to become high or arrive at "1" level. In the meantime, if both the input logic signals A and B change to "1" level or go high, the voltage at node N1 will be the supply voltage Vcc and the voltages at nodes N2 and N3 will be Vcc-VthN where the VthN is a threshold voltage of the NMOS transistors 202 and 203. When from this condition the clock signal CK changes from "0" to "1", the PMOS transistor 201 turns off and the NMOS transistor 204 turns on, discharging the charges at the nodes N1 to N3 through the NMOS transistor 204 and causing the output OUT to go low. The relation at that time between the output logic signal OUT and the input logic signal is expressed as follows: EQU OUT=A.multidot.B
FIG. 3 is a time chart showing the operation of the circuit of FIG. 2. In FIG. 3, (a) represents the waveform of the clock signal CK, (b) the input logic signals A and B, and (c) the output signal OUT. In the precharge period from time t0 to time t2, the nodes N1 to N3 are precharged to a level "1". With the input signals A and B both at "1", the nodes starts discharging from time t2 after the precharging period. The MOS transistor has a small current drive capability. So, when the load CL is small the discharging finishes during the period from t2 to t3. But with a larger load the discharging time prolongs lasting from t2 to t4. FIG. 2 shows the example of 2-input NAND circuit and the discharging period will become longer as the number of NMOS transistors connected in series increases, as with 3-input NAND circuit and 4-input NAND circuit. The only available means to reduce the discharging period under a given load CL and a given manufacturing process of a device is to increase the width W of the channel of the MOS transistor. This method, however, results in reduced speed of a drive circuit frustrating the initial aim for higher operation speed since the gate capacitance of the MOS transistor increases with the channel width W.
A BiCMOS logic circuit that resolves the drawback of low current drive capability of the MOS transistor and which also has a low power consumption comparable to that of CMOS transistor is proposed in the European Pat. Publication 0099100 (1/1984). This concerns a high speed static logic circuit with the CMOS logic stage consisting of two output stage bipolar transistors for driving a load, a PMOS transistor and an NMOS transistor. This circuit, however, does not consider a dynamic circuit which is a combination of bipolar transistor and field-effect transistor.
As mentioned above, the conventional MOS dynamic circuit has a disadvantage that the response speed reduces as the load increases, which is a major problem in increasing the operation speed. The conventional BiCMOS logic circuits which are all static and thus complicated in circuit configuration are not suited for logic circuits of snychronization type.