Q:

Implementing logic gates in CMOS

I'm trying to build the below function with CMOS, is my implementation correct?
$$ F =  ABC + (\overline{B+C})D $$
I am having trouble with the $$(\overline{B+C})$$ in all of the examples I've seen the function is in the form $$F = \overline{blablabla}$$ (the inverse of the whole expression).
I gave it a try but I'm not sure if it's correct, for example is it ok to have ~A as input to a PMOS (I don't see why not). 
The correct layout after Dave Tweed pointed out the missing connections on the N-block.
(The added connections are marked with pink)  

A:

Yes, your solution is very nearly correct. Here are the steps, which you really should have shown in your question:
In order to deal with the second top-level term, you need to apply De Morgan's Law, which states:
$$\overline{A \cdot B} = \overline{A} + \overline{B}$$
and
$$\overline{A + B} = \overline{A} \cdot \overline{B}$$
Using this, you can make the following transformation:
$$(\overline{B + C}) \cdot D = \overline{B} \cdot \overline{C} \cdot D$$
This transforms the entire function into:
$$F = A \cdot B \cdot C + \overline{B} \cdot \overline{C} \cdot D$$
which is a normal sum-of-products expression.
In order to implement this in CMOS, however, you need a function that has an overall inversion, so you need to apply the law again:
$$F = \overline{\overline{(A \cdot B \cdot C)} \cdot \overline{(\overline{B} \cdot \overline{C} \cdot D)}}$$
and again (two places):
$$F = \overline{(\overline{A} + \overline{B} + \overline{C}) \cdot (B + C + \overline{D})}$$
Your schematic diagram is correct, but your layout does not quite match it. There are a few missing connections on the NMOS side.

