1. Field of the Invention
The invention relates to design of semiconductor chips. More specifically, the invention relates to a method and an apparatus for generating a plan for adding power pads to a design of an integrated circuit.
2. Related Art
Pads that supply power in an integrated circuit (IC) design can be created in any of a number of different ways known in the prior art. For example, see a paper by M. Zhao, Y. Fu, V. Zolotov, S. Sundareswaran, and R. Panda, entitled “Optimal Placement of Power Supply Pads and Pins,” in Proceedings of Design Automation Conference (DAC), pp. 165-170, 2004. This paper addresses a problem of finding an optimum set of pads, pins, and on-chip voltage regulators (all referred to as “pads”), and their placement in a given power supply network, subject to constraints on the voltage drops in the network and maximum currents through the pads. In this paper, the problem is modeled as a mixed integer linear program using macromodeling techniques and several heuristic techniques are described to make the problem tractable. This paper is incorporated by reference herein in its entirety.
See also another paper by J. Oh and M. Pedram, entitled “Multi-pad power/ground network design for uniform distribution of ground bounce,” in Preceedings of DAC, pp. 287-290, 1998. This paper presents a method for power and ground (p/g) network routing for high speed CMOS chips with multiple p/g pads. Their objective is to distribute ground bounce evenly among the pads while the routing area is kept to a minimum. This paper shows that proper p/g terminal to pad assignment is necessary to reduce the maximum ground bounce and then presents a heuristic for performing simultaneous assignment and p/g net routing. This paper is also incorporated by reference herein in its entirety.
U.S. Pat. No. 6,405,357 granted to Chao, et al. on Jun. 11, 2002 entitled “Method for positioning bond pads in a semiconductor die” is incorporated by reference herein in its entirety. This patent describes (I) setting parameters including (a) setting a baseline pad pitch to a first value, (b) setting a first pad position equal to a first pad value and (c) providing a focal point; (II) determining a first angle between a first line through a center of the first pad position and the focal point and a second line through a center of the semiconductor die and normal to the edge; (III) determining a first pad spacing increment value equal to the first value divided by a cosine of the first angle; (IV) setting a second pad position equal to a second pad value, wherein the second pad value at least equals the first pad value plus the first value if both of the first bond pad and the second bond pad are ground pad or power pad with the same potential, else the second pad value at least equals the first pad value plus the first pad spacing increment value; and (V) using the first and second pad values to respectively position a first bond pad and a second bond pad along the edge of the semiconductor die. Beginning from the bond pad closest to the die corner, optimized positions of bond pads are determined by repeating steps I to V.