As integrated circuits (IC's) have become more and more complex by including more and more functions in them, effectively testing the IC's has become more and more difficult. The more functions the IC chip contains, the larger the number of circuit blocks which it typically has in order to communicate with other devices external to the IC. The circuit blocks that provide this interface function between the core functions of the IC and the outside world are referred to as input/output (I/O) PAD's. PAD blocks are used to drive signals out of the chip and/or receive signals into the chip. These circuit blocks typically contain drivers for obtaining signals from other chip circuitry and driving them out of the chip, receivers for receiving signals from external devices and propagating those signals to other chip circuitry, test circuits, as well as other interface, control, and data manipulation circuitry, such as registers, logic gates etc.
Historically every I/O PAD on an IC was connected to a separate channel in an integrated circuit test machine so that all I/O PAD's on the IC could be accessed by the machine for testing. However, for expense and other reasons an IC tester has only a limited number of channels which in modern very large scale integrated (VLSI) circuits maybe less than the number of I/O PAD's of the chip. Thus, while a complete, or at least substantial, test of the I/O circuitry is still needed, it becomes impossible to perform in practical applications.
This ongoing need to perform more complete testing of integrated circuit chips has been alleviated by including circuitry on the chip itself for performing a large sub-set of the testing. By appropriately interconnecting the PAD's, this built-in self-test circuitry now enables the I/O PAD's to effectively test each other by connecting a tester channel to only one PAD in a related group of PAD's. Typical tests which are performed are (1) driver leg, (2) leakage, (3) receiver trip, and (4) round-trip timing tests.
Driver tests usually include a driver leg test and a leakage test. A typical driver may include multiple parallel control paths referred to as driver legs for pulling the driver up to its higher potential level and for pulling it down to its lower potential level. It is important to be able to individually test each of these legs. Field effect transistors (FET's) are typically used to perform the pull up/pull down functions. In a related test, leakage of current in the FET's off state is also tested. In typical implementations, so-called weak FET's are included in the on-chip test circuitry. These weak FET's are used to compete with the driver pull-up and pull-down FET's for control of the driver's output level. For the leakage test, the FET's are turned off and the weak FET attempts to pull-up and pull-down the driver potential level. Excessive leakage is indicated if the weak FET is unsuccessful.
Receiver tests usually include a receiver trip test and a round-trip timing test. Drivers, as well as the receivers, are tested by the round trip timing test. The receiver trip test determines the input voltage at which the output of the receiver changes or trips from its lower potential level to its higher potential level and/or the input voltage at which it changes from its higher potential level to its lower potential level. Various input voltages are applied to the input of the receiver, and the input voltage at which the output switches from its previous value to that representative of the input voltage is determined with the output of the receiver having been previously placed in its opposite state. For pass/fail test a preselected input voltage is applied, and then it is determined whether or not the output switches.
In the round-trip timing test, two pads are used to test each other. The PAD contacts are shorted together off-chip for this test. In a typical example, data is driven out of the driver of the first PAD on the rising edge of the clock, and the differential receiver output of the second PAD is latched on the falling edge of the clock. The latched data is then compared to the data that was driven out of the first PAD. The outputs of the driver and receiver were previously placed in complementary states to that switched to during this test. The test is repeated for various clock duty cycles while detecting whether or not the receiver switched states. To test the driver on the second PAD and the receiver on the first PAD, the test is repeated by driving data out of the second PAD on the rising edge of the clock and latching the differential receiver output of the first PAD on the falling edge of the clock. For pass/fail testing a preselected clock duty cycle is used. A failure is indicated if the correct data is not latched into the register.
Existing techniques include circuitry for performing these tests on single ended pads. However, they do not have the capability of performing tests on differential pads. Since differential mode circuits are becoming more and more prevalent on IC chips, there is a growing need to provide circuitry capable of testing such functions.