For high-power switching applications, power semiconductor products may often be fabricated using N-channel or P-channel DEMOS transistor devices (e.g. a lateral double diffused MOS (LDMOS) device or a reduced surface field (RESURF) transistor). Drain extended MOS field effect transistors (i.e. a DEMOS transistors) with extended drain regions may attempt to maximize the breakdown voltage (BV) characteristics of the transistor device.
A DEMOS transistor may combine short-channel operation with relatively high current handling capabilities, relatively low drain-to-source on-state resistance (Rdson), and/or the ability to withstand relatively high blocking voltages without suffering voltage breakdown. BV may be measured as drain-to-source breakdown voltage (BVdss) with the gate and source short-circuited together. In some designs, a DEMOS device is designed around a tradeoff between breakdown voltage BVdss and Rdson. In addition to performance advantages, DEMOS device fabrication may be relatively easy to integrate into CMOS process flows, facilitating use in devices where logic, low power analog, and/or other circuitry may be fabricated in a single integrated circuit (IC).
A P-channel DEMOS (DEPMOS) transistor may include a p-type source formed in an n-well, where the n-well includes an n-type channel region between the source and an extended p-type drain. An extended drain may include an n-type drain into which impurity ions are implanted at a high concentration in p-well and a p-type drift region in a p-well extending between a channel region and the drain. Low p-type doping on the drain side may provide a large depletion layer with a relatively high blocking voltage capability. A n-well may be connected by an n-type back-gate connection to prevent or minimize the n-well from floating. Accordingly, a device threshold voltage (Vt) may be stabilized. The drain region of the device may be spaced from the channel (e.g. extended) to provide a drift region and/or an extended drain in the p-type semiconductor material between the channel and the drain. In operation, the spacing of the drain and the channel may spread out the electric field, thereby maximizing the breakdown voltage rating of the device (e.g. facilitate a relatively high breakdown voltage BVdss). However, the drain extension maximizes the Rdson (i.e. drain-to-source on-state resistance). Accordingly, the design of a DEMOS transistor often involves a difficult tradeoff between high BVdss and low Rdson.
DEMOS devices may be widely used for power switching applications requiring relatively high blocking voltages and/or relatively high current carrying capabilities (e.g. when solenoids or other inductive loads are to be driven). In one possible configuration, two or four n-channel DEMOS devices may be arranged as a half or full H-bridge circuit to drive a load. In a half H-bridge arrangement, two DEMOS transistors may be coupled in series between a supply voltage VCC and ground with a load coupled to the ground from an intermediate node between the two transistors. In such a configuration, the transistor between the intermediate node and the ground may be referred to as a ‘low-side’ transistor and the transistor between the voltage source and intermediate node may be referred to as a ‘high-side’ transistor. The transistors may be alternately activated to provide current to the load. A full H-bridge circuit may include two high-side transistors and two low-side transistors with the load being coupled between two intermediate nodes.
In operation, a high-side DEMOS transistor may have a drain coupled to the supply voltage and a source coupled to the load. In an ‘on-state’, a high-side transistor may conduct current from the supply voltage to the load, wherein the source may be essentially pulled up to the supply voltage. Some DEMOS devices may be fabricated in a wafer having a p-doped silicon substrate with an epitaxial silicon layer formed over the substrate. The substrate may be grounded and the source, drain, and channel (e.g. including an n-well and p-well) of the transistor may be formed in the epitaxial silicon layer.
In order to prevent a punch-through current between the p-well and the substrate during the on-state for high-side DEMOS device, it may be desirable to separate the p-well that surrounds the source from the underlying p-type substrate that is grounded. Although the n-well may extend under the p-well, the n-well may only be lightly doped. Therefore, the n-well may not provide an adequate barrier to the on-state punch-through current from the source to the substrate. Accordingly, a highly doped n-buried layer (NBL) may sometimes be formed in the substrate prior to forming the epitaxial silicon layer to separate the n-well from the substrate and may thereby inhibit on-state punch-through current from the p-well to the substrate in high-side DEMOS devices.
A NBL (n-buried layer) may be connected to a drain terminal of the high-side DEMOS device by a deep diffusion or sinker and may be tied to the supply voltage which may prevent the on-state punch-through current. Although the NBL may operate to prevent the on-state punch-through current, the NBL may limit the off-state BREAKDOWN VOLTAGE rating of high-side DEMOS device. In an “off” state, the high-side transistor source may essentially pulled down to ground. The low-side transistor may enter a conductive state and a drain-to-source voltage across the high-side DEMOS device may essentially he the supply voltage VCC. In high-voltage switching applications, the presence of the n-buried layer under the p-well limits the drain-to-source breakdown of the device as the n-buried layer is tied to the drain at VCC. In this situation, the p-well is at ground, since the source is low in the off-state, and the supply voltage (VCC) is essentially dropped across the n-well portion extending between the bottom of the p-well and the n-buried layer and between the channel-side of the p-well and the drain. As the high-side driver is shut off when driving an inductive load, the transient drain-to-source voltage may increase beyond the supply voltage level VCC.
Hereafter, a DEMOS transistor will be described with reference to accompanying drawings. FIG. 1 illustrates full H-bridge driver semiconductor device 2, powered by a DC supply voltage (VCC), in accordance with embodiments. For example, semiconductor device 2 may be fabricated as a single IC having four driver transistors T1 to T4, an external connection for power and gate signals, a load terminal, and/or may selectively provide a connection to an external diode for high-side transistors T2 and/or T3.
As shown in FIG. 1, semiconductor device 2 may include four p-channel DEMOS (DEPMOS) devices T1 to T4 having sources SI to S4, drains D1 to D4, and gates G1 to G4, coupled in an H-bridge to drive a load coupled between intermediate nodes N1 and N2. The transistors T1 to T4 may be arranged as a pair of low-side transistors T1 and T4 and another pair of high-side transistors T2 and T3 which have the load coupled between the intermediate nodes, thereby forming an “H-shaped” circuit. A half bridge driver circuit may be implemented using transistors T1 and T2. In this case, node N2 on the right side of the load may be coupled to ground, whereby transistors T3 and T4 would be omitted. In automotive applications, portable electronic devices and/or other similar device (as mere examples), a supply voltage VCC may serve as a positive terminal of a battery and ground may serve as a negative terminal of the battery.
On the left side of the H-bridge in FIG. 1, low-side transistor T1 and high-side transistor T2 are coupled in series between the supply voltage VCC and the ground. Low side transistor T4 and high side transistor T3 may be coupled in a similar manner. High-side transistor T2 may have drain D2 coupled to supply voltage VCC and source S2 coupled to intermediate node N1 at the load. Low-side transistor T1 may have drain D1 coupled to node N1 and source S1 coupled to ground. Node N1 between transistor T1 and transistor T2 may be coupled to a first terminal of the load and node N2 at the other load terminal may be coupled to the transistor T3 and transistor T4. In some situations, the load is not part of semiconductor device 102. High-side transistor gate G1 and low-side transistor gate G4 may be controlled to drive the load in an alternating manner. When transistor T2 and transistor T4 are turned on, current may flow in a first direction (e.g. the right direction in FIG. 1) through high-side transistor T2, the load, and transistor T4. Similarly, when both transistor T3 and transistor T1 are turned on, current may flow in a second direction (the left direction in FIG. 1) through transistor T3, the load, and low-side transistor T1.
To understand at least one disadvantage of related art DEMOS transistors in applications such as the H-bridge of FIG. 1, FIG. 2 provides a cross-sectional view of semiconductor device 2 having an example high-side DEMOS transistor 3, in accordance with the related art. DEMOS transistor 3 may be coupled to drive a load in a full or half-bridge driver circuit configuration, such as transistor T2 in H-bridge circuit in FIG. 1.
Referring to FIG. 2, semiconductor device 2 includes p-doped silicon substrate 4 having epitaxial silicon layer 6 formed thereon. NBL 20 (n-buried layer) may be positioned in the silicon substrate 4 under the DEMOS transistor 3, and partially extended into the epitaxial silicon layer 6. N-type dopants may be implanted into part of epitaxial silicon layer 6 above NBL 20, thereby forming n-well 8. Field oxide (FOX) layer 10 may be formed in the upper portion of epitaxial silicon layer 6. N-type back gate (BG) 12 and p-type source 14 may be formed in n-well 8 and p-type drain 16 may be formed in p-drift region 6a. A gate structure including gate oxide 18 and gate electrode 20 may be formed over channel region 21 of n-well 8. For illustrative purposes, gate G2, source S2, and drain D2 of high-side DEMOS transistor 3 may be represented as if they are coupled to form the half or full bridge driver circuit as in FIG. 1.
In some driver applications, drain 16 of high-side DEMOS transistor 3 may be coupled to supply voltage VCC and source 14 thereof may be coupled to the load at intermediate node N1. When high-side DEMOS transistor 3 is turned on, both source 14 and drain 16 may be at or near supply voltage VCC. NBL 20 may help to prevent a punch-through current from flowing between n-well 8 and grounded p-type silicon substrate 4 and NBL may be electrically coupled to drain 16 (e.g. VCC). However, when high-side DEMOS transistor 3 is turned off, source 14 is essentially pulled down to ground through the low-side transistor, whereby a drain-to-source voltage across high-side DEMOS transistor 3 substantially corresponds to supply voltage VCC. When high-side DEMOS transistor 3 is switched from the ‘on state’ to the ‘off state’, the drain-to-source voltage temporarily becomes relatively large compared to supply voltage VCC.
At least a portion of the above-described regions may be susceptible to breakdown at higher supply voltages than in the off state of the high-side DEMOS transistor, due to NBL 20 located under p-drift region 6a, wherein the breakdown voltage (BVdss) of a related art high-side DEMOS transistor 3 is relatively low. Therefore, while NBL 20 inhibits on-state punch-through current from p-drift region 6a to silicon substrate 4, the off-state BVdss of high-side DEMOS transistor 3 may be limited by NBL 20.
Without changes in design from the related art discussed above, supply voltage VCC may not be maximized without risk of off-state or transient voltage breakdown. One approach in the related art for maximizing breakdown voltage performance is to reduce the dopant concentration of p-drift region 6a. However, this approach maximizes Rdson, thereby having an adverse effect on an on-state drive current. Another approach in the related art for maximizing BREAKDOWN VOLTAGE performance is to maximize the thickness of epitaxial silicon layer 6. However, as discussed above, when epitaxial layer 6 is formed to a relatively large thickness, the fabrication process may become complex.