This disclosure relates to apparatus and methods of testing and characterizing the electrical integrity of the array and cell properties of semiconductor memories, more specifically 3D or vertical memories. Semiconductor memories ICs are prevalent in the electronics industry today in all kinds of products, consumer as well as industrial. Memories can be broadly categorized into two types, the first is planar (2D) memories and the second is vertical (3D) memories. In 2D memories, all the memory cells are substantially contained on a single plane semiconductor substrate, where as in 3D memories, the memory cells are vertically arranged across multiple layers of semiconductor substrate.
As the consumer electronics products such as cell phones, tablets, laptops become smaller in size, the demand for high density memories increases. That is why in recent times 3D memories have become more popular as those can provide higher densities in smaller sizes compared to their 2D counterparts. In other words, 3D memories allow more memory cells to be contained in a relatively smaller size compared to the 2D memories. Testing and characterization of semiconductor memories is an important phase in the memory process development and manufacturing process. Especially, an early phase testing during technology development can help detect faults in the memory ICs, which can save a considerable amount of money in the long run. Therefore, more and more product manufacturers now demand an early phase testing of memory ICs.