1. Technical Field
The present invention relates to a phase locked loop (PLL) circuit, and in particular, to a spread-spectrum PLL circuit.
2. Related Art
In recent years, as the speed of the SoC (System on Chip) has been increased, problematic electromagnetic interference has become increasingly serious in large-scale integrated circuits and digital household electrical appliances. The spread spectrum control PLL (SS-PLL) is an effective means of reducing electromagnetic interference, which, by performing fine tuning on the frequency of a reference clock signal in an integrated circuit, spreads the spectrum of an output clock signal to reduce electromagnetic interference.
FIG. 1 is a block diagram of a prior art SS-PLL. The SS-PLL, in addition to including a phase-frequency detector (PFD), a first charge pump (CP), a low pass filter (LPF) and a voltage controlled oscillator (VCO), further includes a second CP. The operating frequency of the second CP is lower than that of the first CP. The charge and discharge currents of the second CP are superimposed onto those from the first CP through the LPF, so as to modulate a voltage applied to an input end of the VCO, thereby modulating the frequency of an output clock signal. However, the scheme requires the LPF to satisfy R1*C1=R2*C2. More importantly, as one of input signals of the PFD also contains a component of a modulated signal, the bandwidth of the PLL in the non-spread spectrum mode must be small enough to filter out such a feedback component generated by the modulated signal.
FIG. 2 is a block diagram of another prior art SS-PLL. The SS-PLL modulates a frequency divider therein. Although the scheme has achieved a good effect, the structure is complex.