1. Field of the Invention
The present invention relates to non-volatile memory cells. More particularly, the present invention relates to reduced-edge, radiation-tolerant, non-volatile transistor cells for memories or programmable logic devices.
2. The Prior Art
Reduced edge transistors such as so-called “H-gates” used in regular logic have been employed to increase radiation tolerance of such circuits. A special case of reduced edge transistors is so-called “edgeless” transistors. Edgeless or circle-gate transistors have also been used in logic and other peripheral circuits and charge pumps to eliminate increased leakage due to exposure to ionizing radiation. Although such radiation-hardening techniques have been applied to standard single-polysilicon-gate devices, they have not been applied to programmable non-volatile memories.
Antifuse-based radiation tolerant products available from Actel Corp. of Mountain View, Calif. include edgeless regular and high-voltage transistors to minimize the effects of ionizing radiation. A channel-stop implant may also be introduced under the field edge to suppress leakage, but this requires a specialized process.
Non-volatile transistors used in flash memories are traditionally n-channel transistors with two gates. The upper gate is typically known as the control gate while the bottom gate is known as the floating gate. The floating gate is typically made of conductively doped polysilicon, but it is electrically isolated from the control gate above and the transistor active area below, as well as from all other circuits on the integrated circuit by means of sufficiently thick silicon dioxide. The floating gate can be thought of as a charge storage layer (or charge storage region) interposed between the control gate above and the active silicon region underneath. The terms “charge storage region” and “charge storage layer” are used interchangeably herein, though the former is typically used in this disclosure to emphasize the lateral area of a flash transistor covered by the material while the later is typically used to emphasize the vertical relationships between the layers comprising a flash transistor. Electrical charge is added or removed from the floating gate to effectively change the threshold voltage (sometimes called the turn-on voltage) of the transistor. Typically, since the floating gate is conductive, electrical charges are free to redistribute themselves on the floating gate. As is well known in the art, an n-channel flash transistor uses negatively charged carriers to conduct current in the channel region under the gate when the transistor is turned on by applying a higher voltage on the control gate than is applied when the transistor is turned off. By convention, for n-channel transistors the drain terminal is at the end of the channel region at the higher voltage potential while the source terminal is at the end of the channel region at the lower voltage potential.
More recently as shrinking process geometries have made floating gate non-volatile transistors less area efficient than in previous generation processes, alternative flash technologies like, for example, SONOS (an abbreviation for Silicon-Oxide-Nitride-Oxide-Silicon) and silicon nanocrystals have been introduced as alternative ways to implement the charge storage layer. These technologies typically replace the polysilicon floating gate with a layer of a non-conductive charge trapping material. By adding or removing electrical charge the threshold voltage of the transistor is changed, though the electrical charges are not free to redistribute themselves within the layer of charge trapping material.
Typically flash memories comprise arrays of flash transistors arranged in rows and columns. Often a large array is broken into a number of smaller arrays. Typically in the fabrication process long, narrow strips of active material (silicon) separated by field oxide (silicon dioxide) are laid out in a first direction spanning the array. Then the oxide forming the isolation between the charge storage layer and active silicon (also known as the “bottom oxide”) is grown all over the array area. Next, the charge storage layer is laid down, again all over the array. If the charge storage layer is to be conductive, like a doped polysilicon floating gate, an additional masking step is required to remove strips of the floating gate polysilicon that run parallel to and in between the strips of active silicon. Then the oxide forming the isolation between the charge storage layer and the control gates (also known as the “top oxide”) is grown all over the array, followed by the conductively doped control gate polysilicon layer. A masking step (often called the poly mask since it defines the geometries of the polysilicon conductors) is used to etch away the unwanted portions of the control gate polysilicon layer, the top oxide layer, the charge storage layer, and bottom oxide layer. The etching leaves long, narrow strips of polysilicon conductors spanning the array running in a second direction perpendicular to the long, narrow strips of active silicon running in the first direction. The active regions between the polysilicon conductors are also left exposed by the etch, and the only remnants of the original charge storage layer are aligned with and underneath the control gate polysilicon conductors.
Wherever there is an intersection of the polysilicon conductors and the active silicon, a flash transistor is formed. In floating gate technologies where the charge storage layer is conductive, there is a piece of the floating gate that covers at least the region of the active silicon where the transistor is, although it typically extends beyond the active region and into the field oxide by some amount (this extension is called an endcap). Due to the additional masking step needed to separate the floating gates, there is enough distance between the floating gate endcaps to keep them electrically isolated from one another. In technologies where the charges in the charge storage layer are not mobile, the charge storage layer runs continuously under the control gate polysilicon conductors for their entire length, but since charges in that material are immobile, the portion of the charge storage layer for each transistor is inherently isolated and the extra charge storage material over the field oxide does no harm.
In the next fabrication step, the exposed active silicon is conductively doped. If, for example, the flash transistors are to be n-channel transistors as is typically the case, then an n-type dopant is implanted in sufficient concentration to overcome the intrinsic p-type doping intrinsic to the active silicon. This leaves regions of p-type material in the active under the control gates and n-type material in the exposed active. The doping of the active region is said to be self-aligned because the polysilicon mask and the boundaries of the active material abutting the field oxide are used to define those areas of the active that are to be implanted and those that are not.
After the implantation, a layer of salicide (an abbreviation for Self-Aligned siLICIDE) is typically grown on top of the exposed active regions. This is generally a metal silicide of a type well known in the art. It is conductive, which reduces the sheet resistance of the active region and makes for a better electrical connection between the active silicon and a contact. It is also self-aligned in that the only place the salicide is grown is on the exposed active regions that received the implantation. The contacts will be used to couple the active silicon regions to a metal layer that later will be deposited above the polysilicon conductors used as the control gates. After the implantation and salicide growth, more oxide is grown and contacts, metals and vias are fabricated.
Persons skilled in the art will realize that this is a very simplified description of the semiconductor process that emphasizes the essence of the steps important for understanding the present invention. For example, many steps go into growing and planarizing a single layer of silicon dioxide or polysilicon. Similarly, many steps go into a “mask step” like, for example, covering the wafer with photoresist, aligning the mask to the wafer repeatedly for each integrated circuit location (called stepping), developing the photoresist, etching away the undesired portion of the developed photoresist, etching, cleaning, implanting, growing, etc., as appropriate for the mask step once the mask pattern of the photoresist is in place. The simplified description above is sufficient for the understanding of the present invention by such skilled persons and that the majority of details omitted are for clarity of presentation and to avoid overcomplicating the disclosure and obscuring the inventive aspects therein.
A major challenge using prior art non-volatile transistors in a radiation environment is known as Total Dose. During its lifetime in a radiation environment, a semiconductor is repeatedly hit by charged particles—both negatively charged electrons and positively charged ions of various types. Positive ions tend to become lodged in the silicon dioxide regions of the semiconductor—and are a particular problem in the Shallow Trench Isolation (STI) silicon dioxide areas used to electrically isolate transistors in modern deep-submicron processes. When they lodge at the edge of a transistor channel region (the area under the gate where the channel forms when the transistor is on), their positive charge attracts unwanted electrons into the region. This effectively lowers the threshold voltage of the transistor locally near the edges of the transistor where the STI is located and can cause current leakage along the edge of the transistor. The leakage can cause undesirable power consumption, may interfere with re-programming the cell, and, in extreme cases, may cause the off state of the transistor to read as on.