There are many applications of semiconductor (SC) devices where it is important to minimize the series ON-resistance of the device, as for example Rdson of field effect transistors. This is especially critical in devices intended for high speed and/or high frequency operation where it is also important to minimize the figure of merit=Rdson*Qg or Rdson*Qgd where Qg is the gate charge or capacitance and Qgd is the gate-drain charge or capacitance and Rdson is the series source-drain resistance of the device in the ON state.
FIG. 1 illustrates prior art vertical diffused metal-oxide-semiconductor (VDMOS) device 20 comprising N+ substrate 22, N-epi region 24, P-body regions 26 in which are provided P+ body contacts 28 and N+ source regions 30 separated from N-epi region 24 by channels 35 in P-body regions 26, gate dielectric 34 overlying channel 35 and JFET portion 36 of N-epi region 24, and gate 38 overlying gate dielectric 34. Contacts (e.g., metallization) 31 are provided for making ohmic contacts to sources 30 and body contacts 28. Contacts 31 are separated from gate 38 by dielectric sidewall spacers 39. Electrode 32 is provided to make electrical connection to contacts 31. When device 20 is appropriately biased, current 37, 37′ flows from source electrode 32 through source contacts 31 to sources 30, from sources 30 through channels 35 in body regions 26 into JFET portion 36 of epi-region 24, and through carrier drift space 25 provided by the remainder of N-epi region 24 to substrate 22 which acts as the drain of VDMOS device 20. Rdson comprises the combined resistances of the various device regions through which currents 37, 37′ flow.
FIG. 2 is a simplified bar chart 41 showing how the various regions of device 20 contribute to Rdson, wherein the vertical axis is the relative contribution to Rdson, expressed as percentage of the total Rdson for the various device regions listed on the horizontal axis. For example, the height of bar 42 shows the relative contribution to Rdson of contacts, 32, 31, the height of bar 43 shows the relative contribution of source regions 30, the height of bar 44 shows the relative contribution of channels 35, the height of bar 45 shows the relative contribution of JFET region 36, the height of bar 46 shows the relative contribution of drift region 25 and the height of bar 47 shows the relative contribution of substrate 22. These data were measured for a VDMOS device with Wp (see FIG. 1) of ˜1.1 micro-meters and channel length Lch ˜0.35 micro-meters (Lch is measured perpendicular to the plane of FIG. 1), at a gate bias VGS of about 4.5 volts with VSD of about 0.1 volts. It was found that contacts 32, 31 contributed about 1% of Rdson, source regions 30 less than 1%, channel regions 35 about 8%, JFET region 36 just under about 50%, drift region 25 about 30% and substrate 22 about 11%. This shows that JFET region 36 and drift region 25 are major contributors to Rdson in this VDMOS device. The series resistance of JFET region 36, for example, can be reduced by increasing Wp while keeping Lch constant. While this will reduce Rdson, it increases the gate-drain charge or gate-drain capacitance Qgd so that the figure of merit=Rdson*Qgd is not improved. Conversely if Wp is reduced in an attempt to improve high frequency performance by reducing Qgd, Rdson increases, which negates the effect of smaller Qgd. Accordingly, there is a need for improved device structures, materials and methods of fabrication that can provide improved performance without such adverse interactions.
Accordingly, it is desirable to provide improved device structures, especially structures that offer improved Rdson without adversely affecting Qgd, or that allows Qgd to be reduced without increasing Rdson so as to improve the figure of merit=Rdson*Qgd. Further it is desired that the structures and methods be useful with a wide array of device types and not be limited merely to VDMOS devices such as that shown in FIG. 1. It is still further desirable to provide an improved device structure and method of fabrication that is useful with a variety of semiconductor materials. It is further desirable that the methods, materials and structures employed be compatible with present day manufacturing capabilities and materials and not require substantial modifications of available manufacturing procedures or substantial increase in manufacturing costs. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.