The present invention relates generally to integrated circuits and, in particular, to a method for forming a metallization layer.
An integrated circuit comprises a large number of semiconductor devices, such as transistors, that are formed on a semiconductor substrate or, more colloquially, a xe2x80x9cchip.xe2x80x9d These devices are selectively interconnected by one or more patterned layers of a conductive material, typically aluminum, to form a circuit that performs a desired function. These layers are referred to as xe2x80x9cmetallizationxe2x80x9d layers. As integrated circuits become more complex, designers reduce the minimum feature size of the constituent devices of the circuit, so as to fit more devices on a chip. With this reduction in size, it becomes more difficult to achieve proper pattern definition using conventional techniques such as photolithography and dry etch techniques for forming metallization layers. Further, designers have attempted to use copper instead of aluminum as the principle metallization material in the metallization layers, due to perceived advantages in resistivity, ductility and melting point. Unfortunately, developers have not been able to create a reliable technique for patterning a copper layer.
For example, one process using electro-deposition for forming a copper metallization layer is described in U.S. Pat. No. 5,151,168. According to this process, a conductive barrier layer is deposited on a semiconductor substrate. Further, a photoresist reverse image of the maskwork normally used to etch the metallization pattern is created on the substrate. The wafer is then transferred to an electrolytic bath in which the copper is complexed with EDTA molecules. A fixed voltage is applied between a voltage source and the semiconductor substrate to deposit the copper ions on the barrier layer that is not covered by the photoresist layer including contact/via openings on the semiconductor substrate. Unfortunately, when the substrate is placed in the electrolytic bath, the photoresist material may lift-off from the substrate thus depositing copper in areas where it is not required.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a method for forming a metallization layer that avoids the disadvantages and problems of prior techniques.
A method for forming a metallization layer is described which uses a single electro-deposition step to reliably form both the metallization layer and to fill the contact vias. In particular, one embodiment of the present invention uses first and second layers of materials that are placed at different surface potentials to form the metallization layer. The first layer is formed outwardly from a semiconductor substrate. Contact vias are formed through the first layer to the semiconductor substrate. The second layer is formed outwardly from the first layer. Portions of the second layer are selectively removed such that the remaining portion of the second layer defines the layout of the metallization layer and the contact vias. Metal ions in a solution are electro-deposited by applying a bi-polar modulated voltage having a positive duty cycle and a negative duty cycle to the layers and the solution. The voltage and surface potentials are selected such that the metal ions are deposited on the remaining portions of the second layer. Further, metal ions deposited on the first layer during a positive duty cycle are removed from the first layer during a negative duty cycle. Finally, exposed portions of the first layer are selectively removed.
In another embodiment of the present invention, the first and second layers are placed at different surface potentials by applying a first voltage to a surface of the first layer and applying a second voltage, higher than the first voltage, to the second layer. In another embodiment of the present invention the different surface potentials are achieved in part by selecting materials for the first and second layers that have different innate surface potentials.