For a word line decoding circuit of such a non-volatile memory as Flash and EEPROM, high-voltage output is required in erasion or programming modes, while fast decoding output in read mode. FIG. 1 is an architecture block diagram of a memory including the word line decoding circuit.
FIG. 2 is word line decoding circuits of three common non-volatile memories. FIG. 2(a) shows withstanding the high voltage by making use of inverters I8 and I9 composed of a high-voltage transistor. Inverters I3 and I4 in FIG. 2(b) are of a low-voltage structure; the output terminal of the second inverter I4 is connected serially with a high-voltage NMOS transistor M1, so as to isolate the grid of the high-voltage NMOS transistor M1 and obtain a control voltage higher than the power source voltage via a charge pump or a bootstrap circuit, thus ensuring that high level VC can be transmitted to a word line WLx without loss in read mode; in high voltage mode, the high-voltage NMOS transistor M1 is turned off, isolating the second low-voltage inverter I4, and a negative high voltage VNEG is transmitted to the word line WLx through a high-voltage NMOS transistor M2. FIG. 2(c) and FIG. 2(b) are different only in that isolation is realized by using the NMOS transistor M1 together with a PMOS transistor M3, such that it is not necessary to increase the grid voltage of the NMOS transistor M1 above the power source voltage in read mode. Several high-voltage tubes have to be used in the above-mentioned three circuits. These high-voltage tubes are very big, so as to guarantee the read speed. This will, with area of the device increased inevitably and greatly, not only reduce integration level for the same device area, but also increase circuit complexity and reduce reliability.