Bus environments increasing rely on high bandwidth Input/Output (I/O) connections and components. One common application of a high bandwidth I/O interconnect is a bridging component that may, on one side, support a standard bus such as a Peripheral Component Interconnect (PCI) bus. The bridge may support single or multiple bus segments. The bridge then interconnects these bus segments to other system resources, such as main memory. Communications initiated on one of the bus segments then passes through the bridge and onto the interface with the other system resources.
Bus standards, such as PCI, provide a multi-drop bus. That is, multiple bus agents (devices) may exist on the same bus. On such multi-drop buses, it is easy to read from or write to other devices on the same bus. For example, a personal computer (PC) typically contains one PCI bus. In this case, it is easy for one device on the bus to perform a peer-to-peer communication with another device on the same bus.
However, as bus interface speed increases, bus architectures are moving away from multi-drop architectures and toward point-to-point architectures. As bus speed increases, point-to-point architectures become more important because a bus cannot operate at higher speeds with the load of multiple cards on the same interface. In architectures supporting multiple independent buses, peer-to-peer communications are not as straight forward as with the multi-drop bus. Synchronization is more important if peer-to-peer traffic is present in a point-to-point architecture. That is, with point-to-point architectures, proper ordering of the communications becomes important.
For example, two devices on separate bus segments connected on the same side of a bridge may communicate with one another. Keeping this peer-to-peer communication within the bridge and not passing it though to the other side of the bridge would yield greater performance. However, proper ordering of these peer-to-peer communications with those that do traverse the bridge then becomes an issue since, due to propagation and processing delays, various components of the bus environment may handle the communications out of order.