Electronic information handling or computer systems, whether large machines, microcomputers or small and simple digital processing devices, require memory for storing data and program instructions. Various memory systems have been developed over the years to address the evolving needs of information handling systems. One such memory system includes semiconductor memory devices.
Computer, communication and industrial applications are driving the demand for memory devices in a variety of electronic systems. One important form of semiconductor memory device includes Dynamic Random Access Memory (DRAM). A typical DRAM includes an array of memory cells. Each memory cell includes a capacitor that stores the data in the cell and a transistor that controls access to the data. The charge stored across the capacitor is representative of a data bit.
Data can be either stored in the memory cells during a write mode, or data may be retrieved from the memory cells during a read mode. The data is transmitted on signal lines, referred to as bit lines, which are coupled to input/output (I/O) lines through transistors used as switching devices. Typically, for each bit of data stored, its true logic state is available on an I/O line and its complementary logic state is available on an I/O complement line.
The memory cells are typically arranged in an array and each cell has an address identifying its location in the array. The array includes a configuration of intersecting conductive lines and memory cells are associated with the intersections of the lines. In order to read from or write to a cell, the particular cell in question must be selected, or addressed. The address for the selected cell is represented by input signals to an address decoder. In response to the decoded address, row access circuitry activates a word line. The selected word line activates the access transistors for each of the memory cells in communication with the selected word line. In response to the decoded column address, column access circuitry selects a bit line. For a read operation, the selected word line activates the access transistors for a given word line address, and data is latched to the selected bit line.
Designers are under constant pressure to increase memory cell density to reduce costs and increase performance. As memory cell density is increased, memory cell size is generally decreased. As memory cell size decreases, contact resistance becomes more critical as the cross-sectional area for current flow decreases. As an example, a metal-containing bit line may make contact to a source/drain region of an access transistor through a polysilicon contact plug. To improve contact resistance between the bit line and the contact plug, a titanium silicide interface is often formed for good ohmic contact between the metal of the bit line and the polysilicon of the contact plug. However, this titanium silicide interface is susceptible to agglomeration if the device is exposed to high temperatures. Such high temperatures are routine in semiconductor processing such as Rapid Thermal Processing (RTP). The risk of agglomeration increases as the thickness of the silicide layer increases. Agglomeration of the titanium silicide or other refractory metal silicide can cause delamination of the bit line, resulting in increased contact resistance.
For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative structures and processes for improving contact resistance in integrated circuit devices.