The present invention is directed to circuit boards, and more particularly, bus topologies for circuit boards.
With increasing processor clock rates in the personal computer, workstation, and server industry, there is a pressing need to provide high speed, economical bus topologies. In particular, designing for high speed and economical communication among more than one processor or agent connected to a bus presents various challenges.
Over the years, many bus topologies have been designed. For example, FIG. 1 illustrates a xe2x80x9c3Dxe2x80x9d topology (e.g., vertical cards on a motherboard give the interconnect a 3D nature) in which processor modules 102, along with their associated heat sinks 104, are mounted on processor cards 106, which are connected together to chip set 108 via bus 109 on motherboard 110. (In an actual embodiment, bus 109 and other traces indicated in FIG. 1 may not be visible.) The connections between an agent, such as a microprocessor, and a bus are often referred to as stubs, and are indicated by numeral 112 in FIG. 1. For some applications, the stub lengths for the 3D topology of FIG. 1 are too long, resulting in undesirable signal reflections.
Yet another bus topology is illustrated in FIG. 2, sometimes called a xe2x80x9c2.5Dxe2x80x9d topology (because there is less vertical dimension when compared to the 3D topology of FIG. 1). For this topology, components (processors or agents) 202, along with their associated heat sinks 204, are mounted on both sides of motherboard 206, facing each other, using connectors 210, and are connected to chip set 208 via bus 209. A stub is identified by numeral 212, but not all stubs are shown. Such topologies are relatively expensive due to motherboard assembly costs. Also, for the topology of FIG. 2, some of the stubs may be too close to each other, so that signal reflections pose a more serious problem.
Busses with many traces may also present design challenges. Some prior art bus topologies use many layers in the motherboard to route the bus traces to chip packages. However, this adds to motherboard complexity and cost. Alternatively, some prior art bus topologies route the bus traces on only one layer or a few layers of the motherboard. But because the dimension of the chip package is often smaller than the physical width occupied by the bus traces when deposited on one layer, some of the stubs may be too long for some applications.
Embodiments of the present invention are directed to addressing these problems.