1. Technical Field
The present invention relates generally to dynamic logic circuits, and more particularly to a dynamic logical circuit having improved noise tolerance by reducing the swing of the pre-charge element control clock.
2. Description of the Related Art
Dynamic logic circuits are well known in field of digital circuits. Dynamic logic is used to decrease device count and increase speed in large-scale circuits such as very-large-scale-integration (VLSI) circuits. Dynamic logic includes pure cascaded dynamic logic referred to as “domino” logic circuits as well as static/dynamic hybrid forms of logic such as limited-switch dynamic logic (LSDL). Dynamic logic performs evaluation and storage functions in microprocessors, memories and other digital devices.
Dynamic logic circuits operate in a two-phase manner: clock signals are used to pre-charge nodes in the circuits to known values, typically at or near one of the power supply rails. Then, when the pre-charge clock changes state, an evaluation is performed by discharging the pre-charged nodes with ladders or “trees” of transistors connected in parallel-series arrangement to the opposite power supply rail. In a typical gate, with an inverter coupling a summing node to the output and N-channel transistor ladders used to pull down the summing node from a logical high level pre-charge state, each ladder combines its inputs in a logical AND function (as all transistors in a ladder must be on for the ladder to pull down the summing node), while the parallel connected ladders are combined in a logical OR function, as any activated ladder will pull down the summing node, resulting in a logical high level at the output of the dynamic logic gate.
In certain topologies and particular gate arrangements, static logic can be combined with dynamic logic to reduce circuit size, increase speed or provide other topological benefits. One such architecture is the above-mentioned LSDL logic, which reduces circuit area below that of other competitive logic types such as domino logic, while still providing the ability to generate complementary logic outputs, via one or more static stages that receive the dynamic evaluation node as an input.
However, as transistor size and power supply voltages have decreased, leakage at the dynamic node has necessitated the introduction of keeper devices in dynamic logic gates so that leakage does not cause false evaluation, especially when leakage is combined with noise present on the logic inputs and charge-sharing effects in the input logic tree. The keeper devices generally take the form of half-latches or complementary inverter pairs that are used to hold the state of the dynamic node of the circuit until a strong evaluation current or the pre-charge state of the clock causes a change in the dynamic node.
The keeper devices not only add additional device area to a dynamic gate, but also increase the capacitance at the evaluation node, leading to an increase in device size or corresponding decrease in channel length in order to provide the same evaluation speed at the dynamic node.
Therefore, it would be desirable to provide a keeper-less dynamic logic gate with decreased sensitivity to dynamic node leakage and noise/charge-sharing effects in the input logic tree.