1. Field of the Invention
The present invention relates to an address trap comparator used in a computer system.
2. Description of the Related Art
Generally, in a computer system, a plurality of address trap comparators are provided, and the address trap comparators are controlled by a central processing unit (CPU). That is, when an address trap occurs in one of the address trap comparators, the CPU carries out an interrupt operation or the like in accordance with the address trap signal of the one of the address trap comparators.
A prior art address trap comparator is constructed by an address trap register for storing a reference address, a bit-by-bit comparator for comparing an address with the reference address stored in the address trap register on the bit-by-bit basis, and an all-bit comparator for detecting whether or not the outputs of the bit-by-bit comparator are the same. This will be explained later in detail.
In the above-mentioned prior art address trap comparator, a test mode is carried out to detect a fault such as a "stuck-at-1" fault or a "stuck-at-0" fault. Note that a "stuck-at-1" fault and a "stuck-at-0" fault will be explained later. For this purpose, special test patterns are supplied to the address trap comparator. This requires a large number of clock signal pulses, which increase the test time.