Semiconductor-on-insulator (SOI) devices are increasingly employed in high performance semiconductor chips for superior performance to bulk semiconductor devices. The SOI devices require a semiconductor-on-insulator (SOI) substrate including a buried insulator layer that provides electrical isolation to a top semiconductor layer from an underlying handle substrate.
Relative to a bulk substrate, the SOI substrate provides benefits such as lower parasitic capacitance and resistance to latch up. As for reduction of parasitic capacitance, a handle substrate is separated from a top semiconductor layer by the buried insulator layer so that the distance of capacitive coupling between devices in the top semiconductor layer and a handle substrate is significant. Further, the dielectric constant of the buried insulator layer is lower than the dielectric constant of typical semiconductor materials. For example, the dielectric constant of silicon oxide is about 3.9, while the dielectric constant of silicon is 11.8 and the dielectric constant of gallium arsenide is 12.85. Thus, the parasitic capacitive coupling of semiconductor devices formed above the buried oxide layer to the portion of the SOI substrate below the buried insulator layer is reduced significantly, which reduces power consumption of the semiconductor devices on the SOI substrate relative to semiconductor devices having matching performance and formed on a bulk substrate.
Further, SOI devices are more resistant to latchup since semiconductor devices are electrically isolated by a combination of shallow trench isolation and the buried insulator layer. In other words, parasitic bipolar transistors comprising a p-n-p type junction or an n-p-n type junction are not present in an SOI substrate. Elimination of such parasitic devices provide the advantage of latchup resistance to the semiconductor devices formed on the SOI substrate relative to semiconductor devices formed on a bulk substrate.
FIGS. 1A-1C show an exemplary prior art semiconductor manufacturing sequence. Referring to FIG. 1A, an exemplary prior art structure comprises a semiconductor substrate 8 containing a contiguous semiconductor layer 9 containing a semiconductor material such as silicon. Referring to FIG. 1B, the contiguous semiconductor layer 9 is implanted with oxygen to form an oxygen enriched layer 20 within the semiconductor substrate 8. The oxygen enriched layer 20 contains a high percentage of oxygen atoms as in a silicon oxide. The portion of the semiconductor substrate 8 above the oxygen enriched layer 20 constitutes a top semiconductor layer 30, and the portion of the semiconductor substrate below the oxygen enriched layer 20 constitutes a bottom semiconductor layer 10. Referring to FIG. 1C, the semiconductor substrate 8 is annealed at a high temperature about 1,300° C. to convert the oxygen enriched layer 20 into a buried insulator layer 22 containing silicon oxide.
As semiconductor devices scale down for enhanced performance of reduction of power consumption in each technology generation, variations in electrical characteristics of semiconductor devices tend to increase. For example, the ratio of a standard deviation in the physical length, called a “gate length,” of a gate electrode across a channel of a field effect transistor relative to the mean of the physical lengths of the gate, or the “mean gate length,” increases as the mean gate length decreases with scaling since improvements in lithographic tools and etch process tend to be insufficient to enhance accuracy of physical features of printed and etched structures at the same rate as the scaling of physical dimensions. Further, as devices shrink, some device characteristics that are determined by stochastic processes, such as a threshold voltage of a field effect transistor that is determined by stochastic distribution of dopant ions in an ion implantation process, are subject to more variation with scaling down of device dimensions.
For consistent performance of an integrated circuit, the electrical characteristics of semiconductor devices need to be consistent. Thus, controllable aspects of the variations in the electrical characteristics need to be controlled more tightly. One of the mechanisms of inducing variations in device characteristics in a semiconductor-on-insulator (SOI) substrate is diffusion of dopants (B, Ga, In, P, As, Sb. etc.) over time through isolations through the buried oxide layer in the SOI substrate. The diffusion of dopants may occur vertically or laterally through the buried oxide layer. The dopants may eventually diffuse into semiconductor devices located in the top semiconductor layer and cause shifts in device characteristics such as the threshold voltage (Vt) of a transistor. Another negative impact to device characteristics is loss of dopants from source and drain extension regions and deep source and drain regions into the buried insulator layer, which causes an increase in source resistance and/or drain resistance.
As scaling of semiconductor devices continues, the thickness of the top semiconductor layer decreases, making control of dopant diffusion to the buried insulator layer more critical. While thermal processing techniques, such as a laser anneal or a flash anneal, have been proposed to reduce diffusion of the dopant atoms in SOI devices, such techniques tend to significantly increase complexity of a semiconductor processing flow. Further, some processing steps, such as activation of dopants introduced into a polysilicon gate by on implantation, requires a high temperature thermal processing step that for dopant activation that invariably induces diffusion of dopants. Such processing steps make it difficult to provide an integration scheme that avoids diffusion of dopants introduced into the semiconductor devices during well level ion implantation steps, i.e., ion implantations steps prior to formation of a gate stack. For example, in semiconductor devices formed on an ultra-thin semiconductor-on-insulator (UTSOI) substrate having a 18 nm thick top semiconductor layer, increase in source and drain resistance that degrades the drive current of a p-type field effect transistor by more than 30% due to loss of boron atoms from the source and drain extension regions has been observed. In an n-type field effect transistor which employs a portion of a top semiconductor layer having a thickness of about 13 nm, loss of arsenic atoms from the source and drain regions may also cause degradation of device performance. Similar problems exist for dopant atoms introduced into a semiconductor device during halo ion implantations, since loss of dopant ions from the halo regions introduces negative impacts and device parameter variations.
In view of the above, there exists a need for a semiconductor structure providing beneficial effects of semiconductor-on-insulator substrate, while concurrently preventing diffusion of dopants into or out of a buried insulator layer, and methods of manufacturing the same without significantly increasing process complexity or cost.