1. Field of the Invention
The present invention relates to a semiconductor apparatus, and in particular to a semiconductor apparatus including a protection circuit for protecting the semiconductor device against electrostatic discharge.
2. Description of the Related Art
FIG. 19 is a circuit diagram for a general monolithic semiconductor integrated circuit 50 in which the potential of a substrate power supply is set to be equal to the potential of a ground power supply. The monolithic semiconductor integrated circuit 50 includes a protection circuit 60 for protecting the integrated circuit 50. Hereinafter, such a protection circuit for protecting the semiconductor device such as the integrated circuit 50 against electrostatic discharge will simply be referred to as the "protection circuit". The protection circuit 60, which is described in Terry V. Hulett, "On Chip Protection of High Density NMOS Devices" published in EOS/ESD Symposium, 1981, has been widely used as a typical protection device against electrostatic discharge used in a MOS device until the present time.
The protection circuit 60 includes a resistance 13 between an input terminal 11 and an internal circuit 12. Point A between the resistance 13 and the internal circuit 12 is connected to the ground power supply through a MOS transistor 14. The resistance 13 is provided for restricting the amount of an electrostatic current. The MOS transistor 14 is an enhancement n-channel transistor for sending the electrostatic current to the ground power supply, and has a drain connected to point A and a source and a gate both connected to the ground power supply.
When a high electrostatic voltage is applied to the input terminal 11, the high voltage is applied to the MOS transistor 14 through the resistance 13. When being supplied with a high voltage, the MOS transistor 14 acts as a bipolar transistor, and is conductive with a low resistance due to a punch-through phenomenon. As a result, the electrostatic current flows to the ground power supply through the resistance 13 and the MOS transistor 14, thereby preventing a high voltage from being stored at point A. Thus, breakdown of the internal circuit 12 by electrostatic discharge is prevented.
FIG. 20 is a cross sectional view of the protection circuit 60 formed in a p-type semiconductor substrate 15. The p-type semiconductor substrate 15 is connected to the ground power supply through a p-type diffusion layer 16 and a wiring 17. The resistance 13 includes an n-type diffusion layer 18 formed in the p-type semiconductor substrate 15. The n-type diffusion layer 18 is connected to the input terminal 11 through a wiring 19 at one end thereof and to the wiring 20 at the other end thereof. Point A, which is connected to the wiring 20, is connected to the internal circuit 12 (not shown). The MOS transistor 14 includes n-type diffusion layers 21 and 22 formed in the p-type semiconductor substrate 15 and a gate electrode 23 provided above a region between the n-type diffusion layers 21 and 22. The n-type diffusion layer 21 is connected to the wiring 20, and the n-type diffusion layer 22 is connected to the ground power supply through the wiring 17. The gate electrode 23 is also connected to the ground power supply. The wirings 17, 19 and 20 are formed on the p-type semiconductor substrate 15 over the an insulating layer film 33.
When a high electrostatic voltage is applied to the MOS transistor 14 from the input terminal 11 through the resistance 13, the MOS transistor 14 acts as an npn transistor 24 shown in FIG. 20. The n-type diffusion layers 21 and 22, which respectively act as a collector and an emitter of the npn transistor 24, are conductive to each other with a low resistance due to a punch-through phenomenon. Accordingly, the electrostatic current flows from the input terminal 11 to the ground power supply through the wiring 19, the n-type diffusion layer 18 (namely, the resistance 13), the wiring 20, the n-type diffusion layers 21 and 22, and the wiring 17.
The n-type diffusion layers 21 and 22 are electrically connected with each other when the level of the applied electrostatic voltage exceeds the breakdown voltage of the MOS transistor 14. Usually, the breakdown voltage is lower than a breakdown voltage of a parasitic diode 25 formed by the pn junction of the p-type semiconductor substrate 15 and the n-type diffusion layer 18. Therefore, the electrostatic current in the MOS transistor 14 flows out to the ground power supply due to a punch-through phenomenon before the parasitic diode 25 breaks down. When an excessively high electrostatic voltage is applied, the voltage drop in the resistance 13 is increased. Accordingly, the level of the voltage applied to a connection area between the n-type diffusion layer 18 and the wiring 19 possible exceeds the breakdown voltage of the parasitic diode 25. In such a case, the electrostatic current flows in a reverse direction in the parasitic diode 25 to the p-type semiconductor substrate 15 and further to the ground power supply through a p-type diffusion layer 16. Since the power dissipation caused by the electrostatic current is mostly generated in the parasitic diode 25, namely, the junction interface of the n-type diffusion layer 18 and the semiconductor substrate 15 is broken. In "One Chip Protection of High Density MOS Devices", it is proposed to form the resistance 13 of polysilicon in order to prevent such a breakdown of the interface. In Japanese Laid-Open Patent Publication No. 2-5478, it is proposed to provide another diffusion layer having an identical conductivity with and having a lower density than those of the n-type diffusion layer 18 in a region below the connection area of the n-type diffusion layer 18 and the wiring 19, in order to raise the breakdown voltage of the parasitic diode 25. The resistance 13 for restricting the amount of the electrostatic current may be eliminated by increasing the current capacitance of the npn transistor 24 to a sufficient level.
In the MOS transistor 14, which functions as the npn transistor 24 for utilizing the punch-through phenomenon, the gate electrode 23 does not have any important function. Accordingly, the MOS transistor 14 may be replaced by an npn transistor 26 shown in FIGS. 21 and 22. FIG. 21 is a plan view and FIG. 22 is a cross sectional view of the npn transistor 26. The npn transistor 26 includes n-type diffusion layers 21 and 22 formed in the semiconductor substrate 15 and an isolation layer 27 formed of SiO.sub.2 between the n-type diffusion layers 21 and 22. Such an npn transistor is described in the U.S. Pat. No. 4,692,781. Similar structures and concepts are described in Japanese Laid-Open Patent Publication Nos. 59-51558, 60-235451, 60-235452 and 2-3957.
FIG. 23 is a circuit diagram for another conventional protection circuit 61 used in an integrated circuit 51 in which the potential of a substrate power supply is set to be different from the potential of the ground power supply, such as a DRAM (dynamic random access memory). FIG. 24 is a cross sectional view of the protection circuit 61.
As is shown in FIG. 23, the protection circuit 61 includes a resistance 13 between an input terminal 11 and an internal circuit 12. Point A between the resistance 13 and the internal circuit 12 is connected to a ground power supply through a MOS transistor 14. The internal circuit 12 is supplied with a power supply voltage V.sub.CC and a substrate power supply voltage V.sub.BB as well as a ground power supply voltage GND. The power supply voltage V.sub.CC is higher than the ground power supply voltage GND; and the substrate power supply voltage V.sub.BB is lower than the ground power supply voltage GND. As is shown in FIG. 24, a p-type semiconductor substrate 15 is not supplied with the ground power supply voltage GND, but is supplied with the substrate power supply voltage V.sub.BB through a p-type diffusion layer 16. Parasitic diodes 25, 29, 30 and 31 are respectively formed between the p-type semiconductor substrate 15 and an n-type diffusion layer 18, between the p-type semiconductor substrate 15 and an n-type diffusion layer 21, between the p-type semiconductor substrate 15 and an n-type diffusion layer 22, and between the p-type semiconductor substrate 15 and an n-type diffusion layer 28.
As an evaluation method of the resistance of such a semiconductor device against electrostatic discharge, the MIL standards (MIL-STD 883C 3015) are used as the most common international standards. According to the MIL standards, a capacitance of 100 pF is stored to have an appropriate voltage, and this voltage is applied to a terminal of the semiconductor device through a resistance of 1.5 k.OMEGA.. The voltage at which the semiconductor device is broken is measured.
The evaluation is performed for the protection circuit 61 in the following manner. The ground power supply voltage GND and the power supply voltage V.sub.CC are used as the reference voltages. In the following explanation, a voltage higher than the ground power supply voltage GND will be referred to as the voltage in the "GND+ mode", a voltage lower than the ground power supply voltage GND as the voltage in the "GND- mode", a voltage higher than the power supply voltage V.sub.CC as the voltage in the "V.sub.CC + mode", and a voltage lower than the power supply voltage V.sub.CC as the voltage in the "V.sub.CC - mode".