Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. As used herein, “include” and “including” mean including without limitation.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (“PIPs”). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.
For all of these programmable logic devices (“PLDs”), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.
Conventionally, to have valid communication between a transmitter and a receiver, a lock condition for a clock data recovery (“CDR”) module is used. A CDR is conventionally used to control operation of a phase interpolator (“PI”). In short, before data from a PI is considered valid, a lock condition for the CDR is used. If a recovered phase is not phase-locked, then output of a phase detector tends to be in the same direction of the out-of-lock condition, either up or down. If, however, a recovered phase is phase-locked, then conventionally a phase detector output is generally at or about 50/50, namely 50 percent up and 50 percent down.
However, lock conditions are susceptible to phase drift between transmit (“TX”) and receive (“RX”) clock signals. It should be understood that conventionally there is some phase drift between TX and RX clock signals. This phase drift may be for example 100 cycles in 1 million cycles, or some other ratio. However, heretofore it may not have been known how much a current RX clock has drifted from an associated TX clock. For example, a registered phase value of a filter at the beginning of a sample window and a registered phase value of such filter at the end of such a sample window may have been obtained to provide a difference thereof. This would provide a magnitude of a phase difference; however, because of phase drift, this magnitude may be significantly in error. Furthermore, magnitude of such out-of-lock condition may not be well understood due to a wraparound condition of code input to the PI.
Accordingly, it would be desirable and useful to provide a more accurate CDR module.