A content addressable memory system (hereafter simply a CAM system) is a memory system in which individual memory elements are not exclusively indexed by a unique address. Instead, a memory element in a CAM system may be addressed by a portion of the data within the memory element. The way in which a memory cell in a CAM system is addressed distinguishes a CAM system from a conventional random access memory (RAM) or a read only memory (ROM) system.
A particular data word stored in a RAM cell or a ROM cell is accessed by supplying a unique address to the memory system associated with the desired memory element. In a CAM memory system, a "tag" is supplied to the memory system. The CAM memory system compares the tag to a subset of the data bits contained in each memory element. Generally, the portion of each memory element that contains this subset of memory bits is referred to as the CAM. The CAM portion typically has several CAM cells within it. Each CAM cell stores one data bit. Each CAM, or group of CAM cells, is associated with a conventional memory element storing other data bits. The CAM that contains data bits logically equivalent to the input tag "matches" and asserts a logic signal referred to as a "matchline." The asserted matchline causes the CAM memory system to output the other data bits associated with the matching CAM. These other data bits are the desired data bit, byte, word, etc.
CAM systems are particularly useful as caches in data processing environments. In such environments, CAM systems store a subset of frequently used data in a plurality of RAM memory elements. The frequently used data might be instructions to execute in the data processing system, operands of the executed instructions, or a combination of both instructions and operands. In these cases, the CAM system would be called an instruction cache, a data cache, or a unified cache, respectively. Or, the frequently data might be used to convert internal virtual memory addresses into external real memory addresses. In this case, the CAM system would be called a translation look aside cache (or buffer). In all cases, an associated tag identifies the data stored in each corresponding CAM portion. In the case of an instruction, data or unified cache, the tag identifies a memory address in memory space from which the data originated. In the case of a translation look aside cache, the tag identifies the virtual memory addresses for which the associated translation is valid.
Known CAM systems suffer several disadvantages arising primarily from their complexity. First, known CAM systems typically require two timing signals to operate properly. One of these timing signals gates the CAM matchlines before the matchlines reach the wordlines of the RAM cells. This first timing signal prevents the matchlines from indicating a false match during precharge and tag input equalization. A second of these timing signals may enable the sense amplifier connected to the output of the RAM array. This second timing signal prevents the sense amplifier from turning on until the voltages on the RAM bitlines begin to separate, preventing a false output. Both of these timing signals require circuits to generate them, resources to test them, etc. Second, the use of these two timing signals slows down the cycle time of the CAM system. Both signals must be generated to operate correctly in all situations, including the slowest matchline generation condition and the slowest bitline separation condition. Therefore, the two timing signals must be generated "conservatively," guaranteeing proper operation in all conditions and throughout all manufacturing process variations.