Conventionally, COT (Chip on Tape) semiconductor devices wherein semiconductor chips are offset to be mounted on flexible tapes that can be freely bent are known. FIG. 13 shows a structure of a TCP semiconductor device 51 as one example of the COT semiconductor devices. The TCP semiconductor device 51 is prepared such that a metal wiring pattern 53 is formed on a substrate 52, and to inner leads 53a of the metal wiring pattern 53 which are positioned in a vicinity of a center of the substrate 52, a semiconductor chip 54 is connected by an ILB (Inner Lead Bonding) process via an ACF (Anisotropic Conductive Film). The metal wiring pattern 53 is connected to an external circuit by means of outer leads 53b of the metal wiring pattern 53 formed in the end portions of the substrate 52 by the OLB (Outer Lead Bonding) process.
It may be also arranged such that device holes 52a are formed around a center of the substrate 52, and in this region, a semiconductor chip 54 is mounted to inner leads 53a of the metal wiring pattern 53 by the ILB like a TCP semiconductor device 61 shown in FIG. 14. In this structure, the semiconductor chip 54 and the inner leads 53a are sealed with resin 62 so as to protect them mechanically.
The described TCP semiconductor devices 51 and 61 are typically used for liquid crystal drivers. The structures wherein these liquid crystal drivers are mounted to liquid crystal modules are shown in FIG. 15 and FIG. 16 respectively.
The liquid crystal module can be roughly divided into two parts: a display section 71 for use in an image display area of a liquid crystal panel; and a frame section 72 for mounting therein a drive circuit for driving the liquid crystal section 71. The described TCP semiconductor devices 51 and 61 are provided in the frame section 72, and one of the outer leads 53b is connected to a glass panel wiring 73a formed on a glass panel 73, and the other outer lead 53b is connected to an input substrate wiring 74a formed on an input substrate 74. In the described liquid crystal module, the semiconductor chip 54 functions as a driver IC of the display section 71.
Next, the structure of a TBGA semiconductor device 81 as another example of the COT semiconductor devices is shown in FIG. 17. The TBGA semiconductor device 81 is arranged such that connecting paths for connecting metal wiring pattern 53 and the back surface side of the substrate 52 are formed by punching throughholes 52b in the substrate 52 having formed thereon the metal wiring pattern 53, and solder balls (or conductive projections) 83 which permit a connection with the external circuit are arranged in a form of grid at the leading end portions of the conductive paths 82. On the side of the metal wiring pattern 53 of the substrate 52, a semiconductor chip 54 is face-down connected to the metal wiring pattern 53 via an anisotropic conductive film 55.
An array of the solder balls 83 in a form of a grid is called a BGA (Ball Grid Array). The connection between the external circuit and the BGA is performed by controlling the surface extension or the viscosity characteristics of the solder by melting the solder balls 83 in a reflow furnace. This method was developed by IBM in the U.S.A. as a technique of soldering the semiconductor chip to a ceramic substrate at high density, and is known as the controlled collapse chip connection (C4 method).
The described tape ball grid array (TBGA) semiconductor device 81 is disclosed by Japanese Unexamined Patent Publication No. 102474/1996 (Tokukaihei 8-102474). Other known TBGA semiconductor devices TBGA includes semiconductor devices 91 and 101 wherein device holes 52a are formed in a vicinity of a center of the substrate 52, and the semiconductor chip 54 is connected to the metal wiring pattern 53 as disclosed in Japanese Unexamined Patent Publication No. 88245/1996 and Japanese Unexamined Patent Publication No. 148526/1996 (see FIG. 18 and FIG. 19). Here, the semiconductor chip 54 is connected to the inner leads 53a which are parts of the metal wiring patterns 53 and are projected on the device holes 52a. Then, solder balls 83 are formed at predetermined positions of the metal wiring pattern 53 outside the area on the device holes 52a. Although not shown, another arrangement is known wherein after a semiconductor chip is die-bonded to the substrate, the semiconductor chip and the metal wiring pattern are mounted by wire-bonding.
However, when mounting the TCP semiconductor chip 51 shown in FIG. 13 to a liquid crystal module, the structure of the semiconductor chip 54 shown in FIG. 15 which is projected from the substrate 52 to the metal wiring pattern 53 requires a space for storing therein the semiconductor chip 54 between the glass panel 73 and the input substrate 74. For the liquid crystal module, the smaller the width of the frame 72, the greater the area of the display section 71, and thus the quality of the product can be improved as it offers clearer images. On the other hand, it is not preferable to ensure the space for storing the semiconductor chip 54 as shown in FIG. 15 as a wider frame 72 is required.
In order to eliminate the described problem, another arrangement has been proposed wherein a longer substrate is adopted so as to bend the TCP semiconductor device such that the lengthwise direction of the glass panel and the lengthwise direction of the input substrate form a right angle. In this method, however, problems arise in that costs increase by adopting the longer substrate, and therefore the throughput in the manufacturing processes is lowered, thereby increasing manufacturing costs.
In the structure wherein a longer substrate cannot be adopted, it may be arranged so as to cut a part of the input substrate so as to allow the semiconductor chip to be stored therein. In this method, however, even if the width of the frame can be made narrower, preciseness is required to cut the part of the input substrate to be suited for the size of the semiconductor chip, which increases the manufacturing costs.
In the case of adopting the TCP semiconductor device 61 shown in FIG. 14, as the semiconductor chip 54 is mounted on the different side of the metal wiring pattern 53 with respect to the substrate 52, when mounting the TCP semiconductor device 61 to the liquid crystal module, the glass panel 73 and the input substrate 74 can be proximate to each other as shown in FIG. 16. However, when an attempt is made to reduce the width of the frame 72 in the described manner, as the semiconductor chip 54 is connected to the inner leads 53a by the thermocompression, it is likely that the inner leads 53a are deformed, which lowers a yield of the manufacturing process.
On the other hand, in the structure of the TBGA semiconductor device 81 shown in FIG. 17 given as another example of the COT semiconductor device, to conduct the semiconductor balls (or conductive projections) 83 and the metal wiring patterns 53, throughholes 52b are punched in the substrate 52 beforehand. In order to punch the throughholes 52b, high precision NC processing, laser processing, or punching with a mold is required. In the case of punching the throughholes 52b by the NC processing or the punching through the mold, a processing time is required in proportion to the number of the throughholes 52b, which results in an increase in the manufacturing costs. In the case of punching the throughholes 52b by the processes using a laser beam, expensive facilities are required.
The TBGA semiconductor device 91 shown in FIG. 18 and the TBGA semiconductor device 101 shown in FIG. 19 are arranged such that after connecting the inner leads 53a to the semiconductor chip 54, in order to mechanically protect the inner leads 53a and the surface of the semiconductor chip 54, these members are coated with resin. For this reasons, the metal wiring patterns 53 or the solder balls (or conductive projections) 83 which are required for the mounting of the substrate 82 cannot be formed in the area of the device holes 52a. As a result, a layout of the pattern on the package of the TBGA semiconductor devices 91 and 101 is restricted which lowers a degree of freedom, thereby presenting the problem that semiconductor balls (or conductive projections) 83 cannot be arranged in a full matrix.
Furthermore, in the case of adopting the TBGA semiconductor devices 81, 91 and 101, as it is likely that the package warps, a self-alignment is difficult to be achieved when connecting the BGA to the external circuit substrate. Namely, the warpage of the package causes the problem that the external circuit substrate and the package cannot be bonded uniformly within the connection surface, and there may exist an unconnected part between the solder paste applied to the external substrate and the solder balls (conductive projections) 83 of the package. As described, a non-uniform package causes a problem of inferior connection between the solder balls and the external circuit substrate.