(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to the formation of shallow junction MOSFETs with a novel technique that eliminates shorts due to junction spiking.
(2) Description of the Prior Art
The next generation of metal-oxide-semiconductor field effect transistor (MOSFET) devices will likely use shallow junction technology in the formation of source and drain regions. Shallow junctions are herein defined as junctions of less than 0.15 microns in depth. Such junctions are necessary to further reduce MOSFET channel lengths and thus achieve greater packing densities and switching speeds.
One problem encountered in the use of shallow junction devices is that of junction spiking. It is typical in the art to contact metal conductor layers directly to the surface of substrate junctions. It is possible that metal will diffuse into the bulk of the junction and form a spike. In the case of relatively deep junctions, this spike does not necessarily pose a problem. For shallow junctions, however, this metal spike can be deep enough to short across the junction into the substrate below.
In addition, the use of silicides to prevent metal spiking is not practical for shallow junctions. The formation of silicide consumes part of the substrate during the anneal process. In the case of shallow junctions, the junction remaining after the silicide formation will tend to exhibit unacceptable junction leakage.
Referring to FIG. 1, a cross-section of a partially completed prior art integrated circuit is shown. A silicon substrate 10 is shown. Isolation regions, formed by shallow trench isolation (STI), are also shown 14. A gate oxide layer 18 has been grown or deposited on the surface of the silicon substrate 10. A polysilicon layer 22 is deposited overlying the gate oxide layer 18 as conventional in the art.
Referring to FIG. 2, a reactive ion etch (RIE) has been performed to pattern the polysilicon layer 22 to form the gate electrode for a planned MOSFET device. During the etch process, an undesirable effect call microtrenching can sometimes occur. In microtrenching, an enhanced etch attack is seen at the edge of the polysilicon gate and can result in the etch breaking through the gate oxide layer 18. When this occurs, a microtrench 26 can form. The use of bromine- and oxygen-containing gases in the etch process can increase the etch selectivity and reduce the likelihood of microtrenching. However, this effect does still occur for ultra-thin gate dielectrics. When a microtrench 26 is formed, it is a likely location for a metal junction spike to form in subsequent processing.
Referring to FIG. 3, the results of further processing of the prior art MOSFET structure are shown. The gate electrode, including sidewall spacers 38, has been fabricated. Shallow junctions have been formed with lightly doped junctions 30 and heavily doped junctions 34. An intermetal dielectric layer 42 was deposited and etched to form contact openings. A metal layer 46 was deposited to fill the contact openings and patterned to form interconnects. Finally, a passivation layer 50 was deposited to complete the MOSFET structure.
A metal spike 44 is shown formed in the junction region of the MOSFET. The metal spike 44 may have formed due, in part, to the aforementioned microtrench 26 feature from the gate etch step or by other means. The metal spike is shown to have penetrated entirely through the shallow junction and into the underlying silicon substrate 10. The short will cause the MOSFET to fail and this device will be rejected during the testing process.
Several prior art approaches disclose methods to form gate, source, or drain electrodes using polysilicon and chemical mechanical polish techniques. U.S. Pat. No. 5,856,225 to Lee et al discloses a method to form self-aligned, ion implanted channel regions in MOSFETs following the formation of source and drain regions. A sacrificial polysilicon gate is formed and then removed to open the channel region for implantation. Chemical mechanical polishing is used to define the gate electrode from a second polysilicon deposition. U.S. Pat. No. 5,786,255 to Yeh et al teaches a process to form a MOSFET where the polysilicon contact layer for the source and drain regions is defined by a chemical mechanical polish. The gate and isolation regions are formed in a silicon nitride layer that then is etched away to leave the gate and isolation regions above the surface of the silicon substrate. U.S. Pat. No. 5,674,774 to Pasch et al discloses a method to define source and drain remote polysilicon contacts by chemical mechanical polishing of a polysilicon layer. U.S. Pat. No. 5,767,005 to Doan et al teaches a process to form floating gates for EEPROMs using a chemical mechanical polish of the polysilicon layer. U.S. Pat. No. 5,447,874 to Grivna et al discloses a process to form a dual metal gate.