1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, especially, relates to a semiconductor device and a method of manufacturing the same applied to device manufacturing that requires miniaturization.
2. Related Art
The conventional MOSFET (Metal Oxide layer Semiconductor Field Effect Transistor) has a gate electrode formed only in an upper part of a surface of a semiconductor principal plane functioned as a channel. However, with miniaturization of MOSFETs, there are high demand to realize a MOSFET with a double-gate structure having gate electrodes formed not only in an upper part of a surface of the semiconductor principal plane functioned as the channel but also on a lower surface of the channel. In the MOSFET with the double-gate structure, for example, it is confirmed that there is an advantage that it is possible to maintain a switching characteristic even against the fall in a voltage due to the miniaturization. For the double-gate MOSFET, besides a method of forming a surface of a semiconductor principal plane as a channel and forming gate electrodes on an upper surface and a lower surface of the channel, there has been proposed a FINFET (Fin Field Effect Transistor) structure in which a channel is formed vertically to a semiconductor principal plane (in a fin shape) and gates are formed on both sides of the channel (Japanese Patent Laid-Open No. 2002-118255, Japanese Patent Laid-Open No. 2003-298051, and Japanese Patent No. 3543946).
As characteristic of this FINFET structure, for example, it is easier to manufacture the FINFET structure than the method of manufacturing the MOSFET with the double-gate structure. The MOSFET with such a conventional FINFET structure has the characteristic that manufacturing thereof is easy as described above but has problems explained below.
In the conventional MOSFET 8 with FINFET structure, the gate electrode is formed after forming an SOI region in the FIN shape. In the case of patterning the gate electrode due to a lithography technique, the lithography is performed by aligning gate patterning locations to the FIN shape. However, an error may be involved in the alignment. As a result, in the FIN shape, it is necessary to incorporate an alignment margin in a pattern in advance taking this error into account. Therefore, it is necessary to set length F of FIN in a source to drain direction (a vertical direction on a paper surface) longer than width L of the gate electrode by length of an alignment error G.
In other words, there is a relation of F>L+G. As a result, in the MOSFET with the conventional FINFET structure, source and drain regions of the FIN shape are formed. In order to perform further miniaturization, it is necessary to reduce width H of FIN. On the other hand, parasitic resistance of the source and drain regions of the FIN shape increases as the FIN width H is reduced. Thus, it is impossible to realize high performance of the MOSFET even if the MOSFET is miniaturized. As described above, in the MOSFET with the conventional so-called double-gate structure, a margin for aligning the gate pattern is necessary. Therefore, it is impossible to shorten the FIN length even if the FIN width is narrowed due to the miniaturization, and there is a problem that a high parasitic resistance is generated.