Voltage islands are often designed into and implemented on integrated circuit chips to allow active and standby power reduction by changing the supply voltages to individual voltage islands. Voltage islands have also been implemented to reduce noise via supply isolation. The voltage island concept can reduce power consumption substantially by allowing designers to build, for example, processors that vary their voltages across a chip. In particular, a single system-on-a-chip processor could be built to run one voltage in one or more areas of the chip, such as a processor core, a different voltage in other areas of the chip, and to switch off the voltage to areas of the chip that are not in use.
In today's voltage island implementations, all voltage islands of a chip are powered up during test. One test, for example, involves measuring the quiescent (Q) current (IDD) in the VDD supply (hereafter referred to as “IDDQ”). This test is performed by measuring the standby current of a chip. IDDQ testing depends on the fact that some defects in the chip cause additional standby current. By comparing the IDDQ value of the device under test (DUT) to a pass/fail value, a determination can be made as to whether the DUT is defective or not. The pass/fail value may be determined using statistics from individual wafers/lots, or may be determined using other known methods.
IDDQ testing has been shown to be effective in screening out a class of reliability problems. However, the effectiveness of IDDQ testing decreases as the level of standby current increases. For example, if the IDDQ test is capable of finding defects that cause a 10% increase in standby current, on a chip with 1 mA of standby current, a defect that generates 0.1 mA of additional standby current can still be detected. On a chip that generates 1 A of standby current, however, a defect must generate 100 mA of standby current to be detected. Thus, on a chip that generates 1 A of standby current, a defect that generates 0.1 mA of standby current will not be detected and may potentially cause a reliability problem. Accordingly, there exists a need for a method/apparatus for increasing the effectiveness of IDDQ testing by limiting the standby current.
Chip burn-in testing is also becoming more difficult as standby currents increase. During burn-in, the DUT is exposed to high source voltages (i.e., high VDD) and temperatures to induce early life/marginal fails. These conditions raise the standby current even more than at the IDDQ measurement conditions, which in turn creates problems in supplying the needed current to the DUT, and in maintaining the correct burn-in temperature on the DUT and in the burn-in ovens. Accordingly, there exists a need to reduce standby current during burn-in operations.
IDDQ testing is just one of the many different types of scan-based tests that are commonly performed on an integrated circuit chip. Several scan-based tests, including the burn-in test described above, involve observing the operation of a chip at voltage levels that are higher or lower than the nominal operational source voltage of the chip. Regardless of the type of scan-based test performed on a chip containing voltage islands, however, the test must be performed using an “all or nothing” approach. That is, all of the voltage islands must be powered up and held at the same voltage level during test. The voltage islands are not independent from one another during test and, as such, the voltage islands cannot be independently turned on/off or adjusted during test, thereby limiting the effectiveness of the chip and sub-chip testing processes. Accordingly, there exists a need for voltage island architecture wherein the source voltage of the voltage islands can be independently turned on/off or adjusted during a scan-based test.
Referring to FIG. 1, there is illustrated a related art integrated circuit chip 10 that includes a first voltage partition (i.e., first voltage island 12) and a second voltage partition (i.e., second voltage island 14). Although only two voltage islands 12, 14 are shown in the integrated circuit chip 10, it should be appreciated by one skilled in the art that a typical integrated circuit chip may include more than two voltage islands.
Voltage island 12 is powered by a source voltage VDDI1 and is coupled to VDDI1 through a first island voltage controller 16. Similarly, voltage island 14 is powered by a source voltage VDDI2 and is coupled to VDDI2 through a second island voltage controller 18. The first and second island voltage controllers 16, 18 control the source voltage that is provided to the first and second voltage islands 12, 14, respectively.
The integrated circuit chip 10 includes a scan-in pin (SI) 20 and a scan-out (SO) pin 22. A scan chain 24, comprising a plurality N of latches connected in series, is connected between the scan-in pin 20 and a scan-out pin 22. A portion of the scan chain 24, hereafter referred to as “partial scan chain 26,” is illustrated in FIG. 1. It should be appreciated that the although the scan chain 24 is shown in FIG. 1 as only including three latches 28, 30, and 32 (i.e., N=3), a typical scan chain may include literally millions of latches that are connected in series and distributed throughout the voltage islands 12, 14 and the other components of the integrated circuit chip 10. Further, the integrated circuit chip 10 may utilize a plurality of additional scan chains, each containing a scan-in and scan-out and a plurality of scannable storage elements, such as latches or the like.
As known in the art, a scan chain is used to input test patterns into, and output test data from, an integrated circuit chip. In particular, a test pattern containing a string of ones and zeros is applied to the scan-in pin of the chip and serially scanned into the latches of the scan chain. A predetermined number of clock cycles are then executed and test data is captured in the latches. The test data is then serially scanned out of the latches to the scan-out pin of the chip. The use of such a scan chain minimizes the number of pins that are required for test.
The partial scan chain 26 passes through both the first voltage island 12 and the second voltage island 14. The latch 28 of the partial scan chain 26 located within the first voltage island 12 and is powered by the same voltage as the first voltage island 12 (i.e., the voltage (Island 1 VDD) provided by the first island controller 16). Similarly, the latch 30 is located within the second voltage island 14 and is powered by the same voltage as the second voltage island 14 (i.e., the voltage (Island 2 VDD) provided by the second island controller 18). Accordingly, if the power is cut off to either voltage island 12, 14, the corresponding latch 28, 30, respectively, will no longer operate, thereby breaking not only the partial scan chain 26, but also the scan chain 24, and preventing scan chain based testing of the integrated circuit chip 10. The scan chain architecture of the related art, therefore, requires that all of the voltage islands 12, 14 of the integrated circuit chip 10 remain powered up (i.e., “on”) during test. Independent control of each voltage island 12, 14, therefore, is not possible during test. This limits the types of tests that can be performed on the integrated circuit chip 10, and reduces the effectiveness of these tests.