The microelectronic industry is continually striving to produce ever faster and smaller microelectronic devices for use in various mobile electronic products, such as portable computers, electronic tablets, cellular phones, digital cameras, and the like. As these goals are achieved, the fabrication of the microelectronic devices becomes more challenging. One such challenging area relates to the interconnect layers that are used to connect the individual devices on a microelectronic chip and/or to send and/or receive signals external to the individual device(s). Interconnect layers generally comprise a dielectric material having conductive interconnects (lines) coupled to the individual devices. The interconnects (lines) generally comprise a metal line portion and a metal via portion, wherein the metal line portion is formed in a trench within the dielectric material and the metal via portion is formed within a via opening that extends from the trench through the dielectric material. It is understood that a plurality of interconnection layers (e.g., five or six levels) may be formed to effectuate the desired electrical connections. For example, a first interconnection layer having first interconnects formed in a first dielectric material may have a second dielectric material deposited on the first dielectric material and the first interconnects as a part of a second interconnection layer, wherein second interconnects may be formed in the second dielectric material, etc.
As these interconnects are manufactured at smaller pitches (e.g. narrower and/or closer together), the surface area of the interconnects in a first interconnection layer contacting the dielectric layer in a second interconnection layer formed thereon increases. However, materials which are used to form interconnects, such as copper and copper containing materials, generally have poor adhesion to dielectric materials. In order to increase the adhesion between interconnects and dielectric materials, the interconnects may be roughen, such as by chemical etching, to provide physical anchoring for the dielectric material. However, poor control over the roughening process may limit the achievement of fine interconnect spacing which is crucial for high density interconnects.