The present invention relates to a multilayer wiring board which can carry a large number of LSI chips used for central processing units (CPUs) for large computers, the multilayer wiring board having via holes for supplying the power to the mounted LSIs.
Conventionally, multilayer printed wiring boards have been used for LSI chip mounted wiring boards. The multilayer printed wiring board is fabricated by alternately laminating a copper clad laminate acting as core materials and prepregs acting as an adhesive sheet and then thermally pressing the laminated structure as one piece body. In order to electrically interconnect laminated plates, after core materials and prepregs are integrally laminated, through holes are formed in the laminated structure with a drill. Then, the inner walls of the through holes are plated with copper. Usually, the multilayer printed wiring board is power supplied or grounded via the through holes.
Recently, multilayer wiring boards, in which polyimide resin acting as interlayer insulation is formed on a ceramic substrate, have been used for large computers demanding a high wiring density.
FIG. 14 is a cross-sectional view illustrating a conventional polyimide/ceramic multilayer wiring board.
A ceramic substrate 150 has through holes 151 therein each which electrically connects with an IO terminal 156. Wiring layers are formed on the surface of the ceramic substrate 150. Plural polyimide resin layers 152, each in which a power-source via hole 112 is formed, are build-up on the ceramic substrate 150.
Each polyimide resin layer 152 is made by repeating a series of steps including a polyimide-resin-layer forming step and a wiring layer forming step. The polyimide-resin-layer forming step includes the steps of coating a polyimide precursor on the ceramic substrate 150, drying it, and then forming a power-source via hole 112 in the coated film. The wiring layer forming step includes a photolithographic process, vacuum deposition, and plating.
In such a layer structure, each of the 1aM layer, the 2aM layer, the 4aM layer, the 5aM layer, and the 7aM layer acts as a signal layer. Each of the 0aM layer, the 3aM layer, and the 6aM layer acts as the grounding layer. The 8aM layer acts as a cover surface layer. A power-source conductive pattern 100a with power-source via holes 112 is formed on each of the 8aM layer, the 7aM layer, the 4am layer, and the 1aM. Similarly, a power-source conductive pattern 100b is formed on each of the 6aM layer, the 3aM layer, and the 0aM layer. A power-source conductive pattern 100c is formed on each of the 5aM layer and the 2aM layer.
In order to energize the LSI 155 assembled on the upper surface of the polyimide/ceramic multilayer wiring board with the above-mentioned structure, the power is first guided from the IO terminal 156 formed on the back surface of the ceramic substrate 150 to the 0aM layer through via holes. Moreover, the power is supplied to the soldering bump 154 through the 0aM layer and through the power-source via hole 112 of each layer and through the pad 188 on the 8aM layer being a cover surface layer.
Another mounting pad (not shown) is electrically connected with another soldering bump of the LSI 155 so that the power is electrically connected to the signal layer and the ground layer.
FIG. 15 illustrates a copper-foiled power-source conductor pattern with power-source via holes, arranged on the polyimide/ceramic multilayer wiring board shown in FIG. 14. Power-source via holes 112 are respectively formed at three points of nine points where line segments X1a, X2a and X3a dividing in the X direction of the power-source conductor pattern cross with line segments Y1a, Y2a and Y3a dividing in the Y-direction thereof. The power-source conductive pattern 100 is of the so-called 3xc3x973 matrix type. Each power-source conductive pattern 112 is formed within the via hole land 113 through a photolithographic process.
The power-source conductive pattern 100 has, for example, a square of 189 (xcexcm)xc3x97189 (xcexcm). The via hole land 113 has a square of 56 (xcexcm)xc3x9756 (xcexcm). The power-source via hole 112 has rounded corners R and is of a square of 45 (xcexcm)xc3x9745 (xcexcm).
FIGS. 16A to 16I illustrate power-source conductive patterns arranged on each of laminated layers in the polyimide/ceramic multilayer wiring board shown in FIG. 14. That is, FIG. 16I shows the bottom layer. FIG. 16A shows the top layer. The power-source conductive patterns 100a, 100b and 100c as well as the via holes 112a, 112b and 112c respectively therein are represented schematically.
FIG. 16A shows the power-source conductive pattern 100a formed on the 8aM layer covering the surface of the top layer. FIG. 16B shows the power-source conductive pattern 100a arranged on the 7aM layer on which a signal line is formed in the Y-direction. FIG. 16E shows the power-source conductive pattern 100a arranged on the 4aM layer on which a signal line is formed in the Y-direction. FIG. 16H shows the power-source conductive pattern 100a arranged on the 1aM layer on which a signal line is formed in the Y-direction. FIG. 16C shows the power-source conductive pattern 100b arranged on the 6aM layer or the ground layer connected to the ground. FIG. 16F shows the power-source conductive pattern 100b arranged on the 3aM layer or the ground layer connected to the ground. FIG. 16I shows the power-source conductive pattern 100b arranged on the 0aM layer or the ground layer connected to the ground.
Moreover, FIG. 16D shows the power-source conductive pattern 100c arranged on the 5aM layer on which a signal line is formed in the X-direction. FIG. 16G shows the power-source conductive pattern 100c arranged on the 2aM layer on which a signal line is formed in the X-direction.
Each of FIGS. 17A and 17C is a plan view schematically illustrating a conductive pattern formed on each layer.
FIG. 17A shows the power-source pattern 100a arranged on the layer on which a signal line is formed in the Y-direction. FIG. 17B shows the power-source pattern 100b arranged on the layer connected to the ground. FIG. 17C shows the power-source pattern 100c arranged on the layer on which the signal line formed in the Y-direction. Three power-source via holes 112a are arranged in the power-source conductive pattern 100a, as shown in FIG. 17A. Three power-source via holes 112b are arranged in the power-source conductive pattern 100b, as shown in FIG. 17B. Three power-source via holes 112c are arranged in the power-source conductive pattern 100c, as shown in FIG. 17C. That is, the power-source via holes 112a to 112c are positioned in such a way that the projected positions of the power-source via holes 112a to 112c are not aligned with each other when the power-source conductive patterns 100a to 100c are piled up.
The power-source conductive patterns 100a to 100c are piled up in the order shown in FIGS. 16A to 16I. The power-source via holes 112a to 112c respectively formed in the power-source conductive patterns 100a to 100c are of the same type of conductive pattern. For example, the power-source via hole 112a in the power-source conductive pattern 100a disposed on a layer having signal lines formed in the Y-direction is electrically connected to only the power-source via hole 112a in the power-source conductive pattern 100a disposed on another layer. In other type of conductive pattern, that is, both the power-source via hole 112b formed on the power-source conductive pattern 100b and the power-source via hole 112c formed on the power-source conductive pattern 100c are not electrically connected to the power-source via hole 112a in the power-source conductive pattern 100a because the power-source via hole 112a is arranged as shown in the above example.
FIG. 18 illustrates the relationship between conductive patterns formed on the 5aM layer and X-directional signal lines.
Of areas where five wiring channels can be arranged on the 5aM layer with the power-source conductive patterns 100c, only the areas where two outer signal lines, that is, the X-directional signal lines 120 and 121 act as wiring channels. Three inner signal lines act as non wiring channels because of the presence of the power-source conductive pattern 100c. 
The power-source via holes 112a to 112c are positioned in such a way that the projection positions thereof are not aligned with each other in the adjacent layer and the next adjacent layer. For example, the power-source via hole 112c on the 2aM layer is formed at a different position with respect to the power-source via hole 112a on the 1M layer (an adjacent layer), the power-source via hole 112b on the 3M layer (an adjacent layer), the power-source via hole 112a on the 0aM layer (the next adjacent layer), and the power-source via hole 112a on the 4M layer (the next adjacent layer). The reason is to solve the question that degradation of the stiffness of the portion where upper and lower via holes are aligned with each other may cause a warp of the polyimide resin layer 152, so that the reliability of via hole connection cannot be ensured.
Next, a conventional build-up board will be explained below as one example of multilayer wiring boards.
The build-up board belongs to one of multilayer wiring boards. An insulating layer of a photo-sensitive resin is formed on a multilayer printed wiring substrate using a glass epoxy resin insulator. Minute via holes are opened in the printed substrate using a photolithographic process or laser. Connection between the upper layer and the lower layer and pattern formation are performed through a plating step. Thus, the build-up board is made by sequentially piling up build-up layers. This allows LSI terminals to be arranged in high density.
FIG. 19 is a plan view schematically and partially illustrating a conventional build-up board.
The mounting pad 188b, on which a soldering bump of a LSI (not shown) is placed, is electrically connected to a signal transmission via hole 189 for signal transmission formed within a via hole land 190. The mounting pad 188a is electrically connected to a signal transmission via hole 187b formed within a via hole land 190.
The via hole land 190 has a dimension of 0.075 (mm)xc3x970.075 (mm). The signal via hole 189 has a diameter of 0.05 mm. The power-source via hole 187b has a diameter of 0.05 mm. The build-up board has a ground via hole (not shown) of a diameter of 0.05 mm and a via hole land (not shown) of a diameter of 0.05 mm.
However, in order to deal with an increased number of signals connected between LSIs with the recent trend toward high density, it is required to increase the number of wiring channels per layer within a limited number of wiring layers. The number of via holes for power supplying or grounding has to be reduced as small as possible. Meanwhile, the voltage necessary for operation of an LSI has to be maintained, with an electric resistance suppressed between the power supply pin on the back surface of the base substrate and the LSI. This leads to increasing the diameter of a via hole or to increasing the number of via holes for power supplying and for grounding as degree as possible. There is a contradiction between that approach and a demand for increasing the number of wiring channels.
In the conventional structure, a plurality of via holes are uniformly arranged in a matrix form of 3xc3x973 to one power supply pin of an LSI, independently of the layer structure. In the 3xc3x973 type arrangement, as shown schematically in FIG. 18, the case often occurs where, of areas where five wiring channels are disposed, only two outer lines are wiring channels while the inner three power-source lines are wiring channels because of the presence of the power-source conductor pattern 100c. In the case of the 3xc3x973 conductive pattern, since an increasing number of LSI pins leads to increasing not only signal lines but also power supply terminals, the number of signals to be wired increases. However, in that case, it becomes difficult to increase the number of wiring channels because of the presence of a conductive pattern in which via holes are formed. The number of wiring channels may be increased by densely making the wiring grid or increasing the number of wiring layers. However, this approach results in increased costs due to degradation in product quality.
In order to fully power-supply or ground LSIs on the build-up board, a single power-source via hole or grounding via hole having the same diameter as that the signal via hole formed one via hole land has a high resistance, so that an necessary voltage cannot be often supplied. In order to decrease the resistance, it is necessary to increase the size of a via hole. However, formation of a through hole in the build-up layer makes it difficult to deal with a high dense assembly being the feature of the build-up board.
The objective of the invention is to provide a multilayer wiring board that can increase wiring channels in a wiring layer and can secure power-source via holes needed for power supplying.
A second object of the invention is to provide a multilayer wiring board that has via holes for power-supplying and grounding, each having a decreased electric resistance.
In achieve the above mentioned objectives, a multilayer wiring board according to the present invention comprises a first wiring layer having a first wiring pattern; a second wiring layer having a second wiring pattern; the wiring direction of the first wiring pattern and the wiring direction of the second wiring pattern being substantially perpendicularly to each other, the first wiring layer and second wiring layer being laminated; and a plurality of conductive patterns formed on each of the first and second wiring layers in such a way that each of long sides is oriented substantially in the same direction as the wiring direction of a wiring pattern formed on each wiring layer, each of the conductive patterns in which a plurality of via holes are formed, each of the conductive patterns having a nearly rectangular form.
In the multilayer wiring board with the above-mentioned structure according to the present invention, the long side of a rectangular conductive pattern on which via holes are formed is oriented substantially in the same direction as that of the wiring pattern. The area occupied by a wiring pattern in the arranged direction on a conductive pattern on which the long side is oriented substantially the same direction as the direction of the wiring pattern is small, compared with the occupied area of a conventional rectangular conductive pattern.
The position at which each via hole in each of the conductive patterns formed on the first wiring layer is projected may not aligned with a position at which each via hole in each of the conductive patterns formed on the second wiring layer. This structure can avoid electrically interconnecting wiring layers on which wiring patterns are formed in different directions.
Moreover, the long side of each of the conductive patterns may correspond to the length along which at least three via holes can be formed. The short side of each of the conductive patterns may correspond to the length along which at least two via holes can be formed. In this case, at least two via holes may be formed in each of the conductive patterns.
Moreover, according to the present invention, the multilayer wiring board comprises a first wiring layer and a second wiring layer laminated to each other; a plurality of first conductive patterns arranged on the first wiring layer, each of the plurality of first conductive patterns having a plurality of power-source via holes; and a plurality of second conductive patterns arranged on the second wiring layer, each of the plurality of second conductive patterns having a plurality of power-source via holes at positions which are not aligned with positions where the via holes in the first pattern are projected.
In the multilayer wiring board with the above-mentioned structure according to the present invention, plural power-source via holes are formed in the conductive pattern, so that the electric resistance upon power supplying can be reduced.
Furthermore, according to the present invention, the multilayer wiring board comprises a first wiring layer and a second wiring layer laminated to each other; a plurality of first conductive patterns arranged on the first wiring layer, each of the plurality of first conductive patterns having a plurality of grounding via holes; and a plurality of second conductive patterns arranged on the second wiring layer, each of the plurality of second conductive patterns having a plurality of grounding via holes at positions which are not aligned with positions where the via holes in the first pattern are projected.
In the multilayer wiring board with the above-mentioned structure according to the present invention, plural grounding via holes are formed in the conductive pattern, so that the electric resistance upon power supplying can be reduced.