The on-resistance Ron of vertical MOS transistor elements is dependent on the length of the current path within the silicon substrate of the semiconductor element, i.e. on the thickness of the substrate (chip). Therefore, in the manufacturing of such semiconductor elements thinning of the silicon wafer is known as a means for reducing the resistance. Using conventional thinning processes, such as grinding, etching or CMP (Chemical-Mechanical-Polishing), thickness values down to about 50 μm can be achieved.
Tf thinning a semiconductor wafer to such low thickness, as well as subsequent acts, such as implantation steps or metallization steps, generally require provision of a suitable support system to handle the very thin and, therefore, highly bendable wafer, protecting it from damage in the course of the several handling steps. Conventional support systems rely on a certain, although not fully sufficient, degree of internal mechanical stability of the wafer. For this reason, among others, the presently achievable minimum thickness of thin semiconductor elements is limited.