1. Field of the Invention
The present disclosure generally relates to the fabrication of semiconductor devices, and, more particularly, to a method for reducing gate height variation due to overlapping masks.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area. In integrated circuits fabricated using metal-oxide-semiconductor (MOS) technology, field effect transistors (FETs) (both NMOS and PMOS transistors) are provided that are typically operated in a switching mode. That is, these transistor devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). FETs may take a variety of forms and configurations. For example, among other configurations, FETs may be either so-called planar FET devices or three-dimensional (3D) devices, such as finFET devices.
A field effect transistor (FET), irrespective of whether an NMOS transistor or a PMOS transistor is considered, and irrespective of whether it is a planar or 3D finFET device, typically comprises doped source/drain regions that are formed in a semiconductor substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. The gate insulation layer and the gate electrode may sometimes be referred to as the gate structure for the device. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region. To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the FET as an active switch is degraded.
In contrast to a FET, which has a planar structure, a so-called finFET device has a three-dimensional (3D) structure. FIG. 1A is a perspective view of an illustrative prior art finFET semiconductor device 100 that is formed above a semiconductor substrate 105. In this example, the finFET device 100 includes two illustrative fins 110, 112, a placeholder gate structure 115 (e.g., polysilicon with an underlying gate insulation layer (not shown)), sidewall spacers 120 (e.g., silicon nitride), and a gate cap 125 (e.g., silicon nitride). When employing a gate replacement fabrication technique, the placeholder gate structure 115 is subsequently replaced with a high-k gate insulation layer and one or more metal materials to serve as a gate electrode for the device. The fins 110, 112 have a three-dimensional configuration. The portions of the fins 110, 112 covered by the gate structure 115 define channel regions for transistor devices. An isolation structure 130 is formed between the fins 110, 112.
As illustrated in FIG. 1B, in a conventional process flow, the portions of the fins 110, 112 that are positioned outside of the spacers 120, i.e., in the source/drain regions of the device 100, may be increased in size by performing one or more epitaxial growth processes to form epitaxial semiconductor material 135 on the fin 110 and epitaxial semiconductor material 140 on the fin 112. The process of increasing the size of the fins 110, 112 in the source/drain regions of the device 100 is performed to reduce the resistance of source/drain regions and/or make it easier to establish electrical contact to the source/drain regions.
In some devices, such as memory devices, the fin 110 is associated with an N-type transistor device, and the fin 112 is associated with a P-type transistor device, while the gate structure 115 is shared by the devices. The type of epitaxial semiconductor material 135, 140 employed is different for the different types of transistor devices. Typically, a first mask is used to cover the fin 112 while the epitaxial semiconductor material 135 is grown. The first mask is removed and a second mask is employed to cover the epitaxial semiconductor material 135 to allow the epitaxial semiconductor material 140 to be grown on the fin 112. Due to the etch processes for removing the masks and imperfect alignment, a bump feature 145 is typically formed in an overlap region at the boundaries of the first and second masks. This bump feature 145 may be formed from remnants of the masks and from material loss in the cap layer 125.
FIG. 1C illustrates a cross-sectional view of the finFET device 100 and a second finFET device 150 in a different region of the integrated circuit product. The cross-sectional view of FIG. 1C is taken through the fin in the gate length direction of the two transistor devices 100, 150. The device 100 includes transistor devices having different types with a shared gate structure 115. Due to the overlapping masks employed to grow the different epitaxial materials on the fins of differing conductivity types, a bump feature 145 is present above the gate structure 115 of the device 100. In contrast, the device 150 represents a device with fins associated with transistor devices having the same conductivity type, so overlapping masks are not used and no bump feature 145 is present.
In a gate replacement technique, a planarizing process is employed to expose the placeholder gate structures 115 of both devices 100, 150 so that they can be removed and replaced with a conductive material, such as metal. Due to the absence of a bump feature 145 on the device 150, the polishing process exposes the placeholder structure 115 more quickly, resulting in dishing of the device 150 and a lower gate height as compared to the device 100, as illustrated in FIG. 1D. A similar disparity can arise in regions with different device densities, and as a result different bump densities. The region with a lower bump density is planarized more aggressively and more quickly than the region with higher bump density, so more dishing occurs and the gate height is comparatively reduced. In some instances, due to the bump height differences, the placeholder structure 115 may be incompletely exposed, resulting in the formation of defects during the gate replacement process.
The present disclosure is directed to various methods and resulting devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.