Field effect transistors (FET's) are a fundamental building block in the field of integrated circuits. FET's can be classified into two basic structural types: horizontal and vertical. Horizontal, or lateral, FET's exhibit carrier flow from source to drain in a direction parallel (e.g., horizontal) to the plane of the substrate and vertical FET's exhibit carrier flow from source to drain in a direction transverse to the plane of the substrate (e.g., vertical) on which they are formed. FET structures may include a single gate (e.g., for forming a single channel) or a pair of gates (e.g., for forming a pair of channels), with double-gate versions providing an advantage of an increased current carrying capacity (e.g. typically greater than twofold over the single-gate versions).
A FET typically consists of source and drain electrodes interconnected by semiconductor material. Conduction between the drain and source electrodes occurs basically within the semiconductor, and the length between the source and drain is the conduction channel. In particular, the output current is inversely proportional to the channel length, while the operating frequency is inversely proportional to the square of the channel length.
The basic metal-oxide-semiconductor field-effect transistor (MOSFET) structure has a so-called “flat design”. A nFET structure is a four-terminal device and consists of a p-type semiconductor substrate, into which two n-regions, a source electrode and drain electrode are formed (e.g., by ion implantation). The metal contact on the insulator is a gate. Heavily doped polysilicon or a combination of silicide and polysilicon can also be used as the gate electrode.
The basic device parameters are the channel length L, which is the distance between the two metallurgical n-p junctions, the channel width W, the gate oxide thickness t, the junction depth, and the substrate doping. When voltage is applied to the gate, the source-to-drain electrodes correspond to two p-n junctions connected back to back. The only current that can flow from source to drain is the reverse leakage current. When a sufficiently positive bias is applied to the gate so that a surface inversion layer (or channel) is formed between the two n-regions, the source and the drain are connected by the conducting surface of the n-channel through which a current can flow.
It is known, though, that the nFETs are optimized in the horizontal plane of the substrate. That is, the electron mobility across the channel is optimized when the nFET is fabricated on the 100 plane and the 110 direction. This is a typical flat structure fabrication. The pFET device, on the other hand, has significantly decreased performance characteristics when it is fabricated on the 100 plane and the 110 direction; namely, the hole mobility is significantly decreased, thereby degrading the performance of the entire device. However, it is typical in semiconductor fabrication to build both the nFET and pFET structures in the 100 plane and the 110 direction, using well-known processes.