1. Field of the Invention
The present invention relates to an apparatus and a method for automatically controlling the gate bias voltage for Field Effect Transistor (FET) devices, and, more particularly in FET high power amplifiers.
2. Description of the Prior Art
High power amplifier circuits often use FETs in their output and driver stages. Generally, VDMOS (vertical double-diffused MOS) FET transistors are used for frequencies up to 500 MHZ and LDMOS (laterally diffused MOS) FET transistors are used for frequencies above 500 MHZ. For the best linearity, these high power amplifiers typically operate in Class A mode. Class A amplifiers are defined as having current flowing in all of the output transistors for the entire 360 degrees of an input cycle at the full, unclipped output of the amplifier. To achieve this, the output stage is biased halfway between the cutoff value and the saturation value and the load impedance is set at a value providing the maximum undistorted output power. Thus, the output transistors require a particular positive gate bias voltage for optimal operation in the amplification mode. The gate bias voltage sets the nominal current through the channel of the transistors.
Characteristically the gate bias voltage of the transistors may vary substantially from unit to unit and from lot to lot. With the threshold gate voltage variations in the range from 1 to 7 volts, the resultant operating gate voltage is typically in the range from 3 to 9 volts. In amplifiers using a balanced circuit design with complementary output drive circuitry, there is a requirement for balancing the transistor behavior between the two branches of the balanced amplifier. This balancing is important as the third order distortion of the amplifier is minimized thereby. Normally this balancing is sufficiently satisfied when the quiescent drain current of the output transistor is equal for both branches.
Presently, the standard methods for controlling gate bias voltage include using: (1) potentiometer in a voltage divider circuit or (2) a voltage regulator with a potentiometer in a voltage divider circuit at the output of the voltage regulator or (3) a potentiometer to program the output of a variable voltage regulator. The structural disadvantages of these methods, all of which require a potentiometer, is twofold, namely, component reliability and circuit optimization. The disadvantages of component reliability is inherent by including a mechanical component—the potentiometer—in the circuit. The disadvantage of circuit optimization is that the process introduces compromise into circuit performance as the circuit is tuned for a single operating point. Further, the standard methods have the economic disadvantage of requiring labor to tune the circuit.
In the past, several methods have developed for providing matched performance in a pair of transistors for a balanced amplifier. In one method, transistors are selected at the factory for matched electrical characteristics and are packaged as a pair of matched transistors in a single package. Another approach is to fabricate matched transistors on a common substrate. These methods all carry a cost penalty for the test and select function of for the smaller batch size inherent in common substrate production. Also, the commercially available matched-characteristic transistors are limited to what is made available by the factory. Alternately, when transistors are sorted for matching characteristics by the end user, besides incurring the same labor cost penalty, there is the additional risk of purchasing unusable devices, especially of the transistors are widely divergent in electrical characteristics.
As described in the standard methods hereinabove, providing matched performance in transistors that are not inherently matched is accomplished with potentiometers to tune the gate voltages. This tuning is either directly through a voltage divider or indirectly through a variable voltage regulator. Although this allows the use of a wider range of transistors than the factory sorting methods, these methods also have the penalty of a labor cost.
One example of a FET gate voltage biasing circuit is taught by U.S. Pat. No. 6,288,613 to J. H. Bennett entitled BIAS CIRCUITS FOR DEPLETION MODE FIELD EFFECT TRANSISTORS, issued Sep. 11, 2001, which discloses a FET-based circuit that provides a controlled gate bias voltage for maintaining a set drain current in the gate-biased depletion mode FET. Additionally, this circuit maintains the selected drain current over temperature variations and again effects on the performance characteristics upon the FET. One embodiment of this circuit is also capable of providing the bias voltage for multiple FETs.
A significant drawback to the circuit taught by the '613 patent is that it requires the FETs that comprise the active elements of the circuit to all be manufactured by the same process and be integrated with one another. Such similar performance characteristics are found generally only when all of the active circuit elements formed as one integrated circuit. This patent does not teach a circuit for unmatched components and the circuit is not likely to function properly if manufactured from discrete devices.
Another example of a FET gate voltage biasing circuit is taught by U.S. Pat. No. 6,091,302 of A. Arevalo, issued Jul. 18, 2000, entitled ELECTRONIC CIRCUIT BIASING CONTROL SYSTEM which discloses a digital biasing and monitoring system for controlling the gate bias voltages of one or more FETs. This circuit monitors both drain current and ambient temperature and provides a gate bias voltage to an FET based on these monitored quantities.
The circuit taught by this patent requires considerable digital electronics to function, including a microprocessor, an A/D converter and a D/A converter. Further, Arevalo 302 is based on look-up tables programmed into the microprocessor for desired FET gate bias voltages at each increment of drain current and temperature variation.
Another FET gate voltage biasing circuit is taught by H. Sakamoto in U.S. Pat. No. 6,486,724 issued Nov. 26, 2002 and entitled FET BIAS CIRCUIT, which patent discloses a bias circuit including an operational amplifier and a reference voltage. This circuit performs closed-loop control of the FET gate voltage with the output of the operational amplifier. Further, careful choices in resistance values and temperature coefficients of the resistors in the voltage divider that comprises the reference voltage source can enable this circuit to also control the FET gate voltage versus ambient temperature changes.
One drawback to the circuit taught by the '724 patent is the use of a resistive voltage divider connected to a voltage supply rail as the reference voltage source. Here, upon a variation in the voltage supply, there is a corresponding variation in the reference voltage that is supplied to the operational amplifier. Thus, such variation results in a FET gate bias voltage shift from the desired level. Further, the closed-loop control performed by this circuit is dependent upon the voltage drop at a current limiting resistor and not from the drain-source path of the FET. This is therefore an indirect closed-loop control.
Another example of a FET gate voltage biasing circuit is taught by Poulin et al., U.S. Pat. No. 6,304,130 entitled BIAS CIRCUIT FOR DEPLETION MODE FIELD-EFFECT TRANSISTORS which discloses a bias circuit with a voltage offset circuit a transistor, a resistive path, and two power supply connections. Here, the voltage offset circuit ensure that the transistor of the bias circuit operates on a similar regime as the biased power transistor allowing both transistors to track process variations.
A significant improvement over the existing art would be a transistor biasing scheme that automatically provided a reliable and controlled gate bias voltage that remained optimized over the desired range of circuit performance and that protected the transistors from damage in cases of excessive supply voltages or excessive operating temperatures. Additionally, it would be desirable to have this transistor biasing scheme function both for pairs of matched or unmatched transistors such that the unmatched transistors performed like matched transistors over the full range of expected use conditions.
None of the above provide the automatic biasing and protection for field effect transistors utilizing the circuitry of this invention. The submission of the above discussion of documents is not intended as an admission that any such document constitutes prior art against the claims of the present application. Applicant does not waive any right to take any action that would be appropriate to antedate or otherwise remove any listed document as a competent reference against the claims of the present application.