1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device. More particularly, it relates to a method for manufacturing a semiconductor device having a triple-well structure to be used for a flash memory and the like to erase data by applying a negative bias.
2. Related Arts
A conventional method for manufacturing a typical semiconductor device having a triple-well structure is disclosed in, for example, Japanese Unexamined Patent Publication No. Hei 5 (1993)-283629. Hereafter, this conventional method is described with reference to FIGS. 5(a) to 5(c) and FIGS. 6(a) to 6(c).
First, a resist mask 12a is formed on a surface of a p-type silicon substrate 11 as a mask for forming an n-type well layer 13. A first ion implantation of phosphorus ions into the p-type silicon substrate 11 is then carried out with an implantation energy of 120 KeV in a dose of 6.times.10.sup.12 cm.sup.-2 (FIG. 5(a)). After removal of the resist mask 12a, the silicon substrate 11 is subjected to an annealing treatment at 1150.degree. C. for 20 hours to form the n-type well layer 13 (FIG. 5(b)). At this stage, the depth of the n-type well layer 13 is about 6 .mu.m and the impurity concentration in the surface of the n-type well layer 13 is about 1.times.10.sup.16 to 2.times.10.sup.16 cm.sup.-3.
Next, in order to form an n-type well layer 14 having a high impurity concentration, a resist mask 12b is formed having the same pattern as the resist mask 12a used in the process of the first ion implantation. Then, a second ion implantation of phosphorus ions into the n-type well layer 13 is carried out with an implantation energy of 8 MeV in a dose of 1.times.10.sup.13 cm.sup.-2. The n-type well layer 14 having an high impurity concentration is formed in the previously formed n-type well layer 13 at a depth of 5 to 6 .mu.m from the surface of the p-type silicon substrate 11 (FIG. 5 (c)). Then, the resist mask 12b is removed.
Next, a resist mask 12c is formed as a mask to form a p-type well layer. Then, a third ion implantation of boron ions is carried out into the n-type well layer 13. The third ion implantation of boron ions is carried out four times with an implantation energy of 140 KeV, 340 KeV, 600 KeV and 800 KeV each in a constant dose of 2.times.10.sup.12 cm.sup.-2 to form a boron implanted region 15a having a multi-layer structure in the n-type well layer 13. The boron implanted region 15a having the multi-layer structure has a peak concentration of the implanted boron at a depth of 0.4 .mu.m, 0.8 .mu.m, 1.2 .mu.m and 1.6 .mu.m (FIG. 6(a)).
The resist mask 12c is then removed and an annealing treatment is carried out, for example, at 1100.degree. C. for 10 hours to form the p-type well layer 15b, thereby providing a semiconductor device of a triple-well structure (FIG. 6(b)).
Thereafter, an n.sup.+ -type diffusion layer 17 is formed as a source/drain constituting a transistor in the surface layer of the p-type well layer 15b, and a gate 16 is formed over a channel region between the source and the drain. Further, a terminal 18 adding a bias to the formed p-type well layer 15b and a terminal adding a bias 19 to the formed n-type well layer 13 are formed in the surface layer of the p-type well layer 15b and the n-type well layer 13, respectively (FIG. 6(c)).
The semiconductor device having the conventional triple-well structure mentioned above has problems described below.
First, in the case that a peak impurity concentration is high in the n-type well layer 14, there will be a decrease in a voltage (hereafter referred to as a breakdown voltage of on-state (BV on)) at which the elements constituting the semiconductor device start to operate as a parasitic bipolar transistor. The operation principle of the parasitic bipolar transistor is described with reference to FIG. 7. When an inverse voltage is applied between the n-type well layer 14 and the p-type well layer 15b and a noise of a forward bias is applied between the n.sup.+ -type diffusion layer 17 and the p-type well layer 15b, the n.sup.+ -type diffusion layer 17 functions as an emitter, the p-type well layer 15b functions as a base and the n-type well layer 14 functions as a collector. A set of the emitter, the base and the collector is called as the parasitic bipolar transistor. In this case, when the inverse voltage applied between the n-type well layer 14 and the p-type well layer 15b is larger than the BV on, a breakdown current flows inside each well layer. This break-down current could destroy the transistor formed on the surface of the p-type well layer 15b.
On the other hand, when a dose of ion implantation is decreased in order to lower the impurity concentration in the n-type well layer 14, a sheet resistance of the n-type well layer 14 increases. Also, when a concentration of the impurity in the n-type well layer 14 is low, a punch-through occurs between the p-type well layer 15b and the p-type silicon substrate 11. Therefore, it is necessary to precisely control a distribution of the impurity concentration in the n-type well layer 14.
However, in the conventional method, an annealing treatment is conducted at a high temperature for a long time to form the n-type well layer 13 and a drive-in diffusion treatment is conducted at a high temperature for a long time to form the p-type well layer 15b and to optimize an impurity concentration in the n-type well layer 14. Accordingly, the concentration of the n-type well layer 14 can be optimized but, at the same time, the n-type well layer 14 and the p-type well layer 15b spread horizontally, so that a whole well area becomes broader. Therefore, it is difficult to achieve size reduction of a peripheral circuit.
Second, in the conventional method, since the p-type well layer 15b is formed in the previously formed n-type well layer 13, the p-type impurity ions need to be implanted at a sufficiently high concentration for canceling the conductivity of the n-type well layer 13 in order to form the p-type well layer 15b as shown in FIG. 4(a). Accordingly, there is a problem such that the impurity concentration in the surface of the silicon substrate 11 becomes high. In FIG. 4(a), symbol A represents a distribution of the impurity concentration in the p-type well layer 15b, symbol B represents a distribution of the impurity concentration in the n-type well layer 13 and symbol C represents a distribution of the impurity concentration in the n-type well layer 14.
Third, in order to suppress the operation of the parasitic bipolar transistor, it is necessary to achieve a high BV on. To this end, it is necessary to anneal at a high temperature for a long time after the ion implantation, as is apparent from FIG. 3 showing a relationship between an annealing time for forming the n-type well layer 14 and the BV on.
However, a well area becomes broader if the annealing is conducted at a high temperature for a long time, so that it is difficult to achieve size reduction of a peripheral circuit.