(1) Field of the Invention
The present invention relates to a power supply circuit for a dynamic random access memory (hereinafter referred to as a "dynamic RAM"), and more particularly to a power supply circuit for a dynamic RAM having an internal power supply circuit for generating an internal power supply potential lower than an external power supply potential and a circuit for generating an intermediate potential which is one half of the internal power supply potential.
(2) Description of the Related Art
In the actual use of the dynamic RAMs, with the advancement of a higher integration thereof, the potential of an opposing electrode of a capacitor constituting a memory cell is set to an intermediate potential between a power supply potential and a ground potential from such a stand point as increasing reliability. In a dynamic RAM of 16 M-bits, it has reached to a point where one having an internal power supply circuit to generate a power supply potential lower than an external power supply potential is available. In that arrangement, the external power supply potential is generally 5 V but the internal power supply potential is used after it is lowered to 3.3 V. In this connection, the intermediate potential is set to 1.65 V which is an intermediate value between the internal power supply potential of 3.3 V and the ground potential.
FIG. 1 shows in a block diagram a conventional power supply circuit for a dynamic RAM, which has an internal power supply circuit and an intermediate potential generating circuit as described above.
The internal power supply circuit 2 receives an external power supply potential of 5 V and generally produces an internal power supply potential V.sub.INT of 3.3 V. The intermediate potential generating circuit 4a receives the internal power supply potential V.sub.INT and generates an intermediate potential V.sub.H which is one half the internal supply potential V.sub.INT.
The intermediate potential V.sub.H which is driven by the internal power supply potential V.sub.INT is stable and not influenced by any fluctuations of the external power supply potential V.sub.CC, which results in an increase in an operation margin or tolerance of the circuit to which the intermediate potential V.sub.H is supplied. However, when the power supply is switched on, there inevitably occurs a delay in the rise time of the internal power supply potential V.sub.INT because it rises in response to the external power supply potential. Further, since the intermediate potential generating circuit 4a has been designed to operate at a low potential and a low power consumption, the driving capability thereof is accordingly small so that it takes a time before the intermediate potential V.sub.H reaches a predetermined potential.
On the other hand, as for the rise time of the intermediate potential V.sub.H, there is a requirement for this to be usable within 100 .mu.S after the rising of the external power supply potential V.sub.CC. In order to meet such requirement, it is necessary to make the intermediate potential generating circuit 4a sufficiently large for maintaining the corresponding driving capability.
In the conventional power supply circuit for the dynamic RAM described above, the internal power supply potential is received and then the intermediate potential V.sub.H is generated so that, after the power is switched on, it takes a time for the intermediate potential V.sub.H to reach a predetermined potential. Any attempt to make such time shorter will inevitably result in an increase in current consumption. These are problems to be solved by this invention, in the conventional power supply circuit for the dynamic RAM.