1. Field of the Invention
The present invention relates to the fabrication of a heterojunction bipolar transistor (HBT) and more specifically to a submicron emitter HBT with limited parasitics and a fully self-aligned process for fabricating the same.
2. Description of the Related Art
An HBT is a bipolar transistor with at least two adjacent layers of different chemical composition but of similar crystalline structure. Typically, the emitter layer is made of a wider bandgap material than the base to provide an energy barrier for holes flowing from the base to the emitter that is greater than the energy barrier for electrons flowing in the opposite direction. This inhibits the flow of holes into the emitter, allowing for high base doping and a low base resistance. Also, the emitter can have low doping, resulting in a thick base-emitter depletion layer and low emitter-base capacitance. This improves the emitter efficiency and the current gain of the HBT.
HBTs are generally fabricated by growing lattice matched layers on a semiconductor substrate by molecular beam epitaxy (MBE) or a similar technique. Design variations for each layer include its composition, doping concentration, thickness and defect density. Electrical contacts are made to the emitter, base and collector layers, and the transistor is isolated from the layers outside the transistor region. Typically, a contact is made to the emitter directly from its top surface. To contact the base, the top layers of the transistor are etched and a metal film is deposited directly on the base layer. An alternate method of contacting the base is to change the doping of the structure's top layers by ion implantation of acceptors. Contact to the collector is usually made by etching through the upper epitaxial layers down to a sub-collector layer which is between the substrate and the collector. A contact is then made to the sub-collector. The problem with this method is that a considerable etch depth is required to reach the sub-collector.
It is also necessary to isolate the transistor from other devices on the substrate. This can be done by inducing lattice damage to the layers outside the transistor region through ion-implantation and making them semi-insulating. This however can damage the substrate and ion-implantation technology is not available for all materials. An alternate isolation procedure is to etch the epitaxial layers around the transistor to form a mesa on a semi-insulating substrate. Also, etched gaps at the transistor region's edges can be filled with dielectric or planarizing materials to achieve a planar device.
Parasitic elements associated with an HBT can degrade its speed and increase power consumption. One of the most significant parasitic elements is the extrinsic region base-collector capacitance, which is the space charge layer capacitance between the base and the collector layers extrinsic to the transistor's active region (the active region lies under the emitter and is referred to as the intrinsic region). The device's speed and performance can be improved and its frequency response increased by limiting the size of the extrinsic region and thus limiting its base-collector capacitance. However, it is difficult to eliminate the extrinsic region because it supports the base contact.
There are several well known ways to reduce the HBT dimensions which mainly concentrate on reducing the emitter dimensions. They include defining the emitter dimensions by metal lift-off. There is, however, a limit to how small a feature size can be defined by metal lift-off. Another method includes dry-etching with a dielectric mask to define the minimum feature size. However, this approach requires multiple metalization steps and lift-off or dry etchins of the metal layers to define the base and collector ohmic contacts. Furthermore, the collector metal will not be self-aligned to the emitter mesa when using the dry-etching technique.
One specific method of fabricating a self aligned AlGaAs/GaAs HBT is disclosed in Won-Seong Lee et. al., "Submicrometer Self-Aligned AlGaAs/GaAs Heterojunction Bipolar Transistor Process Suitable for Digital Applications", IEEE Transactions On Electron Devices, Vol 39, No. 12, December 1992, pages 2694-2700. The process, after forming a subcollector, collector, base, emitter and emitter cap layer in sequence on a substrate by MBE, includes; a) formins a dummy emitter mesa and an external base by photolithography, b) deposition of a base metal and electron cyclotron resonance (ECR) plasma deposition of oxide, c) removal of the exposed base metals deposited on a sidewall region by ECR plasma deposition of oxide and ECR plasma etching by NF.sub.3, d) planarization of the device with a photoresist, e) etch back of the photoresist, and f) defining the emitter metal region. Although this process is claimed to produce a submicrometer AlGaAs/GaAs HBT, it has several problems. Primarily, the process does not produce a fully self-aligned HBT with the collector, base and emitter contacts aligned together. Rather, only the base and emitter are self-aligned. This results in more than one metalization process, increasing the tolerance associated with the metalizations. Furthermore, a thin Ti layer is evaporated and a tungsten layer is sputtered onto P+ GaAs to form the base metal of step b above; this requires a special sputtering system which is expensive. Removal of exposed base metals from the sidewalls using ECR as in step d above also requires expensive and complicated procedures.