In a computer system, various buses are provided for interconnecting a host processor(s) and other devices and transferring data among them. As an example, PCIe has been developed for replacing the older Peripheral Component Interconnect (PCI) and PCI-X standards. PCIe is used in consumer, server, and industrial applications as a motherboard-level interconnect to link motherboard-mounted peripherals and as an expansion card interface for add-in boards.
A difference between PCIe and earlier PC1 or PCI-X buses is a topology based on point-to-point serial links, rather than a shared parallel bus architecture. PCIe can be thought of as a high-speed serial replacement of the older parallel PC1 and PCI-X bus. At the software-level, PCIe preserves compatibility with PC1 so that a PCIe device can be configured and used in legacy applications and operating systems which have no direct knowledge of the new features of PCIe.
In PCIe 1.0 or 1.1, each lane carries 250 MBIs. PCIe 2.0, released in late 2007, adds a second generation signaling mode, doubling the rate to 500 MBIs. PCIe 3.0, currently in development, will add a third generation signaling mode at 1 GBIs.
PCIe 2.0 and 3.0 also maintain compatibility with the earlier generation of PCIe (i.e., PCIe 1.x). Since PCIe 1.x compatible devices are still being used in the market, PCIe 2.0 or 3.0 compatible devices may need to be connected with PCIe 1.x compatible devices. Upon power up or in certain conditions, the devices at both ends of the link perform link training and initialization. Conventionally, for backward compatibility with PCIe 1.x, the PCIe 2.0 or PCIe 3.0 devices initially advertise themselves as PCIe 1.1 devices. Upon training the PCIe link, the software determines whether the device on the other end of the link supports the PCIe 2.0 or PCIe 3.0 specification. If so, part of the training sequences have to be repeated with the PCIe 2.0 or PCIe 3.0 settings that were initially advertised with PCIe 1.1 settings. This is not desirable because of the high software overhead required to support the compatibility with the PCIe 1.x compatible devices.