1. Technical Field
The techniques described herein relate to techniques for reducing the complexity of delta sigma (ΔΣ) modulator circuits such as continuous time (CT) ΔΣ modulator circuits in CT ΔΣ analog-to-digital converters (ADCs).
2. Discussion of the Related Art
Delta sigma (ΔΣ) analog-to-digital converters (ADCs) have become more popular because they overcome some inherent problems of other types ADCs. For example, other types of ADCs may inconveniently require highly accurate analog circuitry. In contrast, ΔΣ ADCs relax the requirements on analog circuitry at the tolerable expense of a higher sampling frequency. However, ΔΣ ADCs exhibit several non-idealities, such as excess loop delay (ELD). The ELD may be caused by the non-ideal nature of electronic components, such as transistors, in ΔΣ ADCs. For example, ELD may be introduced by the non-zero switching time of transistors in the ΔΣ ADC. The ELD undesirably causes the overall signal and noise transfer function of the ΔΣ ADC to be shifted. Thus, ΔΣ ADCs typically include circuitry for ELD compensation to reduce the ELD in the ΔΣ ADC. The ELD compensation circuitry typically compensates for the ELD through a feedback loop where a delayed version of an output digital code is combined with a current version of another digital code in the ΔΣ ADC to form the output digital code.