Various methods are known for bonding an integrated circuit (IC) die to a package substrate, such as printed circuit board (PCB). The surface of the package substrate generally includes a solder mask material in areas outside the metal land pads. Solder mask over conventional copper traces prevents copper oxidation, masks against solder spreading around the solder joints, and provides enhanced adhesion to the later applied underfill that is generally injected under the IC die after the bonding process. During flip-chip (FC) packaging, the IC die is turned upside down to connect the active circuit comprising top of the IC die to the metal land pads on the package substrate surface. In contrast, when packaging IC die having through substrate vias (TSVs), the IC die is mounted active circuit comprising top side up to connect to the TSVs accessible from the bottom of the IC die to the land pads on the package substrate surface. In either case, the metallic joints formed generally include solder provided by at least one of the IC die and the package substrate. Following the mounting of the IC die, capillary underfill is generally used to fill the volume that is generally referred to as an “underfill gap” that is between the mounted IC die and the package substrate.
One packaging challenge is related to void-free underfilling, particularly when the height of the underfill gap is small (e.g., <20 μm). Narrow gaps challenge capillary underfill flow, and tend to produce underfill voids in tight areas concentrated primarily in the die attach region under the IC die near the center of the die. As known in the art, underfill voids can lead to reliability failures. For example, chip scale package (CSP)/package on package (POP) technologies can result in a very small underfill gap, for small pitched pads and particularly for stud collapse (e.g., Au) to the FC land pad on the package substrate during ultrasonic bonding. This issue can be even more challenging for Au-to-Au interconnect technology.
Another assembly concern during IC die mounting is that the IC die can hit the top of the solder mask in the die attach region lateral to land pads, and result in damage to the active circuitry on the top surface of the IC die. The IC die hitting the top of the solder mask can also result in laterally offsetting the joint, which is known to increase the resistance of the joint, and in extreme cases can result in open circuits.