1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various methods of forming SRAM (Static Random Access Memory) devices using sidewall image transfer techniques.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements, such as transistors, resistors, capacitors, etc., in a given chip area according to a specified circuit layout. A field effect transistor (FET) is a planar device, irrespective of whether an NMOS transistor or a PMOS transistor is considered, that typically includes doped source and drain regions that are formed in a semiconducting substrate that are separated by a channel region. A gate insulation layer is positioned above the channel region and a conductive gate electrode is positioned above the gate insulation layer. By applying an appropriate voltage to the gate electrode, the channel region becomes conductive and current is allowed to flow from the source region to the drain region.
In contrast to a FET, which has a planar structure, there are so-called 3D devices, such as FinFET devices, which are 3-dimensional structures. More specifically, in a FinFET, a generally vertically positioned fin-shaped active area is formed and a gate electrode encloses both sides and an upper surface of the fin-shaped active area to form a tri-gate structure so as to use a channel having a 3-dimensional structure instead of a planar structure. In some cases, an insulating cap layer, e.g., silicon nitride, is positioned at the top of the fin and the FinFET device only has a dual-gate structure. Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to reduce the physical size of the semiconductor device. Also, in a FinFET, the junction capacitance at the drain region of the device is greatly reduced, which tends to reduce at least some short channel effects.
Numerous processing operations are performed in a very detailed sequence, or process flow, to form such integrated circuit devices, e.g., deposition processes, etching processes, heating processes, masking operations, etc. In general, the formation of integrated circuit devices involves, among other things, the formation of various layers of material and patterning or removing portions of those layers of material to define a desired structure, such as a gate electrode, a sidewall spacer, etc. Device designers have been very successful in improving the electrical performance capabilities of transistor devices, primarily by reducing the size of or “scaling” various components of the transistor, such as the gate length of the transistors. In fact, device dimension on modern day transistors have been reduced to the point where direct patterning of such features is very difficult using existing 193 nm based photolithography tools and technology. Thus, device designers have employed various techniques to pattern very small features. One such technique is generally known as a sidewall image transfer technique.
FIGS. 1A-1E depict one illustrative example of a prior art sidewall image transfer technique. As shown in FIG. 1A, a mandrel 12 is formed above a structure 10, such as a semiconducting substrate. The mandrel 12 may be made of a variety of materials, e.g., amorphous silicon, polysilicon, etc. The size of the mandrel 12 may vary depending upon the particular application. The mandrel 12 may be formed be depositing and patterning a layer of mandrel material using known deposition, photolithography and etching tools and techniques. Next, as shown in FIG. 1B, a layer of spacer material 14 is conformably deposited above the mandrel 12 and the structure 10. The layer of spacer material 14 may be comprised of a variety of materials, such as, for example, silicon nitride, silicon dioxide, etc. As reflected in FIG. 1C, an anisotropic etching process is performed to define spacers 14A adjacent the mandrel 12. Then as shown in FIG. 1D, the mandrel 12 is removed by performing a selective etching process that leaves the spacers 14A to act as masks in a subsequent etching process that defines features 18 in the structure 10, as depicted in FIG. 1E.
Semiconductor memory devices are in widespread use in many modern integrated circuit devices and in many consumer products. In general, memory devices are the means by which electrical information is stored. There are many types of memory devices, SRAMs (Static Random Access Memory), DRAMs (Dynamic Random Access Memory), ROMs (Read Only Memory), etc., each of which has its own advantages and disadvantages relative to other types of memory devices. For example, SRAMs are typically employed in applications where higher speed and/or reduced power consumption is important, e.g., cache memory of a microprocessor, mobile phones and other mobile consumer products, etc. Millions of such memory devices are typically included in even very basic electronic consumer products. Irrespective of the type of memory device, there is a constant drive in the industry to increase the performance and durability of such memory devices. In typical operations, an electrical charge (HIGH) is stored in the memory device to represent a digital “1”, while the absence of such an electrical charge or a relatively low charge (LOW) stored in the device indicates a digital “0”. Special read/write circuitry is used to access the memory device to store digital information on such a memory device and to determine whether or not a charge is presently stored in the memory device. These program/erase cycles (“P/E cycles”) typically occur millions of times for a single memory device over its effective lifetime.
As shown in FIG. 2, a typical 6 T (six transistors) SRAM memory cell 100 includes two N-FinFET pass gate transistors 102A/B, two P-FinFET pull-up transistors 104A/B, and two N-FinFET pull-down transistors 106A/B. Each of the P-FinFET pull-up transistors 104A/B has its gate connected to the gate of a corresponding N-FinFET pull-down transistor 106A/B. The drains of the P-FinFET pull-up transistors 104A/B are connected to the drains of corresponding N-FinFET pull-down transistors 106A/B to form inverters having the conventional configuration. The sources of the P-FinFET pull-up transistors 104A/B are connected to a high reference potential, typically VCC, and the sources of the N-FinFET pull-down transistors 106A/B are connected to a lower reference potential, typically VSS or ground. The gates of the P-FinFET pull-up transistor 104A and the N-FinFET pull-down transistor 106A, which make up one inverter, are connected to the drains of the transistors 104B, 106B of the other inverter. Similarly, the gates of the P-FinFET pull-up transistor 104B and the N-FinFET pull-down transistor 106B, which make up the other inverter, are connected to the drains of the transistors 104A, 106A. Hence, the potential present on the drains of the transistors 104A, 106A (node N1) of the first inverter is applied to the gates of transistors 104B, 106B of the second inverter and the charge serves to keep the second inverter in an ON or OFF state. The logically opposite potential is present on the drains of the transistors 104B, 106B (node N2) of the second inverter and on the gates of the transistors 104A, 106A of the first inverter, keeping the first inverter in the complementary OFF or ON state relative to the second inverter. Thus, the latch of the illustrated SRAM cell 100 has two stable states: a first state with a predefined potential present on charge storage node N1 and a low potential on charge storage node N2; and a second state with a low potential on charge storage node N1 and the predefined potential on charge storage node N2. Binary data are recorded by toggling between the two states of the latch. Sufficient charge must be stored on the charge storage node, and thus on the coupled gates of the associated inverter, to unambiguously hold one of the inverters “ON” and unambiguously hold the other of the inverters “OFF”, thereby preserving the memory state.
Data is read out of the conventional SRAM cell 100 in a non-destructive manner by selectively coupling each charge storage node (N1, N2) to a corresponding one of a pair of complementary bit lines (BL, BL). The selective coupling is accomplished by the aforementioned pass gate transistors 102A/B, where each pass gate transistor is connected between one of the charge storage nodes (N1, N2) and one of the complementary bit lines (BL, BL). Word line signals are provided to the gates of the pass gate transistors 102A/B to switch the pass gate transistors ON during data read operations. Charge flows through the ON pass gate transistors to or from the charge storage nodes (N1, N2), discharging one of the bit lines and charging the other of the bit lines. The voltage changes on the bit lines are sensed by a differential amplifier (not shown).
It appears that, for the foreseeable future, SRAM devices will continue to enjoy widespread use in integrated circuit products. Semiconductor manufacturers will thus continue to try to develop more efficient and effective methods of making SRAM devices. The present disclosure is directed to various methods of forming SRAM devices using sidewall image transfer techniques.