1. Field of the Invention
The present invention relates to a semiconductor integrated circuit in which a static memory (SRAM) circuit is integrated on a semiconductor chip, and more particularly to a configuration of an SRAM integrated circuit device that allows operating margins to be increased.
2. Description of the Related Arts
In recent years, there has been a strong need to increase the speed of semiconductor devices such as SRAM circuits, as well as reducing their power consumption.
FIG. 32 shows a conventional SRAM memory cell circuit. Referring to the figure, symbols BLT and BLB denote bit lines; WL, a word line; Vdd, a high level power supply line; and Vss, a ground line. Further, reference numerals 201 and 202 denote transfer transistors used to access the memory cell; 203 and 204, drive transistors for driving storage nodes to store data in the memory cell; 205 and 206, load transistors for supplying charge to store data in the memory cell; and 207 and 208, the storage nodes.
The simplest and most effective method for reducing the power consumption of an SRAM circuit is to reduce its power supply voltage.
However, a reduction in the power supply voltage results in a reduction in the operating margins of the transistors, leading to unstable operation. To solve this problem, the following techniques have been disclosed. Japanese Laid-Open Patent Publication No. 11-39879 (patent document 1) discloses a technique of controlling the substrate potential of transistors making up an SRAM cell to increase the speed in a write operation and reduce the power consumption in a read operation. Japanese Laid-Open Patent Publication No. 2003-151277 (patent document 2) discloses a circuit technique of forming a high speed, low voltage memory cell by using two types of transistors having different threshold voltages Vth. Further, Japanese Laid-Open Patent Publication No. 2003-86713 discloses a technique of producing an SRAM memory cell that can operate at a low voltage and that is resistant to data destruction by forming transistors of the memory cell such that those transistors connected to one storage node have a larger gate width than those connected to the other storage node.