Formation of multi-level semiconductor devices entails the formation of multiple levels of metal interconnects such as vias and trench lines (local interconnect lines). For example, in a multi-level semiconductor device there are frequently formed several layers of vias interconnecting wider metal interconnect line portions among the multiple layers or levels of the device. Frequently, several vias will connect a wider metal portion, for example a bonding pad in an uppermost metallization layer to an underlying metallization level through several relatively narrower vias. For example the vias and metal interconnect lines are typically formed with line widths having a dimensions of about 0.25 microns and smaller. The electrical continuity of the various metal interconnects, particularly through the vias is critical to proper functionality of a device.
Copper and copper alloys are increasingly becoming the metal of choice in forming damascene structures as it has improved electrical resistivity and electrical migration resistance compared to aluminum, previously widely used as a metallization metal. The use of copper, however, has presented several technical manufacturing problems that must be overcome for successful implementation of the technology. For example, copper cannot be successfully etched to form metal lines since it does not form volatile components with known etching chemistry's. As a result, copper lines must be formed as metal inlaid structures, also referred to a damascenes or dual damascenes where an anisotropically etched opening is formed in a dielectric insulating layer followed by filling the opening with copper and planarizing the wafer process surface by a chemical mechanical polishing step.
One difficulty with prior art copper damascene processes is the process involving etching through an etch stop layer at a via bottom portion to form closed communication with an underlying copper region and the subsequent process of barrier layer deposition followed by copper seed layer deposition which takes place prior to filling the copper damascene, for example dual damascene, with copper according to an electro-chemical plating process. In prior art processes, a furnace baking method has been used to bake the dual damascene opening following etching through the etch stop layer to remove moisture from the IMD layer, particularly porous IMD layers and to prevent the formation of copper oxides over the underlying copper region. In addition, removing residual etching chemistries are removed to avoid corrosive attack of the copper prior to formation of a barrier layer to line the dual damascene opening.
The prior art process of a separate furnace baking method presents a significant slowdown in wafer throughput, typically requiring several hours, and frequently requiring costly ambient environmental controls in wafer queing stations to prevent the further absorption of moisture by IMD layers, formation of copper oxides, and corrosive attack of exposed copper portions.
There is therefore a need in the semiconductor art for an improved method to form copper damascene features to avoid or prevent moisture absorption, formation of copper oxides, and corrosive chemical attack of exposed copper portions while reducing a cycle time and processing cost.
It is therefore an object of the invention to provide an improved method to form copper damascene features to avoid or prevent moisture absorption, formation of copper oxides, and corrosive chemical attack of exposed copper portions while reducing a cycle time and processing cost in addition to overcoming other deficiencies and shortcomings of the prior art.