A programmable logic device, like an FPGA, has a programmable logic core and programmable I/O circuitry that provides incoming signals to the logic core and presents outgoing signals generated by the logic core. The logic core and I/O circuitry can be programmed to support different signal-processing applications.
FPGAs and other programmable logic devices can be configured for particular signal-processing applications using external devices called configuration interfaces. Some FPGAs are capable of being configured with a variety of different types of configuration interfaces, where each different type of configuration interface may have its own unique set of interface signaling requirements that dictate the characteristics of the I/O circuits on the FPGA that receive signals from and provide signals to the configuration interface. In a conventional FPGA, a different set of I/O circuits are designated for each different type of configuration interface that the FPGA supports. Each of these I/O circuits may be programmable to (i) support the corresponding configuration interface before configuration of the FPGA is completed and (ii) provide any of one or more different programmable operating modes after the FPGA has been configured.
In particular, I/O control circuitry in the I/O circuit of a conventional FPGA may have one or more (2×1) multiplexers (muxes), each of which receives (i) a hard-wired mode-control signal value (i.e., either a 1 or a 0) at one of the mux inputs, (ii) a configurable mode-control signal value from the FPGA's configuration memory at the other mux input, and (iii) a global output enable (GOE) signal from the FPGA's configuration controller as the mux selection-control signal, where the GOE signal indicates whether or not configuration of the FPGA has been completed. For example, when the GOE signal is low (indicating that FPGA configuration has not been completed), then the mux outputs the hard-wired mode-control signal value to the rest of the I/O circuitry for use in programming the I/O circuit to interface with the external configuration interface currently being used to configure the FPGA. When the GOE signal is high (indicating that FPGA configuration has been completed), then the mux outputs the configurable mode-control signal value (that was set during FPGA configuration) to the rest of the I/O circuitry for use in programming the I/O circuit for post-configuration operations.
Because different configuration interfaces have different interface signaling requirements, a different set of I/O circuits, and therefore a different set of I/O pads on the FPGA, may be required to support each different configuration interface, which can increase the number of I/O pads that need to be part of the FPGA design, thereby increasing the cost of the device.