1. Field of the Invention
The present invention relates to a semiconductor memory device and a manufacturing method for manufacturing the semiconductor memory device.
2. Description of Related Art
Semiconductor memory devices have memory cell areas and peripheral circuit areas. A large number of device elements are formed in the memory cell area, and the device elements formed therein are miniaturized, compared to device elements formed in the peripheral circuit area. When a semiconductor memory device is manufactured, memory cells adjacent to the border of the peripheral circuit area are subject to the proximity effect of light and the loading effect, because of the difference in density between the peripheral circuit area and the memory cell area. This may cause defective memory cells.
The present invention has been developed to solve the above-described problem. It is an object of the present invention to provide a semiconductor memory device and a method for manufacturing the semiconductor memory device, which are less susceptible to the proximity effect and the loading effect.
In accordance with one embodiment of the present invention, a semiconductor memory device has a semiconductor substrate that defines a main surface, a peripheral circuit area and a memory cell area on the main surface of the semiconductor substrate. Peripheral circuits are formed in the peripheral circuit area, and memory cells are formed in the memory cell area. The semiconductor memory device includes a first well formed in the peripheral circuit area, and a second well of a first conductivity type formed in the memory cell area and having a depth shallower than a depth of the first well. A third well of a second conductivity type is formed in the memory cell area. The third well is in contact with the second well and equal in depth to the second well. A device isolation structure is formed in the memory cell area. The second well and the third well are formed down to a level lower than the device isolation structure. The semiconductor memory device of the present invention has a border region between the peripheral circuit area and the memory cell area. Dummy elements that do not function as active device elements are formed in the border region in substantially the same forming density as that of the memory cells. The dummy elements are located on the same layer on which field effect transistors of the memory cells are formed. The first well is in contact with the border region, but not in contact with the memory cell area.
The cell arrangement described above prevents the memory cell from becoming defective under the proximity effect and the loading effect, attributable to a difference between the device element forming density in the peripheral circuit area and the device element forming density in the memory cell area. In one feature of the present embodiment, the dummy elements, which do not function as active device elements, are subjected to misalignment or deformation of resist patterns, which are attributable to the proximity effect and the loading effect, and which occur during the formation of the first well. As a result, other device elements, such as transistors, in the memory cell area are prevented from being affected by the proximity effect and the loading effect.
The device element forming density of the dummy elements may not be exactly the same as that of the memory cells to substantially prevent the memory cells from becoming defective under the proximity effect and the loading effect. In other words, the device element forming density for the dummy elements may or may not be exactly the same as that for the memory cells within a certain range to substantially prevent the memory cells from becoming defective under the proximity effect and the loading effect. In accordance with one embodiment, substantially the same device element forming density for the dummy elements and the memory cells may be attained when the dummy elements and the memory cells are arranged in an identical pattern (for example, in terms of the width of wells, well spacing, gate length, gate width, active area, inter-gate distance, and so forth).
The second well has the same depth as the depth of the third well in accordance with one embodiment of the present invention. Therefore, substantially no imbalance occurs in performance between transistors, attributable to the difference between the well depths. It is noted that, in this specification, the term xe2x80x9cthe same depthxe2x80x9d is not strictly limited to the same depth but also covers a well depth difference that causes substantially no imbalance in performance among transistors.
Also, in this specification, the device isolation structure refers to a LOCOS oxidation layer, a semi-recessed LOCOS oxidation layer or a shallow trench (as deep as about 0.4 to about 0.8 xcexcm).
In a semiconductor memory device in accordance with one embodiment of the present invention, the length of the border region may preferably be equivalent to the length that covers 1.5 to 3 memory cells that are arranged at a predetermined pitch in the memory cell area. If the length of the border region is shorter than 1.5 memory cells, the dimension of a well pattern for the border region becomes smaller than a well pattern for the memory cell area (in terms of the line width and spacing), when the second and third wells are formed in the border region. With this arrangement, a difference occurs between the pitch of the wells in the memory cell area and the pitch of the wells in the border region. As a result, accuracy in processing well patterns for the memory cell area is substantially reduced.
When the border region is disposed in a direction parallel to a direction in which wells alternate at a fine pitch in the memory cell area, for example, in an SRAM, the length of the border region needs not be longer than 1.5 cells. Any length of the border region is acceptable if it can absorb the proximity effect created during the formation of the first well.
Preferably, the length of the border region is set to cover 3 memory cells or shorter that are arranged at a predetermined pitch, because a border region longer than 3 cells causes the area of the semiconductor memory device to increase.
In a semiconductor memory device in accordance with one embodiment of the present invention, the border region may preferably have a well contact region. A potential is supplied to the well of the memory cell through the well contact region. Because the border region is designed to serve as the well contact region, the semiconductor memory device is miniaturized.
In a semiconductor memory device in accordance with one embodiment of the present invention, the first well may preferably be composed of a twin-well having an n-type well and a p-type well. The second well and the third well may also be formed in the border region. In a preferred embodiment, at least a part of the second well and at least a part of the third well may be formed in the border region. The n-type well of the first well may preferably be disposed between the second well or the third well, whichever is of a p-type, and the p-type well of the first well.
A substrate current may result in a latchup. The substrate current flowing through a p-type well (n-channel transistor formation area) is greater than a substrate current flowing through an n-type well (p-channel transistor formation area). The latchup margin is small in the memory cell area and the border region where wells are provided in a fine pitch. If the n-type well of the first well is arranged between the p-type well of the border region and the p-type well of the first well, the p-type well of the border region is isolated from the p-type well of the first well. This arrangement prevents the substrate current from flowing from the p-type well of the first well into the p-type well of the border region, thereby improving latchup withstandability.
In the above structure, the semiconductor substrate may preferably be of a p-type. As a result, the p-type wells are interconnected to each other in the memory cell area via the semiconductor substrate, and the well resistance is reduced. The reduced well resistance suppresses substrate potential from rising in the n-channel transistors that have a relatively large substrate current among the n-channel transistors and p-channel transistors in the memory cell area.
In the semiconductor memory device in accordance with one embodiment of the present invention, the first well, the second well and the third well may preferably be retrograded wells. The retrograded well refers to a well that is produced using a high-energy ion implantation, rather than thermal diffusion.
In the semiconductor memory device in accordance with one embodiment of the present invention, a CMOS cell type SRAM is formed in the memory cell area. The CMOS cell type SRAM refers to an SRAM in which each cell is formed from CMOS.
In accordance with one embodiment of the present invention, the depths of the second well and the third well are preferably within a range from about 0.5 xcexcm to about 1.2 xcexcm. If the depths of the second well and the third well are shallower than about 0.5 xcexcm, the depth of the device isolation structure becomes deeper than the depths of the wells. This creates the problem in forming the well contact region for fixing the well potential. The second well and the third well deeper than about 1.2 xcexcm creates another problem in that the overlapped area between the second and third wells expands beneath the device isolation structure.
In accordance with one embodiment of the present invention, a semiconductor memory device having a peripheral circuit area, a memory cell area, and a border region positioned in a border between the peripheral circuit area and the memory cell area, on a main surface of a semiconductor substrate may be manufactured by a method including at least the following steps: (a) the step of forming a device isolation structure on the main surface of the semiconductor substrate; (b) the step of forming a first well in contact with the border region but not in contact with the memory cell area, by ion-implanting an impurity in the peripheral circuit area only; (c) the step of forming a second well of a first conductivity type by ion-implanting an impurity in the memory cell area, wherein the second well is shallower in depth than the first well and is formed down to a level lower than the device isolation structure; (d) the step of forming a third well of a second conductivity type by ion-implanting an impurity in the memory cell area, wherein the third well is equal in depth to the second well and is adjacent to the second well beneath the device isolation structure; and (e) the step of forming a field effect transistor in the memory cell area. In accordance with one embodiment of the present invention, step (e) includes the step of forming dummy elements, that do not function as active device elements, in the border region at the same device element forming density as that of the memory cells.
In accordance with the embodiment of the present invention, a method for manufacturing a semiconductor memory device having a dummy element is provided.
In accordance with one embodiment of the present invention, step (b) includes forming a twin-well composed of an n-type well and a p-type well, with the n-type well positioned adjacent to the border region, step (c) includes forming the second well in the border region, and step (d) includes forming the third well in the border region. In one embodiment, the second well or the third well, whichever is of the p-type, is positioned adjacent to the peripheral circuit area.
The above embodiment provides a manufacturing method for manufacturing the structure in which the n-type well of the first well is located between the p-type well of the first well and the p-type well of the border region.
Either a positive resist or a negative resist will work as the resist pattern in step (b). Either a positive resist or a negative resist will work as the resist pattern in steps (c) and (d) as well. However, in a more preferred embodiment, a positive resist is used in steps (c) and (d). This is because the positive resist outperforms the negative resist in the control of the vertical configuration of the end portion of the resist pattern and the dimensional control of the resist pattern.
Other features and advantages of the invention will be apparent from the following detailed description, taken in conjunction with the accompanying drawings which illustrate, by way of example, various features of embodiments of the invention.