Increasing the performance of integrated circuits (ICs), both with regard to more complex functionality and higher speeds, is a primary goal of efforts in advancing the semiconductor arts. One method that has been extensively employed to achieve this goal is scaling, that is decreasing area or size of individual device components that are used to form such integrated circuits. For example, the gate length of a typical MOS transistor has been reduced over the past several years from several microns to fractions of a micron and gate lengths of 0.1 micron or less will soon be desired. Such scaling efforts have also effected the size of capacitors used in a variety of ICs such as DRAMS and SRAMS (dynamic and static random access memories, respectively).
While such scaling efforts have resulted in the desired increases in performance, generally such size reductions also impact at least some characteristics of the devices so “scaled.” For example, reducing the gate length of a transistor generally reduces the transistor's output and decreasing the size of a capacitor generally reduces the capacitance or amount of charge such a capacitor can store. Fortunately, changing other features of devices such as transistors and capacitors has made it possible to retain or at least control such changes in their aforementioned characteristics. Thus as transistor gate length has been reduced, the gate dielectric layer's thickness has also been reduced to at least partially compensate for the change in device output. Similarly, as the size of capacitor structures has been reduced, materials such as hemispherically grained polysilicon (HSG) have been employed to increase the effective surface area of such structures and compensate, at least in part, for such size reductions.
However, it appears likely that as scaling continues such exemplary compensation techniques may not be possible. Silicon dioxide (SiO2), with a dielectric constant of about 3.9, remains the most common material employed for gate dielectric layers. To maintain transistor output at an acceptable level, a transistor having a gate length of 0.1 micron will require an ultra-thin SiO2 layer with a thickness of about 2 nanometers (nm). Ultra-thin being defined herein as a thickness of about 5 nm or less.
The forming and use of such ultra-thin SiO2 layers is problematic for a variety of reasons since such layers consist of only a few layers of molecules. Thus only one additional or missing layer of molecules can have a dramatic effect on device performance; for example where a desired layer is four SiO2 molecules thick, a change of one molecule will change a characteristic such as the layer's capacitance by as much as 25%. In addition, such thin layers typically exhibit high current leakage, for example due to band to band or Fowler-Nordheim tunneling. Such layers are also more susceptible to dopant penetration or diffusion through the layer thus changing the characteristics of an adjacent layer or region; for example boron diffusion from the gate electrode into the channel region alters channel characteristics.
One method of reducing these problems is the use of a thicker layer of an alternative dielectric material such as a metal oxide having a higher dielectric constant than that of SiO2. For the purpose of illustration, a metal oxide gate dielectric having an appropriately high dielectric constant can be formed with a thickness several times that of a SiO2 layer while having the performance characteristics of the thinner SiO2 layer. Thus the thicker metal oxide layer is said to have the equivalent oxide thickness (EOT) of the thinner layer. Alternate metal oxide materials such as titanium oxide (TiO2), aluminum oxide (Al2O3), tantalum oxide (Ta2O5) and others have therefore received attention as replacements for SiO2. However, such alternate materials must exhibit, in addition to a high dielectric constant (greater than that of SiO2), a large band-gap with a favorable band alignment, low interface state density, good thermal stability and the ability to be formed in a manner consistent with known semiconductor process methods at reasonable cost and yield. Unfortunately, many candidate metal oxide materials having an appropriately high dielectric constant, cannot meet these additional requirements. Thus it would be desirable to provide alternate dielectric materials and methods of forming such materials that are appropriate as a replacement for ultra-thin SiO2 layers.