1. Field of the Invention
The present invention relates to a semiconductor device having electric capacitive elements for storing data, and a method of manufacturing thereof.
2. Description of the Related Art
Using a DRAM (Dynamic Random Access Memory) as an example of a semiconductor device having capacitors, conventional STC (Stacked Capacitor Cells) type DRAMs have accommodated reduction in electric capacitance of capacitors resulting from miniaturization by increasing the size of three-dimensional capacitors in a height direction in order to compensate for the reduced electric capacitance. This causes an increased aspect ratio in a cross-sectional direction of capacitors or causes complicated structures, leading to difficulties in simultaneously ensuring the capacitance of capacitors and the yield rate.
Specifically, the STC type DRAM involves such problems as a failure in ensuring the characteristic for embedding insulating films among capacitors and the characteristic for embedding conductive films, and peripheral circuit through holes positioned at levels higher than before for connecting upper and lower wires across the capacitors. These problems make it increasingly difficult to ensure the profile for embedding conductive films in through holes (see JP-A-2000-332213).
The capacitance of capacitors in a DRAM is designed to have approximately 25-35 [f Farad] in order to ensure resistance to data corruption such as soft errors. However, with the expansion of the DRAM market into electric appliance fields, there is a strong need to reduce the power consumption of some products, resulting in a pressing need for improving the refresh characteristic of DRAM memory cells.
While one secure solution for improving the refresh characteristics may involve increasing the capacitance of capacitors to increase signal amounts, the manufacturing process becomes complicated in order to increase the capacitance of the capacitor, causing costs to increase. On the other hand, a reduction in cost is also required, such as in the field of personal computers, so that there is a challenge to respond to these requirements when using the same manufacturing process. Further, while increasingly higher performance and functions are associated with requirements for an increase in the number of metal wiring layers, the challenge is how to limit increased costs.
A mixed device which has a Logic device and DRAM device involves an exclusive memory cell process added to a logic process, and includes the problems that higher costs cannot be avoid and a lower yield rate in comparison with the basic manufacturing process of only DRAM device or a Logic device.