Embodiments of the invention relate to an array substrate and a manufacturing method thereof.
Currently liquid crystal displays have become the major kinds of flat plate displays, and thin film transistor liquid crystal displays (TFT-LCDs) have been prevailing in the market of the liquid crystal displays.
An array substrate is an important component of a liquid crystal display. FIG. 3 is a schematic structural diagram of an array substrate. As shown in FIG. 3, the array substrate comprises a display area 1 and a dummy area 2 which is located at the periphery of the display area 1. The array substrate comprises a base substrate 20, gate lines 11 and data lines 12 formed on the base substrate 20. The gate lines 11 and the data lines 12 cross with each other and define a plurality of pixel units. A first thin film transistor (TFT) 13 and a pixel electrode 14 are formed in each pixel unit. During line-by-line scanning for displaying, the gate lines 11 are applied with an On-voltage line by line on the array substrate. When a gate line 11 is applied with an On-voltage in scanning, the voltage over the gate line 11 is increased from an Off-voltage to the On-voltage gradually. When the voltage over the gate line 11 reaches the On-voltage, the data line 12 applies a voltage to the pixel electrode 14 through the first TFT 13 in each pixel unit, so that the voltage of the pixel electrode 14 will become equal to that over the data line 12. Subsequently, the voltage over the gate line 11 is decreased from the On-voltage to the Off-voltage, and the corresponding first TFT 13 is converted into an Off-state. The pixel electrode 14 stay at the voltage applied from the data line 12 until the next gate line 11 is applied with an On-voltage.
As for any of the gate lines 11, the charging time period of the gate line 11 comprises a voltage rising time period, a voltage holding time period and a voltage descending time period. During the voltage rising time period, the voltage over the gate line 11 is increased form the Off-voltage to the On-voltage; during the voltage holding time period, the On-voltage is held over the gate line 11; and during the voltage descending time, the voltage over the gate line 11 is decreased from the On-voltage to the Off-voltage. Generally, the Off-voltage is 0, so it is necessary for each gate line to increase the voltage from 0 to the On-voltage, which leads to a long charging time period.