An example of structure of memory array of the existing electrically erasable and programmable ROM (EEPROM) is illustrated in FIG. 1. As illustrated in FIG. 1, a memory array is formed of a plurality of blocks, each of which is consisting of a unit block for erase and program operation. FIG. 2 illustrates a layout of the internal circuit of block. Each block is usually composed of one byte (8 bits) to a plurality of bytes. In the case of EEPROM, one bit is composed of a switch transistor and a memory transistor. FIG. 2 illustrates a block of the one byte structure.
A structure of the MONOS (Metal Oxide Nitride Oxide Semiconductor) type EEPROM and concept of erase and program operations thereof are illustrated in FIG. 3 and FIG. 4. In the erase operation illustrated in FIG. 3, a negative high level voltage Vpp is applied to a gate of a memory transistor and holes are injected to a nitride film from a p-well to reduce a threshold voltage (Vth) of a memory transistor. On the contrary, in the write operation, a negative high voltage Vpp is applied to the p-well and electrons are injected to the nitride film to raise Vth of the memory transistor in order to store a binary data in the memory transistor.
A profile of change of Vth of the memory transistor is illustrated in FIG. 5. It is already known that after the erase and reprogram operations have been repeated and changes by aging are detected, the Vth of memory transistor comes close to the initial Vth. Therefore, an electrically reprogrammable EEPROM is limited in the number of times of reprogram operations and in the application years. Such limitation will be explained in more detail. When erase Vth in FIG. 5 is deteriorated and it comes close to the initial Vth, a drain current Ids of the memory transistor is reduced. Usually, when the read operation is executed, the initial Vth is applied as a gate voltage of memory.
Meanwhile, in the read operation of EEPROM, the bit line is charged through Vcc as illustrated in FIG. 6 and FIG. 7 and thereafter a voltage is applied to the switch and gate of the memory transistor to turn ON the memory transistor. When a memory is in the erase “1” state, voltage drop of the bit line is detected by discharging the bit line. When the memory is in the program “0” state, voltage drop of the bit line is never generated.
Deterioration of erase Vth and reduction of memory transistor Ids mean that the voltage detection period of bit line is extended. Usually, when the specification of read time is determined, it is determined by estimating deterioration of the erase Vth of this memory transistor. With the specification of this read period, the read data is determined by receiving a read signal from external control or the like.
When the read time is determined as explained above, even if Vth of memory transistor is almost not deteriorated due to the number of times of reprogram operation and application years are rather small, the read time has the relationship of tRD≧y (ns) as illustrated in FIG. 7 and the read operation is executed within the read period when the Vth is deteriorated. Namely, the specification of read time with the read signal has been fixed. Moreover, the number of times of reprogram operation and application years of EEPROM have been restricted with deterioration of Vth and limitation on the read time.
When the number of times of reprogram operation and application years are small in the electrically reprogrammable EEPROM, here lies a problem that a read operation rate is rather low due to the specification of fixed read period assuming deterioration of Vth of memory transistor while the read operation can be executed at a high speed.