The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size (e.g., shrinking the semiconductor process node towards the sub-20 nm node), which allows more components to be integrated into a given area. As the demand for miniaturization, higher speed and greater bandwidth, as well as lower power consumption and latency has grown recently, there has grown a need for smaller and more creative packaging techniques of semiconductor dies.
As semiconductor technologies further advance, stacked semiconductor devices, e.g., 3D integrated circuits (3DIC), have emerged as an effective alternative to further reduce the physical size of a semiconductor device. In a stacked semiconductor device, active circuits such as logic, memory, processor circuits, and the like are fabricated on different semiconductor wafers. Two or more semiconductor wafers may be installed on top of one another to further reduce the form factor of the semiconductor device.
In order to electrically connect the active circuits of different wafers, interconnect structures know as through vias (TVs) may be used. However, it may be difficult or impractical to form through via (TV) interconnect structures in 3DIC devices because of tight design specifications.