1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method for fabricating a semiconductor device, in which a silicon nitride layer is formed on a lower surface of a semiconductor substrate to prevent the lower surface of the semiconductor substrate from being contaminated by copper during a copper line formation process.
2. Discussion of the Related Art
Device isolation of a semiconductor device may be achieved by local oxidation of silicon or by shallow-trench isolation. FIGS. 1A-1E illustrate a conventional method for fabricating a semiconductor device using shallow-trench isolation.
As shown in FIG. 1A, a semiconductor substrate 100 having an active area and a non-active area is prepared. A pad oxide layer 101 and a pad nitride layer 107 are sequentially deposited on the entire surface of the semiconductor substrate 100.
As shown in FIG. 1B, a photoresist is coated on the entire surface of the semiconductor substrate 100, including the pad oxide layer 101 and the pad nitride layer 107, and is then patterned by photolithography, thereby forming a photoresist pattern PR on the pad nitride layer 107. The photoresist is patterned to cover the active area of the semiconductor substrate 100. Subsequently, the exposed portion of the pad oxide layer 101 is etched and removed with the patterned photoresist PR used as a mask.
As shown in FIG. 1C, after removing the photoresist pattern PR, the exposed pad oxide layer 101 and the semiconductor substrate 100 are removed with the patterned pad nitride layer 107 used as a mask. Thus, a trench 102 is formed in the non-active area of the semiconductor substrate 100.
As shown in FIG. 1D, an insulating layer is deposited on the entire surface of the semiconductor substrate 100, including the trench 102. The deposited insulating layer is then planarized by chemical-mechanical polishing until the pad nitride layer 107 is exposed. Thus, the insulating layer is selectively formed inside the trench 102. In this case, the insulating layer of the trench 102 serves as a device isolation layer 103.
As shown in FIG. 1E, the device isolation layer 103 is exposed by removing the patterned pad oxide layer 101 and the pad nitride layer 107.
However, the semiconductor substrate may become contaminated if copper permeates an exposed lower surface of the semiconductor substrate during a subsequent copper line formation process.