Bipolar transistors are currently used as sensor elements in imaging arrays. Each transistor can be used both as an integrating photosensor and as a select device to read out the integrated charge. The phototransistor sensor produces an output (photo)current as a result of absorbing photons, with the output current being proportional to the intensity of light incident on the sensor. Photons absorbed in the area of a phototransistor collector-base or emitter-base junction produce electron-hole pairs that are collected by a nearby p-n junction. Minority carriers collected by either junction act as a base current and are multiplied by the transistor gain to produce the collector current. The emitter current is the sum of the base current and collector current, and is usually used as the output of the sensor.
FIG. 1 is a schematic diagram of a pixel 10 based on a vertical NPN bipolar transistor which may be used in an imaging array. It is noted that although FIG. 1 shows a pixel based on an NPN type phototransistor, a corresponding PNP type phototransistor may be used as a pixel by interchanging the n-type and p-type regions of the transistor and reversing the polarities of the associated voltages. Pixel 10 has a floating base 12 which is capacitively coupled through capacitor 14 to a common row line 16 (labelled "row strobe input") it shares with other pixels in a row of the array. Collector 18 of pixel is connected to all of the pixels in the array through a common substrate. Emitter 20 of pixel is connected to a common column line 22 (labelled "column output") which it shares with other pixels in a column.
An important feature of pixel 10 of FIG. 1 is that the integrating node, base 12, is "floating". The use of capacitive coupling between row select line 16 and base node 12 means that there is no direct electrical connection between the base and a potential source, i.e., a connection without an intervening energy barrier. Such a pixel design is desirable because it requires fewer processing steps than do pixels having a direct connection.
During the operation of phototransistor 10, row select line 16 is held at a fixed voltage which is chosen to reverse bias the base-emitter junction of phototransistor 10. As image photons impact the phototransistor, electrons and holes are generated. The photo-generated electrons are swept into n-type collector 18 and removed through the collector voltage line (V.sub.cc). The photo-generated holes accumulate in the p-type base region and produce an increase in the base potential. The photocurrent generated integrates on capacitor 14 which is formed as part of the structure of the phototransistor. This corresponds to an image storage operation. When it is desired to read out the stored image contained in the imaging element represented by phototransistor 10, row select line 16 is brought to a high value. The readout pulse, termed a row strobe pulse, is capacitively coupled to base 12 of pixel 10 by capacitor 14. The pulse causes a forward biasing of the base-emitter junction of the transistor. In this situation, the integrated photocurrent, multiplied by the current gain of phototransistor 10 flows from the emitter region to column sense line 22.
Each column line is connected to a charge sense amplifier which senses the charge dumped onto each column line during a sensing cycle. The charges for each column of the array are sensed in parallel by the sense amplifiers at the bottom of each column. The sensing operation typically uses both a sense amplifier and a second amplifier which performs a correlated double sampling to compute the difference in the sense amplifier output prior to and after strobing the charge out of the pixel. This acts to remove charge fluctuation on the column line (the kTC thermal charge noise component) during reset of the sense amplifier which might otherwise contribute to the readout signal. After sensing of the charge, the signal is input to a sample and hold stage which drives a video scanout stage.
Readout of an array of such pixels occurs row by row; while a row is strobed and its pixels' charge output is sensed by the column charge sense circuits, the previous row's already sampled sense amplifier outputs are serially scanned out of the imager array by sequentially sensing the currents produced by the video output stages of the column circuits. The output transistors at the bottom of the columns of the array are turned on sequentially by a horizontal shift register circuit that shifts a single bit along the bottom of the array. The bit acts to turn on the video output transistor of each column one by one.
As noted, the integrated charge (the amount stored in the base region since the previous readout cycle) for each pixel in a row is dumped onto a corresponding column line by strobing the row select line momentarily high. This capacitively couples the high-going pulse into the base, raising the base potential and forward-biasing the base-emitter junction. The forward biasing turns on the base-emitter junction, dumping integrated base charge onto the emitter (column output) line. The strobe signal is generated during the sense phase of the column charge sense amplifier and is routed to a particular row by a vertical scan circuit. FIG. 2 is a graph of voltage versus time showing the pixel dynamics of the pixel of FIG. 1 during a cycle of the row strobe pulse. The figure shows the collector, emitter and base nodes' voltage as a function of time during the row strobe cycle. As is evident from the figure, when the row strobe is pulsed high, the base voltage becomes greater than the emitter and the base-emitter junction becomes forward biased.
The sequence of events and control signals used to perform a readout cycle of a selected row of the array is as follows:
(1) reset the sense amplifier(s); PA1 (2) enable the sense amplifier(s) to start the sense phase of the amplifier(s); PA1 (3) enable the strobe (readout) pulse pathway to the selected row; PA1 (4) pulse the row strobe line to the selected row, dumping the integrated charge and resetting the pixels in the row; PA1 (5) each pixel in the selected row dumps its integrated charge to its corresponding column line and associated sense amplifier; PA1 (6) sense the dumped charge, generating a sensed charge signal; PA1 (7) transfer the sensed charge signal from the sense amplifier(s) to the sample and hold stage; PA1 (8) sequentially clock the charge signals out of the array column by column; and PA1 (9) repeat process for the next row.
Note that sequential clocking of the charge signals out of the array column by column occurs concurrently with the listed steps, except for the sample and hold step. Serial readout of a row's output starts just after application of the sample and hold pulse and is completed just before the next sample and hold pulse.
An image is captured by the imager during a time period referred to as a "frame". During the frame period, all of the pixels contained in the array are exposed to the image and integrate the charge generated by the phototransistors which are part of the pixels. Thus, every row of the array has an integration period approximately equal to the frame time. Each row of pixels is read out once per frame. The portion of the image contained in one row of the array is referred to as a "line" and the time period during which the charge from a row of pixels is readout is termed a "line-time".
FIG. 3 is a block diagram showing the layout of an imager 30 based on the pixel of FIG. 1. Imager 30 includes a pixel array 32 formed from a plurality of pixels which are arranged into rows and columns. Strobe scanner 34 is used to select the row of array 32 to which the strobe or row select pulse is applied. Strobe scanner 34 is typically implemented in the form of a vertical scan circuit such as a dynamic shift register, in which a control signal input to the scanner determines to which row the strobe pulse is applied.
A column charge sense amplifier 36 is connected to each of the columns of array 32 and serves to sense the amount of charge dumped onto each column line during readout of a row of the array. The column charges are sensed in parallel by the amplifiers at the bottom of each column. After sensing, the results are sampled and held for each column. While a row of pixels is being sensed, the previous row's charge signals are scanned out serially under the control of serial output scanner 38, which typically takes the form of a dynamic shift register. Timing generator 40 generates the timing (control) signals used to control the operation of strobe scanner 34, output scanner 38, and column amplifiers 36.
Although an imager formed from the pixel of FIG. 1 has many advantageous features, it does have disadvantages. Reflections from specular surfaces (e.g., water, metal, glass) of bright sources such as sunlight can cause image highlights that are more than two decades brighter than the average image luminance. In addition, luminant sources (like light bulbs) themselves are generally several decades brighter than the scene as a whole. In order to provide practical images, imaging arrays must be able to handle these highlights, without becoming over- exposed and generating artifacts.
When a strong image (intense light) is incident on an imaging element formed from a transistor of the type shown in FIG. 1, the base potential increases rapidly during the integration period due to the photo-generated charge, until the base-emitter junction becomes slightly forward biased. Further charge collected in the base region during the integration period is injected into the emitter. This is termed "overflow", and causes a bright vertical streak in the image as the overflowing pixel continuously dumps current onto the column line, including during the column sense amplifier sense phases for other rows being read out. This behavior is indicated by the dotted line in FIG. 2 labelled "ov". Overflow contributes to a degradation of the image quality in cases of images with bright highlights. This reduces the utility of such photosensors for obtaining images in situations of bright (intense) light or scenes with extreme contrast.
In CCD based imagers, the overflow problem is typically addressed using an overflow drain or by using a clocking mechanism which causes recombination of excess photocharge. An overflow drain is a lateral or vertical feature of the pixel which is set to a potential less than the capacity potential of the pixel. It forms a location to which excess charge is preferentially spilled instead of being transferred to another pixel (or in the case of active pixel imagers to a column sense line).
The clocking mechanism approach to overflow control uses a charge pump to insure that a sufficient supply of holes are available for the excess photogenerated electrons to recombine with prior to interfering with the image being captured by adjacent pixels. Charge-pumped overflow protection (termed anti-blooming) can be implemented in frame transfer CCD imagers that have buried n-channel structure. Anti-blooming is provided by holes trapped in surface interface sites that recombine with excess buried channel electrons. The holes are loaded into the interface states by applying a large negative pulse to the gate of the pixel. The negative pulse places the p-type surface channel into inversion, filing the interface states with holes provided by the p+ channel stoppers. This sets the surface potential equal to that of the p- substrate. The gate voltage is then raised to a positive potential, forming a buried channel that collects photocharge.
The channel is buried, so only in overflowing pixels, where channel charge approaches full-well, will the channel electrons recombine with the holes at the surface. The surface holes may be replenished each line-time to increase the overflow protection capability. However, charge-pumped anti-blooming requires a frame transfer device having gates overlying the pixel integration area, buried channels, and a complicated three-level clocking scheme. In addition, such an approach requires sufficient surface interface states to hold anti-blooming holes. In the absence of such interface states, the charge pump negative pulse inverts the surface, but the holes flow out of the surface channel through p+ channel stoppers when the gate voltage is raised to begin the integration time. The requirement of sufficient interface states conflicts with the desire to reduce such states in order to minimize the dark current generated.
In active pixel CMOS imagers, overflow may be handled by using a lateral overflow drain formed from a reset transistor. In photodiode active pixel imagers, the reset transistor resets the photodiode to a reverse-biased condition. If the pixel is overexposed, the photodiode discharges to a potential where the reset transistor is turned on, supplying the photocurrent. The excess photocurrent is dumped into the substrate, where the minority carriers are mainly collected by nearby reverse-biased junctions that form part of the pixel and surrounding pixels. However, these methods have the disadvantage of requiring a pixel structure which includes a lateral reset transistor, and hence the additional surface area and processing steps required to form such a device.
Another proposed method for handling overflowing charges in imagers that are based on a bipolar-transistor pixel, is to use a second emitter in the pixel for the purpose of removing excess image generated charge. The second emitter forms an overflow drain which is biased slightly lower than the first emitter of the phototransistor so that the base-second emitter junction is forward biased sooner than the base-emitter junction when the imaging element is exposed to a strong image. Just before readout of the pixel, the second emitter potential is raised above that of the first emitter, so that current flows into the first emitter during pixel readout. After readout, the second emitter potential is lowered below the first emitter potential to re-enable overflow protection.
This mode of operation prevents the base-emitter junction potential from becoming forward biased during image integration when the phototransistor is exposed to a strong image. Instead, the overflow current of the generated holes is drained to the second emitter, rather than into the first emitter where it would produce noise on the column sense line. However, this method has the disadvantage of requiring a modification to existing active pixel designs, producing a larger device, reducing the fill-factor and quantum efficiency, and necessitating a more complex process flow.
In summary, currently utilized CCD overflow protection mechanisms are either vertical or lateral overflow drains, or are based on charge-pumping. Vertical overflow drains are dominant at present in high resolution, high quality CCD imagers. They afford overflow rejection ratios typically around 10,000, while occupying no extra silicon area. Use of such overflow drains requires complex 2- and 3-dimensional numerical process simulation to design a process flow that will result in the vertical and horizontal doping profiles that produce the correct potential distributions. This fabrication process flow is much more complex than a standard CMOS flow. In existing CMOS process based active-pixel imagers, overflow protection is generally provided by the reset transistor in each pixel. This lateral device is shared, so it does not increase device area or complexity. However, as noted, it does require a pixel design having a reset transistor and the associated more complex process flow and reduced yield for a given size substrate.
Another disadvantage of most imagers, including those formed from the pixel of FIG. 1, is that during each exposure of the image array (termed a "frame"), all of the pixels integrate for a fixed, predetermined amount of time. For bright objects, if the integration time is long enough, this can lead to over-exposure of the pixels, contributing to saturation and eventual overflow of the pixels. Similarly, for dark objects, if the integration time is not long enough, this can lead to under-exposure of the pixels.
In addition, moving objects may give rise to images which are not sharp as a result of the pre-set, fixed integration time for each row of pixels. For example, assume an imager array having dimensions of 1000 by 1000 pixels (105 total pixels) which can be read out at a rate of 10 MHz. These values are typical for a present-day still image device. The assumed characteristics produce a frame time of 0.1 seconds. In such a case, subframe exposure is clearly desirable to avoid image blurring artifacts owing to subject motion or shaking of the camera. Thus, the fixed integration time for all of the pixels can give rise to both exposure and image clarity problems.
In CCD based imagers, the pre-set integration time issue may be addressed by resetting the pixels during the frame period so that the integration time of the pixels is shortened from its full-frame value. The reset pulse is applied to each row once per frame (readout cycle), with the reset pulse being applied to all rows at the same time. The reset pulse causes the pixels to dump the integrated charge, with the removed charge being passed through a reset switch. This provides both an improvement in image clarity for moving objects and reduces the integrated charge built up during the frame time when a bright image is captured.
However, this approach to implementing an electronic shutter has disadvantages. A global electronic shutter reset mechanism which acts on all pixels in the array simultaneously results in different integration times for different rows of pixels. This complicates the processing of the image and the production of a realistic image of the illuminating object. In interline transfer or frame transfer CCD imagers, this complication is addressed by having integrated photocharge from pixels in the array "hidden" from further changes by transfer to the adjacent CCD (interline transfer imagers) or to charge storage sites (frame transfer imagers) that are covered by metal. In either type of CCD imager, the charge transfer from imaging to storage elements occurs very rapidly and simultaneously for the entire array. This permits a shutter function to be realized by simultaneously resetting all of the pixels in the array.
However, this approach is not applicable to some active pixel based imagers. In such active pixel designs the pixels integrate continuously whenever they are illuminated; there are no sites where integrated pixel photocharge can be temporarily stored. Hence, a global electronic shutter reset would not be an appropriate shuttering mechanism for such pixel designs.
Instead, in such active pixel imagers, an electronic shuttering function is implemented by restricting the pixel integration period to a subframe. The array is read out line by line, with the pixels being reset a certain number of line-times before they are read out. The charge removed as a result of the reset (shutter) pulse is passed through a lateral reset transistor. The number of line-times the pixels integrate after they are reset and before they are readout determines the exposure. However, this method has the disadvantage of requiring a pixel structure which includes a lateral reset transistor, and hence the additional surface area and processing steps required to form such a device.
What is desired is an imaging array and method of operating the same which solves the overflow and shuttering problems in a more efficient manner than that presently available. It is desirable to utilize an unmodified pixel to solve these problems since such an approach does not result in an increase in the pixel area or require a more complex process flow. This permits the fabrication of high resolution imaging arrays using less complex processing methods. It is also desired to implement these features in a manner which doesn't contribute artifacts to the sense amplifier signal representing the readout of the pixels. These and other advantages of the present invention will be apparent to those skilled in the art upon a reading of the Detailed Description of the Invention together with the drawings.