1. Field
An embodiment of the present invention relates to the field of high frequency integrated circuits and, more particularly, to a latching mechanism that may be used in high frequency integrated circuits.
2. Discussion of Related Art
Advances in semiconductor manufacturing technologies have enabled circuit designers to continue to integrate more transistors on a single die. At the same time, computer architecture, and more specifically, processor architecture, continues to focus on shorter and shorter cycle times.
Domino logic is frequently used in an effort to reduce power, die area and output capacitance as compared to static full complementary metal oxide semiconductor (CMOS) logic. The reduction in parasitic capacitance provided by domino CMOS logic permits higher speed and lower power operation.
As clock speeds continue to increase (and thus, cycle times continue to decrease) and/or where certain parts of a chip operate at a much higher frequency, limitations of conventional logic circuits, including conventional domino logic circuits, may prevent such circuits from operating properly at the higher clock speeds. Further, many conventional domino logic circuits operate using a two-phase clock. For very high operating frequencies, it may not be feasible to generate and distribute a two-phase clock due to noise, clock jitter and/or other issues.
Where a pulsed clock is used instead of a conventional two-phase clock, the logic may be more susceptible to functional errors due to race conditions making such circuits more difficult for design engineers to work with. Further, pulsed signals can only be communicated relatively short distances as compared to their static counterparts.