1. Technical Field
The present invention relates to semiconductor chips and, more particularly, to chips in which a command causes different operations in different chips.
2. Background Art
Conductors are typically terminated through resistive structures, such as resistive materials and transistors. The terminations have been positioned in various places. Examples of the location of terminations include on motherboards or other circuit boards or cards. Other examples of locations of terminations include on a chip that transmits a signal and/or on a chip that receives a signal. Terminations on the chip are commonly referred to as on die terminations (ODTs).
Some Dynamic Random Access Memories (DRAM) chips have registers referred to as a mode register set (MRS) which includes bits to control functions of the DRAM chips. One or more bits in the MRS may control particular functions of the DRAM chips. Extended MRSs (such as EMRS0, EMRS1 etc.) may provide additional bits for use.
DRAM chips are typically included in memory modules, some of which are dual in-line memory modules (DIMMS). The term rank refers to a group of memory chips that are selected together, for example, through a shared chip select signal or through some other way. Some modules include only one rank per module and some include more than one rank per module. Some ranks include chips on more than one module.
In some two rank memory systems, for best electrical performance, the ODT is enabled on the DRAM chips that are not receiving the data for write operations.
The JEDEC Solid State Technology Association has provided standards for DDR2 (dual date rate 2 or double data rate 2) DRAM chips. In DDR2 DRAM chips, the ODTs are controlled by using discrete signals per rank. In some two rank-1 DIMM systems, two ODT pins are used on the controller and the DIMM. Two pins may also used per DRAM chip to support stacking solutions. As used in this disclosure, the word “pin” means traditional pins or other connections to die pads.
In GDDR3 (graphics DDR3) and also DDR3/DDR2 proposals, the command bus may be shared between two ranks. The DRAM can monitor or snoop the command bus for a write transaction. If it sees a write cycle and no CS# asserted then, it can turn its ODT on. The write command may target the other rank. (CS# are rank or device specific). The term “2N timing” refers to a situation in which it takes an extra clock cycle for sampling as compared to a 1N timing. The sampling may be of a signal, such as an address signal. Snooping may work well for 1N timings, but not for 2N timings (with an additional clock cycle before sampling) because snooping may cause additional clock cycles in turnaround cycles and in leadoff write cycles.