The present invention relates to a memory structure.
The development of memories has occurred simultaneously with the development of computer processors. This means that the development of processors has guided the development of memory. Therefore it has been traditional that information in a memory is arbitrarily divided into bit groups (called bytes from now on), with a fixed number of bits, most often being addressed independently of earlier selected information. This leads to the address decoder having to be able to reach an arbitrary position in the memory within a certain access time in order to read or to write information there. The data transfer speed is inversely proportional to the access time. The access time is naturally dependent on which sort of manufacturing technology is used for the memory. VLSI-technology (VLSI=Very Large Scale Integration) is used and efforts are made to minimize the size and complexity of the circuits. For a given technology the size of the memory is always limited by the propagation speed of the signals. At the same time there is also the relationship that for traditional architecture increased memory area implies increased access time because the complexity of the address decoder increases when the memory increases. The demand for data processing speed is constantly increasing. Since the complexity of the address decoder increases and the propagation speed is constant, then the total storage space, that is to say the addressable surface where information can be stored, always decreases with increased computer speed.
In many fields of use which have become of immediate importance in the last years, such as telecommunications, radar, bulk memories for computers etc., information is not handled in the form of bytes but as sequences of bytes which are called vectors. In modern digital telephone systems and in data communication systems packets of information, ATM, are used. In radar the information is in the form of pulses. After digitalization the pulse can be considered as being a large vector, defined by the start point and length.
In many applications large blocks of connected bytes are handled in the same way, for example a block of text in a word processor. Another example is swap memory in computers. These have in common that a large amount of information (vector) is handled as a whole. Addressing at the byte level is not used.
An object of the invention is to produce a memory structure which is adapted for storing vectors.
Another object of the invention is to produce a memory structure which gives fast and continuous access to storage places for the reading and/or writing of vectors.
A further object of the invention is to produce a structure where the writing of a vector can take place at the same time as, and independently of, the reading of a vector is taking place.
Yet a further object of the invention is to produce a memory structure where the writing of a vector can take place almost simultaneously with the reading of it.
Yet another object of the invention is to produce a memory structure where the time for outputting written data can be controlled right down to the clock period.
Yet another object of the invention is to produce a memory structure which can be used as a complement to the current type of memory structure for a computer.
A further object of the invention is to produce a memory structure which permits the treatment of a stored vector in parallel by a plurality of storage positions for vectors in order to either reposition the processed vector or to get out a processing result.
The above objects are achieved with a memory structure which has the characteristics described below.
According to the invention, after configuration, each of the storage positions in the memory has a length adapted for the length of the large vectors and is arranged in a parallel fashion, extending from an information input and deeper into the memory so that each vector is arranged to be stored undivided in consecutive order with the beginning of the vector by the input of the memory, whereby addressing is arranged to take place to the input of the memory. There are means acting as shift registers for the inputting of information in undivided order to the storage positions in the memory.
The memory is preferably divided transversely into memory blocks, so that all storage positions each have a part in each memory block. The storage positions in the memory can be lengthenable through joining together of one or more memory blocks. Each memory block can comprise:
as means acting like shift register;
an input buffer with serial inputting of data analoguosly with a shift register;
as storage positions:
a number of data memory fields in which information from the input buffer can be sequentially inputted.
In this connection a control logic is arranged in each memory block. The control logic controls the input of information in memory fields via the input buffer whereby the memory blocks are cascade coupled with each other through the input buffers in them being cascade coupled with each other, so that information is serially stepwise feedable through a number of the buffers in the different memory blocks after one another, and the control logic in each memory block is arranged to inform the control logic in the next memory block when the memory fields in its own memory block are filled with information or all information in them is read out, so that the control logic in the next memory block can take over the job of writing the information to this memory block. There can be means acting like shift registers for the outputting of information in undivided order from the storage positions in the memory. Moreover there can be means for data processing of data stored in a parallel manner in the different memory blocks.
The memory structure according to the invention permits the setting up of a large and expandable storage space for information, continuous data transfer and at the same time extremely high transfer speeds. Expansion of the storage space for a vector, and thereby the size of the memory, can be performed without affecting the data transfer speed as the interface with the memory seen from outside is unchanged.
With the memory structure according to the invention a continuous data transfer can be performed at approximately 0.5-1 Gbytes/sec compared with todays 30-100 Mbytes/sec. This implies a factor of ten times faster with the use of corresponding basic technology. The memory structures in themselves are not dependent on the technology used but can be used for arbitrary storage technologies (RAM, magnetic memory, optical memory etc.).