1. Field of the Invention
The present invention relates to a semiconductor memory device and a manufacturing method thereof, and particularly to a semiconductor memory device and a manufacturing method thereof in which a single memory cell consists of a single field effect transistor.
2. Description of the Background Art
Conventionally, a semiconductor memory device is known which includes an ROM (Read Only Memory). FIG. 24 is an equivalent circuit diagram of a conventional semiconductor memory device including an ROM. Referring to FIG. 24, a single memory cell of the ROM is constituted of a single enhancement type MOS (Metal Oxide Semiconductor) transistor. MOS transistors 201 and 203 have their gate electrodes connected to a gate electrode (wiring) 104a, MOS transistors 202 and 204 have their gate electrodes connected to a gate electrode (wiring) 104b, MOS transistors 205 and 207 have their gate electrodes connected to a gate electrode (wiring) 104c, and MOS transistors 206 and 208 have their gate electrodes connected to a gate electrode (wiring) 104d, respectively. Source regions of MOS transistors 201 to 208 are connected to an aluminum wiring 110a for the sources, while drain regions are connected to an aluminum wiring 110b for the drains.
When reading is performed with supply voltage V.sub.DD set at 3 V to 5 V, MOS transistor 201 will have its threshold voltage V.sub.TH set at 0.5 to 1.0 V and MOS transistor 202 will have its threshold voltage V.sub.TH set at 5.0 V or more. Thus, when supply voltage V.sub.DD =3 V to 5 V, MOS transistor 201 would be turned ON and MOS transistor 202 would be turned OFF. As a result, data "1" can be read from MOS transistor 201 and data "0" from MOS transistor 202, or data "0" can be read from MOS transistor 201 and data "1" from MOS transistor 202. In the semiconductor device of FIG. 24, threshold voltages V.sub.TH of MOS transistors 203 to 208 are all set between 0.5 V and 1.0 V.
FIG. 25 is a plan view of the semiconductor memory device shown in FIG. 24. Referring to FIG. 25, region 300 of FIG. 24 corresponds to region 300 of FIG. 25. Aluminum wirings 110a for the sources are connected to the source regions (not shown) via source contact holes 113. Aluminum wirings 110b for the drains are connected to the drain regions (not shown) via drain contact holes 112. At predetermined regions under aluminum wirings 110a for the sources, element isolating regions 122 are formed.
FIG. 26 is a cross sectional view of the semiconductor device shown in FIG. 25, taken along line 400--400 of FIG. 25. Referring to FIG. 26, N type high impurity concentration regions 107a and 107b are formed on a main surface of a silicon substrate 101, spaced apart by a predetermined distance with channel region therebetween. At the end portions of N type high impurity concentration regions 107a and 107b adjacent to gate electrode 104a, N type low impurity concentration regions 105a and 105b are formed, respectively. N type high impurity concentration region 107a and N type low impurity concentration region 105a constitute the source region with an LDD (Lightly Doped Drain) structure. N type high impurity concentration region 107b and N type low impurity concentration region 105b constitute the drain region having an LDD structure which is shared by MOS transistors 201 and 202.
Gate electrode 104a is formed on the channel region of MOS transistor 201 through a gate oxide film 102a. Gate electrode wiring 104b is formed on the channel region of MOS transistor 202 through gate oxide film 102b. Thickness of gate oxide films 102a and 102b is about 150 .ANG. to about 250 .ANG.. Gate electrodes 104a and 104b consist of doped polycrystalline silicon layer, and their thickness is about 1000 .ANG. to about 3000 .ANG.. On the side surfaces of gate electrodes 104a and 104b, sidewall insulating films 106 are formed.
In addition, an interlayer insulating film 109 having a thickness of about 10000 .ANG. is formed entirely on the surface. Drain contact hole 112 is formed at a region in interlayer insulating film 109 located on N type high impurity concentration region 107b. Aluminum wiring 110b having a thickness of about 7000 .ANG. to about 100000 .ANG. is formed so that it is electrically in contact with N type high impurity concentration region 107b within drain contact hole 112 while extending along the surface of interlayer insulating film 109. A passivation film 111 having a thickness of about 7000 .ANG. to about 8000 .ANG. is formed on aluminum wiring 110b.
In a conventional semiconductor memory device, threshold voltage V.sub.TH of MOS transistor 202 is set at 5.0 V or more by forming a high concentration channel doped region 108 at the channel region of MOS transistor 202. Since no high concentration channel doped region 108 is formed at the channel region of MOS transistor 201, threshold voltage V.sub.TH of MOS transistor 201 is about 0.5 V to about 1.0 V.
FIGS. 27 to 36 are cross sectional views illustrating a process of manufacturing the semiconductor memory device shown in FIG. 26. Referring to FIGS. 27 to 36, manufacturing process of the conventional semiconductor memory device will be described in the following.
As shown in FIG. 27, an oxide film 124 having a thickness of about 100 .ANG. to about 500 .ANG. is formed first on the main surface of silicon substrate 101 by thermal oxidation. Then, a channel doped layer 103 is formed by ion implantation of B or BF.sub.2 to silicon substrate 101 through oxide film 124.
Thereafter, oxide film 124 is removed, and a gate oxide film 102 as shown in FIG. 28 with a thickness of about 150 .ANG. to about 250 .ANG. is formed on silicon substrate 101. On gate oxide film 102, a doped polycrystalline silicon layer 104 with a thickness of about 1000 .ANG. to about 3000 .ANG. is formed by CVD method (Chemical Vapor Deposition) method. By patterning doped polycrystalline silicon layer 104 through photolithography and dry etching, gate electrodes 104a and 104b as shown in FIG. 29 are formed.
Thereafter, as shown in FIG. 30, gate electrodes 104a and 104b are used as a mask for an ion implantation of phosphorus (P) to silicon substrate 101, thereby forming N type low impurity concentration regions 105a and 105b. Then, an oxide film (not shown) having a thickness of about 2000 .ANG. to 3000 .ANG. is formed entirely over the surface by CVD method and is etched anisotropically to form sidewall insulating films 106 as shown in FIG. 31. Using sidewall insulating films 106 and gate electrodes 104a, 104b as a mask, ion implantation of arsenic (As) is performed to silicon substrate 101 thereby forming N type high impurity concentration regions 107a and 107b.
As shown in FIG. 32, a resist pattern 125 having an opening above gate electrode 104b is formed by photolithography. Resist pattern 125 is used as a mask to preform an ion implantation of a P type impurity (for example, boron) to silicon substrate 101 through gate electrode 104b and gate oxide film 102b. This ion implantation is performed with an implanting energy of 150 KeV to 250 KeV and impurity concentration of 1.times.10.sup.13 to 1.times.10.sup.14 cm.sup.-2. Thus, high concentration channel doped region 108 is formed at the channel region of enhancement type MOS transistor 202. As a result, only enhancement type MOS transistor 202 can have its threshold voltage V.sub.TH set at 5.0 V or more. Resist pattern 125 is then removed. By heat treatment, N type low impurity concentration regions 105a and 105b as well as N type high impurity concentration regions 107a and 107b are formed to have such shapes as shown in FIG. 33.
Then, as shown in FIG. 34, interlayer insulating film 109 with a thickness of about 10000 .ANG. is formed by CVD method entirely over the surface. A resist pattern 126 is formed on interlayer insulating film 109 by photolithography. Using resist pattern 126 as a mask, interlayer insulating film 109 is subjected to isotropical etching followed by anisotropical etching. By effecting heat treatment after resist pattern 126 is removed, drain contact hole 112 having such a shape as shown in FIG. 35 is formed.
Then, as shown in FIG. 36, aluminum wiring 110b is formed such that it is in contact with N type high impurity concentration region 107b within drain contact hole 112 and extends along the surface of interlayer insulating film 109. Aluminum wiring 110b is formed to have a thickness of about 7000 .ANG. to about 10000 .ANG. by sputtering method.
Finally, as shown in FIG. 26, passivation film 111 having a thickness of about 7000 .ANG. to about 8000 .ANG. is formed entirely over the surface by CVD method. Thus, the conventional semiconductor memory device including an ROM is completed.
In the conventional semiconductor memory device including an ROM, writing into the ROM (formation of high concentration channel doped region 108) is performed in a process shown in FIG. 32. Accordingly, the steps of effecting heat treatment for activation of an impurity region (see FIG. 33), forming interlayer insulating film 109 (see FIG. 34), forming drain contact hole 112, (see FIG. 35), forming aluminum wiring 110b (see FIG. 36), and forming passivation film 111 (see FIG. 26), are required after the step of writing into the ROM. Therefore, in the conventional semiconductor memory device, many steps are required after writing into the ROM until the semiconductor device is completed. Accordingly, it takes a long period after it was ordered by the user to perform the writing into the ROM and to complete the product.