Modern electronic appliances are frequently manufactured using one or more packaged semiconductor devices, which are sometimes called chips, each enclosed in a familiar black plastic package or in some other type of protective enclosure. Each chip performs a specific function associated with the operation of electronic appliance, and is mounted on one or more printed wired boards (PWBs) that provide for mechanical support and for electrical connections between the various chips. The PWBs and one or more input and output devices such as keyboards or LCD screens are then secured in some type of housing. Examples of modern electronic appliances include mobile telephones, personal digital assistants, and personal gaming devices. Larger electronic appliances include personal computers and television sets.
A chip is, generally speaking, a small piece of semiconductor material onto which a large number of tiny electric components have been fabricated and connected with one another to form integrated circuits. An example is shown in FIG. 1. FIG. 1 is a simplified perspective view illustrating a typical semiconductor chip 10. As can be seen in FIG. 1, semiconductor chip 10 is thin and usually in the shape of a square or rectangle. On the top surface 11 of semiconductor chip 10 is an active area 12. Active area 12 is simply the portion of top surface 11 at which the many tiny electrical components (not shown) are located. In this particular example, active area 12 also includes a series of bond pads 13, which are basically larger, externally-accessible conductive pads to which exterior electrical connections may be made, for example by attaching a bond wire (see FIG. 3). A seal ring 14 is formed on surface 11 of semiconductor chip 10 about the periphery of active area 12, segregating it from the rest of the chip and providing protection during certain fabrication operations. The backside 15 of chip 10 is referenced but not visible in FIG. 1. Ordinarily there are no circuits or pads formed on the backside 15, although there may be in some applications.
For efficiency, the electronic components for a number of chips are often fabricated simultaneously. For this purpose a thin wafer may be sliced from an ingot of, for example, silicon, and treated by ion implantation to impart semiconductor properties. An example is shown in FIG. 2. FIG. 2 is a plan view illustrating a typical semiconductor wafer 20. For the purpose of illustration, chip 10 is pointed out, although at this stage it has not yet been separated from the other, adjacent devices, and is typically referred to as a die. As can be seen in FIG. 2, a plurality of dice 22 is often formed in an array on the surface 21 of wafer 20. The dice 22 are collectively fabricated in a series of process steps that, in general, selectively deposit and selectively remove layers of insulating, conductive, and semiconductor material. Much of this process is automated, and great precision is required. An orientation notch 23 is for this reason formed in the periphery of wafer 20 so that it's proper positioning may be confirmed. Other methods of orientation control are used as well. Inspection and various types of testing take place at certain points in the fabrication process to identify those dice containing irremediable defects so that they are not used. Each of the dice 22 are usually though not necessarily identical with respect to each other, and will later in the fabrication process be separated into individual chips, such as the chip 10 shown in FIG. 1. The process for separating the chips is sometimes referred to as dicing.
As mentioned above, the various chips mounted on a given PWB (not shown) are often interconnected, and may in that manner form systems intended to perform an overall function, or set of functions, with each chip performing its own function-associated tasks. As small, energy-efficient electronic appliances become more popular, however, there arises a demand for new ways to configure the systems on which they rely. The chips forming an entire system, for example, may be contained within a single package. An exemplary SIP (system in package) device is shown in FIG. 3.
FIG. 3 is a simplified perspective view illustrating an exemplary 3D (three-dimensional)-SIC (stacked integrated circuit) semiconductor device 30. As should be apparent, this device consists of three chips that have been mounted one on top of the other. Semiconductor chip 10 shown in FIG. 1 is in this example at the top of the three-chip stack. Semiconductor chip 31 is directly beneath it, and semiconductor chip 32 is beneath a semiconductor chip 31. An intermediate layer 33 is shown between chip 31 and chip 32, and intermediate layer 34 is shown between chip 31 and chip 10. These intermediate layers are typically some type of insulating material that may also serve to bond the chips together. When assembled, the entire device 30 may be encased in this or a similar material, though this is not shown in FIG. 3. Semiconductor chip 10 is the smallest of the three chips in device 30, and semiconductor chip 31 the largest, permitting the numerous electrical connections required between the chips to be made using bond wires 35. As should be apparent, this is a very simplified illustration; an actual device may have dozens of such bond wires. Alternative means of providing electrical connections may also be used, for example creating vertical conductive structures that connect components on one chip with components on another, usually adjacent chip.
Unfortunately, when using vertical conductive structures to make connections between the components of one semiconductor device and those of another, problems in bonding may occur. The processes used to prepare one chip for bonding with another, such as grinding and polishing, often leave behind chemical residue and deleterious material that interferes with the bonding process. In addition, if too much time is allowed to elapse between preparation and bonding, oxidation or corrosion may degrade the quality of the exposed conductors. Eliminating this delay (sometimes referred to as Queue-time, or simply Q-time), however, may impose addition costs or other undesirable consequences. Needed, then, is a manner of manufacturing semiconductor devices such as 3D-SICs, and in particular preparing the multiple chips involved for bonding, which provides for greater bonding reliability and permits longer Q-times. The present invention provides just such a solution.