This invention relates to a pulse signal control circuit and more particularly a pulse signal control circuit for obtaining an amplified pulse data signal containing a high frequency pulse corresponding to a data signal, for use as a drive circuit of an AC plasma display unit, for example.
FIG. 1 shows a typical example of the prior art pulse signal control circuit 10, in which a data signal shown in FIG. 2A is supplied to one input a of a gate circuit 11 and a high frequency pulse signal as shown in FIG. 2B is applied to the other input b so as to produce an pulse data signal as shown in FIG. 2C on the output terminal c of the gate circuit 11. The pulse signal control circuit 10 further comprises an amplifier circuit 12 for amplifying the pulse data signal. The amplifier circuit 12 comprises a switching transistor 13, a buffer transistor 14, a resistor 15 connected across the base collector of transistor 13, a buffer diode 16 connected across the base and emitter electrodes of the transistor 14 with the opposite polarity, a speed-up capacitor 17 and a resistor 18 which is connected in parallel with capacitor 17, the capacitor 17 and the resistor 18 being connected between the output terminal c of the gate circuit 11 and the base electrode of the switching transistor 13.
The switching transistor 13 comprises an NPN type transistor with its emitter electrode grounded and its collector electrode connected to a source +V via resistor 15 which acts as a collector resistor for transistor 13. The buffer transistor 14 comprises an NPN type transistor with its collector electrode connected directly to the source +V whereas its base electrode is connected to the juncture of resistor 15 with collector electrode of the switching transistor 13.
When the pulse data signal shown in FIG. 2C appears on the output terminal c of the gate circuit 11, this pulse data signal is voltage-amplified by the switching transistor 13 and then current-amplified by the buffer transistor 14 thus producing an amplified data signal as shown by FIG. 2D as an output P. Such a pulse signal control circuit 10 as discussed above was described in a technical bulletin for "Plasma Display Panel UTOVUE PH 2008-03" published Jan. 30, 1975 by the assignee of the present application.
However, the pulse control circuit 10 described above has the following defects. Considering the output signal P of the amplifier circuit 12 although the switching-ON characteristic of transistor 13 is fast, that is its fall time characteristic is steep, its risetime characteristic is poor because the output builds up to the source voltage +V in accordance with a time constant determined by the collector capacitance and the collector resistance of the switching transistor 13 (see portions d shown in FIG. 2D).
As the collector capacitor is in the range of 10 to 50pF and the collector resistance is 100 to 500 K.OMEGA. under conventional operating conditions, the build up or rise time of the output signal P will be more than 1 .mu.s, thus seriously affecting the high speed switching operation.
To increase the switching-OFF speed of the switching transistor 13, it is necessary to make the value of the collector resistor 15 to be quite small. However when this resistance value is decreased, a large current would flow when the switching transistor 13 is turned ON, thus not only increasing power loss but also possibly damaging the transistor.
Since the pulse signal control circuit 10 is provided for each discharge cell when it is applied to an AC plasma display unit, increase in the power loss greatly increases the overall power consumption of the system making it difficult to design a practical system.