1. Field of the Invention
The present invention generally relates to a semiconductor memory device, and more particularly, to a Static Random Access Memory having a write recovery circuit structure.
This application relies for priority on Japanese patent application, Serial Number 264522/1998, filed Sep. 18, 1998, which is incorporated herein by reference in its entirety.
2. Description of the Related Art
A static random access memory (hereinafter SRAM) is used as, for example, a cache memory for a computer or the like. In such SRAM, a write recovery period is needed for stabilizing a data read operation. The write recovery period is generally known as a time period at the end of a write cycle in preparation for a succeeding read cycle. On the other hand, if the write recovery period becomes long, an operation speed of the SRAM decreases. Therefore, the write recovery period must be reduced.
There is a conventional technique for reducing the write recovery period. That is, a transistor which connects a bit line to a complimentary bit line at the end of the write cycle is provided. This transistor is known as an equalize transistor. Furthermore, transistors which supply a predetermined voltage level, e.g., a power supply voltage, to the bit line and the complimentary bit line at the end of the write cycle are provided. These transistors are known as pre-charge transistors.
However, since there is a demand for higher computer operation speeds, the operation speed of the SRAM must be even further decreased. Therefore, an improved semiconductor memory device, having a short write recovery period, has been needed in this technical field.