Circuits and methods for measuring a clock signal, for example, for measuring a period of a clock signal, are widely used in many applications. For example, circuits and methods for generating a compensated percent-of-clock period delay signal may be used to produce a delayed data strobe signal that is used to capture read data that is provided along with and edge aligned to the data strobe signal from a Double Data Rate (DDR) Synchronous Dynamic Random Access Memory (SDRAM). More specifically, a DDR SDRAM can transfer data on both rising and falling clock edges at relatively high rates. Such rates may result in a very narrow data valid window. Moreover, the read data strobe signals generally are edge aligned with the data signals rather than being edge centered. Thus, to be used as a clock for the data capture registers, the data strobe signals should be phase shifted by about 90°. However, the absolute value of the delay may change depending on the clock speed and may also shift depending on the process, voltage and/or temperature conditions under which the device is operating. Thus, it may be desirable for the absolute value of the delay to be adjustable, so that it represents the same percentage of the clock period when the clock frequency changes and under varying process/voltage/temperature conditions. Accordingly, circuits for measuring a period of a clock signal that can generate a compensated percentage-of-clock period delay signal may be highly desirable.
U.S. Pat. No. 6,664,838 to Talledo, entitled Apparatus and Method far Generating a Compensated Percent-of-Clock Period Delay Signal, assigned to the assignee of the present invention, the disclosure of which is hereby incorporated entirely herein by reference as if set forth fully herein, describes an apparatus and method for generating a compensated percent-of-clock period delay signal. A first circuit determines how many delay elements a clock signal passes through during one period of the clock signal. A second circuit passes a signal to be delayed through the same number of delay elements according to information received from the first circuit. The ratio of the values of delay elements in the first and second circuits determines the percent-of-clock period that the passed signal is delayed. Since the clock signal is relatively insensitive to reference voltage and temperature variations as compared to the delay elements, the percent-of-clock period is maintained as more or less delay elements are passed through during a period of the clock signal. See the Abstract of U.S. Pat. No. 6,664,838.
U.S. Pat. No. 6,856,558 to Proebsting et al., entitled Integrated Circuit Devices Having High Precision Digital Delay Lines Therein, assigned to the assignee of the present invention, the disclosure of which is hereby incorporated entirely herein by reference as if set forth fully herein, describes integrated circuit delay devices that include a digital delay line that is configured to provide a percent-of-clock period delay to a timing signal accepted at an enabled one of a plurality of injection ports thereof. The digital delay line may be responsive to an injection control signal having a value that sets a length of the delay by specifying a location of the enabled one of the plurality of injection ports, with the end of the delay line being a fixed output port. A delay line control circuit is also provided that is responsive to a clock signal having a period from which the percent-of-clock period delay is preferably measured. The delay line control circuit is configured to generate the injection control signal by counting multiple cycles of a high frequency ring oscillator signal having a period less than, and typically substantially less than, the clock period, over a time interval having a duration greater than, and typically substantially greater than, the clock period. The ring oscillator signal may be generated by a ring oscillator having a relatively small number of stages and the time interval may be sufficiently long so that a large number of cycles of the ring oscillator signal may be counted over many periods of the clock signal. See the Abstract of U.S. Pat. No. 6,856,558.