High-level synthesis is the process of transforming an un-timed description of circuit behavior (in programming languages like C or others) of a circuit design (e.g., Very Large Scale Integration (VLSI) circuit) to a cycle-accurate Register Transfer Level (RTL) description of the design (in programming languages like SystemC, VHDL, Verilog, etc.). FIG. 1 is a flow diagram of a conventional high-level synthesis method under the prior art, where code transformation is performed to optimize input code, scheduling assigns operations to control states and binding assigns operations to functional units, variables to storage elements, and data transfers to interconnects.
Scheduling is a critical and complex component of high-level synthesis because many important aspects relating to the final implementation of a circuit design, including performance, area, power, reliability, yield, etc., are largely influenced by the quality of scheduling.
Designers or tools, in generating the scheduling for a circuit design, typically impose constraints to state the necessary requirement of the design. Some of these constraints are necessary in order to guarantee the resulting circuit is functionally correct, like data dependency constraint, or input/output protocol requirement. Notably, many other constraints are not actually strict in that these constraints are preferably followed but not necessarily, as they are not essential to a correct implementation. In fact, many practical designs are under conflicting constraints which cannot be satisfied simultaneously. For example, a target frequency and a latency constraint may be specified at the same time, but the target frequency might be too high to meet given the target platform. The conventional method used in scheduling has clearly defined constraints, which are hard constraints. These constraints are hard constraints because even a slight violation of any constraint is considered unacceptable by a typical solver for scheduling. If two hard constraints contradict each other, the conventional problem solver either stops solving and reports a failure, or discards one of the constraints completely. In the later case, the order in which constraints are processed can be a significant factor in deciding the final solution.