Differential amplifiers are used to amplify the difference voltage between two input signals. A common mode input change occurs when the two input signals change together, and a normal mode input change occurs when the difference voltage between the two input signals changes. Ideally, the output voltage of a differential amplifier responds only to normal mode input changes and is independent of common mode input changes. The response of a differential amplifier can be measured by determining the ratio of the response for a normal mode signal to the response for a common mode signal. This quantity is the common-mode rejection ratio (CMRR), with good differential amplifiers having high CMRRs.
The normal mode voltage gain of a differential amplifier is the ratio of the amplified output voltage to the differential input voltage. Ideally, the gain of a differential amplifier does not depend on the magnitude of the differential input voltage. However, gain of a differential amplifier typically has a maximum value when the differential input voltage is small, and then decreased values as the magnitude of the differential input voltage increases. The change in gain causes distortion in the amplified output voltage. The degree to which the gain changes based on the differential input voltage can be specified as the linearity of the differential amplifier. Amplifier linearity, for example, can be defined as the largest differential input voltage within an acceptable gain limit of -1 dB, with good differential amplifiers having high linearity and, hence, low distortion and high dynamic range.
A conventional differential amplifier circuit 10 is shown in FIG. 1. Circuit 10 includes a first transistor 12 and a second transistor 14 arranged as a pair. Transistors 12 and 14 each have a base, a collector, and an emitter. The emitters of transistors 12 and 14 are connected together at a common emitter node 16. The collectors of transistors 12 and 14 are each connected to a first supply voltage +V.sub.CC through first and second load elements 18 and 20, respectively. Load elements 18 and 20 may include, for example, resistors R.sub.L or impedances Z.sub.L. A differential input voltage V.sub.IN is connected across the bases of transistors 12 and 14, with the positive V.sub.IN node connected to the base of transistor 12 and the negative V.sub.IN node connected to the base of transistor 14. Common emitter node 16 is connected to a second supply voltage -V.sub.EE through an adjustable current source 22. The amplified output voltage V.sub.OUT of circuit 10 is taken across the collectors of transistors 12 and 14, with the positive V.sub.OUT node at the collector of transistor 14 and the negative V.sub.OUT node at the collector of transistor 12. Transistors 12 and 14 are, for example, bipolar npn transistors formed within a common integrated circuit.
The voltages around the loop including differential input voltage V.sub.IN and the base-emitter junctions of transistors 12 and 14 yields: EQU V.sub.IN -V.sub.BE1 +V.sub.BE2 =0 (1)
Provided that V.sub.BE1 and V.sub.BE2 are much greater than the thermal voltage V.sub.T (25.3 mV at room temperature of 68.degree. F. or 20.degree. C.), the Ebers-Moll transistor model yields: EQU V.sub.BE1 =V.sub.T In(I.sub.1 /I.sub.S1) (2) EQU V.sub.BE2 =V.sub.T In(I.sub.2 /I.sub.S2) (3)
wherein the thermal voltage V.sub.T =kT/q, k is Boltzmann's constant (1.38.times.10.sup.-23 joules/.degree. K), T is the absolute temperature in degrees Kelvin, q is the electron charge (1.60.times.10.sup.-19 coulombs), and I.sub.S1 and I.sub.S2 are the saturation currents of transistors 12 and 14, respectively. Combining equations (1) through (3) and solving for I.sub.1 /I.sub.2 gives the ratio of the collector currents: EQU I.sub.1 /I.sub.2 =exp(V.sub.IN /V.sub.T) (4)
wherein saturation currents I.sub.S1 and I.sub.S2 of transistors 12 and 14 are assumed to be equal (i.e., transistors 12 and 14 are matched). Now, assuming that the current gain h.sub.FE of transistors 12 and 14 is high so the base currents can be ignored, summing the current into common emitter node 16 yields: EQU I.sub.E =I.sub.1 +I.sub.2 (5)
wherein I.sub.E is the tail current through current source 22. Combining equations (4) and (5), the collector currents can be written as: EQU I.sub.1 =I.sub.E /(1+exp(-V.sub.IN /V.sub.T)) (6) EQU I.sub.2 =I.sub.E /(1+exp(V.sub.IN /V.sub.T)) (7)
Referring to FIG. 2, collector currents I.sub.1 and I.sub.2 are plotted as a function of differential input voltage V.sub.IN. The graph shows that at V.sub.IN =0, tail current I.sub.E is split equally between transistors 12 and 14. At high positive V.sub.IN, tail current I.sub.E passes substantially through transistor 12 (i.e., I.sub.1 =I.sub.E and I.sub.2 .apprxeq.0). At high negative V.sub.IN, tail current I.sub.E passes substantially through transistor 14 (i.e., I.sub.2 .apprxeq.I.sub.E and I.sub.1 .apprxeq.0).
The voltage gain A.sub.V of differential amplifier circuit 10 is defined as: EQU A.sub.V =V.sub.OUT /V.sub.IN (8)
wherein EQU V.sub.OUT =R.sub.L (I.sub.1 -I.sub.2)=R.sub.L .DELTA.I (9)
The small signal gain of differential amplifier circuit 10 is: EQU A.sub.V =g.sub.m R.sub.L (10)
wherein the transconductance, g.sub.m, is: EQU g.sub.m =(.differential.I.sub.c /.differential.V.sub.be)=1/2I.sub.E /V.sub.T (11)
Thus, g.sub.m depends on the adjustment of adjustable current source 22.
Referring to FIG. 3, the small signal gain A.sub.V =g.sub.m R.sub.L is the maximum voltage gain which occurs at small magnitudes of differential input voltage V.sub.IN (e.g., at V.sub.IN =0, A.sub.V =g.sub.m R.sub.L). However, as shown, voltage gain A.sub.V decreases as the magnitude of V.sub.IN increases. The amplifier linearity can be defined as the largest magnitude of V.sub.IN wherein voltage gain A.sub.V is within acceptable gain limits. For example, if the acceptable gain limit is -1 dB, amplifier linearity is within the range of V.sub.IN to V.sub.IN+. However, the linearity of the circuit of FIG. 1 is relatively low, and it would be desirable to provide a differential amplifier circuit having expanded linearity.