1. Technical Field
The embodiments described herein relate semiconductor memory apparatuses, and more particularly, to a phase change memory apparatus and a test circuit therefor.
2. Related Art
There are various types of nonvolatile memories, including flash memories, phase change memories, and the like. Phase change memories, in particular, are designed to conduct write operations by varying the amount of write currents.
FIG. 1 is a schematic diagram of a general phase change memory apparatus.
As shown in FIG. 1, the phase change memory apparatus 10 is generally formed to include a plurality of unit cell arrays 110, an X-decoder 120, a Y-decoder 130, a block 140 including write drivers W/D and sense amplifiers S/A, a block 150 of global bit-line switches GYSW, blocks 160 of local bit-line switches LYSW, and blocks 170 of local word-line switches LXSW.
The operation of the phase change memory apparatus 10 will be explained in more detail in FIG. 2.
FIG. 2 is a block diagram illustrating a programming mechanism in a conventional phase change memory apparatus.
A current for a write operation is supplied to a sense-amp input/output line SIO from a write driver (W/D) 142. Global bit-line switches 150-1 and 150-2 are disposed between the sense-amp input-output line SIO and global bit lines GBL-1 and GBL-2. Each global bit line GBL is selected according to on/off states of the global bit line switches 150-1 and 150-2. These may comprise transmission gates each of which responds to a switch control signal gysw and an inverted switch control signal gyswB, the complementary signal of gysw, respectively. Reference numeral 144 denotes the sense amplifier S/A.
Data transferred to the sense-amp input/output line SIO from the write driver 142 is delivered to the local bit-line switch 160 through the global bit-line switches 150-1 and 150-2 and the global bit lines GBL-1 and GBL-2. Following the operation, the data is programmed into the memory cell selected by the word and bit lines.
It should be noted that a large amount of current and time is expended during this process of programming the phase change memory cells.
FIG. 3 shows the particular time and current expenditure through a program current profile of the general phase change memory cell.
Plot P13rs in FIG. 3 shows the amount of current and time expended when reset data is programmed into a selected memory cell. It should be noted that a large amount of current is applied to the memory cell in a relatively short time, a characteristic of reset data programming.
The process of programming set data, on the other hand, can be understood by the rectangular wave plot P_s1, or the slow quench wave plot P_s2.
According to FIG. 3, a large amount of current is required to program a phase change memory cell. The set data, in particular, requires a great amount of time in addition to a large amount of current.
Therefore, due to time and current constraints, programming a large number of phase change memory cells simultaneously (i.e., multi-cell programming) burdens the phase change memory apparatus with degradation of operation performance. Despite the efficiency of the multi-cell programming, the set data requires a programming time longer than 300 ns on average, due to limitations on current consumption in simultaneously programming multiple memory cells.
The number of memory cells simultaneously selectable from a memory bank in a write operation is dependent on the driving capacity of the write drivers W/D, the current supply capacity of the global bit-line switches 150, the local bit-line switches 160, and the local word-line switches 170. The transistors constituting the drivers and switches should be larger in size, but this may not be helpful to scaling down the phase change memory apparatus.
In a case, considering the capacitive limit of the write drivers W/D and the current supply burden of the switches, there is a programming mode of x8 or x16 in which data are programmed into one or two memory cells in each unit cell array. Accordingly, if data are to be programmed into 512M bit-memory cells in x16 mode in every unit cell array, it is necessary to execute 32M times of programming operations.
Because the production cost is increasingly dependent on the test time of the memory apparatus, there has been a great demand for shortening this particular test time.