1. Field of the Invention
The present invention relates to an ESD protection device for protecting an internal circuit in a semiconductor integrated circuit device, and a manufacturing method thereof.
2. Description of Related Art
A technique of inserting an ESD (Electrostatic Discharge) protection device between a pad and an internal circuit so as to prevent excessive current from flowing in the internal circuit when an ESD surge is applied from the pad, is generally known. The ESD protection device needs to be designed such that current instantaneously flows in the ESD protection device when a voltage applied to the internal circuit or a current flowing in the internal circuit exceeds a rated value.
A MOSFET, a PN diode, or an SCR (Silicon Controlled Rectifier) have conventionally been used as ESD protection devices. In a MOSFET, a current driving capability can be enhanced by designing a channel region so as to have a larger width. Further, in an SCR, a high ESD protection capability can be acquired due to a small holding voltage and a small ON-resistance in a relatively small area. Therefore, both of the MOSFET and the SCR have been widely utilized in the conventional art. The small holding voltage can reduce power consumption as defined by current multiplied by voltage. Furthermore, the small ON-resistance allows the current to instantaneously flow in the ESD protection device, thereby producing an advantage of an excellent ESD resistance.
One example of an ESD protection device utilizing a MOSFET will be explained in reference to FIG. 6.
On a P-type semiconductor substrate 101, an N-type drain region 102 and an N-type source region 103 are formed. On the drain region 102, a drain electrode 104 is formed whereas on the source region 103, a source electrode 105 is formed. Between the drain region 102 and the source region 103 on the P-type semiconductor substrate 101, a gate electrode 107 is formed via an oxide film 106. On both sides of the gate electrode 107, side walls 108 are formed. An LDD (Light Doped Drain) region 109 is formed at an end of each of the drain region 102 and the source region 103 in a direction of the substrate facing the gate electrode 107. On the other hand, a device isolation region 110 is formed at an end of each of the drain region 102 and the source region 103 on a side opposite to the LDD region 109. Outward of the device isolation region 110 in the direction of the substrate, a P well 111 serving as a P-type conductive region is formed, on which a well electrode 112 is formed.
Breakdown occurs mainly when an impact ionization phenomenon becomes manifest. Therefore, in the ESD protection device 100 shown in FIG. 6, breakdown occurs mostly at the drain region 102 in the vicinity of an end of the gate electrode 107 of the drain 102 under a channel region in the case that a concentration of an impurity doped in the drain region 102 is high.
For the ESD protection device, a structure may be adopted in which the width of a channel region is larger than that of an internal device, or a comb structure, or a device having a combination of a MOSFET and an SCR may be adopted.
Devices using a MOS structure as other ESD protection devices are disclosed in Japanese Patent Application Laid-Open (JP-A) No. 5-235283 and Japanese Patent No. 3422313.
An ESD protection device and an integrated circuit including the same are designed in a process that is performed near a final stage of an LSI manufacturing process. Therefore, it is difficult to change the setting of an impurity profile or the like relating to basic characteristics of transistors which have been already optimized.
In addition, in order to reduce the number of masks and the number of processes, an internal device that forms an internal circuit, and an ESD protection device, are formed in the same process. As a consequence, it is difficult to adjust the breakdown voltage of an ESD protection device having the structure shown in FIG. 6 at the final stage, by which stage the internal device has been completely optimized.