1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, to integrated circuits comprising static random access memory devices.
2. Description of the Related Art
Types of semiconductor memory include dynamic random access memory (DRAM) and static random access memory (SRAM). DRAM comprises memory cells having a relatively simple structure, in particular memory cells wherein an amount of charge stored in a capacity is used to represent a bit of information. Due to the simple structure of DRAM cells, a high density of integration can be obtained. However, due to leakage currents in the capacities, DRAM typically requires constant refresh cycles to avoid a loss of information.
In SRAM devices, cross-coupled inverters are used for storing information. In SRAM devices, refresh cycles need not be performed, and they typically allow a greater speed of operation than DRAM devices. However, SRAM comprises memory cells which typically have a more complex structure than the memory cells of DRAM devices, which may limit the density of integration that can be obtained in SRAM devices.
An SRAM device 100 will be described with reference to FIG. 1. The SRAM device 100 comprises an SRAM cell 101, a bit line 102, an inverse bit line 103, a word line 104, a high voltage power supply line 105 and a low voltage power supply line 106.
In the operation of the device 100, the high voltage power supply line 105 can be maintained at a higher voltage than the low voltage power supply line 106. Accordingly, the voltage of the high voltage power supply line 105 will be denoted as “high voltage” and the voltage of the low voltage power supply line 106 will be denoted as “low voltage,” although the high voltage is typically on an order of magnitude of a few volts.
The SRAM cell 101 comprises a first inverter 107 having an input 113 and an output 111, and a second inverter 108 having an input 114 and output 112. The output 111 of the first inverter 107 is electrically connected to the input 114 of the second inverter 108, and the output 112 of the second inverter 108 is electrically connected to the input 113 of the first inverter 107.
Each of the inverters 107, 108 comprises a pull-up transistor, wherein the pull-up transistor of the first inverter 107 is denoted by reference numeral 115, and the pull-up transistor of the second inverter 108 is denoted by reference numeral 116. Moreover, each of the inverters 107, 108 comprises a pull-down transistor, wherein reference numeral 117 denotes the pull-down transistor of the first inverter 107, and reference numeral 118 denotes the pull-down transistor of the second inverter 108.
The pull-up transistors 115, 116 may be P-channel transistors, which may be switched from an on state, wherein they have a relatively high conductivity, to an off state, wherein there is only a relatively low leakage conductivity, by applying the high voltage to their gate electrodes. The pull-down transistors 117, 118 may be N-channel transistors which may be switched from an off state, wherein there is only a relatively low leakage conductivity, to an on state, wherein they have a relatively high conductivity, by applying the high voltage to their gate electrodes.
The SRAM cell 101 further comprises pass-gate transistors 109, 110. The pass-gate transistor 109 is electrically connected between the inverse bit line 103 and the output 111 of the first inverter, and the second pass-gate transistor 110 is electrically connected between the bit line 102 and the output 112 of the second inverter 108. Gate electrodes of the pass-gate transistors 109, 110 are electrically connected to the word line 104. The pass-gate transistors 109, 110 may be N-channel transistors which may be switched from an off state to an on state by applying the high voltage to their gate electrodes. Accordingly, if the high voltage is applied to the word line 104, an electrical connection is established between the inverse bit line 103 and the output 111 of the first inverter, and between the bit line 102 and the output 112 of the second inverter 108.
The device 100 may comprise a plurality of SRAM cells having a structure corresponding to the structure of SRAM cell 101, and may also comprise a plurality of low voltage power supply lines similar to power supply lines 105, 106, a plurality of word lines similar to word line 104, and a plurality of bit lines and inverse bit lines similar to bit line 102 and inverse bit line 103. Typically, there is an array 120 of SRAM cells having rows and columns of SRAM cells, wherein the power supply lines and word lines extend along the rows of the array, and the bit lines and inverse bit lines extend along the columns of the array. Individual SRAM cells of the device 100 may be addressed by applying the high voltage to the word line to which the SRAM cell is connected to switch the pass-gate transistors of the respective cell into the on state and by applying and/or reading voltages from the bit line and the inverse bit line to which the SRAM cell is connected. The other word lines may be maintained at the low voltage. Bit lines and inverse bit lines are typically kept at the high voltage during standby mode and are left electrically floating during reading.
The SRAM cell 101 may have three modes of operation. In a standby mode, the voltage of word line 104 is low, so that pass-gate transistors 109, 110 are in the off state and the inverters 107, 108 are electrically disconnected from bit line 102 and inverse bit line 103. Since the output 111 of the first inverter 107 is electrically connected to the input 114 of the second inverter 108, and the output 112 of the second inverter 108 is electrically connected to the input 113 of the first inverter 107, the inverters 107, 108 can reinforce each other, so that they substantially maintain their respective state. Accordingly, there is a first state of the SRAM cell 101, wherein the output 111 of the first inverter 107 is substantially at the low voltage and the output 112 of the second inverter 108 is substantially at the high voltage, and a second state, wherein the output 111 of the first inverter 107 is substantially at the high voltage, and the output 112 of the second inverter 108 is substantially at the low voltage. These two states may be used to store one bit of information.
For reading the bit of information stored in the SRAM cell 101, the bit line 102 and the inverse bit line 103 may be pre-charged to the high voltage. Then, the bit line 102 and the inverse bit line 103 are left electrically floating and the word line 104 is switched from low voltage to high voltage, so that the pass-gate transistors 109, 110 establish an electrical connection between the bit line 102 and the output 112 of the second inverter 108, and an electrical connection between the inverse bit line 103 and the output 111 of the first inverter 107. Depending on the state of the SRAM cell 101, a voltage difference between the bit line 102 and the inverse bit line 103 is created, which can be sensed by a sense amplifier (not shown) to determine the state of SRAM cell 101.
An issue in reading data from SRAM cell 101 can be avoiding the occurrence of a read disturbance wherein the state of the SRAM cell 101 is inadvertently flipped during the read operation. The stability of the SRAM cell 101 with respect to a read disturbance may be dependent on the so-called beta ratio between the conductivity of pull-down transistors 117, 118 in the on state and the conductivity of pass-gate transistors 109, 110 in the on state. A greater beta ratio may be helpful for increasing the stability of SRAM cell 101 with respect to read disturbances. Since the conductivity of a channel of a field effect transistor in the on state typically increases with an increasing width of the channel of the transistor, from the point of view of stability during the read operation, it may be of advantage if a width of the channel regions of the pass-gate transistors 109, 110 is relatively low compared to a width of the channel regions of the pull-down transistors 117, 118.
For writing data to the SRAM cell 101, the high voltage may be applied to one of the bit line 102 and the inverse bit line 103, and the low voltage may be applied to the other one of the bit line 102 and the inverse bit line 103, depending on the state of the SRAM cell 101 to be obtained after the write operation. Thereafter, the voltage of the word line 104 may be switched from low to high to switch the pass-gate transistors 109, 110 into the on state. Thereby, the voltages applied to the bit line 102 and the inverse bit line 103 are applied to the inputs 113, 114 of the inverters 107, 108. If the initial state of SRAM cell 101 is different from the state to be written to SRAM cell 101, this typically causes the inverters 107, 108 to change their state.
An issue in writing data to SRAM cell 101 can be avoiding a write failure, wherein the SRAM cell 101 does not change its state, although the state to be written to the SRAM cell 101 is different from the initial state. The likelihood of a write failure occurring may be related to a ratio between a conductivity of pass-gate transistors 109, 110 in the on state, and a conductivity of pull-up transistors 115, 116 in the on state, which is denoted as “gamma ratio.” In general, a greater gamma ratio may reduce the likelihood of a write failure occurring.
Accordingly, for avoiding write failures, it may be advantageous if the conductivities of the pass-gate transistors 109, 110 in the on state (and, accordingly, a width of the channel regions of these transistors) are relatively large compared to the conductivities of the pull-up transistors 115, 116 in the on state (and, accordingly, a width of the channel regions of these transistors).
Hence, there may be a trade off between the stability of SRAM cell 101 with respect to read disturbances, and a writability of the SRAM cell 101, which is related to the occurrence of write failures occurring. A greater conductivity of the pass-gate transistors 109, 110 in the on state may be helpful for reducing the likelihood of write failures occurring, but, at the same time, may increase the likelihood of read disturbances.
For avoiding these issues, it has been proposed to modify the design of SRAM cells by separating the write and read path though an additional port. However, such solutions typically require two additional transistors per SRAM cell, and also require an additional read word line per row of the device 100, as well as an additional read bit line per column of the device 100. This can substantially increase the area of the device 100 that is required for storing one bit of information.
In view of the situation described above, the present disclosure is related to a method of writing data to one or more SRAM cells and a device comprising a plurality SRAM cells that allows obtaining a relatively high stability with respect to read disturbances and a relatively low likelihood of write failures occurring, while substantially avoiding or at least reducing an increase of the area of the device required for storing one bit of information.