The present invention relates generally to electronic circuits. More particularly, it pertains to sense amplifiers operating with low voltage supplies.
Lower and lower power supply voltages are being employed on DRAM memory chips, which places more stringent requirements on the design parameters of sense amplifiers. It is difficult to get a conventional sense amplifier to have adequate response characteristics at these lower power supply voltages. FIG. 1A is a schematic diagram illustrating a conventional cross-coupled sense amplifier. FIG. 1B is a graph illustrating the very slow response of the conventional cross-coupled sense amplifier at a power supply voltage of 0.5V. As shown in FIG. 1B, it can take up to nearly 100 nanoseconds (t=100 ns) to achieve a significant sense signal and output voltage from the sense amplifier. This is far too long to be of any use in a conventional memory system.
Recently, synchronous body bias has been utilized in the sense amplifier designs in SOI technology with 0.9V power supply voltages on DRAMs. Examples of this are provided by: S. Kuge et al, xe2x80x9cSOI-DRAM circuit technologies for low power high speed multigigascale memories,xe2x80x9d IEEE J. Solid-State Circuits, Vol. 31, pp. 586-591, April 1996; and K. Suma et al., xe2x80x9cAn SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology,xe2x80x9d IEEE J. Solid-State Circuits, Vol 29, pp. 1323-1329, November 1994. In the synchronous body bias arrangement, the body of the n-channel metal oxide semiconductor (NMOS) transistors are separately forward biased when the sense amplifier is activated to lower the magnitudes of the threshold voltages (Vt). This was found to be necessary to achieve reasonable response time from the sense amplifier at low power supply voltages. Unfortunately, the synchronous body bias arrangement requires extra clock or phase voltages, extra control lines and extra body contacts for the devices. These requirements quickly consume valuable surface area on the semiconductor chip.
Another technique to achieve improved performance from sense amplifiers includes the use of current sense amplifiers in the place of voltage sense amplifiers. Still another technique includes using gate-body connected transistors in the construction of the sense amplifier. Current sense amplifiers achieve a significant improvement in response by virtue of the fact that the voltage swing on the bit lines is very small, and by virtue of the fact that the large bit line capacitances are not connected to the output nodes. However, a current sense amplifier is not compatible with low power supply voltages. This is because the current sense amplifier is basically three devices are stacked up one atop another.
In its basic form, the three devices of a current differential amplifier include a current sink device, designed to provide common mode feedback and rejection, a pair of transistors for amplification, and a pair of load devices. Operation criteria demand that some significant overdrive, e.g., the excess in a transistor""s gate to source potential (VGS) over the transistor""s threshold voltage (VT), or (VGS-VT), is required in order to provide reasonable gain (G).
Another prior art method is basically to use a traditional sense amplifier and after firing the word line, dumping the charge onto the digitlines, then turn off the isolation transistors, perform the sensing process, and then once again turn the isolation transistors back on. This is one approach to attain high-speed sensing by separating the bitline capacitances at the expense of somewhat delaying your write back. However, there is still a delay between turning off the isolation transistors and firing the sense amplifier. And, still even better low-voltage designs are needed.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, it is desirable to develop sense amplifiers with improved response characteristics which can be fabricated according to a CMOS process and which can operate at power supply voltages of 1.0 V and below.
The above-mentioned problems with sense amplifier configuration and operation as well as other problems are addressed by the present invention and will be understood by reading and studying the following specification. Structures and methods are provided which accord exemplary performance.
The new modified sense amplifier for low-voltage DRAMs is as much as 100 times faster than a conventional voltage sense amplifier when low power supply voltages, e.g. Vdd less than 1.0 Volts, are utilized. In the novel sense amplifier, the bit line capacitances are separated from the output nodes of the sense amplifier. High performance, wide bandwidth or very fast CMOS amplifiers are possible using the new circuit topology of the present invention.
A first embodiment includes a sense amplifier having a pair of cross-coupled invertors. Each inverter includes a transistor of a first conductivity type and a pair of transistors of a second conductivity type which are coupled at a drain region and are coupled at a source region. The drain region for the pair of transistors is coupled to a drain region of the transistor of the first conductivity type. A pair of input transmission lines are included where each one of the pair of input transmission lines is coupled to a gate of a first one of the pair of transistors in each inverter. A pair of output transmission lines are included where each one of the pair of output transmission lines is coupled to the drain region of the pair of transistors and the drain region of the transistor of the first conductivity type in each invertor.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.
FIG. 1A is a schematic diagram illustrating an embodiment of a convention sense amplifier.
FIG. 1B is a graphical representation of the output voltage versus time (V-t) curve for the conventional sense amplifier shown in FIG. 1A.
FIG. 1C is a schematic diagram of a small signal equivalent circuit model for FIG. 1A.
FIG. 2A is a schematic illustration of a novel sense amplifier according to the teachings of the present invention.
FIG. 2B is an V-t graph illustrating one embodiment of the operation of the novel sense amplifier circuit shown in FIG. 2A.
FIG. 2C is a schematic diagram of a small signal equivalent circuit model for FIG. 2A.
FIG. 3 illustrates one possible configuration for the inclusion of other transistors in the novel sense amplifier of FIG. 2A as in normally done to achieve enable functions, and precharge and balance of the sense amplifier.
FIG. 4 illustrates a memory circuit formed according to the teachings of the present invention.
FIG. 5 is a block diagram illustrating an electronic system 500 according to the teachings of the present invention.