FIG. 14A shows a conventional level shift circuit. In FIG. 14A, terminal VO outputs a signal that is same in phase as input signal VIN, and terminal VON outputs a signal that is reverse in phase to input signal VIN.
The voltage level of first power source 1000 (hereafter referred to as power source 1000) is V1, the voltage level of second power source 1001 (hereafter referred to as power source 1001) is V2, and the voltage level of third power source 1002 (hereafter referred to as power source 1002) is V3. The voltage level V3 is an amplitude voltage of input signal VIN, and the voltage level V3 is same in voltage level as voltage V2 or a different voltage level. Inverter circuit 1003 executes the logical inversion of the input signal VIN. The voltage level V1 is supplied to the source of the first conduction type transistor 1004 (hereafter referred to as transistor 1004), the input signal VIN is applied to the gate, and the drain is connected to the output terminal VON. The voltage level V1 is supplied to the source of the first conduction type transistor 1005 (hereafter referred to as transistor 1005), a logically inverted signal of input signal VIN is applied to the gate, and the drain is connected to the output terminal VO. The voltage level V2 is supplied to the source of the second conduction type transistor 1006 (hereafter referred to as transistor 1006), the gate is connected to the output terminal VO, and the drain is connected to the output terminal VON. The voltage level V2 is supplied to the source of the second conduction type transistor 1007 (hereafter referred to as transistor 1007), the gate is connected to the output terminal VON, and the drain is connected to the output terminal VO. Signal 1008 is reverse in phase to the input signal VIN.
Regarding a level shift circuit having a configuration as described above, the operation of FIG. 14A will be described by using FIG. 14B. In the following description, when the voltage is at a low level, it is represented by “L”, and when the voltage is at a high level, it is represented by “H”.
When the voltage of input signal VIN is “L”, the voltage of signal 1008 is “H”. Accordingly, the voltage of output terminal VO is V1, and the transistor 1006 is ON. Also, the output terminal VON is same in potential as V2, and the transistor 1007 is OFF.
In the above condition, when the voltage of input signal VIN shifts from “L” to “H” at time T1, then the voltage of signal 1008 shifts from “H” to “L”. At the same time, the transistor 1004 turns ON, and the transistor 1005 turns OFF. Accordingly, the transistor 1006 and transistor 1004 turn ON, while the transistor 1007 and transistor 1005 turn OFF.
At that time, since the drain current Idsn of transistor 1004 is saturated, it can be represented by formula (1).Idsn=Kn(Vgsn−Vtn)2  (1)
As the drain current Idsp of transistor 1006 is not saturated, it can be represented by formula (2).Idsp1=2Kp(Vgsp−Vtp−Vdsp/2)Vdsp  (2)
After that, when the voltage of output terminal VON lowers from V2 to become |V2−VON|>|Vgsp−Vtp|, then the drain current Idsp of transistor 1006 changes to a saturated state, establishing the formula (3).Idsp2=Kn(Vgsn−Vtp)2  (3)
In the formulas (1), (2), and (3), constant Kn is the conduction coefficient of transistors 1004 and 1005, constant Kp is the conduction coefficient of transistors 1006 and 1007, constant Vgsn is the gate-source voltage of transistors 1004 and 1005, constant Vgsp is the gate-source voltage of transistors 1006 and 1007, constant Vtn is the threshold value of transistors 1004 and 1005, constant Vtp is the threshold value of transistors 1006 and 1007, and constant Vdsp is the drain-source voltage of transistors 1006 and 1007.
In case the voltage V3 is higher than V2 when the input signal VIN is “H”, then from formulas (1) and (2), |Idsn|>>|Idsp1| will be satisfied. And, the voltage of output terminal VON lowers from the level of V2. When VON<(V2−|Vtp|) is satisfied at time T2, the transistor 1007 turns ON, and VO rises from the level of V1. Thus, the transistor 1006 changes from a non-saturated state to a saturated state. In this condition, further from formulas (1) and (3), input signal VIN that satisfies |Idsn|>>|Idsp2| is applied, and therefore, the above operation will be continued and the voltage of output terminal VON shifts from V2 to V1, while the voltage of output terminal VO shifts from V1 to V2, thereby completing the level shift circuit operation.
Next, in case the voltage V3 is lower than V2 when the input signal VIN is “H”, then from formulas (1) and (2), the difference between |Idsn| and |Idsp1| is small, and the shifting speed of VON from V2 to V1 is slower than when the condition |Idsn|>>|Idsp1| is satisfied. Accordingly, during that time, a through-current will flow to the power source 1000 from the power source 1001 via the transistor 1006 and transistor 1004. When VON<(V2−|Vtp|) is satisfied at T3, the transistor 1007 turns ON, and VO slowly rises from V1 to V2. Thus, the transistor 1006 changes from a non-saturated state to a saturated state. In this condition, further from formulas (1) and (3), input signal VIN that satisfies |Idsn|>|Idsp2| is applied, and therefore, the above operation will be continued and the transistor 1006 turns OFF. In this way, the through-current stops flowing to the power source 1000 from the power source 1001 via the transistor 1006 and transistor 1004.
As a result of the above operation, VON shifts from V2 to V1, and VO shifts from V1 to V2, thereby completing the level shift circuit operation.
Also when the voltage of input signal VIN shifts from “H” to “L”, the same operation as described above will be executed in the transistor 1005 and the transistor 1007.
In the conventional level shift circuit described above, when the voltage of input signal VIN shifts from “L” to “H”, to achieve the purpose of changing the voltage of VON (and VO) at a high speed, it is required that, from formulas (1) and (2), the condition |Idsn|>>|Idsp1| be satisfied, and from formulas (1) and (3), the condition |Idsn|>>|Idsp2| be satisfied.
Accordingly, it is necessary to increase the area of the transistor 1004 (or transistor 1005), and there arises a problem of causing the layout area be increased.
The above problem obviously appears especially in case of low input signal VIN that makes it difficult to satisfy the conditions |Idsn|>>|Idsp1| and |Idsn|>>|Idsp2|.
Further, in logical inversion of input signal VIN, since there exists a length of time that causes both of the transistor 1006 (or transistor 1007) and the transistor 1004 (or transistor 1005) to turn ON, there arises a problem that a through-current flows to the power source 1000 from the power source 1001.
In order to solve such a problem that the circuit area is increased, for example, as disclosed in Japanese Laid-open Patent H2-188024, it is well known that various current feed circuits are arranged in parallel relation with the transistor 1006 and transistor 1007 of a level shift circuit based on prior art. However, this method is unable to solve a problem such that a sub-threshold current constantly flows when the area is increased due to increasing the number of elements or the current feed circuit is configured with transistors.