Integrated circuits (ICs) generally include various modules combined to perform various functions. For example, a digital signal processor (DSP) includes processor and memory blocks embedded in the IC. The memory blocks containing plurality of addressable memory locations are tested for defects, ensuring the operability of the IC. To test these blocks, special test circuits, referred to as “Built-In Self Test” (BIST) circuits are incorporated into the IC. BIST circuits generate a test pattern to determine whether the memory block is defective or not. In some cases the circuit provides redundant rows and/or columns that are used to repair defective rows and columns in the memory block.
Electronic fuse or Efuse or fuseROM is also used for memory repair. fuseROM store a repair data or repair signature that identifies a defective element in the memory block. A repair signature for all the memory blocks under test is stored in the fuseROM. The repair signature is used for repair of the memory blocks. In a system with many memories, the size of the fuseROM is directly related to the sum of the number of memory blocks under test.
With increasing memories in today's SoCs (System-on-chip), memory repair has become crucial to improve yield in low process technologies such as 45 nm and below. It has been observed across multiple SoCs, that fuseROM area is increasingly becoming an area bottleneck, partly due to the fact that fuseROM utilization is very poor even after memory repair. The repair data load time (autoload time) is a time required to load the repair data from the fuseROM to the plurality of memory blocks. Additionally, for devices where wakeup time is crucial, the repair data load time (autoload time) forms a significant portion of the overall boot time or activation time.
Thus, there is a need to efficiently test memories without requiring an enormous fuseROM area, with low autoload time and without compromising on memory reparability or test quality.