Conventionally, in order to realize size reduction of electronic devices, a semiconductor module including a plurality of semiconductor chips have been manufactured. In order to increase the bandwidth and to decrease power consumption, the semiconductor chips built in such a semiconductor module are connected to each other by wire bonding conventionally used or by bump connection by use of convexed electrodes (bumps) formed on surfaces of the semiconductor chips (e.g., Japanese Patent No. 4809957).
Recently, semiconductor chips have been desired to be thinner in order to decrease the thickness of semiconductor devices or to facilitate formation of through-silicon vias (TSVs). Various methods for processing thin semiconductor wafers have been proposed (e.g., Japanese Laid-Open Patent Publication No. 2010-267653 and Japanese Laid-Open Patent Publication No. 2012-084780). However, manufacturing of a semiconductor module in which thin semiconductor chips are connected to each other by bump connection involves problems that, for example, chip cracks are caused by use of a BSG tape, dicing or pickup, or that bump connection faults are caused by the thin chips being curved at the time of bump connection. In the case where a wafer support is used for easier handling of a thin wafer, there occurs another problem that the cost is increased.