As described in Patent Documents 1 and 2 below, it has conventionally been known that a 3-level inverter outputs three levels of signals and realizes a reduction in harmonics contained in an output voltage, while 2-level inverter output two levels of signals.
A first example of a conventional 3-level inverter, shown in FIG. 11 and FIG. 16, etc. of Patent Document 1 below, has a configuration in which two series-connected semiconductor switching elements (such as Insulated Gate Bipolar Transistors (IGBTs)) are connected between direct current (DC) high potential terminal P and DC low potential terminal N, alternating current (AC) output terminals are further connected to the connection points of the two semiconductor switching elements, and it is divided so that DC high potential terminal P and DC low potential terminal N are symmetrical with respect to intermediate potential terminal M.
A 3-level inverter is also disclosed, in which a bidirectional switch configured of two IGBTs is disposed between the AC output terminals and intermediate potential terminal M in such a manner that reverse connections to each other are made (the 3-level inverter of this first example will be referred to as a “T-type 3-level inverter” hereinafter” in this description).
In the above case, Patent Document 1 discloses an example in which a silicon (Si) element and a silicon carbide (SiC) element are used for the switching element and the diode of a T-type 3-level inverter.
As a second example of a 3-level inverter, FIG. 1, FIG. 4, etc. of Patent Document 1 below disclose a 3-level inverter in which four Insulated Gate Bipolar Transistors (IGBTs) are connected in a four-series connection between DC high potential terminal P and DC low potential terminal N, the connection points being a result of dividing the four-series connection into two, and in which the AC output terminals are connected, the four-series connection is divided into two, and a clamp diode is connected between the connection points of two IGBTs of two-series connections that are paired by the division into two and intermediate potential terminal M (the 3-level inverter of this second example will be referred to as an “I-type 3-level inverter” hereinafter).
In the above a case, Patent Document 1 discloses an example in which a silicon (Si) element and a silicon carbide (SiC) element are used for the switching element and the diode of an I-type 3-level inverter.
FIG. 1 shows a configuration example of a case where a conventional 3-level power conversion circuit is realized by a T-type 3-level inverter, and is included in Patent Document 2 below. In FIG. 1, it is proposed to make the ampacities of diodes D13 and D14 that are in parallel to semiconductor switching elements (such as Insulated Gate Bipolar Transistors (IGBTs)) T13, T14 smaller than those of semiconductor switching elements (such as Insulated Gate Bipolar Transistors (IGBTs)) T11 and T12.
Note in FIG. 1 that symbols P, N and M denote a DC high potential terminal, a DC low potential terminal and an intermediate potential terminal, similarly to the above, and that 101 and 102 denote capacitors serving as power sources for supplying DC voltages.
However, Patent Document 2 does not describe anything about relationships between the ampacities of diodes D13 and D14 that are in parallel to semiconductor switching elements T13 and T14 and those of semiconductor switching elements T13 and T14.
Because SiC (silicon carbide) devices, which have already been put into practical use as a wideband gap semiconductor, operate at high temperatures and are expensive, it is desirable in view of cost that they be used with a minimum possible chip area.
On the other hand, power conversion devices are required to operate with a higher efficiency, making it necessary to increase a chip area in order to lower a conduction voltage of a diode through which the load current flows.
These requirements are contradictory about whether to emphasize cost or efficiency, and it has conventionally been considered difficult to solve these problems.
Patent Document 1: Japanese Patent No. 5554140
Patent Document 2: Japanese Patent No. 5774086