Modern integrated circuits are formed on semiconductor chips. To increase manufacturing throughput and lower manufacturing costs, the integrated circuits are manufactured in semiconductor wafers, each containing many identical semiconductor chips. After the integrated circuits are manufactured, semiconductor chips are sawed from the wafers and packaged before they can be used.
In typical packaging processes, semiconductor chips (also referred to as dies in the art) are first attached to package substrates. This includes physically securing the semiconductor chips on the package substrates and connecting bond pads on the semiconductor chips to bond pads on the package substrates. Underfill, which typically comprises epoxy, is used to further secure the bonding. The semiconductor chips may be bonded using either flip-chip bonding or wire bonding. The resulting structures are referred to as package assemblies.
It was observed that after the semiconductor chips are bonded onto the package substrates, the solders that join the semiconductor chips with the package substrates often suffer from cracking. This is caused by the stress resulting from the difference in coefficients of thermal expansion (CTE) between the package substrates and the semiconductor chips. The difference in CTEs of different layers of the package substrates and the semiconductor chips also results in stresses. It was observed that with the increase in the size of the package substrates and the semiconductor chips, the stress increases. As a result of the stress, the solder may crack, and delamination may occur between different layers in the semiconductor chips. Particularly, the delamination may occur between low-k dielectric layers in the semiconductor chips.