The present invention relates to a process for manufacturing a semiconductor integrated circuit device and a semiconductor integrated circuit device technique; and, more particularly, the invention relates to a technique which is effective when applied to a process for manufacturing a semiconductor integrated circuit device having a DRAM (Dynamic Random Access Memory), and a semiconductor integrated circuit device technique.
The DRAM has a plurality of memory cells each comprising one memory cell selecting MIS transistor and a capacitor connected in series with the MIS transistor, so that its degree of integration is high enough to lower the unit price per bit. Therefore, DRAMs are widely used in main memories for various computers or communication devices that require a memory of high storage capacity.
With developments in technology, the memory capacity of a DRAM has tended to increase more and more. In accordance with this tendency, the area occupied by the memory cell has been reduced with a view to improving the degree of integration of the memory cells of the DRAM.
However, the capacitance of the information storage capacitive element (capacitor) in a memory cell of a DRAM is required to be a certain value from the standpoint of the operation margin, soft errors and so on, independently of the DRAM generation, and cannot be proportionally reduced, as is generally known in the art.
Thus, the capacitor structure has been developed to have a necessary capacitance in a limited small occupation area. As one of the results of these developments, a three-dimensional capacitor structure, such as the so-called “stacked capacitor”, in which two layers of capacitor electrodes are stacked through a capacitor insulation film has been adopted.
The stacked capacitor generally has a structure in which the capacitor electrodes are arranged over a memory cell selecting MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and is represented by a cylindrical or fin type capacitor structure. Either of these structures is characterized in that a large capacitance can be ensured by increasing the size in the height direction of the capacitor, but without increasing the size in the widthwise direction of the capacitor.
A DRAM having memory cells is disclosed in Japanese Patent Laid-Open No. 122654/1995 relating to the so-called “Capacitor Over Bitline (will be abbreviated to COB)” arrangement in which the information storage capacitive elements are provided in a layer over the bit lines.