Serializer/deserializer (SERDES) circuits are becoming ubiquitous in many computational environments. The SERDES can compress a relatively wide, parallel input into a relatively narrow, serial signal (e.g., a single “bit,” differential signal) for communication over a serial bus. The serial bus switches at an appreciably higher rate than the parallel bus, and serial communication of the data stream tends to reduce cost, complexity, power, and board real estate relative to comparable parallel communications. As bus speeds increase, parallel communications manifest even higher power consumption and more issues relating to timing (e.g., skew mismatches and bit misalignment), making SERDES circuits even more attractive.
Typically, the SERDES has one or more components that sample a received analog serial signal into discrete bits for various purposes. For example, the SERDES can include clock data recovery (CDR) and decision feedback equalization (DFE) adaptation components that can attempt to shift clocking locations to optimize sampling reliability. This can involve determining where signal transitions (e.g., zero-crossings) occur, which can often be frustrated by clock jitter, noisy data, small signal levels, and/or other difficult conditions.