Embodiments of the present invention relate to apparatus and methods for transmitting digital data, and more particularly to apparatus and methods for transmitting video data.
Various kinds of apparatus and methods have been proposed to transmit digital data. For example, in a case that the digital data is MPEG-2 system, there are two types of MPEG-2 system where one is a Program Stream (PS) and the other one is a Transport Stream (TS). The program stream is designed to be used in a relatively less error prone environment. On the other hand, the transport stream is designed to be used in an environment where errors occur often, but it can combine multiple programs into a single stream. The transport stream is used in a digital broadcasting. The transport stream is a time division stream where an elementary stream (ES) is divided into transmission units, each unit is called a transport stream packet (TS packet). FIG. 1A shows an example of the transport stream. Each of TS packets A-C comprises a TS header and a payload, and time information PCR (Program Clock Reference) representative of a time reference is set for the TS header of a predetermined TS packet (for example, the packet B). The PCR has the time information that is inserted at a transmitter side by counting a clock, e.g. 27 MHz clock. A synchronized operation is done on a receiver side by reference to the time information PCR.
In such a digital transmission system, especially MPEG-2 system, as shown in FIG. 2, the receiver writes the input transport stream in a FIFO (First-In First-Out) memory 10 in response to an input TS clock and reads out the written transport stream in response to an output TS clock in order to produce an output transport stream. Therefore, the FIFO memory 10 acts as a buffer. The input TS clock signal is generated by reference to the input transport stream. If a frequency of the input TS clock is the same as that of the output TS clock, a writing speed and a reading speed of the FIFO memory 10 are the same and no problems occur. However, if the data process at the receiver side causes the output TS clock frequency to be higher than the input TS clock frequency, namely, if the reading speed is higher than the writing speed, the input transport memory in the FIFO memory 10 goes out and the memory becomes empty and thereby a receiving wait condition occurs. In order to solve this disadvantage, an apparatus shown in FIG. 3 was proposed. In this apparatus, a null packet generator 12 is provided to generate a null packet that is a dummy packet. Control means 14 watches the writing speed and the reading speed of the FIFO memory 10 and controls an electronic switch 16 to insert the null packet into the output transport stream from the FIFO memory when a difference between the writing and reading speeds exceeds an allowable range. In a case that the difference between the writing and reading speeds is out of the allowable range, the switch 16 selects the FIFO memory 10. The out of the allowable range means a situation that the volume of the input (transport) stream stored in the FIFO memory 10 is equal to or less than a predetermined value in accordance with the speed difference between the reading and writing speeds and this situation is just before a situation that it is hard to read out the stream from the FIFO memory in accordance with the speed difference.
An operation as illustrated in FIG. 3 will be discussed by reference to FIG. 1. In FIG. 1, it is assumed that each packet data volume of the input transport stream A is the same as that of the output transport stream B, and each packet length of the output transport stream B is shorter than that of the input transport stream A because the reading speed is higher than the writing speed. In FIGS. 2 and 3, the same reference numbers have been employed to designated like blocks and their operations will not be explained, as they are known to those skilled in the art. First, an electronic switch 16 selects the FIFO memory 10. The input transport stream shown in FIG. 1A is written in the FIFO memory 10 in response to the input TS clock. After the packet A is written completely, the packet A is read out as the output transport steam of FIG. 1B in response to the output TS clock. The packet B is not written in the FIFO memory 10 completely after the packet A is read out. Then, the control means 14 detects this situation of the out of the allowable range, makes the electronic switch 16 to select the null packet generator 12 so as to insert the null packet into the output transport stream B. Since the packet B of the input transport stream is being written in the FIFO memory 10 at a time when the null packet is completely inserted, the control means 14 makes the electronic switch 16 to select the FIFO memory 10 so as to read out the packet B from the FIFO memory 10 as the output transport stream. The operation of writing the packet C of the input transport stream into the FIFO memory 10 is completed at a time when the packet B is completed to be read out. Ongoingly, the FIFO memory 10 is in the reading operation to produce the packet C as the output transport stream.
In this example, the time information PCR representative of the time reference is set to the packet B. In the output transport stream B, the null packet as the dummy is inserted between the packets A and B. Since the time information of the PCR in the packet B takes no account of the time for the dummy packet, a disadvantage is that a PCR jitter occurs.
In order to overcome the above discussed disadvantage, an apparatus shown in FIG. 4 was proposed. The same reference numbers in FIG. 4 have been employed to designated like blocks in FIGS. 2 and 3 and their operations will not be explained, as they are known to those skilled in the art. A first PCR detection means 18 detects a PCR value from the input transport stream. Comparator means 20 compares the PCR value detected by the PCR detection means 18 with the counted value of a PCR counter 24 so as to control an oscillation frequency (for example 27 MHz) of a voltage controlled oscillator (VCO) 22 in accordance with the difference of these values. The counter 24 counts a pulse signal from the VCO 22. Therefore, the blocks 20, 22 and 24 operate such that the counted value of the counter 24 is synchronism with the PCR of the input transport stream. A second PCR detection means 26 detects the PCR in the transport stream from the electronic switch 16. A PCR exchange means 28 exchanges the PCR value in the transport stream from the electronic switch 16 with the counted value of the counter 24 in response to a detection signal from the second PCR detection means 26 (that represents a detection timing of the PCR). Even if the null (dummy) packet is inserted between the packet A and the packet B as shown in FIG. 1B, the PCR counter 24 counts a time for the null packet and thereby the PCR of the packet B is replaced with the new PCR value that takes account of the period of the null packet. Such apparatus is disclosed in, for example, Japanese Unexamined Patent Publication No. 11-239179. In the digital transmission apparatus in FIG. 4, if a transmission is interrupted, the PCR in the packet with PCR becomes an outlying value so that the oscillation frequency of the VCO gets out of order significantly, the counted value of the PCR counter 24 gets out of order too and the PCR exchange means 28 cannot exchange the PCR correctly. In addition, an offset between the counted value from the counter 24 and the PCR value detected by the PCR detection means 18 becomes unstable, so that the PCR value as well as PTS (Presentation Time Stamp)/DTS (Decoding Time Stamp) values should be corrected. For this purpose, an additional PTS/DTS value correction circuit is required.
In order to overcome the above discussed disadvantage of the apparatus shown in FIG. 4, an apparatus shown in FIG. 5 was proposed. The same reference numbers in FIG. 5 have been employed to designated like blocks in FIGS. 2, 3 and 4 and their operations will not be explained. A first PCR detection means 30 detects the PCR from the input transport stream, applies the PCR value to a load terminal of a counter 34 and applies a detection signal representative of the PCR detection timing to a preset terminal PR of the counter 34 and to a synchronous oscillator 32. The synchronous oscillator 32 oscillates a 27 MHz pulse signal in synchronism with the PCR detection timing. The counter 34 loads the PCR when the PCR detection means 30 detects the PCR in the input transport stream and then the counter 34 counts the output pulse from the oscillator 32 from this load value. Therefore, the counter 34 is reset to the PCR value every time when detecting the packet with the PCR from the input transport stream and then the counter 34 counts the pulse from the oscillator 32 from the value to reset to the PCR value. The PCR exchange means 28 exchanges the PCR value of the output transport stream with the PCR value generated by the counter 34 every time when the second PCR detection means 26 detects the PCR in the output from the switch 16. This apparatus is disclosed in, for example, Japanese Unexamined Patent Publication No. 2005-151153.
In the digital transmission apparatus shown in FIG. 5, when plural programs are combined to a single stream, which is one advantage of the transport steam, each program has its own PCR having a different continuity so that the first PCR detection means 30 should detect which program belongs to the detected PCR and a counter 34 is required for each program. Moreover, the PCR exchange means 28 should recognize which program belongs to the PCR detected by the second PCR detection means 26 and should select one of the plurality of counters for exchanging the PCR. The apparatus of FIG. 5 can improve the PCR jitter but is expensive in configuration. The above description is for MPEG-2 system but there is a similar problem in digital data transmission other than MPEG-2 system.
What is desired are digital transmission apparatus and methods that store an input stream at a writing speed, the input stream comprising a packet train including a packet to which time information representative of a time reference, e.g., a PCR is set, and improves the jitter of the time information when reading out the output stream from the memory at a reading speed higher than the writing speed. Such apparatus and method is desired to be simple in configuration and inexpensive for multiple stream trains, e.g., transport streams for multiple programs.