1. Field of the Invention
This invention generally relates to integrated circuit (IC) fabrication and, more particularly, a dual-pixel full color imager with a large well-capacity single photodiode, and associated fabrication process.
2. Description of the Related Art
FIG. 1 depicts a complementary metal oxide semiconductor (CMOS) imager with a “buried” or “pinned” photodiode (prior art). Conventionally, the image cell circuit includes four transistors and one photodiode. The pixel operation is divided into three main stages: reset, exposure, and reading.
(1) The reset stage: by turning on the reset and transfer (Tx) transistors, the photodiode capacitance is charged to a reset voltage. As for the case of the p+np buried photodiode shown in FIG. 1, the buried cathode (n) is totally depleted and set to the pinned voltage (Vpin).
(2) The exposure stage: with the absorption of light by the photodiode, electron and hole pairs are generated. The holes fill the depleted acceptor sites in the p-region, and the electrons fill the depleted donor sites in the n-region. The potential of the photodiode cathode decreases as the photoelectrons fills up at the donor sites.
(3) The reading stage: the pixel value is read out by a correlated double sampling (CDS) circuit. First, the select transistor and the reset transistor are turned on, the floating diffusion (FD) is set to high, and the output is set to the reference level. Then, the transfer transistor (Tx) is turned on, the accumulated photo-electrons in the photodiode are transferred to the FD. Photo-charges in FD are converted to the signal voltage by a source follower (SF) and read out as signal voltage level. The signal is constructed by subtracting the reference voltage level from the signal voltage level (see FIG. 2).
FIG. 2 is a timing diagram associated with of the pixel circuit of FIG. 1 (prior art). The advantage of using a buried photodiode in a CMOS imager sensor is that low dark currents may be obtained. If the charge in the buried n-cathode can be completely depleted during the reset, and the signal electrons in the buried n-cathode can be completely transferred, then zero lag and zero reset noise can be achieved. Several device design parameters optimizations, such as low voltage depleted diode, wide transfer transistor, low threshold voltage, and high gate voltage on transfer transistor must be considered to achieve the complete transfer of the signal electrons in the buried n-cathode.
FIG. 3 is a Bayer color filter pattern (prior art). Conventional CMOS and charge-coupled device (CCD) digital image sensors use a standard photodiode or photogate as the photosensing element. In their native state, the photosensing element captures the light signal as black-and-white. In order to perform color imaging, small color filters are placed on top of each photo sensing element. Usually the red, green, and blue (RGB) color filters are arranged in a Bayer pattern, as shown, which alternately samples red, green, and blue pixels.
A required image-processing step for Bayer pattern sensors is interpolation, during which missing data is estimated from neighboring pixel data. Misalignment of the color filter results in color artifacts, and the color filter adds to the cost of the imager. Furthermore, the continuing design pressures to decrease pixel size act to reduce the photodiode sensing area and the signal strength.
One way to prevent the use of color filters and potentially increase the sensing element area is to stack the photo sensing elements (photodiodes). Silicon has characteristic photon absorption lengths that vary with the energy of the photons absorbed. For the wavelengths of 450 nanometers (nm), 550 nm, and 650 nm, the absorption lengths are 0.24 microns (μm), 1.13 μm, and 3.17 μm, respectively. This variation provides an opportunity to fabricate stacked diode junctions at depths that are capable of separating photons of various wavelengths, using standard CMOS manufacturing processes. Various technologies have been applied to this idea over the past 30 years and full color imaging is available in the market place.
With the pixel size continuing to shrink, the CMOS image sensor faces limitations with regard to both low signal to noise ratio (SNR) and low dynamic range (DR). These limitations result in a degradation of image quality and reduction of usable full range of illuminations. Both the DR and maximum SNR can be improved by increasing the well capacity of the pixel.
For the commonly used buried photodiode active pixel sensor (APS) image sensor structure, the well capacity is represented as:QPD=(Vpin−Vblooming)CPD 
The blooming voltage is the minimum voltage required for stopping the photoelectrons from overflowing into the substrate during high illumination. Therefore, full well capacity can be increased by either increasing the pin voltage or increasing the PD capacitance. Increasing the pin voltage is not a favorable option because it increases the operating voltage and/or decreases the maximum voltage swing at the floating diffusion.
FIG. 9 is a schematic diagram of a stratified photodiode structure (prior art). As reported by Lim et al., a stratified photodiode structure increases the photodiode capacitance and well capacity. The DN1, the insertion-p, and a portion of the DN2 are implanted using an addition mask.
It would be advantageous if the n doped layers in photodiode could be formed in different processes, using separate masks, to create a photodiode with even more well capacity that the above-mentioned stratified structure.