1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and especially to a semiconductor integrated circuit comprising a central processing unit and memories.
2. Description of the Background Art
FIG. 11 is a block diagram showing the structure of a single-chip microcomputer 9a which is a conventional semiconductor integrated circuit of the background art. In the single-chip microcomputer 9a, a block 1 including a central processing unit (also referred to as a “CPU” in the specification and drawings) and peripheral functional devices, random access memories (also referred to as “RAMs” in the specification and drawings) 21a and 22a, and a read-only memory (also referred to as a “ROM” in the specification and drawings) 3 are surrounded by a bonding pad array 4a. 
In terms of electrical properties and the effective use of area, the above components of the single-chip microcomputer 9a are designed as a single unit called a core block 8a. 
For improving the productivity in the layout of the core block 8a, when a plurality of memories (e.g., RAMs) of the same type are located, memories having the same physical configuration have been employed. Here, the “physical configuration” refers to a concept including the number of word lines and the number of data lines. The concept further includes the sequence of access to the word and data lines when consecutive addresses are given.
Referring to FIG. 11, for example, the RAMs 21a and 22a each have 4 bits of word lines (i.e., 16 word lines, not shown) arranged in the Y direction and 3 bits of data lines (i.e., 8 data lines, not shown) arranged in the X direction. In both the RAMs 21a and 22a, an address A6A5A4A3A2A1A0 formed of a plurality of bits is assigned to a data cell as shown in FIG. 12. For example, the address A6A5A4A3A2A1A0=0110100 (=34H) indicates a cell in the location identified by “34H” in FIG. 12.
Since, in this way, both the RAMs 21a and 22a have cells each indicated by the address A6A5A4A3A2A1A0, a higher order bit A7 than the bits forming the address is introduced and the RAM 21a or 22a to be accessed is selected in accordance with the value of this one bit. FIG. 13 illustrates the correspondence between the value of the bit A7 and the RAMs 21a, 22a to be selected.
As above described, the components of the conventional single-chip microcomputer have been designed as a core block in terms of electrical properties and the effective use of area. And, for improving the productivity in the layout of the core block, when a plurality of memories of the same type are located, memories having the same physical configuration have been employed.
Therefore, if more memory space is required, the design of the single-chip microcomputer must start over from the design of the core block.
FIG. 14 is a block diagram showing the structure of a single-chip microcomputer 9b that has more memory space than the single-chip microcomputer 9a. In the single-chip microcomputer 9b, the ROM 3 remains the same but the capacities of the RAMs are doubled. More specifically; RAMs 21b and 22b each have 3 bits of data lines (i.e., 8 data lines, not shown) and 5 bits of word lines (i.e., 32 word lines, not shown). The RAMs 21b and 22b, the ROM 3, and the block 1 are surrounded by a bonding pad array 4b, which forms a core block 8b. The single-chip microcomputer 9b is thus longer in the Y direction than the single-chip microcomputer 9a. 
In this fashion, even if the core block is already designed, the conventional single-chip microcomputers require redesign of the core block for giving more memory space.