1. Field of the Invention
The present invention relates to a method for fabricating semiconductor devices, and in particular to a method for forming a titanium nitride layer and the use of the method for fabricating capacitors of DRAMs.
2. Description of the Related Art
Dynamic Random Access Memory (DRAM) are widely applied integrated circuits. At the moment, the common DRAM cell in the product line is comprised of a transistor and a capacitor. As known to those familiar with this art, a capacitor is used to store electric charges, which provides electronic information. The capacitor must contain a sufficiently large capacitance, so that loss of information is avoided and refresh frequency is reduced.
Highly integrated DRAM elements are fulfilled by capacitors having three dimensional structures. In terms of material, capacitors are usually formed by metal-insulator-metal (MIM), or metal-insulator-semiconductor (MIS). Capacitance can be increased by increasing surface area of storage plate, increasing the dielectric constant of the dielectric layer, or reducing thickness of the dielectric layer. In the first method, capacitors having rugged surfaces, such as fin or tree shape are derived. For the third method thickness of the dielectric layer is currently very thin, and when smaller than 50 angstroms, direct tunneling is easily induced, causing excess leakage. This is not advantageous for element performance. As a result, there has been research into dielectric material having high dielectric constant to replace the commonly used silicon oxide. Tantalum pentoxide (Ta2O5) is a newer, valued option. It has replaced SiO2 or Si3N4 to become a more ideal dielectric material. The reason is the high dielectric constant of Tantalum pentoxide, about three times that of Si3N4, i.e. 22˜25. Hence, the stored charges increase greatly and performance of elements is improved.
A general structure for a stacked capacitor using Ta2O5 as the dielectric layer is shown in FIG. 1, wherein 2 represents the MOS transistor, 10 represents plug and lower electrode plate formed by conductive material, such as polysilicon or tungsten, 12 is the Ta2O5 capacitance dielectric layer, 14 is the upper electrode plate formed by TiN, and 16 is the inner dielectric layer. Although not drawn in the figure, the capacitance dielectric layer 12 separates the upper electrode plate and the lower electrode plate. The upper electrode plate of TiN on the Ta2O5 capacitance dielectric layer is usually formed by chemical vapor deposition and annealing. However, conventionally, the electrical properties, such as resistance (Rs) and leakage cannot meet the requirements simultaneously. That is, when high deposition temperature (600° C. and above) is used, Ta2O5 film is damaged, and the formation of TiO2 upon the Ta2O5 causes increased leakage of TiN. if deposition temperature is lower (500° C. or less), the obtained TiN film exhibits high resistance. In other words, either high resistance or high leakage is induced by conventional processes.