1. Field of the Invention
This invention relates to memory management in which access protection information is examined simultaneously with translation of the virtual address of the protected signal.
2. The Prior Art
Every computer has at least one section in which data is processed and at least one memory in which data is stored, either waiting to be processed or after it has been processed, or both. It is desirable to have the memory as accessible as possible to the processor and to have as much storage capacity as desired. However, some compromise is always necessary. There is always a limit to the amount of information that can be stored in a memory to which the processor has relatively rapid access, and so it is common to provide a less accessible memory, such as a disc or tape or other device, on which more information can be stored. The more accessible memory is commonly called the main, or primary, memory and the less accessible one a secondary, or auxiliary, memory.
A system having two or more memories related as has just been described is referred to as a hierarchical memory system. The secondary memory is connected in a hierarchical system in such a way that storage space in the main memory can be dynamically allocated to blocks of information fetched from the secondary memory when required by the program or programs running in the computer. The address of a data word in the secondary memory is referred to as its virtual address, and the address of the same data, when fetched from the secondary memory and stored in the main memory is referred to as its real, or physical, address. Data is not usually fetched one word at a time from the secondary memory; instead, a related block of words is fetched at one time for relatively temporary storage in the main memory. The same block may be fetched and replaced more than once in the execution of a program, and each time it is fetched, it may be stored at a different real address in the main memory. To simplify the programmer's task, hierarchical memory systems are arranged so that the data is always addressed by its virtual address, not by the real memory address, even though the data must be at a real address in the main memory when it is in use in a program.
The correlation between each virtual address and the corresponding real address of information brought into the main memory is kept track of automatically by translation means in the computer. In the course of executing a program, the computer generates virtual addresses that are automatically applied to address translation means to be translated into the corresponding real memory addresses. If those virtual addresses have already been fetched and stored in the translation means, the translations can be accomplished and access can thereby be obtained to the coresponding data fetched from the secondary memory and stored at those real addresses in the main memory. If such fetching of a virtual address has not previously taken place, the attempt at address translation will, of course, not yield a corresponding real address, and the virtual address, together with the data stored there in the secondary memory, will have to be fetched at that time.
Not all information fetched into main memory as just described can be used without restriction. If the information is being used in more than one program, security measures are required to ensure that one user's program does not illegally access or modify information that is private to another user (for example, bank account information). Nor is it permissible to modify the code of the operating system. There are still other reasons for denying access to information stored at certain virtual addresses, and all such denial may vary from program to program and even from time to time in the same program. Heretofore, the protection code, or attributes, have been fetched and stored in the real memory along with data that is to be protected, and it has been necessary to carry out the translation of the virtual address first and then to examine the information at the real address to learn if there were any access prohibition code included with the data stored there.
A number of U.S. Patents relating to memory management have come to the attention of Applicant and his attorneys during the preparation of this application and are included in the following list, but none of them suggests the present invention:
U.S. Pat. No. 3,588,839 entitled "Hierarchical Memory Updating System" by L. A. Belady et al.
U.S. Pat. No. 3,725,870 entitled "Parallel-Access Data File System" by M. Felcheck et al.
U.S. Pat. No. 3,811,117 entitled "Time Ordered Memory System and Operation" by R. A. Anderson, Jr. et al.
U.S. Pat. No. 4,055,851 entitled "Memory Module with Means for Generating a Control Signal that Inhibits a Subsequent Overlapped Memory Cycle During a Reading Operation Portion of a Reading Memory Cycle" by S. R. Jenkins et al.
U.S. Pat. No. 4,084,225 entitled "Virtual Address Translator" by L. D. Anderson et al.
U.S. Pat. No. 4,084,230 entitled "Hybrid Semiconductor Memory with On-Chip Associative Page Addressing, Page Replacement and Control" by R. E. Matick.
U.S. Pat. No. 4,096,568 entitled "Virtual Address Translator" by D. B. Bennett et al.
U.S. Pat. No. 4,177,510 entitled "Protection of Data in an Information Multiprocessing System by Implementing a Concept of Rings to Represent the Different Levels of Privileges Among Processes" by M. Appell et al.
U.S. Pat. No. 4,224,664 entitled "Apparatus for Detecting When the Activity of One Process in Relation to a Common Piece of Information Interferes with Any Other Process in a Multiprogramming/Multiprocessing Computer System" by M. G. Trinchieri.