In the general development of integrated circuits toward greater packing densities, MOS transistors having a reduced space requirement are needed. In a miniaturization of the structure of an MOS transistor a shortening of the gate length occurs. Either high leakage currents or high threshold voltages are observed in MOS transistors having gate lengths below 0.25 .mu.m. Both are disadvantageous and cannot be accepted for MOS transistors of this technology generation.
It is known to avoid these disadvantages (see K. Yamaguchi et al., Jap. J. Appl. Phys. 22, suppl. 22-1, pages 267-270 (1983)) by employing a delta-doped layer in the channel region between source and drain. The delta-doped layer thereby represents a replacement for an anti-punch implantation.
A delta-doped layer has a thickness of approximately 20 nm and it is doped with the conductivity type opposite the source and drain region. It has a dopant concentration of more than 10.sup.19 cm.sup.-3. In comparison to the traditional anti-punch implantation that forms a smeared distribution in the substrate, the dopant concentration in delta-doped layers is strictly localized.
It is known to manufacture MOS transistors having a delta-doped layer with a MESA insulation (see A. A. van Gorkum et al., J. Crystal Growth 95, pages 480-483 (1989). The wiring, however, is thereby difficult. Further, this method is not suitable for use in a manufacturing process for integrated circuits having ultra large scale integration (ULSI).