Although the invention can in principle be applied to any method of manufacturing a semiconductor device comprising stacked chips, the invention and its underlying problem will be hereinafter explained for a manufacturing method of a semi-conductor memory device comprising two memory chips.
Modern electronic articles, like computers, mobile phones, cameras, are composed of a plurality of individual electronic devices including semiconductor memory devices. It is requested for the manufacturing process to reduce the amount of individual electronic devices in order to shorten the manufacturing time of the electronic articles. Therefore, several memory chips are grouped within a single semiconductor memory device such that these memory chips may be arranged in the electronic article by a single manufacturing step. Further, it is requested to miniaturize the electronic articles. By grouping or a pre-integration of the memory chips within a single housing a higher integration density of the memory chips may be achieved and thus their external dimensions reduced.
One generally known semiconductor memory device comprises two memory chips as illustrated in FIG. 1. A first memory chip 110 is placed on an interposer substrate 150 and electrically connected with the interposer substrate 150 via contacting pads 152 and bonding wires 151. The contacting pads 152 are arranged along a border of an active surface of the first memory chip 110. A spacer 160 is fixed by an adhesive layer 161 to the active surface of the first chip 110 in an area between the contacting pads 152. A second memory chip 110′ is fixed on top of the spacer 160. The second memory chip 110′ is as well provided with contacting pads 152′ at a border of an active surface of the second memory chip 110′. The contacting pads 152′ are connected via bonding wires 151′ with the interposer substrate 150. The above described arrangement allows an interconnection of the memory chip 110 and the second memory chip 110′ via the interposer substrate 150, and thus the amount of external contacts 153 may be reduced. Additionally, the space occupied by the two memory chips 110, 110′ integrated within one housing 154 is significantly reduced compared to two semiconductor memory devices comprising each an encapsulated single memory chip.
The bonding wires 151, 151′ should be applied with a minimal pressure to the contacting pads 152, 152′. As the spacer 160 provides no mechanical support to the border of the second memory chip 110′, i.e. to the area of the contact pads 152′, the contacting of the bonding wires 151′ leads to a significant mechanical stress within the second memory chip 110′. In order to avoid damages of the second memory chip 110′, its thickness cannot be further reduced. Additionally, the spacer 160 itself contributes to the height of the semiconductor device. Thus a further reduction of the external dimensions of the semiconductor memory device is not feasible with the aforementioned concept.
A further drawback of the above structure resides in the fact that each bonding wire 151, 151′ must be individually contacted with the contacting pads with a bonding machine during a manufacturing process. These bonding steps significantly contribute to the manufacturing and thus the costs of the semiconductor memory device.