Field programmable gate arrays (FPGAs) are integrated circuits generally characterized by configurable logic blocks with programmable interconnects. FPGAs are designed to be reprogrammed subsequent to manufacture. A combination of a pass transistor and a memory cell such as static random access memory (SRAM) is conventionally used as a binary memory wiring switch in FPGAs. The area taken by the pass transistor and the SRAM cell (comprised of several transistors) is a large fraction of the total area inside a FPGA.
FIG. 1 illustrates a conventional floating gate memory device 20 including a “normally off” transistor structure. The device includes an electrically insulating layer 22 such as a buried oxide (BOX) layer. Silicon dioxide is among the materials from which the insulating layer may be formed. A semiconductor layer 24 including highly doped source and drain regions 26 and a channel region 28 adjoin the electrically insulating layer 22. The source and drain regions 26 have the same conductivity type (n+) while the channel region is p−. A drain electrode 30 is formed directly on one of the regions 26 and a source electrode 32 is formed directly on the other of the regions 26. A tunneling dielectric layer 34 adjoins the channel region 28 and a floating gate 36, for example a p+ polysilicon layer. A second (gate) dielectric layer 42 such as a high-k dielectric layer adjoins the floating gate. A gate 44 adjoins the second dielectric layer and is functional as a control gate. The transistor structure turns on if the read voltage on the gate 44 is higher than the programmed threshold voltage of the device. A positive gate bias is applied to perform a write function. An electron channel is formed in the p− channel region 28 close to the interface with the tunneling dielectric layer 34. The floating gate 36 is negatively charged by tunneling of channel electrons into the floating gate. In NAND flash applications, hot electrons, energized by the lateral electric field, tunnel into the floating gate. In NOR flash applications, electron tunneling is via the Fowler-Nordheim (direct tunneling) mechanism. Program voltages are relatively high (typically>10V) due to thick tunnel dielectric (typically>10 nm) required for sufficient retention. A positive gate bias is required to perform a read function. The negative charge retained in the floating gate 36 results in a net positive threshold voltage shift. The transistor does not turn on if the read voltage on the gate is lower than the new threshold voltage. A negative gate bias is provided to implement an erase function. The electrons tunnel out of the floating gate 36 into the n+ regions 26. The erase voltages are also relatively high (typically<−10V) due to the thick tunneling dielectric layer 34.