Aspects of the present invention relate generally to the field of circuit design and test, and more specifically to static timing analysis and simulation of electronics.
Integrated circuit (IC) design is increasingly complex, sometimes involving millions of elements, shapes or geometries, and may be facilitated with an electronic design automation (EDA) tool that allows a designer to interactively position (“place”) and connect (“route”) various shapes on the circuit. The EDA tool then creates a circuit layout containing the physical locations and dimensions of the circuit's components, interconnections, and various layers from the original design that may then be fabricated, creating the IC. The designed IC is eventually fabricated by transferring or printing the circuit layout to a semiconductor substrate in a series of layers that collectively will form the features that constitute the devices that make up the components of the integrated circuit.
After or during the design and creation of an IC layout, validation, optimization, and verification operations are often performed on the IC layout using a set of testing, simulation, analysis and validation tools. These operations are conventionally performed in part to detect and correct placement, connectivity, and timing errors. For example, as part of the verification, the IC layout may undergo circuit simulation and analysis where the signals between components are tested, for example using static timing analysis (STA) or gate level simulation (GLS). STA is used to model the expected timing of a digital circuit by estimating the expected delay within the circuit, for example, via the anticipated worst case signal path, without requiring a lengthy and cost prohibitive full simulation of the circuit.
During STA, a circuit design is reduced to a series of simplified models that are used to simulate the timing of the design. Then the STA considers a conservative scenario for the circuit using a model of the longest path in the design to evaluate the input and output signal slews and identify the delay. As part of the STA, a plurality of waveforms can be applied to the design models to evaluate the timing of the design. The waveforms applied during traditional STA are often represented by a single number—the slew of the waveform. However, waveform effects can cause significant errors in the delay calculations of the timing analysis. A waveform effect is the deviation of an actual waveform shape from an applied waveform. Waveform effects can be caused by wire resistance, nonlinear pin capacitance, back-Miller effect, crosstalk, a difference in the characteristics of the cells, etc. Additional information about the actual waveform is needed to counteract such inaccuracies. However, maintaining such waveform information for all pins of a design has conventionally been costly and impractical.
Therefore, there is a need in the art to accurately and efficiently propagate more comprehensive waveform information to account for waveform effects when simulating a circuit design.