FIGS. 1 and 2 schematically depict a typical prior art single binary digit (i.e. 1-bit) six-transistor (6 T) SRAM bit cell incorporating cross-coupled inverters 1, 2. Inverter 1 is formed by PMOS “pull-up” transistor P1 and NMOS “pull-down” transistor N1, as shown in FIG. 2. PMOS transistor 1's source is connected to a logic 1 voltage reference (Vd1==Vdd), PMOS transistor 1's drain is connected in series with NMOS transistor 1's drain, NMOS transistor 1's source is connected to a logic 0 voltage reference (Vg1==system ground, Gnd), and PMOS transistor 1's gate is connected to NMOS transistor 1's gate. Inverter 2 is formed by PMOS pull-up transistor P2 and NMOS pull-down transistor N2. PMOS transistor P2's source is connected to Vd2 (==Vdd), PMOS transistor P2's drain is connected in series with NMOS transistor N2's drain, NMOS transistor N2's source is connected to Vg2 (==Gnd), and PMOS transistor P2's gate is connected to NMOS transistor N2's gate. Inverters 1, 2 are cross-coupled by connecting the gates of PMOS transistor P1 and NMOS transistor N1 to the drains of PMOS transistor P2 and NMOS transistor N2 to define a first storage node Q; and, by connecting the gates of PMOS transistor 2 and NMOS transistor 2 to the drains of PMOS transistor 1 and NMOS transistor 1 to define a second storage node Q. The source-to-drain path of NMOS pass transistor N3 is connected between first storage node Q and first bit line, BIT, and the gate of NMOS transistor N3 is connected to read-write word line RW. The source-to-drain path of NMOS pass transistor N4 is connected between second storage node Q and second bit line, BIT, and the gate of NMOS transistor N4 is connected to word line RW.
Pass transistors N3, N4 are selectively turned on from a decoder (not shown) via word line RW to read or write data from/to the bit cell via bit lines BIT, BIT. The cross-coupled structure of inverters 1, 2 ensures that logically opposite voltages are maintained at first and second storage nodes Q, Q respectively. The properties (e.g. Width, Length, and threshold Vt) of transistors P1, P2, and N1 through N4 are selected to accommodate conflicting circuit requirements for reading and writing. Large numbers of such bit cells are combined to form memory arrays, therefore any reduction in size is of considerable commercial interest.
FIG. 3 schematically depicts another prior art SRAM bit cell incorporating cross-coupled inverters. The FIG. 3 bit cell is schematically similar to the FIG. 1 bit cell, except that NMOS pass transistor N4 and associated BIT line have been removed.
In the FIG. 3 embodiment, data are written into the bit cell by applying a logic high voltage signal, Vdd, to the read-write word line RW, thereby turning NMOS transistor N3 on coupling node Q to the BIT line which must also be driven to the correct datum logic voltage value. A datum is read from the bit cell by first setting the BIT line to an intermediate (pre-charge) voltage, usually above or close to Vdd/2. Then, by applying a logic high voltage signal, Vdd, to word line RW, internal node Q is connected to the BIT line through transistor N3. If Q is initially high (storing a logic 1), the BIT line is pulled weakly higher by P2 whereas if Q is initially low (storing a logic 0), the BIT line is pulled lower by N2. A sensing circuit, not shown, is used to determine when the BIT line is being pulled high and when it is being pulled low.
The writing of a logic 0 value from BIT through NMOS transistor N3 into the FIG. 3 bit cell is a relatively “strong” event, in that NMOS transistor N3 inherently pulls down to ground, so if a logic 1 value is already stored at node Q, that value is easily overwritten by the logic 0 value. However, the writing of a logic 1 value through NMOS transistor N3 into the FIG. 3 bit cell is a relatively “weak” event, in that if a logic 0 value is already stored at node Q, NMOS transistor N3 tends to shut off before the stored logic 0 value is fully overwritten by the applied logic 1 value. Consequently, the operation of writing a logic 1 value into the FIG. 3 bit cell may fail or require an unacceptably long period of time. One way to compensate for this is to preferentially adjust the sizes (and possibly thresholds) of the transistors in inverters 1, 2, as well as transistor N3, so that a “weak” logic 1 value driven onto inverter 1's node Q, more easily cross-couples through node Q and inverter 2 to complete the writing event at node Q. While this technique can be made to work, as taught by Carlson et al (European Solid-State Circuits Conference, ESSCIRC, 2004, pp 215-218), the drawback is that larger transistors consume additional integrated circuit silicon area and power. Since the primary advantage of the 5 T cell over the 6 T cell is a reduction in silicon area, the full advantage of a 5 T cell is not realized with this technique.
FIG. 4 depicts another 5 T bit cell, as taught by Tran (Symposium on VLSI Circuits, 1996, pp 68-69). In this invention, transistor Nb is inserted between bit cell node Vg2 and system ground to facilitate a write 1 operation. Many bit cells in a column are usually connected to transistor Nb in the preferred embodiment, although only one of them has its RW line activated (selected) at a time. Capacitor, Cg2, is chosen to limit the voltage increase on Vg2, which rises during a write 1 operation. Prior to any read or write, node WriteZ is high, thereby maintaining node Vg2 at Gnd as its standby state. At the beginning of a write, node WriteZ is driven to Gnd shutting off transistor Nb, so that node Vg2's voltage is held by capacitor Cg2. During a write 1, when storage node Q must be forced from logic 0 to logic 1, floating node Vg2 is pulled up via transistors N2 and N3 so that the voltage on storage node Q can more easily exceed the trip voltage of the bit cell's first inverter, to help change the storage state of Q from 0 to 1. This write-assist technique eases the burden of designing a 5 T cell that reads and writes with more equal facility, although the low standby power objective is not met. Care must be taken to limit the rise of Vg2 as other cells in the same column, which are not being accessed, are write-disturbed by the rise of Vg2 which connects to a whole column (or sub-column). Another write-assist approach is set out in U.S. Pat. No. 6,044,010, where node Vg2 of FIG. 4 is driven across multiple columns of bit cells, in the same direction as the word line, RW. This approach requires 2 steps to write data, a pre-write step and a write step. It also fails to meet the low standby power objective.
Another write-assist method is to reduce the logic 1 voltage value (Vdd or Vd1, Vd2 in FIGS. 1-4) during a write operation as taught in U.S. Pat. No. 6,205,049. Furthermore, individual voltages to inverters 1,2 in FIGS. 1-3 can be varied as taught by Kushida (U.S. Pat. No. 6,940,746) and Hobson (Proc. 2009 Conf. on Computer Design, pp 10-16). The latter reference combines a reduction in Vd1, Vd2 and an increase in Vg1, Vg2 to both lower standby leakage power and provide a write 1 assist for 5 T bit cells, as shown in FIG. 5. A disadvantage of the control circuitry in FIG. 5 is that the number of transistors used to control Vd1, Vd2 and Vg1, Vg2 is significant, thereby reducing the potential area savings of a 5 T bit cell. A further disadvantage of FIG. 5, is that transistor, e, used for “equalizing” Vg1, and Vg2 during a write operation, slows the write operation by passing charge from Vg2 onto Vg1.
When a memory requires a large number of bit cells, the standby leakage power of said cells may become excessive, especially for battery operated applications. One method to reduce the leakage power of a bit cell, as taught by Mann et al. (IBM J. Res. And Dev. Vol. 47, No. 5/6, September/November 2003, pp 553-566), is to use transistors P1, P2, N1 to N4 (in either a 5 T or a 6 T bit cell) which have higher turn-on thresholds, Vt. This is because off-state channel leakage current is exponentially related to threshold voltage. Higher pass transistor thresholds worsen the write 1 problem because, for example, pass transistor N3 shuts off earlier when its threshold is increased, thereby having even less pull-up capability at storage node Q. This drawback can be reduced by driving word line RW slightly above the bit cell Vdd voltage, as taught by Huffman et al in U.S. Pat. No. 6,191,883.
Standby power can also be reduced if the voltage across bit cells is reduced. This may be accomplished either by reducing the logic 1 voltage value (Vd1, Vd2, FIGS. 1, 2), or increasing the logic 0 voltage value (Vg1, Vg2, FIGS. 1, 2), or simultaneously lowering Vd and increasing Vg, as taught by Khellah et al (IEEE JSSC, Vol. 42, No. 1, January 2007, pp 233-242). An embodiment of this is also shown in FIG. 5 (Proc. 2009 Conf. on Computer Design, pp 10-16). Another embodiment of this technique is taught in U.S. Pat. No. 7,372,721, where voltages Vh and V1 are used to retain 6 T bit cell state, Vh (Vh<Vdd) being used for logic 1 and V1 (V1>Gnd) being used for logic 0. A drawback of the latter teaching is that noise margin during a read operation, especially at higher temperatures, could be significantly reduced. It is further affected by manufacturing process parameter variations which can cause unwanted asymmetry in a 6 T bit cell.
Prior to a 5 T bit cell read operation, the BIT line should be pre-charged or set to a safe voltage that minimizes the loss of noise margin due to connecting node Q (FIG. 3) to the BIT line. Prior art designs generally pre-charge BIT lines to Vdd/2 or higher voltages. According to simulations, the voltage which maximizes Read-Noise-Margin (RNM) for the fast-NMOS, slow-PMOS (FS) process corner is the best one to use for all process corners (Jarollahi et al, Proc. Midwest Symposium on Circuits and Systems, MWSCAS 2010, pp 121-123). This voltage may be less than Vdd/2. If a separate time slot or cycle is required for a pre-charge operation, as in Carlson et al (European Solid-State Circuits Conference, ESSCIRC, 2004, pp 215-218), this time may not be fully recoverable by overlapping with other operations, such as decoding. It is thus desirable to be able to “park” BIT lines at a standby voltage that not only maximizes RNM, but may also be used for a bit cell standby power reducing voltage, Vsb.
The present invention addresses 5 T bit cell prior art drawbacks related to maintaining BIT line voltage while simultaneously reducing bit cell standby power and providing write 1 support.