Q:

Please explain what happens when I run this Makefile

I'm learning flex and (for really the first time) using the command line.
I created a Makefile to simplify my testing process but I don't understand why the commands are in reverse.
For instance, in the terminal the order is as such:
flex test.l

this creates the file lex.yy.c
then I compile that:
g++ lex.yy.c -ll -o test

The Makefile reads backwards:
test: lex.yy.c
     g++ lex.yy.c -ll -o test

lex.yy.c: test.l
     flex test.l

So what happens specifically when I run make?  

A:

Makefiles follow this format (Makefiles should always use tabs instead of spaces, since it is required in most (if not all) implementations of make) :
target: dependencies
    operations to build target

The target is what you're willing to build/compile/create. There may be several of them, and they should be built in the Makefile order, unless dependencies need to be met first. The first target in your file is called the default target, it is what make tries to build when you call it without arguments.
The dependencies are the different pieces required to build a target.

In this Makefile, you have two targets:

test
lex.yy.c

Since lex.yy.c is a dependency required to build test, it'll be built first from test.l. Once it is generated, it'll be possible to compile test. Basically, make... :

Tries to build test.
Unresolved dependency. lex.yy.c does not exist (or has been updated), it needs to be built first.
Reading operations to build lex.yy.c. Running flex test.l : lex.yy.c is built.
All dependencies for test are met. Running g++ lex.yy.c -ll -o test.
test is created.

Additional info: For more information about makefiles, I would recommend The Linux Development Platform by Rafeeq Ur Rehman. Chapter 4: Using GNU Make.

A:

Make calls the target test first, but lex.yy.c is a dependency.
So before perform the real execution, make analyzes your targets and all dependencies.
The first target is test, but before start to execute it, lex.yy.c is called.

