Integrated circuits are currently being designed with substantially increased speed and complexity. The development of these complex high-speed integrated circuits increasingly depends upon the ability to test the circuitry sufficiently to ensure proper operation. As the number of logic gates in a given integrated circuit increases along with the overall clocking speed, the difficulty of testing the circuitry increases. The input test data, hereinafter referred to as test vectors, must also increase in order to gain sufficient fault coverage for the possible input states.
On less complex digital ICs, a commercial test machine within the factory is sufficient to test for functionality, by probing the wafer or testing the packaged part directly. For more complex chips, the fault coverage using this method is usually less than 100%. This coverage is dependent on how many vectors are used, how well the vectors are written, and the degree of complexity of the circuitry to be tested. Even if full coverage was attainable, this testing scheme cannot function with sufficient speed to test high-speed parts at their normal operation speed. As well, standard test vectors applied to the bond pads, as described above, cannot always be applied to digital circuitry requiring testing that is embedded in an application specific integrated circuit (ASIC) design.
A technique for testing that has been implemented within IC chips is Built In Self Test (BIST). This technique, includes internal BIST circuitry which is triggered to perform a predefined test with use of an externally applied signal to the chip. Typically during a BIST, a shift register produces a pseudo-random sequence that is applied to the circuitry under test. An expected signature is then compared to the outputs from the circuitry under test. BIST, although being used successfully in many areas, has a number of problems. For one, despite having BIST solutions for regular structures such as memories, there is no general way known to produce BIST for random logic with high fault coverage. In addition, BIST requires adding area resources and possibly speed resources to the chip, hence increasing costs and decreasing marketability.
To overcome the above problems and to allow for testing of more complex IC chips, a Joint Test Action Group (JTAG) test port was developed to perform on site testing of IC chips mounted on a board. The standard for the JTAG test port is defined as the Institute of Electrical and Electronics Engineers, Inc. (IEEE) Standard 1149.1, IEEE Standard Test Access Port and Boundary-Scan Architecture. In this standard, a Test Access Port (TAP) is added to each device under test or group of devices on a board. The TAP includes a test clock (TCLK) pin, a test mode select (TMS) pin, a test RESET pin, and a test data in (TDI) pin for inputting to the device under test, and a test data output (TDO) pin used to output from the device. All devices incorporating the JTAG standard contain a boundary scan register and a bypass register. The boundary scan register provides for serially shifting any desired data pattern from the TDI pin into the input stages of the device, for receiving the output data of each output stage of the chip, and for serially shifting these bits out through the TDO pin. The TMS allows for the enabling of the boundary scan register, the TCLK allows for the clocking of the registers, and RESET allows for the resetting of the registers.
One key advantage of the JTAG standard is that it allows arbitrary data to be serially scanned into a device's boundary scan register, with each bit position corresponding to an input or output terminal of the device. The data may then be applied as if it were test vectors input to or output from the chip. A problem with the JTAG testing scheme is that testing of a chip by serial scanning is relatively slow; hence functional testing cannot be performed at the full chip speed. This concern becomes more prevalent as newly designed IC chips gain increasing speeds.
Typical testing speeds for relatively low-speed testers that have the capability of JTAG scan testing range as high as 50 to 100 MHz. There currently exist publicly available testers capable of testing IC chips that function at much higher speeds. For example, an HP (Hewlett Packard) 83000 Model F660 tester produced by Hewlett Packard of Palo Alto, Calif. allows for testing in the range of 660 MHz to 1 GHz. Unfortunately, this tester only allows for 4 Megabytes of memory per pin for the input of test vectors, which is insufficient for a scan testing procedure on any relatively complex chip. This memory is heavily integrated on the tester, is water cooled, and has very high power consumption. Thus, adding memory to the tester is not a viable solution.
The method currently used to test complex high-speed integrated circuits is a two stage testing procedure. First the chip is tested for functionality using a low-speed tester that has the capability for scan testing. Secondly, the chip is tested on a high-speed tester such as the HP F660 tester to ensure proper workings at full chip speed. This two tiered system increases testing time and time to market of the chips since this procedure must be performed for every individual IC. Along with the increased time to market, the two tiered test system also requires that the device be handled twice, hence increasing the potential of damage to the device, and increasing the required capital investment for testing, that being two testers and their supporting facilities.
Therefore, a testing system is needed that will allow the scan testing protocol defined by the JTAG testing scheme to be implemented with a tester such as the high-speed HP 83000 F660. This system requires the capability to add memory resources to the tester without making any significant modifications to its internal hardware. As well, this testing system should not require the additional implementation of further test circuitry within the chip, hence increasing die area and therefore cost required for the testing of the chip. With such a testing system both full operating speed testing and scan testing should be performed with the same tester, thus eliminating the need for the scan testing tester, as well as the handling time associated with transporting each device under test to the second tester.