The present invention relates to semiconductor devices, and more particularly to a strained Si/silicon germanium-on-insulator (SGOI) structure having an elevated source/drain region and a raised trench isolation region. The present invention also relates to a method of fabricating such a strained Si/SGOI structure.
Improvements in transport properties, i.e., carrier mobility, through strain have been demonstrated in the operating characteristics of field effect transistors (FETs). For complementary metal oxide semiconductor (CMOS) devices, an improvement in device characteristics through carrier mobility has significant potential for the fabrication of very high-speed devices. Strained silicon on a relaxed SiGe substrate is one system where such an improvement occurs.
Experimental research on enhanced carrier mobility MOSFETs caused by strain has concentrated on a strained Si layer grown on a relaxed SiGe layer that is located on a bulk semiconductor wafer. MOSFETs fabricated using a strained Si/SiGe system exhibit the following disadvantages: (1) High source/drain junction leakage—the FET source/drain junctions, as well as the channel region, are formed in a strained Si area resulting in higher junction leakage. (2) The Si/SiGe system MOSFET process is not compatible with mainstream CMOS fabrication techniques requiring specially prepared substrates using molecular beam epitaxy. (3) The Si/SiGe system MOSFET process is costly with low production rate.
In addition to the above mentioned drawbacks with strained Si/relaxed SiGe/bulk wafer structures, prior art structures including strained Si formed on a SiGe-on-insulator (SGOI) template (also referred to herein as a strained Si/SGOI structure) exhibit the following unique problems:    (A) Loss of trench isolation oxide during a multiple gate oxide thickness process (which requires an oxide wet etch selectively with the resist mask, adding trench isolation height). A wider range of trench isolation height requires more etching of the polySi gate resulting in potential gate oxide punchthrough.    (B) A trench isolation divot forms at the strained Si/trench isolation interface. This can create a short circuit between the strained Si islands due to a gate polySi stringer.    (C) A chemical mechanical polishing (CMP) uniformity restriction is imposed or a narrow process window is obtained.    (D) A narrow polySi gate over etching window.    (E) A limitation of thermal budget during pad oxide growth.    (F) Strained Si sidewall exposure and Si loss.
In view of the drawbacks mentioned with the prior art, there is a need for providing a new and improved method of fabricating a strained Si/SGOI structure that overcomes the aforementioned issues recited under items (A)–(F).