1. Field of the Invention
The present invention relates to a semiconductor structure and fabrication of the same. More particularly, the present invention relates to a semiconductor structure having a doped strained layer as a source/drain and a method for fabricating the same.
2. Description of the Related Art
Metal-oxide-semiconductor (MOS) transistors are essential to VLSI and ULSI circuits, and are widely used in microprocessors, semiconductor memory devices and power devices, etc., as basic constituent units. In some nanometer processes, the speed of a MOS transistor is increased by forming an opening in the substrate beside the gate structure and then filling the opening with a doped strained material as a source/drain (S/D) region to increase the carrier mobility of the S/D region.
FIGS. 1A-1B illustrate a process flow of fabricating a prior-art MOS transistor in a cross-sectional view. Referring to FIG. 1A, a substrate 100 with a well 101 therein is provided, and then a gate structure 102 including gate dielectric 104 and a gate 106 is formed on the well 101, A spacer 108 is formed on the sidewall of the gate structure 102, and then etching is conducted with the gate structure 102 and the spacer 108 as a mask to remove a portion of the exposed substrate 100 and form an opening 110.
Referring to FIG. 1B, a doped strained layer 112 is formed in the opening 110 to serve as an S/D region, wherein a portion 113 of the doped strained layer 112 is above the surface of the substrate 100. A (self-aligned silicide) salicide layer 114 is then formed on the gate structure 102 and the doped strained layer 112.
Because the top surface of the doped strained layer 112 is higher than that of the substrate 100, the stress caused by the salicide layer 114 is decreased. When the MOS transistor is PMOS, for example, to increase the compressive stress in the strained layer 112, a SiGe layer with a Ge-content higher than 20% is formed as the strained layer 112, or the thickness of the same is increased by increasing the depth of the opening 110.
However, the thickness of a strained SiGe layer decreases with increase in the Ge-content thereof. Moreover, when the Ge-content is higher, the cell parameter of the SiGe layer is larger making the difference between the cell parameter of the SiGe layer and that of the substrate larger, so that defects easily occur at the interface of the SiGe layer and the substrate lowering the device performance. Furthermore, in a subsequent salicide process, the Ge-atoms will enter the metal silicide layer degrading its quality.