Semiconductor memory devices (hereinafter referred to as "memories") typically store information in memory cells. The capacity (number of memory cells) of memories increases year by year, resulting in memories having many millions of cells. Such large capacity memories has made it difficult to produce a single memory that is completely free from defective memory cells. To overcome this problem, redundancy memory cells are provided so that defective memory cells can be replaced. In this way, when memories are produced in large numbers, the number of functional devices within a production group is increased ("yield" is improved).
Within a memory device, memory cells are usually arranged into an array having rows and columns. Memory cells can then be activated on a row basis by word lines, and then accessed by the bit lines. One major technique for replacing defective memory cells is to provide one or more additional rows of memory cells that function as redundancy cells. In this arrangement, when a row has a defective memory cell, instead of activating the word line coupled to the defective cell, the word line coupled to a redundant cell will be activated. As a result, a row of redundancy memory cells is accessed instead of the row having the defective memory cell.
A memory is typically accessed by way of one or more input/outputs (I/Os). For example, memory cells within a "volatile" type memory can be read from or written to by way of I/Os, and memory cells within "non-volatile" type memory can be programmed, read from, and sometimes erased by way of I/Os. In the past it has been common to design memories with 4 to 16 I/Os. In recent years this number has increased up to 32 to 64. In addition, some memory-incorporated gate arrays and "systems-on-chip" can have as many as 256 I/Os.
Such an increase in the number of I/Os has also increased the percentage of defective cells in the column direction. In the column direction, there are many column-specific circuits, such as memory cells, a column selection circuit, sense amplifiers and data amplifiers. Accordingly, conventional redundancy circuit approaches that provide redundant memory cells in the row direction do not adequately address defects encountered in the column direction.
FIG. 17, which presents a first conventional device, is a diagram showing a configuration of a main portion of a memory circuit disclosed in Japanese Patent Application, JP-A-8-335399 filed on Jun. 7, 1995, and laid open to the public on Dec. 12, 1996.
The memory circuit of FIG. 17 is configured so that memory cell arrays M11 to M35 are connected to word lines WL1 to WL3 and bit lines BL1 to BL5. Each bit line (BL1 to BL5) is connected to a plurality of outside bit lines OBL1 to OBL4 through row selection circuits (selectors) SEL1 to SEL4.
The selectors SEL1 to SEL4 control the way in which bit lines BL1 to BL5 are connected to outside bit lines OBL1 to OBL4. In particular, the selectors (SEL1 to SEL4) are configured to prevent any bit line having defective cells from being connected to an outside bit line (OBL1-OBL4). In this way, defective cells in a column direction can be bypassed.
The switching operation of the selectors (SEL1-SEL4) is controlled by control memory cells C11 to C14. Each control memory cell (C11 to C14) stores switching information for a particular selector (SEL1-SEL4). The use of control memory cells can be more cost effective than other approaches. For example, other conventional column redundancy approaches may use fusible links (fuses) to disable (or otherwise avoid) a column of defective cells and enable a column of redundancy cells. The fuses are usually programmed for such a replacement operation by opening (or "blowing") selected fuses with a laser. This can be a time consuming operation, require expensive equipment, and consume additional device area, as fuses are typically relatively large structures.
Accordingly, by employing such control memory cells, expensive laser devices for disconnecting fuses can be dispensed with. However, the above configuration requires that the switching information be stored in the control memory cells C11 to C14 on a bit-by-bit fashion via a single data line. Such an approach can be problematic in that it can require considerable time to complete the initial setting of the switching information values.
Another conventional approach involves utilizing a shift register in place of the control memory cells of the first conventional device. A shift register is a circuit having a series of storage units. Data bits can be shifted from one storage unit to the next, until all the storage units store data. Switching information can then be set in synchronism with a clock, with data shifting to the next storage unit on a given clock cycle. However, this technique also imposes the problem that the time required to set the values increases in proportion to increases in the number of I/Os.
To shorten such switching time, a second conventional device shown in FIG. 18 is disclosed in Japanese Patent Application JP-A-7-122096. FIG. 18 is a diagram showing a configuration of a main portion of a semiconductor memory having a redundancy cell array.
In FIG. 18, the semiconductor memory has many memory cell arrays NS0 to NS5, and so on. Each array has a corresponding I/O node 1/O0 to 1/O4, and so on. Each group of I/O lines I/O0 to I/O4 is connected to a corresponding group of switches SW0 to SW4. Each switch connects an I/O line to only one I/O node selected in response to a supplied control signal.
In the second conventional device, it is assumed that array NS3 is defective, and so must be bypassed. As shown in FIG. 18, all the switches on the left side of a defective array NS3, as viewed in FIG. 18, are set to be connected to arrays on the left side of their I/O connection sections. At the same time, all the switches on the right side of the defective array NS3 are set to be connected to arrays on the right side of their I/O connection sections.
Fuses can be used to set the switching directions for the arrangement of FIG. 18. The number of fuses is equal to the number of I/O lines plus one, and are connected in series with one another. One end of each fuse is connected to the power supply and the other to the ground. Further, nodes between the fuses are connected to the switches, providing switch control signals, respectively. By disconnecting a fuse during inspection, the nodes toward the power supply with respect to the disconnected fuse are set to "1," and the nodes toward the ground to "0" so that the switching directions of the switches can be set in such a fixed manner. With this operation, switching speed can be improved by avoiding delays introduced by the propagation of control signals used for replacing a defective cell array with a redundancy cell array.
The first conventional device shown in FIG. 17 determines the switching directions by giving the switching information to the control memory cells. A drawback to such an approach is that an increase in the number of outside bit lines increases the amount of time required to set the switching information in the control memory cells.
The second conventional device shown in FIG. 18, a defective cell array is avoided by employing a number of switches, and setting the switching direction of the switches to prevent a defective memory cell from being coupled to an I/O node. A drawback to the second conventional device is that the switching direction is established by fuses. Consequently, an increase in the number of input/outputs increases the number of fuses that must be employed. Since the fuses must be physically disconnected using laser devices or the like, the fuse circuits cannot be reduced in size the same manner as other circuit devices (such as transistors). Hence, additional fuses can result in additional device ("chip") area. In addition, a larger-scale memory requires a larger number of memory cells to be connected to a single bit line, and this increases the incidence of defective cell arrays. The specification describing the second conventional device discloses no solution to addressing the problem arising when a plurality of defective arrays are present.