Integrated circuits (ICs), such as microprocessors, continue to increase circuit densities to support higher levels of performance and functionality. The growth in transistor density has resulted in transistors having shorter gate lengths while power supply voltages have not been scaled as much. The increase in performance may include an increase in clock speeds and accordingly an increase in the power required to operate the ICs. Increases in speed and power and decreases in gate size and operating voltage result in increased currents. Leakage power is becoming an increasing ratio of the total power, and ways to lessen its impact are needed. One solution is to lower or shut down the supply voltage when it is not needed, thus saving power. For example, in a multi-core platform individual cores may be shutdown when not needed (e.g., when in a sleep mode).
FIG. 1 illustrates an example prior art schematic of a power gating circuit for controlling power to a core logic circuit 100. The gating circuit includes a power gate transistor 110 (e.g., PMOS) placed between a voltage source (Vcc) 120 and the core logic circuit 100. A ‘sleep’ signal is received at an input 130 and is provided to a gate of the power gate transistor 110 to control the operation of the power gate transistor 110 and application of the Vcc 120 to the core 100. The power gate transistor 110 provides a virtual supply voltage (Vccv) 140 to the core 100. During an ON-state the Vccv 140 supplied to the core 100 may be approximately the Vcc 120 and during an OFF-state the Vccv 140 supplied to the core 100 may be set by the final steady state of the leakage between the power gate transistor 110 and the core 100.
Utilizing the power gate transistor 110 to control the Vccv 140 provided to the core 100 during a sleep mode may not be optimum. For example, during a sleep mode the power gate transistor 110 may supply such a low voltage that states in the core 100 are wiped out. Accordingly, the states may need to be saved in some external registers that may require a special architectural design and complex circuitry. Moreover, it may take a significant amount of dynamic power and many clock cycles to restart the core 100. After the core 100 is restarted the states may need to be reloaded to the core 100 from the external registers before normal operations may begin. The sequence for restarting the core 100 may become more complex in multi-core designs where one core can be slept while other cores are in normal operation.
Furthermore, the power specification is imprecise as the Vccv 140 is floating (the level is set by some balance reached between the leakage through the power gating device and the core leakage) when the IC is in sleep mode.