Biological information processing systems are compact, energy efficient, and excel at solving difficult problems in sensory perception and complex motor control in a massively parallel fashion using slow, imprecise hardware. Thus, it is not surprising that computer scientists and engineers in their quest to endow present-day computers with perceptual processing capabilities are studying the organization and physics of computation in the nervous system.
In recent years, researchers have used knowledge about the physics of information processing in the nervous system, and about its organization, to engineer synthetic sensory processing systems (see, e.g., U.S. Pat. Nos. 4,962,342; 4,786,818; and 4,771,196). Power dissipation, area efficiency, and interconnects are the main engineering constraints in these types of systems. Precision in computation and speed are of secondary importance.
Analog very large scale integration (VLSI) is a novel and promising approach to engineering large-scale synthetic sensory computing systems that feature distributed processing and local connectivity with robust performance in the presence of hardware faults. In such systems, the physical laws that govern the cooperative behavior of many simple processing elements are exploited to process information.
At the analog VLSI system level, global properties such as energy are used to solve problems. Koch's "smart vision chips" employ resistive networks that converge to a state of minimum power dissipation to solve ill-posed problems in computer vision (C. Koch, "Seeing Chips: Analog VLSI Circuits for Computer Vision", Neural Computation, vol. 1, no. 2, pp. 184-200, 1989). Sivilotti's implementation of Hopfield's associative memory (M. A. Sivilotti, M. R. Emerling, and C. A. Mead, "VLSI Architectures for Implementation of Neural Networks", Neural Networks for ComputingJ. S. Denker ed., AIP Conference Proceedings 151, pp. 408-413, 986) uses the stable states of a dynamical system to represent information; associative recall occurs as the system converges to its local energy minima.
The above approach to Analog VLSI implementation of biological information processing systems has been adopted by C. A. Mead and his coworkers at Caltech. Their design methodology is based on the transconductance amplifier and utilizes differential voltage signal representations (C. A. Mead, Analog VLSI and Neural Systems, Reading, Mass., Addison-Wesley, 1989).
The approach of the invention described and claimed herein is more minimalistic than the just described processes, emphasizing design at the transistor level. High functionality and integration density are achieved by using unidirectional current signals and Current-Mode (CM) subthreshold metal oxide semiconductor (MOS) circuits. The use of complex building blocks, e.g., transconductance amplifiers, and of differential voltage signals is thereby avoided. The necessary ingredients of the CM approach to analog VLSI neural systems design are described below.
Subthreshold complementary MOS (CMOS) technology has long been recognized as the technology of choice for implementing micropower digital and analog LSI circuits. It offers the same advantages for the implementation of synthetic neural systems: high integration density, low power dissipation, and useful parasitic bipolar devices. In addition, it is easily accessible to engineers and scientists through silicon foundry services such as MOSIS.
Subthreshold currents are comparable to ionic currents in cell membranes; they range from a few pico-amps to a few micro-amps. There is also a direct analogy between the device physics of voltage-gated ionic channels in excitable membranes and that of the MOS transistor in subthreshold region. Their operation is based on Boltzmann's Law and thus both exhibit the same exponential current dependence on voltage; this dependence is sometimes steeper in ionic channels because of correlated charge control. Thus, a one to one mapping of ensembles of gated channels to a single MOS transistor can be made.
For an n-type MOS transistor, the subthreshold current is given by: ##EQU1## where V.sub.gs is the gate-to-source potential, V.sub.ds is the drain-to-source potential, V.sub.bs is the substrate (or well)-to-source potential (body effect), I.sub.o is the zero-bias current for the given device, V.sub.T =kT/q, is the thermal voltage (26 mV at room temperature), V.sub.o is the Early voltage (which is proportional to the channel length), and .kappa. measures the effectiveness of the gate potential in controlling the channel current. All potentials are measured with respect to the source potential and are sign reversed for a p-type device. Typical parameters for minimum-size devices (4.mu.m.times.4.mu.m) fabricated in a standard digital 2.mu.m n-well process are: I.sub.o =0.72.times.10.sup.-18 A, .kappa.=0.75 and V.sub.o =15.OV. Thus, the current changes by a factor of 10 for an 80 mV change in V.sub.gs or a 240 mV change in V.sub.bs (up to about 100 nA, which is the limit of the subthreshold region). The above model matches experimental data reasonably well and is adequate for design simulations.
For devices in saturation (that is V.sub.ds .gtoreq.4V.sub.T), neglecting theearly effect and the body effect, EQU I.sub.ds =I.sub.o e.sup..kappa.v.sbsp.gs.sup./V.sub.T. (2)
This simplified equation (eq.), containing only the dependence on V.sub.gs, is sufficient for most circuit designs. On the other hand, eq. (1) shows an explicit V.sub.bs dependence that underlies the role of the substrate as another terminal which can control the drain-source current.
In the saturation region, the MOS transistor is a voltage-controlled current source with output conductance: ##EQU2## The transconductance, g.sub.m, of the device is given by: ##EQU3##
High functionality is obtained by using the MOS transistor itself to perform as many functions as possible in the same circuit:
In the common-source mode, it is an inverting amplifier with high voltage gain: A.sub.v =g.sub.m /g.sub.dsat (FIG. 1a). For our process A.sub.v =.kappa.V.sub.o /V.sub.T .apprxeq.430.
In the common-drain mode, it is a voltage follower with low output resistance: 1/g.sub.m (FIG. 1b).
In the common-gate mode, it is a current buffer with low output conductance: g.sub.dsat (FIG. 1c).
In silicon integrated circuits, non-uniform substrate doping produces random variations in the drain current, while the nonzero drain conductance results in systematic variations.
Traditional analog integrated circuits depend on good matching between components. Therefore, large devices operating above threshold are used to reduce mismatch to very low levels. In contrast, to achieve VLSI densities, transistors that have small geometries, typically (4 .mu.m.times.4 .mu.m), must be employed. This together with their operation in the subthreshold region, makes the drain current strongly dependent on variations of fabrication process parameters, in particular I.sub.o. Characterization of the fabrication process and the matching properties of the basic devices is thus of paramount importance because it provides the necessary information for designing working systems.
Large, dense transistor arrays in the subthreshold region of operation have now been characterized. More than 150,000 transistors have been tested using an automated data acquisition system. Measurements, established three factors affecting matching: edge effects, striation effects, and random variations.
The edge effect manifests itself as a dependence of the transistor current on its position with respect to the surrounding structures. N-type transistors surrounded by other n-type transistors have a larger drain current than identically designed and biased transistors on the edges of the arrays. The opposite is true for p-type transistors. Variations in transistor currents caused by the edge effect typically range from 5% to 15% for n-type transistors and from 20% to 50% for p-type transistors.
The striation effect exhibits itself as a sinusoidal spatial variation in transistor current. The amplitude is about 30% of the average current and the spatial period varies slowly from 100 .mu.m to 200 .mu.m for p-type devices in the p-well process.
The random variation of subthreshold current follows a Gaussian distribution (FIG. 2). FIG. 3 shows the dependence of normalized standard deviation of subthreshold current on transistor size. Each data point represents measurements from approximately 1000 transistors. The standard deviation of the current is proportional to the current and inversely proportional to the length of square devices (i.e., devices whose length and width are the same): ##EQU4## where .sigma..sub.o is the proportionality constant for the given device type, I.sub.ds is the nominal device current, and L is the length of the device (square geometry).
Edge effects and striation effects present significant problems in large-scale analog computational systems, since they cannot be reduced by increasing transistor area. The striation effect is especially damaging, since the orientation of the striations is not known a priori. The edge effect can be canceled by symmetrical placement of transistors.
At the system level, random variations are addressed by distributing computations over a large number of elements. The normalized standard deviation of the currents from matched current sources can be reduced by a factor of .sqroot.N by using N small devices for each current source. Furthermore, N small devices can be positioned in a way that minimizes the edge and striation effects. Finally, this distribution of the signal over many devices permits implementation of parallel computation. Thus, such systems are carefully designed to simultaneously perform parallel distributed processing and reduce matching problems.
At the circuit level, the transistors are biased at a constant I.sub.ds rather than a constant V.sub.gs. This is so because the variability of I.sub.0 is much larger than the variability of .kappa.. Biasing at a constant current and thinking in terms of current-domain signals is the essence of the Current-Mode (CM) approach in circuit design.
There has been a renewed interest in CM circuits (Papers on Current-Mode circuits, B. Gilbert chair, Proceedings ISCAS-89, pp. 1567-1595, May 1989). A CM circuit is one whose input signals and output signals are currents; voltages play only an incidental role. The simplest CM circuit is the current mirror.
At the circuit level, conservation of charge (Kirchoff's Current Law (KCL)); conservation of energy (Kirchoff's Voltage Law (KCL)); and the device physics of active devices can be exploited to implement powerful computational primitives. Current signals may be summed simply by bringing them to the same node. Voltage signals may be summed around a loop.
The Translinear Principle can be used to synthesize a wide variety of circuits to perform both linear and non-linear operations on the current inputs, including products, quotients, and power terms with fixed exponents (see, e.g., B. Gilbert, "A Monolithic 16-Channel Analog Array Normalizer", IEEE Journ. of Solid-State Circuits, vol. SC-19, No. 6, pp. 956-963, 1984). The translinear principle can be stated as follows:
In a closed loop containing an equal number of oppositely connected translinear elements, the product of the current densities in the elements connected in one direction is equal to the corresponding product for elements connected in the opposite direction.
Translinear circuits (see, e.g., U.S. Pat. No. 3,582,689), traditionally built using bipolar transistors, are a computationally powerful subclass of CM circuits. A translinear circuit is defined as one whose operation depends on a linear relationship between transconductance and channel current in the active device. Such a circuit relies on KVL and on the exponential dependence of drain current on the gate voltage in the MOS transistor (Boltzmann's Law). Explicit use of differential voltage signals (not referenced to ground) is avoided. The MOS transistor is a translinear element when operated in the subthreshold region (see eq. (4)); the absence of a base current makes it an ideal one. The current mirror in subthreshold operation is a trivial example of a translinear circuit.
The silicon optical motion detector (A. G. Andreou and K. Strohbehn, "Analog VLSI implementations of the Hassenstein-Reichardt-Poggio models for vision computation," in Proc. 1990 IEEE Symp. Systems, Man and Cybernetics (Los Angeles, Ca.), Nov. 1990.) uses the MOS translinear multiplier/divider in FIG. 4 to compute the correlation I.sub.z between two signals, I.sub.x and I.sub.y. By applying the translinear principle around the loop indicated by the arrows, we find ##EQU5## where I.sub.w normalizes the result.
The above relation can also be derived by summing the voltages around the loop GND-A-B-C-GND (conservation of energy): EQU V.sub.1 +V.sub.2 +V.sub.3 +V.sub.4 =O.
Replacing the gate-source voltages for M.sub.1, M.sub.2, M.sub.3, and M.sub.4 with their respective drain-source currents through eq. (2) and assuming the same .kappa. and I.sub.o for all devices, we obtain ##EQU6## from which eq. (6) readily follows.
Yet another way of looking at the function of the circuit in FIG. 4 is a log-antilog block. Transistor M.sub.1 does the log-ing and M.sub.4 the antilog-ing. The other two transistors serve as voltage level shifters; this is equivalent to normalization in the current domain.
The translinear property of subthreshold MOS transistors is also useful for analyzing the dynamics (temporal response) of large-scale collective computational systems and for simplifying circuit synthesis and analysis. Unlike traditional analog design, optimizing circuits by careful sizing of the devices is not necessary. This is because the transconductance is determined by the current signals and does not depend on the geometry of the devices. Longer channels are used to avoid the Early effect and large devices are employed in a few critical parts of the system to improve accuracy in the computation (current matching).
A current conveyor is an ingenious translinear, hybrid voltage/current three-port device. It is a versatile building block for analog signal processing applications designed to replace the operational amplifier.
Although its original implementation (see U.S. Pat. No. 3,582,689) used five bipolar transistors, the current conveyor can perhaps be most easily explained by considering a single device. A transistor can transfer a current from a high-conductance to a low-conductance node (see FIG. 1c) or a voltage from a high-impedance to a low-impedance node (see FIG. 1b). These two characteristics can be exploited simultaneously (see FIG. 5a) such that the device acts as a voltage follower (node X will follow voltage changes at node Y) and conveys the current at X to the low-conductance node Z. This dual role, obtained in this case using only a single transistor, captures the essence of the current conveyor.
Current conveyors can easily interact with one another as shown in FIG. 5b. Here, node X follows the greatest input voltage V.sub.yi, turning off all other current conveyors. The tail current, I.sub.x, is then entirely conveyed to the output node Z.sub.i identifying the ith input voltage as being the greatest.
The circuits described and claimed herein build on the current conveyor to achieve even higher functionality and integration density while avoiding the use of complex components and differential voltage signals. These circuits are faster, generate less heat, are more reliable, and use less area than prior art devices.