The cost of manufacturing tests for integrated circuits (“ICs”) has been growing significantly in the past decade. Some of the contributing factors include the increasing complexity of the circuits, shrinking line widths, shrinking line separations, and the increased popularity of new packaging technologies (for example, systems-in-a-package (“SIPs”)). These factors have in part resulted in tens of millions of gates being integrated onto a single integrated circuit that supports a wide range of functionality. In addition, stringent quality requirements, newer technology nodes, and narrower time-to-market windows increase the cost and effort needed to test manufactured integrated circuits. The quality of test is often improved by employing advanced fault models (such as transition, path-delay, multiple-detect, bridging, or other such fault models) that are designed to catch additional defects missed by the conventional stuck-at fault model. Unfortunately, these fault models typically require complex test sets that are much bigger in size when compared to conventional stuck-at pattern test sets. The growing circuit size and the desired support for advanced fault models increase the test data volume that is stored inside an external tester (e.g., automated test equipment (“ATE”)) as well as the test application time, which is proportional to the volume of test data shifted into the circuit during testing.
Another factor contributing to the test cost equation is the cost of the ATE equipment itself. The cost of an ATE is generally proportional to the number of pins it can support, its operating frequency, the pin electronics, the memory per pin, and other such factors. As the operating frequency of integrated circuits increase, packages become more complex and the demand for scan memory continues to rise. Thus, the infrastructure cost to support testing increases exponentially, often affecting the bottom line of a product. This has caused many companies to evaluate whether full-bandwidth, at-speed functional testing can be reduced (or replaced) by low-pin-requirement, slower-speed, structural testing. In such cases, the ATE is able to perform structural testing effectively but has been incapable of performing functional testing. Therefore, DFT is typically incorporated into the device such that one can get high fault coverage for structural testing and gain enough confidence about test quality such that functional tests can be reduced.
Several DFT techniques have been proposed to address the issue of rising test costs. Test data compression is one of the foremost techniques that help reduce test cost by decreasing the test data volume and test application time. Compression techniques store compressed patterns in the ATE memory, which are typically decompressed on-chip using some hardware before shifting the decompressed data into scan chains of the circuit-under-test. Similarly, at the output side, the test responses are typically compressed before sending them back to the ATE for determining failures. Among the different compaction schemes that can be used are selective compactors, convolutional compactors, X-compact, and MISRs. See, e.g., Rajski J., et al., “Embedded Deterministic Test,” IEEE Trans. on CAD, vol. 23, pp. 776-792 (2004); Rajski J., et al., “Convolutional Compaction of Test Responses,” Proc. of ITC, pp. 1079-1088 (2003); Koenemann B., “A SmartBIST Variant with Guaranteed Encoding,” Proc. of ATS, pp. 325-330 (2001); and Mitra S., et al., “X-Compact: An Efficient Response Compaction Technique for Test Cost Reuction,” Proc. of ITC, pp. 311-320 (2002). These exemplary schemes are each capable of compressing the test data to a different extent before sending it back to the ATE. The test application time can be reduced through the use of such techniques because the number of scan pins required to transport data to and from scan chains is reduced as a result of the test data compression. However, if the number of non-scan I/Os of a device is very high, then testing typically still requires an expensive ATE to deliver all the data to the functional pins.
Multi-site testing is another technique for reducing test application time. Multi-site testing involves reducing the test cost by improving the throughput of the test equipment. Multi-site testing entails applying test data to multiple dies concurrently, and observing the circuit outputs at the same time. Special test equipment is typically used to support multi-site testing. However, if a device has a large number of pins, it is extremely difficult to perform multi-site testing without requiring very expensive functional testers.
As discussed more fully below, reduced pin count testing (“RPCT”) is another technique that can be used to reduce the cost of testing. RPCT generally involves reducing the number of test pins used when testing on an ATE. For example, by using RPCT, devices can be tested using structural DFT testers that cost about $200/pin compared to high-end functional testers that cost almost $8-10K/pin. Because RPCT can create significant cost savings, improved architectures that enable high quality testing with reduced numbers of test pins are desired.