Contemporary semiconductor memory devices commonly employ trench transistors in both memory cell regions and peripheral regions of a device. In a Buried Channel Array Transistor (BCAT) device, for example, a transistor gate is buried in a trench formed in a semiconductor substrate. The buried gate operates to extend the channel length of the resulting transistor structure, resulting in increased integration and greater reliability. Such trench transistors are disclosed, for example, in United States Patent Application Publication No. 2005/0127437, the contents of which are incorporated by reference in their entirety
In a conventional trench transistor, a trench is formed in the substrate and the inner walls and base of the trench are coated with an insulative oxide film. A polycrystalline metal fill layer is then provided to fill the trench, and upper regions of the substrate at sides of the trench are doped with impurities to form source and drain regions for the transistor. A relatively thin silicon nitride layer is formed over the resulting structure as an etch stop layer, and an interlayer insulator silicon oxide layer is formed over the etch stop layer. Direct contact holes are then formed in the silicon oxide layer, to expose the source and/or drain regions at sides of the trench gate, using the underlying etch stop layer as an etch stop. Optionally, the source/drain regions can be formed following formation of the contact holes. The side walls and bottoms of the contact holes are then lined with a barrier metal to prevent diffusion during subsequent processes, and the contact holes thus lined are filled with a conductive metal, for example tungsten W, to form the direct contacts.
The resulting direct contacts suffer from a number of limitations that become more problematic as devices are further integrated and operate at higher speeds and at lower voltage levels. For example, the resulting junction between the tungsten contact and the underlying source/drain region formed in the substrate creates a relatively narrow p-n junction, and is therefore highly resistive. In addition, with increased integration, the distance between the gate and source/drain region is reduced, and therefore, leakage current between the gate and source/drain region can be increased. Also, with increased integration, photolithographic alignment is more critical. Under these conditions, the resulting transistor is more likely to fail, or otherwise will operate with reduced reliability. Also, fabrication of such devices can result in reduced yield, and therefore fabrication costs can be increased.