1. Field
The present invention relates to a semiconductor device, and more particularly to a discharging order control circuit for use in a destructive-read and nonvolatile memory such as a ferroelectric memory.
2. Description of the Related Art
As a kind of nonvolatile semiconductor memories, there is known a ferroelectric memory (FeRAM) (for example, see JP-A 2003-196974 (KOKAI)). The FeRAM has an advantage of reading/writing operations at higher speeds over a flash memory. However, the FeRAM may have the following disadvantage. The FeRAM has a destructive reading operation in which an electric field of a direction from a plate line to a bit line is applied to between the both electrodes of a ferroelectric capacitor in a memory cell to thereby read data. According to this operation, a malfunction may occur in the core circuits of the memory cell during the reading operation, or a wrong data writing operation may occur in the memory cell due to the sudden lowering of a power supply voltage. Therefore, in the FeRAM, it is necessary to prevent the occurrence of the malfunction in the core circuits and thus prevent the writing of wrong data.
The possibility of the wrong data writing occurring is highest in the time when the inner power supply voltage of a chip is not stable, that is, the time when the FeRAM is turned on and the time when it is turned off. In view of this, in the time when turning on the FeRAM, various internal power supplies are sequentially turned on in good order. In this case, it is most important that the internal power supply to be supplied to an array part of the FeRAM should be activated after the internal power supplies to be supplied to peripheral circuits are supplied and the peripheral circuits are held in their normal operating conditions. On the other hand, when turning off the FeRAM, the respective internal power supplies are forcedly discharged sequentially. In this case, it is most important that, after the voltage to be supplied to the array part is deactivated to thereby eliminate the possibility of the malfunction occurring in cell array, the internal power supply voltages to be supplied to the peripheral circuits should be deactivated.