The photolithography process is one of the most important technologies in integrated circuit fabrication, because the device structures or the patterns of each film in the integrated circuit are all determined by the photolithography process. Since the circuit layout is composed of multiple layers, it is necessary to perform an alignment step in each exposure process to prevent improper pattern transfer. Therefore, the alignment marks are provided on the mask for alignment in each of the photolithography processes. In addition, in order to further detect the overlay accuracy between two adjacent layers, the overlay marks are also provided on the mask for measuring an overlay error between two layers.
FIG. 1 is a conventional alignment mark 100, which includes a Y-direction mark 110 and X-direction marks 120 and 130. The Y-direction mark 110 includes a plurality of rectangular regions, being arranged in Y direction and parallel with each other, for Y-direction alignment, are disposed on two opposite sides of the Y-direction mark 110 respectively in X direction, and each of the X-direction marks 120 and 130 includes a plurality of rectangular regions, being arranged in X direction and parallel with each other, for X-direction alignment. Typically, for an exposure machine, before executing the calibration procedure, a photolithography process is performed on a wafer via a mask having the alignment mark 100, and an etching process is then performed to form an exposed pattern corresponding to the alignment mark 100 on the wafer. Next, in the subsequent exposure process, the exposure machine can execute the calibration procedure by utilizing the pattern formed on the wafer to make necessary adjustment.
FIG. 2 illustrates a conventional overlay mark 200 for determining a relative position between two or more layers in a semiconductor structure, which includes first mark patterns 210a, 210b, 210c, 210d associated with the first layer and second mark patterns 220a, 220b, 220c, 220d associated with the second layer. The first mark patterns 210a and 210c are used together with the second mark patterns 220a and 220c for measuring the overlay error in X-direction, and the first mark patterns 210b and 210d are used together with the second mark patterns 220b and 220d for measuring the overlay error in Y-direction. The first exposed patterns corresponding to the first mark patterns 210a, 210b, 210c, and 210d are formed on the wafer during the first-layer process, and then the second mark patterns 220a, 220b, 220c, and 220d are transferred into the photoresist layer by the photolithography process of the second-layer process to form the second exposed patterns. Next, a relative position between the first and the second patterns is measured and the overlay error between two adjacent layers is calculated to determine whether an offset is necessary for these two adjacent layers.
Generally, a plurality of alignment marks and a plurality of overlay marks are simultaneously present on different positions of the mask, and occupy a space of the mask respectively. Besides, because the mark used for alignment is different from the mark used for overlay error measurement, the overlay error between two adjacent layers is likely too large to meet the process requirements, which may reduce the accuracy, increase the failure rate, and further raise the production cost.