This invention pertains to the field of simulating the operation of integrated circuits, and has application to the interconnects of deep sub-micron devices.
In the modeling and simulation of integrated circuits, all of the various parts need to be considered. Some of these circuit elements can be neglected in some circumstances, but begin to introduce non-negligible effects in other circumstances. Similarly, models and techniques that are effective in one regime begin to become unreliable when pushed into other regimes. In particular, one set of integrated circuit elements is the on-chip interconnect elements. Although there are a number of prior art optimization methods, the accuracy of these methods has become increasingly inaccurate as technology has extended into Ultra-Deep Sub-Micron (UDSM) processing.
In deep sub-micron semiconductor process technologies, interconnect delays can easily dominate gate propagation delays as major contributors to the total delay through signal paths of an integrated circuit device. Accordingly, it is important that interconnect delays be thoroughly and accurately accounted for in computer simulations of integrated circuits designs. Otherwise, unexpected timing problems in the resulting silicon may require time consuming and costly redesigns with little or no guidance on how to correct the problems. Various aspects of ultra-deep submicron technology are presented in “Full Chip Verification of UDSM Designs”, R. Saleh et al., Proceedings of 1998 IEEE/ACM International Conference on Computer Aided Design, pp. 453-460, which is hereby incorporated by reference.
In addition to delay, crosstalk is an issue in the design of interconnect structures for circuitry. As circuitry is increasingly miniaturized, neighboring interconnects are brought into closer proximity. As a result, undesired signal coupling among interconnects is increased.
A highly specialized field, commonly referred to as “electronic design automation” (EDA), has evolved to handle the demanding and complicated task of designing semiconductor chips. In EDA, computers are extensively used to automate the design processes. Computers are ideally suited to performing tasks associated with the design process because computers can be programmed to reduce or decompose large complicated circuits into a multiple of much simpler functions. Thereupon, the computers can be programmed to iteratively solve these much simpler functions. Largely, the design process has become such that integrated circuit (IC) chips cannot be designed without the help of computer-aided design (CAD) systems.
Generally, interconnect characterization consists of T/P (Test Pattern) draw, wafer fabrication, measurement, and extraction and optimization with simulation. FIG. 1 is a schematic diagram of a conventional interconnect characterization flow. Starting from a wafer having a copy of the circuit to be simulated, a set of measurements is made. With a set of input parameters, a simulation can be ran using the field solver and then compared with the measurements from the wafer to calibrate the simulation. From the simulation and measurement results, a layout parasitic extraction (LPE) is then performed, followed by the extraction of the interconnect process parameters. Aspects of parasitic extraction are described further in U.S. patent application Ser. No. 09/969,186, filed Sep. 27, 2001, which is hereby incorporated by reference.
Some features of the extraction/optimization of interconnect process parameters are shown with respect to FIG. 2. FIG. 2a shows a portion of a structure having a series of metal interconnects from metal layer M1, 211a, 211b, 211c, running into the page below a metal layer M2 running along the page. The layer M1 is separated from the substrate 230 (assumed to be a conductor) by the field oxide 240, and from the M2 layer by inter-layer dielectric ILD 220, which is also between the different lines, 211a-c, of M1. Each metal line of M1 is taken to have a width W with a process variation of ΔW. As shown FIG. 2b, the process of determining existing inter-layer dielectric ILD 220 thickness consists of capacitance simulations, electrical measurements and mathematical interpolations. For example, the density of metal layer M1 is extracted from the layout, and the capacitance or ILD thickness is then determined using mathematical interpolation. More details of this approach can be found in “A Statistical Metrology Framework for Characterizing ILD Thickness Variation in CMP Process”, Eric Choong-Yin Chang, Ph.D. Thesis, MIT, February 1996, which is hereby incorporated by reference.
Other prior art work, described in “3-sigma Worst-Case Calculation of Delay and Crosswalk for Critical Net”, N. Chang, 1998 ACM/IEEE International workshop on Timing Issues in the Specification and Synthesis of Digital Systems and in U.S. Pat. No. 6,018,623, both of which are hereby incorporated by reference, suggests generating randomized but correlated R and C values using the Monte-Carlo simulation instead of measurement. To determine the interconnect parameters, a typical interconnect simulation structure requires information on interlayer dielectrics, metal thickness, width and spacing, and dielectric thickness, as shown for three metallization layers in FIGS. 3a and 3b. FIG. 3a is a perspective view of a three layer interconnect with the dielectrics not shown. The interconnect model includes a metal array of three interconnects 312a-c above an orthogonal array of interconnects 311a-c and below an orthogonal array of interconnects 313a-c. FIG. 3b is a side sectional view of the interconnect structure of FIG. 3a, taken along lines 3b—3b. 
The idealized structure of FIG. 3b contains a metal array in a metal layer, such as 312a-c, on top of an orthogonal array 311 and below another orthogonal metal array 313, with the area in between these filled with inter-layer dielectric. Lines 312a and 312c are taken at ground and 312b is taken to be at a higher voltage. By convention, metal array 311 is referred to as metal 1 or M1, metal array 312a-c is referred to as metal 2 or M2, and metal array 313 is referred to as metal 3 or M3, although, strictly speaking, these layers may not be metal but another conductive layer. Individual runs of metal connecting coupled gates are referred to as interconnects. The metal layers are separated and supported by interlayer dielectric material 300 having a dielectric constant ε. Other material and geometry values include the coupling capacitance per unit length, Ci, between adjacent interconnects of the metal array 312; capacitance per unit length, Cgu, between interacting portions of the metal array 312 and the orthogonal array 313 above; and capacitance per unit length, Cgd, between the metal array 312 and the orthogonal array 311. Still other material and geometry values include the height h1 between the interlayer dielectric material 300 between the metal array 312 and the orthogonal bottom metal array 311 below it, and the height h2 of the interlayer dielectric 300 between the metal array 312 and the orthogonal top metal array 313 above it. Other material and geometry values for M2 include its thickness t, its width W, its spacing S between adjacent cords 312a and 312b, its resistivity ρ, and resistance per unit length R as determined from t, W, and ρ. Although not shown, corresponding material and geometry values may be defined for other metallization layers.
When using a EDA tools to simulate the operation of the circuit, an interconnect model file (IMF) is generated. For example, an IMF may include an R, C nominal table and an R, C sensitivity table for each type of interconnect arrangement in an integrated circuit design. The R, C nominal table provides nominal resistance and capacitance parameters for specified range widths and spacings, and the R, C sensitivity table provides sensitivity data for R, C parameters with respect to changes in material and geometry values. Data for the IMF is generated from data provided in an interconnect technology file (ITF) based on these various parameters. More details are described in U.S. Pat. No. 6,219,631, which is hereby incorporated by reference, and other aspects related interconnects are given in U.S. Pat. No. 6,189,131, which is also hereby incorporated by reference
Another variation, as described in “Circuit Sensitivity to Interconnect Variation,” by Zhihao Lin, IEEE Transactions on Semiconductor Manufacturing, Vol. 11, No. 4, November 1998, also hereby incorporated by reference, which does not use the top plate (M3 in FIG. 3). This variation is shown in FIG. 3b, which is labeled similarly to FIG. 3a. In this case, the layer M1 is take as the metal layer 411 that is placed above the silicon layer 430, from which it is separated by the interlayer dielectric (ILD) 420.
As feature sizes decrease, these prior art methods become increasingly inaccurate and improvements are needed.