1. Field of the Invention
This invention relates to the field of integrated circuits. More particularly, this invention relates to integrated circuits formed of a stack of wafer layers interconnected by a plurality of through silicon vias.
2. Description of the Prior Art
FIGS. 1, 2 and 3 of the accompanying drawings schematically illustrate one example of an integrated circuit formed of a plurality of wafer layers interconnected with through silicon vias (TSVs). FIG. 1 illustrates an integrated circuit 2 comprising four wafer layers 4, 6, 8, 10 with through silicon vias 12 providing electrical connections between the wafer layers 4, 6, 8, 10. This type of technology allows more compact devices to be produced. Furthermore, the speed of communication between the wafer layers 4, 6, 8, 10 is higher than is typically achieved between separate integrated circuits each formed of one wafer layer and interconnected with a signal bus.
FIG. 2 illustrates a through silicon via used to provide an electrical connection between two wafer layers 14, 16. Each wafer layer 14, 16 comprises a silicon substrate with multilayer circuitry formed thereon using conventional lithographic techniques. In order to provide an electrical connection between wafer layers 14, 16, a through silicon via 12 is provided by etching the silicon substrate of the wafer layer 16 to produce a hole therein. This hole is then filled with a conductive material, such as copper (or tungsten cored copper) extending through the silicon substrate, connecting with one or more portions within the multilayer circuitry and protruding from the silicon substrate. The adjacent wafer layer 14 has a contact pad 18 formed on the upper surface of the multilayer circuitry and this makes mechanical contact with the conductive material protruding from the through silicon via 12. Adhesive bonding is used to hold the wafer layers 14, 16 together. It will be appreciated that FIG. 2 illustrates a single electrical connection and that in reality a large number of such connections will typically be provided between wafer layers to pass the desired electrical signals between the wafer layers 14, 16. There are other ways of forming a through silicon via, such as drilling holes which are then filled at different points in the manufacturing process. These different ways of forming the through silicon vias do not materially effect the invention.
FIG. 3 schematically illustrates a wafer layer 20 having an array of through silicon vias 12 formed upon its surface. These through silicon vias are illustrated as having a regular layout, but it will be appreciated that this is not a requirement and the through silicon vias 12 could be more randomly located across the surface of the wafer layer 20. The through silicon vias 12 are typically physically large structures (e.g. approximately 1 micrometre in diameter) when compared to the geometry size of the circuit elements within the multilayer circuitry of the wafer layers (approximately a few tens of □ anometers). It is known that the mechanical engagement of the through silicon vias 12 between wafer layers results in mechanical strain within the wafer layers. This mechanical strain can alter the electrical properties of the circuitry, e.g. speed up or slow down the circuitry, change threshold voltages etc. These changes in the electrical properties can result in incorrect operation of the circuitry if it is located too close to a through silicon via 12 which is subject to a high level of mechanical strain. For this reason, it is known to define keep out areas (KOAs) 22 surrounding each of the through silicon vias and form the wafer layers such that no circuitry which may be perturbed by the strain-induced electrical changes is formed within the keep out areas 22.
While this approach may avoid incorrect operation due to strain induced changes as a result of the use of through silicon vias, there are a number of disadvantages and problems associated with the keep out areas 22. As the number of through silicon vias 12 it is desired to provide increases, then the proportion of the area of the wafer layer 20 which is occupied by the keep out areas 22 increases. When the number of connections is relatively small, e.g. connecting between a wafer layer carrying processing logic and a wafer layer carrying only memory, then the overhead of the keep out areas 22 may be accommodated. However, in circumstances where a higher number of electrical connections provided by through silicon vias 12 is desired, such as connecting between two wafer layers each carrying active processing logic (e.g. two wafer layers carrying different portions of a microprocessor), then the area of the keep out areas may be so large a proportion of the area of the wafer layers 20 that there is insufficient space to accommodate the processing logic required on the wafer layers.