1. Field of the Invention
The present invention relates generally to integrated circuit manufacture, and more particularly, to a method of manufacture and a structure in which a shallow junction CMOS device is formed in a semiconductor substrate.
2. Description of the Related Art
The structure and the various components, or features, of metal oxide semiconductor (MOS) devices are generally well known. A MOS transistor typically includes a substrate material onto which a gate dielectric and a patterned gate conductor are formed. The gate conductor serves to self-align impurities forwarded into the substrate on opposite sides of the gate conductor. The impurities placed into the substrate define a junction region, also known as source/drain regions. The gate conductor is patterned from a layer of polysilicon using various lithography techniques.
A typical n-channel MOS transistor employs n-type junctions placed into a p-type substrate. Conversely, a typical p-channel MOS transistor comprises p-type junctions placed into an n-type substrate. The substrate comprises an entire monolithic silicon wafer, of which, a portion of the substrate known as a "well" exists. The well is doped opposite the substrate so that it can accommodate junctions of an impurity type opposite the junction in the non-well areas. Accordingly, wells are often employed when both n-type and p-channel transistors (e.g., Complementary MOS, "CMOS") are needed.
A common trend in modern integrated circuit manufacture is to produce transistors having feature sizes as small as possible. To achieve a high density integrated circuit, features such as the gate conductors, source/drain junctions, and interconnects to the junctions must be made as small as possible. Many modern day processes employ features which have less than 0.20 microns critical dimensions. As feature sizes decrease, the size of the resulting transistors as well as the interconnects between transistors also decrease. Smaller transistor size allows more transistors to be placed on a single monolithic substrate, thereby allowing relatively large circuit systems to be incorporated on a single and relatively small die area. Further, smaller transistors typically have lower turn-on threshold voltages, faster switching speeds and consume less power in their operation. These features in combination allow for higher speed integrated circuits to be constructed that have greater processing capabilities and that produce lesser heat.
The benefits of high density circuits can only be realized if advanced processing techniques are used. For example, semiconductor process engineers and researchers often study the benefits of electron beam lithography and x-ray lithography to achieve the higher resolutions needed for submicron features. To some extent, wet etch has given way to a more advanced anisotropic (dry etch) technique. Further, suicides and polycides have replaced higher resistivity contact structures mostly due to the lower resistivity needed when a smaller contact area is encountered.
Many other techniques are often used to achieve a higher density circuit. However, these techniques must contend with problems resulting from higher density itself. Even the most advanced processing techniques cannot, in all instances, offset the problems associated with small features or features arranged extremely close to one another. For example, as the channel length decreases, short channel effects ("SCE") generally occur. SCE cause threshold voltage skews at the channel edges as well as excessive subthreshold currents (e.g., punch through and drain-induced barrier lowering). Related to SCE is the problem of hot carrier injection ("HCI"). As the channel shortens and the supply voltage remains constant, the electric field across the drain-to-channel junction becomes excessive. Excessive electric fields give rise to so called hot carriers and the injection of these carriers into the gate oxide which resides between the substrate (or well) and the overlying gate conductor. Injection of hot carriers should be avoided since these carriers can become trapped and skew the turn-on threshold voltage of the ensuing transistor. In view of these considerations, certain scaling limits are being realized. Unfortunately, however, there continues to exist a need to further reduce device scaling.
An integrated circuit is, by definition, a number of electrically interconnected circuit elements defined on the same substrate or "chip". Some of the interconnections are done in the silicon substrate itself, but most are done by means of thin conductive strips running across the top surface of the substrate. Each strip is often connected within a contact area to underlying semiconductor materials (often referred to as "junctions"). Contact to junctions must be of low resistivity. For example, the contact junctions should have resistivity that is as low as a few micro ohms per square centimeter of contact area. The conductive strips are usually made of a metal such as aluminum or an aluminum alloy, and, in some instances, can have silicon placed therein. Aluminum adheres well to silicon dioxide and has low contact resistance, but may suffer numerous problems, such as, for example, a propensity to grow "spikes".
In ultra-shallow regions (i.e., junctions having a thickness less than, for example, 1,000 angstroms), aluminum may spike completely through the underlying junction at the contact area. To prevent spiking, the contact structure must be altered with, for example, a sacrificial, passive or stuffed barrier material. The barrier material resides between the aluminum and underlying silicon. A popular barrier comprises titanium nitride, wherein the nitride stuffs the grain boundaries of the titanium thereby preventing a substantial amount of silicon diffusion into the overlying aluminum from the junction region. As the junction region becomes shallower in accordance with modern day technologies, a barrier typically remains configured between the underlying silicon and overlying aluminum. However, the barrier must be formed in a low-temperature ambient so as to not further deepen the shallow junction region.
Along with barrier materials, the contact structures further include steps for lowering the contact resistance at the interconnect/silicon juncture. Specifically, most manufactures utilize a silicide formed at the juncture. The silicide helps break through the residual surface oxide so that good electrical contact can be made. Applying heat necessary for silicidation is sometimes required to adjust the silicon dioxide-silicon interface states. Silicides are made by depositing a thin layer of metal over the entire wafer, heating the wafer to a high enough temperature for the silicon and metal to react in the contact window areas and then etching away the unreacted metal on top of the oxide. Most metals used to form silicide are transition or refractory metals in group IV(B), V(B) and VI(B).
By depositing a refractory metal across the wafer and then heating it, the metal reacts with underlying silicon to form a silicide. Simultaneously, nitrogen atoms are inserted into the upper surface of the metal to provide barrier functionality. For this reason, metals that provide suitable properties for both silicide and barrier formation in a single anneal step are preferable. Unfortunately, the advent of ultra-shallow junctions has lead to many constraints on the silicidation process steps.
First, conventional silicidation processes require an anneal greater than approximately 800 degrees Celsius to form the silicide. Any temperature less than 800 degrees Celsius can produce a non-stoichiometric silicide leading to greater sheet resistance in the contact area. However, at more suitable silicide temperatures approaching 800 degrees Celsius, highly mobile boron dopants within the junction diffuse at greater diffusion lengths causing a deepening of the junction. Deepening of the junction can result in greater parasitic source/drain capacitance and lower breakdown voltages. Additionally, driving away of boron impurities from the surface area to deeper positions can increase the contact and sheet resistance in the contact area. Still further, increased heat can cause boron to diffuse along with silicon atoms into the growing silicide and further deplete boron at the silicon surface (adjacent the lower edge of silicide). Boron depletion caused by high temperature processing or by silicide-induced consumption must be minimized.
It is also important that the silicide be grown to a controlled thickness. If the silicide film becomes too thick, defects can occur at the edge of the silicide film due to stresses in the film. Such defects are reported to begin occurring once the thickness of the silicide film exceeds approximately 100 nanometers. The mechanism for growing silicide is generally understood as species of silicon diffusing from the underlying substrate surface to the overlying (and abutting) silicidation metal. If an excessive amount of silicon atoms are allowed to diffuse, then the silicide is made too thick causing undo stresses in the film. It is therefore important not only to minimize the silicide growth temperature, but also to prevent excessive silicon consumption during the growth process. It is important that the integrity of the boron atoms, once placed, remain in their position to maintain the ultra-shallow junction region and the advantages thereof.
Along these lines, an entire doped region, for example, a source or a drain, can become converted to a silicide thereby ruining the device. Thus, there exists a need in the art for better methods of forming devices that have shorter channels and more particularly, there exists a need to form shallow devices having been subjected to a silicidation step whose doped regions are not excessively converted to a silicide.