Generally, from the viewpoint of attaining a high speed and high performance of an information processing system, the integrated circuit mounted on a system board thereof is required to process and transmit/receive packets within a shorter time (see Japanese Patent Application Laid-Open No. 62-245462, for example).
FIG. 8 is a block diagram schematically showing an example of the configuration of the system board of the conventional information processing system, and FIG. 9 is a block diagram schematically showing an example of the configuration of a system controller thereof.
A conventional information processing system 80, for example, includes a system board 81, which has mounted thereon, as shown in FIG. 8, an I/O (Input/Output: IO) unit (external input/output controller) 82, a CPU (Central Processing Unit) 83, a plurality of (two, in the case shown in FIG. 8) memories 84a, 84b and a plurality of (two, in the case shown in FIG. 8) system controllers (SC) 85a, 85b. 
The I/O unit 82 is a device for controlling the transmission/reception of signals to and from devices external to the system board 81. This I/O unit 82 transmits the data received from external devices, for example, to the CPU 83 through the system controller 85a. 
The CPU 83 is a device which carries out various arithmetic operations using the data received from the system controllers 85a, 85b. This CPU 83 issues a request to the system controllers 85a, 85b to fetch data from the memories 84a, 84b described later, and receives the fetch response data corresponding to the fetch request from the system controllers 85a, 85b. The fetch response data is packetized data (hereinafter sometimes referred to simply as the packet). The memories 84a, 84b are devices for storing and holding the data.
The conventional information processing system 80 is explained in detail below taking the system controller 85a as an example.
The system controller 85a is a device for controlling the transmission and reception of the data between the CPU 83, the memory 84a and the I/O unit 82.
The system controller 85a retrieves the fetch response data from the memory 84a in response to the fetch request of the CPU 83 and sends it out to the CPU 83.
The system controller 85a, for example, as shown in FIG. 9, is configured of a MAC (memory access controller) 86, a data queue (data queue) 87, a fetch response data port 88, a plurality of (k, in the case shown in FIG. 9, where k is a natural number) ports 89-1 to 89-k and a send-out control unit (CPU sending priority) 90.
The system controller 85a that has received a memory fetch request from the CPU 83 retrieves the fetch response data from the memory 84a. The fetch response data retrieved from the memory 84a is shaped, in the MAC 86, into a packet format operable to be processed by the CPU 83 and stored in the data queue 87 on FIFO (first-in first-out) basis. As long as the fetch response data port 88 for participating in the priority control has a vacancy, the fetch response data is retrieved from the data queue 87 and set in the fetch response data port 88. After that, the fetch response data set in the fetch response data port 88 is sent out toward the CPU 83 from the fetch response data port 88 at the time point when the priority is acquired in the send-out control unit 90.
The system controller 85b is a device for controlling the data exchange between the CPU 83, the memory 84b and the I/O unit 82. The configuration and the operation of the system controller 85b are similar to the configuration and the operation, respectively, of the system controller 85a described above.
In the conventional information processing system 80, however, all the fetch response data retrieved from the memory 84a are sent out toward the CPU 83 after being retrieved into the data queue 87. In a case where the capacity of the fetch response data is large, therefore, the write operation into and the read operation from the data queue 87 take considerable time.
Also, even in a case where the packets sent out to the CPU 83 are so small in number and the CPU sending bus has a margin, the fetch response data is required to pass through the data queue 87 without fail. Under any condition, therefore, the write operation and the read operation require some length of time.
The fetch speed is known to have a direct effect on the system performance.
The fact that the fetch response data is sent out to the CPU 83 through the data queue 87, therefore, causes an increased latency and impedes improvement in the performance of the information processing system.
Another cause of the latency increase is the actual path along which the fetch response data passes in the system controller 85a. 
FIG. 10 is a diagram for explaining the fetch response path in the system controller of the conventional information processing system, and shows an example of layout of the various parts on the SC chip.
As shown in FIG. 10, for example, the conventional system controller 85a is such that the MAC 86 is arranged at one end and the data queue 87 at the other end of the SC chip, while the send-out control unit 90 is arranged between the MAC 86 and the data queue 87 on the SC chip.
In the case shown in FIG. 10, the fetch response data retrieved from the memory 84a is transmitted to the send-out control unit 90 through the fetch response data port 88 (not shown in FIG. 10) (see reference character “C2” in FIG. 10) after being transmitted to the data queue 87 from the MAC 86 (see reference character “C1” in FIG. 10).
As described above, the path (C1+C2) permitting the fetch response data to participate in the priority control after being retrieved into the data queue 87 on the chip layout results in a long-distance path. The transfer of the fetch response data along this long-distance path is another cause of the increased latency and impedes improved performance of the information processing system.