The invention relates to a circuit arrangement for controlling and detecting the load current through a load having a load transistor and at least one auxiliary transistor. Each of the transistors have a control terminal, and in each case, a load path and a first load path terminal and a second load path terminal. The load is connected in series with the load path of the load transistor and this series circuit is connected between terminals for supply potential and reference potential. A current measuring arrangement having a first and second input respectively is connected to the first load path terminal of the load transistor and to the first load path terminal of the at least one auxiliary transistor. The current measurement arrangement also has an output, at which a signal dependent on the load current can be tapped off, and a drive unit connected to the control terminal.
A known circuit arrangement of this type is disclosed in DE 198 12 920 A1.
In the case of circuit arrangements of this type, the measurement of the load current through the load is effected according to the so-called “current sense principle”. In this case, the load current that flows into the load via the load transistor, which is very large under certain circumstances, is determined indirectly by way of a measurement current flowing through the auxiliary transistor. The ratio IL/IS of load current to measurement current, the so-called sense ratio, corresponds to the ratio of the transistor areas or number of transistor cells of the load transistor and of the auxiliary transistor if these two transistors are operated at the same operating point. In order to set the common operating point, the load transistor and the auxiliary transistor have a common control terminal, and they are connected to an identical supply potential. A regulating arrangement, which is part of the measuring arrangement, furthermore has the effect that the potential at the first load path terminal of the auxiliary transistor is set to the value of the potential of the first load path terminal of the load transistor. The same voltage in each case is thus present between the common control terminal and the first load path terminals of the two transistors. The voltage across the load path of the load transistor likewise corresponds to the voltage across the load path of the auxiliary transistors, so that the two transistors are operated at the same operating point.
The accompanying FIG. 1 illustrates an example—designated by the reference numeral 1—of the above-described known circuit arrangement for controlling and detecting the load current through a load RL. As mentioned, the load transistor LTR, here an n-channel FET, and the auxiliary transistor STR, here likewise an n-channel FET, which are interconnected on the drain side and gate side, are at the same supply potential Vbb. The load path D-S of the load transistor LTR is connected in series with the load connected to the output A, here indicated by way of example by a load resistor RL, through which the load current IL flows. Connected to the same circuit point, that is to say to the source electrode S of the load transistor LTR, is a first input of a current measuring arrangement MA comprising an operational amplifier OPV, a p-channel regulating transistor PTR and a measuring resistor RS. The second input of the current measuring arrangement MA is connected together with the source electrode of the regulating transistor PTR to the source electrode S of the auxiliary transistor STR so that the potential at the source electrode S of the auxiliary transistor STR is set to the value of the source potential of the load transistor LTR. The current IS flows through the measuring resistor RS, which current is ideally in a fixed ratio to the load current IL, so that a voltage US proportional to the current IS is dropped across the measuring resistor RS, which voltage is input into an analog-to-digital converter ADC of a drive unit μC. The drive unit μC supplies a drive signal to an input terminal E of the circuit arrangement. For the case where the supply potential Vbb is the higher potential and the reference potential M is the lower potential, for example ground, and the load transistor is an n-channel FET, the circuit arrangement illustrated in FIG. 1 forms a so-called “high-side switch”.
Comparators, such as the operational amplifier—designated OPV—of the current measuring arrangement MA, and in particular comparators produced in integrated CMOS technology, disadvantageously have an unavoidable voltage offset which, in the circuit arrangement illustrated in FIG. 1, has the effect that a readjustment of the regulating transistor PTR no longer takes place even when a voltage difference corresponding to the voltage offset of the comparator OPV exists between the potentials of the first load path terminals, that is to say the source electrodes of the load transistor and of the auxiliary transistor. The voltage across the load path D-S of the auxiliary transistor STR thus always deviates from the voltage across the load path of the load transistor by the magnitude of the voltage offset of the comparator OPV. In other words, the load transistor LTR and the auxiliary transistor STR do not operate exactly at the same operating point.
In the case of large load currents and, by virtue thereof, a correspondingly large voltage drop exists across the load path of the load transistor, and this deviation of the load path voltage of the auxiliary transistor STR by the value of the voltage offset of the comparator OPV, which is usually in the region of a few millivolts, is hardly significant at all. However, if very small load currents flow, and bring about a very small voltage drop across the load path of the load transistor LTR, which voltage drop, in the extreme case, is in the region of the voltage offset of the comparator OPV, then said voltage offset has a considerable effect on the operating point setting of the auxiliary transistor STR, so that the operating points of the two transistors deviate considerably from one another and the measurement current IS is no longer proportional to the load current IL. The measurement result is thereby corrupted to a significant extent.
DE 198 12 920 A1 mentioned above proposes solving this problem by additionally connecting in parallel with the load transistor LTR at least one second load transistor, which can be driven via a second control terminal by the drive unit μC depending on the load current or depending on a load path voltage obtained across the load path of the load transistors.
Another possibility, not used in practice, would be to increase the value of the measuring resistor RS in the case of small measurement currents IS, thereby obtaining a higher voltage drop US for the same current IS. The external circuitry outlay for changing over the resistor is disadvantageous in this case.
At the present time, the so-called sense ratio nL/nS cannot be decreased arbitrarily by increasing the number of auxiliary transistors STR, since, due to the higher measurement current Is thus achieved, the regulating transistor PTR for the upper current range, in the case of which very large measurement currents IS flow, would become very large and thus expensive on account of the power loss consumed by it. In practice, the sense ratio nL/nS is at present downwardly limited to 5,000/1, for example.