Scaling in semiconductor fabrication can be problematic, particularly in SRAM cells. For example, in SRAM cells, as the fin spacing and gate pitches become smaller, contact shorting and epitaxial merging of source and drain regions can occur. This can also occur in different types of devices.
For example, the space between an NFET device and PFET device can be 50 nm or less in smaller nodes; whereas, the space between PFET devices can be 40 nm or less in smaller nodes. This can result in epitaxial regions for the source and drains of these devices merging together. Similarly, contact spacing between the devices can be 40 nm and even 30 nm for smaller nodes, each of which present a problem associated with contacts shorting, e.g., Vdd, Vss and bitlines in SRAM cells. Tighter fins, e.g., spacing between fins, also presents problems of shorting and/or merging of epitaxial materials, leading to impaired device performance.