As is well known, the manufacture of non-volatile matrixes with a memory of the so-called EPROM and Flash types has proved to have a relatively low yield.
The prior art attempted to rectify the low yield of the Flash memory production process and the solution adopted so far consists in equipping the cell matrix with additional so called redundancy, which may be used to replace faulty columns and/or rows that show malfunctions after the device has been tested.
Those skilled in the art are familiar with the design and use methodology of redundancy columns and rows as well as of the relative selection circuitry. The latter makes it possible for the memory to be readdressed in such a way as to replace the addresses containing faulty bits by those containing functional bits in the redundancy columns or rows.
At present, the constant evolution of technology and the semiconductor market trend dictate the design of memory devices capable of operating at lower and lower supply voltages.
This gives rise to a number of problems due to the fact that in order to obtain a memory device that is efficient and has a fast response time, particularly in the reading mode, even the redundancy cells and circuitry must meet certain stringent specifications. In particular, the UPROM memory cells incorporated in the selection circuitry, containing the binary code of the addresses to be set as redundant, must be designed to operate efficiently even at low voltages.
In FIG. 1, there is illustrated the basic structure of a UPROM 2 memory cell provided between a first reference voltage Vdd and a second voltage reference GND, a ground signal, for example.
Such UPROM cell comprises a memory element represented by an EPROM or Flash type cell FC having a floating gate and containing a binary code of an address to be set as redundant. This cell FC has a conduction terminal, the source terminal, directly connected to ground, while another conduction terminal, the drain terminal, is connected to the power supply Vdd by means of a complementary MOS transistor pair M1, M2.
The basic structure of the UPROM 2 cell also comprises a latch structure consisting of a first inverter I1 and a second inverter I2 each having their respective input and output terminals connected to the output and input of the other inverter.
The first transistor MOS M1 of the complementary pair is of the P-Channel type and connects the input of the first inverter I1 with the supply Vdd. The second transistor MOS M2 is of the N-Channel type and connects the input of the first inverter I1 to the drain terminal of the cell FC in a source follower configuration.
The control terminal of the FC cell receives a signal UGV, whereas to the respective control terminals G1 and G2 of transistors M1 and M2, a signal POR# and a polarization voltage signal VB are applied. The signal POR# represents the NOT form of the start and reset signal POR referred to as POWER ON RESET.
The signal POR is applied to the control terminal G3 of an enabling transistor M3 inserted between the output of the first inverter I1 and ground GND.
Inverters I1 and I2 form a latch register and transistors M1, M2 and M3 allow to effect the start-up step of said latch.
The cell FC is programmed during the testing step, i.e., when the memory devices undergo an EWS (Electrical Wafer Sort) test. Before carrying out any kind of operation on the memory device, all the cells FC of the UPROM circuitry are read, thus enabling correct addressing of the memory cells which are to be replaced.
In order to carry out the reading it is necessary to suitably polarize the terminals of the cell FC.
While operating at low supply voltages Vdd, close to 1.8 Volts, problems arise when generating and controlling the signals necessary to achieve the above mentioned polarization step.
The cells FC incorporated in the UPROM cells generally have a voltage threshold exceeding 2 V, usually of approximately 2.5 V, and a low current absorption; therefore, in order to effect the reading it is necessary to boost the supply voltage Vdd to reach an appropriate voltage level UGV to be applied to the control terminal of the Flash cell type memory element FC.
In order to carry out the reading it is also necessary to supply a correct drain voltage value VB onto the FC cell so as to avoid electrical stresses. Usually, the drain voltage level is set at 1 V.
A known technical solution to generate the voltage levels UGV and VB is described in the European Patent Application No. 95830242.2 in the name of SGS-Thomson Microelectronics S.r.l.
The hereto attached FIG. 2 illustrates an example of embodiment of a polarization circuit disclosed in that application.
Said circuit, indicated in its whole with the numeral 1, is responsible for the generation of the signal VBa to be applied to the control terminal of the transistor M2 of the UPROM 2 cell.
The level of voltage VBa must be such so as to maintain the drain potential of the memory cell FC at approximately 1 V.
Circuit 1 essentially comprises a first section for timing and a second section 8 for generating the voltage VBa.
Generation section 8, comprises a logical gate P5 of NOR type inserted in the circuit with a feedback loop 9.
The output of the logical gate P5 is connected to the control terminal of a N-channel natural transistor M10 having a conduction terminal connected to the power supply source Vdd by means of a transistor M11 and the other conduction terminal connected to ground via transistor M12 in diode mode connected in turn to another transistor M13.
The control terminal of the transistor M11 is connected to a first input A of the gate P5, whereas the node linking transistors M12 and M13 are feedback connected to the other input B of the gate P5.
The control terminal of transistor M13 is connected to the output of the first timing section.
Between the transistors M10 and M12 there is an output node U2 from which output voltage VBa is derived; Such output node U2 is connected to ground via a transistor M14 in parallel with a stray capacitor C11.
The control terminal of this latter transistor M14 is connected to the first input A of the logical gate P5.
When the gate P5 has a high logic value on one of its inputs, its output will accordingly have a low logic value, which will keep the transistor M10 switched off. If the input A is high, then the transistor M14 is switched on and maintains the value of the output node U2 at ground.
When the transistor M10 is switched on, on the contrary, current is allowed to pass through the transistors M10, M11, M12. Voltage VBa on the output U2 can reach the operating level set by the trigger threshold of gate P5 and by the threshold voltage of the transistor M12.
If the voltage VBa were to have a lower value than that indicated, the output of the gate P5 would allow the transistor M10 to conduct more current, thus increasing the output voltage value.
If, on the contrary, the voltage VBa were to exceed the chosen value, the feedback input of gate P5 would have a potential value higher than the trigger threshold of the gate itself, bringing the output to a low potential level and switching off the transistor M10. In this way VBa would be reduced until it reaches the pre-set value.
Although for various reasons this could be considered a viable solution, it does not completely fulfill the actual requirements for a correct polarization (that is biasing) of UPROM cells due to a low rejection to the rapid changes of supply voltage Vdd caused by electrostatic discharges.
It is, in fact, extremely important that voltage VBa never reaches undesired levels during electrostatic discharges.
The output voltage VBa of the circuit just described is determined by the trigger voltage of the NOR logic gate and by the threshold voltage of the MOS natural transistor M12.
Since the trigger voltage of the NOR logical gate depends on the value of the supply voltage Vdd, even the output voltage VBa will depend on and vary linearly with the voltage Vdd.
Therefore, the solutions put forward by the prior art do not offer proper rejection to the changes in the supply voltage and are not able to prevent spurious alterations (unwanted programming) in the flash memory cell incorporated in the UPROM cell.