1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to methods and apparatus for connecting capacitors to substrates.
2. Description of the Related Art
All integrated circuits require electrical power to operate, and packaged integrated circuits, which consist of a semiconductor chip mounted on a package substrate, are no exception. Power is normally delivered to integrated circuits via a power supply and some form of power delivery network. Although currently-available power supplies are designed to supply stable voltages, the actual power delivered to integrated circuits can contain significant amounts of noise. There are many sources of noise, such as voltage fluctuations caused by other devices coupled to the power supply, electromagnetic interference and other causes.
Packaged integrated circuits use decoupling capacitors to lower noise on the power supply. Some of these decoupling capacitors are located on the package substrate. A typical conventional decoupling capacitor consists of a stack of plates commonly connected to two terminals. The capacitor is mounted to a package substrate by way of a pair of solder capacitor pads: one for each terminal. The capacitor pads are positioned on and electrically connected to corresponding conductor pads. The conductor pads are connected to various conductor lines or traces in the substrate that link up electrically with the semiconductor chip.
In a typical conventional substrate, multiple conductor pads are fabricated with different sizes tailored to match different physical sizes of capacitors. The conventional solder capacitor pads are sized to closely match the sizes of the underlying conductor pads. For example, two large solder pads are fabricated on two large underlying conductor pads to accommodate a large two terminal capacitor. Conversely, two small solder pads are fabricated on two small underlying conductor pads to accommodate a small two terminal capacitor.
After the conductor pad layout for a package substrate is selected, the designer makes an estimate of the decoupling capacitance required for the combination of the package substrate and a particular semiconductor chip. The estimate is based on experience, rules of thumb, and simulations. With an estimate in hand, the designer then selects a collection of capacitors that provide the estimated decoupling capacitance for connection to the solder capacitor pads.
A difficulty can arise where the actual required decoupling capacitance does not match the estimated decoupling capacitance. If, for example, the estimated decoupling capacitance turns out to be too large, the excessive capacitance may result in excessive damping. In this circumstance, it would be desirable to lower the actual decoupling capacitance for the substrate. One conventional technique to solve the problem involves a costly and time consuming redesign of the substrate. Another technique involves attempting to retrofit different sized capacitors to the substrate to raise or lower the actual total decoupling capacitance. Since the conventional solder capacitor pads are sized to correspond to the sizes of the underlying conductor pads, the retrofit often involves trying to place a small capacitor on a large solder capacitor pad. If small capacitor-to-large capacitor pad alignment is off, or if the large solder capacitor pad has any stringers, open or short circuit conditions can occur.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.