In a conventional semiconductor device, reduction of a core region that is a region other than an I/O (Input/Output) region is possible with miniaturization of semiconductor technology node. However, the chip size of the semiconductor device cannot be reduced correspondingly to the reduced core region. The reasons are as follows.
(1) Since the electrode pads of the integrated circuit, which are disposed in the I/O region, are not so much decreased while the circuit in the core region can be reduced, the chip size would be undesirably determined depending on the electrode pads disposed in the I/O region.
(2) While the layout of the integrated circuit is carried out using cells, in order to prevent wires from contacting the cells during plastic molding that is performed after wire bonding, it is necessary to secure the spaces between the adjacent electrode pads in the vicinity of the corner of the semiconductor chip, which are larger than those in cases where the cells including the electrode pads are closely arranged, as a restriction on assembly.
(3) When initial failures of semiconductor devices should be eliminated by performing an acceleration test in wafer level (hereinafter referred to as “wafer level burn-in” (WLBI)), in order to perform reliable contact to the cells by using such as a probe for supplying signal and current for WLBI to the semiconductor devices, it is required to dispose WLBI pads which are larger than the electrode pads for wire bonding for normally operating the semiconductor devices, on the semiconductor device. Further, when these plural WLBI pads are adjacently disposed on the semiconductor devices, large spaces must be secured between the respective WLBI pads. This results in a restriction on WLBI.
FIG. 11 is a schematic diagram illustrating a layout of a corner portion of the conventional semiconductor device.
As shown in FIG. 11, in the corner portion of the conventional semiconductor device, an I/O region 51 and a core region 52 are provided on a semiconductor substrate 50.
A plurality of cells 54 having electrode pads for I/O 53, which are parts of the integrated circuit, are disposed in the I/O region 51, while the integrated circuit and other circuits are disposed in the core region 52. The I/O region 51 is provided along the periphery of the semiconductor substrate 50, and a corner cell 57 is disposed in a corner portion of the semiconductor substrate 50. The core region 52 is disposed in the center of the semiconductor substrate 50. The electrode pads 53 are pads for performing wire bonding with the outside, and the adjacent electrode pads 53 are disposed with a space 55 between them, and this space 55 is set to a value that satisfies the above-mentioned restriction on assembly.
For example, in order to keep the restriction on assembly in designing the semiconductor device, it is necessary to secure a space 55a between the adjacent electrode pads, for example, 53a and 53b, as shown in FIG. 11. Thereby, the wires connected to the electrode pads are prevented from contacting each other during plastic molding, and reduction in the yield is avoided. However, since the chip size is undesirably determined by the space 55 between the adjacent electrode pads 53 which is determined by the restriction on assembly, it is difficult to minimize the chip size even when micro processing is used.
FIG. 12 is a schematic diagram illustrating a layout of a periphery portion of another conventional semiconductor device.
In FIG. 12, the same reference numerals as those shown in FIG. 11 denote the same or corresponding parts. In an I/O region 51 at the periphery of the semiconductor substrate 50, two I/O cells for WLBI 80 having electrode pads for WLBI 81 are disposed with a space 88 between them. This space 88 is set to a value that satisfies the above-mentioned WLBI restriction.
The WLBI is an acceleration test that is performed to eliminate initial defectives, prior to the assembly processes for semiconductor chips, such as wire bonding and plastic molding. By performing this acceleration test, reduction in the assembly cost can be achieved. Usually, in the WLBI, plural semiconductor devices fabricated on a wafer are kept at a high temperature in the wafer state, and humidified, and further, held under the state where a power supply voltage and signals such as a clock signal are applied to the respective chips of the semiconductor devices, thereby deteriorating the semiconductor devices. Therefore, it is necessary to fabricate a signal application probe card for applying the above-mentioned signals during the WLBI, and there also exists a restriction on layout of the electrode pads for WLBI to fabricate the probe card without failures and make accurate contacts with the respective chips on the wafer. To be specific, as shown in FIG. 12, an electrode pad having a size larger than the standard-size electrode pad to be wire bonded, usually, having a width about 30% larger than that of the electrode pad for wire bonding, is used as the pad for WLBI 81. Further, when plural pads for WLBI 81 are disposed, it is necessary to secure a space 88 between the adjacent pads.    Patent Document 1: Japanese Published Patent Application No. 3-99445.