1. Field of Invention
The present invention relates to a method for manufacturing a dynamic random access memory (DRAM) capacitor. More particularly, the present invention relates to a method for forming a lower electrode opening for a DRAM capacitor.
2. Description of Related Art
As the microprocessor of a computer becomes more powerful, the number of software programs that can be run by a computer simultaneously increase exponentially. Consequently, the amount of memory space necessary for storing digital data must also be increased. Therefore, highly efficient memory capacitors are in great demand. Accompanied by the increase in level of integration of DRAMs, a DRAM cell is now constructed from just one transfer field effect transistor and a storage capacitor. In general, a capacitor has an upper electrode and a lower electrode with a dielectric layer sandwiched between the two for providing the necessary dielectric constant. In addition, the capacitor is electrically coupled to a bit line, and reading and writing to and from the DRAM memory is achieved by charging or discharging the capacitor. Charging and discharging of the capacitor is carried out through the control of a transfer field effect transistor (TFET). The source terminal of the transfer transistor is connected to the bit line while the drain terminal of the transfer transistor is connected to the capacitor. The transfer transistor is switched on or off through a selection signal coming from a word line, which is electrically connected to the gate terminal of the transfer transistor. Hence, whether the capacitor is connected to the bit line allowing for charging or discharging of the capacitor depends upon the selection signal passed to the gate terminal.
Factors that affect the capacitance of a capacitor include: (1) the lower electrode; a lower electrode having a larger surface area will have more capacitance; (2) the dielectric constant of the dielectric layer; using a dielectric material having a higher dielectric constant to form a capacitor will increase its capacitance; and (3) the thickness of the dielectric layer; the thinner the dielectric layer, the higher its capacitance will be. Conventional DRAMs having storage capacity smaller than one megabits (Mbit) mostly have two-dimensional capacitors, commonly referred to as a planar type of capacitor. However, a planar type capacitor occupies lots of semiconductor substrate area, and so is unsuitable for use in high level integrated circuits. Highly integrated DRAM circuits, for example, those with memory having a storage capacity larger than about four Mbits, use three-dimensional capacitors. Three-dimensional capacitor constructs include the stacked type and the trench type.
Compared with a planar type of capacitor, a stacked type or a trench type of capacitor is able to provide the same capacitance to a capacitor despite a dimensional reduction. However, when the scale of integration for memory devices is further increased, for example. DRAM memory that stores up to 64 Mbit, even a simple three-dimensional capacitor construction is not enough.
One method of further increasing the surface area of the lower electrode, hence increasing the capacitance of a capacitor, is to develop horizontal extensions and then stacking them one over the other creating a fin-type of stacked capacitor. Another method is to allow the electrode and the dielectric film of the capacitor to extend vertically up to form a vertical structure called a cylindrical stack.
Yet, in the near future, the trend for integrating more and more devices into a wafer will continue, and the dimensions of a DRAM cell will shrink still further. As anybody familiar with the technology may well know, more reduction in memory cell dimensions will lead to a further reduction of the capacitance for its capacitor. One consequence of this is the production of more soft errors due to an increased effect by alpha rays. Therefore, people engaged in the semiconductor industry are still searching for ways to increase the capacitance of a capacitor though the available area is reduced.
In light of the foregoing, there is a need provide an improved method of fabricating DRAM capacitor.