An example of a prior art RF receiver chip 10 connected to an antenna 12 is illustrated in FIG. 1. In FIG. 1, the chip 10 is comprised of a radio frequency front end 14. The front end 14 comprises circuitry for receiving an RF signal 13. The front end 14 demodulates the received RF signal 13 to produce a baseband signal 15. The baseband signal 15 is output from the RF front end 14 to an automatic gain controlled amplifier 16. The gain of the amplifier 16 is automatically adjusted, typically through a feedback loop 17, so that the baseband signal 15 is appropriately amplified to take advantage of the full dynamic range of a digital to analog converter 18. After amplification, the baseband signal 15 is input to the analog to digital converter 18 which produces a digital signal 19. The digital signal 19 is input to a baseband digital signal processor (DSP) 20 which produces output data 21. The DSP 20 has a DC offset adjustment circuit 22 at its front end. The analog to digital converter 18 may also perform a DC offset adjustment. Alternatively, a DC offset adjustment may be made prior to the analog to digital converter 18. However, after the analog to digital conversion, there may be a residual DC offset. This residual DC offset is an artifact typically present in conventional RF receiver chips and may be as much as 50 milivolts, or ten percent of the dynamic range of the analog to digital converter 18. That DC offset, coupled with carrier frequency offset (CFO), can severely degrade the performance of high-data rates which have higher order constellations. It is therefore prudent to compensate for this DC offset.
One example of a prior art circuit for dealing with DC offset compensation is illustrated in FIG. 2. The DC offset adjustment circuit 22 is comprised of a feedback loop in which a portion of the signal is multiplied by a weighting factor alpha through the use of a multiplier 26. Typically, alpha will be less than one. The weighted signal component is then input to a summer 28, the output of which is input to a delay circuit 29. The output of the delay circuit 29 is fed back to the summer 28. The combination of the multiplier 26, summer 28, and delay circuit 29 acts as an estimator 31 which, over time, averages the signal to produce an estimate of the DC offset. That estimate of the DC offset is then input to a summer 32 so as to be subtracted or removed from the signal produced by the analog to digital converter circuit 18.
In operation, by making alpha large (i.e., close to 1), more weight is placed on the current sample value and less weight is placed on the average value. Conversely, by making alpha small (i.e., close to 0) less weight is placed on the current sample value and more weight placed on the average value. Typically, alpha is close to zero such that the estimator 31 needs time to accumulate a number of samples to produce a reasonable estimate of the DC offset. Thus, the DC offset adjustment circuit 22 illustrated in FIG. 2 works well if the DC offset is low or if there is sufficient time to estimate the DC offset. For example, in the case of an 802.11b preamble, there is sufficient time (approximately 150 to 200 microseconds) to estimate the DC offset. However, if the DC offset has to be estimated quickly, the DC offset adjustment circuit 22 illustrated in FIG. 2 will not have sufficient time to produce an accurate estimate of the DC offset.
An example of a situation in which the DC offset adjustment circuit 22 illustrated in FIG. 2 will not have sufficient time to produce an accurate estimate of the DC offset can be found in certain communication schemes which fall within the 802.11 standard. In the case of an information packet in conformance with 802.11 a/g/n, the preamble will be on the order of eight microseconds. FIG. 3 illustrates a short training field (STF) within a preamble of an 802.11 a/g/n compliant information packet. The short training field comprises ten equal time periods, which are each 0.8 microseconds in length. The short training field is used for presence detection, synchronization, gain setting, and coarse carrier frequency offset calculation. The entire short training field, at eight microseconds in length, is substantially shorter than the approximately 150 to 200 microseconds of an 802.11b preamble.