a) Field of the Invention
The present invention relates to a semiconductor device having an antireflection film on the surface of a wiring layer, and a method of manufacturing such a semiconductor device. More particularly, the invention relates to a semiconductor device and a method of manufacturing the same, capable of forming a fine wiring at a high precision.
b) Description of the Related Art
A resist exposure process such as illustrated in FIG. 11 has been used for manufacturing a semiconductor device such as an LSI.
Referring to FIG. 11, on the surface of a semiconductor substrate 1 such as silicon (Si) substrate, an insulating film such as silicon oxide is selectively formed by thermal oxidation. Thereafter, a wiring layer 3A made of aluminum (Al), alloy or the like is formed by sputtering or other methods. A photoresist layer 4A is coated on the surface of the substrate by spin coating or other methods. In the following description, it is assumed that a positive resist is used.
For the resist exposure, a light shielding mask 5 corresponding to a desired wiring pattern is disposed above the substrate, and light 6 is radiated down to the resist layer 4A. Since the surface of the wiring layer 3A made of Al alloy or the like has a light reflection property, the light 6 is reflected also at the slopes AB and CD at a step region. The light 6 goes back to the area of the resist layer 4A andl exposes it, in spite of the fact that the area is covered by a mask 5 and should not be exposed.
After the following resist development process, the remaining resist layer takes different sizes and dimensions in the slope area and the flat plane area such as shown in FIGS. 12 to 14. Namely, as shown in the plan view of FIG. 12, the width W at the step area becomes narrower than the width at the flat area. In other words, the wiring layer has a neck or a notch shape. The cross sections taken along lines X--X' and Y--Y become as shown in FIGS. 13 and 14, respectively. As shown in FIG. 13, the cross section at the flat area is rectangular as designed. However, as shown in FIG. 14, the cross section at the step area is semicircular and has a width W narrower than the designed width.
The narrow part having a smaller width W of the resist layer 4 broadens the variation of dimension of a wiring layer pattern formed by dry-etching the wiring layer 3A by using the resist layer 4 as the etching mask. Moreover, during the etching process, the narrow part may cause a breakage of wiring if the etching rate relative to the resist layer is low. The variation of dimension, particularly of gate electrodes, may easily become a cause of a variation of device performances.
As a method of reducing the generation of the narrow part of a resist pattern to be caused by reflected light from a slope, methods such as using resist added with dye which absorbs reflected light from a slope, and coating an antireflection film such as titanium nitride (TiN) on the surface of a wiring layer to suppress reflection at a slope, are known.
In the case of the dry etching using the resist layer 4 as the etching mask, there is another problem of a low etching rate relative to an SiO.sub.2 film which underlies of the wiring layer. For example, in forming gate electrodes and wirings of a MOS LSI, the gate electrode/wiring layer such as polysilicon is dry-etched using the resist layer as the etching mask, under the condition that the etching rate or speed of the gate electrode/wiring layer is faster than that of the mask. If the etching rate relative to the SiO.sub.2 is low, the SiO.sub.2 film serving as the gate insulating film is over-etched and made thin. As a result, the device performance iaiay change because the SiO.sub.2 film is very thin. It is therefore required to raise the etching rate relative to an underlying layer such as an SiO.sub.2 film.
In order to meet this requirement, use of a silicon oxide film in place of a resist film as the etching mask, is known (for example, refer to a monthly magazine "Semiconductor World", January, 1990, pp.81 to 84). In this case, in order to stop or reduce a supply of carbon (C) to the etching system, a silicon oxide film not containing C is used as the etching mask instead of a resist film containing C. By using a chlorine-based (Cl-based) or bromine-based (Br-based) based gas as an etchant, the etching rate of a wiring layer relative to an SiO.sub.2 film can be improved.
If a resist film added with dye is used, the resolution of the resist film patterning lowers so that a fine wiring is difficult to form. Moreover, as shown in FIG. 15, the resist layer 4 is likely to have a tapered section with skirt regions 4a and 4b. The skirt regions 4a and 4b are etched at the later process, making the width of the wiring layer narrower than a desired width.
If a TiN antireflection film, the resist layer 4 as an etching mask, and gas containing Cl or Br, are used to plasma-etch the lamination of the wiring layer and TiN film, a wiring made of the remaining wiring layer 3 and TiN film 5 can be obtained as shown in FIG. 16. However, because of a low etching speed, the etching selectivity relative to the resist film lowers, and a fine wiring is not able to be formed.
Furthermore, the reaction product by the etching gas and TiN attaches to the pattern side walls to form sticking layers 6a and 6b: As a result, the width W.sub.1 of the resist layer increases to W.sub.2, making the width of a wiring broader than a desired width. The increase of the width depends on the density of a pattern. The coarser the pattern, the increment width becomes greater and the variation of dimension becomes larger.
If a silicon oxide is used as an etching mask, the narrower area of a resist pattern caused by reflected light from a slope is inevitable because the silicon oxide film will not function as an antireflection film.