In recent years, many telephone, video and data communication systems have been developed where digital data streams are encoded into short packets or cells instead of using synchronous transmission. The evolving world-wide standard for this packet-based transmission and switching technology is called Asynchronous Transfer Mode (ATM). Although networks are evolving to ATM transmission, interfaces are needed to present-day synchronous switching and transmission systems and to end-point terminal equipment. Voice and video channels invariably require constant bit rate, synchronous interfaces. The process of converting from ATM, or other packet-based transmission, to a constant bit rate synchronous system basically requires two steps. The first step is extracting the cell payload data, which carries the synchronous bit stream, and storing it in a first-in-first-out (FIFO) memory. The FIFO acts as an elastic store to smooth out the bursty cell arrival. The second step is to recover or derive a clock, based on the average data arrival bit rate, and use the derived clock to clock data out of the FIFO and into a transmission interface circuit for transmission. Adaptive clocking is a name for the process of deriving an accurate clock rate from the data rate of the arriving cell/packet stream.
The ATM cell stream is often bursty with short term variations in the cell arrival rate, which are on the order of one millisecond for some ATM systems. The derived (adapted) clock rate must stablize in seconds to a typical level of a few parts-per-million (ppm), and in the long term, must track the source rate exactly. Requirements vary widely between different systems and applications. Integrating the number of arriving ATM cells over a period of time is the fundamental technique in determining the mean clock rate. Long integration times can be used to produce a low jitter, narrow-band clock output. However, relatively long integration times cause a host of stability problems if a "conventional" phase-locked-loop (PLL), e.g., arrangement 210 (FIG. 10) described herein, is applied to this application. The integration time is directly related to feedback delay in the PLL control loop, which tends to make closed loop control systems unstable. Additionally, the adaptive clock slew rate must be limited, which causes more feedback delay. The damping factor will be large causing slow response and unstable operation. The use of phase-lead or multiple pole circuits, in the loop of a "conventional" PLL, to control damping is not practical because the cell stream has too much jitter to derive needed phase-lead information over short intervals. Another way to state this is that the signal to noise ratio of input phase/frequency information does not facilitate use of a two-pole filter in a "conventional" PLL. Without the use of multiple poles in an (extremely) narrow-band PLL, the damping factor cannot be effectively adjusted to provide stable operation in this application. A "conventional" PLL with sufficient gain and narrow-band characteristics has been found to oscillate.
In addition to solving the above mentioned response damping problem, an adaptive clock recovery circuit should: (1) develop a low jitter (narrow-band) clock from the bursty ATM input stream; (2) have good or near ideal damping stability; (3) have fast response which is limited only by the necessary integration of jitter; (4) have sufficient gain (FIFO level control) to meet clock tracking and wander specifications; (5) have controlled clock slew rates; (6) maintain a precise jitter build-out delay (the elastic FIFO store queuing level); and (7) be adjustable by parameters and suitable for a range of applications and requirements.
In view of the foregoing, a need exists in the art for an improved arrangement for recovering a synchronous clock from an asynchronous packet stream without relying on closed-loop adjustment of the recovered synchronous clock frequency as in "conventional" phase-locked loop (PLL) arrangements.