In the formation of wafer-level chip scale package structures, integrated circuit devices such as transistors are first formed at the surface of a semiconductor substrate in a wafer. An interconnect structure is then formed over the integrated circuit devices. A metal pad is formed over, and is electrically coupled to, the interconnect structure. A passivation layer and a first polyimide layer are formed over the metal pad, with the metal pad exposed through the openings in the passivation layer and the first polyimide layer.
A seed layer is then formed on the first polyimide layer, followed by the formation of Post-Passivation Interconnect (PPI) lines and pads. The PPI lines and pads may be formed by forming and patterning a first photo resist on the seed layer, plating the PPI lines and pads in the openings in the first photo resist, and then removing the first photo resist. The portions of the seed layer that were previously covered by the first photo resist are removed. Next, a second polyimide layer is formed over the PPI lines and pads, and an Under-Bump Metallurgy (UBM) is formed extending into an opening in the second polyimide layer. The UBM is electrically connected to the PPI lines and pads. The UBM is used to form a solder joint with a package substrate.
The formation of the UBM also involves forming a UBM seed layer, forming and patterning a second photo resist, forming the UBM on the UBM seed layer, removing the second photo resist, and removing the portions of the UBM seed layer that were previously covered by the second photo resist.
In the above-discussed process steps, two photo resists are formed and removed, and two seed layers are formed and partially removed. The manufacturing cost is thus high. Improved methods and structures for wafer-level package continue to be sought.