In conventional FETs, a structure in which a buried layer having a conductivity type opposite to that of an operating layer, is formed under the operating layer, including a channel layer, to reduce leakage current from the operating layer to the semi-insulating substrate has been proposed.
FIG. 8(a) is a cross-sectional view schematically showing the structure of a conventional self-aligned gate MESFET having a buried layer. In FIG. 8(a), reference numeral 1 designates a semi-insulating GaAs substrate. A gate electrode 2 is disposed on the substrate 1. N type high dopant concentration layers, i.e. n.sup.+ type source and drain regions, 5a and 5b are disposed at the opposite sides of gate electrode 2. An n type channel layer 3 is disposed directly under the gate electrode 2. A p type buried layer 11 is disposed under the n type high concentration layers 5a and 5b and surrounds these semiconductor layers 3, 5a, and 5b. Source and drain electrodes 6a and 6b are disposed on the n.sup.+ source and drain regions, respectively.
FIG. 8(b) shows an energy band structure in the depth direction in the channel region of a MESFET having the p type buried layer. In this structure, carriers (electrons) in the n type channel layer 3 are confined in the n type channel layer 3 because of the existence of a p-n junction barrier produced by the n type channel layer 3 and the p type buried layer 11, so that the leakage current to the substrate below the channel layer is reduced. Therefore, the short channel effect, for example a shift of threshold voltage V.sub.th toward negative side, is suppressed, resulting in MESFETs having high uniformity, high reproducibility and improved high-frequency characteristics.
As shown in FIG. 10(a), the threshold voltage V.sub.th varies depending on the thickness W of channel region C formed between the source S and the drain D. That is, the threshold voltage V.sub.th decreases with an increase in the thickness W. Therefore, when a leakage current flows, a current path is also formed below the channel region and then the effective thickness of channel region increases to W.sub.1, resulting in a reduction of threshold voltage V.sub.th. This phenomenon is the same as the above-described shift of threshold voltage V.sub.th toward negative side, which is one of various unfavourable phenomena, i.e., the short channel effect, occurring when the gate length L.sub.g is reduced. When a buried layer is formed below the channel layer, the leakage current is reduced and then the short channel effect is suppressed. As a result, deterioration in the high frequency characteristics of FET, i.e. the switching characteristics at high frequency of FET, are prevented.
It is difficult to suppress the variations in the thickness W of channel region C, and this is a problem in view of uniformity and reproducibility of FETs. However, when the buried layer is formed below the channel region, the buried layer prevents the channel region C from extending downward and keeps the thickness W constant, so that the uniformity and reproducibility of FETs are enhanced.
FIGS. 9(a) and 9(b) are cross-sectional views, respectively, showing other structures of conventional MESFETs having p type buried layers. The structure of FIG. 9(a) includes a p type buried layer 11a formed under the n.sup.+ source and drain regions 5a and 5b and the n type channel layer 3. The p type buried layer 11a does not cover the side surfaces of source and drain regions 5a and 5b, as only one difference from the structure of FIG. 8(a). In this structure, the leakage current from the bottom surfaces of high concentration n type regions 5a and 5b and channel layer 3 can be prevented, although a little leakage current is generated at the side surfaces of those regions 5a and 5b.
The structure of FIG. 9(b) includes a p type buried layer 11b formed below the n type channel layer 3. The p type buried layer 11b is only in contact with portions of bottom surfaces of n type high concentration regions 5a and 5b which is different from the structure of FIG. 8(a). In this structure, although the leakage current from the channel layer 3 to the substrate is prevented, the leakage current from the source and drain regions 5a and 5b to the substrate cannot be sufficiently suppressed.
In the above-described structures of conventional MESFETs, the p type buried layer formed below the n type channel layer is effective in suppressing the short channel effect. However, since the p type buried layer is in contact with the n type high concentration layers 5a and 5b with sufficiently larger area than the area of the n type channel layer, the gate parasitic capacitance increases due to the capacitance between the p type buried layer and the n.sup.+ type layers, whereby the operation speed of FET is reduced.
Japanese Published Patent Applications Nos. Hei.1-225169, Hei.2-105539, Sho.63-52479 and Sho.61-187277 disclose FETs in which the p type buried layer is only disposed directly under the channel layer so that the parasitic gate capacitance is not likely to increase.
However, the FET disclosed in Japanese Published Patent Application No. Hei.1-225169 is not a self-aligned gate FET and includes a recess groove at the center of an operating layer, a gate electrode disposed in the recess groove, and source and drain regions at opposite sides of the gate electrode. In such a structure, since the thickness of channel region is established depending on the depth of recess groove, the threshold voltage varies, resulting in poor uniformity and reproducibility of element characteristics. In addition, since this FET is not a self-aligned gate FET, a mask is required for ion implantation of the source and drain regions to increase the dopant concentrations of these regions in order to improve the element characteristics, i.e. conductivity, so that the manufacturing process is complicated.
In the FET disclosed in Japanese Published Patent Application No. Hei.2-105539, although a large portion of the lower surface of channel layer is covered by a p type buried layer, both side portions thereof are directly in contact with the substrate. Therefore, current leaks into the substrate through these portions, so that the leakage current in the channel region cannot be completely suppressed.
In the FETs disclosed in Japanese Published Patent Applications Nos. Sho.63-52479 and Sho.61-187277, a channel layer is formed at a shallower position in the substrate than the source and drain regions and the upper side surfaces of p type buried layer directly below the channel layer are in contact with the lower side surfaces of source and drain regions, whereby excessive parasitic capacitances are generated.