Power consumption has become an important design challenge in modern integrated circuit (IC) devices, for example, programmable logic devices (PLDs) and standard cell application specific integrated circuits (ASICs). PLDs exist as a well-known type of IC that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure (routing resources). The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. The configuration bitstream may be read from an external memory, conventionally an external integrated circuit memory EEPROM, EPROM, PROM, and the like, though other types of memory may be used. The collective states of the individual memory cells then determine the function of the FPGA.
FIG. 1 is a flow diagram depicting a conventional design process (“CAD process 100”) for an integrated circuit, such as an ASIC or an FPGA. CAD process 100 begins by receiving a design 101. Design 101 represents a circuit design at a schematic or logic level. At step 102, design 101 is synthesized to produce a logical network list (“netlist”) supported by the target device. At step 103, the synthesized design is mapped onto primitive components within the target device (e.g., programmable logic blocks of an FPGA). At step 104, placement for the components of the synthesized and mapped design is determined for the target device. At step 105, interconnects (e.g., signal conductors) are routed within the target device for the placed components. CAD process 100 ends by producing a CAD result 106. Steps 101 through 105 are referred to herein as standard map-place-route (SMPR) process 110.
Performance and frequency requirements translate to a maximum allowable delay for paths traversing routing resources between circuit elements. As such, the conventional design process is “timing-driven” in that SMPR process 110 is optimized in accordance with timing constraints. SMPR process 110, however, does not optimize design 101 for power. Typically, incorporating power optimization in the conventional design process adversely affects the timing performance of the design.
Accordingly, there exists a need in the art for an integrated circuit design process that optimizes power without adversely affecting the timing performance of the design.