1. Field of the Invention
This invention relates to semiconductor device packages. More particularly, this invention relates to semiconductor packages having die pads.
2. Description of the Related Art
Semiconductor device packages provide environmental protection to integrated circuit devices (dies). Such packages typically include at least one semiconductor device (die) having its input/output (I/O) pads electrically connected to a lead frame type substrate or an interposer type substrate, with a molding compound coating the die and at least a portion of the substrate. Typically, the I/O pads on the die are electrically connected to bond sites on the substrate using either a wire bonding, tape bonding, or flip-chip bonding method. The lead frame or interposer substrate transmits electrical signals between the I/O pads and an electrical circuit external to the package.
In semiconductor device packages having a lead frame type substrate, electrical signals are transmitted between at least one die and external circuitry, such as a printed circuit board, by an electrically conductive lead frame. The lead frame includes a plurality of leads, each having an inner lead end and an opposing outer lead end. The inner lead end is electrically connected to the I/O pads on the die, and the outer lead end provides a terminal for connecting to the external circuitry. Where the outer lead end terminates at a face of the package body, the package is known as a “no-lead” or “leadless” package. Examples of well-known no-lead packages include quad flat no-lead (QFN) packages, which have four sets of leads disposed around the perimeter of the bottom of a square package body, and dual flat no-lead (DFN) packages, which have two sets of leads disposed along opposite sides of the bottom of a package body.
In many semiconductor device packages, the die is attached to a portion of the lead frame that serves to support the die and to transfer heat between the die and an environment external to the package. This portion of the lead frame is known as a die pad (also known as a die pad, die paddle, heat spreader, or heat sink). In certain semiconductor device packages, the die pad is exposed at a surface of the package. With the die pad exposed, heat transfer between the die and the environment external to the package is enhanced. However, because the die pad is exposed at a surface of the package, there is no molding compound to support the exposed surface of the die pad, and steps must be taken to ensure that the die pad does not become dislodged from the package.
One method to prevent the die pad from being dislodged from the package is described in U.S. Pat. No. 6,143,981, which is incorporated by reference herein in its entirety. The '981 patent is directed to a package wherein the die pad and the leads have side surfaces that include reentrant portions and asperities to engage the encapsulant. The reentrant positions and asperities enhance the connection of the die pad and tabs to the plastic encapsulating material.
Another method to prevent the die pad from being dislodged from the package is described in U.S. Pat. No. 6,281,568, which is incorporated by reference herein in its entirety. The '568 patent is directed to a package wherein the lower surfaces of the die pad and leads are provided with a stepped profile by an etching step that etches partially through the thickness of a peripheral portion of the die pad, and also etches partially through the thickness of portions of the leads. Encapsulant material fills in beneath the recessed, substantially horizontal surfaces of the die pad and leads formed by the above-described etching step, and thereby prevents the die pad and leads from being pulled vertically from the package body.
While the solutions described in the '981 and '568 patents are acceptable for certain applications, they are not without their deficiencies. For example, the half-etched steps or reentrant portions on the side surfaces of the die pad may not be sufficiently robust to retain the die pad within the package under certain conditions or for certain applications. In another example, as described in U.S. Pat. No. 6,525,406, which is incorporated by reference herein in its entirety, the size or length of this half-etched step or reentrant portion is insufficient to thoroughly prevent moisture from permeating into the vicinity of the semiconductor chip. Thus, much moisture may be collected in the vicinity of the semiconductor chip under the high temperature conditions that exist during the operation of a semiconductor chip. The moisture may then spread widely over the inside of the semiconductor package, resulting in cracking of the semiconductor package or causing protuberances to form on the surface of the semiconductor package.
To cure this deficiency, the '406 patent proposes that a perimeter of both an upper and lower surface of the die pad be half-etched to increase the moisture-permeation path of the finished package, where the moisture-permeation path between the semiconductor chip and the bottom surface of the package along the interface of the die pad and molding compound. While this solution is effective in increasing the moisture-permeation path of the finished package, half-etching the perimeter of both the upper and lower surface of the die pad results in a very thin protrusion (relative to the thickness of the die pad) extending around the perimeter of the die pad, which may break during fabrication or use of the package.
Thus, there remains a need for a package having an exposed die pad that is resistant to being dislodged from the package.