Digital addition is a fundamental operation of processors and digital computer systems, not only to provide basic addition functions but also to provide many other logical operations. Addition and other arithmetic operations are generally performed by an arithmetic logic unit (ALU) contained with the computer's processor unit.
Additionally, high-performance processors may use a variety of memory management techniques to map a logical address to a physical address space. An address generation unit (AGU) is a component of a memory management block and may be used to compute an effective address of the location being addressed in memory.
Integer execution cores in processors may use high-performance adder cores to perform ALU/AGU operations in a signal clock cycle. The adder cores may be implemented using a high-fanout, dense carry-merge tree structure. This may result in high power consumption and high interconnect complexity. Further, the presence of multiple ALUs/AGUs in the execution core may result in a large layout footprint and hotspots on the die.