1. Field of the Invention
The present invention generally relates to a frequency dividing circuit and, more particularly, to a frequency dividing circuit having a frequency dividing ratio which is a rational number smaller than 1. The present invention is also concerned with a frequency dividing method and a telephone terminal device which employ the frequency dividing circuit.
2. Description of the Related Art
A conventional frequency dividing circuit having a fractional frequency dividing ratio, i.e., a rational number smaller than 1, incorporates an oscillating circuit. Such an oscillating circuit employs a PLL (Phase Lock Loop) which uses, as a comparative frequency, the frequency obtained by dividing a base clock frequency by the denominator of the frequency dividing ratio. Known also is a frequency dividing circuit having a counter for receiving a base clock signal and a logical circuit or a storage device which receives the output from the counter so as to select the clock pulses to be delivered from among the base clock pulses.
A description will be given of the conventional frequency dividing circuit which employs PLL, with specific reference to FIG. 6. The circuit shown in FIG. 6 is designed to produce, upon receipt of input pulses of a frequency f.sub.0, output pulses at a fractional frequency dividing ratio of N.sub.2 /N.sub.1. The circuit has the following components: a counter 41 which divides the input frequency f.sub.0 by the denominator N.sub.1 of the frequency dividing ratio, i.e., multiplies the same by 1/N.sub.1, to determine the quotient f.sub.0 /N.sub.1 ; a phase comparator 42 which performs phase comparison by using the quotient f.sub.0 /N.sub.1 as the comparative frequency; a low-pass filter (LPF) which passes the output from the phase comparator 42; a voltage-controlled oscillator (VCO) which oscillates at a frequency corresponding to the output voltage derived from the LPF 43; and a counter 45 which divides the output oscillation pulses of the VCO 44 by the numerator N.sub.2 of the frequency dividing ratio.
Representing the oscillation frequency of the VCO 44 by f.sub.1, the quotient f.sub.1 /N.sub.2 produced by the counter 45 is delivered to the phase comparator 42 which performs phase comparison between the quotient f.sub.1 /N.sub.2 and the quotient f.sub.0 /N.sub.1 and produces a voltage corresponding to the phase differential. This voltage is delivered to the VCO 44, so that the VCO oscillates at a frequency corresponding to this voltage. In this system, the two inputs which are input to the phase comparator 42 are made to progressively converge into two signals which have an equal frequency with a constant phase differential therebetween. Consequently, the condition of f.sub.0 /N.sub.1 =f.sub.1 /N.sub.2 is established to provide the output frequency f.sub.1 which is given by f.sub.1 =f.sub.0 N.sub.2 /N.sub.1, whereby clock pulses of the frequency f.sub.1, which is the result of frequency-division at the fractional frequency-dividing ratio of N.sub.2 /N.sub.1, is obtained at the output terminal of the VCO 44.
This frequency dividing circuit, which incorporates the oscillation circuit employing PLL, has to deal with an analog voltage corresponding to the phase differential, so that the whole circuit inevitably incorporates both analog and digital circuits, making it difficult to construct the whole circuit in the form of an integrated circuit (IC). As a consequence, the scale of the circuit is enlarged and the power consumption is increased. Another problem is that a comparatively long time is required until the clock frequency is stabilized, due to characteristics of the automatic control.
The later-mentioned type of frequency dividing circuit, which relies on the combination of a counter with a logical circuit or a storage device, can be constructed purely digitally and, hence, contributes to miniaturization of the circuit through circuit integration and also to reduction in power consumption. This type of frequency dividing circuit, however, is still unsatisfactory in that it cannot fully meet the requirements of performance posed by current electronic devices.