As computers and computer processors increase in performance, memory access performance becomes a significant bottleneck on overall system performance. The interface technology utilized to communicate data between a memory device and memory controller or other form of application device in particular can be a significant source of such a bottleneck.
For dynamic random access memory (DRAM) devices, which are commonly used as the main working memory for a computer, various interconnect technologies have been developed over the years. One such interconnect technology is used for synchronous DRAMs, or SDRAMs, which utilize a form of source synchronous interface, where the source of data during a memory transfer is relied upon to provide a clock signal, often referred to as a data strobe signal, that is used by a target for the data to capture such data as it is being transferred over a data line to the target. In particular, the capture of data on a data line is typically gated by the rising and/or falling edge of a data strobe signal, e.g., so that the value stored on a data line when the data strobe signal transitions from low to high (or visa-versa) will be latched into a data latch in the target.
Thus, assuming a memory controller coupled to an SDRAM is attempting to read data from the SDRAM, the SDRAM, as the source of the data, supplies data over one or more data lines, coupled with a data strobe signal on a separate line that is used by the memory controller to capture that data. Conversely, where a write to the SDRAM is being performed, the memory controller functions as the source of the data, and provides the data strobe signal to the SDRAM along with the data over the data lines.
A significant advantage to a source synchronous interface such as is used with SDRAM's is found in high frequency applications, as the delays inherent in signal transmission, e.g., due to transistor switching delays, transmission line propagation delays, etc., are comparatively greater at faster operating speeds, so having the same device driving the data and data strobe lines during a data transfer minimizes any misalignment between the data and data strobe lines (also referred to as skew).
Typically, to minimize the number of interconnections in an SDRAM memory interface, bidirectional transmission lines are utilized to handle the data and data strobe signals. Thus, during a read operation, the SDRAM drives the data and data strobe lines, while during a write operation, the memory controller drives these lines. The bidirectionality of the data and data strobe lines, however, can raise significant data integrity and reliability concerns.
In particular, it is often difficult to manage the control over a data strobe line to ensure that an appropriate data strobe signal is driven at the appropriate times and by the appropriate device, and without any undesired transitions, or “glitches” on the line. An unintended spike on a data strobe line, for example, may be interpreted by a latch on either the memory controller or the SDRAM as a data strobe signal transition, and cause whatever value is currently driven on the data line to be latched into that data latch. Such inadvertent latchings may produce data integrity problems, which at the best may reduce performance due to the need to repeat a faulty memory transfer operation, or at the worst may corrupt the data utilized by a data processing system.
Conventionally, to minimize the risk of unintended glitches on a data strobe line, a memory controller is configured to drive the line to a low state whenever a data transfer operation in not occurring. In the alternative, an external pull down resistor may be coupled to the data strobe line to prevent the line from settling to an indeterminate state when undriven.
However, as SDRAM interfaces are driven at higher speeds, control over the data strobe signal becomes a comparatively bigger problem, often resulting in more glitches on the data strobe line. Moreover, some SDRAM interfaces have been extended to support double data rate (DDR) capability, where data is clocked twice per cycle, on the rising and falling edges of the data strobe signal. Thus, the effective speed of a DDR SDRAM is roughly twice that of single data rate SDRAM, so the effects of signal skew are significantly greater.
Moreover, signal skew variations may make it difficult to ensure that only one source drives the data strobe signal at a time, often due to the inability to predict accurately whether a device coupled to the other end of the interface is going to be driving the data strobe signal. In this context, conventional manners of minimizing glitches on a data strobe signal line are inadequate. First, utilizing a memory controller to drive the data strobe line low when the line is not being used presents a significant risk of damaging or destroying the driver circuits on either or both of the memory controller and the SDRAMs. In particular, the sum of the delays present across an interface may be such that one source may attempt to drive the data strobe line while the other source is also attempting to drive the line, or alternatively, while the memory controller is holding the line in a low state to prevent glitches. Should both the memory controller and SDRAM attempt to drive the data strobe line simultaneously at different levels, excessive current would typically be generated across the line, and potentially damage or destroy the driver circuitry on either or both devices.
Second, the use of a pull down resistor is also not compatible with high speed operation, since the additional delays due to additional capacitance, current and wiring associated with the pull down resistor can restrict the maximum operating frequency of the interface.
Between read and write memory operations, a greater concern is typically presented with respect to read operations, since in a SDRAM source synchronous interface, the memory controller typically initiates all memory transfers, and generates the base clock from which the SDRAM operates. Thus, delays from the memory controller to the SDRAM, coupled with delays back to the memory controller when the SDRAM is performing the data transfer (which can vary from device to device due to process variations), make it difficult to predict the total amount of skew that will occur in the system. Nonetheless, similar problems as discussed above may be associated with write operations, as well as in source synchronous interfaces other than SDRAM interfaces.
Therefore, a significant need has arisen in the art for a manner of minimizing the adverse effects of glitches or other indeterminate signals on a data strobe line to prevent inadvertent latching in a source synchronous interface. In particular, a significant need exists for a manner of preventing inadvertent data latching in a DDR SDRAM memory interface.