I. Field of the Invention
The invention generally relates to integrated circuits and in particular to dynamic latching comparators for use therein.
II. Description of the Related Art
Dynamic latching comparators are commonly employed within integrated circuits for comparing a pair of input signals and outputting a signal that is a function of the result of the comparison. Typically, the comparator outputs a signal indicating which of the pair of input signals is greater. Dynamic latching comparators are used, for example, in analog-to-digital (A/D) converters, such as those used within digital wireless telephones.
FIG. 1 illustrates a simple dynamic latching comparator 10. Comparator 10 includes a pair of primary pull-down (nmos) devices 12 (m2) and 14 (m1) having gates connected, respectively, to a pair of input lines 16 and 18. Pull-down device 12 is connected between a node A and ground. Pull-down device 14 is connected between a node B and ground. A pair of capacitors 20 and 22 also connect nodes A and B, respectively, and ground. A pair of cross-coupled pull-up (pmos) devices 24 (m4) and 26 (m3) connect nodes A and B, respectively, to a high voltage source V.sub.DD. A gate of pull-up device 24 is cross-coupled to node B and a gate of pull-up device 26 is cross-coupled to node B.
Dynamic latching comparator 10 operates to determine whether an input signal asserted on input line 16 is greater than an input signal asserted on line 18 as follows. Initially, nodes A and B are both set to V.sub.DD. Upon assertion of suitable input signals to the gates of pull-down devices 12 and 14, device 12 begins to pull down the voltage at node A toward ground while device 14 begins to pull down the voltage at node B toward ground. The rate at which the voltage of each node is pulled down is a function of the voltage level of the input signals asserted on the respective pull-down devices. The relative difference between the voltage of A and B is attributed to the transconductance (gm) of the devices, with a higher voltage causing a quicker reduction of voltage at the node. Hence, assuming the gm's of pull-down devices 12 and 14 are the same, then the pull-down device seeing a higher input voltage will pull-down the voltage at its respective node faster. Thus, a "race" occurs. Eventually, a threshold is reached on one of the nodes causing the corresponding cross-coupled pull-up device to be activated. The threshold occurs when the current in the pull-down device equals that of the corresponding pull-up device, i.e. when the current through device 12 equals that of device 24 or when the current through device 14 equals that of device 26. If node A reaches the threshold first, then pull-up device 26 is activated, otherwise pull-up device 24 is activated first. The pull-up devices are of sufficient size to override the pull-down effect of the corresponding pull-down device and thereby cause the node connected to the drain of the pull-up device to be pulled back up to V.sub.DD. Hence, if node A reaches its respective threshold first, then pull-up device 26 is activated causing node B to be pulled up to V.sub.DD despite the opposing effect of pull-down device 14. Also, with node A connected to the gate of pull-up device 26, pull-up device 26 is thereby prevented from activating. Alternatively, if node B reaches its respective threshold first, then pull-up device 24 is activated causing node A to be pulled up to V.sub.DD despite the opposing effect of pull-down device 12. Also, with node B connected to the gate of pull-up device 24, pull-up device 24 is thereby prevented from activating.
Thus, if the input signal asserted on input line 16 has a lower voltage than that of input line 18, node A is eventually pulled down to ground and node B returns to V.sub.DD. If the input signal asserted on input line 18 has a lower voltage than that of input line 16, node B is eventually pulled down to ground and node A returns to V.sub.DD. Output signal lines, not shown, connected to nodes A and B thereby output a signal representative of whether the input signal along line 16 is lower than that or line 18 or vice versa.
FIG. 2 illustrates a dynamic latching comparator with reset circuitry. As with the comparator of FIG. 1, comparator 110 of FIG. 2 includes a pair of primary pull-down devices 112 (m2) and 114 (m1) cross-coupled to a pair of pull-up devices 124 (m4) and 126 (m3). Input lines 116 and 118 are connected to respective gates of the pull-down devices. Capacitors 120 and 122 are also provided. Additionally, comparator 110 includes reset circuitry including pull-up devices 128 (m6) and 130 (m5) connected in parallel with pull-up devices 124 and 126 between V.sub.DD and nodes A and B, respectively. Gates of pull-up devices 128 and 130 are connected to a reset line 131. The reset circuitry also includes additional devices 132 (m8) and 134 (m7) connected between pull-down devices 112 and 114 and nodes A and B, respectively. These devices operate as switches to prevent current flow. Gates of switch devices 132 and 134 are also connected to reset line 131. The devices of the reset circuitry are sized such that, upon assertion of an active low reset signal on the reset line, the voltage levels of nodes A and B are returned to V.sub.DD despite opposing effects of the other devices of the overall comparator and such that current flow is prevented while the comparator is in the reset state. To prevent current flow after a latch has been achieved but before a reset signal is asserted, yet another pair of switch devices 136 (m10) and 138 (m9) is provided. Switch devices 136 and 138 are connected, respectively, between pull-down device 112 and accompaning switch 132 and pull-down device 114 and accompaning switch 134. Output lines, not shown, may be connected to nodes A and B to output a signal representative of whether the input signal along line 116 is lower than that or line 118 or vice versa.
For most applications, it is desirable to configure the comparator to provide the quickest possible comparison of the input signals, and the various devices of the comparator are sized and positioned accordingly. Additionally, though, it is necessary to ensure that a correct comparison is made despite possible process variations between the devices of the comparator. In this regard, if the pull-down devices connected to the input lines are too small, then process variations between those devices could cause the pull-down device seeing a lower voltage input signal to nevertheless win the aforementioned "race" causing an incorrect output signal to be generated. More specifically, a voltage error (err) or mismatch can occur at the time the latching threshold is reached. The error occurs primarily as a result in current differences between the primary pull-down devices due to variances in gate threshold voltage (vt) and susceptance (B). The voltage error may be derived using the following equations (with the various terms in the equations having their standard definitions in the art): ##EQU1##
To minimize the voltage error and thereby ensure accuracy despite process variations, the pull-down devices connected to the input lines are typically made relatively wide and long. This, however, slows the comparison time. Comparison time is related to the gm between the pull-down devices which is reduced when the pull-down devices are made larger. Moreover, the larger pull-down devices yield a larger input capacitance thereby requiring more power for operation, particularly insofar as driver devices (not shown), used to assert input signals onto the input lines, are concerned. Hence, to overcome process variations, higher overall power is required and the comparison rate is reduced. A slower comparison rate is almost always undesirable, and for many applications, such as A/D converters used in battery-powered wireless telephones, a higher power requirement is particularly disadvantageous.
Hence, it would be highly desirable to provide an improved dynamic latching comparator that achieves a fast comparison rate with relatively low input capacitance and it is to that end that aspects of the invention are primarily directed.