Electrolytic capacitors, such as tantalum capacitors, are traditionally known for their high capacitance value and compactness. Despite the existing compactness of known electrolytic capacitors and electrolytic capacitor arrays, there are constant efforts to reduce the volume and corresponding volumetric efficiency of such electronic components.
Essential components of a conventional electrolytic capacitor include a main capacitor body, an anode wire, and a leadframe all molded together in an encapsulating resin package. The volumetric efficiency of an electrolytic capacitor is typically defined as the ratio of the main capacitor body volume to the volume of the entire molded capacitor package. The anode wire and leadframe of such capacitors form respective positive and negative electrical connections to the capacitor structure. These electrical connections typically extend axially from the capacitor structure, and often take up a significant amount of space inside the capacitor package.
Many known technological endeavors have addressed the desire for tantalum or other types of electrolytic capacitors with improved volumetric efficiency. U.S. Pat. No. 6,400,556 (Masuda et al.) discloses a solid electrolytic capacitor with eliminated redundant space, improved volumetric efficiency and a low profile. U.S. Pat. No. 5,198,968 (Galvagni) concerns a compact surface mount tantalum capacitor with high capacitance per volume.
The prevalent desire to reduce the component size of electrolytic capacitors becomes even more advantageous when such capacitors are employed in circuit board applications. Thus, chip-type electrolytic capacitors, an example of which is disclosed in U.S. Pat. No. 6,017,367 (Nakata), have been designed not only with volumetric performance characteristics in mind, but also such that device mounting to a substrate is facilitated. Such facilitated device mounting is often achieved by configuring both electrical terminations to extend from a selected surface of the capacitor. Examples of this technology can be found in U.S. Pat. No. 4,107,762 (Shirn et al.), U.S. Pat. No. 4,017,773 (Cheseldine) and U.S. Pat. No. 3,789,274 (Pfister).
When both device terminations extend to a selected surface of a chip-type capacitor, it is often desirable to provide such electrical connections in a generally coplanar fashion. A coplanar termination arrangement may facilitate device mounting to a substrate and may also help to maintain uniformity of certain electrical characteristics of the device. U.S. Pat. No. 5,198,968 (Galvagni) discloses a surface mount tantalum capacitor with coplanar terminations. Similarly, U.S. Pat. No. 6,236,561 (Ogino et al.) discloses an exemplary chip type capacitor with exposed anode and cathode portions flush with a surface of the capacitor device such that dual terminations are provided in a generally coplanar arrangement. This particular configuration is also intended to increase capacitor volume.
While examples of various aspects and alternative embodiments are known in the field of electrolytic capacitors, no one design is known that generally encompasses all of the above-referenced and other preferred capacitor characteristics.
The disclosures of foregoing United States patents are hereby fully incorporated into this application for all purposes by reference thereto.