Conventional memory controllers typically first execute a terminate command to end a row access in progress followed by a precharge command to deactivate the row. Alternately, a precharge can end and close the bank altogether. Conventional controllers can also operate with a fixed burst length. A read or a write needs to be executed every so often to sustain the data burst. Conventional controllers execute more than one refresh and make a longer available continuous time for read/write accesses. Furthermore, in order to hide mandatory SDRAM overhead cycles (i.e., precharge, active, refresh) from the transferring master, a first-in-first-out (FIFO) buffer is typically used.
Conventional controllers use memory control logic to keep track of row activation status in each bank to streamline data burst transfers. Read or write commands are executed in a fixed data length basis if explicit termination is not used. At a minimum, opened banks with activated rows are due to be closed with a precharge.
More refresh cycles lead to a longer blackout time on the memory interface for data access. A FIFO with a large depth is needed to accommodate the larger amount of data incurred from the transferring master (which is unconcerned of the blackout time). Implementing a deeper FIFO causes a longer fill and drain time (and longer latency) at the start of a read and at the end of a write, respectively.
If the clock rate on the memory interface is not running at a sufficiently slow clock rate (i.e., being much higher than what is necessary) the memory interface could spend large portion of time waiting for new data or a new request from the transferring master. Each of the shortcomings outlined above can cause frequent command issuance from a memory controller to a SDRAM interface, high idle to payload data transaction time ratio, superfluous hardware logic, deep pipelining flip-flops, fast silicon process requirement, and/or high power consumption.
It would be desirable to implement a method and/or apparatus for paging to a dynamic memory array that takes advantage of the available bandwidth on the memory interface. Such a paging system may reduce unnecessary resource consumption.