1. Field of the Invention
The invention relates to nonvolatile memory, and particularly an EEPROM device suitable for use in programmable logic devices and a method of forming the device.
2. Description of the Related Art
Non-volatile memory devices of the type commonly referred to in the art as EPROM, EEPROM, or Flash EEPROM serve a variety of purposes, and are hence provided in a variety of architectures and circuit structures.
As with many types of integrated circuit devices, some of the main objectives of non-volatile memory device designers are to increase the performance of devices, while decreasing device dimensions and consequently increasing circuit density. Cell designers strive for designs which are reliable, scalable, cost effective to manufacture and able to operate at lower power, in order for manufacturers to compete in the semiconductor industry. EEPROM devices are one such device that must meet these challenges. In some applications, such as flash memory cards, density is at a premium, while in applications such as programmable logic devices (PLD's), reliability is more important and space is at less of a premium. Generally, arrays of individual memory cells are formed on a single substrate and combined with sense and read circuitry, and connected by row-wise and column-wise conductive regions or metallic conductors to allow for array wide bulk program and erase as well as selected bit programming.
Semiconductor process technology has continued to move toward defining smaller device features, and the conventional "stacked gate" EEPROM structure has given way to different cell designs and array architectures, all intended to increase density and reliability in the resulting circuit. In addition, in EEPROM devices used for programmable logic devices, designers strive to reduce power requirements of devices by reducing program and erase voltage requirements.
Conventionally, programmable logic EEPROMS were typically formed by stacked gate devices operating utilizing Fowler-Nordheim tunneling to program and erase the floating gate or in single polysilicon-based cells such as that set forth in U.S. Pat. No. 4,924,278. An alternative to the aforementioned Fowler-Nordheim tunneling-based cell structures is presented in Ranaweera, et al., "Performance Limitations of a Flash EEPROM Cell, Programmed With Zener Induced Hot Electrons," University of Toronto Department of Electrical Engineering (1997). Discussed therein is a flash EEPROM cell which accomplishes programming and erase by establishing a reverse breakdown condition at the drain/substrate junction, generating hot electrons which are then injected into the floating gate to program the cell. To program the flash ZEEPROM cell, the PN junction is reverse-biased to create an electric field of approximately 10.sup.6 volt/cm. and generate energetic hot electrons independent of the channel length. The P+ region adjacent to the drain enhances this generation. A low junction breakdown voltage can be used for programming by optimizing the PN junction depth and profiles.
A structure and method for programming an avalanche injection cell is detailed in co-pending U.S. patent application Ser. No. 08/871,589, inventors Hao Fang, et al., filed Jul. 24, 1998 and assigned to the assignee of the present application.
In Fang, et al. the non-volatile memory cell is formed of a P substrate having embedded therein an N+ source region, an N-type diffused drain region, a floating gate capacitively coupled to the P substrate through a tunnel oxide, or other gate dielectric such as nitride oxide; and a control gate coupled capacitively to the floating gate through an oxide/nitride/oxide, or other type of inter polysilicon dielectric, film. The diffused region is formed of a shallowly diffused but heavily doped N-type junction, while the source region is formed of a deeply diffused but lightly doped N junction.
To program the cell, electron injection is effected from the drain side. The programming operation is accomplished by applying +3 volts on the drain and -6 volts on the P substrate so as to shift upwardly the threshold voltage V.sub.t by 4 volts in approximately 0.002 seconds. To erase, holes are injected from the drain side by applying +6.5 volts on the drain and -3 volts on the P substrate so as to shift down with the voltage threshold V.sub.t by 4 volts.
The Fang, et al. application also teaches a single polysilicon layer embodiment wherein the stacked control gate is replaced with a diffusion region. FIG. 1 represents a schematic depiction of such embodiment. The control gate can be switched between 0 volts and V.sub.cc to select and de-select the cell during the read period and between V.sub.jb and 0 volts to program and erase the cells as set forth above. A select transistor is added at the source side to enable a fast read of the memory cell. Cell size is decreased in comparison to conventional single poly memory cells for programmable logic devices.
Even with the scaling advantages presented by the ZEEPROM-type cells, designers constantly seek to improve scalability, performance and cost advantages of cells.
Each of the aforementioned configurations presents advantages and disadvantages when used in particular applications. Nevertheless, improvements in both the structure of individual cells and the manner in which they are connected together will result in more reliable, stable, faster, and lower power devices which can be programmed and erased at lower voltages.