1. Field of the Invention
The present invention relates to the field of integrated circuit design, specifically to redundancy circuits used to increase the production yield of non-volatile memory integrated circuits.
2. Prior Art
Particle defects due to fabrication environments can cause non-volatile memory integrated circuits, especially those with high density memory arrays, to fail. As a result, a yield loss in final production test is realized, causing the final satisfactory product to cost substantially more so as to cover the cost of the faulty parts. To help increase the yield, a technique commonly known as redundancy repair (row, column, or block), is used to avoid use of the failed memory portion in favor of a corresponding redundant memory portion included on the integrated circuit just for such purposes, should it be needed.
Redundancy circuits typically store the addresses of the failed memory portion in some form of storage, and in use, compare the incoming addresses versus the stored redundancy addresses for a match. If a match is found, the redundancy array is enabled and the main array is disabled. An enable fuse is typically included to enable or disable the redundancy addresses. Some conventional implementations use a resistor fuse as a programmable element to store the failed addresses. The fuse is blown by applying a high current through the fuse by a test enabling circuit. Such a fuse is one-time programmable only. Since the current required to blow the fuse is normally high, the transfer switch has to be large, and requires a corresponding large chip area.
Other implementations use EPROM technology (erasable programmable read-only memory). However, as implemented, an EPROM fuse is also one-time programmable. Further, an EPROM requires complicated shielding over the fuse after programming in order to retain the programming charge. Other implementations use EEPROM (electrically erasable programmable read only memory) in an inverter mode (as commonly known), i.e., the cell in the read mode acts as a current sink for some loading elements such as a PMOS, NMOS, or a resistor. The device gate is typically held at 2 V and its source at ground, with its drain coupled to the load. The voltage at the loading element is the output of the memory cell.
Prior art implementations for a memory cell row repair normally include a separate redundancy row decoder and an enable/disable fuse for each redundancy row. Prior art implementations for the row repair also normally include a redundancy row decoder which is different from the regular row decoder. Further, prior art implementations also require a separate high voltage decoder for programming each fuse element. All these require additional circuits and added complexity to achieve the desired result.
In prior art U.S. Pat. No. 4,617,651 by W. Ip and G. Perlegos and U.S. Pat. No. 4,538,245 by G. Smarandolu and G. Perlegos, a redundancy disable/enable circuit is required for each redundant row. In the present invention, out-of-bound addressing is used to self enable a redundant row, thereby eliminating the need for a redundant disable/enable circuit. Moreover, in both the '651 and '245 patents, the redundancy element is a one time programmable fuse. However, the EEPROM fuse in the present invention enables the redundancy to be programmable many times and eliminates the need for high current devices required to burn the one time programmable fuse. Finally, in the '651 and '245 patents, a separate redundancy programming circuit is required whereas in the present invention, the programming circuit is shared with the normal programming circuit through the use of column switches.