Schematics of two typical static random access memory (SRAM) are shown in FIGS. 1A and 1B. The cell in FIG. 1A is called a six transistor (6T) SRAM cell and comprises a pair of cross-coupled inverters to store a data bit state and pair of pass transistors to read and write a data bit between the cross-coupled inverters and a pair of bitlines. The bus which connects the pass transistor gates is called a wordline. To access a particular cell in an array, for reading or writing, the wordline connected to its pass transistor gates is activated to turn on the pass transistors.
The cell in FIG. 1B is an eight transistor (8T) SRAM cell and comprises a pair of cross-coupled inverters to store a data bit state and a pair of two transistors in series between the output nodes of the cross-coupled inverters and a pair of bitlines. The two transistors in series between the output of an inverter and a bitline are also called an X-pass transistor and a Y-pass transistor. The X-pass transistors have their gates connected to a row select bus running in the X-direction called an X-address drive and the Y-pass transistors have their gates connected to a column select bus called a Y-address drive running in the Y-direction. To access a cell in an array, for reading or writing, both X-address and Y-address drives must be turned ON.
DC characteristics of a static random access memory (SRAM) cell are determined by three parameters--read current, bitline write voltage (i.e. trip voltage), and static noise margin. The static noise margin reflects upon the cell stability against noise in the circuit during a read operation. A relatively high noise margin is a desired feature of a static random access memory cell. However, for low voltage/power devices with a supply voltage of typically 1 volt or below, obtaining a good static noise margin is difficult because the threshold voltages of the transistors within a cell are kept low to maintain a certain level of drive current for the transistors.
The static noise margin can be increased by increasing the beta ratio of a cell. The beta ratio for a 6T cell is defined as the ratio of the drive currents for the driver (pull-down) transistor to that for the pass transistor when they have the same threshold voltage. For the 8T cell, the beta ratio is defined as the ratio of the drive current for the driver transistor to that for the series of combination of the X-pass and Y-pass transistors. For the 6T cell, the beta ratio is also the same as the width ratio of the driver and the pass transistors if they have the same gate length and threshold voltage.
A disadvantage of a high beta ratio is that it is difficult to write into a cell because an increase in the beta ratio lowers the bitline write voltage for the cell. This problem becomes more severe as the supply voltage Vcc is reduced for low voltage and or low power applications. Typically, a voltage below 1.5 V is considered a low voltage implementation. Therefore, it is desirable to increase the beta ratio of the memory cell without adversely affecting its write capability.