Memory devices (which are sometimes referred to herein as “memories”) are typically provided as internal, semiconductor, integrated circuits in computers or other electronic systems. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming of a charge storage structure, such as floating gates or trapping layers or other physical phenomena, determine the data state of each cell. Common electronic systems that utilize flash memory devices include, but are not limited to, personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, cellular telephones, and removable memory modules, and the uses for flash memory continue to expand.
Flash memory typically utilizes one of two basic architectures known as NOR flash and NAND flash. The designation is derived from the logic used to read the devices. In NOR flash architecture, a string of memory cells is coupled in parallel with each memory cell coupled to a data line, such as those typically referred to as digit (e.g., bit) lines. In NAND flash architecture, a string of memory cells is coupled in series with only the first memory cell of the string coupled to a bit line.
As the performance and complexity of electronic systems increase, the requirement for additional memory in a system also increases. However, in order to continue to reduce the costs of the system, the parts count must be kept to a minimum. This can be accomplished by increasing the memory density of an integrated circuit by using such technologies as multilevel cells (MLC). For example, MLC NAND flash memory is a very cost effective non-volatile memory.
A prior art double machine controller 100 is shown in FIG. 1. The controller 100 has a controller 102 for conventional control flow instructions (e.g., greater than 16 bit instructions), and a controller 104 for conventional macro-sequencer instructions (e.g., 16 bit instructions). Referring also to FIG. 2, prior art general purpose flow instructions are shown at 202, and prior art macro-sequencer instructions are shown at 204. Flow control instructions are conventional. Each instruction has an operational-code (op-code) that identifies an instruction and some argument. This allows flow control instructions including jumps, calls, return operation and conventional register-to register data moves or arithmetical operators. Macro-sequencer instructions (referred to macro-sequencer) are not conventional instructions. Instead, macro-sequencer instructions are referred to as “no-opcode” or “zero-code” instruction sets, in the sense that each instruction of a macro-sequencer instruction set is couple of address and data. “No op-code” allows just value-to-register instruction and delay. No control flow is allowed in macro-sequencer instruction sets.
A separate macro-sequencer controller 104 is used because it is more compact in terms of a total size of program instructions (e.g., silicon area on a PROM). 16 bit instructions are not used for control flow instructions because the control registers 106 spaced about a die are written as couples of 8 bits comprising an address, and 8 bits of data, for example the sequence of register write operations 204 shown in FIG. 2. Therefore, a 16 bit sequencer is not suitable for general purpose instructions that often exceed 16 bits, and are not in the proper format for a 16 bit sequencer, for example the if else instruction 202 shown in FIG. 2.
Memories typically operate internally using a plurality of registers such as registers 106 for buffering instructions to be executed on the memory array. A control process, operated by a controller 100, is often used to control memory operations. These operations are usually called algorithms by people skilled in the art. Typical registers have 16 bits, and use 8 bits for data and 8 bits for an address. A macro is defined as a sequence of 16 bit words. Controller instruction sets typically contain different types of instructions. These instructions may be broken into two sets of instructions, a first control flow set of instructions (executed at 102), and a second macro sequencer set of instructions (executed at 104). An instruction set that controls execution flow (102) is often larger than 16 bits, so macros are executed by a dedicated 16 bit machine often referred to as a macro sequencer (104). The controller calls macros for execution through a master/slave protocol (108). The double machine architecture occupies valuable die space on an integrated circuit.
Control flow instruction sets can be complicated, using, for example, nested commands and the like. Coding for control flow instruction sets especially results in fragmented microcode. Typical macro sequencers are limited in operation. For example, conditional branching is not done in current macro sequencers. For the reasons stated above and for other reasons that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for merging the two instruction sets and providing a single machine controller.