1. Field of Invention
The present invention relates to a method for preparing a chip structure, specifically to a method for preparing a germanium-on-insulator (GOI) chip structure.
2. Description of Related Arts
With rapid development of silicon-based large scale integrated circuit technologies, performances of bulk silicon complementary metal-oxide-semiconductor (CMOS) devices are gradually approaching physical limits of silicon materials, and the further improving of the performances of the bulk silicon CMOS devices along a direction guided by Moore's Law will face growing investments and market risks. The semiconductor industry is a market quite sensitive to a ratio of quality to price of the product. How to constantly improve the performances of the silicon-based devices on the basis of an existing very large scale integration (VLSL) technique without a significant increase in investment has become a common problem in the industry. Exploration of new materials and new techniques is absolutely an important idea and research direction for solving the problem.
The GOI is the latest achievement in the development of the field of advanced silicon-based substrate materials, and it is of great importance for the high-performance CMOS integrated circuit (IC), the photodetector, and the solar cell. The GOI can be used as a photodetector GOI (the efficiency of absorbing light with a wavelength of 850 nm by germanium is 70 times of that of silicon), and can also be used to make a high-speed transistor. A conversion speed of a transistor based on germanium is 3 to 4 times higher than that of the silicon. Germanium metal is capable of improving electron mobility of a material, so that the germanium material has a good perspective for high-speed logic IC applications in the future. The GOI is used to manufacture a high-speed photodetector (running at 30 GHz), so that the high-speed photodetector is theoretically applicable to detection of a signal with a speed higher than 50 Gb/sec, and optical interconnection on a chip is much closer to the reality. The GOI technology can be compatible with a silicon CMOS technique. The germanium can be selectively placed in a region where the photodetector is located, so that the new detector is compatible with a standard microchip technology. The compatibility makes it possible to integrate an optoelectronic circuit on the same chip, such as a microprocessor and other electronic devices. Currently, the GOI technology is mainly focused in the following several fields: GOI high-speed CMOS device, high-frequency CMOS device, photodetector and solar cell. A few decades ago, people knew that the germanium had a speed advantage compared to the silicon; however, the instability of a germanium oxide layer makes it feasible to make a MOS device. Today, a new generation of a high-K dielectric deposition technology and these new GOI substrates endow device manufactured with more flexibility in the use of the germanium, thereby avoiding a problem of MOS gate oxide. A bulk germanium wafer is heavier than the silicon, and is fragile. The GOI can help to overcome these problems, and makes a germanium metal-oxide-semiconductor field effect transistor (MOSFET) technology be compatible with a silicon processing apparatus. An epitaxy method applied to a germanium donor can easily change the germanium donor to 300 mm in an equal ratio, but higher crystal defects. The germanium surface processing is a quite difficult task, for the reason that a typical silicon cleaning solution may corrode the surface of the germanium, making a rough surface. Although it has been confirmed that a silicon processing apparatus can be used to process the GOI and a 0.15-micron device has already been made successfully, an Ion/Ioff ratio of the MOSFET is undesirable and the mobility also needs to be further improved. The quality of the MOSFET on the germanium surface is quite a problem. Besides that, due to the small forbidden band gap (0.66 eV) of the germanium, the germanium device undergoes a fatal defect of large leakage current which also seriously hinders a wider application of a germanium MOS device, so that the GOI technology should solve impacts of a leakage of narrow band gap bond of germanium and band-to-band tuning. Like the SOI which solves many shortages of bulk silicon in a semiconductor device, the GOI, as a candidate material, is also a good solution to the defects of Ge materials. In order to get low leakage current and the MOS device with better performance, the GOI has been brought into focus. Some research structures and companies have prepared out a GOI structure by using many methods, for example, the Big Three, Soitec, IMEC, and Umicore, in the European semiconductor field announce a joint development of the GOI technology. Umicore focuses on research and development of 8 and 12-inch single crystal Ge chips, Soitec researches and develops the GOI chip by using a SMART CUT technique, and IMEC focuses on the research of the preparation of the high-performance CMOS circuit applied to a process of 45 nanometers or below by a Ge-based technique. Silicon Genesis also announces that they are working on the research and production of the GOI wafer, IBM announces the development of a high-speed photodetector based on a newly developed GOI technology, in which the method for manufacturing the GOI of Silicon Genesis and IBM is: growing the germanium directly on a quite thin SOI. However, currently, they all have some imitations on their own. The Ge condensation technology is one of the most promising technology. The previous Ge condensation technology used epitaxial SiGe on the SOI substrate, which may introduce a high dislocation density (≧107), seriously affecting the final quality of the GOI and the performance of the later device. From the formation mechanism of a threading dislocation, at the beginning of the concentration, a misfit dislocation of a SiGe/Si interface descends to a SiGe on insulator (SGOI)/buried oxide (BOX) interface, and then after the further concentration, the misfit dislocation threads upwards, forming the threading dislocation.
In view of this, how to propose a preparation method having an easy technique and capable of reducing a GOI threading dislocation destiny has become a problem to be solved currently.