The basic function of a modern digital exchange is to connect the exchange input port to the correct output port, in other words, to connect an incoming call on a specific incoming circuit to an outgoing call on a specific outgoing circuit. The core of the system is the exchange control, whose functions have been distributed over a plurality of units, each carrying out its own task. As examples of such units are a unit controlling the switching matrix, signaling units carrying out different types of signaling and supervision at the input and output sides, a unit collecting call-specific charging data, a unit gathering statistics, etc. Each unit comprises at least one central processing unit CPU, a bus, and memory. Thus, each unit actually constitutes a computer.
In addition, the exchange comprises an Operation and Maintenance Unit (O&M), which takes care of the maintenance of the system.
Apart from the type described above, the telecommunication network nodes may also be ATM nodes (Asynchronous Transfer Mode). ATM is a connection-oriented, packet switched, general purpose, and scalable data transmission method in which information is sent in fixed-length cells. The cell consists of a five-byte-long header and a 48-byte-long information section. The header fields include a Virtual Path Indicator (VPI) and a Virtual Channel Indicator (VCI). At the ATM switch, the cells are transferred from a logical input channel to one or more logical output channels. The logical channel consists of the number of the physical link (e.g. optical cable) and the channel identifier on this link, in other words the VPI/VCI information. One physical transfer medium, such as an optical cable, may comprise a plurality of virtual paths VP, and each virtual path comprises a plurality of virtual channels VC.
Because the cells are of a fixed length, the connections at ATM switches can be performed at hardware level on the basis of the cell header, and therefore at very high speed. Cells belonging to different connections are distinguished from one another on the basis of the virtual path (VPI) and the virtual channel (VCI) identifier. As the connection is set up, a fixed route is determined through the network, i.e. a virtual link along which the cells of the connection are routed. Based on the VPI/VCI values, the cells are switched at the network nodes. The VPI/VCI values are transmission link specific and consequently usually change in connection with switching at the VP or VC level. At the end of the data transfer, the connection is released.
FIG. 1 illustrates a simplified ATM switch. It consists of input stages and output stages, into which the physical input and output lines are connected, and of a switching fabric. The physical line can consist of any suitable medium, of an optical fiber as shown in the figure, of a twisted pair, of a coaxial cable, for example. As an example the medium herein is the optical fiber. The input and output stages constitute the external network interfaces. The interface type may be either UNI (User Network Interface) or NNI (Network Node Interface). The input stage reads the address information, i.e. the VPI and VCI identifiers, of the cell received from the input link and converts them into new VPI/VCI values which the output stage inserts into the header of the cell sent to the output link.
The software of the switch is distributed over functional blocks, processor units 1, . . . N., handled by computers. The computers are nearly always of the embedded type, meaning that display units and other peripheral devices are not required.
FIG. 2 is a more detailed illustration of an ATM switch. A cell, either of the UNI or NNI type, from optical fibre 20 is received at circuit 21 of the PHY layer (Physical Layer) that terminates the line. The PHY carries out transmission system specific tasks at the bit level and is responsible for cell adaptation to each of the transmission systems, as well as for cell masking, cell header error checks, and cell rate justification.
From circuit 21 of the PHY layer, the cell passes to circuit 22 of the ATM layer. The ATM layer only deals with the cell header, its tasks being cell switching, multiplexing and demultiplexing, and cell header generation and removal. Above the ATM layer, the AAL (ATM Adaptation Layer) fragments the higher layer frames and reassembles them at the other end, in other words, carries out the SAR (Segmentation and Re-assembly) function.
Circuit 22 of the ATM layer sends the cell to the input buffer of ATM switching fabric 23. From there, the fabric connects it to the other side of the fabric, to output port 25. At the output port, the VPI/VCI value in the cell address field is examined, and the cell is transmitted to the correct virtual channel.
The processor units in FIG. 1 must be able to negotiate with each other. The most common way is to set up a dedicated common message bus, into which the units are connected via a bus adapter.
FIG. 3 depicts another of arranging the routing of the internal-traffic of cells through the ATM switching fabric. A group of processor units, here Processor Unit 1, . . . , Processor Unit N, are connected to multiplexer 31, whereas a second group of units, Processor Unit A1, . . . , Processor Unit An, are connected to multiplexer 32. A third group of units, Processor Unit B1, . . . , Processor Unit Bn, are connected to multiplexer 33. A multiplexer multiplexes ATM cells received from an attached group of units to an input port of ATM switching fabric 34, which routes the cells through the fabric to destination output ports.
For example, let us consider a case when processor unit 1 is sending cells to processor unit B1 and processor unit N is sending cells to processor unit 2. Multiplexer 31 provides the cells with the proper VPI/VCI addresses and multiplexes the cells to input port 0 of the switching fabric. The switching fabric returns the cells addressed to processor unit N to output port 0. Demultiplexer 31 routes the cells further to processor unit N.
Switching matrix 34 routes the cells addressed to processor unit B1 to output port 1, whereupon multiplexer 33, which is connected to that port, routes the cells to target processor unit B1.
Still referring to FIG. 3, it is advantageous to form a group of processor units from the units having similar processor types. Hence, processors of units from 1 to N could be general purpose microprocessors, whereas processors of units from B1 to Bn could be signal processors.
Operation and maintenance unit 35 is also connected through multiplexer 31 to port 0 of ATM switching fabric 34. The task of the operation and maintenance unit is to ensure that the functional units of the exchange are operating properly. In addition, the unit acts as an input and output device through which the operator can update software and input instructions to the software. For those purposes there are bi-directional control connections between the operation and maintenance unit 35 and the processor units.
The operation and maintenance unit plays an especially important role when commissioning the exchange. After the power to various units of the exchange has been switched on, the operation and maintenance unit ensures that the exchange starts to operate properly.
A problem in the prior art exchanges switching packets of a fixed length is how to form control connections between the operation and maintenance unit and the processor units from the time the power is switched on. These connections are needed for downloading the program code from the operation and maintenance unit to the processor units.
FIG. 4 illustrates this problem. In reality, the problem is reduced to that of how to establish a connection between each of the multiplexers and the operation and maintenance unit. A software application runs in each of the multplexor units 1-N of the exchange. Accordingly, a plurality of software applications runs in operation and maintenance unit 41. In order for the operation and maintenance unit to be able to control the setting-up of the processor units, a logical channel for communication through the switching fabric is needed between operation and maintenance unit 41 and each of the multiplexers. After the logical channels have been created, the applications in processor units (see FIG. 3) can communicate with the applications in the operation and maintenance unit for further configuration instructions during the setting-up process. The applications running in the processor units are directly connected to the operation and maintenance unit via the AAL/ATM and PHY layers.
Unfortunately, the multiplexer units can not begin creating logical channels because they do not know to which port of the switching fabric they are physically connected. Due to the lack of logical channels, processor units can not receive a program code from the operation and maintenance unit.
A prior art solution for the problem is that after switching the power on, the operator enters information about the connection port manually into each of the multiplexer units. In addition, software programs including configuration information are loaded manually into the memories of the processor units. Alternatively, all the program code which is necessary for powering up the processor units may be stored in the flash memory of the unit. However, this solution is not acceptable because upgrading a program code is difficult. Hence, only a minimum amount of the program code is stored in the flash memory, the rest of the code is retrieved from the operation and maintenance unit.
A drawback of the known method is that entering information about connection ports manually to several multiplexer units and loading the program code into the units are a time consuming and error-prone operation.