The Cell processor eXtreme Data Range (XDR) memory interface developed by SONY-Toshiba-IBM (STI) has two 32 bit-serial buses, each of which performs high-speed signal transmission by 3.2 Gbps. The interface used to connect between the Cells and between the Cell and the I/O Controller (FlexIO) (input/output) is connected by a bundle of 5 Gbps buses, which is much faster than the 32 bit-serial buses. Therefore, a Cell mounted system is adapted to perform calibration (Initialization) between the Cell and XDR and between the Cell and the I/O Controller in booting.
FIG. 1 depicts a typical block diagram of this cell system with two Cells (120). The FlexIO interface (160) connects between the Cells and between the Cell and the I/O Controller (130). The cell system has a system controller (110) which is connected with the I/O Controller/Cell via the SPI interface (140) and several external interfaces (150). When this cell system boots, it adjusts the clock to timely read data by calibrating the XDR and the FlexIO interface. With that calibration, the system slightly changes the clock position against the data eye to adjust the timing to read the bit-serially transmitted data. The Cell system performs the adjustment on both of the XDR interface and the FlexIO interface in boot up.
Because the clock position for the data depends on the environmental temperature, the XDR interface in the Cell has a correcting mechanism that sends out a simple version of the calibration at certain intervals during the operation. The “FlexIO” interface is less influenced by the temperature than the XDR interface is. Thus, the “FlexIO” interface does not have such a simple correcting mechanism that works during the operation. Some electronic equipment such PlayStation 3 (SONY) or Cell Blade (QS20) developed by IBM are normally used in a rather stable environmental temperature and does not require to correct the FlexIO after the system boot up. When the Cell is used for embedded purposes, especially when environmental temperature significantly changes during the operation, the FlexIO needs correction. The current Cell system has no means for correcting the FlexIO during the operation besides the boot up.
This embodiment addresses the problem of calibrating the interface clock in a multi-cell system between the cell processors and I/O controllers without rebooting and this multi-cell processor is used as an example to better describe this calibration method.