Memory devices are used to store information in a number of applications for this purpose, each memory device comprises a plurality of memory cells, each one for storing one or more logic values (such as one bit). For example, non-volatile memory devices are used to store information that has to be retained even when the memory devices are not powered. Generally, each memory cell is based on a floating gate MOS transistor, which has a threshold voltage that may be set (according to an electric charge in its floating gate) to different levels representing corresponding logic values. Particularly, in Few Time Programmable, or FTP (non-volatile) memory devices (also known as Multiple Time Programmable, or MTP, or Cost-effective memory devices) the memory cells are manufactured without a dedicated oxide layer for their floating gates (so as to allow the use of standard CMOS production processes at relatively low cost); this makes the FTP memory devices very attractive for use as embedded memories of small capacity (such as up to some Kbytes) in CMOS devices (for example, for storing corresponding booting information).
The memory devices may be subject to faults during a reading of their memory cells, which faults may cause corresponding errors in the logic values that are read. For example, in the FTP memory devices the faults may be due to a relatively poor quality of the oxide layer of the floating gates of the memory cells; in any case, a fault rate of the FTP memory devices significantly increases with their aging (because of retention phenomena of electric change in the floating gates of its memory cells).
Several techniques are known in the art for improving a reliability of the memory devices. Particularly, the memory devices may have different architectures. For example, in a single-ended architecture each memory cell storing one bit is read by comparing its state with a corresponding reference. On the other hand, in a differential architecture the memory cells are organized in pairs. Each pair of memory cells (referred to as direct memory cell and complementary memory cell) defines a memory location for one bit (represented by the actual bit stored in the direct memory cell and its complement stored in the complementary memory cell), which memory location is read by comparing the states of its memory cells between them. The differential architecture increases the reliability of the memory devices, since it substantially doubles a reading margin of its memory cells (at the cost of a reduced capacity thereof).
In addition, Error Correction Codes, or ECC, may be used. In this case, (redundancy) control information is added to the (actual) payload information of interest; for example, one or more control bits (also called check bits) of the control information are added to each data word (formed by one or more bits of the payload information), thereby creating a code word that is stored in the memory device. The control information is used for detecting and correcting (if possible) some errors in the reading of the memory cells, so as to tolerate the corresponding faults without impairing operation of the memory devices. The capability of correcting the errors or of simply detecting the errors (but without correcting them) depends on the amount of control information that is added to the payload information; for example, code words each one composed by a data word of 32 bits plus 7 control bits allow correcting 1 error, whereas code words each one composed by a data word of 64 bits plus 21 control bits allow correcting 3 errors.
However, an increase of the amount of control information (to increase the error correction and detection capability) accordingly reduces the capacity of the memory device. Moreover, the complexity of a circuitry used to implement the above-mentioned ECC functionality increases with the amount of the control information. This complexity of the ECC circuitry involves a waste of area of the memory devices (with a further reduction of their capacity). In addition, this complexity of the ECC circuitry increases an access time of the memory devices (thereby slowing down their entire operation) and a power consumption thereof.