1. Field of the Invention
The present invention generally relates to the field of fabrication of microstructures, such as integrated circuits, and more particularly relates to the formation of metal layers over a dielectric that may contain trenches and vias by a deposition process including an electroless plating process.
2. Description of the Related Art
In a microstructure, such as an integrated circuit, a huge number of structure elements, such as transistors, capacitors, resistors and the like, are formed in or on an appropriate substrate. In many cases, the microstructures include complex circuitry, in which, due to the large number of structure elements and the complex layout of the circuitry, the electrical connection of the individual circuit elements may not be established within the same level on which the circuit elements are manufactured, but requires one or more additional “wiring” layers, also referred to as metallization layers. These metallization layers generally include metal lines, providing the inner-level electrical connection, and also include a plurality of inter-level connections, also referred to as vias, wherein the metal lines and vias may also be commonly referred to as interconnects.
Due to the continuous shrinkage of the feature sizes of circuit elements in modern integrated circuits, the number of circuit elements for a given chip area, that is the package density, also increases, thereby typically requiring an even larger increase in the number of electrical interconnections to provide the desired circuit functionality. Therefore, the number of stacked metallization layers may increase as the number of circuit elements per chip area becomes larger and/or the corresponding interconnect structures also need to be reduced. Since the fabrication of a plurality of metallization layers entails extremely challenging issues to be solved, such as mechanical, thermal and electrical reliability, in combination with an efficient deposition technique to provide high throughput, for sophisticated applications, such as microprocessors, semiconductor manufacturers are increasingly replacing the well-known metallization metal aluminum by a metal that allows higher current densities and hence allows a reduction in the dimensions of the interconnections. For example, copper and alloys thereof are metals generally considered to be viable candidates for replacing aluminum due to superior characteristics in view of higher resistance against electromigration and significantly lower electrical resistivity when compared with aluminum.
In spite of these advantages, copper also exhibits a number of disadvantages regarding the processing and handling of copper in a semiconductor facility. For instance, copper may not be efficiently applied onto a substrate in larger amounts by well-established deposition methods, such as chemical vapor deposition (CVD) and physical vapor deposition (PVD), and also may not be effectively patterned by the usually employed anisotropic etch procedures, due to copper's characteristics to form non-volatile reaction products. In manufacturing metallization layers including copper, the so-called damascene technique is therefore preferably used, wherein a dielectric layer is first applied and then patterned to define trenches and vias, which are subsequently filled with copper.
A further major drawback of copper is its propensity to readily diffuse in silicon dioxide and other dielectric materials. It is therefore necessary to employ a so-called barrier material in combination with a copper-based metallization to substantially avoid any out-diffusion of copper into the surrounding dielectric material, as copper may then readily migrate to sensitive semiconductor areas, thereby significantly changing the characteristics thereof. Since the dimensions of the trenches and vias are currently approaching a width or a diameter of approximately 0.1 μm and even less with an aspect ratio of the vias of about 5 or more, the deposition of a barrier layer reliably on all surfaces of the vias and trenches and subsequent filling thereof with copper substantially without voids is one of the most challenging issues in the fabrication of modern integrated circuits.
Currently, the formation of a copper-based metallization layer is performed by patterning an appropriate dielectric layer and depositing the barrier layer, for example comprised of tantalum and/or tantalum nitride, by advanced PVD techniques, such as sputter deposition. Thereafter, the copper is filled in the vias and trenches, wherein electroplating has proven to be a viable process technique, since it is capable of filling the vias and trenches with a high deposition rate, compared to CVD and PVD rates, in a so-called bottom-up regime, in which the openings are filled starting at the bottom in a substantially void-free manner. Generally, during electroplating a metal onto a surface, an external electric field has to be applied between the surface to be plated and the plating solution. Since substrates for semiconductor production may only be contacted at restricted areas, usually at the perimeter of the substrate, a conductive layer covering the substrate and the surfaces that are to receive a metal has to be provided. Although the barrier layer previously deposited over the patterned dielectric may act as a current distribution layer, it turns out, however, that in view of crystallinity, uniformity and adhesion characteristics, presently a so-called seed layer is preferably used in the subsequent electroplating process to obtain copper-filled trenches and vias having the required electrical and mechanical properties. The seed layer is typically applied by sputter deposition using substantially the same process tools as are employed for the deposition of the barrier layer.
For vias having critical dimensions of 0.1 μm and less in future device generations, the sputter deposition of extremely thin metal layers having a high degree of conformity as required for the barrier layer and the seed layer may become a limiting factor, since the coverage characteristics of the above-described advanced sputter tools may not be further enhanced without significant modifications of these tools, which may be difficult to accomplish. Especially the deposition of the seed layer may not be performed in a straight-forward manner by PVD, as here the uniformity of the seed layer, contrary to the barrier layer which “only” requires a sufficient and complete coverage of the inner surfaces of the openings, determines to a certain degree the uniformity of the following electroplating process. Moreover, PVD techniques producing extremely thin layers appropriate for barrier layers may result, when applied to the formation of seed layers, in an increased electric resistance, thereby reducing an initial deposition rate of the subsequent electroplating process.
As a consequence, alternative deposition techniques for highly sophisticated applications have been proposed for barrier deposition, seed deposition, metal cap deposition on copper-based lines and metal gate deposition. The electroless deposition of metals and alloys, known for instance in the printed wire board industry, represents a promising approach as an alternative or an extension to well-established electroplating strategies. The process of electroless deposition requires a plating solution including a reducing agent, a metal carrier and a complexing agent with a precise control, in addition to the control of the bath composition, of the pH value and the temperature, as an active initiation of a chemical reaction of the plating agents by means of a catalyst contained in the underlying material or deposited prior to the actual deposition process is highly sensitive to the process temperature.
Typically, the operating temperature of the electroless metal plating solution may be in the range of approximately 50-90° C., which means that the electroless plating solution is maintained very closely to the self-catalyzing temperature for spontaneous self-decomposition of the electroless plating solution. The occurrence of a self-catalyzed decomposition of the electroless plating solution, however, results in metal plating not only on desired areas, that is the substrate surface to be plated, but also on surfaces of the plating equipment, such as the reactor cell, the plating solution tank, supply lines and the like. In severe cases of self-catalyzed decomposition, substantially the entire metal contents in the plating solution is rapidly reduced to pure metal, thereby possibly causing clogging of all lines and tubings and the chemical reactor. As a consequence, great efforts have to be made in cleaning the plating equipment with nitric acid while additionally the complete expensive plating chemistry is lost. At the same time, the resulting toxic waste has to be disposed, thereby significantly contributing to cost of ownership of the electroless metal plating process.
In view of the situation described above, there exists a need for an enhanced technique that avoids or at least reduces the effects of at least some of the problems in the electroless plating of metal as described above.