Electronic packages typically include one or more electrical components, e.g., semiconductor chips, and thus demand that damaging heat from the components be effectively removed and passed to the package's external environment. The ability of a package to dissipate heat generated by its components is generally a function of the quality of the primary heat dissipation path from the component(s) to the external surface of the package. As is well known, failure to provide an effective path for such heat escape may result in destruction of the component(s) or, at a minimum, may significantly reduce the operational capabilities thereof.
In some known package designs, thermal paste or some other thermally conductive material is used as a type of interposer at a point in the primary heat dissipation path from the chip(s) to the package's external surface. Such paste is normally compliant in nature, thus presenting advantageous features. Some of these advantages include the ability to accommodate statistical variations in thickness of the chip(s) to be housed in the package, height of the chip's solder connections (in the case of the more advantageous “flip chip” packaging), cavity depth of the cooling structure, thickness of the seal between the cooling structure, if bonded onto the package substrate, substrate camber, etc. The ability to control variations in the dimensions of such components is difficult, especially where the components are provided from different sources (vendors) or where reworking or modification of such components is required. This problem is especially apparent where large scale commercial production is involved.
With respect to such heat dissipation paths, including those which utilize compliant pastes or the like, the interposer or like component which forms the path from the chip(s) to the underside of the cooling structure may form the “weakest link” in the heat dissipation path; that is, interposers that use pastes or other materials may possess a lower thermal conductivity than do other components of the heat dissipation path. It is essential, therefore, that any interfacing structure between chip and the cooling structure possess effective thermal conductivity, to thereby assure optimal heat escape for the sensitive chip.
Various examples of electronic packages, including those having interposers, are described in the following patents. The listing thereof is not an admission that any are prior art to the presently claimed invention nor that an exhaustive search has been completed.
In U.S. Pat. No. 5,387,815, issued Feb. 7, 1995 to Nishiguchi, entitled SEMICONDUCTOR CHIP MODULE, there is described a semiconductor chip module which includes a substrate on which a wiring portion is formed, a semiconductor chip mounted so as to face a circuit side down to the wiring portion, a heat sink with one end in contact with a side opposite to the circuit side of the semiconductor chip, and a cap enclosing the semiconductor chip and having an opening exposing externally the other end of the heat sink. A metal film is formed at least on the inner wall of the opening and on the surface of the heatsink which is inserted into the cap. An adhesive material is filled between the tip portion of the heat sink and the semiconductor chip, while an adhesive material is filled between the metal films.
In U.S. Pat. No. 5,396,403, issued Mar. 7, 1995 to Patel, entitled HEAT SINK ASSEMBLY WITH THERMALLY-CONDUCTIVE PLATE FOR A PLURALITY OF INTEGRATED CIRCUITS ON A SUBSTRATE, there is described a heat sink assembly for a multi-chip module. A thermally conductive plate is bonded to the chips using indium solder. The plate in turn is thermally coupled to a heat sink (cooling) structure (e.g., comprised of finned aluminum) by thermal paste. The plate is made of a material such as silicon carbide or copper-tungsten alloy having a relatively low coefficient of expansion to minimize mechanical stress resulting from lateral motion of the chips due to thermal expansion. Relatively low-power chips may be thermally coupled to the plate by thermal paste instead of being bonded by solder.
In U.S. Pat. No. 5,585,671, issued Dec. 17, 1996 to Nagesh, et al., entitled RELIABLE LOW THERMAL RESISTANCE PACKAGE FOR HIGH POWER FLIP CLIP ICS, there is described a “flip chip” package with a thermally-conductive lid attached to a backside of the chip by a die attach layer of a predetermined thickness range. A rim is formed on the lid with a depth less than a sum of a thickness of the chip, the interconnect elements, and a minimum final thickness of the die attach layer by a predetermined margin. An initial thickness of thermally-filled epoxy is applied to the backside of the chip and a layer of lid attach epoxy is applied to the rim of the lid in a thickness sufficient to span the predetermined margin. The lid is floated on the die attach layer with the rim of the lid surrounding the chip and floating on the lid attach material. The lid is clamped against the chip with a force sufficient to compress the die attach material to a predetermined thickness in a range less than the initial thickness and not less than the minimum final thickness. An oxide layer, such as an iron or iron-alloy oxide layer, is formed on the bottom surface of the rim. A spacer is placed on the backside of the chip within the die attach material, to define the minimum final thickness of the die attach layer. A beveled or stepped vent hole is formed in the lid and plugged and sealed.
In U.S. Pat. No. 5,621,615, issued Apr. 15, 1997 to Dawson, et al., entitled LOW COST, HIGH THERMAL PERFORMANCE PACKAGE FOR FLIP CHIPS WITH LOW MECHANICAL STRESS ON CHIP, there is described a “flip chip” package comprised of a substrate, a ring structure attached to the substrate, a heat removal structure, and a chip thermally coupled to the heat removal structure. The package lid is comprised of a ring structure and a heat removal structure. The ring structure and heat removal structure are separated until after attachment of the ring structure to the substrate allowing the ring structure to be brazed to the substrate. Brazing the ring structure to the substrate decreases the mechanical stress to the chip. A die attach material between the first major surface of the die and the first major surface of the heat removal structure adheres the die to and thermally couples the die to the heat removal structure. The die attach layer is of a predetermined thickness and thus provides a determined low thermal resistance making the thermal performance of the package certain.
In U.S. Pat. No. 5,710,459, issued Jan. 20, 1998 to Teng, et al., entitled INTEGRATED CIRCUIT PACKAGE PROVIDED WITH MULTIPLE HEAT-CONDUCTING PATHS FOR ENHANCING HEAT DISSIPATION AND WRAPPING AROUND CAP FOR IMPROVING INTEGRITY AND RELIABILITY, there is described an electronic package which includes a chip cap for covering and protecting an integrated chip therein. The chip cap further forms a concave step near a lower edge of the cap for wrapping around the edge of the package's adapter board for increasing the contact areas between the cap and the board and for attaching the cap to the board. The chip cap is composed of thermal conductive materials and the chip cap further includes a heat sink for dissipating heat generated from the chip. The adapter board further includes a plurality of connecting vias and a plurality of conductive metal balls forming a ball grid array (BGA) underneath the adapter board. The chip is in electrical and thermal contact with the BGA by filling the connection vias with conductive materials. A printed circuit board (PCB) is used for supporting and receiving the adapter board thereon. The PCB includes a plurality of thermal vias penetrating there-through and filled with thermal conductive materials, wherein the thermal vias corresponding to and in contact with a plurality of the conductive metal balls of the BGA are used for dissipating heat generated from the chip.
In U.S. Pat. No. 5,757,620, issued May 26, 1998 to Edwards, et al., entitled APPARATUS FOR COOLING OF CHIPS USING BLIND HOLES WITH CUSTOMIZED DEPTH, there is described an apparatus and a method that provides customized cooling of a MCM (Multi-Chip Module) by varying the depth of a thermal compound-filled gap or blind hole above each chip in the module.
In U.S. Pat. No. 5,759,047, issued Jun. 2, 1998 to Brodsky, et al., entitled FLEXIBLE CIRCUITIZED INTERPOSER WITH APERTURED MEMBER AND METHOD FOR MAKING SAME, there is described a flexible circuitized interposer and method of making same wherein the interposer includes at least one flexible circuitized substrate having a dielectric (e.g., polyimide) layer with a conductor and plated elements, e.g., copper pad, including possibly with dendrites thereon for enhanced connection, an apertured support member aligning with the conductor, and a support member having the apertured member thereon. When the interposer is engaged, the flexible circuitized substrate is depressed within the aperture. Various alternatives, including a support formed with compressible portions that extend into respective apertures in the support member, and an interim, compressible support, are disclosed. The support member may also be metallic, e.g., for use as an electrical ground shield. Flexure is also enhanced by utilization of patterns of one or more apertures in the flexible substrate relative to and substantially surrounding the positioned conductors.
In U.S. Pat. No. 5,821,161, issued Oct. 13, 1998 to Covell, II, et al., entitled CAST METAL SEAL FOR SEMICONDUCTOR SUBSTRATES AND PROCESS THEREOF THERE, there is described a structure and a method that uses a multi-layer metallic seal to provide protection to chips on a chip carrier. This multi-layer metal seal is a two layer, solder structure which is used to create a low cost, high reliability, hermetic seal for the module. This solder structure has a thick high melting point temperature region that is attached to a cap, and a thin interconnecting region of lower melting point temperature region for sealing the substrate to the cap.
In U.S. Pat. No. 5,825,087, issued Oct. 20, 1998 to Iruvanti, et al., entitled INTEGRAL MESH FLAT PLATE COOLING MODULE, there is described an electronic module with integrated circuit chips mounted on a substrate and having a specially designed cooling plate overlying the chips and producing a gap above same in which a thermal paste or thermal adhesive is positioned. The cooling plate has a roughened area made by grit blasting and the like which penetrates the thermal paste and thermal adhesive and improves the adhesion and inhibits the flow of thermal paste from between the lower surface of the cooling plate and the upper surface of the chip during operation of the electronic module.
In U.S. Pat. No. 5,881,945, issued Mar. 16, 1999 to Edwards, et al., entitled MULTI-LAYER SOLDER SEAL BAND FOR SEMICONDUCTOR SUBSTRATES AND PROCESS, there is described a structure and method that uses a multi-layer metallic seal to provide protection to chips on a chip carrier. This multi-layer metal seal provides both enhanced hermetic lifetime and environmental protection. In one embodiment, the multi-layer metallic seal band is a three layer, solder sandwich structure which is used to create a low cost, high reliability, hermetic seal for the module. This solder sandwich has a high melting temperature thick solder inner core, and lower melting point thin interconnecting solder layers, where the thin interconnecting solder layers may have similar or different melting points.
In U.S. Pat. No. 5,938,454, issued Aug. 17, 1999 to Brodsky, et al., entitled ELECTRICAL CONNECTOR ASSEMBLY FOR CONNECTING FIRST AND SECOND CIRCUITIZED SUBSTRATES, there is described an electrical connector for coupling two circuitized substrates (e.g., a ball grid array module and a printed circuit board) wherein the connector includes a base member fixedly secured (e.g., soldered) to the printed circuit board and having one substrate oriented therein. The connector further includes a 2-part retention member including one part movably oriented in the base and a second part for directly engaging the retained substrate to cause it to move downwardly (and thus in a completely different direction than the direction of rotation of the movable one part within the base) to thereby provide effective connection between substrates. An interposer may be used if desired.
In U.S. Pat. No. 5,990,418, issued Nov. 23, 1999 to Bivona, et al., entitled HERMETIC CBGA/CCGA STRUCTURE WITH THERMAL PASTE COOLING, there is described a device and method for hermetically sealing an integrated circuit (semiconductor) chip between a substrate and a lid while providing dissipation of heat generated by the integrated circuit chip. The device includes an integrated circuit chip, carrier substrate, interface coolant, and a lid. The chip is attached to the top of the carrier substrate. The interface coolant is disposed on the top of the integrated circuit chip and the lid is placed on top of the carrier substrate/integrated circuit chip combination and contacts the interface coolant. The interface coolant provides a thermal path for conducting heat from the integrated circuit chip to the lid.
In U.S. Pat. No. 6,091,603, issued Jul. 18, 2000 to Daves, et al., entitled CUSTOMIZABLE LID FOR IMPROVED THERMAL PERFORMANCE OF MODULES USING FLIP CHIPS, there is described an integrated circuit chip packaging module characterized by a customized lid understructure which enables a reduction in the amount of compliant thermally conductive material in the primary heat dissipation path. The lid structure and module are made by processes wherein the lid understructure is customized for the chip(s) to be housed. The customization is achieved by the use of shims and a deformable lid understructure.
In U.S. Pat. No. 6,218,730, issued Apr. 17, 2001 to Toy, et al., entitled APPARATUS FOR CONTROLLING THERMAL INTERFACE GAP DISTANCE, tolerances in chip, substrate and hardware dimensions are accommodated by means of a floating sealing structure to insure that compliant thermally conductive paste disposed between the chip and its lid is as trim as possible in order to reduce thermal resistance of the paste so as to be able to run the chip at a cooler temperature. Standoffs are also preferably employed to insure proper paste gap thickness.
In U.S. Pat. No. 6,292,369, issued Sep. 18, 2001 to Daves, et al., entitled METHODS FOR CUSTOMIZING LID FOR IMPROVED THERMAL PERFORMANCE OF MODULES USING FLIP CHIPS, there is described an integrated circuit chip package including a customized lid understructure which enables a reduction in the amount of compliant thermally conductive material in the primary heat dissipation path. The lid structure and package are made by processes wherein the lid understructure is customized for the chip(s) to be housed. The customization is achieved by the use of shims and a deformable lid understructure.
In U.S. Pat. No. 6,294,408, issued Sep. 25, 2001 to Edwards, et al., entitled METHOD FOR CONTROLLING THERMAL INTERFACE GAP DISTANCE, there is described an electronic chip assembly which maintains a thin gap spacing between the chip and the lid or heat sink to allow the electronic chip to operate at a relatively cool temperature. Thermal performance is allegedly enhanced by a thermal interface material provided in the thin gap and maintained at a minimal thickness as a result of the structure and assembly process. A thin thermal interface material layer may be achieved with a compression step to compress the thermal interface material before the sealant is cured. In addition, a vent hole is provided in the assembly to prevent pressure build-up inside the package during sealant cure. As the sealant is cured, the gap spacing is maintained, further compression of the thermal interface material is not required, and seal defects are allegedly prevented.
In U.S. Pat. No. 6,407,924, ISSUED Jun. 18, 2002 to Brodsky, entitled ENHANCED THERMAL PATH MECHANICAL TOLERANCE SYSTEM, there is described a method and structure for interfacing a thermally conductive pad between a heat generating module and a heat-sink, such that the pad is in substantial thermal contact with both the module and the heat-sink despite the fact that both the module and the heat-sink are under mechanical tension. The mechanical tension causes deflection of a surface of the module and a surface of the heat-sink so as to generate an air gap between the pad and the heat-sink, as well as between the pad and the module. The present invention overcomes the deflection by crowning the pad, crowning the heatsink, or crowning the module.
In U.S. Pat. No. 6,493,240, issued Dec. 10, 2002 to Broglia, et al., entitled INTERPOSER FOR CONNECTING TWO SUBSTRATES AND RESULTING ASSEMBLY, there is described an interposer for electrically coupling a “micro-card” with a mother board (PCB). The interposer includes a frame which is interposed between the micro-card and the motherboard, electrically connecting the micro-card and the motherboard by means of plated via-holes. The substrate is organic and a plurality of chips is mounted on both sides of the substrate. On the opposite sides of the interposer are pluralities of metal pads which are coupled by metallized via holes, the pads in turn connected to the chips, thereby coupling chips or cards on one side of the interposer to chips or boards on the other side. Electrical connection between the chips on the top side of the substrate and the metal pads on the lower side of the substrate is provided by the metallized via holes.
In U.S. Pat. No. 6,516,513, issued Feb. 11, 2003 to Milkovich, et al., entitled METHOD OF MAKING A CTE COMPENSATED CHIP INTERPOSER, there is described a multilayer CTE compensated chip interposer for connecting a semiconductor chip to a laminate chip carrier. A first dielectric layer, on the chip side of the interposer, is made of a stiff, high elastic modulus, material, such as a ceramic material, with a CTE closely matching the CTE of the chip. A second dielectric layer, on the laminate chip carrier side of the interposer, is made of resilient, low elastic modulus, material with metallurgy formed thereon, such as circuit board material, with a composite CTE closely matching the CTE of said chip carrier. A third dielectric intermediate layer, laminated between said first and second layers, is made of a low elastic modulus material with metallurgy formed thereon, such as a Teflon/glass particle material, with a composite CTE between the CTEs of said first and second layers.
In U.S. Pat. No. 7,326,643, issued Feb. 5, 2008 to Desai, et al., entitled METHOD OF MAKING CIRCUITIZED SUBSTRATE WITH INTERNAL ORGANIC MEMORY DEVICE, there is described a method of making a circuitized substrate comprised of at least one dielectric material having an electrically conductive pattern thereon. At least part of the pattern is used as the first layer of an organic memory device which further includes at least a second dielectric layer over the pattern and a second pattern aligned with respect to the lower part for achieving several points of contact to thus form the device. The organic memory device is thus embedded within and part of the circuitized substrate.
In U.S. Pat. No. 7,511,518, issued Mar. 31, 2009 to Egitto, et al., entitled METHOD OF MAKING AN INTERPOSER, there is described an interposer in which at least two dielectric layers are bonded to each other to sandwich a plurality of conductors there-between. The conductors each electrically couple a respective pair of opposed electrical contacts which are formed within and protrude from openings which are also formed within the dielectric layers. The contacts may have sculpted, grooved or the like configurations, which in turn may mate with and partially penetrate solder elements, e.g., solder balls. The resulting interposer is ideally suited for use as part of a test apparatus to interconnect highly dense patterns of solder ball contacts of a semiconductor chip to lesser dense arrays of contacts on the apparatus's printed circuit board.
In U.S. Pat. No. 7,629,684, issued Dec. 8, 2009 to Alcoe, et al., entitled ADJUSTABLE THICKNESS THERMAL INTERPOSER AND ELECTRONIC PACKAGE UTILIZING SAME, there is described an electronic package which includes a substrate (e.g., a chip carrier or PCB), an electronic component (e.g., a semiconductor chip), a heat-sink and a thermal interposer for effectively transferring heat from the chip to the heat-sink. The interposer includes a compressible, resilient member (e.g., an elastomeric pad) and a plurality of thin, metallic sheets (e.g., copper foils) and the thickness thereof can be adjusted by altering the number of such foils.
The present invention defines an electronic package including at least two circuitized substrates and an interposer structure capable of providing effective heat transference from at least one electrical component positioned substantially within the interposer. The package defined herein is able to provide many advantages through the effective heat transference of the internally positioned component, thereby further enhancing the operational capabilities of the final package. It is believed that such a package, as well as a method of making same, would represent significant advancements in the art.