This invention relates generally to the field of wireless communications systems and more particularly, to apparatus and methods for modulating and filtering the signal in a mobile transmitter in a TR45.5 ITU-R code division multiple access (CDMA) system.
Third generation mobile standards (TR45.5 ITU-R) for wireless communications improve upon second generation mobile standards by offering higher bit rate channels for data and voice communications. TR45.5 ITU-R proposes the use of four distinct channel types in the uplink. These are pilot, control, supplemental, and fundamental. Each of the four channel types is identified by a unique code which makes the channel signals orthogonal.
In a mobile communications system it is desirable to independently control the power of each of the channels according to their data rates such that a minimum bit error rate (BER) threshold is achieved at the receiving end. Exceeding the threshold would result in power wasted at the mobile station and excessive interference to other mobile stations in the system. Operating significantly below threshold results in either low effective throughput due to multiple repeated transmissions or a poor quality link due to data corruption.
Fundamental to digital communications systems with limited bandwidth is filtering the channel signals prior to transmission. This is performed to restrict the channel to the allocated bandwidth while minimizing intersymbol interference within the channel. Such filters are well known in digital communications. They are typically implemented in the digital domain as finite impulse response (FIR) filters. FIG. 1 shows a typical modulator structure including a power control 6, a spreader 5, and a filter 7. As shown, the filter 7 is at the last stage.
Each of the four channels referred to above consists of a one bit digital signal prior to modulation. To represent a range of power levels for a digital signal, more than the two levels of the signal will be required. For example, if a signal prior to power control 6 were represented as +1 and xe2x88x921, and a coefficient quantized to eight bits were to represent the power level, the result would be a 512 state output signal where the signal amplitude could range from xe2x88x921 to +1 in steps of 1/256. To filter a signal such as this would require greater complexity in the multipliers of the FIR filter since instead of consisting of a 1-bit by N-bit multiply, where N is the number of bits desired in the coefficients, the multipliers would consist of Mxc3x97N multipliers, where M is the number of states in the input sample to the filter. This is significant in a digital hardware implementation of the filter because a multiplier""s complexity will grow approximately linearly with expansion of the dynamic range of its input (assuming the coefficient dynamic range is fixed). In this case an Mxc3x97N multiplier requires approximately M times greater complexity than a 1xc3x97N multiplier. Greater complexity results in larger hardware and may also result in more power consumption.
FIG. 2 shows a standard FIR filter. The Zxe2x88x92n blocks represent unit delays 200, where the cascaded string of unit delays 200 form a tapped delay line. In digital form this is a shift register with a bit width as required to store all of the bits of the input sample. The number of bits of each sample would be dictated by the dynamic range requirement of the system. This would be determined by the worst case signal to noise ratio requirements of the system and by taking into account whatever power control adjustment range is applied to the signal. The value of each tap of the delay line is multiplied (module 220) by its corresponding coefficient (Cn). The products of all the Znxc3x97Cn multiplications are then summed by a summation unit 230.
According to the TR45.5 ITU-R specification, the channel inputs can be only 1 bit. Conventional systems and methods do not take advantage of this element of the specification. Since the inputs can be only 1-bit, a multiplier output need have only two states. Thus, instead of having hardware multipliers 220, a simpler look-up table can be used. The concept of a lookup table is well known. However, current systems and methods do not provide for such efficient software or hardware that inputs a signal to each of the channel filters that is only 1 bit wide. Thus conventional systems do not minimize the gate complexity of the mobile component for the wireless communications system proposed in TR45.5 ITU-R. In fact, as described above, the implementation proposed in the TR45.5 ITU-R System Description Draft contemplates the application of channel power control prior to filtering. This results in a wide dynamic range signal at the input to the FIR filter which would require processing using multipliers of equivalent input dynamic range. While this solution can work, it requires very high gate complexity.
Accordingly, there exists a need for a system and method that decreases the gate complexity in a mobile transmitter by reducing the dynamic range of the signal at the input to the FIR filter in the modulator.
A need also exists for a system and method of FIR filtering the signal from a mobile transmitter that provides for adjusting filter coefficients while minimizing gate complexity.
Accordingly, it is an object of the present invention to provide systems and methods that decrease the gate complexity in a mobile transmitter by reducing the dynamic range of the signal at the input to the FIR filter.
It is another object of the present invention to provide systems and methods of FIR filtering the signal from a mobile transmitter that provides for adjusting filter coefficients while minimizing gate complexity.
In accordance with the teachings of the present invention, these and other objects may be accomplished by the present invention, which is a transmitter for modulating and filtering signals in a wireless communications system. The invention acts on a plurality of CDMA signals.
The signals are processed by a plurality of modulators. More specifically, the plurality of modulators performs orthogonal code and pseudonoise (PN) spreading on the plurality of CDMA signals, where the spreading produces a 1-bit in-phase (I) data stream and a 1-bit quadrature (Q) data stream. These streams are also processed by a plurality of filters electrically coupled to the modulators. The filters filter the 1-bit I and 1-bit Q data streams and produce at least one n-bit wide I data stream and at least one n-bit wide Q data stream, where n is an integer of at least one.
The invention further includes a central processing unit for generating at least one gain factor. A processor is coupled to the filters and the central processing unit. The processor performs per channel power control and combining of the n-bit wide I data streams and n-bit wide Q data streams into one I stream and one Q stream using the gain factor generated by the central processing unit. A gain amplifier is also electrically coupled to the processor. The streams are sent to the gain amplifier for amplifying the output of the processor using the gain factor.
The invention will next be described in connection with certain exemplary embodiments; however, it should be clear to those skilled in the art that various modifications, additions and subtractions can be made without departing from the spirit or scope of the claims.