Recent efforts in miniaturizing ICs have focused on reducing the space consumed by the circuit components. The ongoing evolution in miniaturizing IC components has resulted in reduced costs and more circuit functionality for a given substrate size and manufacturing cost. For example, only a few years ago spacing between adjoining circuit elements in a typical IC was in the neighborhood of two to three microns. Today, many ICs are being designed at spacing distances as small as 0.35 microns or less. To accommodate narrower spacing, the electrical conductors are reduced in width. The reduction in width is compensated for by increasing the thickness of the conductors to avoid degrading the quality of the signal conducted.
Increasing the thickness of the conductors also requires increases in the thickness of the dielectric insulation material which separates and covers the conductors and components. The thickness of the dielectric must be greater than the height or topology difference among the components, to provide adequate insulation to separate the layers and components of the IC structure from one another. Increases in the thickness of the dielectric material are possible, in part, as a result of advanced planarization techniques such as chemical mechanical polishing (CMP). CMP smooths relatively significant variations in the height of the different components to a planar surface. Smoothing the variable-height topology to a planar surface allows the typical lithographic semiconductor fabrication techniques to be used to form considerably more layers than were previously possible in IC construction. Previously, only one or two layers were typically constructed before the topology variations created such significant depth of focus problems with lithographic processes that any further precision fabrication of layered elements was prevented. However, because of CMP, the number of layers of the IC is no longer limited by the topology. Some present ICs are formed using as many as five or more separate metal or interconnect layers, each of which is separated by a CMP planarized dielectric layer. Consequently, CMP has created the opportunity to incorporate more circuitry on a single substrate in a single IC.
Each interconnect layer comprises many electrical conductors which connect to separate functional components in the IC. The conductors are formed on top of the planarized dielectric layer and extend above conductors positioned in a lower interconnect layer. The conductors of one interconnect layer are electrically separated from each other by dielectric material as are the conductors of separate interconnect layers. In order to connect the conductors of separate interconnect layers, holes or vias are formed in the dielectric material. The vias extend through the dielectric material down to the lower conductor. The vias are then filled with metal or some other conducting material to form a via interconnect. The filler material is typically referred to as a "plug" and thus via interconnects are also referred to as "via plug interconnects." Numerous connection possibilities using via plug interconnects and the multiple interconnect layers may result in substantial unused areas of relatively thick interlayer dielectric material in the IC.
Recent efforts of reducing space consumed in increased density ICs has resulted in orienting some of the components, such as capacitors, vertically. Trench capacitors located in the substrate exemplify one implementation of vertical components, because the parallel plates of the trench capacitor extend vertically. Since the plates extend vertically, less surface area is consumed by the capacitor.
In order to take advantage of the horizontal space saving characteristics, and to take advantage of the unused portions of interlayer dielectric, trench capacitors have been formed in the interlayer dielectric material. Embodiments of an interlayer trench capacitor are discussed in the previously mentioned U.S. Patent Applications titled "High Aspect Ratio, Metal-To-Metal Linear Capacitor for an Integrated Circuit" and "Method of Electrically Connecting and Isolating Components with Vertical Elements Extending Between Interconnect Layers in an Integrated Circuit." As disclosed in these applications, the capacitor comprises a lower U-shaped plate positioned against the walls of a trench in the dielectric material and electrically contacting a conductor of a lower interconnect layer. The capacitor dielectric material is also U-shaped and is positioned within the interior of the lower U-shaped plate. The capacitor dielectric material also extends along the upper surface of the lower U-shaped plate. The upper plate of the capacitor is positioned within the U-shaped opening defined by the capacitor dielectric material. The upper plate contacts a conductor of the upper interconnect layer. Since the capacitor is located above the substrate between interconnect layers, no substrate surface area is consumed by the capacitor. Additionally, owing to the vertical plate orientation, the capacitor does not consume large quantities of horizontal space and can thus be placed in previously unused portions of interlayer dielectric material.
As disclosed in the above-mentioned method patent application, forming the vertical capacitor begins with forming the trench in the layer of interconnect dielectric material. The lower metal U-shaped plate is then formed by uniformly depositing metal in and around the trench and then chemical-mechanical polishing the upper surface to remove metal located above the dielectric layer. Subsequent steps involve depositing the dielectric material and the upper plate metal.
The CMP process step used to create the flush upper ends of the lower metal plate occurs while the trench is open, i.e., not filled. Residual slurry from the CMP process and resist material from the subsequent photolithographic process forms on or catches in the upper edges of the open trench and within the trench. These residual materials are contaminants to subsequent metal application steps (and possibly other steps) and as such can severely interfere with or destroy the effectiveness of the subsequent steps. For example, residual resist will outgas when metal is applied over it. The outgas effect prevents the metal from depositing properly, if at all, thereby resulting in circuit connections which are either unreliable or nonexistent. If the metal does not deposit or adhere properly, an open or unintended circuit situation may occur, degrading the functionality of the IC or capacitor.
The residual materials are extremely difficult to remove completely from the edges of the opening. Moreover, any attempt to remove the materials adds cleaning process steps and may even raise the risk that the other existing circuit components on the IC will be damaged by the cleaning process itself.
It is with regard to these and other considerations and problems that the present invention has evolved.