A single very large scale integration (VLSI) semiconductor chip may contain thousands of interconnected logic gates which may include, for example, AND, OR, NAND, NOR, and XOR gates. A critical part of the manufacturing process for any such integrated circuit is verifying the functionality of the logic gates included in the integrated circuit. Verifying the functionality of each logic gate can be difficult because of the limited number of input/output (I/O) pins for the integrated circuit and the complex interconnections between the inputs and outputs of the multitude of logic gates. In many cases, multiple channels within the integrated circuit share I/O pins.
During functional tests of an integrated circuit contained within a semiconductor chip, the integrated circuit's inputs receive known digital data patterns, made up of sequences of 0s and 1s, that are input to the logic gates internal to the chip. In response, the logic gates process the input data patterns, and eventually, the integrated circuit generates output data patterns, again made up of sequences of 0s and 1s, that are dependent upon the input data patterns and the functionality of the logic gates. When the output data patterns do not match predicted output data patterns, it is known that a fault has occurred in at least one of the logic gates.
One option for integrated circuit functional testing involves the application of multiple data patterns to the inputs of the chip in hopes of generating every predicted output data pattern. However, such a test process may require extremely long test times due to the need for generating and inputting a large number of different input data patterns.
Another option involves the application of random data patterns to the integrated circuit's inputs in hopes of identifying defective logic gates. Again, the measured data patterns output from the logic circuit are compared to predicted output data patterns. However, one problem associated with applying random data patterns is that only a portion of the logic circuits will be tested, and therefore, there is a likelihood that an integrated circuit having a defect may go undetected. Applying a larger number of random input data patterns to the integrated circuit's inputs will increase the likelihood that more of the logic gates will be tested. However, the increased number of input data patterns lengthens the overall test time, and thus, increases the overall manufacturing cost for the integrated circuit.
Many integrated circuits include logic gate structures that are difficult to test using a purely random input data pattern. An example of such a logic gate structure is an AND gate. The probability of faults being detected in an AND gate decreases as the number of inputs to the AND gate increases. Initially, in order to check the AND gate for faults, all of the AND gate's inputs must receive an input digit of 1 in order for the signal output from the AND gate to be 1. Next, all but one of the AND gate's inputs should be 1 in order to verify the correct functioning of the AND gate. Therefore, the bits that make up the data pattern input to the integrated circuit must be configured so as to facilitate the various bit changes that must be input to each of the AND gate's inputs.
In order to deal with the limitations of the random number generation test, testing methods that alter the probabilities of generating a 0 or a 1 have been developed. These testing methods weight random input data patterns using a weighted random number generator so as to perform specific tests of a desired logic gate. The weighted random number generator outputs weighted random input patterns to the integrated circuit under test. In the weighted random input patterns, the probability that the input digit is 0 is multiplied by a weighting factor times one half, and the probability that the input digit is 1 is one minus the weighting factor time one half, where the weighting factor is a positive number. Thus, the weighting factor is expressed as a probability of occurrence of a 0 or a 1. The weighting factor is selected dependent upon the number of inputs to the integrated circuit and the number and type of logic gates internal to the chip. In addition, the weighting factor is selected in a manner to facilitate time and cost efficient testing with an acceptable level of confidence that no faults exist in the logic circuit.