1. Field of the Invention
The present invention relates to a memory circuit, and more particularly to an integrated-circuit type memory circuit having bit lines, memory cells and sense amplifying circuits.
2. Description of the Prior Art
As is well known, an integrated-circuit type memory circuit is used together with sense amplifying circuits. An example of prior art integrated-circuit type memory circuits comprising sense amplifying circuits is explained hereinafter with reference to FIG. 1. This embodiment is disclosed in U.S. Pat. No. 4,.061,999.
Memory cells m1, m2, . . . mn and a dummy cell d' are connected to a bit line BL1. Memory cells m'1, m'2, . . . m'n and a dummy cell d are connected to another bit line BL2. The memory cell m1 comprises a memory capacitor C1 and a field effect transistor Q-m1 (FET Q-m1). The FET Q-m1 is controlled through a word line W1. The dummy cell d comprises a dummy capacitor C.sub.sa, a parallel connected FET Q-d1 and a series connected FET Q-d2. The series connected FET Q-d2 is controlled through a dummy word line DWA. The capacitance of the dummy capacitor C.sub.sa is approximately one half of the capacitance of the memory capacitor.
Each of the bit lines BL1 and BL2 is connected to a sense amplifying circuit SA-1. The sense amplifying circuit SA-1 includes a pair of connecting FETs Q.sub.1 and Q.sub.2 through which the sense amplifying circuit SA-1 is connected to the bit lines BL1 and BL2. The main part of the sense amplifying circuit SA-1 consists of a pair of cross-coupled FETs Q.sub.3 and Q.sub.4.
A memory group No. 1 is connected to a pair of bus lines RL1 and RL2 through FETs Q.sub.x and Q.sub.y. The bus lines RL1 and RL2 are connected to a differential amplifier D.A. which produces an output which is to be used as an output of the entire memory circuit of FIG. 1.
A controlling circuit X-1 for controlling the gate potential of the connecting FETs Q.sub.1 and Q.sub.2 is connected to the sense amplifying circuit SA-1.
The circuit of FIG. 1 is operated as follows. In the initial state, the potentials of the bit line BL1, the bit line BL2, the point P1 and the point P2 are equal to the drain supply voltage +E. The potential of the point P3 is arranged (explained below) to be higher than the voltage +E so that the FETs Q.sub.1 and Q.sub.2 are caused to be conductive. Voltages E-C1 and E-C1' are stored in memory capacitors C1 and C1', respectively.
Under the above-described initial state, the reading out of information stored in the memory circuit is effected as follows. It is assumed that the word line W1 is selected and is caused to become HIGH level. Simultaneously, the dummy cell d is selected and the word line DWA of the dummy cell d is rendered HIGH level. Thus, the electric charges of BL1 and BL2 are transferred to P5 and P8, respectively, so that the potentials of BL1 and BL2 are reduced. Since the potential E-C1 was at HIGH level before the reading-out, the amount of transfer of electric charge from BL1 to P5 is small. On the other hand, since the potential at P8 is rendered zero before the dummy cell d is selected, the amount of transfer of electric charge from BL2 to P8 is relatively large. Accordingly, the potential of BL2 is reduced more than the potential of BL1 is reduced. Thus, a potential difference is formed between BL1 and BL2. The potentials of BL1 and BL2 are transmitted to the points P1 and P2 through FETS Q.sub.1 to Q.sub.2. Accordingly, the potential at P1 is caused to be higher than the potential at P2.
After that, the potential .phi..sub.1 at an electrode of the capacitor C.sub.o, included in the controlling circuit X-1 for controlling the connecting FETs Q.sub.1 and Q.sub.2, is made HIGH level. Then, FET Q.sub.a is rendered ON because the gate potential of FET Q.sub.a becomes sufficiently higher than +E, and the potential at P3 goes down to the level of +E. Accordingly, the transconductances of FETs Q.sub.1 and Q.sub.2 are reduced. The potential .phi..sub.1 at an electrode of the capacitor C.sub.o is also applied to the gate of FET Q.sub.5 ' included in the sense amplifying circuit. The sensitivity of the sense amplifying circuit SA-1 is preliminarily increased by the operation of FET Q.sub.5 ' with a small current before the large scale amplification of an input signal is conducted by the sense amplifying circuit. Thus, when FET Q.sub.5 ' turns ON due to the application of the potential .phi..sub.1 to the gate thereof, the operation of the sense amplifying circuit SA-1 is started slowly, the potentials at the points P1 and P2 are together caused to go down, and the potential difference between P1 and P2 is caused to increase.
At this moment, the potential .phi..sub.2 of the gate of FET Q.sub.5 is rendered HIGH level. Then the potential at P4 becomes quickly zero, and the flip-flop circuit consisting of FETs Q.sub.3 and Q.sub.4 conducts its operation so that the potential difference between P1 and P2 is enlarged.
In the sense amplifying circuit SA-1, FETs Q.sub.1 and Q.sub.2 are provided. The necessity for the FETs Q.sub.1 and Q.sub.2 can be explained as follows. In the initial period of the operation of the sense amplifying circuit, the transconductances of FETS Q.sub.1 and Q.sub.2 are small and FETs Q.sub.1 and Q.sub.2 prevent the flow of the charges of BL1 and BL2 to the points P1 and P2, so that the potential difference between P1 and P2 is amplified quickly, and accordingly, the drop of the potential of BL1, which should be maintained at HIGH level, is prevented. If FETs Q.sub.1 and Q.sub.2 were eliminated and the bit lines BL1 and BL2 were connected directly to the points P1 and P2, the charge in the load capacitances of the bit lines BL1 and BL2 would be discharged through FETs Q.sub.3 and Q.sub.4 when the sense amplifying circuit is operated. Thus, the speed of the amplification of the potential difference between P1 and P2 would be low, so that it would take a long time for the potential at P2, which should be brought to LOW level, to reach ground level and the charges of BL1, which for refreshing the charge state of m1 should be brought to the HIGH level, would be discharged. Thus, the potential of BL1 would be lowered and accordingly the complete refreshing of the HIGH levels of the memory cells would not be effected.
Returning to the description of the enlargement of the potential difference between P1 and P2, in the case where the potential difference between P1 and P2 is small, both of the potentials at P1 and P2 are reduced to a great extent because both of the FETs Q.sub.3 and Q.sub.4 become ON and the difference in transconductance is not very large. When the potentials at P1 and P2 are reduced as described above, the transconductances of FETs Q.sub.1 and Q.sub.2 are increased and the cutting-off abilities of FETs Q.sub.1 and Q.sub.2 are decreased. Thus, FETs Q.sub.1 and Q.sub.2 are caused to be ON, so that the flow of charges from the bit lines BL1 and BL2 through FET Q.sub.1 and Q.sub.2 prevents the further enlargement of the potential difference between P1 and P2. In consequence, even if the sense amplifying circuit detects exactly the signal applied thereto and the potential at P2 is rendered zero in accordance with the initial potential difference, the potential at P1 unavoidably falls lower than a required level. Such a fall of the potential at P1 makes it impossible to refresh the memory cells from which the stored information has been read out. In addition, such a difficulty in refreshing memory cells occurs more prominently in the case where the initial potentials at P1 and P2 are lowered due to the decrease of voltage of the power source. Accordingly, the prior art memory circuit shown in FIG. 1 involves the disadvantage explained above.