1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a method of reducing noise, and more particularly relates to an input circuit of a semiconductor integrated circuit and a method of reducing noise in the input circuit.
2. Description of the Related Art
It is well known that a CR filter is inserted into a former stage of an input terminal in order to remove a noise signal superimposed on an input signal. The CR filter removes high frequency signal in the input signal on which the noise signal is superimposed, and separates and extracts the input signal that is lower in frequency than the noise signal. For this reason, a time constant of the CR filter must be selected on the basis of characteristics of the input signal and the noise signal. Also, in many cases, the cutoff property of the filter must be made precipitous, which increases the number of parts. Thus, a circuit, which judges the effective input signal or the noise signal based on a continuation time of the input signal, is used in many cases. For example, Japanese Laid Open Patent Applications JP-A-Heisei, 07-38535 and JP-P 2001-211057A disclose such circuits.
The circuit disclosed in Japanese Laid Open Patent Application JP-A-Heisei, 07-38535 is installed on a data input side of a demodulating circuit for an asynchronous serial coding transmission method. This circuit is used for removing a single noise. This noise removing circuit has four D-type flip-flop circuits. The D-type flip-flop (1) is turned off at the rising of a clock signal when an input data is zero. The D-type flip-flop (1) is turned on at the rising of the clock signal when the single noise is generated in the off state, and turned off at the rising of a next clock signal. The D-type flip-flop (2) is turned off when the D-type flip-flop (1) is turned on by the generation of the single noise, and this is turned on when the flip-flop (1) is turned off. The D-type flip-flop (3) is cleared by the outputs of the D-type flip-flops (1) and (2) and the output of an exclusive-OR circuit. The D-type flip-flop (3) executes frequency dividing at the falling of the clock to generate a sampling clock signal. The D-type flip-flop (4) synchronizes and outputs the outputs of the D-type flip-flop (1) in the sampling clock signal and supplies to a demodulating circuit.
The circuit disclosed in Japanese Laid Open Patent Application JP-P 2001-211057A is the input filter circuit for filtering a data stream supplied through an input line. This circuit has a first register (1A), a clock input signal and switching devices (4, 5 and 8). The first register (1A) is the register inside a register chain (1) where a signal input terminal is connected to the input line (2). The clock input signal is supplied to a plurality of registers (1A, 1B and 1C) connected to a clock line (3). This is used to transfer a sampling signal (T) at a sampling frequency higher than a maximum data transfer frequency in the data stream. The switchers (4, 5 and 8) are connected to the register chain (1). When the output signals generated in the respective plurality of registers (1A, 1B and 1C) are at the same logic level, an output line (9) is switched to the logic levels of the signal outputs of the plurality of registers (1A, 1B and 1C).
This circuit is tend to be erroneously operated, when the noise signal synchronous with a clock cycle is superimposed on the input signal. Thus, when this noise signal is removed in accordance with the asynchronous characteristic of the noise, there is no other way but to make the register chain longer. This implies that a time constant becomes longer.
As a circuit for removing a noise signal independently of a filter constant, there is a circuit disclosed in Japanese Laid Open Patent Application JP-P 2000-286685A. This circuit has first and second registers, which are cascade-connected, so as to be operated in accordance with a filter clock signal corresponding to the filter constant, and this is the digital filter for filtering an input signal in accordance with a two-stage sampling method. A discrepancy detector is provided with: ExOR gates G1, G2; an AND gate G3, an OR gate G4; and a D-flip-flop FF3. The discrepancy detector is operated at a sampling clock SCLK which is higher in frequency than a filter clock FCLK, and detects noise. The discrepancy detector, when detecting the noise, switches and controls a selector S and prevents the output of FF1 from being supplied to FF2. The flip-flops FF1, FF2 of the two-stage cascade configuration is operated at the filter clock FCLK. Then, unless the noise is detected by the discrepancy detector, the FF1 holds/outputs an input signal “a” at the time of the sampling when there is the filter clock FCLK. Then, the FF2 outputs this input signal “a” as the input signal after the filtering at the time of a next sampling.
This circuit requires that the sampling clock is set to be higher than the input signal. Also, the circuit configuration is complex. Here, FIG. 1 is a circuit diagram showing an example of a conventional circuit, which detects an input signal with a predetermined signal length and then removes a noise signal.
This conventional circuit includes D-type flip-flops 110, 112 and 113, logical product circuits (hereinafter referred to as AND circuits) 114, 116 and logical sum circuits (hereinafter referred to as OR circuits) 115, 117. Each of the D-type flip-flops 110, 112 and 113 samples a signal supplied to an input terminal D in synchronization with a sampling clock CK, and outputs an output signal from an output terminal Q. The D-type flip-flop 110 receives an input signal Din from an external circuit, and outputs an output signal indicating a sampling result to a node A. This output signal at the node A is supplied to the input terminal D of the D-type flip-flop 112 at the next stage, the AND circuit 114 and the OR circuit 115. An output signal at a node B of the D-type flip-flop 112 is supplied to the AND circuit 114 and the OR circuit 115. An output signal at a node C of the AND circuit 114 is supplied to the OR circuit 117. An output signal at a node D of the OR circuit 115 is supplied to the AND circuit 116. The AND circuit 16 also receives an output signal Dout of the D-type flip-flop 113. An output signal at a node E of the AND circuit 116 is supplied to the OR circuit 117. An output signal at a node F of the OR circuit 17 is supplied to the D-type flip-flop 113. The output signal at the D-type flip-flop 13 becomes the output Dout in this filtering circuit.
The D-type flip-flop 110 of the first stage is the circuit for sampling the input signal. The D-type flip-flop 112 of the next stage is the circuit for delaying the sampled signal. The combination circuit carries out the noise removal judgment whether or not the signals are at the same level on the basis of this sampled signal and this delayed sampled signal, and then supplies a result signal to the D-type flip-flop 13. Here, whether or not it is the noise is judged, on the bases of the signal level corresponding to one cycle in the sampling cycle as a constant period, namely, the two samplings.
An operation of this circuit will be described below. FIG. 2 is a timing chart showing an operation of the conventional circuit. In FIG. 2, (a) shows the clock signal CK, (b) and (i) show the input signal Din and the output signal Dout, respectively, and (c) to (h) show the signals at the nodes A to F, respectively. In synchronization with the rising of the clock signal CK, each of the D-type flip-flops 110, 112 and 113 samples the signal applied to each terminal D. Symbols T1 to T9 are assigned to the rising timings of this clock signal CK.
The input signal Din has a pulse signal of a level “High”, which does not fulfill one cycle near the time T2, as shown in FIG. 2(b). The D-type flip-flop 110 samples the level “High” in synchronization with the clock signal CK, and then sets the output to the level “High” as shown in FIG. 2(c). At the time T3, since the input signal Din is at a level “Low”, the D-type flip-flop 110 outputs the level “Low”. Thus, the node A becomes in the state of the level “High” between the time T2 and the time T3 (FIG. 2 (c)).
The D-type flip-flop 112 samples the states of the node A. Thus, the output signal at the node B of the D-type flip-flop 112 becomes in the state where the state of the node A is delayed by one cycle, as shown in FIG. 2(d). That is, the node B becomes in the state of the level “High” between the time T3 and the time T4.
The AND circuit 114 outputs the logical product between the states of the nodes A and B. Thus, as shown in FIG. 2(e), the node C does not become at the level “High” between the time T2 and the time T4. Since the OR circuit 115 outputs the logical sum between the states of the nodes A and B, as shown in FIG. 2(f), the node D is at the level “High” between the time T2 and the time T4. The AND circuit 116 outputs the logical product between the node D and the output signal Dout. Since the output signal Dout is at the level “Low” between the time T2 and the time T4 as shown in FIG. 2(i), the node E is still at the level “Low” between the time T2 and the time T4 as shown in FIG. 2(g). Thus, the output of the OR circuit 117 is still at the level “Low” as shown in FIG. 2(h). Then, the D-type flip-flop 113 holds the level “Low” as shown in FIG. 2(i). Hence, in the case of the input of the signal, which is at the level “High” only at the time of one sampling that is the noise signal, it is known that the output signal of this circuit is not changed and the noise signal is removed.
The case that an expected input signal is supplied will be explained next, wherein the input signal Din is at the level “High” between the time T5 and the time T6 as shown in FIG. 2(b). The signal level at the node A becomes the level “High” in the period between the time T5 and the time T7 as shown in FIG. 2(c), because the input signal Din is at the level “High” at the time T5 and the time T6. The D-type flip-flop 112, which samples this signal at the node A at the timing of the clock signal CK, outputs the signal, which is delayed by one clock, to the node B. That is, the signal level of the node B is the level “High” in the period between the time T6 and the time T8 (FIG. 2(d)).
Thus, the signal level of the node C that is the output signal of the AND circuit 114 becomes the level “High” only in the one-clock period between the time T6 and the time T7 (FIG. 2(e)). Also, the signal level of the node D that is the output signal of the OR circuit 115 becomes the level “High” in the three-clock period between the time T5 and the time T8 (FIG. 2(f)). When the node C becomes at the level “High”, the output signal at the node F of the OR circuit 117 becomes at the level “High”. Thus, the D-type flip-flop 113 samples the level “High” at the time T7, and outputs the level “High” to the output signal Dout as shown in FIG. 2(i).
When the output signal Dout becomes at the level “High”, the AND circuit 116 outputs the signal level of the node D to the node E. Thus, the signal level of the node E is the level “High” between the time T7 when the node D becomes at the level “High” and the time T8 when the node D becomes at the level “Low” (FIG. 2(g)). Since the signal level of the node E is “High”, the output signal of the OR circuit 117 is at the level “High” until the time T8 (FIG. 2(h)). Since the signal level of the node F is the level “High” until the time T8, the output Dout of the D-type flip-flop 113 is at the level “High” until the time T9 (FIG. 2(i)). That is, the signal where the level “High” is sampled continuously two times at the time T5 and the time T6 outputs the signal Dout which is at the level “High” in the two-clock period between the time T7 and the time T9.
In this way, the input signal Din which is at the level “High” in the short period is not reflected as the noise in the output Dout. On the other hand, the signal which is continued to some degree (in this case, the two-sampling period) is reflected as the normal input signal in the output Dout. However, as indicated by the dashed lines in FIG. 2(b), even in the case when the level “High” is not continued in the middle near the time T5 and the time T6 where the D-type flip-flop 110 samples the input signal Din, this may be operated as if the level “High” is continued from the time T5 to the time T6. Thus, this circuit is assumed to be used in the environment where the noise is sporadically generated, namely, the environment where the noise, which is sampled continuously two or more times, is removed in view of probability.
This operation is equal even if the effective signal level is “Low”. FIG. 3 is a timing chart showing another operation of the conventional circuit. In FIG. 3, (a) shows the clock signal CK, (b) and (i) show the input signal Din and the output signal Dout, respectively, and (c) to (h) show the signals at the nodes A to F, respectively. As shown in FIG. 3, (a) to (i), even if the input signal Din, which becomes at the level “Low” only at the time T2, is supplied, the output signal Dout of the D-type flip-flop 113 is still at the level “High”. The input signal which becomes at the level “Low” at the time T5 and the time T6 is reflected in the output signal so as to be at the level “Low” in the two-clock period. As indicated by the dashed lines in FIG. 3(b), under the assumption that this is at the level “High” in the middle between the time T5 and the time T6 and that the state is continued even if the level “Low” is not continued, the output signal Dout is at the level “Low” between the time T7 and the time T9.
In this way, the synchronous noise removal effectively functions for the sporadic noise. However, under the environment of various noises or under the situation where the noise is apt to be generated in synchronization with the sampling cycle, the noise cannot be perfectly removed in those circuits.