Currently, threshold voltage adjust implantation is used to properly design MOSFETs. For an example, the NMOS with N+ type polysilicon gate is often formed by adequate boron ions implantation so as to adjust threshold voltage.
FIG. 1. shows the conventional channel profile diagram of a semiconductor device by merely using the boron ions implantation. As shown in FIG. 1, the final distribution of channel profile would show decreased boron concentration with increased channel depth.
However, while the channel depth increases, boron concentration decreases dramatically in the channel. Besides, higher surface channel concentration would degrade the effective electron mobility.
FIG. 2 shows Id vs. Vg diagram for a semiconductor device with the conventional channel profile. As shown in FIG. 2, curve 21 corresponds to the condition while Vd=5V, and curve 22 corresponds to the condition while Vd=0.1V. As shown in curve 21 of FIG. 2, when the device is operated under the condition of Vd=5V and Vg=0, then Id, which is the off leakage current of the device element, is equal to 3.75 pA. The off leakage current is not small enough to provide immunization from punch through effect generally. Therefore, as long as the PN junction is not shallowlized by using advanced formation technology, the channel implantation should be considerably increased to prevent punch through leakage for scaled down channel length.
However, higher surface channel concentration would degrade the effective electron mobility and impact ionization as well. Hence, advanced channel profile is expected to improve the device scalibility.