In a phase locked loop (PLL) the output signal is phase and frequency locked to an input reference signal. A PLL with a frequency divider inserted in the feedback loop can be used to make an integer-N frequency synthesizer. In that case the signal at the phase detector negative input is phase and frequency locked to the reference. The output frequency and phase is N times the reference frequency and phase. Output frequencies can be synthesized in steps of the reference frequency by programming the value of N. There are exactly N periods of the output for every period of the reference and therefore one rising edge of the output in every N is in phase with each rising edge of the reference. For any given value of N the phase of the output relative to the reference is fixed and is the same each time the synthesizer is switched back to that frequency channel. In a fractional-N synthesizer, the divider in the feedback path has an integer and fractional part and the output frequency step resolution is a fraction of the reference frequency, as shown in equation 1:
                              f          OUT                =                              (                          N              +                              F                M                                      )                    ×                      f            REF                                              (        1        )            
The fractional part is generated using a digital interpolator. This outputs a sequence of integer values with an average value given by F/M where F is the input fraction and M is the modulus. The modulus M can also be programmable or it may be fixed for a given implementation.
The interpolator could be, for instance, a single accumulator with the overflow bit as output or it could be a higher order sigma-delta modulator. There are numerous prior art examples of both architectures.
Fractional-N synthesizers have a number of advantages which make them desirable. Their output steps are in fractions of the reference frequency. This allows the use of larger input reference frequencies which in turn allows N to be smaller. This is a major advantage because phase noise gain from input to output is a function of N2 or 20 Log N in dB's so the noise can be much reduced by even a small reduction in N. Also, the availability of a larger reference frequency allows a wider loop bandwidth which in turn allows a shorter settling time each time the synthesizer is switched from one frequency channel to another.
By rewriting equation (1) as follows:
                              f          OUT                =                              (                          MN              +              F                        )                    ×                                    f              REF                        M                                              (        2        )            it is clear that the output will only be in phase with one out of every M edges of the input reference. This highlights a major disadvantage of fractional-N synthesizers in that the output phase can have any one of M possible values with respect to the input reference phase, where M is the fractional modulus. Which one of the M edges of the reference this will be may be different each time the channel is synthesised depending on the particular state of the interpolator when the new N and F values, which specify the channel to be synthesised, are loaded. In some applications this doesn't matter but when it is required that a particular output frequency signal has consistently the same phase relationship with a reference then this is a problem with a fractional-N synthesizer.
Prior fractional-N synthesizers have been designed to synchronize the phase output signal with the input reference signal. For example, U.S. Pat. No. 6,556,086, entitled “Fractional-N Synthesiser And Method Of Synchronisation Of The Output Phase”, incorporated herein by reference, generates a synchronization pulse at integer multiples of periods of the input reference signal and gates one of those synchronization pulses to re-initialize the interpolator of the fractional-N synthesizer in order to synchronize the phase of the output signal with the input reference signal. The design of the '086 patent produces an output signal with a resultant phase which is phase locked to the input reference signal for channels at the same frequency. One drawback of the design of the '086 patent is that it cannot be programmed to vary phase of the output signal with respect to the input reference signal. Varying the output frequency in a fractional-N synthesizer is useful in applications such as wireless systems (e.g., cellular phones) where two or more channels at the same frequency need to have different phases to reduce interference. Other possible applications of a fractional-N synthesizer with programmable output phase include phased radar systems wherein RF waves are transmitted at the same frequency but at different phases to form constructive and destructive interference, e.g., beam forming, where the beam needs to be focused on objects in the sky. Other beam forming applications of a fractional-N synthesizer with programmable output phase may include focusing RF waves of broadcasting/transmitting stations located on the coast only in the direction of the proximate land.