Integrated circuits (ICs) are manufactured by a long sequence of high-precision and hence defect-prone processing steps. Hence, every individual semiconductor product needs to undergo stringent electrical tests to identify defective parts and guarantee outgoing product quality to the customer. The process Design For Testing (DFT) is focused on developing economically adequate tests for ICs. These tests need to assure sufficient quality at acceptable test application costs, corresponding to the target application area. As no IC can be released into high-volume production without an adequate manufacturing test, acceptable test development time is also of key importance.
Structural testing, in which tests are generated based on well-accepted defect-abstracting fault models, have largely replaced traditional functional tests, because they can be generated automatically in relatively short time, achieve objectively better defect coverage, and (in case of failing tests) allow diagnosis algorithms to pinpoint the type and location of the failure root cause. The latter enables automatic high-volume diagnosis to create process learning and yield improvement.
One of the main challenges in IC testing is the limited accessibility from the external chip pins to the internal circuitry of the IC. To improve controllability and the ability to observe, additional DFT hardware can be added to the functional circuitry; this typically amounts to 5-10% of the silicon area.
Scan design is a most common form of DFT design, whereby a test mode is added in which functional registers are concatenated into one or more shift registers that are accessible from the external test equipment. More advanced forms of DFT hardware include (i) ‘wrappers’ that allows modular testing of increasingly complex chips, (ii) on-chip decompression of test stimuli and compression of test responses, (iii) circuitry that tests parts of the IC itself without the need for external test equipment (‘built-in self-test’ or BIST), and (iv) on-chip features for the benefit of the chip user.
Today's large System-on-Chip (SoC) designs present many challenges to DFT processes. Tool runtime and the amount of memory required to load designs continue to grow and stretch available resources and design schedules. For DFT, much of the design and pattern generation activity has traditionally taken place late in the design cycle which puts such activities in the critical path to tape-out. As tool runtimes increase and different design disciplines contend for the same compute resources, DFT poses an even greater barrier to a timely tape-out.
In DFT mode, there is a need to conduct power integrity checks as are also required in functional mode. Power integrity noise can impact timing as well as functional failure in DFT mode and, in severe cases, often more power integrity noise can happen in DFT mode because of the tighter nature of the clock tree configuration and clustered simultaneous switch trend of such mode.
Upon generation of a DFT testing pattern, DFT engineers typically seek to determine which pattern will satisfy the required coverage as well as power integrity impact of the generated pattern. Increasing the coverage (i.e. area or size of circuit that can be tested with a pattern, etc.), often, in general, increases the toggle rate of the SoC; however, the local power noise hot spots can randomly occur in anywhere in an SoC design.