Field effect transistors (FETs) are widely used in the electronics industry for switching, amplification, filtering, and other tasks related to both analog and digital electrical signals. Most common among these are metal-oxide-semiconductor field-effect transistors (MOSFETs), wherein a metal or polysilicon gate contact is energized to create an electric field in a channel region of a semiconductor body, by which current is allowed to conduct between a source region and a drain region of the semiconductor body. The source and drain regions are typically formed by adding dopants to targeted regions on either side of the channel region in a semiconductor substrate. A gate dielectric, such as silicon dioxide (SiO2), is formed over the channel region, and a gate contact (e.g., metal or doped polysilicon) is formed over the gate dielectric, where the gate dielectric and gate contact materials are patterned to form a gate structure overlying the channel region of the substrate.
The gate dielectric is an insulator material, which prevents large currents from flowing from the gate into the channel when a voltage is applied to the gate contact, while allowing such an applied gate voltage to set up an electric field in the channel region in a controllable manner. A continuing trend in the manufacture of semiconductor products is toward a steady reduction in electrical device feature size (scaling), together with improvement in device performance in terms of device switching speed, power consumption and reliability. New materials and processes have been developed and employed in silicon process technology to accommodate device scaling, including the ability to pattern and etch smaller device features. Recently, however, electrical and physical limitations have been reached in the thickness of gate dielectrics formed of SiO2.
By way of example, FIG. 1A illustrates a conventional CMOS device 2 with PMOS and NMOS transistor devices 4 and 6, respectively, formed in or on a silicon substrate 8. Isolation structures 10 are formed to separate and provide electrical isolation of the individual devices 4 and 6 from other devices and from one another. The substrate 8 is lightly doped p-type silicon with an n-well 12 formed therein under the PMOS transistor 4. The PMOS device 4 includes two laterally spaced p-doped source/drain regions 14a and 14b with a channel region 16 located therebetween in the n-well 12. A gate is formed over the channel region 16 comprising an SiO2 gate dielectric 20 overlying the channel 16 and a conductive polysilicon gate contact structure 22 formed over the gate dielectric 20. The NMOS device 6 includes two laterally spaced n-doped source/drain regions 24a and 24b outlying a channel region 26 in the substrate 8 (or alternatively a p-well region (not shown)) with a gate formed over the channel region 26 comprising an SiO2 gate dielectric layer 30 and a polysilicon gate contact 32, where the gate dielectrics 20 and 30 may be patterned from the same oxide layer.
Referring to the NMOS device 6, the resistivity of the channel 26 may be controlled by the voltage applied to the gate contact 32, by which changing the gate voltage changes the amount of current through channel 26. The gate contact 32 and the channel 26 are separated by the SiO2 gate dielectric 30, which is an insulator. Thus, little or no current flows between the gate contact 32 and the channel 26, although “tunneling” current is observed with thin dielectrics. However, the gate dielectric 30 allows the gate voltage at the contact 32 to induce an electric field in the channel 26, by which the channel resistance can be controlled by the applied gate voltage.
MOSFET devices produce an output current proportional to the ratio of the width over the length of the channel, where the channel length is the physical distance between the source/drain regions (e.g., between regions 24a and 24b in the device 6) and the width runs perpendicular to the length (e.g., perpendicular to the page in FIG. 1A). Thus, scaling the NMOS device 6 to make the width narrower may reduce the device output current. Previously, this characteristic has been accommodated by decreasing the thickness of gate dielectric 30, thus bringing the gate contact 32 closer to the channel 26 for the device 6 of FIG. 1A. Making the gate dielectric layer 30 thinner, however, has other effects, which may lead to performance tradeoffs, particularly where the gate dielectric 30 is SiO2.
One shortcoming of a thin SiO2 gate dielectric 30 is large gate tunneling leakage currents due to direct tunneling through the oxide 30. This problem is exacerbated by conventional limitations in the ability to deposit or grow such thin films with uniform thickness. Also, a thin SiO2 gate dielectric layer 30 provides a poor diffusion barrier to dopants, for example, causing high boron dopant penetration into the underlying channel region 26 during fabrication of the source/drain regions 24a and 24b. 
Consequently, recent efforts involving MOSFET device scaling have focused on alternative dielectric materials which can be formed in a thicker layer than scaled silicon dioxide layers and yet still produce the same field effect performance. These materials are often referred to as high-k materials because their dielectric constants are greater than that of SiO2. The relative performance of such high-k materials is often expressed as equivalent oxide thickness (EOT), because the alternative material layer may be thicker, while still providing the equivalent electrical effect of a much thinner layer of SiO2.
In one approach, such high-k dielectrics are typically deposited directly over a silicon substrate to form a gate dielectric layer of about 50 Angstroms. The performance and reliability of the resulting transistors, however, is dependent upon the quality of the interface between the high-k dielectric material and the underlying silicon.
Referring to FIG. 1B, one proposed alternative structure is illustrated, in which a high-k gate dielectric material 30a is used to form a gate dielectric layer 30′ in an NMOS device 6′. A conductive polysilicon gate contact structure 32′ is then formed over the high-k dielectric layer 30a. However, the alternative gate dielectric materials explored thus far typically include oxygen components, and are often deposited using deposition techniques, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) processes, that use oxidizing reactants.
Thus, in forming the high-k dielectric layer 30a, the upper surface of the silicon substrate 8 oxidizes, forming an unintended low quality, low-k oxide layer 30b between the substrate 8 and the high-k material 30a. The presence of this interfacial oxide layer 30b increases the effective oxide thickness, reducing the effectiveness of the alternative gate dielectric approach. In addition, the interface 30b generally has unsatisfied bonds that act as interface charging centers, causing interface states. The high density of such interface states in the low quality oxide 30b results in carrier mobility degradation in operation of the transistor 6′, where the higher the density of the interface states, the more the resulting mobility degradation. Additionally, lower quality oxides may also suffer from issues related to, among other things, charge scattering, charge trapping, fixed charge, density of interface state (Dit), carrier mobility, etc. For example, low charge scattering may be related to a high mobility type of oxide. Carriers in a channel created with a gate oxide of low charge scattering may have high mobility, for example.
Other approaches involve forming an oxide by a non-thermal means (e.g., UV-ozone oxide, UV-O3, or chemical oxides) prior to depositing the high-k material 30a, to try to mitigate the mobility degradation problem. Such non-thermal oxides are typically grown at low temperatures. While these non-thermal oxides are generally better than unintended thermal oxides formed during high-k growth (e.g., layer 30b in FIG. 1B), there is a need for better mobility than that which can be achieved with non-thermal oxides. Growing oxides at higher temperatures produces higher quality oxides, but the oxide growth rate is difficult to control as the oxidation occurs rapidly at higher temperatures. Difficulty in controlling oxide growth rates can lead to non-uniform oxides, to oxides that are too thick, or to other undesirable results. Therefore, there is a need for improved gate fabrication techniques by which high quality interfaces can be achieved between the underlying silicon and deposited high-k dielectrics.