1. Field of the Invention
This invention relates to testing of multi-layer ceramic VLSI chip packaging substrates to determine electrical properties. In particular, this invention relates to a contactless method of electrically testing laminated components.
2. Prior Art
FIG. 1 shows a portion of a multi-layer ceramic (MLC) packaging substrate. Each of the layers making up the substrate begins as a flexible unfired sheet (greensheet) of soft ceramic material. Holes (vias) are punched in the greensheets in known patterns. An electrically conductive paste is then screened through a metal mask to form personalized wiring patterns on the greensheet and to fill its via holes. The completed substrate is fabricated by stacking multiple greensheet layers that are pressed together to form a semi-hard stack or laminate, which is fired. The result is a high performance substrate for VLSI chips, with improved reliability and reduced manufacturing cost.
Many VLSI chips are mounted on top of the substrate which establishes all electrical connections to and between chips. On the top surface of the substrate, each chip site is composed of a central array of chip connect vias (C4 pads or microsockets) surrounded by one or more frames of engineering change (EC) pads. The EC pads allow correction of wiring defects by the deletion of internal wiring and its replacement with discrete surface wires.
The substrate is composed of three main regions of layers: signal redistribution, signal distribution (personalization) and power distribution. The top several layers of the substrate redistribute the signal lines from the central array of chip connect vias, first to the surrounding EC pads and then down to the signal distribution layers. The substrate's central signal distribution layers carry signals between chips and to and from input/output lines. They also provide reference signal levels to the chips. The bottom power layers distribute power and redistribute signals to the bottom surface pin pads.
The signal redistribution and power distribution layers contain fixed wiring patterns while the signal distribution layer wiring varies by substrate part number.
Individual greensheets are pressed together to form laminates. Defects can occur at this point in the manufacturing process such as opens in the via connections, opens in the horizontal line connections and shorts between lines. Following lamination, the stack of greensheets is fired in kilns to produce a multi-layer ceramic MLC substrate.
Given these processing steps, testing subsequent to firing, when the material is more easily handled, results in discarding defective modules after signficant costs have already been incurred. Testing prior to firing, while preferred on a cost basis, has been restricted to optical inspection due to the nature of the deficiencies in existing testing technology.
Given the complexity of the package, sublamination techniques have been proposed to significantly reduce the manufacturing capacity needed to produce a given number of MLC substrates. Sublamination comprises dividing a stack of greensheets needed to produce a complete substrate into several sub-stacks. Typical are power/voltage, personalization and, redistribution sub-stacks. These sub-stacks, comprising in the order of several tens of layers in some cases, are fabricated, pressed to form sublaminates, and independently tested. A set of tested sublaminates is then pressed to form a completed unfired stack or laminate. Given these manufacturing steps, an electrical test capability to determine whether open or short circuit conditions exist in a variety of different connection paths is essential. This test capability should exist prior to firing the laminates so that defective sublaminates may be discarded prior to completing the laminate. It is crucial that the rate of tesing be commensurate with the rate of manufacture of the substrates so that "on-line" testing can take place.
Sublaminates in the unfired state are formed from materials that are soft and easily damaged. Accordingly, prior art testing techniques utilizing some form of mechanical contact cannot be readily employed with these substrates. Any contact to the soft sublaminate structure will easily introduce depressions into the microsockets which are required to be dent free. Additionally, some external level variations are acceptable if the vias are only partially filled with conductive paste. A partial filling of vias occurs randomly and results in the imposition of conflicting requirements if mechanical contacting is employed. Such techniques must be able to contact lines which are several mils high as well as over-filled, filled and partially filled vias, simultaneously. Proposed mechanical contacting techniques that handle height variations in the order of several mils have yet to be proven reliable. They have, however, demonstrated a high probability of creating defects when the mechanical contact is removed.
Testing using human operators is not compatible with current manufacturing rates. Computer controlled handling techniques, however, are well established. Computer control in some areas of testing is also known, but integration of the tasks is still largely experimental.
In order to avoid the difficulties of mechanical probe testing of the described specimens, testing in a non-contact mode has been suggested. The prior art is replete with electron beam techniques for electrical continuity testing of semiconductor devices. U.S. Pat. No. 3,373,353 relates to the testing of sheets of dielectric material and particularly to the achievement of local measurements of thickness for detecting thickness defects. A low energy scanning electron beam charges the surface to cathode potential in a manner compatible with photoconductive target charging in a vidicon camera tube. The current through the dielectric layer to its conductive backing is measured with an electronic potential applied to the conductive backing, thereby generating a potential difference across the dielectric.
U.S. Pat. Nos. 3,763,425 and 3,764,898 both relate to non-contact continuity testing of conductors utilizing electron beams. Both measure the resistance of conductors on or embedded in an insulating matrix. A pair of individually controlled electron beams are used which must simultaneously address both ends of the conductor under test. In both patents, special masks are employed, individually tailored to the configuration of conductors of the specimen under test. As shown, for example, in FIG. 3 of the 3 898 patent, the mask may be a complex structure that makes loading and unloading of specimens difficult, thereby inhibiting thruput in manufacturing lines. In both patents, the masks stabilize the potential on the specimen surface and act as collecting and measuring electrodes. In the case of the '425 patent, the masks are used to generate secondary electrons for excitation of the target. Optimization of the operating parameters of the system can be attained, but only with a throughput penalty resulting from interference in the changing of specimens due to the use of such masks. Other systems utilizing mask techniques include U.S. Pat. Nos. 3,678,384 and 4,164,658.
The prior art also includes a number of proposals to use electron beam techniques in diagnostic analysis of electronic circuits. U.S. Pat. No. 4,139,774 relates to an electron beam apparatus that eliminates specimen staining which is caused by contamination in vacuum pumps. The system is designed for specimen surface analysis and not electrical testing. U.S. Pat. No. 4,172,228 utilizes a scanning electron microscope (SEM) to irradiate selected areas of an integrated circuit until failure occurs. U.S. Pat. No. 4,169,244 relates specifically to electron probes for testing electronic networks. The system requires electrical stimulation of the unit under test by means of external electronics.
I.B.M. Technical Disclosure Bulletin, Vol. 12, No. 7, December, 1969 discloses in very general terms the use of two separately controlled but simultaneously active scanning electron beams. The system is therefore similar to that disclosed in U.S. Pat. Nos. 3,763,425 and 3,764,898. The beams are focused at two distinct points in the array and the potential which exists at one energizing point is measured by capturing scattered secondary electrons with a pickup and measuring device.
I.B.M. Technical Disclosure Bulletin, Vol. 23, No. 5, October 1980, discloses a system that generates a voltage contrast at test points of a specimen utilizing a scanning Auger microprobe (SAM) or a scanning electron microscope (SEM) by biasing the specimen. The testing of IC chips occurs where the biasing corresponds to binary zero and one logic levels. Although the system is contactless and utilizes a commercially available electron beam instrument, it is not suited for testing large area specimens having a dielectric matrix or when physical electrical connections to the specimen are not present. Another SEM technique for testing IC chips is disclosed in I.B.M. Technical Disclosure Bulletin, Vol. 23, No. 7A, December 1980. The system is not contactless, utilizing multiple connections to the chips on a module to drive them. The system is therefore not suitable for soft unfired multi-layer ceramic materials.