1. Field of the Invention
The invention relates to a semiconductor device, and more particularly to a junction type field-effect transistor (FET) capable of high speed operation.
2. Description of the Related Art
A junction type field-effect transistor, which is hereinbelow referred to simply as a junction type FET, adopts p-n junction in a gate, and changes a width of a channel by controlling a width of a depleted layer extending from the junction with a voltage applied to the p-n junction, to thereby control a current running between a source electrode and a drain electrode. A junction type FET including a chemical compound semiconductor, in particular, such as GaAs is superior in high frequency characteristics.
FIG. 1 illustrates a typical structure of a prior junction type FET. On a semi-insulating GaAs substrate 101 is formed a n-type GaAs layer 107 operating as a channel layer. On the n-type GaAs layer 107 are formed p.sup.+ type GaAs layer 103, a drain electrode line 111 and a source electrode line 112. The p.sup.+ type GaAs layer 103 is disposed between the drain electrode line 111 and the source electrode line 112. On the p.sup.+ type GaAs layer 103 is formed a gate electrode line 113. A depleted layer (not illustrated) extends from a p-n junction which is to be formed between the p.sup.+ type GaAs layer 103 and the n-type GaAs layer 107, mainly toward the n-type GaAs layer 107. A width of the depleted layer is controlled by a voltage applied to the gate electrode line 113 to thereby control a current running between the drain electrode line 111 and the source electrode line 112.
A diffusion potential of a p-n junction which restricts a forward signal voltage amplitude of a gate of a normally off junction FET is able to be increased up to a potential nearly equal to a band gap of a semiconductor forming the p-n junction. In the junction type FET illustrated in FIG. 1, there can be obtained approximately 1.2 volts which is sufficient for operation of the junction type FET.
In addition, a high gate voltage can be applied to a gate of the above mentioned junction type FET, and hence it is possible to set a saturation current to be high to thereby obtain a high mutual conductance. As a result, a high speed operation of LSI can be achieved.
In the above mentioned prior junction type FET, since a width of a gate electrode layer is determined by etching crystals by means of lithography technique, it was quite difficult to remarkably shorten a gate length. A dimension of a minimum pattern to be formed by crystal etching is approximately 0.5 .mu.m in the present technique. Thus, it is impossible to shorten a gate length of a junction type FET to be shorter than 0.5 .mu.m, and thereby it is also impossible to further increase an operation speed of a junction type FET.