(1) Field of the Invention
The present invention relates to the field of computer aided design (CAD) systems for integrated circuit (IC) designs. Specifically, the present invention relates to the field of CAD systems for implementation of design for test (DFT) circuitry.
(2) Prior Art
Complex integrated circuits (ICs) are designed with the use of computer aided design (CAD) tools. Specifically, application specific integrated circuits (ASICs) and field programmable gate array (FPGA) circuits are designed using a variety of CAD tools. The development of IC custom designs (e.g., ASICs and FPGA circuits) with the aid of CAD tools is referred to as electronic design automation or EDA. Design, checking and testing of large scale integrated circuits are so complex that the use of programmed computer systems are required for realization of normal IC designs. This is partly because the integrated devices are inherently complex and partly because an IC design can be decomposed into simpler functions and units which can be effectively processed by a computer system. CAD systems are also used in IC designs because considerable computation is required in order to achieve an efficient substrate layout (e.g., placement) of the resultant IC design. The result of the computerized design process is a detailed specification defining a complex integrated circuit in terms of a particular technology. This specification can be regarded as a template for the fabrication of the physical embodiment of the integrated circuit using transistors, routing resources, etc.
As part of the CAD system for fabricating ICs, design for test (DFT) circuitry and techniques are utilized to integrate circuit elements into an IC design which allow for circuit testability. Generally, DFT circuitry can require the replacement of certain cells in an IC design with specialized cells that allow for the application of test vectors (bit strings) to circuitry within the IC design (e.g., "circuit stimulus"). Furthermore, the DFr circuitry also captures the output of the IC circuitry in response to the circuit stimulus and reports this output for comparison against a stored reference output. In one particular DFT methodology, sequential cells are used to shift serial test vectors into the IC design, apply the test vectors to the IC circuitry, capture the circuitry's output and then serially shift the output data for comparison. In this methodology, the DFT cells that serially shift in the test vectors are referred to as scan cells and they are linked together to form scan chains. a single scan chain receives input test vector data and supplies the response data. A single IC design can contain multiple scan chains.
An IC design can contain many subdesigns (modules) which likewise can contain subdesigns therein. Under this topology, the top level of an IC design typically includes a hierarchical structure of interconnected circuit modules. Furthermore, the various modules of an IC design are typically assigned to and developed by different groups of people working under common direction from top level designers and architects. It is desirable to apply DFT circuitry throughout a hierarchical IC design. Therefore it is desirable to apply DFT circuitry to the top level of the IC design and also to any modules (subdesigns) located therein so that the entire IC design can be properly tested. Since different modules of an IC design can be independently developed, it would be desirable to allow independent development and insertion of DFT circuitry for individual modules.
Unfortunately, within prior art CAD systems that automatically construct DFT circuitry, their scan architecture processes generally recognize: 1) scan cells; and 2) complete scan chains that commence at a primary input and end at a primary output of the "chip." Therefore, in constructing a complete scan chain by integrating modules designs, any DFT routing circuitry already present within a module is eliminated by prior art CAD systems and scan paths within the module are then reconstructed using heuristics pertinent to the CAD system and using configurations defined at the top level design. This prior art approach is inefficient in that DFT circuitry located within modules is removed and re-architected instead of directly integrated in larger scan chains. This approach is also inefficient in that same DFT circuitry located in replicated modules is not re-used by the prior art CAD systems.
The above prior art approach is also problematic because it does not allow DFT implementation to be spread among many module designers. It is desirable to allow module designers to implement subdesign scan chains so that the process of adding DFT circuitry can be spread among many designs. By spreading the DFT implementation across modules, the overall time required to generate the integrated DFT implementation in a hierarchical design can be decreased and efficiency increased. Also, by allowing a subdesigner to implement subdesign scan chains which are later used during integration, certain risks associated with DFT integration (e.g., not finding scan design rule violations earlier in the design flow) can be reduced allowing the DFT integration to flow more smoothly with less unexpected problems. Furthermore, since module designers are capable of optimizing their designs, it is desirable not to remove and redesign subdesign scan chains within existing modules because these modifications can risk creating constraint violations within the modified modules. In effect, the act of removing the scan chains and adding new scan structure to an existing module, as done in the prior art, can violate specified constraints that are otherwise satisfied by the original optimized module design.
It is appreciated that some prior art CAD systems allow existing DFT circuitry of a module to be manually presented and used by the top level DFT design. Although this method provides some ability for the module designers to provide DFF information for the top level DFT processes, the requirement that this information be manually entered and maintained is economically expensive for almost all IC designs.
Also, in certain DFT implementations, the time required to perform scan insertion is relatively long. It is desired to provide a mechanism and system allowing a user to observe certain results of the scan insertion, for purposes of DFT designing, without requiring the full scan insertion duration or making actual design modifications.
Accordingly, what is needed is a CAD system and mechanism for effectively allowing top level DFT processes to automatically integrate DFT designs located within modules in order to architect top level scan chains. Further, what is needed is a CAD system and mechanism as above for allowing automatic construction of scan chains within modules when none currently exist. What is further needed is a mechanism and system allowing a user to observe certain results of the scan insertion, for purposes of DFT designing, without requiring the full scan insertion duration. Also, what is needed is a system for allowing user specifications for controlling the above processes. The present invention provides these advantageous functionalities. Under the present invention, a designer of a module within an IC design can independently generate a subdesign scan chain that can be later used by the DFT processing of the top level. Therefore, under the present invention, the module designer can effectively "sign off" his or her work at the completion of the module design and their completed and optimized modules do not need to be later disrupted, and possibly risk constraint violations, during DFT processes of the top level.