Modern computer systems are often implemented as multiprocessor systems wherein a plurality of processors are coupled to one another by, e.g., a bus. In addition to being coupled to the bus, each processor in the computer system my, for example, also be coupled to a data transmission service for the receipt and transmission of messages via the transmission service.
In the operation of the computer system it is often necessary for the processors to communicate messages to one another. Messages which are intended to be communicated by one processor to another processor may include, e.g., messages generated by one of the processors or messages received by one of the processors via the data transmission service coupled to the processor.
The processor generating the message or receiving the message from a transmission service is referred to as the source processor while the processor to which the message is being passed is referred to as the destination processor.
In one known scheme for passing messages between processors, each message is stored in a buffer by the source processor. The source processor then passes a pointer to the buffer which contains the message, to the destination processor to which the message is directed. The destination processor may then utilize the pointer to read the message from the buffer.
Once the message is read from the buffer, the destination processor may, e.g., as required, respond to the message or retransmit the message via the transmission service coupled to the destination processor. As should be understood, each processor can be either a source or destination of messages.
The known buffer pointer passing scheme prevents temporary input/output bandwidth crunches at any particular destination processor, as might occur, e.g., if each entire message was directly transmitted to the destination processor and several source processors needed to forward messages to the particular destination processor during the same time period. The passing of pointers permits each destination processor to schedule the movement of messages from the appropriate buffers to the respective destination processor. A particular destination processor can readily receive and store pointers and access the associated buffers for the full messages over a time period consistent with the input/output bandwidth of the particular destination processor.
The buffers used to communicate messages can all be arranged in a shared central memory, coupled to the bus. The use of a central memory simplifies the overall design requirements for the buffer system and provides flexibility in the allocation of buffers between processors. At initialization time, each source processor is allocated a number of buffers within the central memory consistent with the amount of message traffic expected from that source.
While the known buffer pointer approach to multiprocessor communication provides an advantageous scheme for effectively passing messages between processors, the scheme does not adequately provide for the detection of errors, such as illegal accesses to buffers in the shared central memory, which may occur during communication between various processors of the computer system. Such illegal accesses may include, for example, accesses by a processor to a buffer which does not contain a message intended for the processor accessing the particular buffer.
Accordingly, in the known system, errors which are caused by, e.g., faulty system components may go undetected with the potential result of unrecoverable errors in the communication of messages between processors and the loss of data.
In addition to failing to detect buffer access errors, the known buffer swapping scheme does not maintain a record of system buffer ownership, including a record of the buffer's recent history in terms of processor accesses, which may be necessary to allow for diagnosis of errors in the buffer system. Such a record of buffer ownership may also be necessary to recover buffers allocated to faulty system components.
Accordingly, the known buffer swapping scheme fails to provide an adequate means for error detection and correction with regard to processor accesses to the buffers which comprise the computer system's memory.