In order to produce competitive electronic devices, it is often desired to produce semiconductor chips with several different regions (e.g., core region, low power region, I/O region) having semiconductor devices that vary according to speed and power, for example. Semiconductor devices that provide some or all of these features include silicon-on-insulator (SOI) devices. An existing challenge in SOI technology, however, is forming thin Si channel SOI I/O devices with significant voltage threshold (Vth) control. For example, in an SOI I/O application, a higher Vth is necessary because SOI devices suffer from a larger drain induced barrier lowering (DIBL) effect (which is caused by the floating body characteristics) than do bulk silicon wafer devices. Further, the higher voltages typically applied in the I/O regions increase the concern regarding leakage current. Overcoming these shortcomings will become increasingly significant as SOI device thickness is scaled down to improve performance and to reduce the floating body effects.
Several known methods attempt to control Vth by controlling the body potential of the SOI transistor. A first method is to tie the transistor body to a fixed voltage level through a substrate contact. However, despite reducing the floating body effect (FBE) in SOI devices, the body-tied method may suffer from area and speed penalties. In addition, the benefits obtained by the body-tied method may diminish as SOI silicon thicknesses scale downward because the increasing body resistance will make the body contact useless.
Another known body method for controlling Vth is channel region doping. Despite raising the Vth, however, channel implants reduce the depletion ability of an SOI device, thereby incurring performance degradation from the FBE.
Another commonly used method for FBE reduction is to fully deplete (FD) the channel region of the SOI device by thinning the silicon thickness. The FD SOI device enables an additional impact ionization (I-I) induced carrier sweep out of the channel, thereby suppressing the FBE. Substantial suppression of the FBE in the transistor channel region significantly enhances voltage threshold control.
Biasing the body region of an SOI transistor is conventionally an important part of device Vth control, and thinning the silicon body thickness has become a preferred method that contributes to Vth control. However, there is still a need for SOI technology with the capacity to provide sufficient back gate bias to achieve desired Vth values.
Another known and accepted method of achieving a desired Vth is to modify the gate electrode work function by modifying the material composition of the gate electrode. FIGS. 1a and 1b show known devices 100 and 102, in which the gate electrode 104 material composition, and correspondingly the gate electrode 104 work function, is varied to control the voltage threshold of the devices. The CMOS structure 100 shown in FIG. 1a is disclosed by Polishchuk, et al. in a paper entitled “Dual Work Function Metal Gate CMOS Transistors by Ni—Ti Interdiffusion,” IEEE Electron Device Letters, Vol. 23, No. 4, April 2002, incorporated herein by reference. FIG. 1a shows a gate electrode 104 comprising nickel and titanium over the PMOS region 106 and comprising titanium over the NMOS region 108.
The FD SOI transistors 102 shown in FIG. 1b and disclosed by H. Wakabayashi in a paper entitled “A Novel W/TiNx Metal Gate CMOS Technology Using Nitrogen-Concentration-Controlled TiNx Film,” IEEE IEDM, December 1999, which paper is incorporated by reference herein, have gate electrode 104 material compositions of tungsten W, titanium Ti, a first concentration of nitrogen N and a second concentration of nitrogen Nx. The variation of material composition varies the gate work function of each gate electrode 104, thereby varying the voltage threshold of the FD SOI transistors 102.
FIGS. 1a and 1b show gate electrode material composition variation within a small region of the chip. It is difficult, however, to apply different gate work function materials for SOI core applications and I/O device applications on the same chip, for example. In the conventional circuit application, the threshold voltage for a 3.3 eV I/O device is about 0.65 eV and the threshold voltage for a 1.0 eV core device is about 0.2 eV. The target threshold voltages are achieved by using a well or a pocket implantation in the bulk substrate. However, for a fully-depleted SOI device, the threshold voltage cannot be adjusted by the channel or pocket implantation because heavy substrate concentration will turn the FD device into a partially depleted device and degrade the performance. One method to achieve a different threshold voltage for a fully depleted SOI device is to change the gate work function. This can be demonstrated with reference to the following formula:
  Vth  =                              Φ          ms                -                              Q            f                                C            ox                                      V        FB              +          Φ      s        +                            2          ⁢          ɛ          ⁢                                          ⁢                      qN                          A              ⁡                              (                D                )                                              ⁢                      Φ            s                              Cox      For example, if we keep the Na (substrate concentration) constant, we may need another variable to control the threshold voltage to a desired value in a different application. The gate workfunction (φm) is a good candidate for Vth tuning because recently metal gate development has become mainstream technology. This is because metal gates not only improve gate resistance, but they also show better characteristics, compared to polysilicon, in integrating with high-k dielectric materials, as illustrated in FIG. 1c. 