1. Field of the Invention
The present invention relates to an isolation process using high pressure field oxidation.
2. Background of the Related Art
Integrated circuits depend upon electrical isolation between various components on a chip in order to operate properly.
The isolation technique used depends, in part, upon the type of integrated circuit that is being fabricated, and, more specifically, the minimum achievable dimensions of the circuit components being manufactured.
Isolation techniques, generally, form a thick oxide between different circuit components to isolate these components. Different isolation techniques have different advantages, but it is desirable to keep the isolation technique process as simple as possible, while also fabricating an integrated circuit that has repeatable, high quality isolation between components. Simple processes may not provide sufficient isolation, whereas overly complex processes that provide excellent isolation may not be repeatably performed in a cost effective manner.
Current sub 0.35 micron isolation processes typically utilize recessed field oxidation techniques to form an isolation region between active regions on an integrated circuit chip. Generally, a shallow trench isolation (STI) technique is used.
The typical LOCOS masking operation using layers of silicon dioxide, silicon nitride and photoresist are used to define the active regions. After the photomasking operations a plasma etch is used to remove the nitride and oxide in the open areas to expose the silicon at areas where the shallow trench is desired. A plasma silicon etch is used to form the shallow trench in the open areas that has 80-85 degree sidewalls, which shallow trench then serve as the starting point to achieve the desired isolation between transistors. After the etch, the photoresist is removed and a thin oxide is grown in the exposed trench. At this point in the process, ions can be implanted to form the wells and to introduce dopants on the sidewalls of the trench to prevent inversion regions on the sidewalls of the trench. The trenches are then filled, typically with a deposited oxide, which is then polished back to the silicon nitride layer covering the active regions.
This shallow trench isolation technique, though widely used, has disadvantages that the present inventors have identified, including:
1) A sharp active edge at the oxide filled trench region leading to gate oxide reliability problems;
2) Long CMP polishing times leading to non-uniformity, dishing and erosion problems;
3) A step with greater than 85 degree or re-entrant from the isolation oxide to the active region, causing gate oxide polysilicon stringers;
4) Multiple processing steps, in addition to the steps used in conventional LOCOS operations;
5) Design issues because of CMP dishing, including the creation of dummy patterns or design rule limitations;
6) CMP is a dirty process, particles and impurities in slurry, causing post CMP clean operations to be complicated;
7) Trench depth control is difficult because an endpoint cannot be established; and
8) The angle of the trench has to be less than 90 degrees, typically around 85 degrees, in order to prevent high stress regions in the active region, which angle undesirably enhances transistor leakage.
In addition to the above identified disadvantages, the above described operation used to create a STI structure is, undesirably, very expensive due to the large number of processing steps involved and the expensive equipment needed to implement them. Accordingly, a need exists for a new isolation method that is particularly suited for even smaller dimension integrated circuit devices, such as 0.35 um, which method overcomes the disadvantages of current isolation techniques.