Before explaining the present invention, a conventional semiconductor test apparatus will be first described with reference to FIG. 5 in order to facilitate understanding of the present invention.
As shown in FIG. 5, a semiconductor test apparatus is generally constituted of a timing generator 1a, a pattern generator 2, a waveform formatter 3 and a logic comparator 5.
The timing generator 1a outputs a delayed clock signal obtained by delaying a reference clock signal as much as a predetermined time by use of a variable delay circuit 11a. The variable delay circuit 11a is constituted of a plurality of delay devices which respectively generate delay times different from each other. Further, a delay time which is approximately twofold of a delay time of a delay device on a precedent stage is sequentially set to each delay device in order to realize an efficient combination.
The pattern generator 2 outputs a test pattern signal and an expected pattern signal in synchronization with the delayed clock signal.
The waveform formatter 3 formats the test pattern signal to a necessary waveform and inputs a result to a semiconductor device (which will be also abbreviated as a “DUT” (Device Under Test) hereinafter) 4 as a test target.
Furthermore, the logic comparator 5 compares a response output from the DUT 4 with an expected data signal. Therefore, it detects a failure of the DUT based on the match/mismatch.
Here, an operation timing of the semiconductor test apparatus is determined based on the delayed clock signal outputted from the timing generator 1a. The timing generator la delays a reference clock as much as a desired delay time and generates a delayed clock by using a combination of the plurality of delay devices constituting the variable delay circuit 11a. 
The respective delay devices constituting the variable delay circuit generally have different structures depending on bands of delay times. For example, as a delay device which generates a delay time longer than a clock cycle, a flip-flop is used. Combining the flip-flops can readily obtain a delay time which is an integral multiple of the clock cycle. For example, when the clock cycle is four nano-seconds (ns), a delay time which is an integral multiple of this clock cycle can be easily obtained.
As a delay device which generates a delay time longer than a delay quantity corresponding to two stages of inverters, inverters connected in series are usually used. Further, as a delay device which generates a delay time shorter than a delay quantity corresponding to two stages of inverters, load capacitances of inverters are usually used.
An example of a conventional variable delay circuit will now be described with reference to FIG. 6.
In the variable delay circuit shown in FIG. 6, two delay devices 130 and 140 obtained by connecting multi-stages of inverters with each other are connected with three delay devices 100, 110 and 120 using load capacitances in series.
The delay device 140 is constituted of a delay path 143 obtained by connecting four stages of inverters in series, a bypass 142 of this delay path, and a path selection unit 141 which selects the delay path 143 or the bypass 142 based on a value of a bit D4 in path data. When the delay path 143 is selected, the delay device 140 generates a delay time t4.
The delay device 130 is constituted of a delay path 133 obtained by connecting two stages of inverters in series, a bypass 132 of this delay path, and a path selection unit 131 which selects the delay path 133 or the bypass 132 based on a value of a bit D3 in path data. When the delay path 133 is selected, the delay device 130 generates a delay time t3.
Furthermore, in the delay devices 100, 110 and 120, a load capacitance C is connected to each inverter through a switching device. Moreover, the switching device is opened/closed based on values of bits D0, D1 and D2 in path data. In the respective delay devices, when the switching device is closed (when a conduction state is obtained), delay times t0, t1 and t2 are respectively generated.
The path data (D0 to D4) which specifies a combination of the delay devices is associated with the delay time, and it is stored in a linearization memory 12 (see FIG. 5) in the order of delay times. As a result, specifying the path data can generate a delayed clock with a desired delay time.
Meanwhile, in the variable delay circuit constituting the timing generator, the quality of the delay devices varies, and a delay time of each delay device has an error relative to a designed value. Thus, there may occur a large error between a delay time which is actually given based on a combination of the delay devices and an originally designed delay time.
As a result, intervals of the delay times obtained by combining the delay devices vary, thereby deteriorating a time resolution of the variable delay circuit. Therefore, since the variable delay circuit must be recreated in order to realize the timing accuracy according to a design, it can be a factor of a delay in an development work period.
A description will now be given as to a case that designed delay times of the delay devices 100, 110 and 120 shown in FIG. 6 are t0=2 ps, t1=4 ps and t2=8 ps, respectively. In this case, it is possible to generate delay times t0=2 ps, t1=4 ps, t0+t1=6 ps, t2=8 ps, t2+t0=10 ps, t2+t1=12 ps, and t2+t1+t0=14 ps by combining the three delay devices. In this case, since intervals between the respective delay times are all 2 ps, the time resolution is 2 ps.
However, when the delay time to of the delay device 100 greatly deviates from the designed value 2 ps for example, irregularities are produced in intervals of the generated delay times, thereby lowering the time resolution. For example, when t0=1 ps, the delay times are t0=1 ps, t1=4 ps, t0+t1=5 ps, t2=8 ps, t2+t0=9 ps, t2+t1=12 ps, and t2+t1+t0=13 ps. In this case, there may occur a case that a maximum interval between the delay times is 3 ps. Therefore, the time resolution is lowered to 3 ps.
In order to narrow the intervals between the delay times, it can be considered to increase the number of the delay devices constituting the variable delay circuit and narrowing each delay time difference itself between the delay devices.
However, when the number of the delay devices is increased, the number of bits in the path data used to select the delay device must be also increased. As a result, a memory capacity of the linearization memory is increased.
Therefore, in view of the above-described problems, it is an object of the present invention to provide a timing generator which can absorb an error in delay time of a variable delay circuit and suppress deterioration in timing accuracy from a designed value to a minimum level, and a semiconductor test apparatus including this timing generator.