This invention relates to a laminated substrate and, more particularly, to a laminated substrate fabricated from a pair of silicon wafers bonded to each other without contact between a single crystal silicon layer and an insulating layer selectively formed on one of the silicon wafers.
A laminated substrate structure such as an SOI (Silicon On Insulator) substrate is fabricated through a bonding process, and is appropriate for a semiconductor power device. The laminated substrate is available for a CMOS (Complementary Metal Oxide Semiconductor) device of the next generation.
An intelligent power integrated circuit device contains a power circuit for controlling a large amount of electric power and a peripheral circuit for controlling the power circuit, and the laminated substrate is expected to electrically isolate the peripheral circuit from the power circuit and enhance the reliability of the intelligent power integrated circuit device.
Japanese Patent Publication of Unexamined Application No. 4-29353 discloses a process of fabricating the laminated substrate, and FIGS. 1A to 1C illustrates the prior art process disclosed therein. The prior art process starts with preparation of a lightly-doped n-type silicon substrate 1. A photo-resist etching mask (not shown) is patterned on the lightly-doped n-type silicon substrate 1, and the lightly-doped n-type silicon substrate 1 is selectively etched away by using a reactive ion etching technique. As a result, a shallow recess is formed in a surface portion of the lightly-doped n-type silicon substrate 1, and a step takes place between the bottom surface of the shallow recess and the major surface of the lightly-doped n-type silicon substrate 1. The photoresist etching mask is stripped off.
The lightly-doped n-type silicon substrate 1 is thermally oxidized, or silicon dioxide is deposited over the entire surface of the lightly-doped silicon substrate 1. The lightly-doped n-type silicon substrate 1 is covered with a silicon dioxide layer 2, and the silicon dioxide layer 2 conformably extends over the major surface of the lightly-doped n-type silicon substrate 1 as shown in FIG. 1A.
Subsequently, the silicon dioxide layer 2 is polished or uniformly etched until the lightly-doped n-type silicon substrate is exposed again, and tile silicon dioxide layer 2 is left in the shallow recess. The silicon dioxide layer 2 is coplanar with the lightly-doped n-type silicon substrate 1, and forms a flat surface 3 as shown in FIG. 1B.
Another heavily-doped n-type silicon substrate 4 is prepared, and the flat surface 3 is bonded to the major surface of the lightly-doped n-type silicon substrate 4 as shown in FIG. 1C. The resultant semiconductor structure is treated with heat, and the heat treatment enhances the unity. The lightly-doped n-type silicon substrate 1 is polished until broken line 5, and provides a single crystalline silicon layer With a flat major surface.
A trench isolation is formed in the prior art substrate described hereinbefore as follows. An insulating layer is formed on the flat major Surface of the single crystalline silicon layer 1, and is selectively etched so as to form an insulating pattern (not shown). Using the insulating pattern as an etching mask, alkaline etchant selectively removes the single crystalline silicon layer 1 so as to form a trench (not shown). The trench is formed between an area assigned to a vertical power transistor and an area assigned to a controlling circuit, and further divides the area assigned to the controlling circuit into active areas for fabricating circuit components.
The resultant semiconductor structure is thermally oxidized so as to grow silicon dioxide, or silicon dioxide is deposited through a low-temperature chemical vapor deposition. As a result, inner surfaces defining the trench are covered with a thin silicon dioxide layer (not shown). Polysilicon is deposited over the entire surface of the resultant semiconductor structure by using a chemical vapor deposition. The polysilicon fills the secondary trench defined by the thin silicon dioxide layer, and swells into a polysilicon layer (not shown) over the major surface of the single crystalline silicon layer. The polysilicon layer and the thin silicon dioxide layer are uniformly removed until tile single crystalline silicon layer 1 is exposed, again, by using a polishing or an etching, and the remaining silicon dioxide layer and the remaining polysilicon form a trench isolation in tile trench.
Another laminated substrate is disclosed in Japanese Patent Application No. 6-156451, and FIGS. 2A to 2C illustrate the prior art process for fabricating a laminated substrate. The process starts with preparation of a lightly-doped n-type single crystalline silicon substrate 6. The major surface of the lightly-doped n-type single crystalline silicon substrate is thermally oxidized so as to form a silicon oxide layer (not shown), which is uniform in thickness. A photo-resist etching mask (not shown) is patterned on the silicon oxide layer, and the silicon oxide layer is selectively removed by using a dry etching. Thereafter, using the remaining silicon oxide layer as an etching mask, the lightly-doped n-type single crystalline silicon substrate 6 is partially etched away so as to form a shallow recess, and a step takes place between the bottom surface of the shallow recess and the major surface of the lightly-doped n-type single crystalline silicon substrate 6. The remaining silicon oxide layer is etched away.
Insulating material is deposited over the entire surface of the resultant semiconductor structure. The insulating material fills the shallow recess, and swells into an insulating layer 7 over the major surface of the lightly-doped n-type single crystalline silicon substrate 6 as shown in FIG. 2A.
The insulating layer 7 is uniformly polished or etched away until the lightly-doped n-type single crystalline silicon substrate 6 is exposed. The insulating layer 7 is left in the shallow recess, and the upper surface of the insulating layer 7 is coplanar with the major surface of the lightly-doped n-type single crystalline silicon substrate 6.
Polysilicon is deposited over the entire surface of the resultant semiconductor structure, and forms a polysilicon layer 8. The polysilicon layer 8 is polished, and a smooth surface 9 is created through the polishing as shown in FIG. 2B.
A heavily-doped n-type silicon substrate 10 is bonded to the smooth surface 9 as shown in FIG. 2C, and the lightly-doped n-type single crystalline silicon substrate 6 is polished until broken line 11 so as to regulate the lightly-doped n-type single crystalline silicon layer 6 to a target thickness.
A trench isolation is formed in the prior art substrate described hereinbefore as follows. An insulating layer is formed on the flat major surface of the single crystalline silicon layer 6, and is selectively etched so as to form an insulating pattern (not shown). Using the insulating pattern as an etching mask, alkaline etchant selectively removes the single crystalline silicon layer 6 so as to form a trench (not shown). The trench is formed between an area assigned to a vertical power transistor and an area assigned to a controlling circuit, and further divides the area assigned to the controlling circuit into active areas for fabricating circuit components.
The resultant semiconductor structure is thermally oxidized so as to grow silicon dioxide, or silicon dioxide is deposited through a low-temperature chemical vapor deposition. As a result, inner surfaces defining the trench are covered with a thin silicon dioxide layer (not shown). Polysilicon is deposited over the entire surface of the resultant semiconductor structure by using a chemical vapor deposition. The polysilicon fills the secondary trench defined by the thin silicon dioxide layer, and swells into a polysilicon layer (not shown) over the major surface of the single crystalline silicon layer. The polysilicon layer and the thin silicon dioxide layer are uniformly removed until the single crystalline silicon layer is exposed, again, by using a polishing or an etching, and the remaining silicon dioxide layer and the remaining polysilicon form a trench isolation in the trench.
The prior art laminated substrate shown in FIG. 1C encounters a problem in that a malfunction takes place in the vertical power transistor fabricated thereon. The malfunction is derived from voids between the surface of the lightly-doped n-type silicon layer 1 and the major surface of the heavily-doped n-type silicon substrate 4. The lightly-doped silicon and the silicon dioxide is different in polishing rate or etching rate, and the silicon dioxide layer 2 unavoidably projects from the major surface of the lightly-doped n-type silicon substrate 1. It is impossible for the polishing technology and the etching technology presently available to uniformly etch both semiconductor and insulating materials and, accordingly, to decrease the step less than 10 nanometers. As a result, the lightly-doped n-type silicon layer 1 is not strongly bonded to the heavily-doped n-type silicon substrate 4, and, accordingly, is liable to be separated from each other. When the void takes place between the semiconductor layers assigned to the vertical power transistor, the current is decreased.
The prior art laminated substrate shown in FIG. 2C is free from the malfunction due to the voids, because the heavily-doped n-type silicon substrate 10 is directly bonded to the smooth surface 9 of the polysilicon layer 8. However, the smooth surface 9 requires the deposition of polysilicon and the polishing, and these additional steps increase the production cost of the prior art laminated substrate.
It is therefore an important object of the present invention to provide an laminated substrate, which is low in production cost without separation between semiconductor layers.
It is also an important object of the present invention to provide a process for fabricating the laminated substrate.
To accomplish the object, the present invention proposes to retract an insulating layer from the major surface of a semiconductor layer.
In accordance with one aspect of the present invention, there is provided a semiconductor substrate used for a semiconductor device, and the semiconductor substrate comprises a first semiconductor substrate having a first major surface, an insulating layer selectively formed in the first major surface, and having an upper surface retracted from the first major surface for forming a recess and a second semiconductor substrate having a second major surface bonded to the first major surface.
In accordance with another aspect of the present invention, there is provided a process for fabricating a semiconductor substrate comprising the steps of preparing a first semiconductor substrate having a first major surface and a second semiconductor substrate having a second major surface, selectively growing an insulating layer on the first major surface, partially removing the insulating layer so as to retract an upper surface of the insulating layer from the first major surface, bonding the first major surface to the second major surface so as to obtain a composite substrate, treating the composite substrate with heat so as to enhance the bond between the first semiconductor substrate and the second semiconductor substrate and regulating the composite substrate to a target thickness.