Devices fabricated using silicon-on-insulator (SOI) substrates provide certain performance improvements, such as lower parasitic junction capacitance, in comparison with comparable devices built directly in a bulk silicon substrate. However, semiconductor manufacturers have recognized that straight scaling of either silicon-on-insulator (SOI) device structures or bulk (e.g., non-SOI) device structures cannot improve integrated circuit performance at a rate sufficient to continue current historical trends. To overcome these performance restrictions imposed by physical scalability limitations, integrated circuit designers are exploring other avenues for enhancing device performance. In particular, structural innovations for making smaller and faster transistor devices that consume less power are being explored as alternatives to straight scaling.
Generally, SOI substrates include a thin active layer of silicon partitioned into discrete electrically-isolated islands or regions (i.e., the SOI regions) into which devices are built and a thin buried layer of an insulator, such as oxide (SiO2), electrically isolating the active layer from the rest of the substrate. Traditional transistor devices, such as metal-oxide semiconductor field effect transistors (MOSFET's), feature source and drain regions formed within the active layer of the SOI substrate and a gate defining a channel region in the active layer disposed between the source and drain regions.
The thickness of the silicon active layer of the SOI substrate determines whether the depletion of the channel region will extend beneath the gate fully to an interface between the active silicon layer and the underlying insulator layer. Partially depleted SOI (PDSOI) transistor devices are formed in an active layer that is thick enough that the channel region under typical gate voltages will not be fully depleted across its full thickness when the device is in operation. The design and operation of partially depleted SOI transistor devices and bulk transistor devices are similar. In contrast, the channel region of fully-depleted SOI (FDSOI) transistor devices extends to the interface between the active silicon layer and the underlying buried oxide layer under typical gate voltages.
Although the operation of SOI transistor devices provide certain performance advantages over the operation of comparable bulk devices, SOI transistor devices suffer from floating body effects related to the device isolation from the fixed potential substrate underlying the buried insulator layer. In bulk transistor devices, the device may be electrically connected through the substrate such that the threshold voltage is stable relative to the drain-to-source voltage. In contrast, the un-depleted silicon beneath the gate (e.g., the body) in PDSOI transistor devices is electrically floating with respect to the substrate because of the intervening insulator layer, which lowers the effective threshold voltage and thereby increases the drain current. Consequently, floating body effects may contribute to undesirable performance shifts in the PDSOI transistor device relative to design and instability of the transistor operating characteristics.
FDSOI transistor devices experience reduced floating body problems in comparison to PDSOI transistor devices because the effective thickness of the body is reduced or eliminated. Consequently, semiconductor manufacturers are seeking techniques for effectively thinning the active layer of SOI substrates to an ultra-thin thickness (i.e., less than or equal to about 20 nanometers (nm) and preferably less than about 10 nm) that provides full depletion of the channel region under typical gate voltages. However, the thickness of these thin active layers must be uniform across the entire substrate because device behavior is sensitive to the thickness. Conventional processes for forming active silicon layers in this thickness range are unable to provide satisfactory thickness uniformity.
What is needed, therefore, is an SOI substrate with SOI regions, which are preferably defined in an ultra-thin active silicon layer for building FDSOI devices, and substrate manufacturing methods that overcome these and other disadvantages of conventional SOI substrates and conventional methods of manufacturing such SOI substrates.