1. Field of the Invention
The present invention relates to semiconductor device manufacturing technology, more specifically, to a method for forming a via-hole for interconnection between multilevel metallization and/or wiring layers.
2. Description of the Related Art
Improvement in the integration of a semiconductor chip produces or results in decreasing the size of circuit elements, and also increasing the length of signal lines for electrical connection between elements, because a plurality of complicated functional elements are integrated on a single chip. However, the length of a signal line should be shortened to improve an operational speed of the integrated circuit. Multilevel interconnection technology is necessary to reduce the length of signal lines, thus enabling complicated functional circuit devices having a lower connection resistance and/or signal propagation time.
Multilevel interconnection technology involves electrically interconnecting metallization and/or wiring including a plurality of layers, using multilevel interconnection materials such as Aluminum (Al), Tungsten (W), and dielectric layers (e.g., such as interlevel dielectric [ILD] or intermetal dielectric [IMD]). A conventional method for interconnecting multilevel metallization comprises the steps of forming a hole in an insulating layer over a metallization layer, and filling the hole with a conductive material. An overlying layer of metallization is then formed over (and generally in contact with) the conductive material. This hole, which when filled electrically connects the overlying and underlying metallization layers to each other, is generally called a via-hole. Via holes can be classified into a vertical type or a taper type, according to the shape of the hole. A vertical type of via-hole, having a sidewall perpendicular to a level (horizontal) surface, is widely employed in that a dry etching process is adaptable to the formation thereof and over-etching is preventable during the dry etching process. Especially, the vertical type of via-hole is advantageous for a higher integration and miniaturization of semiconductor device, because it needs a relatively small formation area.
A conventional via-hole forming and filling method is explained hereinafter with reference to FIGS. 1A to 1C. Firstly, as shown in FIG. 1A, lower metallization (wiring) layer 10 is formed on a semiconductor substrate (not shown), and a diffusion barrier layer 12 such as Ti and/or TiN is formed thereon. Next, an insulating layer 20 such as IMD is formed on an entire surface of the substrate (e.g., by blanket deposition), for the purpose of insulating the metallization and/or wiring. Then, a photoresist pattern 30 for a via-hole is formed on insulating layer 20.
Subsequently, as shown in FIG. 1B, insulating layer 20 is selectively etched by RIE (Reactive Ion Etching) using photo-resist pattern 30 as a mask, until a portion of lower metallization layer 10 is exposed, thus resulting in via-hole 40. In such manner as described above, via-hole 40 is formed to be a vertical type, as shown in FIG. 1C. Preferably, via-hole 40 has a small diameter (e.g., substantially equal to the critical dimension for that particular level of metallization) for improvement in the integration of the semiconductor device.
After formation of via-hole 40, it is filled with CVD-Al (Chemical Vapor Deposited Aluminum) or CVD-W (Chemical Vapor Deposited Tungsten) for electrical connection between lower metallization wiring layer 10 and an upper metallization wiring layer to be formed in the subsequent process. Here, a vertical type of via-hole generally has poor step coverage during the metal deposition process (i.e., the gap-fill properties of the via-hole and/or metal deposition method may be unacceptable for large-scale commercial production). It is advantageous to form a vertical type of via-hole having as small a diameter as possible for maximizing integration of semiconductor devices. However, as the diameter thereof becomes smaller, an aspect ratio of via-hole becomes larger. As a result, it becomes more difficult to completely fill a via-hole with CVD-W or CVD-Al.