The present invention relates to flash memory devices, and more specifically, to flash memory devices and method of fabricating the same, wherein interference among floating gates can be reduced and the coupling ratio can be enhanced.
The size of flash memory cells preferably needs to be made smaller and smaller. However, the technology innovations and improvements needed to enable such device shrinkage are becoming more and more difficult to achieve in part due to the limits associated with patterning technology and equipment.
As a result, much research has been done on a multi-bit cell technology, in which a plurality of data can be stored in one memory cell. This type of a memory cell is called a “multi-level cell (MLC)”.
A MLC generally has two or more threshold voltages, and also has two or more data storage states corresponding to them.
FIG. 1 is a view showing a data storage state of a multi-level cell.
As shown in FIG. 1, a MLC into which data of 2 bits can be programmed has four data storage states, i.e., “11”, “10”, “01” and “00”. Distribution of them corresponds to distribution of threshold voltages of the MLC, respectively. For example, assuming that distribution of threshold voltages of a memory cell is −2.7 V or less, 0.3 to 0.7 V, 1.3 to 1.7 V and 2.3 to 2.7 V, “11” corresponds to −2.7 V or less, “10” corresponds to 0.3 to 0.5 V, “01” corresponds to 1.3 to 1.7 V and “00” corresponds to 2.3 to 2.7 V. That is, if the threshold voltage of the MLC corresponds to one of the four threshold voltages, data information of 2 bits corresponding to one of “11”, “10”, “01” and “00” is stored in the memory cell.
Therefore, it is necessary to finely control distribution of threshold voltages in each level. For example, the range for one level has to be controlled to about 1 V. To this end, although sensing margin is related to a program pulse step, the range has to be controlled to about 0.2 V.
If the range for one level or sensing margin is too finely controlled, however, the performance of a product can be degraded. If a unique threshold voltage shift of a cell is controlled to about 0.2 V, a threshold voltage that must be controlled is less than 0.4 V.
In order to attain this threshold voltage, a threshold voltage that can be controlled most ideally cannot be controlled to be about less than 0.2 V when considering that it is related to a program pulse step.
In this case, in consideration of block pattern dependency, a shift in a threshold voltage due to the interference effect depending upon a state of a surrounding cell has to be controlled to about 0.05 V or less.
FIG. 2 is a graph showing a threshold voltage shift (dVt) value according to the interference effect depending upon shrinkage of the cell size.
As shown in FIG. 2, a threshold voltage value (dVt) that varies due to neighboring cells in a bit line direction is 0.05 V or less, which is not a significant problem. However, a threshold voltage value (dVt) that varies due to neighboring cells in a word line direction is 0.3 to 0.5 V. This makes it difficult to implement a MLC cell.