1. Field of the Invention
The present invention relates to a memory device.
2. Description of the Prior Art
In the conventional dynamic memory having an array of so-called one-transistor type memory cells, wherein each memory cell comprises a metal oxide semiconductor field effect transistor, either data of the logic state "0" or "1" is memorized byy the memory cell in accordance with whether an MOS capacity is charged or not charged with electrons, as for example, in an n-channel type MOS transistor. Because this charge amount is very small, it is read out as an information, in general, through amplification by a sense amplifier.
The prior sense amplifier is so designed as shown in FIG. 1 that a pair of bit lines .circle.3 and .circle.4 , .circle.5 and .circle.6 , .circle.7 and .circle.8 . . . from a memory array area M are connected with each sense amplifier SA. A 256K dynamic random access memory includes 512 to 1024 sense amplifiers SA. In each sense amplifier SA, the respective sides of a p-channel type MOS transistor .circle.29 are connected with each other by a line .circle.1 and the respective sides of a n-channel type MOS transistor .circle.28 are connected with each other by a line .circle.2 . These connections assure the function of the sense amplifiers with a smaller occupied area and a high efficiency. But, according to the construction shown in FIG. 1, it is inevitably performed that after data stored in the memory array M is once read out and amplified by the sense amplifier SA, an information of an objective sense amplifier SA is selectively altered by a buffer (inverter) .circle.15 , .circle.16 or .circle.17 with a higher current driving capacity than that of the sense amplifier. This procedure is complicated.
The reason of the procedure is as follows. As mentioned above, the charge amount to be read out from the memory array is very small and a potential difference generated according to the charge amount between each pair of bit lines is also very little, generally being not more than 200 mV. The potential difference tends to change very slowly from t1 to t3 as shown in FIG. 2. This is because the bit line itself has an electrical resistance and capacitance of a certain value to cause RC delay for the stored data. In FIG. 2, the dotted line shows a rise timing of a word line on the write or read operation wherein a time of t.sub.3 -t.sub.1 is required for the potential shift of the bit lines .circle.5 and .circle.6 to read out the data. On the other hand, the writing of the data is performed very rapidly provided that it starts simultaneously for each line. The wave form of FIG. 2 is based on an assumption that a set of lines .circle.21 is used for writing an information and a set of lines .circle.22 is used for reading an information. In more detail, an initial value is set on a stand-by mode or pre-charge mode before the time t1, whereby the terminals .circle.9 to .circle.11 and .circle.24 (See FIG. 1) are set at 0 V to turn only a transistor .circle.26 on so as to short-circuit lines .circle.1 and .circle.2 . In the case where a power supply voltage is 5 V, the potential of line .circle.1 or .circle.2 is around 2.5 V. And, all of the bit lines .circle.3 to .circle.8 are similarly short-circuited to be set at 2.5 V. In FIG. 2, the word line selected at the time t.sub.1 shows 5 V or more to output data of a memory element connected therewith on the bit line. As assumed above, the set .circle.21 is subjected to the writing operation and so the terminal .circle.9 is at 9 V to turn a transistor .circle.12 on. If an input data from line .circle.18 is 5 V, the potential of the bit line .circle.3 already reaches 0 V at t.sub.2. In this case, the bit line .circle.4 is set at 2.5 V to shift the transistor .circle.28 to an on state through which the potential of 0 V is transmitted to a node .circle.2 . In the contrary case, the potential of 5 V is transmitted to a node .circle.1 through the transistor .circle.29 . Whereas the potential of the terminal .circle.24 is still 0 V at that time to short-circuit nodes .circle.1 and .circle.2 through the transistor .circle.26 , nodes .circle. 1 and .circle.2 are chargeable to be set at 2.5 V and 0 V respectively in the area adjacent to the write lines .circle.21 because of significant capacitance and resistance of nodes .circle.1 and .circle.2 . Consequently, the sense amplifier SA in the vicinity of the nodes is liable to start a sensing operation. This is the well-known malfunction called presensing.
To avoid the presensing in the prior art, data of memory cells are first read out in both cases of the writing and reading operations. At the time the amplification of the data is over (t.sub.4 of FIG. 2), the portion requiring the writing of data is electrically connected with the buffer, that is, the potential of terminal .circle.9 is 5 V after t.sub.4. The buffer is functioned to forcibly alter the data of the sense amplifier so as to prevent the presensing.
At the time of the alteration of the data, electric current flows through the circuit. However, in the prior technique as generally applied to memories, data of one bit or four bits or the like is simultaneously altered to cause no relatively significant problem. But, in the case of a FIFO (First-In, First-Out) memory device mentioned later, it becomes necessary to simultaneously alter the data of 256 bits or more, which results in a large electric current being required. This large electric circuit is not advantageous, for example, in view of the power consumption caused thereby.