Phase-locked loop (PLL) circuits are widely used in numerous applications such as I/O interfaces, digital integrated circuits, memory systems, processors, frequency multiplication, or frequency tracking. A typical PLL circuit includes a phase frequency detector (PFD), a charge pump (charge pump), a loop filter (LF), a voltage controlled oscillator (VCO), and a frequency divider circuit. The PFD compares the phase of the reference signal and the feedback signal from the frequency divider circuit. Depending on the relationship of the phase of the reference signal and the feedback signal, the PFD provides one or more signals to the charge pump that instruct the charge pump to increase or decrease the voltage to the VCO through the LF. The LF may integrate the signal to smooth it, and the LF provides the smoothed signal to the VCO. The frequency of the VCO increases or decreases depending on the voltage signal from the LF. The output of the VCO is fed back to the PFD through the frequency divider in a loop that causes the output signal of the VCO to have a frequency that is proportional to (or equal to) and in phase with the reference signal.
In conventional PLL circuit design, the low pass filter generally consists of an integral capacitor and a series resistor in order to maintain loop stability. The resistor provides a zero (e.g., the zero of the low pass filter) that improves the PLL loop stability, but generates a ripple on the control voltage if the charge pump is unable to ideally match. To address this issue, a second small capacitor is typically used in parallel with the integral capacitor and series resistor to filter the ripple. However, the second capacitor may degrade the PLL's phase margin. Thus, in the conventional PLL circuit design, there is a trade-off between stability and jitter.
In addition to the challenge described above, another challenge for conventional PLL circuits is the rapid reduction in core voltage in the semiconductor process development. The rapid reduction in core voltage greatly increases the design difficulty of the charge pump. For example, the power supply for 28 nm semiconductors is around 1.0V and for Fin Field-effect transistor (FinFET) processes, the power supply is lower than 0.8V. Hence, it may be difficult to keep the charge pump current match in the control voltage range with such a low power supply voltage.
Another challenge encountered with conventional PLL design is that, in some applications, the reference frequency may change widely (e.g., from Mega Hz to Giga Hz), which means the PLL must be able to adjust its parameters adaptively to fit the bandwidth and meet stability standards as well.