The present invention relates to a method for operating a flash memory device, and more particularly, to a method for programming a multi-level cell (MLC) flash memory device.
Flash memory devices are non-volatile memory devices that are programmable and erasable, and are widely used for portable electronics (for example, MP3 players, digital cameras, camcorders, laptop computers, personal digital assistants (PDAs), mobile phones, etc.), computer basic input/output systems (BIOS), printers, USB drivers, etc.
NAND flash memory devices are becoming increasingly popular for use as data storage media. Thus, high capacity flash memory devices are in great demand. Recently, to increase storage capacity in a smaller chip size, research for a multi-bit cell storing more than 2 bits is being actively performed. The multi-bit cell is commonly called a multi-level cell (MLC). Unlike a single level cell (SLC) having a programmed state or an erased state (i.e., 2 bits) in each cell, the MLC can store three or more bits in each cell. Therefore, compared to the SLC, the MLC has at least twice the memory capacity of the SLC. The MLC typically includes more than two threshold voltage distributions, and more than two corresponding data storage states.
In an MLC flash memory device, threshold voltage distributions of a programmed state need to be spaced apart from each other between a first read voltage R1 and a pass voltage Vpass. Therefore, the width of the threshold voltage distributions is required to be as narrow as possible after programming.
A program operation of the flash memory device is accomplished by Fowler-Nordheim Tunneling. A predetermined program voltage is applied to a word line of selected memory cells, and a ground voltage is applied to a bit line thereof. To prevent unselected memory cells from being programmed, a power voltage Vcc is applied to a bit line of the unselected memory cells. Once the program voltage is applied to the word line and the ground voltage is applied to the bit line, a high electric field results between a floating gate and a channel of a memory cell. Thus, tunneling occurs, where electrons of a channel pass through a tunnel oxide between a floating gate and a channel due to the electric field. Thus, a threshold voltage of the memory cell rises because of accumulation of the electrons in the floating gate.
FIGS. 1A to 1D illustrate graphs of threshold voltage distributions when a conventional MLC flash memory device is programmed.
A program operation of the MLC flash memory device programs a least significant bit (LSB) first and then a most significant bit (MSB) through an incremental step pulse program (ISPP) method.
Referring to FIG. 1A, an LSB of a memory cell in a [11] state with a negative threshold voltage (i.e., an erased state) is programmed to a [10] state with a second program level.
FIG. 1B illustrates a change of a threshold voltage due to interference of adjacent cells after programming the memory cell of the [11] state to the [10] state. The right tail of the threshold voltage distribution shifts and the width between the right tail and the left tail increases.
As illustrated in FIG. 1C, to program to a [01] state (i.e., a first program level) and a [00] state (i.e., a third program level), an MSB of a memory cell in a [11] state is programmed to a [01] state of a first program level, and an MSB of a memory cell in a [10] state is programmed to a [00] state of a third program level.
FIG. 1D illustrates a change of threshold voltage distribution due to interference between adjacent cells after programming the MSB.
While programming an MLC flash memory device, the variation width of threshold voltage distribution is maximized because the greatest interference occurs from adjacent cells when programming a [11] state (i.e., an erased state) to a [01] state of a first program level. The reason is that it is difficult to accurately measure where a threshold voltage of an actual memory cell is placed in a negative region because a threshold voltage of a memory cell in a [11] state (i.e., an erased state) is negative. Accordingly, when programming a [11] state (an erased state) to a [01] state, a bias difference affecting adjacent cells is maximized. Thus, as illustrated in FIG. 1D, there is almost no margin between threshold voltage distribution and a read voltage R3 when a memory cell is programmed in a [10] state. Therefore, failure may easily occur during a read operation.
Accordingly, in order to provide a memory cell with a uniform narrow threshold voltage distribution after programming, interference of adjacent cells needs to be minimized by reducing a bias difference, which affects adjacent cells, to as small as possible while programming an erased state to a [01] state.