1. Field of the Invention
The present invention relates to a method of calculating the delay of a gate so as to verify the timing of a digital integrated circuit (IC), and more particularly, to a method of exactly calculating the delay of a gate by reflecting a crosstalk effect due to capacitive coupling between adjacent metal conductive lines.
2. Description of the Related Art
The more highly integrated a semiconductor process becomes, the more the height of a metal conductive line included in an integrated circuit (IC), as compared to the width thereof. Capacitive coupling between adjacent conductive lines occupies a portion of 50˜70% of the whole capacitance in a conductive line of an IC manufactured during a process to several tens of nano meters due to the above-described physical characteristic. Such a capacitive coupling increases signal crosstalk between adjacent conductive lines.
A signal transition in a net of an IC causes crosstalk noise from adjacent conductive lines through the capacitive coupling. If the crosstalk noise is induced into an adjacent net during the signal transition, distortion of a signal waveform changes the delay of a gate in the adjacent net. Thus, such a change in the delay of a gate due to the crosstalk noise must be considered when a semiconductor is designed.
FIG. 1 is a circuit diagram of gates 100 for driving an interconnect load 102 coupled by a capacitor Cc in a digital IC. Referring to FIG. 1, the gates 100 drive the interconnect load 102 including a capacitive coupling 103.
When the timing of the digital IC is verified, output waveforms of the gates 100 with regard to input voltage waveforms 104 are obtained in a circuit of a single stage, each delay of the gates 100 is calculated, input waveforms of fan-out gates 101 are obtained, and the interconnect delay is calculated. In this regard, each delay of the gates 100 is each delay of the signals between input ends and output ends of the gates 100. The interconnect delay is the delay of a signal between an output end of one of the gates 100 and an input end of the gates 101.
In general, each delay of the gates 100 is calculated on the basis of time that a signal passes over a 50% level of a power voltage. The interconnect delay may be calculated by using a linear system with regard to the output waveforms of the gates 100.
The interconnect load 102 driven by the gates 100 may be expressed in a linear equation. Thus, the admittance relationship with regard to the interconnected load 102 from the output sides of the gates 100 may be approximated in a frequency domain according to equation 1 below by using a conventional model order reduction technique disclosed in cited reference 1 (Altan Odabasioglu, Mustafa Celik, and Lawrence Pileggi, “PRIMA: passive reduced-order interconnect macromodeling algorithm,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, no. 8, pp. 645-654, August 1998),
                                          [                                                                                                      I                      1                                        ⁡                                          (                      s                      )                                                                                                                                                              I                      2                                        ⁡                                          (                      s                      )                                                                                            ]                    =                                    [                                                                                                                                            Y                          ^                                                11                                            ⁡                                              (                        s                        )                                                                                                                                                                          Y                          ^                                                12                                            ⁡                                              (                        s                        )                                                                                                                                                                                                          Y                          ^                                                21                                            ⁡                                              (                        s                        )                                                                                                                                                                          Y                          ^                                                22                                            ⁡                                              (                        s                        )                                                                                                        ]                        ⁡                          [                                                                                                                  V                        1                                            ⁡                                              (                        s                        )                                                                                                                                                                                V                        2                                            ⁡                                              (                        s                        )                                                                                                        ]                                      ⁢                                  ⁢                                            Y              ^                        ij                    ⁡                      (            s            )                          =                              ∑                          n              =              1                                      q              ij                                ⁢                                                                      k                  ^                                ijn                                            s                -                                                      p                    ^                                    ijn                                                      ⁢                                                  ⁢                          (                                                q                  ij                                ⁢                                  <<                  n                                            )                                                          1        )            
Wherein, n denotes the number of poles of a given original linear system, and each admittance term may be approximated as a very small number of poles as compared to the given linear system. The admittance relationship approximated in equation 1 is configured as an equivalent circuit as shown in FIG. 2 and is substituted as the interconnect load 102.
FIG. 2 is a circuit diagram of an equivalent reduced order model of the interconnect load 102 of FIG. 1. Referring to FIG. 2, in cited reference 2 (Paul D. Gross, Ravishankar Arunachalam, Karthik Rajagopal, and Lawrence T. Pileggi, “Determination of worst-case aggressor alignment for delay calculation,” in Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1998, pp. 212-219), output waveforms of gates 200 and 201 alternate with each other and are iteratively calculated until the output waveforms converge. In more detail, the output waveform of the gate 200, in a state that an output waveform of the previously calculated gate 201 is established, and the output waveform of the gate 201, in a state that an output waveform of the previously calculated gate 200 is established, alternate with each other, and the output waveforms of the gates 200 and 201 are calculated. Such a calculation may be repeatedly performed until the output waveforms converge so that the output waveforms of the gates 200 and 201 can be calculated. The method of calculating the output waveforms of the gates 200 and 201 by repeatedly alternating the output waveforms until the output waveform converge may be equally applied to three or more gates.
The gates 200 and 201 have loads 202 and 203 having the same configuration, respectively. Thus, a method of efficiently calculating output waveforms of a gate and a load circuit enables to calculate an output waveform of each gate.
FIG. 3 is a circuit diagram for explaining calculation of an output waveform of one of the gates 200 and 201 when an output waveform of the other one of the gates 200 and 201 is previously calculated. Referring to FIG. 3, various methods of effectively calculating an output waveform in a circuit having a capacitive load 301 and a noise current source 302 having a current waveform of a gate 300 with regard to an input voltage 303, as a load, have been proposed.
In the circuit of FIG. 3, conventional methods of generating a linear gate model include a transient holding resistance calculation method disclosed in cited reference 3 (David Blaauw, Supamas Sirichotiyakul, and Chanhee Oh, “Driver modeling and alignment for worst-case delay noise,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 2, pp. 157-166, April 2003) and a conventional modified effective capacitance calculation method disclosed in cited reference 2.
The above two methods use a linear gate model 400 including a linear resistor 404 and a voltage source 405 having a saturated ramp waveform, as shown in FIG. 4. The conventional linear gate model 400 includes a capacitive load 401 and a noise current source 402 that are the same as shown in FIG. 3, as loads driven by the gate. Although the linear gate model 400 may be used to obtain an output waveform of the gate, since the linear resistor 404 is a time-invarying resistor, a dynamic change in an output resistance of the gate cannot be exactly reflected.
The conventional modified effective capacitance calculation method uses a cell library with regard to an inclination of an input voltage waveform, 50% delay measured with regard to a single load capacitance, and an inclination of an output waveform. The conventional modified effective capacitance calculation method obtains a value for matching a gate output waveform and a waveform that is discharged by the linear resistor 404 and the load capacitance. In the conventional modified effective capacitance calculation method, the linear gate model 400 does not reflect the dynamic change in the output resistance during the transition of a gate output waveform. Therefore, a noise voltage waveform of a gate output obtained by using the linear gate model 400 may be inexactly calculated and the output waveform of the gate may be also inexactly calculated.
Also, the transient holding resistance calculation method obtains an output waveform through a simulation in the circuit shown in FIG. 3 in order to obtain the output linear resistor 404 of the conventional modified effective capacitance calculation method as a value that exactly reflects non-linearity characteristics of the gate, obtains the output waveform through a simulation with regard to the circuit of FIG. 3 from which the noise current source 302 is removed, and obtains a noise voltage waveform of the gate as a difference between the obtained two output waveforms. Although the transient holding resistance calculation method can obtain an output resistance that more exactly reflects the output characteristics than the conventional modified effective capacitance calculation method, its complicated processing makes it impossible to be applied to timing verification.