Field programmable analogue arrays (FPAAs) are a relatively recent development in the electronics industry which enable a user to quickly and flexibly design and implement an extremely wide range of analog circuits. FIG. 1 shows an example of a FPAA comprising an array of individual, configurable analog blocks (CABs) 10 on a silicon chip 12. The CABs 10 may be based on switched capacitor circuit technology, using capacitors which are integrated on silicon. A CAB might comprise a switched capacitor CMOS op amp, a comparator, an array of capacitors, CMOS switches and SRAM. The configurable analog blocks 10 are interconnected with configurable connections 14.
Configurable Op amps 18, configurable band gap voltage references and other configurable analogue elements are also dispersed across the chip. Configurable I/O blocks 20 and other configurable elements are disposed on the periphery of the chip. Configuration of all the configurable elements on the chip is carried out using configuration logic 16. The configuration logic provides an interface to a configuration data source and implements a mechanism by which configuration data is loaded into configurable elements on the chip, thereby defining the functionality of the FPAA.
Thus, by inputting user controllable configuration data to the FPAA, the FPAA can be programmed to replicate the functions of a large number of analog components or circuits, for example rectifiers, sample and hold circuits, filters, and level detectors. However, it is not possible to replicate the function of all circuits using a single FPAA, due to the finite number of resources available on a single FPAA. In principle, it is possible to solve this problem by utilising a plurality of FPAAs interconnected in a “daisy chain”. In practise, the problems associated with conveniently loading data into such a daisy chain arrangement of FPAAs have been little explored. In one known arrangement (Zetex FAS TRAC) a plurality of FPAAs are ‘daisy chained’, each FPAA having a clock input pin, a data input pin and a data output pin. The data output of the first device is connected to the data input of the second device, the data output of the second device is connected to the data input of the third device etc. and the clock pins are all connected together. To program the last device in the chain data must be clocked through every register stage in each of the previous devices. Thus data inputted into the n'th device in the chain will have been routed through each register in (n-1) devices. A considerable disadvantage with this approach is that the flow of data is slow.
In another known arrangement (Lattice ISPPac), a plurality of field programmable analogue devices are ‘daisy chained’ in a system in which each device is configured via a standard four pin JTAG interface. Following standard JTAG protocol, data to a particular device in a system must be clocked through a single register in each preceding device in a chain of JTAG devices. This introduces a pipelining latency. In a large system of devices this latency will affect the time taken to program a device.
Once a plurality of FPAA devices has been configured, it would be highly advantageous to be able to target specific devices, or groups of devices, for reprogramming or partial reprogramming, without the need to affect any of the other devices in the system, and without having to incur timing penalties such as those indicated above.
Such considerations apply not only to the proposed system of interconnected FPAAs, but also to multiple arrangements of other programmable devices, such as programmable logic devices, for example field programmable gated arrays (FPGAs). Methods have been developed to enable reprogramming (henceforth termed “reconfiguration”) of such devices in a multiple device system, and are discussed below.
In a first method an array of devices are serially programmed and configured. A global REPROGRAM pin can then be asserted to initiate reprogramming of all the devices. This system is very inefficient because even if only one device in a chain requires configuring, all devices have to be reconfigured, since data passes serially through each device to the next.
A second method for configuration, used by ATMEL for configuring arrangements of FPGAs, and illustrated in the AT6000 series datasheet, allows reconfiguration of all devices in the system, partial configuration of individual devices and also allows partial reconfiguration of individual devices in the system. The method used involves the use of a state machine controlled data loading mechanism in each device, coupled with token-based chip select methodology. The first device is selected, data are loaded, and if no further data are to be loaded the state machine exits and passes control on to the next device by asserting the chip enable of the next device. The state machine of the next device processes the input data accordingly. The disadvantage with this method is that although the data are applied in parallel, control is passed serially, and there is therefore a pipelining latency if trying to reprogram individual devices in a chain.
Another method of configuration employed by ATMEL uses a state machine controlled data loading mechanism in each device, as above, but uses an address decoder to select devices individually, rather than relying on a chip select being passed from device to device. The disadvantage of this method is that a separate chip select line is required for each FPAA in a system, which increases routing problems on a printed circuit board, and, in addition, address decode circuitry is required.
A method that involves aspects of the two methods discussed above is known, in which configuration data passes through each device in series. Partial reconfiguration is supported by the state machine controlled data loading mechanism method as discussed in respect of the second prior art method. However, the method is limited by the problem of pipelining latency.
U.S. Pat. No. 5,457,408 and U.S. Pat. No. 5,329,179 describe methods for configuring a FPGA device in which the FPGA is hardwired with an identification code which enables the FPGA to selectively accept data intended for the FPGA.
In summary, although methods have been developed to allow reprogramming of all devices in a system or reprogramming of single devices in a system, a system does not yet appear to have been developed to allow limitless fast and flexible programming, reprogramming and partial reprogramming options for any, some or all devices in a system. Furthermore, prior art techniques are slow and suffer from pipelining latency or a requirement for multiple chip select lines.
Furthermore, it would be hugely desirable to improve the speed of reconfiguration since, as previously noted, the prior art techniques discussed above are inefficient.
The present invention addresses these problems and disadvantages.