1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) panel, and particularly, to one capable of displaying three-dimensional graphics without employing an external Z buffer.
2. Description of the Prior Art
When displaying three-dimensional images, or overlapping two objects on a display, a computer may hide one whose depth is deeper than the other behind the other. This is called a "hidden surface removal" process. This process is usually achieved with the use of an external Z buffer. FIG. 1 shows a conventional display system consisting of a display unit 53 such as a cathode ray tube (CRT) or an LCD panel provided with a Z buffer 49. The Z buffer 49 is external to the display unit 53 and stores depths expressed with the pixels of the display unit 53. If a second depth to be assigned to a given pixel is shallower than a first depth presently assigned to the pixel, the second depth is written into a video RAM (VRAM) 51 so that the second depth is displayed. If the second depth is deeper than the first depth, the first depth is kept unchanged in the VRAM 51. The hidden surface removal is carried out by a central processing unit (CPU) or a graphic processor (GP) 47 that is external to the display unit 53.
The CPU 47 reads a depth for a given pixel out of the Z buffer 49, compares the read depth with a new depth internally calculated for the pixel, and writes a deeper one of the depths with related intensity and RGB data into the VRAM 51 and Z buffer 49.
Employing the external Z buffer 49 is the easiest way to carry out the hidden surface removal but is expensive. To display a color image with red (R), green (G), and blue (B) colors each represented with 8 bits for each pixel, i.e., 24 bits in total per pixel, the VRAM 51, which is usually a DRAM, must have a capacity of about 4 MB for a screen size of 1280.times.1024 pixels. If the number of bits used for each color is reduced, the capacity of the DRAM may be 1 to 2 MB. The size of the Z buffer 49 is dependent on depth resolution. A depth resolution of 16 to 24 bits requires the capacity of the Z buffer 49 to be equal to or greater than that of the VRAM 51, thereby increasing the cost of the display system.
If the CPU 47 uses data pins of the Z buffer 49 commonly for read, compare, and write operations, the operations must be sequential to delay a processing speed. Then, it is difficult to display images in real time.
To solve this problem, a dual-port DRAM may be employed as the Z buffer. The CPU 47 reads a depth through the serial port, compares it with an internally calculated depth, and writes data into the DRAM under a high-speed mode such as a page mode or a nibble mode according to a pipeline method. This technique may improve the processing speed but double the number of data pins, complicate control, and increase the cost of the display system.