1. Field of the Invention
The invention is related to a computer implemented method, and more particularly, to a computer implemented method for performing extraction in a layout versus schematic (LVS) process.
2. Description of the Prior Art
A computer programmed with layout verification software is normally used to verify that a design of an integrated circuit (IC) chip conforms to certain predetermined tolerances that are required by a process to be used in fabricating the chip, to ensure that a layout connectivity of the physical design of the IC matches the logical design of the IC represented by a schematic, and to extract parasitic resistance and capacitance of the IC. These are all very important steps for guaranteeing the properties of the chip manufactured by the process before the tape out of the circuit.
Methods for checking the consistency between the physical design and the logical design of the IC is called layout versus schematic (LVS) process. There are numerous metal lines, poly-silicon shapes, and diffusions in close proximity to one another on each semiconductor chip, all of miniscule dimension, which must be fabricated to exacting tolerances. As technologies advance, smaller and smaller dimensions are used in lithography. All of these semiconductor layers must be designed and fabricated to exacting tolerances. To meet the tight tolerances requirement in modern manufacturing processes, a LVS process which is more accurate is still needed.