A semiconductor element, for example, a large scale integrated circuit (LSI) or a metal oxide semiconductor (MOS) transistor, is manufactured by performing processes, such as an etching, a chemical vapor deposition (CVD) and a sputtering on a semiconductor substrate which becomes as a to-be-processed substrate. For the processes, such as the etching or the sputtering, there are processing methods using plasma as an energy supply source, i.e., a plasma etching, a plasma CVD, a plasma sputtering, and the like.
Here, a technique regarding an etching method in which etching is performed by forming an antireflective film at the time of etching is disclosed in Japanese Patent Laid-Open Publication No. 2009-188403 (Patent Document 1). Patent Document 1 discloses a method in which a characteristic portion within a silicon containing anti reflective coat (ARC) layer while reducing a critical dimension (CD).