1. Field of the Invention
This invention relates generally to voltage controlled oscillator (VCO) circuits and, more particularly, to a VCO having a selectable range of operating frequencies and a frequency sweep within the selected range of operating frequencies.
2. Description of the Related Art
A critical part of the phase-locked loop circuits used in frequency generation and data recovery is the VCO. Most VCO analysis has considered only xe2x80x9cnearly sinusoidalxe2x80x9d oscillations in conventional topologies (such as LC-based circuits), conditions difficult to create in monolithic circuits. For a VCO that is to be used in a PLL, the following parameters are important. 1) Tuning range: i.e., the range between the minimum and maximum values of the VCO frequency. In this range, the variation of the output amplitude and jitter must be minimal. The tuning range must accommodate the PLL input frequency range as well as process- and temperature-induced variations in the VCO frequency range. The tuning range is typically at least xc2x120% wFR. 2) Jitter and phase noise: timing accuracy and spectral purity requirements in PLL applications impose an upper bound on the VCO jitter and phase noise. 3) Supply and substrate noise rejection: if integrated along with digital circuits, VCOs must be highly immune to supply and substrate noise. Such effects become more prominent if a PLL shares the same substrate and package with a large digital processor. 4) Input/output characteristic linearity: variation of KVCO across the tuning range is generally undesirable. If a PLL is used as an FM demodulator, the variation of KVCO introduces harmonic distortion in the detected signal and must be below 1%. In other applications, this non-linearity degrades the loop stability but it can be as high as several tenths of a percent.
In order to achieve high rejection of supply and substrate noise, both the signal path and the control path of a VCO must be fully differential. An oscillator in which signals exist in complementary form, having rail-to-rail swings, is not considered differential because it exhibits poor supply rejection. Differential operation also yields a 50% duty cycle, an important requirement in timing applications, and is immune to the up-conversion of low-frequency noise components in the signal path.
A common oscillator topology in monolithic PLLs is the ring oscillator. Here, a cascade of M gain stages with a total (dc) phase shift of 180xc2x0 is placed in a feedback loop. It can be easily shown that the loop oscillates with a period equal to 2MTd, where Td is the delay of each stage with a fanout of one. The oscillation can also be viewed as occurring at the frequency for which the total phase shift is zero and the loop gain is unity. Since, the gate delay is monitored and controlled within the process corners, the oscillator frequency and its variation can be predicted with reasonable accuracy.
In order to vary the frequency of oscillation, one of the parameters in 2MTd must change, i.e., the effective number of stages or the delay of each stage. In one approach, called xe2x80x9cdelay interpolationxe2x80x9d, a fast path and a slow path are used in parallel. The total delay is adjusted by increasing the gain of one path and decreasing that of the other, and hence is a weighted sum of the delays of the two paths. In a second approach, the delay of each stage in the ring is directly varied with negligible change in the gain or voltage swings. In some prior art circuits, the delay of each stage is tuned by the control input. This can be accomplished by varying the capacitance or the resistance seen at the output node of each stage.
An important issue in ring oscillator design is the minimum number of stages that can be used while attaining reliable operation. Since oscillation occurs at a frequency for which the total phase shift is zero and the loop gain is unity, as the number of stages decreases, the required phase shift and (dc) gain per stage increase. For example, for a three-stage oscillator, each stage must introduce a phase shift of 120xc2x0 and a minimum dc gain of 2. While two-stage bipolar oscillators can be designed to achieve both sufficient phase shift and high speed, it is known that CMOS implementations with only two stages either do not operate reliably or, if they employ additional phase shift elements, oscillate no faster than three-stage configurations. Thus, CMOS VCOs typically utilize three or more stages.
A low VCO gain is a desirable feature as it reduces the circuit noise effects at the VCO output. Therefore, less jittery, more stable VCO output is possible even with lots of power supply noise. However, many VCOs are powered with supply voltages of 1.8 Volts or even lower. Even though the low power supply voltage does not limit the oscillation frequency of a VCO, it puts a limit on the control voltage range in which VCO frequency is swept linearly. As xcex94V gets smaller with low supply voltage values, the VCO gain becomes larger. To make the matters even worse, the process and temperature variations in CMOS circuits mandate that Fmax and Fmin must be farther apart from each other to ensure the coverage of the actual operating frequency of interest under any condition, and thus causing even higher VCO gain.
It would be advantageous if a VCO could generate a low noise output signal, even when powered from a low voltage power supply.
It would be advantageous if the above-mentioned VCO had a selectable frequency range that could be used in acquisition or tracking modes.
It would be advantageous if the above-mentioned VCO had a selectable frequency range to mitigate the gain requirements.
Accordingly, a VCO with variable frequency range is provided. The frequency range in which a VCO is designed to operate is very much process dependent. In some cases, due to process variations, a VCO can be fabricated to supply a range of frequencies, in response to an input voltage range, that does not coincide with the actual operating frequency. The present invention selectable frequency VCO reduces the occurrence of such an event, resulting in high yields in manufacturing such chips.
More particularly, the VCO comprises a frequency range circuit to select a VCO signal frequency range and a frequency sweep circuit to modify the selected range of VCO signal frequencies. The frequency sweep circuit includes a first delay section to delay an input signal a first delay and a second delay section to delay an input signal a second delay, less than the first delay. The variable delay circuit supplies a VCO signal that is a variable sum of the signals with the first and second delays.
The frequency range circuit includes a third delay section to delay an input signal a third delay and a fourth delay section to delay an input signal a fourth delay, less than the third delay. The frequency range circuit has an output connected to the input of the frequency sweep circuit, that is a selected sum of the signals with the third and fourth delays.
The frequency sweep circuit accepts converted control signals in a first range of currents and a second range of currents, less than the first range. The VCO supplies a VCO signal frequency and a range of potential VCO frequencies in response to the converted control signal current.
A converter circuit accepts a control voltage and supplies a converted control signal. A sweep window control input is used to select a converted control signal with the first range of current values or a converted control signal with the second range of current values.
Additional details of the VCO converter circuit, frequency range select, and frequency sweep circuits are provided in the detailed description of the invention below. Also provided is a method for generating a signal with a frequency sweep VCO.