In an IT (Information Technology) device such as an optical transmission device, a server system, a high performance personal computer or the like, function enhancement and/or performance enhancement (capacity enhancement, speed enhancement) have been promoted with a rapid spread of a recent Internet/intranet technology or the like. Accordingly, in a hardware forming the corresponding device or system, particularly a circuit unit (device) such as an FPGA (Field Programmable Gate Array), L2/L3 (Layer 2/Layer 3) switch, a CPU, a DSP or the like, voltage degradation and/or current enhancement have been rapidly promoted. Also, for a type of communications data, communication with data such as 1 GbE, 10 GbE or the like that are a large amount of packet data are becoming a mainstream.
Based on this, a power supply or source (PS) portion or unit driving such a hardware is also required to achieve a performance enhancement such as a high efficiency, high precision and high speed response.
FIG. 12 depicts one example of an optical transmission device, in which an optical transmission device 100_1 has a transmitting function where optical signals from external devices 200_1-200_n are converted into electric signals to be subjected to SONET signal processing or packet signal processing at optical interface boards 101_1-101_n and forwarded to a switch board 102 for switching, and the electric signals out of the switch board 102 are subjected to SONET/packet signal processing, converted into optical signals at an optical interface board 101_m and transmitted to an opposing optical transmission device 100_2; and the optical transmission device 100_1 has a receiving function in the reverse direction to the above transmitting direction. Also from a monitoring/controlling board 104, various settings and changes are performed to the optical interface boards 101_1-101_n, 100_m (hereinafter, occasionally represented by a reference numeral 101) and the switch board 102 for the SONET/packet signals etc.
A specific example of the optical interface board 101 depicted in FIG. 12 is further depicted in FIGS. 13A and 13B as an Ethernet unit. This Ethernet unit 101 is composed of an SFP (Small Form factor Pluggable) processing module 21 for converting a GbE optical signal OS into an electric signal, a PHY (Physical) processing module 22 for performing physical layer processing at a latter stage and an FPGA23, where the FPGA23 performs signal processing of the GbE optical signal.
When a normal signal is received, the signal is to be processed in the order of the SFP processing module 21->the PHY processing module 22->a PCS (Physical Coding Sublayer) processing portion 232->a selector 235->a MAC (Media Access Control) processing portion 236 as depicted in FIG. 13A and outputted from a packet buffer 237, whereas in the absence of signal received, no signal processing portion after the MAC processing portion 236 and the followings will operate as depicted in FIG. 13B. Namely, in the absence of signal received, an idle pattern from an idle pattern generator 231 is selected by the selector 235, thereby making the MAC processing portion 236 and the followings perform the circuit processing of the idle pattern.
This enables the idle pattern to be signal processed even in the absence of signals received, thereby holding a state where a current is always consumed to prevent the output voltage of a power supply (not depicted) within the optical interface board 101 from being dropped due to an increase of the consumption power by a rapid signal reception.
It is to be noted that there is a switching power supply in which by providing a ringing choke converter (RCC) type switching power supply circuit with an oscillation frequency suppressing circuit and an operation switchover circuit for starting or stopping the operation of the oscillation frequency suppressing circuit, the operation of the oscillation frequency suppressing circuit 10 is turned on by application of a signal voltage of the operation switchover circuit under light load while the operation of the oscillation frequency suppressing circuit 10 is turned off under a heavy load, thereby performing a normal RCC oscillation (See e.g. Japanese Laid-open Patent Publication No. 9-47023).
In the related art optical interface board (Ethernet unit) depicted in FIGS. 13A and 13B, for preventing the power supply voltage from being dropped due to an increase of the consumption power by a rapid signal reception of a packet etc., an idle pattern signal is provided to the circuit even in the absence of signal received, so that current is always consumed, disadvantageously consuming a useless power.