Integrated semiconductor memory circuits, particularly those employing cells which include essentially a storage capacitor and a switch, have achieved high memory cell densities. One of the simplest circuits for providing small memory cells is described in commonly assigned U.S. Pat. No. 3,387,286, filed July 14, 1967, by R. H. Dennard. Each of these cells employs a storage capacitor and a field effect transistor acting as a switch to selectively connect the capacitor to a bit/sense line.
Commonly assigned U.S. Pat. No. 3,979,734, filed by W. D. Pricer and J. E. Selleck on June 16, 1975, describes a memory array made of small cells which employ storage capacitors and bipolar transistors. In this latter array, which is word organized, each storage capacitor of these cells has simply one capacitor terminal connected to a separate bit/sense line while selected cells forming a word are simultaneously accessed by utilizing a word pulse for coupling to the other terminal of the storage capacitors of that word.
In commonly assigned U.S. Pat. No. 4,080,590, filed by W. D. Pricer on Mar. 31, 1976, there is described a semiconductor memory produced in a unipolar technology which includes a cell having an inversion storage capacitor with one terminal connected to a bit/sense line, the other terminal being coupled to a source of charges by a pulse from a word line. To provide a word organized array of these cells, each word includes a source of charges disposed at the surface of a semiconductor substrate and a plurality of inversion capacitors disposed also at the surface of the semiconductor in spaced apart relationship from the charge source. Information is written into the capacitors by applying voltages of two different magnitudes, representing 1 and 0 bits of information, to one terminal of each of the capacitors while a word pulse produces inversion layers at the surface of the substrate between the capacitors to interconnect serially the charge source with each of the capacitors. The capacitors having the larger voltage store the greater amount of charge. This charge can then be detected by measuring the voltage across the storage capacitors when a word pulse again connects the charge source with each of the capacitors.
In yet another commonly assigned U.S. Pat. No. 4,040,017, filed by H. S. Lee on Mar. 31, 1976, there is disclosed a memory which is an improvement over the memory described in U.S. Pat. No. 4,080,590. In the improved memory, the source of charges is selectively pulsed to inject charge into the storage capacitors. The pulses of charge are timed so that they begin at least by the onset of the word pulse and terminate prior to the termination of the word pulse. Furthermore, prior to the termination of the word pulse, the voltage at the charge source is set to form a charge sink for draining excess charges. This charge flow technique may be referred to as a fill-spill operation.
In still another commonly assigned U.S. Pat. No. 4,040,016, filed by H. S. Lee and G. Vogl, Jr. on Mar. 31, 1976, there is disclosed a memory of the type described in above-identified H. S. Lee patent but wherein each cell of the memory has a pair of inversion capacitors with one plate of each capacitor connected to one of a pair of bit/sense lines, the other plate of each capacitor being coupled to the source of charges when the word line is pulsed.
U.S. Pat. No. 4,086,662, filed by K. Itok on Aug. 11, 1976, describes a memory of the type disclosed in the above-identified Dennard patent but wherein a common sense amplifier is provided for a plurality of sense lines and a cell is located at each intersection of a word line and a sense line, with a control line connected to plates of the storage capacitors of the cells and a word line being used to read or write information from or to a given cell.
In commonly assigned U.S patent application Ser. No. 419,095, filed by E. P. Thoma on Sept. 16, 1982, there is disclosed a memory cell having a storage capacitor wherein a data sense-restore scheme is used in which a data sense line senses the state of charge in a selected cell and a data responsive circuit is used to rewrite low voltage signals through a separately accessed write device or transistor.
The IBM Technical Disclosure Bulletin article "One-device Memory Cell Arrangement with Improved Sense Signals," Vol. 23, No. 6, Nov. 1980, pp. 2331-2332, by L. Arzubi and W. D. Loeklein, teaches a memory array having cells each of which includes a storage capacitor and a transistor wherein the voltage applied to the plate side of the storage capacitor is dependent upon the state of the data sensed.