This invention generally relates to heat treating wafers for use in microelectronics, optics and optoelectronics applications. In particular, the invention relates to a high temperature heat treatment process (or annealing) for a semiconductor wafer placed on a support, wherein the process includes a slow rise in temperature up to a treatment ending temperature.
The term “high temperature” annealing means annealing in which at least some phases take place at temperatures exceeding a value on the order of 800° C. Thus, high temperature annealing processes means those that typically take place at temperatures on the order of 800 to 1200° C. These temperatures may be treatment ending temperatures.
In the case of multi-layer wafers, the different layers in the wafer may be assembled together by bonding. The term “bonding” means bringing two surfaces into intimate contact, to create a hydrogen bond or Van der Waals type bond between the two surfaces. This type of bonding may also be denoted as “molecular bonding”.
For example, a SMART-CUT® type process could be used to bond layers. This type of process includes a layer transfer, with detachment occurring at a weakened zone that was created by implantation of atomic particles in a donor substrate. The layer to be detached is bonded onto a support before detachment occurs. A general description of the steps of this process can be found in the book entitled “Silicon-On-Insulator technology: Materials to VLSI, 2nd edition”, by Jean-Pierre Colinge (Kluwer Academic Publishers) at pages 50–51. Thus, it is advantageous to use the SMART-CUT® type process for manufacturing Silicon-On-Insulator (SOI) wafers. Note that other types of processes also include bonding between two wafers.
In general, bringing two wafers into intimate contact is not sufficient for making a strong and permanent bond. Conventionally, a multi-layer wafer is exposed to an additional heat treatment to stabilize the bonding interface between the two wafers. This heat treatment typically increases the temperature of a multi-layer wafer, such as an SOI, to a final temperature on the order of 1100° C. Thus, this is an example of a “high temperature” annealing process.
In particular, when manufacturing an SOI, the heat treatment usually occurs in two phases:                A preliminary phase corresponding to a wafer surface oxidation step. This phase creates an oxide layer that will subsequently be eliminated, and the temperature during this first phase is on the order of 950° C.        A stabilization phase for the bonding interface. During this phase, the temperature is increased to reach a temperature of the order of 1100° C.        
During the stabilization phase, the temperature rise occurs along a straight gradient and corresponds to a linear temperature increase. The slope is typically about 5° C. per minute. Such a rise in temperature corresponds to a slow temperature rise. A “slow” temperature rise means an average temperature increase following a general average rate of change of less than 20° C. per minute. A problem related to the second phase (and more generally to stabilization annealing of a multi-layer wafer or even a single wafer) is that the slow temperature rise generates “slip line” type defects. The slip lines may appear anywhere on the surface of the wafer, particularly at the periphery of the wafer and elements supporting the wafer in the annealing oven or furnace. This is illustrated in prior art FIGS. 1–3.
FIGS. 1A and 1B are two different images of slip lines 10 taken by using a scanning electron microscope (SEM) on an SOI. In particular, these defects can be observed from the edge of the SOI.
FIG. 2 illustrates another view of slip lines of an SOI that occurred following a stabilization annealing process. This image was generated by a KLA Tencor SPI® type instrument. In this figure, the slip lines are circled and are distributed such that they remain close to the periphery of the wafer.
FIG. 3 shows another view of an image similar to that of FIG. 2, made on an exposed silicon wafer that was subjected to a high stabilization temperature annealing process of the same type as that applied to the SOI. FIG. 3 also illustrates slip lines (again circled) at the periphery of the wafer. This type of slip line is obviously a disadvantage, and may occur particularly after performing a stabilization anneal of a bonding interface.
In general, slip lines can occur after any high temperature annealing that includes a slow temperature rise up to an end of treatment temperature, applied to a wafer made from one or several semiconductor materials.