In order to improve circuit operation speed, insulate cell-to-cell, and prevent latch-up in a DRAM (dynamic random access memory) device, back bias voltage is generally applied to a bulk region of an NMOS transistor. Since the back bias voltage is then applied to a cell, a core, and a peripheral region of the DRAM device, current may be applied to a back bias voltage generator during forward current operation. Further, the applied current may damage the back bias voltage generator.
Thus, a triple-well structure adding a prior double-well structure to a second conductive first well isolation region 14 is suggested. Although a first back bias is applied to a peripheral region and a second back bias is applied to a cell or a core region in the triple-well structure, applying current to a back bias voltage generator is suppressed by the second conductive first well isolation region 14 formed under a first conductive first well 16 (for example, a P-type first well 16). As a result, the back bias voltage generator is not damaged. The first well isolation region 14 should secure overlap margin with respect to the P-type first well 16 over the first well isolation region 14. This aims at reliable suppression of applying current generated in an edge portion to the back bias voltage generator.
FIG. 1A to FIG. 1D sequentially illustrate a method for forming a prior triple-well.
Next, referring to FIG. 1A, a first photoresist film is formed on a first conductive (that is, P-type conductive) substrate 10 and then the first photoresist film is etched through a conventional photo-etching process defining the first well isolation region 14, so that a first photoresist pattern 12a is formed. The first well isolation region 14 is defined, in view of overlap margin with respect to the first well 16 (referring to FIG. 1B) formed over the first well isolation region 14 in a following process. In case the first photoresist pattern 12a is used as a mask and the tilt angle of the semiconductor substrate 10 is below 10 degrees, N-type impurity ion is implanted to form the first well isolation region 14.
Referring to FIG. 1B, the first photoresist pattern 12a is removed. Thereafter, a second photoresist film is formed through the foregoing method of defining the first well 16 and is patterned by a photo-etching process, so that a second photoresist pattern 12b is formed. Then, the second photoresist pattern 12b is used as a mask and P-type impurity ion is implanted into the semiconductor substrate 10, so that the first well 16 is formed over the first well isolation region 14. The first well 16 is formed in a cell array region of a DRAM device. In the first well 16 where an N-channel MOS transistor is formed, a sense amplifier, a word line driver, and an input/output gate are formed.
Referring to FIG. 1C, the second photoresist pattern 12b is removed. Thereafter, a third photoresist pattern 12c is formed through the foregoing method of defining a second well 18. The third photoresist pattern 12c is used as a mask and P-type impurity ion is implanted, so that the second well 18 is formed. The second well 18 is formed in a peripheral circuit region of the DRAM device. An N-channel MOS transistor is formed in the second well 18.
Referring to FIG. 1D, the third photoresist is removed. Thereafter, a fourth photoresist pattern 12d is formed through the foregoing method of defining a third well 20. The fourth photoresist pattern 12d is used as a mask and N-type impurity ion is implanted, so that the third well 20 is formed. The third well 20 is formed in a peripheral circuit region of the DRAM device. A P-channel MOS transistor is formed in the third well 20.
Since four photoresist patterns respectively define four regions, four-type-photo processes are essentially needed in the prior method.