Conventional multi-junction solar cells are widely used for terrestrial and space applications and provide the highest efficiency for solar energy conversion. Multi-junction solar cells comprise multiple p-n or n-p diodes (junctions) in series connection, realized by growing thin regions of epitaxy in stacks on semiconductor substrates. Each junction in a stack is optimized for absorbing a different portion of the solar spectrum, thereby improving the efficiency of solar energy conversion. These types of structures are varied and are well known to those skilled in the art.
Typical fabrication steps in state-of-the-art multi-junction solar cell processing have been described by D. Danzilio et al. “Overview of EMCORE's Multi-junction Solar Cell Technology and High Volume Manufacturing Capabilities”, CS MANTECH Conference, May 14-17, 2007, Austin, Tex., USA. Multi-junction solar cell fabrication generally involves two parts; namely, front-end and back-end processing. Front-end processing includes growth of epitaxial layers, front and backside metallization, and solar cell die isolation. Standard semiconductor fabrication techniques are used in front-end processing, which yields multiple solar cell die on a semiconductor wafer. The die are electrically isolated and the cells are fully functional. Back-end processing includes steps such as singulation of cells on the wafer (e.g. using dicing blade), packaging, and wirebonding.
FIG. 1A shows a top view of a prototypical multi-junction solar cell die (prior art) after front-end processing. FIG. 1B shows the side view of the cross-section 9 in FIG. 1A. Solar cell die 100 are typically rectangular in shape and are laid out on wafer 5 using a grid pattern. A regular rectangular grid is preferred to yield the maximum number of cells of a given size on the wafer. Metal busbars 22 and gridlines 2 sit on a mesa structure 6, which is obtained by partially or completely eliminating epitaxial layers 4 along the outer edges of each die 100. This process step is referred to as the “mesa isolation process”. The die on the wafer are electrically isolated as a result of mesa structure formation. The mesa isolation process leaves an exposed region 8 of the underlying substrate that runs near and parallel to the edges of the mesa structures 6. The width y of the exposed corner regions 8 is typically on the order of tens of micrometers and these regions serve as dicing streets. Dicing streets are narrow pathways along which the wafer is to be cut during back-end processing to singulate the die on the wafer. A metal contact region 52 is provided on the backside of the substrate 5 and serves as an electrode. The other electrodes are the busbars 22, which are typically located along one or more edges of each die. Multijunction solar cells typically have additional features as well, such as anti-reflection coating (not shown in FIGS. 1A and 1B) and cap regions 3. Cap regions 3 are patterned epitaxial regions underlying metal gridlines 2 to provide an electrical contact between the metal and the underlying semiconductor structure 41. Such features and structures are well known to those skilled in the art.
The active area of a solar cell is defined as the area that actually absorbs the sunlight and generates photocurrent. The active area includes the grid of thin metal lines 2 placed in parallel or in other configurations but excludes the areas occupied by the busbars 22. Consequently, the areas under the busbars do not contribute to the generated electrical power. Henceforth, the active area is the area of the mesa 6 less the area of the busbars 22. In the design of multi-junction solar cells, busbar width x is chosen using engineering practices such that current is collected with minimal resistive losses, wirebonding requirements are fulfilled, and the busbars occupy a small area on the die.
In the prior art, typical testing procedure includes voltage and current measurements that are conducted while the cell is illuminated from the top with a solar simulator. Voltage and current measurements can be done after front-end processing (wafer scale) as well as after singulation of solar cell die. These measurements are important to determine and eliminate defective die before packaging. Prior art solar cells have features that reduce the accuracy of electrical measurements.
Multi-junction solar cells (prior art) typically have two electrodes. The top electrode consists of the busbars 22 and the gridlines 2 and the bottom electrode consists of the metal coating 52 on the backside. The junctions 41, 42, and 43 are serially connected through the epitaxy. Voltage contributions of individual junctions cannot be measured, merely the total voltage difference across all junctions can be measured. In addition, certain features of the test setup negatively impact the accuracy of voltage measurements.
Wafer scale measurements are typically done when the wafer is placed on a vacuum chuck. Henceforth, the metal-coated back surface of the wafer makes electrical contact with the chuck. Electrical measurements are done through microscopic mechanical contacts (pins or probes, typically on a probe card) on the top electrode (busbars) and through the chuck on the back electrode. Voltage and current are typically measured using independent pins. For voltage measurements, contact resistance between the chuck and the back metal and the resistance of the chuck play an important role. Multi-junction solar cells used in concentrated photovoltaic applications are typically high-current devices. The current may result in a significant voltage drop on the chuck due to the resistance. The voltage measured in the test setup is the total voltage including the voltage drop across the chuck. The voltage component coming from the chuck reduces the accuracy of the measurement of the actual solar cell voltage, which is the voltage across the junctions.
Voltage measurements on singulated cells have additional challenges. FIG. 2 shows a schematic of a diced chip 101 being tested on a vacuum chuck 13. The back metal 52 (back electrode) is in contact with the chuck 13 and the probe card 12 is in contact with the busbar 22 (top electrode). For singulated cells, typically the vacuum pull is not strong enough to ensure a good electrical contact between the chuck and the chip. The downward pressure coming from the probe card 12 may prevent a portion of the backside of the chip 101 from making contact with the chuck 13. These effects result in increased contact resistance between the chuck 13 and the backside 52 of the chip, resulting in a higher voltage drop due to photo-generated current. Furthermore, the contact resistance between the chuck 13 and the solar cell chip 101 is inconsistent from run to run. Therefore, as a consequence there is increased inaccuracy in voltage measurements for singulated die compared to full-wafer testing.
One way to eliminate the uncertainty in voltage measurements is to probe the substrate only from the top for voltage measurements. In this measurement configuration, the path of the photo-generated current stays the same. Referring to FIG. 3, the path of the current I includes the junctions 4, the substrate 5, the contact between the back metal 52 and the chuck 13, and through the chuck 13, each with an associated voltage drop. The voltage V is measured using a probe 14 in contact with the exposed areas 81 on the substrate and another probe (not shown in FIG. 3) in contact with the busbars 22. The voltage measured does not include variations coming from the resistance of the chuck-back contact interface 53 and the resistance of the chuck 13. The contact resistance of the busbars 22 and the contact regions 3 is typically small. The resistance of the contact 145 between the voltage probe 14 and the substrate 5 must also be small. However, since the contact 145 is not on the current flow path, there is much smaller current flowing through this contact compared to other contacts. Consequently, variations in the resistance of the contact 145 do not result in significant uncertainty in voltage measurements. Nevertheless, it may be preferred to provide a metal contact region (not shown in FIG. 3) on the surface 81 of the exposed substrate to facilitate probing. It may also be preferred to flow short pulses of high current for “burning” contacts, to thereby provide a low resistance path between the probe and the substrate.
Probing the substrate from the top typically improves the accuracy of voltage measurements; however, it is not the preferred method in the prior art. Referring to FIG. 1A, the regions 8, where the substrate is exposed, isolate devices on the wafer and serve as dicing streets. There is a requirement to yield the maximum number of chips per wafer in order to minimize manufacturing costs. Consequently, there is a requirement to make y as small as possible; hence the exposed substrate regions 8 occupy a minimum area on the wafer. The width y of the regions 8 is typically chosen to be on the order of tens of micrometers to ensure electrical isolation and fulfill dicing requirements. It is generally difficult to probe the substrate from narrow exposed corner regions. Nevertheless, for wafer scale measurements the width y of the exposed corner regions 8 might be sufficient such that the substrate can be probed by using small probe tips. Although, in many cases it will be difficult to align the probe and the devices on the wafer and the devices can be damaged during testing. On the other hand, for singulated chips (FIG. 3), the exposed substrate region 81 has a much smaller width z compared to y. This is because, after singulation the total width y is shared between two adjacent die and also some of the substrate material is removed during dicing. Therefore, probing the substrate from the top will be much more challenging for singulated chips. For both wafer-scale and singulated cell measurements, if larger substrate probing areas are used, fewer chips can be placed on the wafer. Therefore, front side voltage probing is not a preferred method in the prior art.
In typical multi-junction solar cells, the voltage contribution of individual junctions cannot be determined. The ability to measure the voltage drop on each junction is desirable to determine the root cause of failures and to optimize the performance of solar cell devices. For such voltage measurements, it is required to probe the interconnection regions between junctions. This can be achieved by a layout modification such that the epitaxial material is partially removed in certain areas around the cell so that interfacial epitaxy regions between junctions become exposed and accessible from the top. Such a layout change requires dedicating real estate on the wafer, which can reduce the number of solar cells of a given active area yielded per wafer. Consequently, the voltage contribution of individual junctions is not typically measured in the prior art.
In multi-junction solar cell characterization, it may be desirable to obtain certain electrical measurements without a back metal contact 52. For example, such a requirement may come from a process sequence that includes thinning down the substrate 5 (e.g. by lapping and/or grinding). In such a case, the back metal 52 is provided subsequent to the substrate thinning step. To reduce processing costs, it can be desirable to identify defective devices and low-yield wafers through electrical measurements before the substrate is thinned down. A sacrificial back contact metallization (to be removed before substrate thinning) can be used. However, this approach results in additional cost and complexity in the process.
In summary, there are problems in the prior art of multi-junction solar cell characterization, which are as listed as follows:                1. Using back contacts for voltage measurements adds uncertainty to voltage measurements because of the voltage drop on the test chuck and across the solar cell—test chuck interface.        2. The uncertainty in measured voltage is even more pronounced for singulated cells because of additional resistance at the solar cell—test chuck interface.        3. Probing the substrate from the top can eliminate the uncertainty in voltage measurements. However, this approach typically requires dedicating additional real estate on the wafer, reducing the number of chips yielded from each wafer.        4. Measurement of the voltage contribution of individual junctions in a multi-junction stack is desirable, but typically requires allocating real estate on the wafer, thereby reducing the number of chips yielded per wafer.        5. It is desirable in some process flows to conduct certain electrical measurements without a back contact.        
Thermal runaway is a phenomenon that reduces the lifetime and reliability of semiconductor devices. The power dissipated in a semiconductor device is often released as heat, resulting in an increase in the temperature of a device. In certain semiconductor devices, such as diodes and multi-junction solar cells, the increased temperature may result in an even greater increase in the power dissipated. Such a positive feedback loop typically results in the destruction of the semiconductor device. This process is referred to as “thermal runaway” in semiconductor terminology.
Solar cells tested under sun or under electrical forward bias show a common failure pattern of thermal runaway. Typical III-V solar cell die are bonded to a heatsink before on-sun or forward bias testing. Thermal runaway induced failure may result from an imperfect die-attach process whereby one corner of a die is physically higher than the other three with increased thermal resistance in that corner. The corner of the cell which is the highest will heat up more and consequently thermal runaway failure will occur in that corner. The heating consequences of an imperfect die-attach are further exacerbated by the fact that much of the forward bias current flows under the busbars of the chip, and these busbars typically extend into the corners of the chip.
Both electrical testing and thermal runaway problems of the prior art are addressed by the present invention.