Today's high performance data processing systems rely upon sophisticated memory management systems to translate logical addresses into real (physical) addresses. Logical addresses are the software addresses used by the programmer when writing software. Physical addresses are the hardware addresses used by the semiconductor chips and electronic circuitry running the software.
In a very simple microprocessor-based system, the central processing unit (CPU) is linked directly to memory. With this type of configuration, no memory mapping or task protection capabilities are provided, and the addresses generated by the CPU directly identify the physical locations to be accessed. This type of system, however, is unsuitable for multiple-task operations since there is no protection to prevent corruption of memory used by one task during execution of another.
A memory unit with one or more translation-lookaside buffers (TLBs) is often used to provide the address mapping and the task protection needed to construct a multi-tasking data processing system. The memory unit acts as an interface between the CPU and the physical memory. The memory unit controls all accesses to physical devices, and tasks can be prevented from accessing the memory resources used by other tasks. When under the control of an operating system with virtual memory capabilities, the logical-to-physical mapping functions allow tasks to utilize the entire address space of the CPU to build a memory system as large as the CPU address space without detailed knowledge of the physical characteristics of the system.
The logical address is generated by an instruction unit or a data unit of the CPU and is received as an input by the memory unit. The memory unit, using one or more TLBs, performs address translation and privilege checking for the logical address and, if the mapping is valid, drives the corresponding physical address to the data or instruction cache or some other type of memory. Note that the corresponding physical address produced by a TLB may be used to access either data or an instruction, depending upon whether the TLB is part of a data memory unit or part of an instruction memory unit.
Generally, a memory unit contains one or more TLBs which are used to perform address translation and privilege checking; the memory unit may also contain one or more cache memories which store actual data or instructions. Each entry in the TLB usually contains a logical address, a corresponding physical address, and one or more protection or control bits (collectively called attribute bits or attributes).
Typically, a TLB includes a content addressable memory portion (CAM), a random access memory portion (RAM), and associated control circuitry. The CAM is organized in a number of lines with each line capable of storing a logical address and each line including a corresponding match line. On each operation of the TLB, an incoming logical address is received by the TLB and compared to the logical addresses stored in the CAM. If the logical address matches a stored logical address, a translation "hit" (also called a "match") occurs, and the corresponding match line of the CAM produces a valid match signal.
Generally, each line of the CAM couples to a particular portion of the RAM and the enablement of a particular match line causes the RAM to produce a corresponding physical address. When the CAM does not contain the requisite logical address, a translation "miss" (also called "no match") occurs, and a hardware state machine or a software routing is invoked to search main memory in order to determine the physical address that corresponds to the received logical address. This search is often called a "table search" or a "table walk" because it may require the data processing system to access and read more than one memory table stored in MAIN memory.
The advantage of a TLB is that it saves a great deal of time. Rather than having to access tables in main memory every time a translation is required, the data processing system can quickly access the TLB and receive the correct physical address for certain selected logical addresses.
With the typical translation lookaside buffer, at each access of the TLB, charge is consumed by the CAM and by the RAM. During each operation of the CAM, every match line, in the CAM is precharged and then discharged. Thus, significant charge is shunted to ground during each access or operation of the CAM. Further, during each operation of the TLB, the RAM is accessed. Because the bit lines and the inverted bit lines of the RAM are precharged prior to each access of the TLB, and one half of the bit line and inverted bit lines are discharged on each RAM access, significant charge is dissipated through the RAM during each operation. In many applications such as those applications run from batteries, any charge dissipation is undesirable. Therefore, certain techniques have been developed to reduce the power consumption of TLBs.
One particular prior art circuit for reducing the power consumption of a TLB or other types of memory is described in U.S. Pat. No. 5,280,449 assigned to ARM Research. The described circuit disables the RAM precharge when a logical address provided to the CAM matches a prior logical address that was received by the CAM. Upon a disablement of the RAM, the RAM continues to output the previously translated address. The disclosed precharge disablement technique described requires that the RAM sense amps be bypassed when the precharge is disabled in order to avoid power consumption. Thus, the precharge disablement technique requires bypass circuitry as well as multiplexing circuitry that selectively multiplexes RAM output and the sense amp output, both controlled by the precharge circuitry. The additional circuitry adds overhead, cost, and complexity. Further, the circuitry requires that the active match line of the CAM remain fixed during a memory access wherein the logical input does not change. Therefore, additional circuitry is required to hold the CAM in its prior state during such an operation. In addition to additional size and power consumption, precharge disablement requires the circuit to be precharged and accessed when a different logical address is presented to the CAM. As is well known in the art, it is desireable to maintain small precharge device sizes to minimimize loading and circuit space. This results in choosing between slow precharge operation or larger device sizes to allow for a faster precharge time to imprve performance.
since the precharge is normally slow to allow for to minimize precharge device loading in the circuit.
Thus, there exists a need in the art for an improved fast access translation circuit with minimized power consumption.