In a cell-based IC design, repetitive blocks of circuitry are represented by cells that may be accessed from a design cell library using the software tool. Circuit designers can create a custom design of integrated circuits, printed-circuit boards, and other electronic circuit systems using electronic design automation (EDA) technologies that typically run on an operating system in conjunction with a microprocessor-based computer system or other programmable control system. For analog, RF, and mixed signal design applications, the EDA software allows a user to implement “cells” as a basic element of functionality through a layout editor implemented on a graphical user interface. A given cell may be placed, or “instanced,” many times in a layout design to accelerate the design process. In a cell-based hierarchical IC design, cells disposed higher in an IC design hierarchy may contain instances of other cells lower in the hierarchy. A schematic design cell higher in the hierarchy provides a graphical visual representation of the circuit functionality and hides from the user much of the detail and complexity of design cells lower in the hierarchy. A layout design comprises layout cells. A layout cell contains instances of layout cells and/or physical geometries (e.g., a metal1 stripe).
Often, dummy polysilicon (‘poly’) features are inserted into a layout design to enhance critical dimensions during photolithography and etching processes. As used herein, “dummy poly features” shall refer to polysilicon shapes added to a layout design to ensure correct electrical behavior or correct physical fabrication, and/or otherwise support the integrated circuit manufacturing process. The insertion of dummy poly shapes can improve the regularity of poly and enable tuning of the optical proximity correction (OPC) recipe for improved process windows. For example, dummy poly features often are inserted between cells or between active devices, e.g., transistors, in a layout.
A parameterized cell, or ‘pcell’, is a programmable cell that allows creation of a customized instance of the pcell each time it is placed or used in design. A pcell is typically more flexible than a non-parameterized cell (non pcell) because different instances of the pcell may have different parameter values. For example, with a transistor pcell, the length, width, number of gate segments, and/or other design elements of the transistor, can be realized by simply inserting or changing one or more parameter values. Rather than have many different cell definitions to represent the variously sized transistors in a given design, a single pcell may take a transistor's dimensions (e.g., width and length) as parameters. Different instances of a single pcell can then represent transistors of different sizes, but otherwise similar characteristics.
When instantiating a parameterized cell, a designer specifies values for parameters associated with the parameterized cell. A layout pcell is used to generate geometric structures used in a layout design. A schematic pcell is a variant of a layout pcell, which can be used in schematic designs. The use of pcells obviates the need to store individual instances of each cell. Rather, pcells are evaluated and instantiated when a design is opened, for example. The parameters of a pcell typically are used to determine the geometric dimensions of a corresponding circuit element represented by the pcell. Thus, complex geometric structures that make up circuit elements in an electronic design typically can be generated automatically based upon parameters specified by a circuit designer using a design tool. For example, a circuit designer may assemble a design that comprises multiple cells and may associate parameters with the cells. The design tool uses the parameters to generate geometric structures, represented in software data structures that correspond to actual physical structures that will be used to implement circuit elements represented by corresponding design cells.
A pcell supermaster is a type of parameterized cell that is encoded in a computer readable device and that typically is associated with a list of parameters, parameter types, parameter default values and with logic in the form of computer program code. A designer specifies parameter values of its parameters for the pcell supermaster. An automated design tool uses the logic of the pcell supermaster to generate a cell referred to as a pcell submaster that complies with the user-specified parameter values. Persons skilled in the art will appreciate that a pcell submaster typically is created by evaluating pcell code associated with the supermaster, for a given unique set of parameter values. In a typical session of an automated design tool usage, all regular cell instances of the same pcell supermaster that share the same parameter values typically also will share the same pcell submaster. Thus, instances of a regular cell within a design may be copies of a pcell submaster.
FIG. 1 is an illustrative diagram representing an data structure 100 of a parameterized cell (pcell) that is encoded in a computer readable storage device in accordance with certain prior art. The example parameterized cell data structure 100 includes a supermaster object 102 that includes computer program logic to determine geometric structures, and also includes parameter definitions and default values. Submaster objects 104-1 to 104-N are associated with the supermaster and represent different instances of the design cell that contain different unique geometries produced using code from the supermaster 102 and different unique sets of parameter values. Cell instances 106-1 to 106-N of the design cell inherit geometries from corresponding submasters 104-1 to 104-N.
More specifically, the circuit element represented by the illustrative example parameterized design cell data structure 100 of FIG. 1 is an nmos transistor. The supermaster 202 defines parameters L (length) and W (width) and includes program logic (not shown) to determine dimensions of geometric structures associated with the nmos transistor based upon parameter values. Each of the submasters 104-1 to 104-N represents a different unique instance of the nmos transistor determined with the supermaster logic using a different unique parameter value. For example, assume that a pcell supermaster 102 defines two integer parameters, namely “width” and “length”. As well, assume that pcell supermaster is associated with software logic specifying to create a rectangle corresponding to the user-specified values for a width parameter and a length parameter on some hard-coded layer within a circuit design, such as “metal1”. A designer could instantiate that pcell supermaster within a design and specify on the created instance the width parameter value to be 5 and the length parameter value to be 2. At that point, the tool application can be used to automatically create a pcell submaster 104-1 that will contain a rectangle of width=5 and length=2 on layer metal1. It will be appreciated that often the code associated with a pcell supermaster not only can be used to create geometries but also can be used to instantiate some lower level cell.
In addition to parameters for transistor length, width and number of gate segments, for example, a pcell also may include parameters for dummy polysilicon (poly) features associated with the design cell. The physical dimensions and spacing of devices must comply with design rules that ensure that the layout design complies with fabrication requirements. For instance, in some modern design processes (e.g., 20 nm and below), there is a rule which requires that a diffusion cannot have devices (e.g., transistors) of different widths. In other words, for example, all gate poly segments within a diffusion area should have the same width. Another common rule requires that when two chains of devices of different width are getting close together, they must be separated with dummy poly features of increasing size (from the smaller device width to the greater device width). The term “chain” conventionally refers to a set of devices sharing the same diffusion region. Also, another rule specifies the spacing in between all those poly features as a function of their width.
Moreover, in accordance with certain typical design rules, a chain often is required to be bordered by dummy poly features. A chain typically is implemented using one or more pcells. When implemented with only pcell, that pcell should contain at least two devices (to make a chain, you must be at least 2). If implemented with several pcells, then each pcell would have one or more devices.
Therefore, a pcell includes parameters for dummy features that may include, for example, a parameter indicating a number of dummy poly features disposed to the left of a transistor diffusion region, a parameter indicating a number of dummy poly features disposed to the right of the transistor diffusion region, parameters indicating size, e.g., length and/or width of the dummy poly features to the left and to the right of the diffusion region, parameters indicating spacing of dummy poly features disposed to the left and to the right of a dummy poly. The parameters for dummy features also may include parameters specifying location, size and spacing of dummy transistors associated with a transistor diffusion region.