Advanced high speed semiconductor chips are packaged in modules wherein the chips are physically and electrically mounted on ceramic substrates. The modules can be used as components in an electronic computer. The ceramic substrates contain a plurality of layers, each of which contains a plurality of electrical conductors. Within some of the ceramic layers there are electrically conductive vias electrically interconnecting conductors in adjacent conductive layers. The ceramic layers between the electrical conductors act as electrical insulators. These ceramic substrates are formed by laminating together thin green sheets of glass particles or an admixture of glass and crystalline particles mixed with binders and patterns of paste containing metal particles mixed with binders for forming conductors between the ceramic green sheets and for filling through holes in the green ceramic sheets to form conductive vias between adjacent metallization layers. The green laminate is fired to burn off the binder material, fired to densify the glass particles and metal particles to a dense state, further fired, if necessary, to crystallize the densified glass particles or to further crystallize the admixture of glass and crystalline particles to form an insulator and to coalesce the metal particles to form conductive metal lines and vias.
Ceramic module technology for high end computer packaging uses copper conductors and requires that the sintering and densification of the copper and the ceramic occur at comparable rates over a common co-sintering cycle. Since copper densification rates are usually faster than that of ceramics, a coating of fine alumina particles can be applied to the surface of the copper powder particles by a chemical reduction technique, to retard the kinetics of the copper particle densification to make it comparable to that of the ceramic material. See, for example, U.S. Pat. No. 4,595,181, U.S. Pat. No. 4,600,604 and EPO Patent application 0,272,129 filed Dec. 12, 1987. Due to the small volume fraction of the alumina required, the process involves making a coated powder with large volume and area fraction coverage and mixing this powder with an uncoated powder to achieve the desired average levels of alumina coating. This leads to a problem, in that the coating can be nonuniform and hence result in severe retardation of sintering and densification in some areas and almost no retardation in others. This results in localized shrinkage mismatch between the copper and ceramic material resulting in copper via cracking. An electrical open associated with this cracking can occur in the worse case after complete sintering. A more insidious problem is one where the cracking is only partial after sintering and becomes complete leading to a full electrical open after the module has gone through further processing and chip attachment. Since such modules are generally not reparable they may have to be scrapped. Scrapping a fully fabricated part adds substantially to overall fabrication cost. In addition, a conductive via having a partial fracture could become an open during the operation of the electronic computer containing the module due to crack propagation and hence result in field failures.
The finely deposited alumina particles at the exterior of the copper particles serve to retard shrinkage of the copper during the sintering process of the ceramic. The alumina coating at concentrations typically achievable do not prevent grain growth of the copper during the crystallization temperatures of the ceramic materials typically used to fabricate a semiconductor chip packaging substrate. The result is copper grains which are of the order of 50-100 microns which is of the order of the cross sectional size of vias between the conductive layers in the multi layer ceramic substrate. On cooling, vias which fracture or have the potential for fracture do so by the well known mechanism of intergranular creep fracture. Microvoids, which are the result of vacancy precipitation by low tensile strain rate, accumulate at grain boundaries and may extend across the via. FIG. 1 shows ceramic material 2 having a via 4 therein wherein the via is filled with a copper containing material 6 which is composed of substantially a single grain wherein the grain has a fracture 8 therein and microvoids 10 between the material 6 and the ceramic material 2. The low imposed strain rate is caused by thermal expansion mismatch between the copper and ceramic which results in a relatively large differential size change during cool down from the relatively high sintering temperatures. In some cases large voids formed during sintering may also be found at grain boundaries.
It is an object of the present invention to provide conductive material within a via in a ceramic material wherein the conductive material is formed from grains of electrically conductive material wherein the grain size is substantially uniform and substantially smaller than the size of the via.
Quite surprisingly, applicants have achieved electrically conductive vias having substantially small grain size by providing in metal particles grain growth controlling additives which are substantially uniformly distributed throughout metal particles forming the precursor to the electrically conducting via material. Applicants have achieved this result by a combination of high energy mechanical alloying of the additive with the conducting material and impact jet milling of the mechanically alloyed particles.
These and other object, features and advantage will become more apparent from the following, more detailed description and the drawings and claims appended thereto.