Circulating shift register time-keeping circuits are known in the prior art, see, for example, U.S. Pat. Application Ser. No. 492,303 entitled "Circulating Shift Register Time-Keeping Circuit" filed by France Rode et al. on July 26, 1974. In operation, real time data circulates in serially connected delay elements comprising a circulating shift register (CSR) which is clocked at a predetermined circulation rate. With every complete circulation of the CSR, the data word representing the lowest unit of time data available for readout by the user is incremented by an adder through which the data circulates before re-entering the shift register. In such systems, the rate at which the time data is incremented may be selected to suit the frequency of circulation of that data in the shift register and may actually correspond to the smallest unit of time available to the user.
The operation of a binary adder is described for a time-keeping circuit in the above-mentioned patent application. Since the binary adder only increments, other means must be provided for necessary carry functions between digits and for resetting prior digits to initial values. For example, when the hundredths-of-a-second digit (0.01) is incremented to a value of 0.09, the next increment of that digit must cause a carry of the tenths-of-a-second digit (0.1) and reset of the 0.01 digit from 9 to 0. Means for performing these carry and reset functions are also discussed in the above-referenced patent application (see, for example, the discussion of the operation of adder controller 43 in conjunction with auxiliary register 45 therein).
The incrementer/decrementer of the present invention increments, decrements and performs the carry and reset functions for the contents of circulating shift register memories, and is useful in both clock and stopwatch applications. BCD code has been selected for the preferred embodiment because the incrementer must operate on four-bit digits and count only from 0 through 9. Thus, when a 9 is detected in the first digit (1001 in BCD), then the incremented result should not be a 10 (1010) but rather a 0 (0000), with a "carry" to the next digit.
The preferred embodiment of the present invention comprises a flip-flop, two exclusive OR gates, two exclusive NOR gates and an AND gate. The circuit decrements or increments the contents of a circulating shift register memory in response to appropriately timed control signals as those contents circulate therethrough.