1. Field of the Invention
The invention relates to a circuit and a method for generating a set of, for example, linearly or logarithmically spaced intermediate voltages as needed for analog-to-digital conversion, particularly with flash ADC converters.
2. Related Technology
Several types of analog-to-digital converters (ADC), notably flash and folding converters, operate by comparing an input voltage with a set of reference voltages uniformly distributed over the input signal full scale. The accuracy of these reference voltages is a key factor determining the linearity of the ADC. The present disclosure describes how a set of linearly spaced voltages can be produced as the collective result of an array of interacting self-calibration units. The invention lends itself well to a high-accuracy implementation ensuring linear spacing without resorting to calibration on an external reference. With a minor change in the design of the self-calibration unit, the array can also produce logarithmically spaced reference voltages.
By far the most common way to generate a set of linearly spaced voltages consists of using a chain of identical resistors as shown, for example, in U.S. Pat. No. 6,437,724 B1. When the smallest desired voltage is applied to one end of the chain and the largest desired voltage is applied to the other end, intermediate taps in the chain settle to intermediate voltages with uniform spacing. This is illustrated in FIG. 1.
This approach, while sufficient for many applications, suffers from some drawbacks:
Accuracy is limited by resistor matching. Up to a point, matching can be improved by increasing the geometrical size of each resistor, but for highest accuracy, calibration becomes necessary.
When a current is drawn from the taps of the resistor chain—such as input bias currents of comparators for instance—the tap voltages are no longer uniformly spaced. In order to reduce the impact of such parasitic currents, it is generally necessary to choose very small resistor values, which results in a large power dissipation in the resistor chain.
The output impedance is not the same for all taps of the resistor chain. This drawback is significant in the case of fully differential ADC architectures, where the voltage boundaries are not constant but consist of the input signal of the ADC. At high frequencies, different taps will have different bandwidths and group delays, which creates distortion.