Semiconductor memory devices are subject to defects that may cause some memory cells to be read with incorrect data. For example, in DRAM devices, particularly embedded DRAM (eDRAM), a common defect is a data retention defect, which affects the ability of a memory cell to hold data for a certain minimum period of time. This memory cell with poor data retention is often referred to as a “weak” bit or cell. A data retention defect typically causes the associated bit line to remain near a precharge level when it should be pulled further from precharge (e.g., either towards VDD or ground). A conventional method for testing data retention of a memory cell is to add hold time between writing and reading the cell that is equivalent to or greater than a hold-time specification of the cell during normal operation. Unfortunately, however, this method for testing data retention may add significant time to the testing process, which is undesirably reflected in increased cost of the device.
Weak cells are usually found during hold time or column disturb testing, and can be exacerbated by testing with memory voltage levels (e.g., VDD) at or exceeding logic low and/or logic high specification limits. Weak cells may fail intermittently or fail only with specific patterns in the memory array or only at specific voltages and/or temperatures.
Weak columns typically fail because of imbalances or defects in the columns, precharge devices and/or associated sense amplifiers. Weak columns are generally not attributed to atypical cell leakage characteristics. Charge levels within at least some memory cells along a weak column are typically not sufficient to overcome the imbalances or defects in the precharge devices and/or sense amplifier associated with the column.
Another common failure mechanism affecting memory cells is failure associated with increased cell pass-gate device threshold voltage caused primarily by low temperature. The threshold voltage of the cell pass-gate device increases with decreasing temperature. As is known in the art, increased pass-gate device threshold voltage causes less charge to be written into a cell in one of the two data states (e.g., logic high or logic low). To uncover this type of failure, testing is conventionally done at the lowest specified operating temperature for the device, typically −40 degrees Celsius (° C.) or 0° C. Testing at these temperatures is undesirable because relatively long times are required to reduce and stabilize the temperature of the device under test.
Defects of the type described above are generally discovered during post-manufacture testing of integrated circuit (IC) memory devices and may affect a reliability of the device. Defective memory devices may need to be discarded, thereby reducing the yield of the integrated circuit manufacturing process, and increasing the net manufacturing costs for the non-defective devices.
Accordingly, there exists a need for improved memory testing techniques which do not suffer from one or more of the above-described problems associated with conventional memory testing techniques.