In general, various types of communications systems are implemented using phase-locked loop (PLL) circuits to generate clock signals. For example, PLL circuits are used in transceiver circuits for generating LO (local oscillator) signals, data recovery circuits for generating clock recovery signals, and frequency synthesizer circuits for generating stable frequency output signals over a large continuous tuning range. In general, a PLL circuit uses feedback to maintain an output signal of the PLL in a specific phase relationship with a reference input signal of the PLL, as is well known in the art. When the output frequency of the PLL is equal to the frequency of the reference input signal, the PLL is in a “locked” condition. A frequency synthesizer circuit is essentially a PLL circuit that employs a programmable frequency divider in a PLL feedback loop. PLL circuits can be implemented using analog and/or digital circuits, depending on the application.
By way of example, FIG. 9 is a high-level schematic illustration of a conventional analog PLL frequency synthesizer circuit (10). The PLL frequency synthesizer (10) comprises a PFD (phase-frequency detector) circuit (11), a charge pump (12), a loop filter (13), a VCO (voltage controlled oscillator) circuit (14), and a frequency divider (15) in a PLL feedback loop. In general, the PLL frequency synthesizer (10) generates an output signal Vout having a frequency fout that is some multiple N of the frequency fRef of a reference clock signal Ref_CLK, where fout=N×fRef. The PFD circuit (11) receives the input reference signal Ref_CLK and a feedback signal fDiv and compares the phases of such signals. The PFD (11) generates a slowly varying phase error output signal that is a function of the phase difference between the reference and feedback signals. The charge pump (12) operates in conjunction with the PFD (11) to generate an output current signal based on the detected phase difference using matched current sources. In general, the charge pump (12) and loop filter (13) operate to amplify and filter the phase error signal output from the PFD (11) according to a filter transfer function that is selected to achieve desired loop characteristics such as gain, bandwidth, frequency response, etc., in a manner well known in the art. The loop filter (13) built from resistors and capacitors low-pass filters the phase error signal generated by the PFD (11) and CP (12) and outputs a control voltage to the VCO (14).
The control voltage output from the loop filter (13) is a control signal that is input to a control port of the VCO (14). The VCO (14) may be a voltage controlled LC tank oscillator where frequency tuning is achieved based on the voltage level of the control signal output from the loop filter (13). The control signal could be applied to a variable capacitor or varactor in the case of an LC (inductor-capacitor) VCO, or applied to one or more current sources in the case of a current-starved or delay-interpolating ring VCO. The control signal voltage incrementally increases or decreases so as to drive the VCO (14) output frequency fout in the direction of N×fRef. The output signal Vout is fed back to the PFD (11) via the frequency divider circuit (15), which divides the VCO output frequency by the division ratio N to generate a low frequency signal fDiv. When fRef=fDiv the PLL frequency synthesizer achieves the desired “locked” state.
In advanced semiconductor technologies, the ability to realize good analog PLL circuit performance is problematic, especially as target supply voltages are reduced and operating frequencies increase. Moreover, for mixed digital/analog integrated circuit designs, the realization of a PLL using traditional analog frameworks places demands on the underlying process technology which are significantly different from those driven by high-speed digital logic requirements. Indeed, analog PLL circuits typically require elements that are not used in standard digital logic circuits such as resistors and low leakage capacitors, and analog circuits rely on properties that are not critical to standard logic circuits such as matching and output impedance uniformity.
In this regard, all digital PLL circuit topologies have been developed to address issues associated with analog PLLs. In general, a digital PLL includes a digital phase detector, a digital loop filter (instead of the traditional analog filter), and a digitally-controlled oscillator (DCO) (instead of a VCO as in the analog PLL). A DCO is an oscillator that operates at a frequency controlled by the value of a digital control word that is generated by the digital loop filter. With digital PLLs, signal processing and filtering is performed in the digital domain and a digitally-realized loop filter is much smaller in framework and is more programmable than the capacitor-dependent analog filter frameworks used in analog PLLs.
The digital loop filter provides a digital output that is used as a control signal to frequency tune the DCO. In general, a DCO includes tuning control circuits with tuning elements that are driven by the digital control word logic inputs. The DCO tuning elements may include, for example, non-linear capacitors in an LC DCO that are driven on and off by the control signals to frequency tune the DCO. In other conventional embodiments, the DCO elements may be a plurality of active inverter stages in a ring DCO, wherein frequency tuning is achieved by incrementing/decrementing the number of active inverter stages in a ring DCO.
The digital PLL requires a continuous tuning range, which means that small frequency steps are needed. For example, in a ring DCO, a single frequency step is equivalent to the delay of a unit cell inverter, and in an LC DCO, a frequency step is a capacitance of a unit cell varactor. If the frequency step between adjacent digital control settings is too large, however, it will not be possible to realize a PLL with a low-noise output. One method of providing a lower incremental frequency change per digital step is by using smaller tuning elements (e.g., smaller inverters or varactors). However, the ability to achieve the required fine-grain digital tuning of the LC DCO using this approach can be problematic because there are inherent tradeoffs between fixed capacitance and controllable capacitance associated with changing the size of the digitally controlled capacitor. Indeed, the smaller the controllable step, the more fixed capacitance is introduced as a fraction of total capacitance, and thus the smaller the achievable overall DCO tuning range becomes. The growth in fixed capacitance occurs in large part because the wiring needed to connect the digitally controlled capacitors grows as capacitor count grows. Furthermore, there may be process technology limits that affect how small a controllable capacitor can be.
In other conventional methods, fine tune control of DCOs can be implemented by using dither control circuits such as sigma delta modulator circuits to encode fractional frequency control bits into dithering signal that are input to the DCO to increase the frequency tuning resolution by rapidly switching tuning elements on and off. Although the dithered control process enhances resolution, the dither control bit still provides a large frequency step based on the size of each unit tuning element of the DCO. Moreover, once the switching frequency is realized as high as possible (limited by the electronics, available clock rates, power dissipation), and the step size is minimized the step size, dithered control may be insufficient to achieve the desired tuning accuracy. As such, new techniques to further enhance the frequency tuning resolution of DCO circuits in PLL circuits and other circuits are highly desirable.