Modern computer systems have the capacity to store in memory, manipulate and transmit data in byte-blocks. Universally, a data byte contains eight bits of information. Typically, a data "word" consists of two bytes of data or 16 bits and a double word, "dword," consists of four bytes or 32 bits of data. In a 32-bit computer system, a dword of data can be addressed by a single address location, e.g., address n, and all 32 bits of the dword are presented on the 32-bit data bus in parallel. Historically, there are two different byte ordering formats which define the sequence in which individually addressed bytes are stored in the dword. Some computers, like the x86 architecture systems, use little endian format while other computer systems, like Motorola architecture systems, use big endian format.
FIG. 1A illustrates a byte ordering format called "little endian" 12 in which individually addressed bytes of a dword are stored in sequence starting from the least significant end (right hand side) of the dword and increase in address sequence to the most significant end (left hand side), e.g., byte #0, byte #1, byte #2, byte #3. This format is referred to as "little" endian because the bytes in ascending address order are filled from the least significant end of the dword. In "big endian" 14, individually addressed bytes of a dword are stored in ascending address sequence starting from the most significant end (left hand side) of the dword and increase to the least significant end (right hand side), e.g., byte #0, byte #1, byte #2, and byte #3. This format is referred to as "big" endian because the bytes in ascending address order are filled from the most significant end of the dword. As shown by a dword represented on the data bus, in either of the above formats, the least significant byte of the dword is presented on data lines "A" (D7:D0), and next-to-the least significant byte of the dword is presented on data lines "B" (D15:D8), the next-to-the most significant byte of the dword is presented on data lines "C" (D23:D16) and the most significant byte of the dword is presented on data lines "D" (D31:D24).
If packet data is always defined in the same size, or is naturally address aligned (e.g., bytes at any address, or words on modulo-2 address boundaries, or dwords on modulo-4 addresses), then endian domain conversion is not complicated. In reality, however, data packets consist of a mix of differently sized operands aligned at address boundaries that are completely arbitrary. With byte, word and dword accesses moving data at odd-byte and off-word boundaries, the permutations involved in steering the data become very difficult for a conversion circuit. FIG. 1B illustrates a generalized flow of data from one endian 10 domain to another 26. So is the start address for Data Packet 0 (numbered 30) and E.sub.0 is the end address for Data Packet 0. Packets 1 and 2 (numbered 32 and 34) are numbered similarly. All addresses may be assigned arbitrarily by software to be of any byte location within system memory. In this environment, conversion between endian domains (e.g., little to big and big to little) is a complicated problem faced between computer systems when data packets of arbitrary data size and address alignment need to be transferred between computer systems. It would be advantageous to provide an endian conversion circuit that has the flexibility to convert data packets starting on arbitrary address boundaries and of arbitrary packet lengths.
FIG. 2 illustrates a prior art system 11 for performing endian conversion between a first bus of one endian domain format 10 and a second bus of another endian domain format 26. In this system 11, an endian domain formatted dword from 10 enters a 32-bit register 12, is manipulated by a 32-bit to 32-bit switch 14, and its four bytes are independently routed to four FIFOs 16, 18, 20, and 22. The bytes are then multiplexed in a standard (e.g., predetermined) sequence by multiplexer 24 and output in a byte stream over bus 26. The logic 28 required to perform the endian domain conversion operates on the write side by controlling switch 14, via control bus 14a, as the data is written into FIFOs 16-22. Switch 14 while functional, is very expensive to implement in terms of silicon area and circuit resources and slows down the write data path considerably. It would be advantageous to provide an endian conversion circuit that eliminates the need for a large bit switch 14 to simplify and thereby improve the data throughput speed of the write path.
Accordingly, what is needed is an endian conversion circuit that has the flexibility to convert data packets that start on arbitrary address boundaries and are of arbitrary packet lengths. The present invention provides such a flexible system. Further, what is needed is an endian conversion circuit that eliminates the large bit switch on the write path. The present invention provides such a system. These and other advantages of the present invention not specifically recited above will become apparent within further discussions of the present invention presented herein.