Semiconductor memory devices include, for example, static random access memory (SRAM) and dynamic random access memory (DRAM). A DRAM memory cell generally includes one transistor and one capacitor, thereby providing a high degree of integration. The capacitor can be either charged or discharged to store information as a corresponding bit value (e.g., 0 or 1). Because capacitors leak charge, the stored information eventual fades unless the capacitor charge is refreshed periodically. Due to the refresh requirement, DRAM is referred to as dynamic memory as opposed to SRAM and other static memory. The continuous refreshing of DRAM generally limits its use to computer main memory.
DRAM scaling continues to increase the total number of bits for each DRAM chip, directly impacting the specification of DRAM refresh, the process by which a cell's value is kept readable. The specification of DRAM refresh includes the interval at which refresh commands are sent to each DRAM (tREFI) and the amount of time that the refresh command occupies the DRAM interface (tRFC). Unfortunately, DRAM scaling increases the number of weak retention cells (e.g., cells that have a reduced retention time). Such cells involve additional refresh cycles to maintain the stored information. A significant performance and power consumption impact is caused by the increased refresh cycles in a system on chip or other like computer architecture. Otherwise, potential DRAM chip yield loss results without increased refresh cycles.