High speed data transfer between semiconductor devices in an electronic system may be achieved by the use of a serialiser/deserialiser (SerDes). In order to avoid the use of a plurality of parallel connections between devices, a single differential analogue path is used running at a high data rate. One exemplary arrangement is specified by IEEE 802.3/AE/AP.
The interconnect between the transmitter and receiver device, known as a transmission channel, distorts the serial data signal to varying extents. The transmission channel is the electrical path between the transmitter and receiver, and is susceptible to noise and interference.
As serial interface transmission speeds increase, the channel losses present in the transmission medium become harder to equalize in order to maximize the bit-error-rate (BER) of the transmission system. Additionally, the losses also increase as the transmission channel length increases. It becomes increasingly difficult to equalize the transmitted and received waveforms in order to compensate for the channel losses. As SerDes transmission rates approach 40 GBits/sec and head towards 100 GBits/sec, a novel means of performing channel equalization is required that can exploit possible future silicon technologies.