Some CMOS delay flip-flops use a number of inverters and transmission gates. Each transmission gate includes a P channel and an N channel transistor which are connected in parallel. Due to the difference in conductivity type, one or the other must be in a separate well. For example, the P channel device may be in an N well. Due to this fact, the two transistors which form the transmission gate must be physically separated. The interconnection between the two transistors is thus typically longer than is typical for interconnection between two transistors of the same conductivity type. Interconnection between differing conductivity types increases layout complexity and consequently requires more chip area. It is desirable then to reduce the number of transmission gates as well as reducing transistor count in optimizing use of chip area.