The transfer rates used on dynamic random access memory (DRAM) channels continue to increase. The faster transfer rates increases the likelihood of transmission errors on the DRAM channel. Some conventional systems use cyclic redundancy codes (CRC) to provide error protection for data transmitted on the DRAM channel. The generation and incorporation of CRC bits into a frame increases the DRAM read latency. Additional latency is incurred on the host side by regenerating the CRC checksum to validate the read data.