With continuous shrinking of minimal feature size, leaky current is expected to become a major challenge for future complementary metal oxide silicon (CMOS) designs. Although each is about 10% of total chip power for the current generation of CMOS technology, the number is expected to rise to 50% for next generation techniques. The increasing leakage current not only poses a problem for battery powered devices, such as mobile and hand-held electronics, it is increasingly critical for active operation as it is becoming a higher percentage of total power.
Most of the leakage estimation and reduction techniques have focused on sub-threshold leakage due to the lowering of the power supply voltage and the accompanying reduction of the threshold voltage. With the reduction of the gate oxide thickness, the gate leakage current can no longer be ignored. Gate leakage is on a trend to become comparable to the sub-threshold leakage. An accurate full chip leakage estimation needs to consider both gate and sub-threshold leakage.
There are various methods that have been used to estimate the full chip leakage; for example, a linear regression model may estimate full chip leakage based on the gate count in the application specific integrated circuit (ASIC) environments. It is known that the leakage current has strong dependency on the environmental factors, such as device channel temperature, power supply voltage and workload. However, most methods for determining leakage have not taken these parameters into consideration. The dependency of leakage on temperature has an order somewhat greater than linear, for example, a 30° C. change in temperature may affect the leakage by 30%. The dependency of leakage on power supply voltage is exponential; a 20% fluctuation in Vdd may affect the leakage power by more than a factor of two.
Chip designers use empirical methods to estimate leakage power, which assumes a uniform temperature and Vdd distribution across the whole chip. However, in today's complex industrial designs, both temperature and Vdd fluctuations have very strong locality, i.e., they are not uniform across the chip. The exact amount of the fluctuations at certain locations depends on the distribution of the transistors and decoupling capacitors, the workload, as well as the quality of the power grid and package design. Empirical methods in full chip leakage estimation are too simplistic, and thus inaccurate.
Therefore, there is a need for a method for determining the leakage power of a full chip IC that considers the effects of temperature and voltage distribution across the IC.