The invention relates to semiconductor device fabrication and, more particularly, to techniques for removal of residual process films (e.g., polymeric and refractory films) and debris from the edge region (perimeter and bevel) of a semiconductor wafer.
Semiconductor wafers are typically round (circular, disc-like), usually having a diameter ranging from 150-350 mm and a thickness of 1-1.5 mm. Integrated circuit (IC) devices are formed in an interior “device area” on the front (or device) side of the wafer. Typically, nothing is formed on the back side of the wafer. The edge (perimeter) of the wafer is typically beveled.
The normal processing of semiconductor manufacture include the deposition of numerous films, many of which serve as insulators for the creation of inter-level dielectric layers to isolate the metal lines between each level. These films are often organic polymers (e.g. SiLk®), silicon dioxide, carbon substituted silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide and nitrogen substituted silicon carbide and tantalum nitride or tantalum oxide. These films are deposited to serve as diffusion barriers between metal levels, the inter-level dielectric (ILD), or masking layer. Masking layers are frequently used for the reactive ion etching (RIE) or as a polish stop during chemical-mechanical planarization (CMP). The number of films deposited for each level and the number of levels needed for modern semiconductor devices (often 10 or more) results in layers of films on the wafer perimeter that are usually highly stressed. When stress for the film exceeds the yield strength the films crack and delaminate resulting in a release of unwanted particulate across the device area of the wafer. Theses foreign materials reduce wafer device yield.
A semiconductor wafer that has been processed in a typical manner can have undesirable films and or residues on the perimeter or beveled edges of the wafer, in what is referred to herein as the “edge region” of the wafer. These films may result from a processing step during film deposition or as a consequence of a plasma etch process used to form three-dimensional features in the wafer, including vias or trenches. Frequently though, the deposition of the film occurs across the full area of the device side of the wafer, the beveled edges and a small segment of the perimeter of the back side of the wafer. There are frequently several films deposited per device level. This film(s) deposition is often repeated numerous times for each level of the semiconductor manufacturing process. Consequently, these multiple layers which build up in the edge region can result in high film stresses which in turn fracture and result in shards or fragments of the films landing on the device side of the wafer. These unwanted pieces of foreign matter can result in unwanted defects in the device area of the wafer, reducing performance or device yield. The need to remove excess deposits from the edge region of the wafer is understood by those skilled in the art.
Chemical spray processes have been used to remove polymeric films in the edge region, but with limited success owing to limitation of reagents that can be used with acceptable selectivity to the other films present. Special protective means are needed by wet processes to prevent unwanted chemical attack to device area of the wafer.
Plasma processes have been developed where the etch tool itself has been modified to remove unwanted films at the edge of the wafer. Most often, the plasma power is applied through the full body of the wafer risking unwanted etching of the wafer or plasma induced damage. Also the plasma processes do not necessarily get to the bevel of the wafer where the unwanted films may have also been deposited.
“Wafer Edge Region Cleaning With A Torus-Shaped Capacitively Coupled Plasma” by Buil Jeon et al., Department of Physics, Korea Advanced Institute of Science and Technology (KAIST), Guseong-dong, Youseong-gu, Daejeon, Korea (hereinafter referred to as “Jeon”), discloses a torus-shaped Capacitively Coupled Plasma (CCP) source to remove harmful film layers and particles deposited on a wafer's edge, bevel and backside during film deposition or other semiconductor processes. A plasma is generated along 2 mm of an edge and 4 mm of a backside of a wafer. Therefore, films and particles can be removed from the wafer edge, bevel and backside without damaging patterns elsewhere on the wafer.
In Jeon's technique, the wafer is placed on a powered electrode surrounded by two grounded electrodes. A ceramic gas distribution panel (GDP) is disposed between 0.3 mm-0.5 mm from the front side of the wafer. Due to this very narrow gap between the GDP and the wafer, plasma could not be generated on the inner side of a wafer where the semiconductor chip patterns are located.
Jeon's process/apparatus creates a torus-shaped plasma that encompasses the edge perimeter of the semiconductor wafer. In this apparatus the wafer rests on an RF powered electrode and has a gas distribution plate (GDP) over the majority of the wafer leaving only an predefined region of the wafer perimeter uncovered. The size of the powered electrode is also sized such that the back surface of the wafer has a region that is uncovered area and is similar to the wafer top face. Gases are flowed through the openings between the concentric GDP plates and upper perimeter grounded electrode. An RF (13.56 MHz) plasma is generated between the powered wafer/electrode and the grounded electrode. The spacing between the GDP and the wafer surface is between 0.3 and 0.5 trim.
Jeon's plasma created results in etching of films on the exposed areas of the wafer including the front, edge, and back areas of the wafer. Additionally, the front area of the wafer under the GDP is also etched but at decreasing amounts towards the center of the wafer. This etching under the GDP results from some penetration of the plasma into the space between the GDP and the wafer face but is most likely from the diffusion of reactants from the plasma toward the wafer center. The data presented in FIG. 4 shows a change of film thickness at the center of 8000 Å to the open area of 3000 Å. The greatest change occurs under the GDP with a 5000 Å reduction in film thickness. Part of the powered wafer/electrode influence is to induce reaction between diffused reactants and the film as a direct effect of the RF power.