Q:

grouping of bits in square root division

I have written verilog code for square root of a number which is parametrised. If the number of bits are even the code works. 
If the number of bits are odd, the code divides the number of bits into groups of two starting from the right (LSB). The first iteration will select the group which has 1 bit starting from the left most bit. 
I am using a counter to go through the required number of cycles. I do not understand how I should select the group of 1 bit for the first iteration, and 2 for the rest of the iterations.  

A:

Variable number of bit selections does not seem like it would be practical in hardware. If you showed some code answers might be a little more relevant or practical.
Two ways of solving this:

Pad the number on detection of odd number, adding MSB of 0.
Have an if else in the iteration which selects 1 or 2 bits selectively padding the LSB.  

Code example for 1.
parameter DATA_W = 11;
parameter odd    = DATA_W % 2;
input [DATA_W-1:0] data;
reg   [DATA_W-1+odd:0] data_int;

always @* begin
  if (odd)
    data_int = {1'b0, data};
  else 
    data_int = data;
end

Code example for 2.
// Iteration for( loop=0; loop<max; loop=loop+1) begin
  if ((loop == 0) && (odd)) begin
    sel = {data[0], 1'b0};
  end 
  else begin
    sel = data[loop*2+1:loop*2]; 
  end
// end

This should be able to be statically unrolled as odd is based on a parameter and loop has a fixed number of iterations. If a loop can be statically unrolled then it is synthesizable.

