Miniaturization of metal-oxide-semiconductor field-effect transistors (MOSFETs) has improved speed performance and reduced cost per unit function of integrated circuits. One way to improve transistor performance is through selective application of stress to the transistor channel region. Stress distorts or strains the semiconductor crystal lattice and interatomic bonding. The strain, in turn, affects the band alignment and charge transport properties of the semiconductor. By controlling the magnitude and distribution of stress in a finished device, manufacturers can increase carrier mobility and improve device performance. There are several existing approaches of introducing stress in the transistor channel region.
One approach includes forming an epitaxial, strained silicon layer on a relaxed silicon germanium (SiGe) layer. Because SiGe has a larger lattice constant than Si, the epitaxial Si grown on SiGe will have its lattice stretched in the lateral direction, so the Si will be under biaxial tensile stress. In this approach, the relaxed SiGe buffer layer is referred to as a stressor that introduces stress in the channel region. The stressor, in this case, is placed below the transistor channel region. In another approach, a high-stress film is formed over a completed transistor. The high-stress film distorts the silicon lattice thereby straining the channel region.
One problem facing CMOS manufacturing is that NMOS and PMOS devices require different types of stress in order to achieve increased carrier mobility. For example, a biaxial, tensile stress increases NMOS performance approximately twofold. However, for a PMOS device, such a stress yields almost no improvement. With a PMOS device, a tensile stress improves performance when its perpendicular to the channel, but it has nearly the opposite effect when it is parallel to the channel. Therefore, when a biaxial, tensile film is applied to a PMOS device, the two stress effects almost cancel each other out.
Workers are aware of these problems. Therefore, new CMOS manufacturing techniques selectively address PMOS and NMOS devices. An NMOS fabrication method includes using tensile films to improve carrier mobility. A PMOS fabrication method includes using substrate structures that apply a compression stress to the channel. One PMOS method includes selective application of a SiGe layer into the source/drain regions. Another method uses modified shallow trench isolation (STI) structures that compress the PMOS channel.
The use of additional materials, however, adds further processing steps and complexity to the manufacturing process. Therefore, there remains a need for improving the carrier mobility of both NMOS and PMOS devices without significantly adding to the cost or complexity of the manufacturing process.