Since the invention of the integrated circuit, the semiconductor industry has experienced continual rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, allowing for the integration of more components into a given area.
These integration improvements are essentially two-dimensional (2D) in nature, in that the volume occupied by the integrated components is essentially on the surface of the semiconductor wafer. Although dramatic improvements in lithography have resulted in considerable improvements in 2D integrated circuit formation, there are physical limits to the density that can be achieved in two dimensions. One of these limits is the minimum size needed to make these components. Also, when more devices are put into one chip, more complex designs are required.
Three-dimensional integrated circuits (3D IC) have been therefore created to resolve the above-discussed limitations. In some formation processes of 3D ICs, two wafers, each including an integrated circuit, are formed. The wafers are then bonded with the devices aligned. Deep vias are then formed to interconnect devices on the first and second wafers.
Recently, through-silicon-vias (TSVs), also referred to as through-substrate-vias or through-wafer vias, are increasingly used as a way of implementing 3D ICs. Generally, a bottom wafer is bonded to a top wafer. TSVs are often used in 3D ICs and stacked dies to provide electrical connections and/or to assist in heat dissipation. There are challenges in forming TSVs in 3D ICs and stacked dies.