The present invention concerns a method for making transistors with ultrashort channel lengths.
Lots of efforts intend to reduce size of circuitry (on silicon or other substrates), combined with attempts to increase switching speeds by reducing channels lengths more than what follows from design rules and lithography. Circuitry reduction is part of the silicon world""s extensive efforts, the limits are soon reached for photolithography, X-ray lithography and other more exotic approaches are very seriously being pursued, with the goal of reaching line widths and line distances around 0.04 xcexcm (40 nm) in production within 2010. This, however, is still largely measured by what is desirable, e.g. single molecular switches, nanoswitches and the like.
Alternative, non-lithographic patterning techniques may hold better promise, e.g. micropatterning or self-assembly techniques. However, the latter are even more exotic than the most advanced lithography trials, since they introduce completely new processes and equipment into a very conservative industry. Also none of the two have the actual potential at present or possibly ever to allow the building of complex circuitry, partly because of registration issues, partly because of problems related to building multilayer structures. Other techniques (e.g. using hard stamps), are facing the same problems.
The problems that cannot be solved by known technology is: 1) making very short (few atoms long) channel lengths, i.e. the distance between the source and drain electrodes, 2) achieve this using either standard silicon procedures, fabrication techniques and equipment or non-standard, non-lithographic techniques, 3) use this to obtain smaller circuitry footprint, i.e. denser circuitry, with a given lithography/patterning tool, 4) achieve the above with self-registration.
Hence the object of the present invention is to provide a method that in an advantageous manner overcomes the inherent problems of present and prior art technology as listed above.
The object of the invention, as well as a number of further features and advantages are achieved with a method according to the invention comprising the following steps:
a) depositing a conducting material on a substrate of semiconductor material,
b) patterning the conducting material into parallel strip-like first electrodes, with a pitch determined by an applicable design rule and leaving exposed strip-like areas of the substrate between the first electrodes,
c) depositing a barrier layer covering the first electrodes down to the substrate,
d) doping the substrate in the exposed areas thereof,
e) depositing a conducting material over the doped areas of the substrate, thus forming parallel strip-like second electrodes thereabove,
f) removing the barrier layer covering the first electrodes, leaving vertical channels extending down to the undoped areas of the substrate between the first and the second electrodes,
g) doping the substrate in the exposed areas thereof at the bottom of the channels,
h) filling the channels with a barrier material,
i) removing the first electrodes, leaving openings between second electrodes and exposing areas of the substrate therebetween,
j) doping the exposed areas of the substrate in the openings where the first electrodes have been removed,
k) depositing a conducting material in the openings to regenerate the first electrodes, whereby an electrode layer of approximately equal-width parallel strip-like first and second electrodes are obtained, interfacing the doped substrate and separated by an arbitrarily thin layer of barrier material only, such that the first electrodes now either constitute source or drain electrodes and the second electrodes correspondingly drain or source electrodes of transistor structures, as dependent on the dopants used in the doping steps,
l) depositing an insulating barrier layer over the electrodes and the separating barrier layers,
m) depositing the conducting material on the top of the barrier layer, and
n) patterning the conducting material to form parallel strip-like gate electrodes oriented crosswise to the source and drain electrodes, whereby a matrix of field-effect transistor structures are obtained with very short channel length and arbitrarily large channel width, the latter as given by the gate electrode patterned.
In the method according to the invention it is considered advantageous that the conducting material is a metal, or that the conducting material is selected as an organic material, preferably a polymer or a copolymer material.
Generally it is considered preferable that photomicrolithograpy is used in the patterning steps, but equally preferable non-lithographic tools could be used in the patterning steps.
In the method according to the invention the barrier layers and/or the electrodes preferably are removed by means of etching.
Preferably the thin-film/thin barrier layer is formed by a selective deposition process or alternatively the thin-film/thin barrier layer can be formed by spraying.
In the method according to the invention the patterning advantageously can be performed by means of etching.
In the method according to the invention it is also considered advantageous selecting the semiconductor substrate material as silicon.
Finally, in the method according to the invention the matrix or transistor structures can advantageously be divided up as appropriate to form individual field-effect transistors or circuits of more than one transistor of this kind.