Low-energy multimedia processing is growing in importance given the demands of current and emerging mobile devices. Devices such as smart phones, tablets, and other handheld devices are often expected to integrate increasingly advanced technologies that require higher performance levels. In order to accommodate these requirements, processors have now commonly adopted multi-core architectures for performing various multimedia processes such as video decoding, video encoding, and image signal processing, amongst others. An example of a multi-core multimedia processing system 10 is shown in FIG. 1. An example of one of the multimedia cores of FIG. 1 is a video decoder (VDEC) core 20, such as that shown in FIG. 2.
Along with these high-performance architectures, however, the maintenance of low power usage and long battery life has become critical for controlling power and thermal issues. The majority of power consumed by a system-on-a-chip (SoC) circuitry is comprised of dynamic power (αCVDD2F) and leakage power (VDDILEAK), where α=activity factor, C=capacitance, VDD=supply voltage, F=clock frequency, and ILEAK=leakage current. As transistor sizes scale down and levels of integration increase, leakage power has become a dominant problem in modern low-power system designs.
An approach is needed for a low-power system design that can effectively reduce power consumption in the context of multimedia processing.