This invention relates to integrated circuits and more particularly to integrated circuits with cyclic redundancy check circuitry.
Many integrated circuits use cyclic redundancy check (CRC) circuitry for error checking in data storage and transmission applications. A cyclic redundancy check is performed by a polynomial division of user data by a pre-defined divisor. The remainder of the polynomial division, a so-called check value, is attached to the data before transmission or storage. Upon retrieval or reception of the data, the polynomial division is repeated and the resulting calculated remainder is compared to the check value. Mismatches in the comparison are indicative of data corruption.
A cyclic redundancy check (CRC) is usually performed for each data packet. A data packet consists of multiple bits or words. The start of packet starts a CRC calculation and the end of packet stops a CRC calculation. Cyclic redundancy check (CRC) circuitry typically has a fixed input data path width, (i.e. it can receive a fixed number of bits or words and perform an incremental cyclic redundancy check on the received bits or words at a time and then moves to the next increment of data for more incremental CRC computation). Therefore, the start of a data packet or the end of a data packet or both may not be aligned with the last and first word or bit of the CRC circuitry's input data path.
Conventional CRC circuitry has addressed this problem by pre-computing the contribution of each data word or bit to the CRC result as though that word or bit was 1, 2, 3, . . . n words or bits from the end of packet and performing a logic exclusive OR operation on all pre-computed contributions at the position of the end of packet. This approach is problematic because the size of the CRC circuitry quadruples whenever the data path width is doubled.