1. Field of the Invention
The present invention relates to a multilayer circuit board and a manufacturing method thereof, and more particularly to a multilayer circuit board with via holes filled with conductive paste for providing interconnection between layers and a manufacturing method thereof.
2. Description of the Related Art
As electronic equipment becomes lighter, thinner, and smaller, the size and terminal pitch of semiconductor chips and electronic components are reduced, and accordingly printed circuit boards and package boards become more densely packed. Information technology equipment now requires shorter wiring distances between chips as the signal frequency has increased. Multilayer printed circuit board (PCB) technology has become essential to build high density, high performance circuits.
The key issue of multilayer circuit boards is how to establish electrical connection between layers to form three-dimensional circuits. Double-sided boards, which are the first step to building multilayer circuit boards, are fabricated by drilling holes in an insulating material and plating the walls of the holes with a conductive material to achieve interconnection between the front and back surfaces (see, for example, “Build-up Multilayer PCB Technology” by Kiyoshi Takagi; The Nikkan Kogyo Shimbun, LTD; published on Jun. 15, 2001; first edition; second printed version; p. 53-76). Sequential build-up boards such as surface laminar circuits (SLCs) of IBM also use plating for achieving interconnection, part of the insulating layer between circuit layers being removed by laser or the like.
While the plating method has the advantage of accomplishing a low resistance connection between fine circuits, it involves complex processes and a large number of process steps, which increases the cost and poses a limitation to the application of multilayer circuit boards.
As disclosed, for example, in Japanese Patent Publication No. 7-147464, multilayer circuit boards using conductive resin paste instead of metal plating have been put in use recently and multilayer circuit boards are beginning to find wider applications.
One method of manufacturing multilayer circuit boards using conductive paste for interconnection will be briefly described with reference to FIG. 7A to FIG. 7H. FIG. 7A shows an insulating resin plate or film 71, in which via holes 72 are drilled as shown in FIG. 7B by laser. Conductive paste 73 is then filled in the via holes 72 by printing, to obtain an insulating layer 74 that has interconnecting parts at desired locations, as shown in FIG. 7C. Copper foils 75 are heat-bonded to both sides of the insulating layer 74 as shown in FIG. 7D, and wiring patterns 76 are formed in the copper foils 75 by etching as shown in FIG. 7E. These processes are repeated and several layers are bonded together (FIG. 7F to FIG. 7H) to obtain a multilayer circuit board 77.
Other methods include, as with SLCs, using a photosensitive resin for the insulating layer and forming via holes by exposure and development, or removing resin by chemical etching or dry etching.
In the meantime, the base material thickness of each laminated layer of multilayer circuit boards has reduced from approximately 0.1 mm to approximately 0.025 mm as the boards are more densely packed, especially in bare-chip multichip module packaging. Insulating films in such laminated boards tend to bend or wrinkle, because of which dimension stability is becoming hard to achieve.
Japanese Patent Publication No. 2004-221426 shows a multilayer circuit board that uses conductive paste for interconnection and that provides a solution to this problem. The manufacturing method of this multilayer circuit board is described with reference to FIG. 8A to FIG. 8D. A laminate film is first prepared, which is formed by a polyimide film 81 that will be an insulating resin layer, a copper foil provided on one surface of the film, and an adhesive layer 83 of thermoplastic polyimide bonded to the other surface of the film. A resist film is heat-bonded on the copper foil, which undergoes exposure and development to form a resist mask pattern. This is followed by chemical etching to form a circuit pattern including lands 84 and fine apertures 85. Then, a PET film is bonded on the adhesive layer 83 and via holes 86 are drilled by YAG laser. Conductive paste 82 is filled in the via holes 86 by squeezing from the front surface of the PET film. When the conductive paste 82 is dry enough, the PET film is removed. FIG. 8A shows the thus obtained board 90 that will constitute one layer in a multilayer wiring board when laminated.
Another board 91 with a circuit pattern including lands 84 and fine apertures 87 is fabricated similarly, another copper foil 88 is prepared, and as shown in FIG. 8B, fine apertures 87 are formed by etching in the copper foil at positions corresponding to the via holes.
Next, as shown in FIG. 8C, the boards 90 and 91 and the copper foil 88 are superposed such that the via holes 86, the lands 84, and the fine apertures 87 are precisely matched in position.
The boards 90 and 91 and the copper foil 88 are then united by applying heat and pressure, as shown in FIG. 8D. The copper foil 88 is etched to form lands 89, to complete a three-layer board.
With this method, while using a thin film, a high rigidity is achieved because fabrication of each layer starts from a copper clad laminate consisting of a resin film and a copper foil which later form an insulating layer and a conductor layer, respectively.
On the other hand, this conventional method shown in FIG. 8A to FIG. 8D requires precise positioning between the via holes 86 and the lands 84 of the boards 90 and 91, and the fine apertures 87 of the copper foil 88, as they are superposed and united by applying heat and pressure. The positioning between via holes and lands is especially difficult, as lands in high density wiring have a very small diameter.
For example, in a conventional wiring level, if the land diameter is 0.3 mm and the via hole diameter 0.15 mm, the allowable range of error is ±0.53 mm in order that the via holes are inside the corresponding lands, whereas, in a high density wiring board, the land diameter and the via hole diameter are as small as 0.1 mm and 0.05 mm, respectively, in which case the allowable range of error would be ±0.018 mm. If the via hole is offset from the land, the electrical connection resistance increases or varies, which will lead to a problem.
High density boards use a 0.025 mm line/0.025 mm space wiring rule. However, with the chemical etching process, which is performed after forming a resist mask by exposing and developing a pattern in a resist film that is heat-bonded on the copper foil to form the wiring pattern including the lands 84 and the fine apertures 85, the line bottom of the circuit pattern may be made to be 0.025 mm wide, but the line top is usually reduced to approximately 0.015 mm wide by the side-etching effect. Such reduced pattern line width will make it difficult to mount semiconductor chips by wire bonding of gold wires, because the bonding points will easily be displaced from the pattern lines.
Multilayer circuit boards using conductive paste had the drawbacks that the electric resistance of the conductive paste was high and contact resistance between the paste and copper foil circuit was unstable, but various improvements have been made. In the case of using a 0.1 mm thick “B” stage prepreg made of aramid nonwoven cloth impregnated with epoxy resin to prepare multilayer circuit boards using conductive paste, when heat and pressure are applied to the prepreg and the copper foils in the uniting process, the prepreg is compressed between the copper foils and conductive fillers in the conductive paste make tight contact with each other and with the copper foil lands, whereby electrical connection is established. On the other hand, in the case of using a thin base material of about 0.025 mm thickness made of an insulating film such as polyimide and an adhesive layer for high density wiring boards, the thickness of the insulating material cannot be further reduced by compression, and therefore the wiring pattern including lands is embedded in the adhesive layer to increase the compression rate of the conductor paste layer, so that the conductive fillers make tight contact with each other and with the copper foil lands to establish electrical connection. With the above-described conventional board in which lands protrude from the insulating layer on the front surface of the board, the conductive paste could not be compressed enough to achieve the effect of reducing electrical connection resistance.