The present disclosure relates to semiconductor structures, and particularly to flip chip bonding employing bonding pads including reactive materials, and a structure for effecting the same.
Once formation of semiconductor devices and interconnects on a semiconductor wafer (substrate) is completed, the semiconductor wafer is diced into semiconductor chips, or “dies.” Functional semiconductor chips are then packaged to facilitate mounting on a circuit board. A package is a supporting element for the semiconductor chip that provides mechanical protection and electrical connection to an upper level assembly system such as the circuit board. One typical packaging technology is Controlled Collapse Chip Connection (C4) packaging, which employs solder balls each of which contacts a C4 pad on the semiconductor chip and another C4 pad on a packaging substrate. Other packaging technologies employ micro C4's or C2's. The packaging substrate may then be assembled on the circuit board.
Thus, the packaging substrate facilitates formation of an electrical link between the semiconductor chip and a system board of a computer. A semiconductor chip is mounted on a die foot print area located on a top surface of the packaging substrate. The die foot print area contains C4 pads on which a semiconductor chip may be attached by C4 bonding. A typical semiconductor chip employing a packaging substrate may comprise about 10,000˜100,000 input/output nodes. Each of these nodes are electrically connected to a C4 pad on a top surface of the semiconductor chip in a two dimensional array.
During C4 bonding of a semiconductor chip and a packaging substrate, the semiconductor chip with bonded solder balls is brought into contact with the bonding pads of the packaging substrate at an elevated temperature in an oven. Another common tool used is a flip chip bonder. Thus, the temperature of the packaging substrate may be elevated close to the reflow temperature of the solder balls. The elevated temperature during the bonding process subjects the semiconductor chip and the packaging substrate to thermal warp, i.e., the warp caused by thermal expansion of materials with temperature.
The thermal warp of the packaging substrate and the semiconductor chip causes alignment problems and stress-induced reliability problems for C4 bonding. Particularly, the thermal warp of the packaging substrate poses a challenge because the thermal expansion coefficient of a packaging substrate tends to be greater than the thermal expansion coefficient of a semiconductor substrate. Large thermal warp causes the packaging substrate to change shape during the heat up period prior to bonding, and leads to potential non-wets or unequal C4 solder heights. Further, large thermal warp during the cool down period after the reflow of solder balls can lead to defects in the solder ball joints such as hot tears.