On an integrated circuit memory device, the memory cells occupy the majority of the space (area), and the number of memory cells determines the memory capacity of the devices. The integration density of a memory device is thus determined in large part by the size of each memory cell. In a dynamic random access memory (DRAM), column and row decoders are provided to select specific memory cells in response to address signals. Accordingly, in dynamic random access memories having memory capacities of 64 MB to 256 MB or greater, the transistors making up the column and row decoders also become a factor making further integration difficult.
A single column decoder is required for a pair of two bit lines for a parallel test when a multi-bit test function is provided in a dynamic random access memory. Accordingly, the layout for a column decoder driver can be designed relatively easily. Two row decoders, however, may be required for every word line connected to respective memory cells. In addition, word line drive circuits drive word lines connected to memory cells in response to the outputs of row decoders. The layout of these word line drive circuits may thus act as a factor making higher degrees of integration more difficult to obtain.
Furthermore, the access time of a dynamic random access memory is determined in part by the time required to charge the word lines after the voltage on the corresponding decoder output line begins to rise. By reducing the time required to charge the word lines, the access time for the memory device can thus be reduced. To increase the integration of the memory device, however, it may be necessary to reduce the pitch of the word lines. As the integration density of a memory device is increased, however, the number of memory cells connected to each word line is increased and the word line drive circuit may be required to have a larger current driving capacity. More particularly, the transistors making up the word line drive circuit may be required to have a larger driving capacity thus increasing the area occupied by each of these transistors. Accordingly, increased integration may require that the area occupied by the drive circuits be reduced in a vertical dimension in a direction orthogonal to the word lines while providing a larger driving capacity for these drive circuits. Both of these requirements, however, may be difficult to achieve at once because larger areas are typically required for drive circuits having larger driving capacities.
To address these issues, a dynamic random access memory is discussed in U.S. Pat. No. 5,416,748 entitled "Semiconductor Memory Device Having Dual Word Line Structure" to Mamoru Fujita. An example of a DRAM having dual word line structure is illustrated in FIG. 1. As shown, the DRAM has a plurality of memory array blocks 100-1, 100-2, . . . , 100-n. Since each of the memory array blocks has the same construction as one another, only the memory array block 100-1 is shown in the drawing and will be explained in detail below.
The memory array block 100-1 includes a plurality of main word lines MWL-1 to MWL-n arranged in a plurality of rows and which are in turn connected to a row decoder 110. This decoder 110 responds to row address ADI and selects and drives one of the main word lines MWL to an active high level. Provided between the adjacent two main word lines MWL1 and MWL2 are subword line drivers (SWD) 130. Each of the subword line drivers 130 has an input node connected to an associated one of the main word lines MWL, an output node connected to an associated subword line SWL and a control node.
The memory array block 100-1 further includes a plurality of word decoder drivers (WDD) 150-1, 150-2, and 150-3 provided correspondingly to each column of the subword line driver array. Each of the word decoder drivers (WDD) has a first power output node connected in common to the power nodes of the odd-numbered ones of the subword line drivers arranged in the same associated column, a second control output node connected in common to the control nodes of the even-numbered ones thereof. The word decoder driver further has first, second and third address input nodes.
The memory array block 100-1 further includes a word decoder (WD) 140 which responds to another row address ADII and changes its output nodes to the active high level.
In each memory array block, each of first, second and third memory cell arrays 120-1, 120-2 and 120-3 is provided to the right side of each subword line driver group, and each of the word lines MWL1 and MWL2 is split into two subword lines extending through each memory cell arrays 120-1, 120-2 and 120-3. The subword line drivers SWD drive the subword lines SWL0 and SWL1 in the memory cell arrays.
When at least one of the main word lines MWL1-MWLn is activated by a selection signal generated from the row decoder 110, the subword line drivers are enabled by the activated word line MWL as the word line is raised to a fixed voltage potential as a boosting voltage potential. All of the subword line drivers, however, are not selected. In particular, at least one of the subword line drivers which has been enabled may be selected by a logic combination of driving signals .PHI.X1 and .PHI.X2 generated from a corresponding word decoder driver. Accordingly, at least one of the subword lines SWL0 and SWL1 can be raised to the fixed voltage potential as a boosting voltage potential by means of the selected subword line drive circuits.
In the memory device having the above construction, the reduction in the size of the respective subword line drivers may however be limited even though the degree of integration is increased. Furthermore, this configuration may require that the pitch of the subword lines be determined by the size of the corresponding subword line driver. Accordingly, even if the degree of integration is increased using the split word line configuration discussed above, the pitch of the main word lines and the pitch of the subword lines may not be sufficiently reduced. As a result, the conventional split word line drive configuration may be insufficient for integrated circuit memory devices having higher levels of integration.
Accordingly, there continues to exists a need in the art for integrated circuit memory devices including improved word line drive circuits.