A multichannel serial port designed as part of a peripheral design reuse module, supports plural serializers. Each of these serializers is individually programmable as either a transmitter or a receiver. In the receive mode, the serial data comes from an external source into the serializer which is clocked by a slow serial clock. When a block of data, such as 32 bits, is received, the data is transferred into VBUS clock domain. The VBUS clock domain has a clock that is an integral fraction of the central processing unit clock. This data is read by the central processing unit from the VBUS clock domain. A synchronizer is required between the serial clock domain and the VBUS clock domain. To optimize integrated circuit area, typically the data is not synchronized but the control (load enable) is synchronized. This load enable signal is used in the VBUS clock domain to latch the data from the serializer.
Since the receive data continues to come, the data in the serializer must be read before it gets over written by the next incoming serial data bit. This poses a clock ratio limitation of about 3 to 1 for VBUS to serial clock. When the device is run at a slower clock, meaning that the VBUS clock frequency is low, it may be impossible to meet this ratio limitation. Thus there is a need in the art for a serializer capable of operation with a clock ratio of less than 3 to 1.
There are two alternate ways of achieving this in the known art. It is possible to provide a shadow register of 32 bits wide, shadowing the whole serializer register. At the end of receiving a block of 32 bits of data, this shadow register stores the same value as the serial register. Shifting within this shadow register can be disabled so that this retains the data till the register is read into VBUS clock domain. Once read, the serial register can be shadowed into this shadow register. This method requires an additional serial shift register having the data block length, equivalent to an additional serializer register. A second method is to synchronize the 32 bit data rather than the load enable signal. This method requires at least two flip flops for each data bit in the data block. This is equivalent to two additional serializer registers. Thus these prior art solutions require additional circuits as large or larger than the original serializer.