Super-junction metal-oxide-semiconductor field-effect transistor (MOSFET) adopts a new voltage-sustaining structure which is made up of alternately arranged P-type and N-type semiconductor films. The structure allows the P-type and N-type regions to be depleted at a relatively low voltage while the device is in a cut-off state, thereby enabling mutual compensation of electric charges between these two types of regions. As such, heavily doping the P-type and N-type regions can result in a high breakdown voltage of the device. That is, the device is able to achieve a high breakdown voltage while keeping a low on-resistance. This is a breakthrough of the theoretical limit for a traditional power MOSFET. FIG. 1 shows an existing super-junction device, which is a P-type super-junction MOSFET.
The device includes a P+ silicon substrate 101 and a P-type epitaxial layer over the P+ silicon substrate.
Alternatively arranged N-type and P-type films 102, 103 are formed in a unit region of the P-type epitaxial layer. The unit region is a current-flowing region located in a center portion of the super-junction device.
An N-type well region 104 is formed on top of each of the N-type films 102 in the unit region and has a width greater than or equal to a width of the N-type film 102.
A pair of source regions 105, each formed of a P+ doped region, is formed in each N-type well region 104.
A gate polysilicon layer 106 is formed above and covers each P-type film 103 and laterally extends over portions of adjacent N-type well regions 104. Each side of the gate polysilicon layer 106 is self-aligned with a corresponding source region 105. A channel is formed in each portion of the N-type well region 104 covered by a corresponding gate polysilicon layer 106 for enabling source-drain interconnection.
Each source region 105 and nearby N-type well regions 104 are both connected to a metal pattern 107 through the same contact hole. The metal pattern 107 is formed on a front side of the P+ silicon substrate 101 to pick up a source and a gate. Moreover, a metal layer is formed on a backside of the substrate to pick up a drain.
Currently, fabrication methods of such super-junction device can be classified into two categories. The first is to form alternating P-type and N-type doped regions, i.e., the P-type and N-type films, by repeating the processes of photolithography-epitaxial growth and ion implantation. The second is to form the P-type and N-type films by forming trenches in a P-type silicon epitaxial layer and then filling the trenches with N-type polysilicon or by tilted N-type impurity implantation, or filling the trenches with N-type epitaxial silicon.
However, these methods all suffer from various deficiencies. Specifically, methods of the first category are complicated in the above-mentioned processes, difficult to be implemented, and lead to a high cost. Moreover, due to poor stability and repeatability of the tilted implantations, methods of the second category adopting the tilted implantation approach are not suitable for mass production applications, and manufacturers are focusing more on those employing the N-type polysilicon or epitaxial silicon filling approaches. In the existing applications, the epitaxial silicon filling approach is most frequently adopted and typically followed by a chemical-mechanical planarization (CMP) process. However, for trenches with a depth of 40 μm to 50 μm or deeper, this method takes a long time, has a relatively high cost and is hard to achieve non-gap filling. In addition, it is also difficult for this method to control defects in growing epitaxial silicon in the trenches. Although there have been some reports on succeeding in forming the P-type and N-type films using the N-type polysilicon filling approach, limited by the existing mature furnace process which produces polysilicon typically with a doping concentration of 1e18 cm−3 to 1e20 cm−3, higher than a desired N-type film doping concentration for the super-junction device which is of 1e15 cm−3 to 1e17 cm−3, this method has poor repeatability and low productivity (satisfying repeatability is obtainable only at certain positions in the furnace) when the existing production equipment is used.
Furthermore, structurally similar to the existing double-diffused metal-oxide semiconductor (DMOS) transistors, a super-junction device also includes many repeated unit structures. As the unit structures typically have a good uniformity, high voltage-caused breakdown will not occur between them. However, a voltage drop exists between each of the outermost unit structures and the substrate, any may easily lead to a breakdown. Therefore, terminal protection is very important to the super-junction device, and the existing super-junction devices generally include a termination structure surrounding the unit region, which employs a diffused guard ring, a field plate, or alternating P and N structures to protect the unit region.