The present invention relates generally to the electronic arts and, more particularly, to field-effect transistors, interconnect structures and their fabrication.
In highly scaled complementary metal oxide semiconductor (CMOS) technology, due to shrinking of the trench CD (critical dimension), the resistance obtained by using conventional material as the gate electrode, contact and/or interconnect material is dramatically increasing, thereby impacting device performance. The skilled artisan will appreciate that trenches are used, for example, in fabrication techniques employing replacement metal gate technologies and the like. During the replacement gate process, disposable gate structures are removed by at least one etch that is selective to the gate spacers and to the dielectric materials of a planarization dielectric layer. Cavities are formed from the spaces remaining after the disposable gate structures are removed. The semiconductor surfaces above the channel regions of the substrate can be physically exposed at the bottoms of the gate cavities, though native oxide layers may be present. The gate cavities are laterally enclosed by the gate spacers that were formed on the sidewalls of the disposable structures. Replacement gate structures are ordinarily formed in the gate cavities. Middle-of-line (MOL) processing includes the formation of source-drain contacts.
Silicon-based devices typically include multiple interconnect metallization layers above a device layer that contains field-effect transistors (FETs), memory devices, or other structures. The metallization layers often include high aspect ratio holes or vias that are relatively deep and have narrow diameters. The ratio of the depth to the diameter (aspect ratio) of contact holes is often much greater than one. Tungsten (W) is frequently employed as a fill material for contact holes having narrow (sub-micron) diameters. Tungsten fill material is deposited conformally using, for example, low pressure chemical vapor deposition (LPCVD). As the dimensions of tungsten metal contacts are scaled down for future technology nodes, currently used metallization techniques may not be able to deliver structures that meet the resistance targets required. The need for thick TiN liners to prevent fluorine diffusion and poor metal gap fill due to seams or other void types contribute to the high resistance of scaled-down tungsten contacts. Such liners reduce contact hole diameter and thereby displace metal conductor volume that could otherwise be deposited within the contact hole.
Currently employed conformal deposition processes for damascene tungsten involve the use of tungsten hexafluoride (WF6) as a source material for the tungsten. The TiN liner protects the underlying titanium and silicon from the fluorine that is released during deposition. The process of filling high aspect ratio contact holes using conformal deposition processes often results in the formation of vertical seams within the metal contacts. Such seams are formed near the convergence of the tungsten-coated side walls of the contact holes. The seams also displace metal conductor volume and could lead to higher resistance.
Historical use of refractory metals and seams in Tungsten (W) metallization has prevented selective wet removal in wide lines. However, the advent of Cobalt (Co) in the middle-of-the-line (MOL) allows selective wet removal in wider lines.
New materials are being employed to use as the interconnects for highly scaled trenches (i.e. lowest CD trench). For example, Co and Ruthenium (Ru) are used as MOL interconnects in lieu of W. Another example is that Titanium nitride (TiN) fill only is used as a gate electrode in place of W or Aluminum (Al). (Note that TiN is usually employed as a liner for a subsequently deposited gate metal). It is pertinent to note that, at the atomic/molecular scale, resistivity is no longer a purely intrinsic property and varies based on the film thickness.