In the very first computer systems, no interruption of the program running at a given time was possible. In order to enable external units to intervene with the central processing unit, the central processing unit had to poll all of the systems at particular time intervals as to whether or not a service request to the processing unit was present. During these polling periods, the central processing unit could perform no other tasks.
The next computer generation was constructed in such a way that the central processing unit could be interrupted through an interrupt line whenever a service request from a peripheral source was present. In response, the central processing unit had to poll all of the sources, in order to find the source making the interrupt request.
Later computer systems had a plurality of interrupt request lines, or had central interrupt components. These so-called central interrupt controllers generated a vector by means of which the interrupting source could be identified. Some systems already had interrupt masks, which made it possible to prefer sources of higher priority over those of lower priority.
Modern microcontrollers are now equipped with a greater number of function units jointly integrated on the chip, such as counter/timers, analog/digital converters, serial interfaces, and capture and compare units. All of these units execute certain functions assigned to them parallel to the central processing unit, until some service by the CPU is required. Upon such interruptions, the central processing unit stores the status of the program that has just run and branches to a subroutine, in order to service the applicable source.
In modern microcontroller systems, the number of events or tasks that are to be performed quasi in parallel has risen drastically in the meantime. The necessity for simultaneous processing of more and more interrupt requests leads to extremely complex, expensive systems for processing interrupt requests in microcontrollers. Another factor is that one and the same microcontroller component must be constructed for a great number of different applications. Each application requires a special spectrum of tasks to be performed quasi in parallel. These needs for flexibility mean, for instance, that the sequence in which interrupt requests that are simultaneously present are processed must be variable; that is, it must be possible to prioritize the interrupt requests.
Many microcontroller manufacturers presently offer so-called microcontroller families, in which although the central processing unit is identical, the number and type of jointly integrated peripheral units are variable from one component to another. A circuit configuration for priority selection is now expected to meet all of the characteristics of the individual components within the family in the most homogeneous manner possible.
Most systems now include central decision components, which process interrupt requests with one or more request and feedback lines.
If interrupt sources are few in number, then in general a single-wire system is preferred, in which the interrupt source activates a request line, whereupon the central processing unit interrupts the program running at that time and searches for the source of the interruption. In this search operation, the priority of each individual source can also be simultaneously determined, and the source having the highest priority can be selected. If more than one source has the same priority, then the search operation can determine which source is preferred. Generally, the central processing unit will accept only requests having higher priority than the priority of the task that is being performed.
A technique less often used provides a separate interrupt line connected to the central processing unit, for each interrupt source. Each line can be separately released or blocked, prioritized and evaluated. In order to reduce the hardware expense required, an attempt is made to group the interrupt requests into groups of equal priority The advantage of this prioritizing method is that the parallel selection method makes nigh response speeds attainable. However, with a plurality of interrupt sources, the flexibility is greatly restricted.
In addition to the circuits having a central interrupt unit, other interrupt systems, known as distributed interrupt systems, are known, in which each interrupt source has its own hardware circuit, with which it is possible to compare its own priority with that of the other sources. When the source having the highest priority at that instant is found, the central processing unit can be made to interrupt the program being run, through a feedback line.
The advantage of this variant circuit is that an arbitrarily great number of additional interrupt sources can be implemented, without impairing the complete flexibility of the system. A condition for this decentralized interrupt system is that the circuit expenditure in and between the interrupt sources be kept as low as possible. In a known system of this type, all of the sources are connected to one another by a common line. Through a special polling and feedback scheme, each source tests whether or not it has the highest priority by using priority bits that are present over the common line.
The polling process begins in each case with the highest priority bit and jumps in stages to the lower-value priority bit. Each source that has a lower priority with respect to another source must release the common line. At the end of the polling mode, only the source having the highest priority at that instant remains connected with the common line. Although this polling circuit is distinguished by a simple structure of the connecting line, its use in microcontroller systems that have to perform real-time tasks is unsatisfactory, because the system-dictated serial polling mode necessitates an overly long response time.
It is accordingly an object of the invention to provide a circuit configuration and method for priority selection, which overcome the hereinafore-mentioned disadvantages of the heretofore-known methods and devices of this general type and which are distinguished by a simple construction and a short response time.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration for priority selection in an integrated circuit, comprising a central processing unit, a central interrupt node connected to the central processing unit, N interrupt sources for presenting interrupt requests to the central processing unit, peripheral interrupt nodes each being connected to a respective one of the N interrupt sources, and a common interrupt bus connected to the peripheral interrupt nodes and to the central interrupt node.