(A) Field of the Invention
The present invention is related to an operation method for non-volatile memory, and more particularly to an operation method for non-volatile memory capable of storing two bits.
(B) Description of the Related Art
Non-volatile memory devices are currently in wide use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM) and electrically erasable programmable read only memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, Flash EEPROM devices enable the erasing of all memory cells in the device using a single electrical current pulse.
Typically, an EEPROM device includes a floating-gate electrode upon which electrical charge is stored. In a flash EEPROM device, electrons are transferred to a floating-gate electrode through a dielectric layer overlying the channel region of the transistor. The electron transfer is initiated by either hot electron injection or Fowler-Nordheim (F-N) tunneling. One important dielectric material for the fabrication of the floating-gate electrode is an oxide-nitride-oxide (ONO) structure. During programming, electrical charges are transferred from the substrate to the silicon nitride layer in the ONO structure and trapped therein. Moreover, non-volatile memory designers have taken advantage of the localized nature of electron storage within a silicon nitride layer and have designed memory circuits that utilize two regions of stored charge within an ONO layer. This type of non-volatile memory device is known as a two-bit EEPROM. The two-bit EEPROM is capable of storing twice as much information as a conventional EEPROM in a memory array of equal size. A left bit and right bit are stored in physically different areas of the silicon nitride layer, near left and right regions of each memory cell.
Referring to FIG. 1, U.S. Pat. No. 6,011,725 introduces an operation method to an EEPROM device 10, or namely SONOS (silicon-oxide-nitride-oxide-silicon) device, having a non-conducting charge trapping dielectric, such as a silicon nitride layer 20, sandwiched between two silicon oxide layers 18 and 22 acting as electrical insulators. In view of localized trapping electron charge capability of the silicon nitride layer 20, the EEPROM device 10 is capable of storing two bits of information, i.e., there are two bits per cell. A left bit and a right bit are stored in physically different areas of the silicon nitride layer 20, near left and right regions of the memory cell 10, respectively. For programming, voltages are applied to a gate 24 and a drain 16 to create vertical and lateral electrical fields, which accelerate electrons from a source 14 along the length of the channel. As the electrons move along the channel, some of them gain sufficient energy to jump over the potential barrier of the bottom silicon oxide layer 18 and become trapped in the silicon nitride layer 20. For the right bit, for example, the electrons are trapped near the drain 16 indicated by the dashed circle 23. For the left bit, on the contrary, electrons are trapped in the nitride layer 20 near the source 14 as dashed cycle 21. For reading, a way to read in reverse direction, i.e., in a direction opposite to that of programming, is conducted. For instance, to read the right bit of the device 10, voltages are applied to the source 14 and the gate 24, whereas the drain 16 is grounded, in which the voltage applied to the source 14 has to be high enough to ignore the affection by the left bit charge. If there is charge in right bit, no current occurs. In contrast, current is generated if there is no charge in right bit. As to the reading of the left bit, voltages are applied to the drain 16 and the gate 24, whereas the source 14 is grounded.
Accordingly, the above-mentioned technique limits that the reading has to be conducted in a reverse direction, which may enhance the complex of operation.