1. Field of the Invention
The present invention relates to the field of integrated circuits. More specifically, the present invention relates to an integrated circuit comprising a plurality of active layers electrically and mechanically coupled together and a method for providing this integrated circuit.
2. Background of Art Related to the Invention
A majority of semiconductor manufacturers are constructing integrated circuits according to a conventional structure in which the integrated circuit comprises a layer of inactive semiconductive material and a layer of active semiconductive material deposited thereon. Transistors and other electrical components such as resistors and capacitors, are fabricated either within or on an active layer (defined below). The various components of the active semiconductive material are coupled together by a plurality of interconnect lines. The electrical components in the active semiconductive material and interconnect lines are collectively referred to as the "active layer". The active semiconductive material is typically made of doped silicon being 1-5 microns (".mu.m") in thickness. The inactive semiconductive material (commonly referred to as the "substrate layer"), has a thickness substantially larger than the active layer, typically being 625 .mu.m. The substrate layer merely provides sufficient thickness for handling of the integrated circuit during manufacture. As a result, normally less than one-percent (1%) of the volume of the conventional integrated circuit is needed.
Besides defining the operation of the integrated circuit, these plurality of interconnect lines further enable the integrated circuit to operate in association with other integrated circuits to store, process and/or transfer information as a device, subsystem (a combination of devices operating in tandem) and the like. The operational speed of the device is limited by the length and capacitive loading of these interconnect lines. For example, the length and capacitive loading of the interconnect lines coupling together a number of random access memory ("RAM") devices adversely effects the operational speed in storing and retrieving information from any of the RAM devices.
Besides limiting operational speed, the length of the interconnect lines effect the amount of power consumed by the device or subsystem because the capacitance of the interconnect lines generally increases as their length increases. A semiconductor device constructed of CMOS devices consumes power and dissipates heat according to the following equation: EQU Power=1/2 CV.sup.2 F,
where
"C"=total capacitance; PA1 "V"=total power supplied to the device; and PA1 "F"=bus clock frequency.
On a larger scale, the amount of power consumption and thermal dissipation by a subsystem of CMOS based semiconductor devices is approximated using the above equation for each chip and further including capacitance from the chip package and the interconnect between chips. The capacitance of the interconnect lines consumes about one-third to one-half of the power of conventional subsystems, thereby augmenting thermal power dissipation requirements.
In view of the demand for smaller and more powerful computing resources that normally consume less power and dissipate less heat in a smaller area, many semiconductor manufacturers are attempting to provide semiconductor devices having greater active layer densities (hereinafter referred to as "ultra-thin semiconductor devices"). By increasing the density of the active layers and thereby reducing the length and capacitance of the interconnect lines, power consumption and thermal dissipation is reduced. For example, at least one semiconductor manufacturer has recently begun removing the substrate layer of the integrated circuits and vertically disposing a first active layer onto a second active layer, as evidenced by an article entitled Future WSI Technology: Stacked Monolithic WSI. The article discusses a three-dimensional ("3D") wafer scale integration process developed by Hughes Aircraft Laboratories ("Hughes") of Carlsbad, Calif. which has many disadvantages associated therewith.
A primary disadvantage is that the 3D-wafer scale integration process employs an indium bump interconnect technique which is not widely used by most semiconductor manufacturers. As a result, in order to produce ultra-thin semiconductor devices according to that technique, a semiconductor manufacturer would have to modify its fabrication process flow and equipment, which could be an enormous initial capital investment. In addition, the indium bump interconnect technique provides poor thermal dissipation since heat is removed from the active layers through the indium bumps, which occupy negligible surface area. Such thermal dissipation is crucial in maintaining reliable operations of any semiconductor device.
Other disadvantages associated with the 3D-wafer scale integration process is that it employs a complex computer-controlled etching process for slowly removing a desired amount of substrate in order to achieve its "thin" construction. This etching process is extremely time consuming, affecting overall production output of these semiconductor device. A further disadvantage is that the conventional 3D-wafer scale integration process is generally directed toward interconnecting two integrated circuit surfaces and is extremely difficult to successful coupling more than two integrated circuits together.
Another method for bonding two or more entire integrated circuit chips together has been developed in which Silicon Nitride is used for insulating regions of a bond and Titanium Nitride is used for the electrically conducting regions of the bond. In this process, a layer of an appropriate nitride is applied to a top and bottom surfaces of the integrated circuits. The nitrides are activated (i.e., to have an adhesive nature) to couple only two integrated circuits together through NH.sub.3 plasma or a dilute hydrofluoric acid dip. Unlike the present invention, these integrated circuits are aligned through an exotic process involving etching deep trenches into a backside portion of the integrated circuit and employing an infrared microscope to check for alignment as disclosed in an article entitled Low Temperature Si.sub.3 N.sub.4 Direct Bonding, authored by Bower and Ismail.