1. Field of the Invention
The present invention relates to a semiconductor memory device. More particularly, it relates to a semiconductor memory device preferable for a SRAM (Static Random Access Memory) which has secured the operational margin during write operation, and operates at a low voltage and a low electric power.
2. Description of the Related Art
In recent years, there has been an increasingly growing trend towards portable devices, which increases a demand for lower power consumption of a large-scale semiconductor integrated circuit (LSI). Therefore, a technology of an LSI operating at a voltage of not more than 1 V becomes necessary. In the future, presumably, there will be growing demands for a further decrease in supply voltage from that of an LSI operating at a supply voltage of about 0.9 V, so that an LSI operating even at a supply voltage of about 0.5 V will be demanded.
For operating the LSI at a low voltage, the decrease in threshold voltage of a MOS transistor is achieved so that the supply current can be obtained even at a low voltage. However, when the threshold voltage of the MOS transistor in the memory cell of a SRAM has been reduced, the static noise margin, which is the margin with respect to a noise, is reduced, resulting in an unstable read operation. This is shown in FIGS. 24A and 24B. The double-headed arrow line indicated by a reference numeral 11 in FIG. 24A denotes the static noise margin of a prior-art memory cell of which the threshold value is not reduced. In contrast, as shown in FIG. 24B, the static noise margin 12 of the memory cell whose threshold value has been reduced is narrowed.
FIG. 2 is a diagram showing a circuit configuration of a memory cell of a SRAM. The memory cell of the SRAM is made up of N-channel MOS transistors (driver MOS transistors) N1 and N2 whose sources are coupled to each other, P-channel MOS transistors (load MOS transistors) P1 and P2 whose drains are coupled to the drains of the driver MOS transistors N1 and N2, respectively, and N-channel MOS transistors (transfer MOS transistors) N3 and N4 whose gates are respectively coupled to a word line WL, and whose source-drain paths are coupled between bit lines BL and /BL (where the sign xe2x80x9c/xe2x80x9d is used in place of the bar sign denoting the inversion) and the drains of the driver MOS transistors N1 and N2, respectively.
Incidentally, in FIG. 2, a reference numeral 4 denotes a source line of the load MOS transistors P1 and P2, i.e., a power supply line for the memory cell; 5, a source line of the driver MOS transistor N1 and N2, i.e., normally a ground line for the memory cell; 6 and 7, data holding nodes (storage nodes) of the memory cell; a reference character Vw, the voltage of the word line WL; Vb1 and Vb2, the voltages of the bit lines BL and /BL, respectively; Vddm, the voltage of the power supply line 4 for the memory cell; and Vssm, the voltage of the ground line 5 for the memory cell. Further, Vn1 and Vn2 denote the voltages of the data holding nodes 6 and 7, respectively, which individually correspond to xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d as data so as to be in the mutually inverse relationship.
Then, a description will be given to a conventionally adopted method for preventing the static noise margin of the SRAM memory cell having such a configuration from being reduced even when the threshold value of each MOS transistor has been reduced.
For preventing the static noise margin of the SRAM memory cell from being reduced even when the threshold voltage of the MOS transistor has been reduced, the conductance of the driver MOS transistors N1 and N2 are required to be made larger as compared with the conductance of the transfer MOS transistors N3 and N4. For attaining this, it is only required as follows: a voltage Vddxe2x80x2 higher than a high-level voltage Vdd of the word line WL is applied as the voltage Vddm of the power supply line 4 for the memory cell to be coupled to the sources of the load MOS transistors P1 and P2, and the voltage to be applied to the gate electrodes of the driver MOS transistors N1 and N2 are set to be higher than the voltages to be applied to the gate electrodes of the transfer MOS transistors N3 and N4. As a result, the conductance of the driver MOS transistors N1 and N2 is increased, and the static noise margin is also increased as shown by a double-headed arrow denoted by a reference numeral 13 in FIG. 24C.
Therefore, with a prior-art SRAM memory intended for low-voltage operation, as disclosed in Japanese Published Unexamined Patent Application No. Hei 9-185886, there are adopted a method in which, only during read operation, the voltage of the power supply lines for the whole memory cell array is increased, or a high voltage is applied to the power supply line for the memory cell to be read, i.e., the memory cell selected during read operation, and other methods.
The reason why the voltage Vddm of the power supply line for the memory cell is boosted only during read operation is because the operational margin during write operation decreases with an increase in ratio between the conductance of the load MOS transistors P1 and P2 and the conductance of the driver MOS transistors. For this reason, with a prior-art method, the voltage Vddm of the power supply line 4 for the selected memory cell or memory cell array is boosted only during read operation to suppress the reduction in the operational margin during write operation.
Incidentally, in Japanese Published Unexamined Patent Application No. Hei 9-185886, it is described as follows: it is also possible to constantly set the power supply potential for the memory cell to be applied to the memory cell higher than the power supply potential for the peripheral circuits only during read operation.
Further, for conventional SRAM memory cells not intended for only low-voltage operation, the conductance of the driver MOS transistors is required to be set larger than the conductance of the transfer MOS transistors as described above in order to ensure a larger static noise margin during read operation. For this reason, the gate width of driver MOS transistor have been manufactured larger than the gate width of the transfer MOS transistor. Particularly, as disclosed in Japanese Published Unexamined Patent Application No. Hei 2001-28401, in the layout of the memory cell used in a prior-art SRAM memory shown in FIG. 9, in spite of the fact that the diffusion regions of the driver MOS transistors and the transfer MOS transistors are formed without curves, the diffusion regions are not arranged in the form of a simple rectangle due to the difference in size of the gate width. Incidentally, in FIG. 9, a reference numeral 33 denotes a contact; 34, N-type diffusion layers serving as the sources and the drains of N-channel MOS transistors (below, referred to as NMOS transistors) N1, N2, N3, and N4; 35, a polysilicon serving as agate electrode; 36, one SRAM memory cell region; and 39, P-type diffusion layers serving as the sources and the drains of P-channel MOS transistors (below, referred to as PMOS transistors) P1, P2, P3, and P4.
Further, the same prior-art example of Japanese Published Unexamined Patent Application No. Hei 2000-28401 describes as follows. In order for the ratio of the gate width between the driver MOS transistor and the transfer MOS transistor to be 1, the manufacturing process is changed in the following manner. For example, each gate oxide film thickness of the transfer MOS transistors N3 and N4 is increased as compared with that of the driver MOS transistors N1 and N2, alternatively, the impurity concentration of a low-concentration drain region for electric field relaxation is reduced, thereby to cause a difference in driveability, resulting in an increase in so-called cell ratio.
However, with the prior-art method in which a high voltage is applied to the power supply line for the memory cell array only during read operation described above, it takes much time for the power supply voltage Vddm for the memory cell array to change into a desired voltage Vddxe2x80x2 higher than the power supply voltage Vdd for the peripheral circuits. Further, an extra electric power required for charge and discharge of the power supply line is consumed for increasing and decreasing the voltage of the power supply line for the memory cell array. Accordingly, although this circuit is a SRAM circuit operating at a low voltage, it becomes incapable of implementing the lower power consumption. This is due to the following fact. Even when only the power supply voltage Vddm for the selected memory cell for executing the read operation is boosted, the power consumption is increased to one degree or another. Whereas, when the power supply voltage for the memory cell is constantly set higher than the power supply voltages for the peripheral circuits and the like, it is necessary that the ground voltage for the memory cell is set higher than the ground voltage of the peripheral circuits during write operation and during standby, and that the ground voltage for the memory cell is set at the same level as the ground voltage for the peripheral circuits only during read operation. This eventually requires the relative increase and decrease in voltage between power supply lines, so that the extra electric power required for charge and discharge of the power supply lines is consumed.
Further, by forming the diffusion regions 34 and 39 as shown in FIG. 9, and the polycrystal silicon (polysilicon) layer 35 in a line form to generate a high-symmetry layout, it has become possible to suppress the variations in manufacturing as compared with the layout previous to that, wherein less symmetry is present, and the polysilicon is curved. However, with this layout, each gate width W1 of the driver MOS transistors N1 and N2 is different from each gate width W3 of the transfer MOS transistors N3 and N4 for controlling the conductance. As a result, the diffusion regions 34 and 37 are formed in a shape falling short of a perfect rectangle as shown in FIG. 9. Actually, by setting the ratio W1/W3 of the gate width W1 of the driver MOS to the gate width W3 of the transfer MOS to be 1.5 to 2, the ratio of the conductance between the driver MOS transistor and the transfer MOS transistor is controlled to secure the static noise margin. Therefore, as compared with the SRAM memory cell which has not yet adopted this layout, the variations in manufacturing are reduced. However, as compared with the case where the diffusion regions are formed in perfect rectangle, the variations can be considered to be larger.
Further, as described in the same prior-art example of Japanese Published Unexamined Patent Application No. Hei 2000-28401, with the method in which the gate width ratio W1/W3 of 1 is achieved by the change in manufacturing process, for example by changing the impurity concentration of the driving force, and thereby increasing the cell ratio, unfavorably, the manufacturing conditions become complicated, resulting in a reduction of yield, and the number of manufacturing steps is increased, incurring a rise in cost.
An object of the present invention is to provide a semiconductor memory device preferable for a SRAM memory which has secured a static noise margin, and is capable of achieving both the low voltage operation and the low power consumption.
Further, it is another object of the present invention to provide a semiconductor memory device wherein while securing the static noise margin, the gate width ratio between a driver MOS transistor and a transfer MOS transistor is set to be 1 to enable the rectangle layout of diffusion regions, resulting in small manufacturing variations.
In order to solve the foregoing problems, a semiconductor memory device in accordance with the present invention, comprises: a semiconductor substrate, and static type memory cells each comprising N-channel type two driver MOB transistors and two transfer MOB transistors, and P-channel type two load MOB transistors, the static type memory cells being placed in an array on the semiconductor substrate, source electrodes of the driver MOS transistors being coupled to a first operating potential node, and source electrodes of the load MOB transistors being coupled to a second operating potential node, and characterized in that, if it is assumed that the potential difference between the first operating potential node and the second operating potential node is a first potential difference, and that the potential difference between a high-level potential to be applied to gate electrodes of the transfer MOB transistors and the potential of the second operating node is a second potential difference, the first potential difference is set to be larger than the second potential difference in the state in which the memory cells are being operated.
Namely, the device is so configured that a voltage higher than the High voltage Vdd of the word line is constantly applied to the power supply line for the memory cell array during the period in which the SRAM is operating including not only the time of read operation but also the time of write operation. As described in the description on the prior art, the increase in potential of the power supply line for the memory cells during write operation decreases the operational margin during write operation. Therefore, it has been conventionally considered better that such an increase in potential is not done.
However, an attention has been given to the following fact. By boosting the voltage Vddm of the power supply line for the memory cell array, the voltage applied between the gate and the source of the driver MOS transistor becomes higher than the voltage applied between the gate and the source of the transfer MOS transistor. As a result, the conductance of the driver MOS transistor becomes larger than the conductance of the transfer MOS transistor. By positively using this fact, it becomes possible to set the gate width ratio W1/W3 of the gate width W1 of the driver MOS transistor to the gate width W3 of the transfer MOS transistor to be smaller as compared with the memory cell in the prior-art memory cell array whose power supply voltage Vddm will not be boosted.
There is a problem that the noise margin during write operation is reduced when the power supply voltage Vddm for the memory cell array is boosted regardless of the write or read operation. As described below, the boost in voltage Vddm allows the layout resulting in a narrow range of variations in circuit manufacturing. Namely, it becomes possible to set the gate width ratio W1/W3 of the driver MOS transistor to the transfer MOS transistor to be 1 while securing the static noise margin. As a result, it is possible to form the diffusion regions in a perfect rectangle when the memory cells are laid out as shown in FIG. 10 without changing the manufacturing process. Accordingly, it also becomes possible to suppress the variations in manufacturing.
Thus, it is possible to suppress the variations in manufacturing. In consequence, it becomes possible to control the operational margin which has been required during operation to a lower level. Therefore, it is possible to solve the problem that the operational margin during write operation is decreased when the power supply voltage Vddm for the memory cell array has been boosted.
Further, although the variations in manufacturing have been reduced, and the required operational margin has been reduced, there is also a possibility that the operational margin during write operation enough for the circuit operation cannot be actually obtained. Therefore, the threshold voltage of the PMOS transistor is set higher than the threshold voltage of the NMOS transistor. As a result, the ratio between the conductance of the load MOS transistor and the conductance of the transfer MOS transistor in the memory cell is reduced, so that it is possible to increase the operational margin during write operation.
The foregoing and other objects of the invention will become more apparent by referring to the following detailed description and appended claims when considered in connection with the accompanying drawings. It is noted that the same reference characters and numerals designate the same or like parts in the accompanying drawings.