Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor integrated circuit.
As semiconductor devices are developed to increase operation speed and reduce power consumption using ultra-fine process technology, operating voltages are also further lowered. Most semiconductor devices include an internal voltage generator configured to generate an internal voltage by using an external power supply voltage, so that internal circuits of the semiconductor devices are supplied with proper voltages. In designing such an internal voltage generator, a main issue is to constantly maintain an internal voltage at a desired level.
One representative internal voltage is a core voltage (VCORE), which is used in a core region where memory cells are provided. In the following description, a core voltage generator, which generates a core voltage (VCORE), and a write driver, which uses the core voltage as a source voltage, are considered.
FIG. 1 is a block diagram illustrating a partial configuration of a semiconductor integrated circuit.
Referring to FIG. 1, a plurality of bank groups each including banks BK0 to BK15 are provided. The concept of the bank group is introduced in order to efficiently control tens of millions of memory cells provided within the semiconductor memory device and improve operational performance. The banks BK0 to BK15 are provided with a set of memory cells. The bank groups include a plurality of write drivers 200 which write data to the memory cells.
In addition, a plurality of core voltage generators 100 are provided to supply a core voltage (VCORE) to the write drivers 200 provided in the plurality of bank groups. The core voltage generators 100 supply the core voltage (VCORE) to the banks BK0 to BK15 or the like. However, in the following description, it is assumed that the core voltage generators 100 supply the core voltage (VCORE) to only the write driver 200 in order to describe the invention without departing from the principal point of the invention.
A plurality of first ground voltage pads PAD1 to PAD4 are provided to supply a first ground voltage VSS to the core voltage generators 100, and a second ground voltage pad PAD5 is provided to supply a second ground voltage VSSV to only a specific internal circuit. The first ground voltage VSS refers to a general ground voltage supplied to the overall internal circuits of the semiconductor integrated circuit, and the second ground voltage VSSV refers to a ground voltage separated from the first ground voltage VSS and is called “Quiet VSS”. Specifically, the second ground voltage VSSV is a stable ground voltage supplied only to a specific internal circuit, such as a reference voltage generator. Therefore, during the operation of the semiconductor integrated circuit, such as an active operation, a write operation, and a read operation, noise components appear in the first ground voltage VSS, but noise components do not appear in the second ground voltage VSSV. Hereinafter, the first ground voltage VSS will be referred to as a general-purpose ground voltage, and the second ground voltage VSSV will be referred to as a reference-voltage-purpose ground voltage.
FIG. 2 is a block diagram illustrating the configuration of the core voltage generator 100 and the write driver 200 of FIG. 1.
Referring to FIG. 2, the core voltage generator 100 is configured to receive a reference voltage VREFC and generate and maintain a constant core voltage VCORE. The write drivers 200 are configured to use the core voltage VCORE generated by the core voltage generator 100 as a source voltage in response to a write enable signal BWEN.
FIG. 3 is a circuit diagram illustrating the core voltage generator 100 of FIG. 2.
Referring to FIG. 3, the core voltage generator 100 includes a comparison unit 110, a driving unit 120, and a division unit 130. Specifically, the comparison unit 110 is configured to compare the reference voltage VREFC with a fed-back half core voltage VHALFCORE. The driving unit 120 is configured to drive a core voltage (VCORE) terminal to a power supply voltage VDD in response to an output signal of the comparison unit 110. The division unit 130 is provided between the core voltage (VCORE) terminal and a ground voltage (VSS) pad, and configured to divide the core voltage VCORE at a preset division ratio and feed the division voltage, that is, the half core voltage VHALFCORE, back to the comparison unit 110.
The comparison unit 110 is implemented with a current mirror differential amplifier.
The driving unit 120 includes a PMOS transistor having a source coupled to a power supply voltage (VDD) terminal, a drain coupled to the core voltage (VCORE) terminal, and a gate receiving the output signal of the comparison unit 110.
The division unit 130 includes division diodes D1 and D2 coupled in series between the core voltage (VCORE) terminal and the ground voltage (VSS) pad and configured to output the half core voltage VHALFCORE. The division unit 130 may also be implemented with resistors, instead of the diodes D1 and D2. Since the division elements of the division unit 130 are configured to have the same voltage difference at both terminals thereof, the division unit 130 outputs the half core voltage VHALFCORE corresponding to the middle voltage level between the core voltage VCORE and the ground voltage VSS.
FIG. 4 is a circuit diagram illustrating the write driver 200 of FIG. 2.
Referring to FIG. 4, the write driver 200 includes a latch unit 210 and an output driving unit 220. Specifically, the latch unit 210 is configured to latch data loaded on global input/output lines GIO and GIOB. The output driving unit 220 is configured to output the data latched in the latch unit 210 to local input/output lines LIO and LIOB. When a write enable signal BWENB is activated, the latch unit 210 determines the voltage levels of driving control signals LAT and LATB and DRV and DRVB in response to the data signals loaded on the global input/output lines GIO and GIOB.
The output driving unit 220 pull-up drives the local input/output lines LIO and LIOB to the core voltage VCORE and pull-down drives the local input/output lines LIO and LIOB to the general-purpose ground voltage VSS in response to the driving control signals LAT and LATB and DRV and DRVB. Also, the output driving unit 220 precharges the local input/output lines LIO and LIOB to the half core voltage VBLP in response to a precharge signal LIOPCGB. The write enable signal BWENB and the precharge signal LIOPCGB maintain a substantially similar timing. The precharge signal LIOPCGB is deactivated when the write enable signal BWENB is activated, and the precharge signal LIOPCGB is activated when the write enable signal BWENB is deactivated.
The operation of the semiconductor integrated circuit configured as above is described below.
The core voltage generator 100 down-converts the external power supply voltage VDD and generates the constant core voltage VCORE. The write driver 200 precharges the local input/output lines LIO and LIOB to the half core voltage VBLP. In this manner, when the local input/output lines LIO and LIOB are enabled or precharged, the local input/output lines LIO and LIOB are rapidly driven to the core voltage VCORE or the general-purpose ground voltage VSS. Thus, use of the write driver 200 may be advantageous in terms of current consumption.
In a state where the write enable signal BWENB is activated, the write driver 200 pull-up or pull-down drives the local input/output lines LIO and LIOB in response to first and second data signals applied to the global input/output lines GIO and GIOB. Accordingly, the data is stored in a corresponding memory cell.
Meanwhile, due to the write operation of the write driver 200, the consumption of the core voltage VCORE increases, and thus, the voltage level of the core voltage (VCORE) terminal of the core voltage generator 100 is lowered. Therefore, the core voltage generator 100 performs the following operation in order to constantly maintain the core voltage (VCORE) terminal at the core voltage VCORE. First, the comparison unit 110 detects that the half core voltage VHALFCORE fed back from the division unit 130 is lower than the reference voltage VREFC. The driving unit 120 drives the core voltage (VCORE) terminal to the power supply voltage VDD in response to the output signal of the comparison unit 110. For example, where output of the comparison unit 110 is a logic low level signal, the driving unit 120 may drive the core voltage (VCORE) terminal to the power supply voltage VDD. In this case, the voltage level of the core voltage (VCORE) terminal rises and the half core voltage VHALFCORE outputted from the division unit 130 also rises. On the contrary, when the half core voltage VHALFCORE is equal to the reference voltage VREFC, the driving unit 120 is disabled in response to the output signal of the comparison unit 110. Through these operations, the voltage level of the core voltage (VCORE) terminal is constantly maintained.
However, the core voltage generator 100 of the conventional semiconductor integrated circuit has the following limitations.
The operating current used when the write driver 200 operates and the resistance of the general-purpose ground voltage (VSS) line itself together cause a variation in the voltage level of the general-purpose ground voltage VSS. In other words, the voltage level of the general-purpose ground voltage VSS rises as the operating current of the write driver 200 increases, or the voltage level of the general-purpose ground voltage VSS rises in proportion to the resistance which increases as the distance between the core voltage generator 100 and the general-purpose ground voltage (VSS) pads PAD1 to PAD4 becomes longer. In this case, the voltage level of the core voltage (VCORE) terminal of the core voltage generator 100 is also affected. Specifically, the division unit 130 divides the voltage applied between the core voltage (VCORE) terminal and the general-purpose ground voltage (VSS) pad at a preset division ratio, and outputs the half core voltage VCORE. At this time, when the voltage level of the general-purpose ground voltage VSS rises, the voltage level of the half core voltage VHALFCORE outputted from the division unit 130 also rises accordingly. Thus, the output signal of the comparison unit 110 is affected, which will also affect the operation of the driving unit 120. Consequently, the voltage level of the core voltage (VCORE) terminal is adjusted to a voltage level different from a normal voltage level.
FIG. 5A is an exemplary view illustrating the voltage levels of the core voltage VCORE and the general-purpose ground voltage VSS during the write operation in a low frequency environment, and FIG. 5B is an exemplary view illustrating the voltage levels of the core voltage VCORE and the general-purpose ground voltage VSS during the write operation in a high frequency environment.
As can be seen from FIGS. 5A and 5B, the voltage level of the core voltage VCORE is lowered by as much as the increase in the voltage level of the general-purpose ground voltage VSS. That is, in the low frequency environment, the voltage level of the general-purpose ground voltage VSS rises by 0.03V and thus the voltage level of the core voltage VCORE is targeted to a lower level, for example, 1.27 V. Meanwhile, in the high frequency environment, the voltage level of the general-purpose ground voltage VSS rises by 0.07 V and thus the voltage level of the core voltage VCORE is targeted to a lower level, for example, 1.23 V. In this case, the voltage level of the general-purpose ground voltage VSS further rises in the high frequency environment than in the low frequency environment. Thus, the voltage level of the core voltage VCORE is adjusted to a lower level in the high frequency environment than in the low frequency environment. When the operating speed becomes fast like in the high frequency environment, the operating current increases so that the voltage level of the general-purpose ground voltage VSS further rises.
As the voltage level of the general-purpose ground voltage VSS rises, malfunction may occur during the write operation when the core voltage VCORE is adjusted to lower than the high voltage Vih which is a reference voltage level recognized as a “logic high” level in the semiconductor integrated circuit.