1. Field of the Invention
The present invention generally relates to methods, systems, and carrier media for evaluating reticle layout data. Certain embodiments relate to a computer-implemented method that includes determining manufacturability, inspectability, and/or printability of reticle layout data.
2. Description of the Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
Designing an integrated circuit involves creating a schematic design that includes individual devices arranged and coupled to perform a particular function. As integrated circuits become increasingly complex, the design of the integrated circuits also increases in complexity. For example, integrated circuits are generally designed to have smaller dimensions and greater circuit density to improve the speed and other characteristics of the integrated circuits.
The integrated circuit design may be developed using any method or system known in the art such as electronic design automation (EDA), computer aided design (CAD), and other integrated circuit design software. Such methods and systems may be used to generate the circuit pattern database from the integrated circuit design. The circuit pattern database includes data representing a plurality of layouts for various layers of the integrated circuit. Data in the circuit pattern database may be used to determine layouts for a plurality of reticles. Reticles or “masks” are used in a lithography process to transfer a pattern to a resist on a wafer. The terms “reticle” and “mask” are used interchangeably herein.
A layout of a reticle generally includes a plurality of polygons that define features in a pattern on the reticle. Typically, these polygons can be generally defined by their size and placement of the reticle. Each reticle is used to fabricate one of the various layers of the integrated circuit. The layers of the integrated circuit may include, for example, a junction pattern in a semiconductor substrate, a gate dielectric pattern, a gate electrode pattern, a contact pattern in an interlevel dielectric, and an interconnect pattern on a metallization layer.
In particular, the reticle is used to pattern a resist in a lithography process step, then the patterned resist is used to form features of the integrated circuit on the wafer. Therefore, the patterned features that are formed on a reticle and are to be transferred to the wafer reflect the characteristics of the features that are included in the integrated circuit design. For example, the features that are formed on the reticle may be based on and are used to form individual components of the integrated circuits such as those described above. The complexity of the integrated circuit design, therefore, has a direct impact on the manufacture and inspection of reticles.
Accordingly, as the complexity of the integrated circuit design increases, successful reticle manufacture becomes more difficult. For instance, as the dimensions of the integrated circuit features and the spacings between the features decrease, the dimensions and spacings of features on the reticle also decrease. In this manner, it becomes more difficult to form these features on a reticle due to, for example, limitations of the reticle manufacturing process. In a similar manner, it becomes more difficult to inspect these features due to limitations of the reticle inspection processes. Furthermore, as is known in the art, the difficulty of successfully reproducing these features on wafers increases as the dimensions and spacings decrease.
In addition, as the dimensions of integrated circuit features approach the wavelength of the energy source used to print the reticle pattern on a wafer, reticle enhancement techniques (RET) such as optical proximity correction (OPC) features are increasingly relied upon to increase the accuracy of the transfer of the reticle features to the wafer. In particular, RET features cause the pattern printed on a wafer to differ significantly from the pattern physically formed on a reticle. Examples of reticle enhancing techniques include, but are not limited to, OPC features, phase shifting regions, polarization reticles, multiple exposures, off-axis illumination, illumination shapes, and dipole illumination.
OPC features generally take the form of sub-resolution features that are formed on the reticle but which do not print on the wafer. Instead, the OPC features are designed to increase or decrease the amount of light incident on the wafer proximate certain portions of the features such as corners. The OPC features further complicate the design, manufacture, and inspection of the reticle. However, due to the assistance that these features provide in printing features with acceptable characteristics, almost all reticles today include OPC features or another type of RET features. Furthermore, optical effects such as mask error enhancement factor (MEEF) may cause additional distortion of the final image at the wafer level. MEEF may be generally defined as the ratio of the critical dimension of a feature printed in a resist to the critical dimension of a structure formed on a reticle.
Generally, prior to manufacturing a reticle, the reticle layout data that is generated from an integrated circuit design will be checked. The reticle layout data is generally checked using a design rule checking (DRC) technique and/or an optical rule checking (ORC) technique. A DRC tool checks a mask layout file for design rule violations and identifies any violations in an output file. Design rules can include, for example, minimum line spacings, minimum line widths, minimum gate widths, or other geometric layout parameters. The design rules are based on, for example, the manufacturing process to be used to manufacture the resulting design layout. An ORC tool generally analyzes the edge collection by simulating the performance expected on the wafer and determining whether the wafer structures will violate a set of fabrication tolerances. Therefore, the optical rules are based on the lithography process to be used to manufacture wafers with the reticle.
Many DRC and ORC techniques are known in the art, and the results of DRC and ORC are used to correct design rule or optical rule violations. For example, systems and methods for correcting design rule violations in a mask layout file are illustrated in U.S. Published Patent Application No. 2002/0144230 by Rittman, which is incorporated by reference as if fully set forth herein. One method described by Rittman includes correcting design rule violations in a mask layout file by comparing a feature dimension in a mask layout file with a design rule in a technology file. If the feature dimension is less than the design rule, a design rule violation is identified and automatically corrected in the mask layout file. The design rule violation in the mask layout file may be automatically corrected by adjusting the feature dimension until the feature dimension is approximately equal to or greater than a design rule in the technology file. The method is intended to automate correction of the mask layout file to eliminate new design rule violations that may be created when a layout designer manually corrects the mask layout file.
While this and other methods known in the art for correcting design rule violations in a mask layout file have proven to be somewhat successful, DRC and ORC systems currently in use suffer from several limitations. For example, typical systems generally operate entirely on the data as drawn by the layout and RET decoration programs without accounting for the changes that will occur to the data in the mask making and wafer printing processes. In many cases, the mask maker or “shop” will apply sizing corrections to the data of which the designer is unaware. These process biases may alter some of the features included in the design, especially sub-resolution OPC structures such as scattering bars, serifs, or small edge extensions such that they become so small that they disappear from the data entirely or become large enough to cause problems such as bridging in either the reticle or wafer printing process.
In a further example, the list of design rules becomes impractically long as processes become more complex. While the design rules several years ago could be written on a single piece of paper, current processes can have well over 1,000 design rules that need to be checked. Encoding the design rules into software and ensuring that they completely encompass all possible patterning errors that will reduce device yield is increasingly difficult. If the design rule developer fails to anticipate every possible violation that would impact device performance, these violations will pass through the DRC system undetected. Even ORC systems, while making use of more detailed simulation, still require manual input of long rule lists for the checking component.
DRC and ORC simulations also do not capture the details of the mask making process and offer no means of calibrating the patterns to reflect what will actually be written on the reticle. In another example, the existing checkers do not take into account the key question of whether the pattern as laid out by the design program can actually be written by the reticle processing tools. For example, the current state of the art integrated circuit designs can produce complex designs and layouts that pass the current rule checks, but cannot be manufactured either because the RET pattern is too complex to be written correctly on the reticle, inspected on the reticle, and/or printed at the wafer level. Even so called “correct by construction” approaches only optimize the original, pre-OPC layout to eliminate patterns with design rule violations. However, once the OPC structures are added, numerous design rule violations are still possible. Therefore, the existing rule checkers act on idealized data without addressing the key question of whether or not the design can be written and inspected to yield a manufacturable process from design to reticle to wafer levels.
Many design databases take the initial physical design and add incredibly complex RETs which expand the design data by more than an order of magnitude. These huge layout files include tiny jogs, edge extrusions, and minute critical dimension (CD) variations that cannot possibly be reproduced by the mask writing tools. The resulting large data files lead to very long and expensive reticle writing times which are basically wasted since the pattern cannot be reproduced with all of the tiny CD variations and sub-resolution jogs.
In yet another example, the currently available DRC and ORC systems do not take into account whether or not the pattern can be adequately inspected. For example, even if the patterns could be written, no inspection tool is available that is capable of verifying the correct writing of such patterns and no exposure tool is believed to be available that could print such patterns. Therefore, the effort is wasted. Some of the small RET implementations may actually be counterproductive since in trying to write them on the reticle only a partial pattern can be defined, which can end up creating defects on the reticle and later on the wafer. Writing such large data files on a reticle is relatively expensive. As such, it is highly desirable to detect such problems in the data before the design is committed to the mask writing process thereby saving time and money.
Accordingly, it may be advantageous to develop methods, systems, and carrier media that can be used to evaluate reticle layout data to determine the manufacturability, inspectability, and/or printability of the reticle layout data while eliminating at least some of the disadvantages described above.