1. Field of the Invention
The present invention relates to manufacturing metal patterns in semiconductor devices, and more particularly, to a method of manufacturing such metal patterns. This method is applicable to the manufacture of electrodes in liquid crystal display (LCD) devices.
2. Description of Related Art
A typical LCD device includes first and second transparent substrates with a liquid crystal layer interposed therebetween. The first substrate has a thin film transistor (TFT) as a switching element and a pixel electrode disposed thereon, and the second substrate has a color filter disposed thereon. The pixel electrode serves to apply a voltage to the liquid crystal layer, and the color filter serves to transmit only certain colors of light passing through the liquid crystal.
As shown in FIG. 1, the typical LCD device includes a substrate 1 and a gate electrode 2 formed on the substrate 1. A gate insulating layer 3 covers the whole surface of the substrate 1 and the gate electrode 2. A semiconductor layer 4 is formed over the gate electrode 2. Source and drain electrodes 5 and 6 are formed spaced apart from each other on the gate insulating layer 3 and each overlapping a part of the semiconductor layer 4. A passivation layer 7 is formed on the whole surface of the substrate 1, as well as the source and drain electrodes 5 and 6 and a portion of the semiconductor layer 4. A pixel electrode 9 is formed on the passivation layer 7 and contacts the drain electrode 6 through a contact hole 8 in the passivation layer 7.
FIGS. 2 and 3 illustrate a conventional method of forming the area “II” shown circled in the LCD device of FIG. 1. In order to form the pixel electrode 9, first a metal layer 14 is deposited on the passivation layer 7. The metal layer 14 is made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). Subsequently, photoresist is applied on the metal layer 14 and is patterned to form a photoresist pattern 16 shown in FIG. 2. Then, the metal layer 14 is conventionally etched to form the pixel electrode 9 using the photoresist pattern 16 as a mask. Finally, the photoresist pattern 16 is removed.
Conventional techniques for etching the metal layer 14 have the following disadvantages. In case of wet etching techniques, an organic substance such as a photoresist remnant 16a shown in FIG. 3 may be left on the pixel electrode 9 and the passivation layer 7. This is due to heat generated during the photolithography process. Also, pin holes and cracks may develop in the metal layer 14 when wet etching. Further, the gate electrode 2 and the connecting gate line (not shown) may become open due to the wet etchant. Because wet etching causes the problems of low yields and line defects, dry etching techniques have also been conventionally used for etching.
In case of dry etching techniques, the etch rate is typically low, so that the array substrate is subjected to radio frequency (RF) power for a long time. The photoresist pattern may be damaged by maintaining the array substrate at a high temperature. As a result, the photoresist pattern is not easy to remove, leading to a high defect rate. Further, if the RF power is increased to improve the etch rate, the temperature of the array substrate becomes greater, leading to the photoresist problem described above. For example, as illustrated in FIG. 4, the RF power curve 22 of 2000 watts causes the substrate temperature to increase at a greater rate than the RF power curve 20 of 1500 watts.