Semiconductor devices are typically fabricated upon a wafer, which may be a silicon (Si)-based wafer, or other suitable materials known in the art. One process conventionally applied to Si wafers of semiconductor devices is known as a “stress relief’ process. Stress relief processes are typically applied after the bulk substrate used to form the wafer has been thinned, for example, through a backside grinding process. At least in part due to the thinning process, areas of stress may be formed at the backside of the wafer.
In the stress relief process, the thinned backside of the wafer is polished, thereby shifting some of the stress at the backside of the wafer away from the stress-relieved backside of the wafer and distributing it more evenly throughout the wafer. Examples of stress relief processes include dry polish (DP) techniques, such as mechano-chemical polishing (MCP) techniques, and chemical-mechanical polishing/planarization (CMP) techniques, as well as other techniques known in the art. The stress relief process increases the overall strength of the wafer, thereby increasing die strength, particularly for ultra thin dies (i.e., dies in the sub-50 gm range).
During fabrication of a semiconductor wafer, unwanted contaminants and impurities can be introduced to the wafer during crystal growth or subsequent wafer fabrication processes. Such contaminants and impurities can degrade characteristics and overall yield of devices formed in the semiconductor wafer. Gettering processes can be performed during crystal growth or wafer fabrication steps to move contaminants and/or impurities in a semiconductor wafer into its bulk and away from a device region. Gettering creates a zone in the bulk substrate, known as a denude zone, that is substantially clear of contaminants. Preferably, semiconductor devices (for example, source and drain structures, gate structures, and channel sections) are built in, on, or around the denude zone of the substrate.
Two types of gettering processes are employed in conventional semiconductor wafer fabrication. “Intrinsic gettering” refers to the formation of gettering sites within the bulk substrate. One process for providing intrinsic gettering includes the formation of silicon dioxide (SiO2) sites within the silicon bulk. These SiO2 sites attract and trap ionic impurities within the silicon wafer, thus preventing these impurities from contaminating the device region. “Extrinsic gettering” refers to the use of an external process, such as backside grinding, to create damage or stress (“defects”) in silicon lattices in the wafer. Extrinsic gettering is typically applied at a backside of the wafer. The defects that are created at the backside of the wafer attract impurities, pulling them away from the device section, which is located at a different side (typically, a topside) of the wafer.
As discussed above, performing stress relief processes, such as DP, MCP, or CMP techniques, strengthens the wafer, thereby increasing die strength. It has been observed, however, that the electrical performances of semiconductor devices, and particularly of semiconductor devices in ultra-thin, multi-stack memory devices, may degrade after stress relief processes are applied. This degradation of electrical performance may be attributable to an increase in one or more of contamination-induced leakage, stress-induced leakage, dislocation-induced leakage. Contamination-induced leakage results from metal contaminants and/or free ions in the substrate creating a short circuit at the gates of the memory devices. Stress-induced leakage results from the “stress zone,” which would typically attract contaminants and free ions, being shifted from the wafer backside towards the area where the semiconductor devices are formed. Dislocation-induced leakage results from Crystal Originated Pits/Particles (“COPs”), slips, and dislocations within the silicon creating a short circuit.
Applicants have observed that the increase of contamination-induced leakage, stress-induced leakage, and dislocation-induced leakage may be a result of conventional wafer-thinning and stress relief techniques. These conventional techniques reduce and/or eliminate the intrinsic and extrinsic gettering sites of the wafer.
By way of further explanation, FIG. 1 illustrates a conventional intrinsic gettering technique. In FIG. 1, bulk substrate 101 includes crystal defects 103, such as oxidation-induced stacking faults (OSF), or bulk micro defects (BMD), within substrate 101. Crystal defects 103 provide intrinsic gettering to the substrate 101. As shown in FIG. 1, metal contaminants 102 are attracted to the crystal defects 103, providing a denude zone 105 at a front side of the substrate 101.
As illustrated in FIG. 2, however, the bulk substrate 101 is then reduced in thickness through grinding and/or other conventional wafer thinning processes. When substrate 101 is thinned and/or grinded to a desired thickness 110 (as shown in FIG. 2), the volume of the backside of bulk substrate 101, and thus number of crystal defects 103 outside of the denude zone, is reduced, thereby reducing the amount of intrinsic gettering.
FIGS. 3A-3B illustrate a conventional extrinsic gettering technique. As shown in FIG. 3A, a device section 211 may be formed in a denude zone within bulk substrate 101. Substrate 101 includes an intrinsic gettering section 212 with contaminants 102. Intrinsic gettering section 212 may or may not include intrinsic gettering, as described above with regard to FIG. 1. In FIG. 3A, substrate 101 includes an unpolished backside oxidized layer 213. As shown in FIG. 3B, when bulk substrate 101 is reduced through conventional thinning processes, the thickness of intrinsic gettering section 212 is reduced (as discussed above with regard to FIG. 2). Despite this reduction of intrinsic gettering section 212, as shown in FIG. 3B, extrinsic gettering is provided by the backside grind layer 214 formed by the thinning process. Backside grind layer 214 includes defects in silicon lattices that are formed as a result of the thinning of the backside of substrate 101. These defects attract and/or trap impurities, pulling them away from the denude zone 211.
As illustrated in FIG. 4, however, when conventional stress relief processes (such as DP, MCP, and/or CMP) are applied to remove backside grind layer 214 (FIG. 3B) and form a stress-relieved backside 215, many of the defects that were present in backside grind layer 214 and that acted as extrinsic gettering sites are also removed. As stress relief processes shift the stress previously caused by defects in the backside grind layer 214 away from the stress-relieved backside 215 towards the denude zone 211, mobile metals or ions are able to travel freely towards the device area, potentially short circuiting components of devices formed therein or otherwise undesirably affecting the devices' performances.
Experiments have shown that, by maintaining the extrinsic gettering provided by the backside grind layer after the wafer thinning process, device performances are not degraded. Grind wheels with super fine finishing (for example, with extra small diamond grits size) that leave some portion of the backside grind layer in place are known in the art, and may be used in place of conventional polishing processes. Examples of such “fine” polishing techniques may use, for example, Gettering Dry Polish (“GDP”) and Poligrind® grinding wheels from Disco Corp., or other appropriate systems and processes that are known in the art. Experiments have also shown, however, that such fine polishing techniques, while preserving extrinsic gettering, may reduce die strength compared to other techniques that do not maintain extrinsic gettering (such as, for example, DP, MCP, and CMP polish processes). This reduced die strength can be detrimental to the assembly process for semiconductor devices, particularly for sub-50 μm multiple stack die packages.
Accordingly, it is desirable to maintain gettering in fabricated semiconductor wafers and dies formed therefrom. Also desirable is a fabrication process for semiconductor wafers and dies that includes the strengthening benefits of selected stress relief techniques, while maintaining the performance benefits of gettering for the semiconductor wafer.