In polishing thick substrates of nonferrous metal materials, the technical requirements for the polishing are that the uniformity of film thickness distribution can be imparted to the polished surface for a short time (in case of rough surface, similar roughness is needed in the whole surface).
In general, on nonferrous metal substrates, mechanical polishing using lathe or plane machines has been employed. Such a polishing technique results in a rough and non-uniform distribution of film thickness for the surface, although achieving desirabilities of the polished surface for a short time.
On the other hand, in manufactures of semiconductor such as ULSI and others, where surface planarization is of more importance and a high finishing precision is necessary, the key technology is chemical mechanical polishing (CMP). The CMP technique, which combines chemical etching with mechanical polishing, creates formation of wiring line as small as several tens of nanometers on the semiconductor. That is, in the semiconductor fabrication, the CMP is considered to be the basic in order to form circuit construction in a semiconductor surface. In the CMP technology for the semiconductor manufacturing, by physical vapor deposition (PVD), chemical vapor deposition (CVD) or plating, a thin film is formed on the surface of silicon substrate and the global planarization can be accomplished to the thin film in order to remove the excess part of the thin film which is unnecessary for circuit formation. The technology aims at planarizing globally the thin film, and hence the removal rate is about 100 nm/min at the maximum. In many cases, abrasives such a colloidal silica or an alumina, etc., is compounded in a polishing solution to obtain the polishing effect of the abrasives, and then the CMP process proceeds with the interaction between mechanical polishing and chemical etching, as disclosed in JP-A 2001-68437. Thus, removal of the coherent abrasives particles results in complicated operations in a water rinse process. On the other hand, for materials with highly corrosion resistance, e.g., stainless steel, the CMP technology is applied to mirror-processed planaraization to prevent light from reflecting diffusely: convex mirror used as safety confirmation on the road and mirror-finished panel used as construction parts.
However, in the semiconductor fabrication, e.g., ULSI, the deposited metal film of about 100 nm in thickness has to be globally planarized with the surface roughness of 100 nm or less (the 50 nm roughness at the maximum for the semiconductor), and hence the removal rate lower than 500 nm/min enables the CMP to be controlled. The fact that the metal film is about 100 nm in thickness is difficult to control the CMP because the high removal rate promotes the progress in the polishing so that the film may disappear from the surface.
On the other hand, in the case of the polishing for tungsten film, the CMP technology is also applied. As described in JP-A 2000-119638, the removal rate of about 500 nm/min is required, but a removal rate that is required in the technical region of the present invention cannot be achieved.