The accurate reproduction of patterns on the surface of a semiconductor substrate is critical to the proper fabrication of semiconductor devices. The semiconductor substrate may have undergone previous fabrication processes and may already feature layers and structures created by those fabrication processes. Improperly reproduced patterns can result in semiconductor devices that do not operate to design specifications or do not operate at all. For example, transistors can be created with improperly sized gates, conductors can be created that are short circuited or open circuited with other conductors or devices, structures can be created with wrong geometries, and so forth. Improperly reproduced patterns can reduce the yield of the fabrication process, thereby increasing the overall cost of the product. The reproduction process typically involves the use of optical lithography to reproduce the patterns onto the surface of the semiconductor substrate that is subsequently followed with a variety of processes to either subtract (for example, etch) and add (for example, deposit) materials from and to the semiconductor substrate.
One of the sources of error in the production of semiconductor devices is an error in the mask generation process. Even though the masks used for semiconductor lithography are usually 4× the size of the target image, tolerances of the mask itself are often much smaller than the minimum feature size in the semiconductor process due to small feature size adjustments needed for Optical Proximity Correction (OPC). To obtain the necessary mask resolution for fine geometry processes, the typical mask generation system may use an Electron Beam Exposure system, although lasers are also used in some mask generation processes. Reticle or mask substrates, made of a highly polished piece of fused silica are coated with a material such a chromium using sputtering. A thin layer of resist is applied to the mask substrate, and the substrate is exposed to an electron beam to pattern the mask. The electron beam exposes the resist, and then the mask is typically formed using a wet or dry etch process.
Because of the relatively narrow width of the electron beam, however, the shapes and patterns to be exposed on the mask are typically wider than the maximum beam width of the electron beam exposure system. As such, geometric features need to be fractured and patterned using multiple electron beam exposures. Some electron beam systems use a fixed shape beam, while other systems use a variable width beam. As the mask is exposed, the mask or reticle is mechanically stepped. The process of mechanically stepping and exposing the mask to multiple step and repeat exposures has, in itself, the possibility of introducing error. In stepped regions where exposed areas are adjoining non-exposed areas of a minimum or critical dimension, stepping error at the boundaries of the beam may accumulate and cause mask tolerance errors.
Conventional mask generation processes typically fracture the exposed area of the mask into small electron beam exposure regions. In the past, these fracturing algorithms have been prone to produce small slivers of exposure in areas to be exposed, as well as being prone to create irregular and non-uniform exposure patterns in regular exposed structures like DRAM and other forms of memory. Non-uniform fracturing in memory cells can lead to the possibility of yield failure and irregular electronic performance across the memory array. What is needed is a fracturing method that will ensure regular uniform fracturing along regular array structures.