Complementary Metal Oxide Semiconductor (CMOS) circuits, especially large drivers as found in Input/Output (I/O) buffer designs, are required to output high and low levels. This requires transistors to pull voltage signals “up” for high level outputs and pull signals “down” for low level outputs. Large pull-up and pull-down field effect transistors (FETs) in totem pole drivers can be required for clock drivers and to generate fast edge rates required for high bandwidth connectivity. One disadvantage of these drivers are the large amounts of alternating current (AC) switching power that they require for their operation.
FIGS. 1 and 2 are circuit diagrams of prior art CMOS circuits. In FIG. 1, a circuit 10 illustrates the typical AC power consumption by a CMOS circuit. In circuit 10, an input signal on line 12 drives transistors 14 and 16. With a high input signal on line 12, transistor 14 turns off and transistor 16 turns on, driving an output low level on line 18. With a low input signal on line 12, transistor 14 turns on and transistor 16 turns off, driving an output high level on line 18. The output signal on line 18 drives a capacitive load 20. In FIG. 2, a circuit 22 illustrates the typical AC power consumption by a CMOS I/O buffer. In circuit 22, an output signal on line 24 drives a capacitive load 28 via a pad 26. Both exemplary CMOS circuits 10 and 22 require large amounts of AC switching power, which can be a particular disadvantage.
Accordingly, a need exists for improved circuit switching and, in particular, an improved CMOS switching circuit.