FIG. 9 is a circuit configuration diagram illustrating an example of an oscillation circuit according to a related art example. In FIG. 9, a constant current source 1 has one end connected to a power supply Vdd and another end connected to the sources of p channel MOS transistors M1, M3. A drain of the MOS transistor M1 is connected to a drain of an n channel MOS transistor M2. A source of the MOS transistor M2 is connected to a power supply Vss. A drain of the MOS transistor M3 is connected to a drain of an n channel MOS transistor M4. A source of the MOS transistor M4 is connected to the power supply Vss.
The drains of the MOS transistors M1, M2 are connected to one end of a condenser C1 and also connected to a non-inverting input terminal of a comparator 2. The other end of the condenser C1 is connected to the power supply Vss. The gates of the MOS transistors M1, M2 are connected to a Q terminal of an RS flip-flop 4.
Further, the drains of the MOS transistors M3, M4 are connected to one end of a condenser C2 and also connected to a non-inverting input terminal of a comparator 3. The other end of the condenser C2 is connected to the power supply Vss. The gates of the MOS transistors M3, M4 are connected to a QB terminal of the RS flip-flop 4.
The inverting input terminals of the comparators 2, 3 are connected to one end of a constant voltage source 5 and have a reference voltage Vth applied thereto. The other end of the constant voltage source 5 is connected to the power supply Vss. The comparator 2 has a current input terminal being connected to one end of a constant current source 6 and being supplied with an operating current. The other end of the constant current source 6 is connected to the power supply Vss. The comparator 2 generates an output signal of a high level when a voltage of the condenser C1 exceeds the reference voltage Vth and generates an output signal of a low level when the voltage of the condenser C1 is less than or equal to the reference voltage Vth, and supplies the output signal to a setting terminal S of the flip-flop 4.
The comparator 3 has a current input terminal connected to one end of a constant current source 7 and has an operating current supplied thereto. The other end of the constant current source 7 is connected to the power supply Vss.
The comparator 3 generates an output signal of a high level when a voltage of the condenser C2 exceeds the reference voltage Vth and generates an output signal of a low level when the voltage of the condenser C2 is less than or equal to the reference voltage Vth, and supplies the output signal to a resetting terminal R of the flip-flop 4.
A Q terminal output of the flip-flop 4 becomes a high level and a QB terminal output of the flip-flop 4 becomes a low level when a high level signal is supplied to the setting terminal S. Further, the Q terminal output of the flip-flop 4 becomes a low level and the QB terminal output of the flip-flop 4 becomes a high level when a high level signal is supplied to the resetting terminal R.
<Operation>
In a case where the Q terminal output of the flip-flop 4 is a low level (FIG. 10(E)) while at the same time, the QB terminal output of the flip-flop 4 is a high level (FIG. 10(F)), the MOS transistor M1 is on, the MOS transistor M2 is off, the condenser C1 is charged (FIG. 10(A)), the MOS transistor M3 is off, the MOS transistor M4 is on, and the condenser C2 is discharged (FIG. 10(C)). Further, in a case where the voltage of the condenser C1 exceeds the reference voltage Vth, the output of the comparator 2 becomes a high level (FIG. 10(B)), the flip-flop 4 is set, so that the Q terminal output becomes a high level, and the QB terminal output becomes a low level.
In this case, the MOS transistor M1 is off, the MOS transistor M2 is on, and the condenser C1 is discharged while at the same time, the QB terminal output is a low level, the MOS transistor M3 is on, the MOS transistor M4 is off, and the condenser C2 is charged. Further, in a case where the voltage of the condenser C2 exceeds the reference voltage Vth, the output of the comparator 3 becomes a high level (FIG. 10(D)), the flip-flop 4 is reset, so that the Q terminal output becomes a low level, and the QB terminal output becomes a high level.
There is a known art constituting an oscillation circuit that uses: an amplifier that generates a charge/discharge current of a condenser in accordance with high/low of first and second input signals; two comparators that compares the lower limit voltages; a flip-flop that resets/sets according to output signals from each of the two comparators; a switch that supplies driving currents to one of the two comparators in accordance with a control signal (see, for example, Patent Document 1).
In order for the oscillation circuit of the related art example illustrated in FIG. 9 to steadily output an oscillation signal of a predetermined frequency, it is necessary to supply a sufficient amount of driving current from the constant current sources 6, 7 to the comparators 2, 3. Particularly, in a case where the oscillation frequency is large, the driving current to be supplied to the comparators 2, 3 increases. Therefore, the oscillation circuit of the related art consumes a large amount of electric power.
In a case where the oscillation frequency is set having a large value, the comparators 2, 3 cannot sufficiently react. Thereby, a prohibited state occurs in which the setting terminal S and the resetting terminal RS of the flip-flop 4 become a high level at the same time. Thus, there is a possibility causing oscillation to stop.    Patent Document 1: Japanese Laid-Open Patent Publication No. 2009-159344