The square law behavior of a metal-oxide semiconductor field effect transistor (MOSFET) may be utilized to recover the envelope from a modulated radio frequency (RF) signal. In particular, the drain current for a MOSFET in saturation is proportional to the square of the difference between the gate voltage and the transistor threshold voltage for the MOSFET. The resulting squaring of the drain current rectifies the RF carrier and its even harmonics so that MOSFET rectification is commonly exploited in receivers to recover the envelope of a modulated RF signal. For example, a MOSFET voltage-to-current (V/I) square-law circuit functions to recover the envelope of a modulated RF signal in applications such as a peak detector in an automatic gain control (AGC) circuit.
An example V/I square-law circuit 100 is shown in FIG. 1. A bias voltage (Vbias) signal biases the gate of a first n-type metal-oxide semiconductor (NMOS) transistor M1 and the gate of a second NMOS transistor M2 through a pair of resistors R1 so that transistors M1 and M2 are biased in the saturation mode (or the sub-threshold mode) to each conduct a DC bias current But transistor M1 is also conducting a rectified current because an RF input signal (RFin) drives the gate of transistor M1 through an input capacitor Cm. The total current conducted by transistor M1 is thus a sum of the DC bias current I1 and the rectified current. This total current is mirrored by a first current mirror. In particular, a first diode-connected p-type metal-oxide semiconductor (PMOS) has its drain and gate connected to the drain of transistor M1. The gate of diode-connected transistor P1 couples through a first resistor R2 to the gate of a PMOS current mirror transistor P2 to form the first current mirror with diode-connected transistor P1. The drain of current mirror transistor P2 thus mirrors the DC bias current I1 conducted through the drain of transistor M1. With regard to mirroring the rectified current note that although this current is rectified, it will have a high-frequency amplitude modulation due to a rectified RF carrier from the RF input signal and its even harmonics. A peak detector could respond to this high-frequency amplitude modulation undesirably. Thus, the gate of current mirror transistor P2 couples to a power supply node supplying a power supply voltage VDD through a filter capacitor CFilter that forms a low-pass filter with first resistor R2. An envelope current i1 conducted by current mirror transistor P2 will thus correspond to the envelope of the RF input signal without responding to the RF carrier and its harmonics due to the low-pass filtering from resistor R2 and filter capacitor CFilter. This low-pass filtering has no effect on the DC bias current I1. Current mirror transistor P2 thus conducts a total current equaling a sum of the DC bias current I1 and the envelope current i1.
The DC bias current I1 conducted by transistor M2 is also mirrored through a second current mirror formed by a diode-connected PMOS transistor P3 having its gate coupled to a gate of a PMOS current mirror transistor P4. The effects of first resistor R2 are duplicated by a matching second resistor R2 that couples the gate of diode-connected transistor P3 to the gate of current mirror transistor P4. The drain current for current mirror transistor P4 will thus equal the DC bias current I1 also conducted by current mirror transistor P2. A peak detector may then determine the peak power of the envelope responsive to a difference between the drain currents for current mirror transistors P2 and P4. However, note that the frequency response for the low-pass filter includes an RC pole proportional to R2*CFilter. It is conventional to require a settling time from the RC pole to be substantial (e.g., 1 μs) to adequately smooth the envelope. In addition, circuit 100 often requires high sensitivity. The settling time and sensitivity requirements thus force the capacitor CFilter to be relatively large, which then demands die space.
Accordingly, there is a need in the art for a more compact integrated V/I square-law circuit.