A typical computer system has at least a microprocessor and memory. The microprocessor processes, i.e., executes, instructions to accomplish various tasks of the computer system. Such instructions, along with the data required by the microprocessor when executing these instructions, are stored in some form of memory. FIG. 1 shows a typical computer system having a microprocessor (10) and some form of memory (12). The microprocessor (10) has, among other components, a central processing unit (also known and referred to as xe2x80x9cCPUxe2x80x9d or xe2x80x9cexecution unitxe2x80x9d) (14) and a memory controller (also known as xe2x80x9cload/store unitxe2x80x9d) (16). The CPU (14) is where the actual arithmetic and logical operations of the computer system take place. To facilitate the execution of operations by the CPU (14), the memory controller (16) provides the CPU (14) with necessary instructions and data from the memory (12). The memory controller (16) also stores information generated by the CPU (14) into the memory (12).
The operations that occur in a computer system, such as the logical operations in the CPU and the transfer of data between the CPU and memory, require power. If the components responsible for carrying out specific operations do not receive adequate power in a timely manner, computer system performance is susceptible to functional and timing degradation. As an added challenge, power consumption of modern computers has increased as a consequence of increased operating frequencies. Thus, providing power to the components in a computer system in a sufficient and timely manner has become an issue of significant importance.
Often, power supply to a particular computer system element varies, which, in turn, effects the integrity of the element""s output. Typically, this power variation results from the distance between a power supply for the element and the clement itself. This distance may lead to the element not receiving power (via current) at the exact time it is required.
As shown in FIG. 2, one approach used by designers to combat this performance-inhibiting behavior is introducing decoupling capacitance to a particular circuit by positioning one or more decoupling capacitors (22) close to drivers (i.e., circuit elements, such as transistors, responsible for inputting and selectively outputting signals) (24) on an integrated circuit (20). These decoupling capacitors (22) store charge from a power supply and distribute the charge to the drivers (24) when needed. For example, if power received by a driver (24) from a power supply line (26) attenuates, one or more decoupling capacitors (22) will distribute charge to the driver (24) to ensure that the driver (24) is not affected by the power variation on the power supply line (26). In essence, a decoupling capacitor acts as a local power supply for one or more elements in a computer system.
It follows that an important concern for designers is not only to ensure that there is sufficient overall decoupling capacitance on an integrated circuit, but also to ensure that the capacitance needs of the individual elements on the integrated circuit are met. In other words, although the total decoupling capacitance requirement of an integrated circuit may be met through the displacement of decoupling capacitors on the integrated circuit, certain elements may not receive sufficient decoupling capacitance due to (1) excessive decoupling capacitance provided to other elements and/or (2) the positions of decoupling capacitors being xe2x80x98too farxe2x80x99 from decoupling capacitance requiring elements to effectively provide any decoupling capacitance to those elements. Thus, in order to ensure that individual elements on an integrated circuit receive sufficient decoupling capacitance, there is a need for a decoupling capacitance verification technique by which one can determine whether decoupling capacitors are being used effectively and whether particular circuit elements are receiving sufficient decoupling capacitance.
According to one aspect of the present invention, a method for verifying decoupling capacitance on an integrated circuit having a decoupling capacitor and a driver element comprises defining a first node (where the first node represents the decoupling capacitor), defining a second node (where the second node represents the driver element), generating a network comprising the first node and the second node, selectively establishing a connection between the first node and the second node, determining a maximum flow value for the connection between the first node and the second node, and determining whether the maximum flow value is substantially equal to a decoupling capacitance need value of the driver element.
According to another aspect, a method for verifying decoupling capacitance on an integrated circuit having a plurality of decoupling capacitors and a plurality of driver elements comprises defining a first set of nodes (where the first set of nodes represents the plurality of decoupling capacitors), defining a second set of nodes (where the second set of nodes represents the plurality of driver element), selectively establishing a first plurality of connections between a node in the second set of nodes and nodes in the first set of nodes that represent decoupling capacitors that provide decoupling capacitance to a driver element represented by the node, determining maximum flow values for the first plurality of connections; and determining whether a total of the maximum flow values is substantially equal to the decoupling capacitance need value of the driver element.
According to another aspect, a computer system comprises a processor, a memory, and instructions, residing in the memory and executable on the processor, for verifying decoupling capacitance on a microprocessor circuit using a maximum flow determination of a network representing a plurality of driver elements and a plurality of decoupling capacitors on the microprocessor.
According to another aspect, a method for designing an integrated circuit comprises verifying decoupling capacitance of an original design of an integrated circuit using a flow determination of a network representative of decoupling capacitors and driver elements on the integrated circuit and redesigning the integrated circuit dependent on the verification.
According to another aspect, a computer-readable medium having recorded therein instructions executable by processing, where the instructions for defining a first node (where the first node represents a decoupling capacitor on an integrated circuit), defining a second node (where the second node represents a driver element on the integrated circuit), generating a network comprising the first node and the second node, selectively establishing a connection between the first node and the second node, determining a maximum flow value for the connection between the first node and the second node, and determining whether the maximum flow value is substantially equal to a decoupling capacitance need value of the driver element.
According to another aspect, a computer-readable medium having recorded therein instructions executable by processing, where the instructions are for defining a first set of nodes (where the first set of nodes represents a plurality of decoupling capacitors on an integrated circuit), defining a second set of nodes (where the second set of nodes represents a plurality of driver elements on the integrated circuit), selectively establishing a first plurality of connections between a node in the second set of nodes and nodes in the first set of nodes that represent decoupling capacitors that provide decoupling capacitance to a driver element represented by the node, determining maximum flow values for the first plurality of connections, and determining whether a total of the maximum flow values is substantially equal to a decoupling capacitance need value of the driver element.
According to another aspect, a method for graphically verifying decoupling capacitance on an integrated circuit comprises generating a directed graph comprising a plurality of decoupling capacitor nodes and a plurality of driver element nodes, defining a source node (where the source node has edges connected to the plurality of decoupling capacitor nodes), defining a sink node (where the sink node has edges connected to the plurality of driver element nodes), selectively establishing a plurality of edges between the plurality of decoupling capacitor nodes and the plurality of driver element nodes, determining a maximum flow from the source node to the sink node, and using the maximum flow to verify decoupling capacitance on the integrated circuit.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.