Recently, semiconductor devices become more highly integrated. When a plurality of highly integrated semiconductor devices are arranged within a horizontal plane and connected with one another by wiring into a product, the wiring length may increase to lead to an increase in resistance of the wiring and increase in a wiring delay.
Hence, it is proposed to use the three-dimensional integration technology of stacking the semiconductor devices in three dimensions. In this three-dimensional integration technology, for example, a bonding apparatus is used to join two semiconductor wafers (hereinafter, referred to as “wafers”). The bonding apparatus has, for example, a chamber housing two wafers arranged one above the other (hereinafter, the wafer on the upper side is referred to as an “upper wafer” and the wafer on the lower side is referred to as a “lower wafer”), a pressing and moving pin provided in the chamber and pressing the central portion of the upper wafer, and a spacer capable of supporting the outer periphery of the upper wafer and retreating from the outer periphery of the upper wafer. In the case of using the bonding apparatus, the joint of the wafers is performed with the inside of the chamber brought into a vacuum atmosphere so as to suppress generation of void between the wafers. Concretely, the pressing and moving pin first presses the central portion of the upper wafer with the spacer supporting the upper wafer, to bring the central portion into abutment with the lower wafer. Thereafter, the spacer supporting the upper wafer is retreated to bring the entire surface of the upper wafer into abutment with the entire surface of the lower wafer to bond them together (Patent Document 1).    [Patent Document 1] Japanese Patent Application Laid-open No. 2004-207436