In the past few years, the growing demand for low voltage, low power, low cost and high performance mobile communications equipment has changed the way wireless receivers are designed. Complementary metal oxide semiconductor (CMOS) technology has become a practical contender for use in receiver design, especially because it lends itself to easier integration with digital ICs. However, usage of deep submicron CMOS technologies imposes an upper limit on the supply voltages that transistors can handle, therefore it is important to focus on low voltage design when designing RF CMOS circuits.
A typical, direct conversion (or low intermediate frequency (IF)) radio frequency (RF) receiver includes a front end low noise amplifier (LNA) followed by a mixer. The mixer output goes to a continuous time filter that performs the channel selection filtering. Most modem mixers used in current wireless receivers are based on the conventional Gilbert Cell mixer. FIG. 1 diagrammatically illustrates the basic architecture of a conventional continuous-time single balanced Gilbert cell mixer 100. The output voltage of LNA 110, which contains RFin 105, is converted to current by transconductance element 115. Transconductance element 115 can be implemented as a transistor with its gate coupled to an output of LNA 110 and its source coupled to voltage supply (VSS) 112. This current is then fed into two (2) parallel switches, 120 and 125, which are clocked by VLO− 130 and VLO+ 135, respectively. Switches 120 and 125 can be implemented as transistors with their sources both tied to the output of transconductance element 115. VLO− 130 and VLO+ 135 are produced by a local oscillator (LO). The drains of transistors 120 and 125 are coupled to voltage potential (VDD) 114 by a pair of load resistors, 140 and 145, respectively. This ensures that none of the input signal content is lost and that switches 120 and 125 perform the mixing function of the RF signal with the LO frequency. The mixing generates the multiplication of I(RF) with VLO at frequencies RF−LO (via switch 120 ) and RF+LO (via switch 125 ). Of these, RF−LO becomes the IF signal of interest. It is then filtered for appropriate channel selection by a filter (not shown) following mixer 100. After the multiplication, or mixing, by switches 120 and 125, the output current can be expressed as iout(t)=sgn[cos ωLOt]{Ibias+IRF cos ωRFt}, where ωRF is the RF frequency and ωLO is the frequency at which the LO (e.g., a voltage controlled oscillator (VCO)) is running.
One of the main difficulties with the implementation of the receive chain in a conventional continuous domain approach is that it requires high power and area, particularly for the baseband filter, in order to achieve sufficient dynamic range with all the process variations. For a conventional CMOS receiver, the majority of the power and area consumption is in the implementation of a continuous time filter with sufficient dynamic range and low noise. Recently, there have been several approaches to solving the high power requirement of CMOS receivers involving the implementation of the receive chain in a sampled domain switched capacitor approach.
In the conventional sampled domain switched capacitor approach, a single-ended LNA amplifies the RF signal and passes it to the mixer. The mixer then stores the sampled data points in a capacitor, rather than passing on a continuous domain signal. At the same time, several samples over the capacitor can be integrated to implement a filter within the mixer, acting as an anti-alias filter before the next stages. FIG. 2 is a block diagram of sampling architecture using a conventional switched capacitor approach. A signal received in block 210 is input to LNTA 220 which amplifies the signal before passing it to Multi-Tap Direct Sampling Mixers (MTDSM) 225 in block 200. Finally, the output of block 200 is demodulated by demodulator 230. One of the major bottlenecks of this architecture is that much of the linearity and gain are obtained simultaneously from mixers 225.
There have been two (2) published approaches to implementing the mixer in the switched capacitance domain. One uses the LNA to provide a voltage domain output. The other uses the LNA to not only provide a voltage domain output, but also as a voltage to current converter. The latter has been found to be more beneficial because it enables the implementation of an anti-alias filter by simply integrating several samples together on the capacitor. FIG. 3 diagrammatically illustrates a conventional approach to implementing mixer 300 in a switched capacitance domain. The output voltage of LNA 110, which contains RFin 105, is converted to current by transconductance element 115. Transconductance element 115 can be implemented as a transistor with its gate coupled to LNA_OUT 310 and its source coupled to voltage potential (VDD) 114. This current is then fed into two (2) parallel switches, 120 and 125, which are clocked by VLO− 130 and VLO+ 135, respectively. Switches 120 and 125 can be implemented as transistors with their drains both tied to the drain of transconductance element 115. VLO− 130 is applied at the gate of transistor 120, while VLO+ 135 is applied at the gate of transistor 125. The source of transistor 120 is tied to node 345, while the source of transistor 125 is tied to node 335. Capacitor 320 is coupled between node 345 and voltage source (VSS) 112. Capacitor 330 is coupled between node 335 and VSS 112. In this case, after the current is integrated over capacitors 320 and 330 by performing several consecutive samples, the overall integrated charge is transferred to stage 380, the IF amplifier feedback capacitance, by means of dump switches 340 and 350. Dump 340 is coupled between node 345 and input (INP) 360 of stage 380. Dump 350 is coupled between node 335 and input (INM) 370 of stage 380. Dumps 340 and 350 can be implemented as transistors with their drains tied to nodes 345 and 335, respectively, and their sources coupled to INP 360 and INM 370, respectively. The mixing is performed by sampling switches 120 and 125.
Although the requirement of high power and area for the filter in order to achieve high dynamic range and gain programmability can be avoided by implementing the full channel in switched capacitor or sampled domain, there remains a significant interdependency between gain and linearity: linearity of the mixer suffers as gain increases. There are two (2) main reasons why this interdependency occurs and why it is a problem. First, in a switched capacitor mixer, mixer 300 acts as the first switched capacitor block after continuous time LNA 110. This means that the linearity achievable from mixer 300 directly impacts the linearity of the full channel. Since mixer 300 is implemented by MOS switches 120 and 125 and capacitors 320 and 330, the circuit performance is limited by the existence of non-linear switch parasitics operating at very high RF frequencies. These parasitics destroy the advantages of implementing an RF switch at very high frequencies. Therefore, a reasonable gain and linearity can be achieved from mixer 300 only with a very low gain restriction to the LNA-mixer combination. The dynamic range of active components such as LNAs is typically defined on the low-output signal side by the noise figure (NF), and on the high-output signal side by intercept points (e.g., the intercept point second order, IP2, and the intercept point third order IP3). Intercept points indicate how much output level can be achieved before limitations occur due to undesired distortions. An intercept point is actually a fictitious, extrapolated point on an output versus input curve for a given device. Output level limitations may be manifested as nonlinearities in the response of a device, which in turn may appear as harmonics of an input signal. The second reason is that, for a direct conversion architecture, mixer 300 samples (or mixes) the RF input at the same RF frequency at the same time. At this frequency, the implementation of the switch is extremely difficult. This is a key issue when the amount of matching required between two (2) symmetrically placed switches 120 and 125 is considered. For the conventional architecture described above, the matching requirement for two (2) non-overlapping clocks at the positive, VLO+ 135, and negative, VLO− 130, arms of mixer 300 has been found to be less than 5 ps. This limitation is very problematical.
The main problem with the conventional sampling mixer, such as mixer 300, is the linearity of sampling switches 120 and 125. At the instant that each switch 120 and 125 is turning off, its transition is dependant on the absolute gain to the source voltage. If a large gain has been allowed in the LNA-mixer combination (i.e., integration occurred for a long duration), then the absolute voltage levels of capacitors 320 and 330 has become very high. Additionally, due to the existence of several blockers, the signal wave form has become highly amplitude modulated. This makes the “off” instance of each switch 120 and 125 a strong function of signal input RFin 105, leading to severe distortion (IP3 in this case). It has been observed that for such a structure, implemented in 0.15μ CMOS, if gate clocks VLO− 130 and VLO+ 135 are kept at a voltage of 1.5 volts, the dynamic range of each switch 120 and 125 starts degrading significantly as soon as the absolute voltage at the source and drain exceeds 50 mV. This effect can be verified by applying two (2) adjacent channel RF signals to the LNA inputs and observing the IP3 generated tone at the mixer output by using an ideal IF amplifier (dual tone test). The restriction of the maximum voltage at capacitors 320 and 330 limits the maximum gain achievable from the combination of LNA 110 and mixer 300. This makes the entire receiver less effective, since more gain in the LNA-mixer combination results in better overall noise performance in the subsequent blocks.
A similar situation arises due to the signal dependant clock feed-through. If the magnitude of the AC signal at each switch 120 and 125 changes by a large amount, the voltage that gets fed-through to capacitors 320 and 330 from each clock VLO− 130 and VLO+ 135, respectively, becomes signal dependant. This phenomena is also known as LO feed-through. It adds to the degradation of IP3 and also generates a strong “self-mixing” component within the desired channel. This also contributes to limiting the absolute gain in the LNA-mixer combination.
It is therefore desirable to provide a solution that reduces the interdependency between gain and linearity in a switched capacitor mixer circuit, supplies higher power without sacrificing area, and reduces the parasitic effects of the RF switch. The present invention achieves this by implementing the sampling process at the AC ground node, rather than at the signal side, and adding a gated transistor in the signal path. Charge boosting circuitry allows a reduction in the effective size of the series switch that follows the transconductance element.