Semiconductor memory devices include, for example, a static random access memory (SRAM) and a dynamic random access memory (DRAM). A DRAM memory cell generally includes one transistor and one capacitor, thereby providing a high degree of integration. DRAM, however, requires constant refreshing, which limits the use of DRAM to computer main memory. An SRAM memory cell, by contrast, is bi-stable, meaning that it can maintain its state indefinitely, so long as adequate power is supplied. SRAM also supports high speed operation, with lower power dissipation, which is useful for computer cache memory.
One example of an SRAM memory cell is a six transistor (6T) SRAM memory cell that includes six metal-oxide-semiconductor (MOS) transistors. As processes for fabricating MOS devices migrate to nanometer technologies, the use of conventional 6T SRAM cells within processor cache memories prohibits compliance with performance specifications. To meet these performance specifications, eight transistor (8T) SRAM cells are replacing 6T SRAM cells. Use of an 8T SRAM cell may enable independent sizing of the devices on the read and write ports of the memory cell for supporting a lower minimum write voltage (Vmin), while enabling a high performance read operation. Unfortunately, the use of 8T SRAM memory cells does not overcome the effect of weak bits, which are generally caused by the nanometer technology process variations on the read port devices for large size SRAM cache memory arrays.