FIG. 1 is a diagram illustrating a schematic configuration of a high-speed signal transfer system. As illustrated in FIG. 1, the signal transfer system has a transmission circuit 1, a transfer line 2, and a reception circuit 3. In the transmission circuit 1, low-speed parallel data is converted into serial data in a multiplexer (MUX) 11 and the serial data is output to the transfer line 2 by a driver 12 having an output impedance the same as the characteristic impedance of the transfer line 2. The serial data is input to the reception circuit 3 via the transfer line 2. An input reception waveform received by the reception circuit 3 is deteriorated by the characteristics of the transfer line 2. Specifically, the high-frequency component is lost and the waveform is dulled.
Data to be transmitted is two-value data of “0” and “1” and when the degree of deterioration through the transfer line 2 is low, the input reception waveform for the serial data indicated by a string of “0's” and “1's” on the lower side is such that as illustrated in FIG. 2A. With this received signal waveform, it is possible to correctly reproduce the received data by setting a threshold level to a level indicated by the broken line and by determining the waveform with a comparator.
However, when the transfer line 2 is long or the frequency of the transmission data is very high, the degree of deterioration through the transfer line 2 is high and the input reception waveform for the serial data indicated by a string of “0” and “1” on the lower side is such that illustrated in FIG. 2B. With such a received signal waveform, it may not be possible to correctly reproduce received data by determining the waveform using only one comparator. In order to deal with this, the signal level is detected in accordance with a clock of the received data as illustrated in FIG. 2B and then the received data is reproduced correctly.
Because of this, as illustrated in FIG. 1, the reception circuit 3 samples the received signal (analog waveform) and digitizes the signal using an analog/digital converter (ADC) 31 disposed at the input part. An equalization circuit (EQ) 32 shapes the waveform (equalization processing) so as to compensate for the deterioration of waveform through the transfer line. The received data that is shaped is determined to be a “0” or “1” and the determination result is converted from serial data into parallel data by a decision latch/demultiplexer (D/L DMUX) 33. A clock signal may be necessary for sampling in the ADC 31 and processing in the equalization circuit 32. A clock recovery unit (CRU) 34 reproduces a data clock from the received data output from the equalization circuit 32. In the circuits to be explained below, the CRU 34 is provided, however, an explanation is not given for the sake of simplification and it is not illustrated schematically.
FIGS. 3A and 3B are diagrams illustrating a configuration of an embodiment of the equalization circuit 32 called a decision feedback equalizer (DFE). FIG. 3A illustrates a conceptual diagram and FIG. 3B illustrates a specific circuit configuration. If a transfer function of the transfer line 2 is assumed to be H(z), adjustment is made so that the transfer function of a DFE 37 is 1-H(z). One sample received signal is H(z) and if the output 1-H(z) of the DEF 37 is added to the received signal H(z) by an adder 35, a signal without deterioration is output as a result and this is determined by a comparator 36. Due to this, transmission data dn may be received correctly. Specifically, in order to sequentially compensate for the influence of the previous sample data, the sample data ahead by one sample is delayed by one sampling period and the sample data ahead by two samples is delayed by two sampling periods, and in this manner, the sample data is delayed sequentially up to that ahead by a certain number of samples and the delayed data is multiplied by a coefficient in accordance with the degree of influence and added to input data.
As illustrated in FIG. 3B, the equalization circuit 32 has the DFE 37 having a plurality of multipliers cn0 to cnm, a plurality of the adders 35, the comparator 36, a switch 38 that switches between feedback of data having been subjected to equalization processing and feedback of training data, a comparator 39 that binarizes data to be fed back, a plurality of delay units 40 that generate data to be applied to cn1 to cnm after delaying the binarized feedback data, a subtracter 41 that calculates a difference between the data having been subjected to equalization processing and the binarized feedback data and generates an amount of error en, and a coefficient update part (e.c. LMS (Least-mean-square)) 42 that updates the coefficients of the multipliers cn0 to cnm so that the amount of error is small based on the amount of error en. The multiplier cn0 multiplies the data output from the ADC 31 by a certain coefficient and outputs the data and the multipliers cn1 to cnm multiply the previous sample data that is delayed by a certain coefficient and output the data, and the data is added by the adder 35.
H(z) is a z function and because of the limitations of hardware, normally, the terms beyond a certain finite term are truncated. To the coefficients of the multipliers cn0 to cnm, the values acquired by applying the LMS algorithm are set here, however, there may be a case where fixed values are set in advance. The coefficients of the multiplier represent the frequency characteristic of the transfer line. The amount of error, which is an input to the coefficient update part 42, is an error from an ideal waveform that remains even after the waveform shaping using the coefficients. The magnitude of the error represents the quality of the shaped waveform.
The equalization circuit is described in, for example, patent document 1, and therefore, no further explanation is provided.
Returning to FIG. 1, in order that equalization processing is performed correctly in the equalization circuit 32, it may be necessary for the ADC 31 to have an appropriate range of input signal (input quantization range) and precision (resolution).
FIG. 4 illustrates a configuration of a conventional example for appropriately controlling the input quantization range of the ADC in a high-speed signal transfer system. This configuration is described in, for example, patent document 2. In the configuration in FIG. 4, a peak/bottom detection circuit 45 is provided, which detects the maximum value (peak value) and the minimum value (bottom value) of the voltage of the signal waveform (analog signal) received by the reception circuit 3, and the reference voltage of the ADC 31 is adjusted, and thereby, it is possible to quantize the entire range of input signal.
FIG. 5 is a diagram illustrating a configuration of the ADC 31 used in the configuration in FIG. 4. There are various types for the ADC; however, an ADC that may be used generally in high-speed signal transfer as high as Giga bits/sec is almost limited to a flash type at present. As illustrated in FIG. 5, in a flash type ADC, between a high-side reference potential VrefH generated by a VrefH generation circuit 46 and a low-side reference potential VrefL generated by a VrefL generation circuit 47, a resistor string (ladder resistor) 48 is provided and a divided potential, which is the reference potential divided, is generated at the connection node of the resistors. Each of a plurality of comparators 49 compares a voltage V1 of an input signal (input voltage) with a divided potential. When Vi is smaller than a certain divided potential, the output of the comparators located on the upper side of the comparator 49 that made comparison with the divided potential is “0” and the comparators located on the lower side of the comparator, including the comparator 49 that made comparison, is “1”, which is a so-called thermometer style, and when the outputs of the plurality of comparators 49 are encoded by an encoder 50, a digital output in the binary form in accordance with the level of Vi is obtained. For an N-bit ADC without an interpolation method, (2N−1) comparators are desired. Although not illustrated schematically, the comparator includes an amplifier. The part including the VrefH generation circuit 46, the VrefL generation circuit 47 and the ladder resistor 48 is referred to as a reference generation circuit and the part including the amplifier and the comparators is referred to as an ADC core.
The ADC in FIG. 5 has the VrefH generation circuit 46 that generates the high-side reference potential VrefH and the VrefL generation circuit 47 that generates the low-side reference potential VrefL because of the use in the configuration in FIG. 4, and is configured so that VrefH and VrefL are adjusted by the peak/bottom detection circuit 45. In the configuration in FIG. 5, it is possible to adjust both VrefH and VrefL; however, there may be a case where VrefL is a fixed potential (for example, ground) and only VrefH may be adjusted. When the input quantization range is not adjusted, VrefH and VrefL are fixed.
By using such an ADC illustrated in FIG. 5, providing the peak/bottom detection circuit 45, and adjusting the reference voltage of ADC, it is possible to quantize the entire voltage range of input signal by the number of bits of ADC.
FIG. 6 illustrates a configuration of another conventional example for appropriately controlling the input quantization range of ADC in a high-speed signal transfer system. In the configuration illustrated in FIG. 6, an amplitude adjustment (AGC (Automatic gain control)) circuit 51 is provided at the input part of the reception circuit 3 and the input voltage range of the input signal to the ADC 31 is made substantially constant. In this configuration, it may not be necessary to adjust the input quantization range of the ADC 31 and an ADC in which VrefH and VrefL are fixed may be used without the need to provide the VrefH generation circuit 46 and the VrefL generation circuit 47 in the ADC in FIG. 5. Within the AGC circuit 51, it is normal to provide a peak/bottom detection circuit and perform feedback so that the signal amplitude after amplification is a certain value. The AGC circuit is a well-known circuit.
In general, the precision (resolution) of ADC, in other words, the number of bits of ADC is acquired in view of the signal waveform of the transmission circuit, the frequency characteristic (impulse response characteristic) of the transfer line, the sensitivity of ADC, the loss compensation performance (achieved SNR) of the equalization circuit, etc., and an ADC with an appropriate precision is selected based on the simulation result.