The present invention is related to supplying a supply voltage to a digital circuit, and more particularly, to a digital circuit block having reducing supply voltage drop and a method for constructing the same.
In the field of digital circuit design, one of the most efficient ways to arrange each of the digital cells within a digital circuit is to perform an automatic placement and routing (APR) process upon the functional digital cells after the digital circuit is designed. Normally, the APR process is performed by software tools. Please refer to FIG. 1. FIG. 1 is a diagram illustrating a prior art digital circuit 10 after performing the APR process. The digital circuit 10 comprises a plurality of functional digital cells 11a˜11d, a power rail 12, and a ground rail 13, in which the power rail 12 is coupled to a supply voltage VDD to supply power to each of the functional digital cells 11a˜11d, and the ground rail 13 provides a ground voltage GND for the functional digital cells 11a˜11d. However, the APR process may generate a gap between some of the two functional digital cells, such as the gap 14 between the functional digital cells 11b and 11c, when optimizing the whole digital circuit 10. If this happens, the gap 14 will be filled up by a filler capacitor 15 in order to stabilize the supply voltage VDD for the functional digital cells 11b and 11c. However, since the filler capacitor 15 is implemented by a CMOS (Complementary Metal Oxide Semiconductor) transistor, and the electric charge of the filler capacitor is accumulated on the gate terminal and the substrate of the CMOS transistor, the electric charge may leak from the gate terminal to the substrate of the CMOS transistor. Therefore, a significant leakage current may be induced if the digital circuit 10 includes a large number of filler capacitors. Accordingly, to reduce the leakage current problem of the digital circuit 10 is becoming one of the most urgent problems in the field of digital circuit design.