1. Field of the Invention
This invention is related to Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET) structure formed on a semiconductor substrate to protect internal integrated circuits present on the semiconductor substrate from damage due to extreme voltages from electrostatic discharge (ESD).
2. Description of the Related Art
Electrostatic discharge (ESD) damage has become one of the main reliability concerns on the integrated circuit (IC) products. Especially, now that complementary metal oxide semiconductor (CMOS) technology has developed into the deep-submicron lithographic feature size, the scaled-down metal oxide semiconductor (MOS) devices and thinner gate oxide has become more vulnerable to the extreme voltage level from contact with an ESD voltage source. For general industrial specifications, the input and output pins of the IC products have to sustain the extreme voltage level from contact with an ESD voltage source of above 2,000V. Therefore, the ESD protection circuits have to be placed around the input and output pads of the IC""s to protect the IC""s against the ESD damage by shunting the electrical charges present at the ESD voltage source from the internal circuits of the IC""s.
FIGS. 1a and 1b illustrate a modified version of the ESD structure as described in Lee. The second N+ diffusion 60 forms the collector of the parasitic bipolar junction transistor 110 and the third N+ diffusion 70 forms the emitter of the parasitic bipolar junction transistor 110. The base of parasitic bipolar junction transistor is the area of the P-type substrate 5.
The fourth N+ diffusion 80 forms the collector of the parasitic bipolar junction transistor 150 and the N+ diffusion 77 forms the emitter of the parasitic bipolar junction transistor 150. The base of the parasitic bipolar junction transistor 150 is the area of the P-type substrate 5 between the fourth N+ diffusion 80 and the N+ diffusion 77.
Further, the fourth N+ diffusion 80 and the N+ diffusion 77 respectively form the drain and source of the first MOS FET to dissipate the electrical charge of the ESD voltage source. Additionally, the second N+ diffusion 60 and the N+ diffusion 77 respectively form the drain and source of a second MOS device to dissipate the charge of the ESD voltage source. The conductive layer 90 that is formed on the insulative gate oxide 95 forms the gate of the first MOS FET. The conductive layer 92 is optionally formed on the insulative gate oxide 95 to form the gate of the second MOS device. If the conductive layer 92 is eliminated the field device structure of Lee is formed.
The second P+ diffusion 72 of Lee forms an isolation region to separate the third N+ diffusion 70 and the N+ diffusion 77. The third N+ diffusion 70, the N+ diffusion 77, and the second P+ diffusion 72 are connected with the conductive layer 240 through the guard ring 10 to the ground reference potential 40.
As described in Lee, when the ESD voltage source is brought in contact with the input terminal or input pad of the integrated circuit the currents that result due to the avalanche breakdown of the junctions of the second N+ diffusion 60 with the P-type substrate 5 and the fourth N+ diffusion 80 with the P-type substrate 5 cause equal currents to flow in the bulk resistors 130 and 140 thus causing the parasitic bipolar junction transistors 110 and 150 to conduct more evenly to dissipate the charge from the ESD voltage source.
U.S. Pat. No. 5,623,156 (Watt) teaches an ESD protection circuit and structure for input/output devices. The circuit provides protection against ESD on input/output pads by providing a more uniform current distribution through a pulldown FET. The ESD structure of Watt employees a source-side series resistor for the pulldown FET. The structure includes three major portions: the pulldown FET formed in a semiconductor substrate (preferably p-type), an ohmic contact region (preferably P+), and a resistor.
U.S. Pat. No. 5,262,344 (Mistry) discloses an N-channel clamp for ESD protection in self-aligned silicided CMOS process. The ESD protection device is formed in an integrated circuit by an N-channel grounded-gate transistor. This protection device has a polysilicon gate, with the siliciding of the protection device is controlled so that adverse effects of ESD events are minimized. There are no silicide areas created on top of the polysilicon gate of the protection device, nor on the source/drain regions near the gate and self-aligned with the gate, as there is for other transistors made by the CMOS process. The siliciding of the protection transistor near the gate is prevented by using a deposited oxide layer as a mask, and this oxide layer is also used to create sidewall spacers for the transistor gates.
U.S. Pat. No. 5,856,693 (Onishi) describes a semiconductor integrated circuit device that improve the ESD breakdown resistance of its protection MOSFET. The protection MOSFFT with the LDD structure. The LDD region of the drain is larger than the LDD region of the source. Thus, the resistance of the drain region is greater than that of the source region, increasing the breakdown voltage of the protection MOSFET. As a result, even if the snapback voltage of the MOSFET fluctuates or varies from place to place in the same MOSFET, the snapback phenomenon tends to occur within the entire drain region almost simultaneously and improving the ESD protection of the internal circuits.
U.S. Pat. No. 5,565,790 (Lee) discloses and ESD protection circuit with field transistor clamp and resistor in the gate circuit of a clamp triggering FET. The ESD protection circuit has a field transistor connected as a clamp between ground and a pad to be protected and an FET trigger circuit that is connected between ground and an input/output node where the protected circuits are connected. A resistor interconnects the pad and the node. The trigger FET turns on when a high ESD voltage causes avalanche breakdown and charge carriers from the trigger FET turn on the field transistor clamp. Before the field transistor clamp turns on, oxide breakdown in the gate oxide of the FET occurs. A resistor is connected between the gate electrode and ground to limit the current through the oxide during the time for the avalanche to develop and for the clamp to turn on.
U.S. Pat. No. 5,440,163 (Ohhashi) teaches a CMOS inverter that has an resistance between the source regions of the n-channel MOS transistor and the branches the ground wiring layer and an resistance between the drain regions of the n-channel MOS transistor and the branches of the output wiring layer. The p-channel MOS transistor of the CMOS inverter does not have the resistances in the source and drain connections. If electrostatic pulses are applied through the power supply and ground terminals of the device, the CMOS inverter is prevented from being destroyed.
U.S. Pat. No. 5,721,439 (Lin) teaches a MOS transistor structure for an ESD protection circuit of an integrated circuit device. The ESD protection transistor has a structure that comprises a drain diffusion region formed in the silicon substrate of the integrated circuit device, a source diffusion region formed in the silicon substrate, a gate formed in the silicon substrate, and a number of isolated islands evenly distributed throughout the drain diffusion region. The isolated islands provide substantially uniform diffusion resistance between the drain contacts and the gate while increasing the diffusion resistance of the drain region to a level suitable for ESD current protection.
U.S. Pat. No. 5,744,840 (Ng) describes an ESD device structure for protecting one or more nodes of an integrated circuit. The protecting device structure includes an MOS diode structure having source and drain regions and at least a pair of localized auxiliary region. Each of this pair of localized auxiliary regions has a conductivity type that is opposite from that of the source and drain regions. These localized auxiliary regions are located contiguous with the source and drain regions, respectively, and in the channel between the source and drain regions.
An object of this invention is to provide an ESD protection circuit that will prevent internal circuits of an integrated circuit formed on a semiconductor substrate from incurring damage during extreme voltage levels when in contact with an ESD voltage source.
To accomplish this and other objectives, an ESD protection circuit is connected to an input/output pad, which is formed on a semiconductor substrate. The semiconductor substrate is lightly doped with a material of a first conductivity type and connected to the ground reference potential. A plurality of drains of multiple MOS FET""s is formed within the surface of the semiconductor substrate from heavily doped diffusions of a material of a second conductivity type. The plurality of drains are each connected to the input/output pad. Further, a plurality of sources of the multiple MOS FET""s is formed within the surface of the semiconductor substrate from heavily doped diffusions of the material of the second conductivity type. The heavily doped diffusions of the plurality of sources are placed at a distance from the plurality of drains within said area of the semiconductor substrate, and are connected to a ground reference potential. Pairs of the plurality of sources are adjacent to each other. A plurality of isolation regions from a heavily doped diffusion of the material of the first conductivity type placed between each source of the pairs of sources. The plurality of isolation regions are allowed to electrically float.
The multiple MOS FET""s have a plurality of parasitic bipolar junction transistors. Each parasitic bipolar junction transistor has an emitter that is one of the sources of one of the multiple MOS FET""s, a collector that is one of the drains of the one MOS FET, and a base that is a region between the source and drain of the one MOS FET.
A plurality of first bulk resistors is formed whereby each first bulk resistor is formed of a bulk resistance of the semiconductor substrate in a region in close proximity to the base of the one of the parasitic bipolar junction transistors and effectively having a first terminal connected to said base. A plurality of second bulk resistors is formed whereby each bulk resistor is formed of the bulk resistance of the semiconductor substrate not composing said first bulk resistors and having a first terminal connected to the effective junction of a second terminal of a pair of the plurality of first bulk resistors and a second terminal connected to the ground reference potential. The first terminals of the pair of first bulk resistors are connected to the bases of two parasitic bipolar junction transistors whose emitters are formed of adjacent sources of the multiple MOS FET""s.
An ESD voltage source such as an electrostatically charged object is made to instantaneously contact to the input/output pad. The voltage of the ESD voltage source is of a magnitude of at least 2,500 volts. When the contacting of the ESD voltage to the input/output pad transfers the voltage of the ESD voltage to the collectors of the plurality of parasitic bipolar junction transistors, the junction formed between the collector of the parasitic bipolar junction transistor and the base of the parasitic bipolar junction transistor enters into avalanche breakdown. The avalanche breakdown generates a large magnitude of holes to pass through the first bulk resistors into the second bulk resistors. The voltage developed across the first bulk resistors and the second bulk resistors is sufficiently large as to cause the base emitter junctions of all the parasitic bipolar junction transistors to start to conduct thus starting all the parasitic bipolar junction transistors to begin to conduct. The conduction of all the parasitic bipolar junction transistors is sufficient to cause the ESD voltage to be discharged thus preventing damage to the internal circuitry.
The input protection circuit has a snapback voltage that is less than 4.7V.