At present, a main type of a semiconductor memory device as represented by a DRAM (Dynamic Random Access Memory) is a synchronous type that inputs and outputs data synchronously with a clock signal. A synchronous DRAM is most widely used as the synchronous semiconductor memory device.
The synchronous DRAM of an early date is an SDR (Single Data Rate) type that inputs and outputs data synchronously with a rising edge of a clock signal. However, in recent years, there is used a DDR (Double Data Rate) synchronous DRAM that inputs and outputs data synchronously with both edges (a rising edge and a falling edge) of a clock signal.
Even in the DDR synchronous DRAM, a latch circuit that operates synchronous with only the rising edge of the clock signal is used so as to latch a command signal and an address signal. That is, a latch circuit according to the SDR system is used with respect to a command signal and an address signal. This is because while data is required to be continuously input and output by a burst operation, a command signal and an address signal do not require a burst operation. It is more advantageous to use the SDR system having a large latch margin.
However, in recent years, along the expansion of an address space following a large density, a number of necessary address terminals increases. Therefore, to decrease the number of address terminals, a method of inputting an address signal twice by dividing this signal by the DDR system is proposed. According to this method, the number of address terminals can be substantially halved.
Japanese Patent Application Laid-open No. 2000-182399 discloses a semiconductor memory device that can change between the SDR system operation and the DDR system operation.
However, when the address signal is input by the DDR system, a latch margin decreases substantially from the conventional margin. Therefore, an input timing of the address signal needs to be fine adjusted, just as an input and output timing of data needs to be fine adjusted. However, to perform this timing adjustment, a mode signal needs to be supplied from the address terminal after entering to a mode register set (MRS) by a predetermined command being issued. Accordingly, depending on a deviation of latch timing, it becomes difficult to correctly latch the mode signal itself. In this case, adjustment cannot be performed.