Usually the manufacture of a junction field effect transistor (JFET) follows an established routine of forming a drain, a source, and a gate on the surface of a semiconductor substrate or, in the case of a compound semiconductor JFET, on the surface of a semi-insulating substrate. Metallic ohmic contacts generally are used for the drain and source electrodes whereas a rectifying junction barrier contact is selected for the gate electrode. It has been found to be desirable to manufacture JFETs to have a short diffused gate junction and low electrical resistance between the source and the drain. Another design feature is to have the device structure be compatible with the conventional self-aligned gate structure and by applying the technique which can be inferred from the schematic depiction of FIG. 1.
A source contact and drain contact on mesa isolation MI on a semi-insulating indium phosphide substrate SI is fabricated with a self-aligned source and drain as depicted. However, this conventional fabrication technique creates the disadvantageous opened junction OJ between the gate and the substrate, as shown in FIG. 2. This is created when the laminated structure of FIG.3 used in the construction of a self-aligned gate junction field effect transistor has a gate junction between opposite type semiconductors formed on an active channel layer by diffusion, or implantation, or epitaxial growth techniques. Following this formation, the gate metal is defined and used as a mask to etch away the unwanted semiconductor, in this case the p.sup.+ InP layer which was previously, uniformly layered across the active n InP channel, see FIG. 4A.
Noting FIG. 4B, the source and drain contacts were deposited. However, the etching technique which is used to etch away the unwanted semiconductor layer p.sup.+ InP still left an open-junction OJ between two different types of semiconductor which results in a poor performing transistor with respect to objectional capacitance, resistance and leakage current.
In other words, the conventional structure according to the technique of FIG. 1 et seq. has the disadvantage of creating an opened-junction, OJ, between the gate and the substrate which has been discovered to tend to create a large leakage current which inherently degrades the performance of the conventionally fabricated JFETs.
Thus, a continuing need exists in the state of the art for a method of making a JFET which assures that the JFET has a high transconductance, low capacitance, with low leakage to enable its satisfactory use in microwave, millimeter-wave and optoelectronic circuits.