This invention relates to the field of integrated circuits including high-speed amplifiers and their offset- and gain-calibration, in one embodiment high-speed variable gain amplifiers with adjustable gain.
High-speed amplifier circuits are used for amplifying the amplitude of signals. A variable gain amplifier (VGA) varies its gain depending on a control signal. To enable precise gains the endpoints of the gain curve are usually controlled to a high accuracy. This can be established for example by using a first control voltage to adjust the minimum gain and a second control voltage to control a maximum gain. Such high-speed amplifier circuits with variable gain can be used for example in read-circuits for computer hard disk drives.
When using VGAs with high frequencies there is limited bandwidth, wherein the bandwidth limitations become more stringent with increasing frequency due to increasing number of parasitic poles affecting the transfer function. VGA implementations in low speed applications are often based on a closed-loop approach wherein the gain is determined by the feedback ratio, e.g., using resistors in the feedback network. This feedback network includes parasitic poles that limit the maximum achievable bandwidth for stable operation. Such, at high operating frequencies, this technique suffers limited open-loop bandwidth and therefore limited closed-loop bandwidth. VGAs for extreme high speed applications are hence typically based on an open-loop approach that requires additional measures to enable a well controlled gain.
FIG. 1 illustrates a schematic circuit of a conventional high-speed amplification circuit 100. Basically the input signal to be amplified is fed into the circuit as a differential signal, i.e. with a positive component Vin_P and negative component Vin_N. The signal components are fed into a variable gain amplifier (VGA) 110 to produce an output signal, wherein the output signal may include a positive signal component Vout_P and a negative signal component Vout_N accordingly. The actual gain of the VGA can be adjusted by providing a control signal such as a voltage Vtune_max, which defines the maximum gain, and a second voltage Vtune_min for defining the minimum gain.
As illustrated in FIG. 1, an example for that extra gain-control circuitry is a parallel implementation (or more than one) 160, 161, of the open-loop amplifier 110 which is set to operate at required gain (or on more than one gain, e.g., maximum or minimum gain). These replica circuits 160, 161 are complimented by low-speed error amplifiers 180, 181 that are used to adjust gain setting tuning signals. Tuning signals can be e.g., voltages driving gain setting devices of the amplifiers into the desired operating state. In these conventional implementations considerable effort is necessary for adjusting a desired minimum and maximum gain. Furthermore components in these circuits are non-ideal, so that they may introduce parasitic effects, like offsets, into the gain control circuit that degrades the achievable gain accuracy. These parameters may also vary with temperature during operation.
Typically the VGA 110, 160, 161 can be composed of a set of transistors (either MOS or bipolar type or both) which may add an offset-voltage to the amplified output voltages Vout_P and Vout_N. The VGA 110 offers an input for a signal in order to compensate the offset-voltage, i.e. a control signal Offset_comp can be fed into the VGA for compensation.
Two methods are known to deduce the control signal Offset_comp. If the averaged input signals Vin_P and Vin_N are zero, then a low-pass filter can be coupled to the output for this purpose. Low frequency or direct voltage (DC) will pass the low pass filter, whereas a high frequency output signal will be blocked. In this way an offset compensation signal, e.g., a current or a voltage, can be derived based on the DC component at the output of the low-pass filter that serves as control signal for adjusting the offset of the VGA to zero. A drawback of this method is the long settling time for adjusting the control signal due to the required low cut-off frequency of the low-pass filter. The alternative as illustrated in FIG. 1 can be implemented.
In this alternative embodiment, the input signal, i.e. Vin_P and Vin_N, can be decoupled from the VGA for example by switches 120, and the input terminals of VGA 110 can be shorted by switch 130. The short of the input terminals enforces a zero signal at the input terminals of VGA 110. Ideally the output signal should be zero, i.e. there should be no voltage between the output terminals. Auto-zero block 140, which is connected to the output terminals of the VGA, generates a control signal Offset_comp fed into VGA 110, typically a control voltage, in order to compensate any offset voltage at the output of the VGA. As in this auto-zero calibration interval there is no input signal fed into the VGA, the time for settling the control voltage Offset_comp has to be short to minimize the duration of the auto-zero phase. In one form the auto-zero block 140 can be implemented as an OpAmp operating in closed-loop and settling the output offset of the VGA 110 to zero by generating a control signal Offset_comp accordingly. The value of signal Offset_comp can be stored on analog hold circuits, e.g., capacitors. Analogue elements such as capacitors simply loose their charge, so that the auto-zero interval must be repeated regularly to adjust the value of Offset_comp. Due to the non-ideal nature of the components their characteristics may change for example depending on temperature. Repetitive auto-zero phases will cope for these variations. Alternatively, a successive approximation approach can be used instead of a OpAmp including a comparator, a Digital-to-Analog Converter (DAC) and some control logic. Such the signal Offset_comp is static after the DAC is settled to the required output value. This relaxes hold circuit requirements but does not remove the requirement for updates of the signal Offset_comp to cope for variations of the VGA output offset. Furthermore, a more sophisticated control structure has to be applied, e.g., by providing proper clock signals to the DAC, comparator and local control logic.
For generating the gain control signals, for example control voltages, to adjust the minimum gain and the maximum gain of the VGA the circuit of FIG. 1 includes a tuning voltage generator 150 as encircled by the dotted square. On the left hand side the tuning voltage generator 150 includes a first circuit portion generating a control signal Vtune_max for adjusting the maximum gain of VGA 110 and on its right hand side a second, identical circuit portion generating control signal Vtune_min for adjusting the minimum gain of the VGA 110. As these circuit portions include identical elements and are operated the same way, the following description relates to both of them.
The circuit portions are arranged outside of the signal path of the input signal to be processed and are nearly replicas of the VGA 110 in the signal path. The desired control signals Vtune_max and Vtune_min can be tuned in by providing a low reference voltage 150 to the input of the circuit portion generating the maximum gain control signal and by providing a high reference voltage 151 respectively to the input the circuit portion generating the low gain control signal respectively, and by comparing the output signal to a target value. This can be achieved with a voltage divider 170, 171 and a following operational amplifier 180, 181, which tunes in the desired control signal Vtune_max or Vtune_min. The voltage divider, e.g., operating in a differential manner, divides a first input voltage buffered from the VGA output and second input voltage buffered from the reference voltage applied to the VGA input. The resulting mid-voltages Verr and Vε will be zero if the ratio of these two voltages matches the ratio of the resistors in the voltage divider, which defines the gain.
For example, in case of the circuit portion generating the Vtune_max control signal, the lower voltage portion of divider 170 is coupled to the input of VGA 160 and thus to the low reference voltage Vref_L. If the output voltage of VGA 160 does not match the desired gain value and consequently does not output the desired voltage, then voltage divider 170 outputs an error signal Verr, which is fed into amplifier 180. Operational amplifier 180 outputs a corresponding signal, which is used as a control signal for adjusting the gain of VGA 160. As this VGA 160 is a replica of VGA 110, the control signal output from amplifier 180 can be used as a control signal for VGA 110.
Regarding the circuit portion generating the control signal for the minimum gain adjustment of VGA 110, the higher voltage portion of divider 171 is coupled to the reference voltage Vref_H. In analogy to the first circuit portion the control signal output from amplifier 181 can be used as control signal Vtune_min for adjusting the minimum gain value of VGA110.
In this way VGAs 160 and 161 comprised in the circuit portions emulate VGA 110 in order to generate the control signals Vtune_max and Vtune_min.
Offset voltages in the replicas as well as in the residual elements of the circuit portions have impact on generating the desired control signals Vtune_min and Vtune_max, in particular when generating high gain control signals. This is even tightened by designing the elements, i.e. transistors and resistors, in the amplification circuits as small as possible to minimize parasitic capacitances in order to achieve high bandwidths. Thus the elements are designed on small areas, which causes high offset voltages in comparison to the input signal voltage due to the imperfections of processing technologies.
For achieving control voltages the Vtune_max and Vtune_min the VGAs 160, 161 in most cases are exact copies of VGA 110 in the signal path.
The offset voltages of each circuit portion can be minimized by using chopper methods. For this purpose the replica circuits include switches 190 to 195 to cross-couple the input lines of the reference voltages Vref_L, Vref_H and to cross-couple the output voltages of the VGAs 160, 161 according to a chopper clock signal generated by a conventional clock signal generator 1100. As illustrated switches 190 to 195 are coupled to the chopper clock signal. According to the toggling chopper clock signal each of the switches 190 to 195 swaps the polarity of its output. Consequently the polarity of the input and output voltages of VGAs 160 and 161 toggle their polarity, and wherein buffers 1110 to 1113 buffer the voltages when toggling the signals. The output signals of the VGAs 160 and 161 and the reference voltages Vref_L and Vref_H, which are coupled to the input of VGAs 160 and 161, are toggled accordingly by switches 192 to 195, such that the input voltage of the dividers are not toggled.
Any offset voltage introduced by VGAs 160 and 161, which is the same throughout a chopper cycle, is thus modulated according to the chopper clock and adds to the error voltage Verr at the input of the amplifiers 180 and 181 respectively. The feedback loop also reflects the toggling in that the control signals Vtune_max_chop and Vtune_min_chop include an alternating component having the frequency of the chopper signal. As the alternating component must be removed before the output signals of the circuit portions are coupled to VGA 110, each of the circuit portions includes a low-pass filter 1120, 1121 removing the alternating component, such that the control signals Vtune_max and Vtune_min do not include an alternating component. This additional filtering increases the settling time of the control signals after powering up the entire circuit. If circuit 100 will be powered on and off regularly then it may become necessary to keep the circuit portions including the replica VGAs 160 and 161 powered on in order to avoid a long settling time after each power up, but which increases dissipation loss.
Another disadvantage of this circuit results from the fact that the circuit operates only as long as there is a linear correlation between the control signals and the gain of the VGAs. Usually this is the case within a limited range around an actual operating point, whereas large offset voltages result in a non-linear change of the control voltages, which causes different control voltages in the intervals of the chopper clock signal. This non-linearity cannot be removed by simply low-pass filtering the control signals, which thus causes distortions in the gain values of VGA 110. Additional effort has to be taken to avoid these effects, for example by integrating the error voltage Verr in the amplifiers 180 and 181 in order to reduce the amplitude of the swing of the control signal and thus to maintain a linear operation.
Also there are differences between VGA 110 and replica circuits VGAs 160, 161 by which a false error voltage Verr can be generated. As the bandwidth of an amplifier depends on the temperature and other factors there will be always a difference between VGA 110 and its replicas.
Due to the replica circuit portions, the auto-zero block 140 including switches 120, 130 the prior art circuit 100 consumes a large area on a chip, consumes much energy and is prone to gain deviations caused by varying temperature and production variations.
Hence there is a need for a new circuit for controlling the amplification of an input signal.
For these and other reasons, there is a need for the present invention.