In the manufacture of a known resistive random-access memory (RRAM, ReRAM or memristor) device a switching layer, typically a transition metal oxide is positioned between a top electrode and bottom electrode. The bulk switching layer is initially non-conducting. By applying a sufficiently large voltage (a “forming voltage”) across the top and bottom electrodes, haphazard conduction path(s) can be formed within the bulk switching layer. The forming voltage, which generally depends on material quality and thickness of the switching layer(s), can equal the breakdown voltage and can range from a few volts to tens of volts. Once the conduction paths are formed, they may be reset (broken, resulting in higher resistance) or set (re-formed, resulting in lower resistance) by an appropriately applied voltage (the “switching voltage”). The forming process and the haphazard nature of the path for the charged species to migrate under an applied electric field are not desirable features for large-scale memory/computing arrays for system applications.
Significant variations are often observed in current and voltage characteristics of the known RRAM. Such variations include both variations in switching voltage and variations in the resistivity of the states (high resistance state (HRS) and low resistance state (LRS). The variations are often exhibited between different RRAM devices within the same chip. The variations are highly undesirable from a system point of view, as an algorithm and possibly equipment need to be developed to interrogate each memory to determine its operating point dynamically for a single memory element. Further, changes in switching characteristics can occur for a given device over a period of time. Such changes over time of the switching characteristics are additionally troublesome since they may contribute to errors later during the life cycle of the device.
The subject matter claimed herein is not limited to embodiments that solve any specific disadvantages or that operate only in environments such as those described above. Rather, this background is only provided to illustrate one exemplary technology area where some embodiments described herein may be practiced.