1. Technical Field
The present disclosure relates to measurement of stress in a semiconductor circuit, and more particularly to a stress detection circuit, a semiconductor circuit including the stress detection circuit, and a method of detecting stress in semiconductor circuits.
2. Discussion of the Related Art
As a scale of semiconductor devices is reduced, integration of semiconductor devices becomes more difficult. When a high voltage is applied between a gate and a body of a metal oxide semiconductor (MOS) transistor, a high electric field is formed in a dielectric film between the gate and the body. Also, the high electric field may be formed when the high voltage is applied between the source and the drain of a MOS transistor.
Defects may be caused in the dielectric film and the body of the MOS transistor due to the aforementioned high electric field, and these defects could change the characteristics of the MOS transistor such as a threshold voltage. Even when a transistor operates at a relatively low voltage, the characteristics such as the threshold voltage may be altered by repeated application of the voltage.
When transistor characteristics such as a threshold voltage are changed due to a high operation voltage or repeated application of a voltage, a transistor or a function block including the transistor is referred to as “being stressed” or “being degraded”.
FIG. 1 is a circuit diagram illustrating an example of a function block in a semiconductor device.
A function block 10 illustrated in FIG. 1 is an example of a driver included in a row selection circuit of a semiconductor memory device. The function block 10 includes transistors TR1, TR2, and TR3 serially coupled between a high voltage VPP and a ground voltage. The function block 10 generates a word line enable signal NWEi that is selectively activated in response to a bit signal ADDi and the high voltage VPP applied to gates of the transistors TR1, TR2, and TR3. The bit signal ADDi is a signal decoded from an address signal. When the word line enable signal NWEi is activated to near the high voltage VPP, a corresponding word line is enabled.
When the transistors TR1, TR2, and TR3 have been stressed by repeated application of the voltages, a level of the word line enable signal NWEi is decreased, and thus a memory cell transistor (not shown) coupled to the corresponding word line may not be fully turned on, thereby degrading the performance of the entire semiconductor memory device.
Since the performance of an entire system may be affected by variation of the characteristics of some function blocks due to such stress, the stress of the function blocks needs to be tested before and after the packaging of semiconductor chips. That is, after a semiconductor chip including a function block sensitive to stress is manufactured, a burn-in test is performed under high temperature, high voltage, and high pressure conditions for measuring variation of the characteristics of the semiconductor chip due to stress. Such burn-in test may cause additional and excessive stress on the semiconductor chip, thereby unnecessarily reducing the lifetime of the semiconductor chip.