As known, solid state signal memory devices provide interim storage of electronic signal data, e.g. digital signal data. The signals are stored within the memory at various address locations which are identified to allow later data retrieval. In volatile memories, the stored information is preserved only in the presence of applied electrical power. The memory contents are lost in the absence of power. Alternatively, nonvolatile memories maintain the stored signal characters even in the absence of applied power; at least for a specified duration.
Alterable nonvolatile memories, i.e. those in which new data may be written over old data, have been used extensively in avionic, digital flight data recording systems (DFDRS) for storing protected flight parameter data. Typical of the DFDRS nonvolatile memories are the electrically alterable read only memory (EAROM) and the electrically erasable programmable read only memory (EEPROM) devices. Both allow stored data to be written over in situ and both preserve the stored data throughout power interruptions. The data writing process involves the sequence of first erasing the entire former data unit (e.g. word, byte or nibble) and then entering the new data at the same address. Erasing is required due to the physical properties of the materials involved and the memory's designed operating system.
For DFDRS systems which are used for post-accident (incident) analysis the memory unit must be crash survivable. This is accomplished by having the memory encased in an armored housing which results in accelerated operating temperatures on the order of 125.degree. C. As a result the DFDRS memory devices are write cycle limited in the number of data writing entries which may be made at any one address location. Exceeding this limit may result in a "burnout" of that location, which results in a loss in the memory's abiity to store the information intact throughout a power interruption. Device manufacturers specify a maximum number of write cycles, on the order of 10.sup.4, which establishes the upper limit over which the statistical probability of failure of the memory device is defined.
Another performance limitation imposed by the severe DFDRS operating environment is that the memories have long write time cycles. It takes a longer time to write data into memory. System power loss during a write-in is common. Each power loss during write-in results in loss of the frame of data which was in the process of being written in when the power interruption occurred, together with loss of signal frame synchronization. This causes the system to search for the last recognized synch pattern, which may further result in discarding one or more additional frames of stored data before synchronization is again established. The result is a non-recoverable gap in the real time data recording sequence for the stored parameter time history.