The present invention relates to a semiconductor integrated circuit and, more particularly, to a hybrid semiconductor integrated circuit in which semiconductor elements are isolated by the trench isolation method, and analog and digital circuits are formed on a single chip.
The trench isolation method is a known conventional method of isolating semiconductor elements. Using the trench isolation method, a vertical trench is formed on a semiconductor substrate by reactive ion etching (to be referred to as RIE hereinafter), a dielectric (insulation material) is selectively left in this trench, thereby utilizing it for element isolation.
Using the trench isolation method, a trench having a small pattern transfer difference can be formed at an arbitrary depth. Since a dielectric is filled into the trench, the parasitic capacitance is decreased as compared with other p-n junction isolation methods. For this reason, trench isolation is widely used for VLSIs.
However, when transistors are isolated by use of the trench isolation method, they are completely isolated from each other. Thus, in the case of a bipolar semiconductor integrated circuit which requires an electrode for providing a reference voltage to be formed on the lower surface of a chip, an integrated injection logic circuit (hereinafter referred to as an I.sup.2 L circuit), which is a digital circuit, cannot be formed on a single chip.
The reason the I.sup.2 L circuit cannot be formed is that the emitters of vertical transistors, each of which uses an n-type conductive buried layer, are completely isolated from each other. Particularly in the case where analog and digital circuits are formed together on a single chip, the above-described situation presents serious problem.
Thus, a conventional I.sup.2 L circuit is arranged by leading electrodes from the emitters of the respective transistors, to connect them each other by way of lines. Elements, however, cannot be micropatterned by such a method.