In recent years, circuits of a digital information device such as a personal computer or a portable information terminal such as a cellular phone run at extremely high speed because of technological advances in performance and function. If the clock speed rises over several hundred MHz, it becomes difficult to substantially suppress noise (high-frequency oscillation) that leaks from LSI to a power wiring of a printed circuit board by using only conventional laminated ceramic capacitor and three-terminal capacitor, increasing the likelihood that malfunction or radio disturbance would occur due to an increase in noise. As a capacitive element that can deal with the above problem, the applicant(s) has already proposed a strip-line-type element (for example, see Patent Documents 1 and 2).
FIG. 1 is a plain view of a strip-line-type element disclosed in Patent Document 1. FIG. 2 is a cross-sectional view of FIG. 1 taken along the line P-P. As shown in FIGS. 1 and 2, on the surface of a metal plate 10 made of aluminum, a dielectric film 20 made of an oxide compound is formed. On the dielectric film 20, a conductive layer 30 including a conductive polymer layer 31, a conductive carbon paste layer 32, and a silver paste layer 33 is formed. To both ends of the longitudinal direction of the metal plate 10, anode outgoing terminals 11 and 12 are connected. On one surface of the conductive layer 30, metal plates 40 that are copper foil are piled up. Both ends of the longitudinal direction of the metal plate 40 are cathode outgoing terminals 41 and 42.
Moreover, a technique to separate a power layer and dispose a capacitive element is disclosed in Patent Documents 3 to 8.
FIGS. 3A and 3B shows a printed wiring board disclosed in Patent Document 6. FIG. 3A is a plain view. FIG. 3B is a cross-sectional view of FIG. 3A taken along the line A-A′. The printed wiring board 50 includes 6 layers: a power layer 59, a ground layer 60, and signal layers 61 to 64. Immediately under LSI 51, the power layer 59 is divided by a moat 54 into a peripheral power source 65 and an island power source 66 which are electrically connected by inductances 55, 56, 57, and 58. The layers between the power source 66 and the ground layer 60 are electrically connected by capacitors 67 and 68.    Patent Document 1: JP-A-2003-101311    Patent Document 2: JP-A-2003-124066    Patent Document 3: JP-A-2005-033813    Patent Document 4: JP-A-2002-368355    Patent Document 5: JP-A-2001-332825    Patent Document 6: JP-A-2001-274558    Patent Document 7: JP-A-2001-267702    Patent Document 8: JP-A-11-087880