Latency shifters may be used, for example in memory devices, to delay a signal, such as a command signal. A number of flip-flops in a shifter circuit may be selected to delay a signal a desired amount of clock cycles.
FIG. 4A and FIG. 4B are schematic illustrations of apparatuses arranged in accordance with conventional techniques. FIG. 4A and FIG. 4B both include clock generator 202, command decoder 204, DQ system 208, and DQs 210 which may be similar components to those with the same reference number described with reference to FIG. 2. FIG. 4A includes latency shifter 402 and FIG. 4B includes latency shifter 404. The latency shifter 402 of FIG. 4A provides a line of flip-flops between the input and the output of the latency shifter 402. The output along the line of flip-flops may be selected by selecting an appropriate “short cut” to route the signal out of a particular register as the output signal. The latency shifter 404 of FIG. 4B provides multiple lines of flip-flops between the input and the output of the latency shifter 404—each having a different length. An amount of delay may be selected by selecting which line of flip-flops to route the input signal through. Note that, in both latency shifter 402 and latency shifter 404, the last flip-flop a signal may pass through may be different depending on how much delay is provided. The latency shifter 402 and latency shifter 404 both receive an input signal (e.g., CMDin) at a left side of the shifter and provide an output signal (e.g., CMDout) at a right side of the shifter at an opposite end of a line of flip flops which extend from the input to the output. In this manner, the input and output flip flop may be located some distance from one another.
In conventional examples, a signal may be passed through a different number of selectors (e.g., multiplexers) depending on a number of flip-flops selected, which may result in a speed difference based on how much delay is selected. In some conventional examples, gate and wiring capacitances at the contact point of the input signal to be provided to all flip-flops in the shifter may be undesirably large.
In some conventional examples, drivers of clocks for the respective flip-flop groups may be arranged in such a way that parasitic capacitances may increase charge/discharge currents undesirably.