(1) Field of the Invention
The present invention relates to a semiconductor device, in particular, a high withstand voltage MOS transistor of a LOCOS (Local Oxidation of Silicon) offset drain type having a buried layer, and a method of manufacture thereof.
(2) Description of the Related Art
Occasionally, a MOS field effect transistor (MOSFET) in a motor driven/controlled integrated circuit or the like is used in such a manner that a high voltage of, for example, more than several tens of volts is applied to a drain region.
As a type of such high withstand voltage MOS transistor, there is known a LOCOS offset drain type in which an offset layer with a relatively low concentration is provided around a drain layer with a high concentration formed on a surface of a semiconductor substrate in order to secure a drain withstand voltage.
However, a vertical parasitic bipolar transistor disadvantageously operates in this structure, thereby leading to an erroneous operation of circuitry in some cases. In order to avoid this disadvantage, there is proposed a high withstand voltage MOS transistor having a buried layer (refer to, e.g., JP60-020560A).
FIG. 18 illustrates a conventional high withstand voltage MOS transistor of a LOCOS offset drain type having a P-type channel.
This semiconductor device has the following structure. That is, a LOCOS oxide film 205 is formed between a P+-type high concentration drain layer 208A and an end of a gate electrode 207 made of polysilicon such that the end of the gate electrode 207 is offset from the P+-type high concentration drain layer 208A serving as a drain region. This prevents an electric field from being concentrated on the end of the gate electrode 207.
In addition, a P-type offset layer 204 of a conductivity type equal to that of the drain region is formed below the LOCOS oxide film 205. The P-type offset layer 204 has an impurity concentration lower than that of the P+-type high concentration drain layer 208A. Further, an N+-type buried layer 202 is formed for controlling an operation of a vertical parasitic PNP bipolar transistor having a P+-type high concentration source layer 208B (or the P+-type high concentration drain layer 208A) serving as an emitter, an N−-type epitaxial layer 203 serving as a base and a P−-type silicon substrate 201 serving as a collector. Herein, a gate oxide film 206 is also illustrated in FIG. 18.
By formation of the N+-type buried layer 202, the vertical parasitic PNP bipolar transistor having the P+-type high concentration source layer 208B (or the P+-type high concentration drain layer 208A) serving as an emitter, the N−-type epitaxial layer 203 serving as a base and the P−-type silicon substrate 201 serving as a collector is allowed to have a high concentration (of the N−-type epitaxial layer 203). Thus, it is possible to suppress a parasitic operation.
However, this conventional technique has the following problems.
In a conventional high withstand voltage MOS transistor of a LOCOS offset drain type having a P-type channel, a depletion layer from a P+-type drain layer reaches an N+-type buried layer with a high concentration and the depletion layer is difficult to extend, so that an electric field is concentrated on a portion between the P+-type drain layer and the N+-type buried layer. Accordingly, a withstand voltage is determined.
In order to solve the above problem, even if a distance between a drain and a source is widened, a concentration profile of an offset layer is optimized, or a buffer layer is formed between a drain layer and an offset layer such that a lateral electric field is relaxed, it is difficult to improve a withstand voltage.
In order to improve a withstand voltage, it is necessary to improve a withstand voltage between a P+-type drain layer and an N+-type buried layer in the following manner. A film thickness of an epitaxial layer is made large or a concentration of the epitaxial layer is made high such that a depletion layer is prevented from reaching a buried layer. Alternatively, a concentration of the buried layer is made low such that the depletion layer extends into the buried layer.
However, if the film thickness of the epitaxial layer is made large, an isolation layer must be diffused deeper in a case where element isolation is achieved by PN junction isolation. Consequently, an element area is increased due to widening of lateral diffusion. Further, if the concentration of the epitaxial layer is made high, occasionally, a withstand voltage is reduced or on-resistance is increased depending on a relationship in concentration between the epitaxial layer and a P-type offset layer or a P+-type drain layer. Moreover, if the concentration of the buried layer is made low, a concentration of a base layer in a vertical parasitic bipolar transistor becomes low, so that an operation of a parasitic bipolar transistor is increased.
Due to the aforementioned problems, it is difficult to improve a withstand voltage, reduce on-resistance and suppress an operation of a parasitic bipolar transistor simultaneously without an increase in element area.