a) Field of the Invention
This invention relates to a semiconductor device and its manufacture method, and more particularly to techniques of forming a semiconductor device which requires impurity diffusion regions having different impurity profiles on the same substrate. For example, such a device has a high speed transistor having a fine gate capable of high speed operation and a high voltage transistor.
b) Description of the Related Art
In order to realize a high performance of a semiconductor device with MOS type transistors, it is indispensable to make MOS type transistors very fine. Especially, by shortening the channel length of a MOS type transistor, that is, the gate length, high speed of the semiconductor device can be remarkably improved. To decrease the influence of a so-called, short channel effect when the gate length is shortened, it is preferred to adopt a source drain extension (SDE) structure.
For instance, by forming sidewall spacer films or the like on the side surfaces of a gate electrode after forming the gate electrode, source/drain regions are formed spaced apart from the edges of the gate electrode. Impurity diffusion regions having a shallower junction depth than the source/drain impurity diffusion regions and the same conductivity type as the source/drain diffusion regions are formed in space regions between the gate and source/drain regions. This structure is called an SDE structure. It is called a lightly doped drain (LDD) structure, a medium doped drain (MDD) structure, and a highly doped drain (HDD) structure, and the like, sequentially from the region with a lower impurity concentration in the SDE structure.
The extension region is generally considered as a region having a relatively high impurity concentration. However, in this specification, the term named the SDE structure or SDE region is intended to mean the structure or region having a shallower junction depth than the source/drain impurity diffusion regions and the same conductivity type as the source/drain regions and formed in the space regions, irrespective of whether the impurity concentration is high or low.
For instance, if the gate length of a transistor is set to 50 nm, it is preferred to set the thickness of an impurity diffusion region constituting the SDE structure to about 20 nm to 30 nm (refer to SIA load map, 1999).
For instance, to form an SDE region, after impurity ions are injected in a semiconductor substrate, an ion activation process is performed by using a rapid thermal annealing (RTA) method or a laser thermal process (LTP) method. In the RTA and LTP methods, the speed of the temperature rise and fall is increased from a usual thermal anneal (TA) method. The RTA method will change the temperature of an entire semiconductor substrate in a short time. On the other hand, the LTP method can raise the activation rate of impurities by irradiating a laser beam to the surface of a semiconductor substrate in ultra short time. With the LTP method, it is possible to form near to the semiconductor substrate a junction which is very shallow and has a steeply changing impurity concentration.
If ion implantation and ion activation are used together, it is possible to adjust an impurity concentration, a steepness of the impurity concentration profile in the depth direction, and a thickness of an impurity diffusion region.
There are many cases that a semiconductor integrated circuit device has transistors of different types on the same substrate. For example, high speed transistors (hereinafter called a “high speed transistor”) having a short gate length and operating at a low voltage, e.g., about 1.6 V and transistors (hereinafter called a “high voltage transistor”) constituting an input/output (I/O) circuit and operating at a high voltage, e.g., about 3.3 V, are formed together on the same substrate.
FIG. 9A and FIG. 9B are cross sectional views of two kinds of semiconductor devices having a high speed transistor and a high voltage transistor incorporating the SDE structure and formed on same substrates.
FIG. 9A is a cross sectional view showing the structure suitable for forming a high voltage transistor with SDE regions.
As shown in FIG. 9A, a first region 602 and a second region 603 are defined in a p-type silicon substrate 600 by an element isolation region 600a. In the first region 602, a high speed transistor with a short gate length is formed. A first gate electrode 606 of the high speed transistor is formed on a gate insulating film 604 formed on the p-type silicon substrate 600. A high voltage transistor with a long gate length is formed in the second region 603. A second gate electrode 607 of the high voltage transistor is formed on a gate insulating film 605 formed on the p-type silicon substrate 600.
The high speed transistor and high voltage transistor each have n-type SDE regions 611 extending from the region just under the gate electrode to the outer surface layer of the semiconductor substrate and n-type source/drain regions 610 continuous with the SDE regions 611.
Spacer films 612 are formed on the side surfaces of the first and second gate electrodes 606 and 607. The SDE region 611 is formed in the surface layer of the semiconductor substrate just under the spacer film 612.
A metal silicide layer 613 such as CoSi may be formed on the upper surfaces of the first and second gate electrodes 606 and 607 and source/drain regions 610. If the metal silicide layer 613 is formed, the sheet resistances of the gate electrode and source/drain regions lower.
In order to prevent on-current from being reduced by hot carriers, it is preferable to form the SDE region of the high voltage transistor so that the p-n junction between the n-type SDE region 611 and underlying p-type semiconductor region (or p-type silicon substrate) 600 has a gentle gradient of n-type impurity concentration.
However, if the SDE region of the high speed transistor with a short gate length has also the gentle gradient of the impurity concentration, the short channel effect becomes remarkable.
FIG. 9B is a cross sectional view showing the structure suitable for forming a high speed transistor with SDE regions. In FIG. 9B, like constituent elements to those shown in FIG. 9A are represented by reference numerals obtained by adding 100 to the numerals shown in FIG. 9A, and the description thereof is omitted.
In the structure shown in FIG. 9B, a first region 702 and a second region 703 are defined in a p-type silicon substrate 700. In these regions 702 and 703, n-type SDE regions 711 are formed having the same structure for both the high speed and high voltage transistors.
In order to make the SDE region 711 suitable for a high speed transistor, i.e., to improve high speed operation (reduce the source resistance) and suppress the short channel effect, the SDE region 711 is formed in such a manner that the n-type impurity concentration is high and that the p-n junction between the n-type SDE region 711 and p-type semiconductor region (or p-type silicon substrate) 700 has a gentle gradient of the n-type impurity concentration.
However, if the SDE region of the high voltage transistor is also formed, the p-n junction has a steep change in the n-type impurity concentration and the on-current (Ion) of the transistor lowers by hot carriers. Namely, if the transistor is driven at a high voltage, the electric field under the gate insulating film (at the edge of the drain) becomes large. A large number of hot carriers are therefore generated and the on-current lowers. In order to mitigate the influence of the electric field, it is necessary to device the SDE structure.
In the case of a resistor element made of an n-type impurity diffusion region in a semiconductor substrate with a high speed transistor, if the p-n junction between the n-type resistor element and underlying p-type semiconductor region (or p-type silicon substrate) has a steep impurity concentration gradient, leak current to the substrate increases.