I. Field of the Invention
The present invention relates to computer architecture, and more particularly, to a personal computer architecture having a high performance video subsystem.
II. Related Art
In conventional personal computer (PC) architectures, the central processing unit (CPU), main memory, and other peripheral input/output (I/0) devices, such as keyboards, printers, disk drives, and video subsystems, are commonly interfaced by way of a bus network having a host bus and a system bus. The system bus connects to the host bus via buffers and is generally slower than the host bus. The dual bus network is implemented partially because it was realized early on that most of a PC's time is utilized during computation or during the movement of data between the CPU and the main memory. Consequently, the CPU and the main memory are situated on the faster host bus, while the video subsystem as well as other peripheral I/O devices with varying clock speeds are usually connected to the slower system bus. In this configuration, the main memory is sometimes called the "host" memory because it connects to the architecture via the host bus.
The rationale for interfacing the video subsystem to the system bus is that the video subsystem in the PC industry has been historically considered a noncritical computer subsystem as far as performance is concerned. Performance in this context refers to the speed at which a video display can be updated. More specifically, performance is related to the operational bandwidth that is available to the central processing unit when communicating with the video subsystem.
The rationale for considering the video subsystem a noncritical computer subsystem was originally well founded. Initially, video subsystems drove very low resolution displays in the PC industry and, therefore, did not need to handle high speed block transfers of data. Furthermore, customers were using video displays primarily for very low end graphics applications. Hence, performance was just not a major issue.
As a consequence of the rapidly evolving PC industry, high end PCs have migrated into workstation applications, such as high performance Computer Automated Design (CAD) and engineering workstations, where speed is an extremely critical factor. A demand exists in the marketplace for video subsystems which can drive higher resolution displays with more colors and with three-dimensional capabilities. Video subsystems are being developed to far surpass the performance of previous designs. As originally defined by IBM, a video graphics array (VGA) had 16 colors with a picture element (pixel) resolution of 640 by 480. The new Super VGA standard increases the previous video standard resolution to 1024 by 768 pixels, requiring a very high speed video subsystem.
The usual connection of the video subsystem to the system bus along with other peripheral I/O devices, does not adequately meet the high data block transfer rates needed for the high performance video subsystems. When a peripheral device like a video subsystem wishes to perform a transaction on the system bus, the system bus usually has only a few time slots available, or cycle times, partially because of arbitration protocols. When the video subsystem attempts to retrieve data from the system bus, the access time is lengthened by wait states.
Until the present invention, no PC architecture in the marketplace or elsewhere has interfaced the video subsystem to a high speed, 32-bit or 16-bit host bus in order to achieve high speed data transfers to the video subsystem. In this regard, see N. Baran, "EISA Arrives," Byte Magazine, v. 14, number 12, November 1989 (cover story), which is incorporated herein by reference.