1. Field of the Invention
The present invention relates to a memory such as a DRAM (dynamic random access memory), and particularly to an X-address extractor and a memory adaptable to a high speed operation.
2. Discussion of Related Art
A DRAM receives an X-address and Y-address through an address line. The X-address is input through a command line when an active command is input to the DRAM, and the Y-address is input when a read/write command is input to the DRAM. The X-address extractor performs a function of extracting the X-address among the X and Y addresses transferred through the address line.
Hereinafter, a conventional X-address extractor will be described with reference to FIGS. 1 and 2.
FIG. 1 is a block diagram of an X-address abstractor according to a conventional art. In FIG. 1, the X-address extractor includes a selection signal generator 10 and an X-address switch 120.
The selection signal generator 110 inputs a command signal CMD and then outputs a selection signal SEL. The command signal CMD is output as the selection signal SEL at rising and falling edges of a clock signal CLK.
The X-address switch 120 receives an address signal ADD and the selection signal SEL and then outputs an X-address signal XADD. When the selection signal SEL is logic ‘1’, the address signal ADD becomes the X-address signal XADD. When the selection signal SEL is logic ‘0’, the address signal ADD retains its previous value.
By such an operation, the X-address extractor extracts the X-address signal XADD from the address signal ADD.
However, as illustrated in FIG. 2, the selection signal SEL is considerably delayed from the command signal CMD because it is operable in sync with the clock signal CLK. As the address signal ADD is transferred to the X-address signal XADD by the selection signal SEL, the X-address signal XADD is much delayed than the address signal ADD. Furthermore, the X-address signal XADD has a different value not the X-address when the selection signal SEL changes to logic ‘0’ from logic ‘1’ after the address signal ADD changes to another value from an X-address. Such a problem should be overcome for an improvement of a high speed DRAM because it would be more serious as the DRAM is improved in a higher speed.