1. Field of the Invention
This invention relates to an input protection circuit for protecting a semiconductor integrated circuit device from the electrostatic breakdown.
2. Description of the Related Art
It is known that the semiconductor integrated circuit device may be electrostatically broken down by the static electricity charged on the human body or the like. Degradation of the characteristic of the semiconductor device, breakdown of the PN junction and dielectric breakdown of the oxide film may be caused by a so-called electrostatic discharge (ESD). Particularly, in recent years, the electrostatic withstanding voltage of the integrated circuit (IC) tends to be lowered as the semiconductor elements are more miniaturized.
A plurality of pads are disposed on the peripheral surface of the ordinary IC chip. The pads include a power source pad to which a power source voltage Vcc is applied, a ground pad which is set at a ground potential Vss and a signal input or output pad. The power source pad is connected to a Vcc wiring, the ground pad is connected to a Vss wiring and the Vcc and Vss wirings are formed to extend to every portion of the chip surface.
In general, an input protection circuit is provided between the signal input pad and the input buffer of the IC to protect the internal elements from breakdown due to the ESD. The input protection circuit used in the conventional semiconductor integrated circuit device is basically constituted by an input protection resistor and an input protection transistor. For example, the signal input pad is connected to one end of the input protection resistor formed of a diffusion layer, polysilicon layer or the like. The other end of the resistor is connected to the emitter of the input protection NPN bipolar transistor and to the input terminal of the input buffer. Further, the collector of the transistor is connected to the ground terminal, and then the resistor and transistor functions as an input protection circuit.
When an N-type semiconductor substrate is used, the input protection NPN bipolar transistor is constructed as follows. That is, a P-well region is formed in the surface area of the semiconductor substrate and first and second N.sup.+ -type impurity regions are separately formed in the P-well region. The first N.sup.+ -type impurity region is connected to the signal input pad via the input protection resistor. The second N.sup.+ -type region is connected to the ground terminal Vss. The transistor is formed to have the first N.sup.+ -type region as an emitter, the second N.sup.+ -type region as a collector and that portion of the P-well region which lies between the first and second N.sup.+ -type regions as a base.
In order to subject the above semiconductor integrated circuit device to the ESD test under the MIL standard, two methods using a Vss reference and a Vcc reference may be available. The ESD test using the Vss reference is effected under a condition that the ground pad of the IC is set at 0 V. In this case, the other pads are set in the electrically floating state. On the other hand, the ESD test using the Vcc reference is effected under a condition that the power source pad of the IC is set at 0 V. In this case, like the ESD test using the Vss reference, the other pads are set in the electrically floating state.
In a case where the conventional semiconductor device having the above input protection circuit is subjected to the ESD test using the Vss reference, an excessively high voltage applied to the signal pad is absorbed into the ground terminal Vss via the protection transistor so that the internal element can be protected from breakdown due to the excessively high voltage. However, in a case where the conventional semiconductor device is subjected to the ESD test using the Vcc reference, there is no path which permits an excessively high voltage applied to the signal pad to be discharged. Therefore, the withstanding voltage with respect to the ESD becomes smaller than in the case of using the Vss reference. When the semiconductor integrated circuit device is actually operated, the ESD may occur in any operating condition of the semiconductor integrated circuit device. Therefore, it is strongly required to enhance the withstanding voltage with respect to the ESD in the case of using the Vcc reference.