In synchronous integrated circuits, the integrated circuit is clocked by an external clock signal and performs operations at predetermined times relative the rising and falling edges of the applied clock signal. Examples of synchronous integrated circuits include synchronous memory devices such as synchronous dynamic random access memories (SDRAMs), synchronous static random access memories (SSRAMs), and packetized memories like SLDRAMs and RDRAMs, and include other types of integrated circuits as well, such as microprocessors. The timing of signals external to a synchronous memory device is determined by the external clock signal, and operations within the memory device typically must be synchronized to external operations. For example, commands are placed on a command bus of the memory device in synchronism with the external clock signal, and the memory device must latch these commands at the proper times to successfully capture the commands. To latch the applied commands, an internal clock signal is developed in response to the external clock signal, and is typically applied to latches contained in the memory device to thereby clock the commands into the latches. The internal clock signal and external clock must be synchronized to ensure the internal clock signal clocks the latches at the proper times to successfully capture the commands.
In the present description, “external” is used to refer to signals and operations outside of the memory device, and “internal” to refer to signals and operations within the memory device. Moreover, although the present description is directed to synchronous memory devices, the principles described herein are equally applicable to other types of synchronous integrated circuits.
Internal circuitry in the memory device that generates the internal clock signal necessarily introduces some time delay, causing the internal clock signal to be phase shifted relative to the external clock signal. As long as the phase-shift is minimal, timing within the memory device can be easily synchronized to the external timing. To increase the rate at which commands can be applied and at which data can be transferred to and from the memory device, the frequency of the external clock signal is increased, and in modern synchronous memories the frequency is in excess of 100 MHZ. As the frequency of the external clock signal increases, however, the time delay introduced by the internal circuitry becomes more significant. This is true because as the frequency of the external clock signal increases, the period of the signal decreases and thus even small delays introduced by the internal circuitry correspond to significant phase shifts between the internal and external clock signals. As a result, the commands applied to the memory device may no longer be valid by the time the internal clock signal clocks the latches.
To synchronize external and internal clock signals in modern synchronous memory devices, a number of different approaches have been considered and utilized, including delay-locked loops (DLLs), phased-locked loops (PLLs), and synchronous mirror delays (SMDs), as will be appreciated by those skilled in the art. As used herein, the term synchronized includes signals that are coincident and signals that have a desired delay relative to one another. FIG. 1 is a functional block diagram of a conventional SMD 100 that receives an applied clock signal CLK and generates a synchronized clock signal CLKSYNC in response to the CLK signal, the CLKSYNC signal being synchronized with the CLK signal. The SMD 100 includes an input buffer 102 that receives the CLK signal and generates a buffered clock signal CLKBUF in response to the CLK signal. The CLKBUF signal has a delay D1 relative to the CLK signal, where D1 corresponds to the inherent propagation delay of the input buffer.
A model delay line 104 receives the CLKBUF signal and generates a forward delayed clock signal FDCLK having a model delay D1+D2 relative to the CLKBUF signal. The model delays D1 and D2 simulate the delay D1 introduced by the input buffer 102 and a delay D2 introduced by an output buffer 106 that generates the CLKSYNC signal, as will be explained in more detail below. The FDCLK signal propagates through a forward delay line 108 including a plurality of unit delays 110A-N coupled in series, each unit delay receiving an input signal from the prior unit delay and generating an output signal having a unit delay UD relative to the input signal. Each unit delay 110A-N may, for example, be an inverter as indicated for the unit delay 110A, with the inverter introducing the unit delay UD corresponding to the propagation delay of the inverter. In the forward delay line 104, the FDCLK signal propagates through the unit delays 110A-N from left to right in FIG. 1, as indicated by the orientation of the inverter in the unit delay 110A. The forward delay line 108 includes a plurality of outputs 112A-N, each output 112A-N being coupled to the output from the corresponding unit delay 110A-N, respectively. As the FDCLK signal propagates through the unit delays 110A-N, when the signal is present on a respective output 112A-N the signal is designated a delayed forward clock signal DFDCLK.
A backward delay line 114 includes a plurality of unit delays 116A-N coupled in series as previously described for the forward delay line 108. Instead of providing the outputs from the unit delays 116A-N as with the forward delay line 108, however, the backward delay line 114 has a plurality of inputs 118A-N, each input being coupled to the input of the corresponding unit delay 116A-N, respectively. A mirror controller 120 is coupled to the outputs 112A-N of the forward delay line 108 and the inputs 118A-N of the backward delay line 114. In response to rising-edges of the CLKBUF signal, the mirror controller 120 applies the DFDCLK signal from the corresponding unit delay 110A-N in the forward delay line 108 to the input of the corresponding unit delay 116A-N in the backward delay line 114. For example, if the FDCLK signal has propagated to the output of the unit delay 110J, the mirror controller 120 outputs the DFDCLK signal on the output of the unit delay 110J to the input of the unit delay 116J in the backward delay line 114. The DFDCLK signal propagates through the corresponding unit delay 116A-N in the backward delay line 114 and through all unit delays to the left of that unit delay, and is output from the backward delay line 114 as a delayed clock signal CLKDEL. Thus, in the backward delay line 114, DFDCLK signal propagates through the unit delays 116A-N from right to left in FIG. 1, as indicated by the orientation of the inverter in the unit delay 116A. The output buffer 106 receives the CLKDEL signal and generates the CLKSYNC in response to the CLKDEL signal, with the CLKSYNC being delayed by the delay D2 introduced by the output buffer. As illustrated by a dotted line in FIG. 1, the output buffer 106 may correspond to a data driver that receives a data signal DQX and outputs the data signal in response to being clocked by the CLKDEL signal, as will be appreciated by those skilled in the art.
The overall operation of the SMD 100 in synchronizing the CLKSYNC signal with the CLK signal will now be described in more detail with reference to FIG. 1 and a signal timing diagram of FIG. 2 illustrating various signals generated by the SMD during operation. In the example of FIG. 2, an initial rising-edge of the CLK signal occurs at a time T0. In response to the rising-edge of the CLK signal at the time T0, the input buffer 102 drives the CLKBUF signal high the delay D1 later at a time T1, with this initial rising-edge of the CLKBUF signal being designated the N edge of the CLKBUF signal. In response to the rising-edge transition of the CLKBUF signal at the time T1, the mode delay line 104 drives the FDCLK signal high the model delay D1+D2 later at a time T2. The FDCLK signal thereafter propagates through the unit delays 110A-N in the forward delay line 108 until a next rising-edge N+1 of the CLKBUF signal is applied to the mirror controller 120 at a time T3. At the time T3, the forward delay line 108 has delayed the FDCLK signal by a forward delay FD that equals TCK−(D1+D2) where TCK is the period of the CLK signal. This is true because, as illustrated in FIG. 2, the next rising-edge of the CLKBUF signal occurs TCK−(D1+D2) after the initial rising-edge of the FDCLK signal at the time T2.
In response to the rising-edge of the CLKBUF signal at the time T3, the mirror controller 120 applies the FDCLK signal from the output of the appropriate unit delay 110A-N in the forward delay line 108 to the corresponding input 118A-N of the backward delay line 114. For example, assume that the delay TCK−(D1+D2) equals eleven unit delays UD so that the mirror controller 120 receives the DFDCLK signal from the output 112K of the unit delay 110K in the forward delay line 108. In this situation, the mirror controller 120 applies the DFDCLK signal to the input 118K of the unit delay 116K in the backward delay line 114. This is illustrated in FIG. 2 as a rising-edge of the DFDCLK signal at the time T3.
The DFDCLK signal thereafter propagates through the appropriate unit delays 116A-N in the backward delay line 114, and at a time T4 the backward delay line 114 drives the CLKDEL signal high in response to the applied DFDCLK signal. At the time T4, the backward delay line 114 has delayed the DFDCLK signal by a backward delay BD that equals TCK−(D1+D2) which equals the forward delay FD of the forward delay line 108. This is true because the DFDCLK signal propagates through the same number of unit delays 116A-N in the backward delay line 114 as did the FDCLK signal to the unit delays 110A-N in the forward delay line 108, as will be appreciated by those skilled in the art. The total delay of the CLKDEL signal at the time T4 equals D1+D1+D2+TCK−(D1+D2)+TCK−(D1+D2), which equals 2TCK−D2. Thus, the rising-edge of the CLKDEL signal at the time T4 occurs the delay D2 of the output buffer 106 before a next rising-edge of the CLK signal at a time T5. In response to the CLKDEL signal at the time T4, the output buffer 106 drives the CLKSYNC signal high at the time T5 and in synchronism with the rising-edge of the CLK signal. In this way, the SMD 100 generates the CLKSYNC signal having rising-edges that are synchronized with the rising-edges of the CLK signal.
In the SMD 100, although the input buffer 102 and output buffer 106 are illustrated as single components, each represents all components and the associated delays between the input and output of the SMD 100. The input buffer 106 thus represents the delay D1 of all components between an input that receives the CLK signal and the input to the model delay line 104, and the output buffer 106 represents the delay D2 of all components between the output of the backward delay line 114 and an output at which the CLKSYNC signal is developed, as will be appreciated by those skilled in the art.
In SMD 100, the forward and backward delay lines 108, 114 each include the same number of unit delays 110A-N, 116A-N. A large number of unit delays 110A-N, 116A-N is desirable to provide the SMD 100 with better resolution in generating the forward and backward delays FD, BD, which hereinafter will collectively be referred to as a variable delay VD (i.e., VD=FD+BD). The resolution of the SMD 100 is the smallest increment of delay that can be added and subtracted from the variable delay VD, which equals twice the unit delay UD of the unit delays 110A-N, 116A-N in the SMD 100. Better resolution means the CLK and CLKSYNC signals will be properly synchronized, as will be appreciated by those skilled in the art. In addition, the forward and backward delay lines 108, 114 must be able to collectively provide a maximum variable delay VD corresponding to the CLK signal having the lowest frequency in the frequency range over which the SMD 100 is designed to operate. This is true because the forward and backward delay lines 108, 114 must each provide a delay of TCK−(D1+D2), which will have its largest value when the period TCK of the CLK signal is greatest, which occurs at the lowest frequency of the CLK signal.
One approach that has been utilized to reduce the size and power consumed by the delay lines 108, 114 is illustrated in FIG. 3 which depicts an SMD 300 including a bi-directional delay line 302 for generating the required delay to synchronize a synchronized clock signal CLKSYNC with an applied clock signal CLK. The SMD 300 includes an input buffer 304, a delay line 306, and output buffer 308 that operate in the same way as previously described for the corresponding components in the SMD 100 of FIG. 1, and thus, for the sake of brevity, these components will not again be described in detail. The bi-directional delay line 302 includes a plurality of unit delays 310A-N that operate in a forward delay mode to receive a forward delayed clock signal FDCLK from the model delay line 306 and to sequentially delay this signal by a unit delay TPD as the signal propagates through each unit delay in a forward direction (left to right in FIG. 3). The FDCLK signal continues propagating through the unit delays 310A-N in the forward direction until a reflection signal REF is received from a control circuit 312. In response to the REF signal, the bidirectional delay line 302 commences operation in a backward delay mode and reverses the direction of the propagating FDCLK signal, which begins propagating through the unit delays 310A-N in a backward direction (right to left in FIG. 3). Once again, as the FDCLK signal propagates through the unit delays 310A-N in the backward direction each unit delay delays the signal by the unit delay TPD until the signal is output from the unit delay 310A as a delayed clock signal CLKDEL. The FDCLK signal propagates through the same number of unit delays 310A-N in the forward and backward delay modes.
In operation, an initial rising edge of the CLK signal propagates through the input buffer 304 and the model delay line 306 to generate an initial rising edge of the FDCLK signal that is input to the unit delay 310A of the bi-directional delay line 302. In the following description, the edge of the FDCLK signal that is propagating through the bi-directional delay line 302 may simply be referred to as the FDCLK signal propagating through the bi-directional delay line for ease of description. The FDCLK signal continues propagating through the unit delays 310A-N in the forward direction until a subsequent rising edge of the CLKBUF signal from the input buffer 304 is applied to the control circuit 312. In response to the subsequent rising edge of the CLKBUF signal, the control circuit 312 applies an active REF signal to the bi-directional delay line 302 which, in turn, commences operation in the backward mode in response to the REF signal. Note that at this point, as indicated in FIG. 3, the delay introduced by the bi-directional delay line 302 equals a forward delay FD that is equal to TCK−(D1+D2). The FDCLK signal thereafter propagates through the unit delays 310A-N in the backward direction until the signal is output from the unit delay 310A as the CLKDEL signal. The bi-directional delay line 302 delays the FDCLK signal in the backward direction by a backward delay BD which approximately equals the forward delay FD of TCK−(D1+D2). In response to the CLKDEL signal, the output buffer 308 generates the CLKSYNC signal that is synchronized with the CLK signal. More specifically, in the simplified embodiment of FIG. 3 alternate rising edges of the CLKSYNC signal are synchronized with corresponding rising edges of the CLK signal.
FIG. 4 illustrates one embodiment of the bi-directional delay line 302 of FIG. 3 and illustrates the unit delays 310A-N in more detail. Each unit delay 310A-N includes a first group of the PMOS and NMOS transistors 402-408 connected in series and connected to a second group of the PMOS and NMOS transistors 410-416 the connected in series, as illustrated. The PMOS transistors 402 and NMOS transistors 408 in each unit delay 310A-N receive a forward control signal FWD while the PMOS transistors 410 and NMOS transistors 416 receive a backward control signal BWD. The FWD and BWD signals are active high and are complementary signals, meaning that when the FWD signal is high the BWD signal is low and when the BWD signal is high the FWD signal is low. In each unit delay 310A-N, the transistor 406 receives a forward input signal FA−FN−1 from a forward output node 418 of the preceding unit delay, with the unit delay 310A receiving the FDCLK signal as the forward input signal applied to the transistor 406. In addition, each transistor 414 in the unit delays 310A-N receives a backward input signal BB−BN+1 from a backward output node 420 of the subsequent unit delay, with the backward output node 420 of the unit delay 310A providing the CLKDEL signal. In addition, in the final unit delay 310N the forward output node 418 may be coupled to the gate of the transistor 414 to apply the forward input signal FN as the backward input signal BN+1 in the unit delay 310N.
The operation of the bi-directional delay line 302 of FIG. 4 will now be described in more detail with reference to a signal timing diagram of FIG. 5 that illustrates various signals in the bi-directional delay line during operation in the forward and backward modes. Prior to commencing operation of bi-directional delay line 302 in delaying the FDCLK signal, the delay line operates in an initialization mode to precharge various signals to desired values. To place the bi-directional delay line 302 in the initialization mode, the control circuit 312 (FIG. 3) drives the BWD signal active high, drives the FWD signal inactive low, and applies a high backward input signal BN+1 to the final unit delay 310N. In response to these signals, the bi-directional delay line 302 precharges the nodes 420 and thereby the CLKDEL and BB−BN signals high and the nodes 418 and thereby the FA−FN−1 signals low, as will now be described in more detail. In the following description, the BB−BN and FA−FN−1 signals will be described as being precharged either high or low, which means the corresponding nodes 418, 420 are either being charged or discharged to drive the corresponding BB−BN and FA−FN−1 signals to the desired voltage level, as will be appreciated by those skilled in the art.
During the initialization mode, in response to the active high BWD signal, the transistors 410 and 416 in each unit delay 310A-N turn OFF and ON, respectively, and in response to the inactive low FWD signal the transistors 402 and 408 turn ON and OFF, respectively. Starting with the unit delay 310N, the high BN+1 signal turns ON the transistor 414 which, in turn, precharges the FN signal low and turns ON the transistor 404. The transistors 402, 404 are now both turned ON, precharging the BN signal high. In response to the high BN signal, the transistor 414 in the unit delay 310N−1 (not shown) turns ON. At this point, the transistors 414 and 416 in the unit delay 310N−1 are both turned ON, precharging the FN−1 signal low. This low FN−1 signal causes the transistor 404 in the unit delay 310N−1 to turn ON and the turned ON transistors 402, 404 to precharge the BN−1 signal high. The signals propagate through the unit delays 310A-N in this manner until the BB signal from the unit delay 310B is precharged high, turning ON transistors 414, 416 in the unit delay 310A and precharging the FA signal low which, in turn, drives the CLKDEL signal high through the turned ON transistors 402, 404. At this point, the bi-directional delay line 302 is initialized, having precharged the FA−FN−1 signals low and the CLKDEL and BB−BN signals high. Before a time T0 in FIG. 5, the CLKDEL, FA−FE, and BB−BF signals are shown at their precharged levels.
After the bi-directional delay line 302 has been initialized and before the time T0, the control circuit 312 drives the FWD and BWD signal high and low, respectively, to place the delay line in a forward delay mode of operation in anticipation of a rising edge of the CLK signal. At the time T0, a rising edge of the CLK signal is applied to the input buffer 304, and in response to the rising edge of the CLK signal the input buffer 304 generates a rising edge of the CLKBUF signal the delay D1 later at a time T1. In response to the rising edge of the CLKBUF signal at the time T1, the model delay line 306 develops a rising edge of the FDCLK signal the model delay D1+D2 after the time T1, which occurs at just before a time T2. At the time T2, the high FDCLK signal turns ON the transistor 406, driving the CLKDEL signal low through the turned ON transistors 406, 408. In response to the low CLKDEL signal, the transistor 412 turns ON and the FA signal is driven high through the transistors 410, 412, which occurs just after the time T2. The high FA signal turns ON the transistor 406 in the unit delay 310B, which then drives the BB signal low through the transistors 406, 408. As shown in FIG. 5, this falling edge transition of the BB signal occurs a unit propagation delay TPD after the falling edge transition of the CLKDEL signal at just after the time T2. In the forward delay mode, the unit propagation delay TPD introduced by the unit delay 310A may more conveniently be viewed as corresponding to the delay between the rising edge of the FDCLK signal at just before the time T2 and the rising edge of the FA signal just after the time T2.
At just before a time T3, the FB signal from the unit delay 310B goes high in response to the low BB signal, which turns ON the transistors 410, 412 in the unit delay 310B and thereby drives the FB signal high. At the time T3, the subsequent rising edge of the CLK signal is applied to the input buffer 304. The unit delays 310C-E (not shown in FIG. 4) operate in the same way as just described for the unit delays 310A-B, each unit delay 310 receiving the FX−1 signal from the preceding unit delay, which turns ON the transistors 406, 408 in the unit delay and drives the corresponding BX signal low, with the low BX signal turning ON the corresponding transistor 412 to thereby drive the FX signal high through the turned ON transistors 410, 412 in the unit delay, as illustrated for the corresponding signals in FIG. 5.
At a time T4, which is the delay D1 of the input buffer 304 after the time T3, the next rising edge of the CLKBUF signal occurs. In response to this rising edge of the CLKBUF signal at T4, the control circuit 312 drives the FWD and BWD signals low and high, respectively, placing the delay line 302 in a backward delay mode of operation. In response to the low FWD signal, the transistors 408 in each unit delay 310A-N turn OFF and the transistors 402 turn ON, and in response to the high BWD signal the transistors 416 turn ON and the transistors 410 turn OFF.
At the time T4, the FE signal from the unit delay 310E had begun going high to turn ON the corresponding transistor 406 in the unit delay 310F, as illustrated by the FE signal in FIG. 5. Moreover, at the time T4 the transistor 406 in the unit delay 310F had begun turning ON and started driving the BF signal low, as is also illustrated in FIG. 5. But at the time T4, due to the FWD and BWD signals being driven low and high, respectively, the BF signal in the unit delay 310F stops going low and is driven back high by the turned ON transistors 402, 404 in the unit delay 310G. As the BF signal is driven high, the high BF signal turns ON the transistor 414 in the unit delay 310E which, in turn, drives the FE signal back low through the turned ON transistors 414, 416. The unit delays 310E-A thereafter operate in the same way as just described for the unit delays 310E, each unit delay 310X receiving the BX+1 signal from the subsequent unit delay, which turns turn ON the transistors 416, 418 in the unit delay and drives the corresponding FX signal low, with the low FX signal turning ON the corresponding transistor 404 to thereby drive the BX signal high through the turned ON transistors 402, 404 in the unit delay, as illustrated for the corresponding signals in FIG. 5. The delay between the times T3-T4 corresponds to the forward delay FD of the delay line 302. At a time T5, the CLKDEL signal from the unit delay 310A goes high in response to the BB signal going low, with the interval T4-T5 defining a backward delay time BD of the delay line 302. At a time T6, which occurs the delay D2 of the output buffer 308 (FIG. 3) after the time T5, the output buffer drives the CLKSYNC signal in synchronism with a corresponding rising edge of the CLK signal.
In the bi-directional delay line 302, the resolution of the delay line is defined by the analog operation of the last unit delay 310A-N that is utilized in delaying the applied FDCLK signal. In the example of FIG. 5, the unit delay 310F is the final unit delay used in delaying the applied FDCLK signal, and thus the analog operation of the unit delay 310F defines the resolution of the generated forward and backward delays FD+BD. This is true because the analog voltages developed in the final unit delay 310F at the point the delay line 302 terminates operation in the forward delay mode, which corresponds to the time T4 in FIG. 5, are utilized at the start of operation in the backward delay mode, which also corresponds to the time T4. For example, at the time T4 the BF signal in the unit delay 310F returns high from its value at the time T4 and is applied to the transistor 414 in the unit delay 310E to drive the FE signal back low from its value at the time T4. Thus, the time it takes the BF signal in the unit delay 310F to return high depends on its value at the time T4, and this time determines the time required to drive the FE signal back low from its current value at the time T4. The values of these signals at the time T4 thereby determine the propagation delay introduced by the final unit delay 310F.
In the unit delays 310A-N, the delay introduced by the final unit delay 310F is ideally equal for the forward and backward delay modes of operation so that the forward delay FD is equal to the backward delay BD. Thus, in FIG. 5 the waveform of the BF signal around the time T4 is ideally symmetrical since the time T4 defines both the termination of the forward delay mode and the start of the backward delay mode. In order for the delay introduced by the final unit delay 310F to be equal in both the forward and backward delay modes, the NMOS transistors 406,408 and PMOS transistors 402, 404 must be formed having the proper sizes and operating characteristics or “matched”, as will be appreciated by those skilled in the art. More specifically, note that during operation in the forward delay mode the NMOS transistors 406,408 in the final unit delay 310F begin pulling the BF signal low in response to the high going FE signal from the prior unit delay 310E. When the mode of operation is switched to the backward delay mode, however, it is the PMOS transistors 402, 404 in the final unit delay 310F that drive the BF signal back high. Thus, the rate at which the NMOS transistors 406,408 drive the BF signal low during the forward delay mode is ideally equal the rate at which the PMOS transistors 402, 404 drive the BF signal high during the backward delay mode.
In order to make the rates at which the NMOS transistors 406,408 and PMOS transistors 402, 404 drive the BF signal low and high during the forward and backward delay modes, respectively, the transistors must be designed having the required operating characteristics, as previously mentioned. For example, due to the lower majority charge carrier mobility in PMOS transistors, these transistors must be physically larger than corresponding NMOS transistors to provide the same voltage-current characteristics, as will be appreciated by those skilled in the art. For the PMOS transistors 402, 404 to drive the BF signal high during the backward delay mode at the same rate the NMOS transistors 406,408 drive the signal low during the forward delay mode the PMOS transistors must therefore be physically larger than NMOS transistors. The physically larger size of the PMOS transistors 402, 404, however, increases the capacitances of the PMOS transistors relative to the NMOS transistors 406,408. This increased capacitance of the PMOS transistors 402, 404 affects the operation the transistors and thus may result in operating characteristics that are different for the PMOS transistors 402, 404 and NMOS transistors 406, 408, which will result in different delays being introduced by the final unit delay 310F and will adversely affect the resolution of the SMD 300.
As previously discussed for the SMD 100 of FIG. 1, the bi-directional delay line 302 in the SMD 300 must provide a maximum variable delay VD (FD+BD) corresponding to the CLK signal having the lowest frequency in the frequency range over which the SMD 300 is designed to operate. This may require the bi-directional delay line 302 to include a relatively large number of unit delays 310A-N which, as previously discussed, can result in significant power consumption by the SMD 300 and which may be undesirable, particularly in applications where the synchronous memory device is contained in a portable battery-powered device. Moreover, in the SMD 300 the required delay resolution may be difficult to obtain due to the inherent problems associated with properly sizing the NMOS and PMOS transistors in the unit delays 310A-N, as will be appreciated by those skilled in the art. As operating frequencies increase, even small variations in the variable delay VD can introduce undesirable delays or jitter of the CLKSYNC signal relative to the CLK signal.
There is a need for an SMD having good resolution that occupies less space on a semiconductor substrate and consumes less power.