Today's high performance systems need clock generation systems that minimize skew. Indeed, skew has become the major part of constraints that form the upper boundary for the system clock frequency. Skew is defined as the difference in time between simultaneous clock signals within a system.
Reduction in system clock skew reduces cost by avoiding complicated architecture or the necessity for faster logic components. Further, as skew is reduced, higher clock rates and better timing analysis become possible. It desirable to provide every component that needs clocking, such as flip-flops and latches, with the edge of the clock at the same time within each clock period. As can be expected, in current system design, extensive (and expensive) resources are dedicated to creating clock distribution systems and methodologies that minimize skew across entire system.
Known clock distribution methodologies focus on the creation of geometrically similar clock distribution circuits known as clock trees. In other words, each component that receives a clock signal is connected to the reference clock by a trace of the same length having the same electrical characteristics. It is know to provide buffers, at the nodes of such trees to distribute the clock signals. Distributed clock networks are also know that provide for the replication of the clock signal with a single phase locked loop located at multiple points (“nodes”) across a tree (typically in conjunction with a buffer), and distributing the replicated clock signal only to a small section of the chip—once again using equivalent length traces.
The use of clock trees and distributed clock networks requires a significant amount of space on the chip or board and an equally significant amount of design time to ensure that all components requiring a synchronized clock input are located on the clock tree. Several software programs are available that assist with the optimizing of the layout of clock trees. Of course such optimization often comes at the expense of alternative layout that would provide greater design freedom or benefits from a non-distance based layout of components.
The use of clock trees also requires that any transmission line be of a fixed known length. Solutions that depend on fixed length signal paths have proven unsuitable in situations where it is desirable that the signal path be variable either during the design stage or in the actual product. For example, the transmission of a synchronized clock signal over data busses, such as SCSI, AGP, or PCI is difficult. The length of the bus is often varied during the design stage and installers and users frequently expand the bus with riser blocks and bus expanders—both of which increase the length of transmission lines—inducing skew.
Accordingly, the present inventors have recognized a need for clock distribution apparatus and methods capable of providing a coincident clock to dispersed locations wherein the clock traces can be of a variable length.