1. Field of the Invention
The present invention relates to digital electronic circuits and, more particularly, to a method and system for measuring on-chip delays for Field Programmable Gate Arrays (FPGAs) for reliability testing.
2. Description of Prior Art
A Field Programmable Gate Array or FPGA is a semiconductor device containing programmable logic components that can be programmed to duplicate the functionality of basic logic gates such as AND, OR, XOR, NOT or more complex combinatorial functions such as decoders or simple math functions. The FPGA also contains sequential logic in the form of configurable flip/flops. Many FPGAs also include memory elements such as RAMs.
An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs typically include several “lookup tables” (LUTs). A LUT is an addressable memory array that is typically loaded with data during the configuration process. For example, some commercial CLBs includes eight LUTS and eight flip/flops. Each LUT has four data input terminals that address the configurable memory. By storing predetermined values in the appropriate memory locations, the LUT can be configured to provide any function of up to four variables. Indeed, all of the CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory that define how the CLBs, IOBs, and interconnect structure are configured. The collective states of the individual memory determine the function of the FPGA. As the size and complexity of FPGAs grow, manufactures are becoming more concerned with measuring the speed and performance of their designs.
FIG. 1 depicts a conventional test configuration 100 for determining the signal propagation delay of a test circuit 110 in a conventional IC 115. A tester 120 includes an output lead 125 connected to an input pin 130 of IC 115. Tester 120 also includes an input line 135 connected to an output pin 140 of IC 115. Tester 120 applies an input signal to input pin 130 and measures how long the signal takes to propagate through test circuit 110 from input pin 130 to output pin 140. The resulting time period is the timing parameter for test circuit 110, the path of interest.
The above-noted test procedure is problematic with FPGAs because many of the signal paths internal to the chip are not accessible via input and output pins, and therefore cannot be measured directly.
Other techniques have been developed to measure signal propagation delays in FPGAs.
Traditionally, a delay chain of inverters is placed on the FPGA, with an input port feeding the inverter chain and an output port driving the output of the chain off-chip. Unfortunately, this is inaccurate since the input and output delays are included.
Another method arranges the delay chain as a ring oscillator. For example, U.S. Pat. No. 6,075,418 to Kingsley, et al., entitled “System With Downstream Set or Clear for Measuring Signal Propagation Delays on Integrated Circuits,” issued Jun. 13, 2000, describes methods of measuring signal-propagation delays by including signal paths of interest in ring oscillators. The ring oscillators oscillate at frequencies that area function of the delays through signal paths of interest. The oscillation frequencies of such oscillators are therefore indicative of the delays through various paths of interest.
See, also, Direct Measures of Path Delays on Commercial FPGA Chips” by Mania Ruffoni et al., 6th IEE Workshop, Proceedings volume issue, 2002, pages 157-159, which suggests a comparison between the operating frequency of a ring oscillator that includes the path under test, and that of a reference ring oscillator that does not. The ring oscillator approach suffers from the problem that it does not always oscillate as expected.
United States Patent Application 20030098731 by Tabatabaei, Sassan et al. published May 29, 2003 shows a high resolution time-to-digital converter (TDC) that uses a pair of digital oscillators. The periods of the oscillators differ. The oscillators are triggered by START and STOP pulses. A counter counts a number of pulses until reference points on the signals output by the oscillators coincide. Measurements may be made using a dual resolution method. Intrinsic jitter of the TDC can be determined by comparing sets of measurements in which the switch in resolutions is made at different points. A range extender circuit may be provided to extend a valid measurement range of the TDC.
U.S. Pat. No. 6,983,394 to Morrison et al. (Xilinx) issued Jan. 3, 2006 shows a method and apparatus for clock signal performance measurement using a digital delay in conjunction with a processing circuit to continuously measure the jitter of an input clock signal. A pair of digital delay circuits is used to continuously measure the skew or delay between a reference clock signal and a input clock signal, thus providing a measurement of the skew of the input clock signal over time. The digital delay circuit(s) are formed on-chip, and thus an on-chip determination of jitter or skew may be provided.
Santos, A CMOS delay locked and sub-nanosecond time-to-digital converter chip, IEEE Trans on Nuclear Science, vol. 43, pp. 1717-1719, June, 1996 discloses a TDC based on the use of a delay chain. In this circuit, the output of the delay elements in the delay chain are set HIGH as the START rising edge travels through them. A delay locked loop (DLL) is used to calibrate the delay elements to a known delay. Such a calibration requires very good matching between all the delay elements in both the delay chain and the DLL.
M. Abramovici and C. Stroud, “BIST-based delay-fault testing in FPGAs,” Journal of Electronic Testing, vol. 19, no. 5, pp. 549-558, October 2003 discloses a comparison-based delay test method in which a number of identical paths are constructed in the FPGA under test and every LUT on these paths is programmed to propagate an input value to its output. A fault is detected when the difference between the arrival times at the destinations of the first and last signals exceeds a specified threshold.
Design-Specific Path Delay Testing in Lookup Table-based FPGAs, Premachandran R. Menoh et al., Transactions On Computer-Aided Design Of Integrated Cirtuits And Systems, Vol. XX, No. Y (2005) shows an approach for FPGA path delay testing which partitions target paths into subsets that are tested in the same test configuration. Each path is tested for all combinations of signal inversions along the path length. Each configuration consists of a sequence generator, response analyzer and circuitry for controlling inversions along tested paths, all of which are formed from FPGA resources not currently under test.
E. Chmelar, “FPGA interconnect delay fault testing,” in IEEE Int. Test Conf., Charlotte, N.C., September 2003, pp. 1239-1247 is a similar comparison-based delay approach to the Abramovici article.
M. Tahoori and S. Mitra, “Interconnect delay testing of designs on programmable logic devices,” in IEEE Int. Test Conf., Charlotte, N.C., October 2004 disclose a method of testing all paths in a combinational network for delay faults in which all paths are simultaneously tested for slow-to-rise faults by applying 0->1 transitions at all inputs. Slow-to-fall faults are similarly tested by changing LUT functions to ORs and applying 1->0 transitions at all inputs.
It would be greatly advantageous to provide an improved circuit architecture and method for built-in self-test (BIST) of FPGA propagation delay using available (unused) FPGA resources, that provides an actual and very precise measurement of the propagation delay through the delay chain-without any input and output delays.