Q:

Why are NAND flash and NOR flash named using the terms NAND and NOR?

Is the naming of the two flash architectures related to differences between the two types of logic gates?  If so, how?
Why does or doesn't this difference also apply to different DRAM or SRAM configurations or layouts?
(This question is not about the R/W performance or usage differences between NAND and NOR flash, which has already been asked here: What are the differences between NAND and NOR flash? )

A:

Because they're wired like a NAND or NOR gate. (See this question for classical CMOS NAND/NOR gates. Here the logic is just NMOS 'pull-down', not CMOS)

To read NAND flash, every transistor is switched on in the cell except the one being read. Because it's wired like a NAND gate, where if every signal is AND'ed you get a low, if you see a low on the bit line then you know the memory cell was set.

