Packet processors are used in routers, switches, servers, Personal Computers (PCs), etc. for processing and routing packets in a packet switched network, such as the Internet. The packet processor is often required to schedule both the processing of received packets and the outputting of packets after packet processing is completed. The type and amount of packet traffic received and transmitted by the packet processor constantly varies. Thus, these scheduling operations are important for fairly and efficiently processing the packets.
There is a problem efficiently implementing packet scheduling in packet processors. Hardware-based approaches can operate very fast, but tend to be inflexible and costly. For example, a whole Application Specific Integrated Circuit (ASIC) may be required for packet scheduling operations.
The desire to have a flexible solution, for example, one whose algorithm/function can be changed without spinning an ASIC, strongly motivates a software based solution. However, software based solutions for scheduling operations run very slowly due to the number of required serial logic operations.
These extensive processing requirements are further complicated by the large data structures used for packet scheduling. In the case of some hardware implementations, these data structures can be over 1000 bits wide. Even with alternative scheduling structures (e.g., calendars), items such as the schedule state are still too wide for the registers typically used in the packet processor. Needless to say, the task of fetching, updating, and storing such large data structures can be costly on a Central Processing Unit (CPU) or even a Network Processing Unit (NPU).
The multiple fields used in the scheduling data structure also do not correspond well with the register files used in packet processors. For example, these different fields may not have bit lengths of 8, 16, or 32 bits. This forces the packet processor to perform many data alignment and masking operations just to prepare the scheduling data for subsequent processing.
What is missing is a processing architecture in the middle that provides a cheap and flexible solution that runs at speeds significantly faster than current software options, but whose cost is less than previous hardware approaches. The present invention addresses this and other problems associated with the prior art.