1. Field of the Invention
The present invention relates to a periodic signal generator circuit for generating a plurality of periodic signals from a single periodic signal.
2. Description of the Prior Art
FIG. 1 is a block diagram showing a shift register receiving a two-phase clock pulse from a conventional periodic signal generator circuit.
In FIG. 1, a shift register 35 comprises latches 31 to 34 connected in series. Each of the latches 31 to 34 accepts data applied to a D input terminal and outputs a signal at an "H" level from a Q output terminal when a clock signal inputted to a clock input terminal C is at the "H" level, and holds data when the clock signal is at an "L" level. The latches 31 to 34 comprise a D type flip-flop.
The shift register 35 shown in FIG. 1 sequentially transmits data In to the latches 31, 32, 33 and 34 by a so-called two-phase non-overlapped clock signal in which clock signals C1 and C2 alternately attain the "H" level. At that time, when the clock signals C1 and C2 simultaneously attain the "H" level, the data In quickly passes through the four latches 31 to 34, so that a malfunction occurs. In order to prevent such a malfunction, the clock signals C1 and C2 must be non-overlapped signals. Description is now made in detail on a periodic signal generator circuit for generating a two-phase non-overlapped clock signal.
FIG. 2 illustrates a conventional clock signal generator circuit used in a semiconductor integrated circuit device.
The clock signal generator circuit, which generates a plurality of clock signals from a single clock signal, mainly comprises a first AND gate circuit 1, a second AND gate circuit 2, a first inverter 30, a second inverter 40 and a third inverter 5.
The first AND gate circuit 1 comprises two NAND circuits 11 and 12, four inverters 13, 14, 5 and 25, a p channel type transistor 17 and an n channel type transistor 18. The first AND gate circuit 1 has two input terminals, one being a node a1 between an input terminal of the inverter 5 and one input terminal of the NAND circuit 12 and the other being a node b1 between an input terminal of the inverter 13 and the other input terminal of the NAND circuit 12, and an output terminal which is a node c1 of a drain of the transistor 17 and a source of the transistor 18.
In the same manner, the second AND gate circuit 2 comprises two NAND circuits 21 and 22, four inverter circuits 23, 24, 25 and 26, a p channel type transistor 27 and an n channel type transistor 28. The second AND gate circuit 2 has two input terminals, one being a node a2 between an input terminal of the inverter 25 and one input terminal of the NAND circuit 22 and a node b2 between an input terminal of the inverter 23 and the other input terminal of the NAND circuit 22, and an output terminal which is a node c2 between a drain of the transistor 27 and a source of the transistor 28.
In the first AND gate circuit 1, the output terminal c1 attains the "H" level only when both the input terminals a1 and b1 attain the "H" level, and the output terminal c1 attains the "L" level in the remaining conditions. In the same manner, in the second AND gate circuit 2, the output terminal c2 attains the "H" level only when both the input terminals a2 and b2 attain the "H" level, and the output terminal c2 attains the "L" level in the remaining conditions.
The output terminal c1 of the first AND gate circuit 1 is connected to one input terminal b2 of the second AND gate circuit 2 through a first inverter 30. In addition, the output terminal c2 of the second AND gate circuit 2 is connected to one input terminal b1 of the first AND gate 1 through a second inverter 40. A clock signal line CLK is connected to the other input terminal a1 of the first AND gate circuit 1 through inverters 61 and 62, and the clock signal line CLK is connected to the other input terminal a2 of the second AND gate circuit 2 through the third inverter 5, and the inverters 61 and 62. The third inverter 5 constitutes a part of the first AND gate circuit 1, and inverts a clock signal and inputs the same to the input terminal a2 of the first AND gate circuit 2.
As shown in FIG. 3, when a clock signal in which "H" and "L" levels are repeated once per clock period is inputted to the clock signal line CLK, a signal of a slightly deformed waveform of the clock signal appears at the output terminal c1 of the first AND gate circuit 1 and a signal of a slightly deformed waveform of the inverted clock signal appears at the output terminal c2 of the second AND gate circuit 2.
When the clock signal changes from the "H" level to the "L" level and a signal at the output terminal c1 of the first AND gate circuit 1 changes from the "H" level to the "L" level, logic of the inverter 30 is inverted at the logical threshold value at point 31a of the signal at the output terminal c1, so that a signal at the output terminal c2 of the second AND gate circuit 2 is inverted from the "L" level to the "H" level at point 31b. In addition, when the clock signal changes from the "L" level to the "H" level and the signal at the output terminal c2 of the second AND gate circuit 2 changes from the "H" level to the "L" level, logic of the inverter 40 is inverted at the logical threshold value at point 41a of the signal at the output terminal c2, so that the signal at the output terminal c1 of the first AND gate circuit 1 is inverted from the "L" level to the "H" level at point 41b. The threshold value of the inverters 30 and 40 is generally a half of a supply voltage Vcc.
Since the signals at the output terminals c2 and c1 are inverted from the "L" level to the "H" level when both signals change from the "H" level to the "L" level and attain the logical threshold value of the inverters 30 and 40, the portions which are not at a 0 level in the waveforms of the two signals overlap with each other in the same time period, as shown in FIG. 3. In FIG. 3, T2 represents a time period when the portions which are not at the 0 level of the signals appearing at the output terminals c1 and c2 overlap with each other.
If the time periods T1 and T2 become longer, the shift register 35 shown in FIG. 1 erroneously operates. In order to prevent such malfunction, a periodic signal generator circuit must be designed so that the time periods T1 and T2 are as short as possible. However, when the distance between the periodic signal generator circuit shown in FIG. 2 and the shift register 35 shown in FIG. 1 is increased, a long interconnection is required, which means that a large capacitive load is connected to the output terminal of the periodic signal generator circuit. Therefore, even if the time periods T1 and T2 when the portions which are not at the 0 level overlap with each other are shorter, deformation of the waveform becomes large when interconnection capacitance is increased, so that the time period T2 is liable to be longer.
It is desirable that the rising and the falling of signals outputted to the output terminals c1 and c2 of the periodic signal generator circuit should be as abrupt as possible so that the time periods T1 and T2 when the portions which are not at the 0 level overlap with each other do not vary due to the change of the load.