The present invention generally relates to integrated circuits, and, more particularly, to voltage-driver circuits having dynamic slew rate control.
Integrated circuits (ICs) including System on Chip (SoCs) integrate various digital and analog components on a single chip. The ICs communicate with different types of external components, such as dynamic random access memories (DRAMs), double-data rate (DDR) memories, and Ethernet and universal serial data-bus (USB) devices. To facilitate the communication between an IC and the external components, the IC includes input/output (IO) drivers, also referred to as voltage-driver circuits. The voltage-driver circuits perform various IO operations, such as driving voltage signals from the IC to the external components, receiving and conditioning data signals from the external components, and providing electrostatic protection to the IC.
The voltage-driver circuit must output an output signal having a constant slew rate regardless of the type of the external component connected to the IC. However, for each type of external component, the load impedance at the output of the voltage-driver circuit changes based on the power consumed by the external component. Change in the load impedance leads to a change in the slew rate of the output signal received by the external component. Therefore, to ensure that the external component receives an output signal having a constant slew rate, the slew rate of the output signal generated at the output of the voltage-driver circuit must be modified. To facilitate modification of the slew rate of the output signal, the voltage-driver circuit includes multiple output buffers. Generally, output buffers include transistors, capacitors, and resistors. Each output buffer has an input terminal connected to a reference voltage generator for receiving a reference voltage signal and an output terminal for outputting the reference voltage signal having a distinct slew rate as an intermediate output signal. Each output buffer further includes an enable terminal that is connected to a processor. Based on the type of external component, the processor is programmed to generate and provide a set of control signals to the output buffers, thereby controlling the operational state of the output buffers. The voltage-driver circuit collectively outputs the intermediate output signals generated by the output buffers having distinct slew rates as the output signal. Therefore, the slew rate of the output signal depends on the operational state of the output buffers.
FIG. 1 shows a conventional IC 100 connected to a variable load 102 by way of a voltage-driver circuit 104. The variable load 102 is representative of an external component connected to the IC 100. The IC 100 further includes a processor 106 connected to the voltage-driver circuit 104. The voltage-driver circuit 104 includes first through third output buffers 108-112 and first and second reference voltage generators 114 and 116. The first and second reference voltage generators 114 and 116 generate an enable signal and a supply voltage signal, respectively.
The first output buffer 108 has an input terminal connected to the second reference voltage generator 116 for receiving the supply voltage signal, an enable terminal connected to the first reference voltage generator 114 for receiving the enable signal, and an output terminal for providing a first intermediate output signal having a first slew rate. The second output buffer 110 has an input terminal connected to the second reference voltage generator 116 for receiving the supply voltage signal, an enable terminal connected to the processor 106 for receiving a first control signal, and an output terminal for providing a second intermediate output signal having a second slew rate. The third output buffer 112 has an input terminal connected to the second reference voltage generator 116 for receiving the supply voltage signal, an enable terminal connected to the processor 106 for receiving a second control signal, and an output terminal for providing a third intermediate output signal having a third slew rate.
Based on the type of the variable load 102 connected to the IC 100, the processor 106 is programmed to generate and provide the first and second control signals to the second and third output buffers 110 and 112. The voltage-driver circuit 104 collectively outputs the first, second and third intermediate output signals generated by the output buffers as the output signal. Thus, the processor 106 configures the operational modes of the second and third output buffers 110 and 112, thereby controlling the slew rate of the output signal. For example, to decrease the slew rate of the output signal, the processor 106 generates the first and second control signals to switch off the second and third output buffers 110 and 112. Thus, the voltage-driver circuit 104 outputs only the first intermediate output signal as the output signal having a slew rate equivalent to the first slew rate.
However, the power consumed by the external component, i.e., the power consumed by the variable load 102 varies based on the type of the external component. For example, a USB device may consume more power than the power consumed by a DRAM. Thus, the load impedance on the voltage-driver circuit 104 varies based on the type of the variable load 102. The type of printed circuit board (PCB, not shown) used to mechanically support and electrically connect the IC 100 and the variable load 102 also leads to variations in the load impedance. The load impedance also changes based on various environmental conditions, such as ambient temperature and the temperature of the PCB. Further, the composition of the electrical connections decays and changes over time (aging), leading to a gradual change in the load impedance. Variation in the load impedance leads to a change in the slew rate of the output signal. If the load impedance increases, the slew rate of the output signal decreases, which can lead to timing issues and cause timing inconsistencies among various components of the IC 100 and the variable load 102. If the load impedance decreases, the slew rate of the output signal increases, resulting in power supply noise issues.
To account for changes in the slew rate of the output signal caused by changes in the load impedance, the slew rate of the output signal generated by the voltage-driver circuit must be corrected. The processor 106 can be programmed to generate the first and second control signals based on the type of the variable load 102. However, it is time consuming and impractical to program the processor 106 to correct the slew rate of the output signal for each type of the variable load 102. Further, it is difficult to program the processor 106 to account for changes in the load impedance caused by changing environmental conditions and aging. Therefore, there is a need for an IC that dynamically senses changes in the load impedance at the output of a voltage-driver circuit, and corrects the slew rate of the output signal to correspond to the load impedance.
A known technique to overcome the aforementioned problems uses a capacitive feedback circuit connected to the voltage-driver circuit. However, this technique can be used to only reduce the slew rate of the output signal. Another known technique uses pulse width comparison to detect changes in the load impedance and then correct the slew rate of the output signal. However, this technique requires generation of high frequency clock signals that are used for pulse width comparison when the output signal is a high frequency signal (e.g., 1 GHz). Yet another known technique uses a D-type flip-flop that has asynchronous inputs. However, since the inputs to the flip-flop are asynchronous, this technique may lead to stability issues and may malfunction.
Thus, it would be advantageous to be able to dynamically sense changes in the load impedance at the output of a voltage-driver circuit, correct the slew rate of the output signal without using a processor, flip-flops or clock generators, and prevent timing and power supply noise issues.