Devices that form gain stages of a power amplifier (PA) or other similar circuitry are inherently non-linear. Operating such a device in Class A operation in which the device is always in the conducting state may reduce non-linearity effects, but such operation is to be avoided, as a large bias current is needed to make the signal current small compared to the bias current. As a result, it becomes impractical to power the PA in a low power application. Efforts have been made to linearize these devices over a large range of currents, such that as input or signal currents vary over several orders of magnitude, a degree of linearity can be maintained between input to output with a small DC current. However, while a sub-micron complementary metal oxide semiconductor (CMOS) device has a very linear transconductance over some of its bias range due to short channel effects, high efficiency gain stages formed of CMOS devices can suffer from significant gain expansion. This is because stages biased in Class B or AB for high efficiency operate in a sub-threshold region for some portion of their power transfer characteristic. Sub-threshold conduction is an exponential process, and causes significant gain expansion.
Current approaches to solve this problem act to increase the quiescent current in each stage until there is sufficient linearity. However, this does not completely compensate for the non-linearity, and further it consumes significant power. Other approaches that rely on feedback or feed-forward linearization to provide a correction at an output of a gain stage consume significant power, are difficult to implement in portable products, and suffer from stability problems.