In recent years, large size liquid crystal display devices are gathering attention and vigorous efforts are being forwarded to realize low cost liquid crystal panels. However, as to TFT substrates, the effort to reduce the cost is belated. On the occasion of forming an image display element in a liquid crystal display device, a lot of manufacturing steps such as a deposition step, an etching step, a doping step, a washing step, a photolithography step, an ashing step and a heat treatment step are necessary. Accordingly, high manufacturing costs and personnel costs are necessary.
A reason for that a manufacturing process cannot be more simplified than ever is present in a TFT structure. That is, since interconnections are formed into a multi-layered structure to realize cubic crossings, contact holes are necessary to be formed, resulting in an increase in the number of steps.
In what follows, a manufacturing process of a TFT with a polycrystalline silicon film in an active layer will be shown.
1. Formation of active layer
2. Formation of gate insulating film, gate electrode and gate interconnection
3. Source/drain dope
4. Deposition of interlayer insulating film
5. Formation of contact hole
6. Formation of interconnection
Following the formation of the interconnections, a protective film is deposited, followed by further forming contact holes, further followed by connecting to pixel electrodes corresponding to electro-optical elements, and thereby a TFT substrate comes to completion. With reference to FIG. 7, in what follows, explanations of 1 through 6 will be given.
Firstly, on a glass substrate 701, an island-like semiconductor layer 702 is formed. An amorphous silicon film that is deposited, typically, by means of a CVD method is crystallized by use of a laser annealing method, a thermal annealing method or an RTA method and the like; a predetermined region that is to be an active layer is covered with a resist mask; a polycrystalline silicon film that is not covered with the resist is removed by use of a dry etching device; and thereby an island-like semiconductor layer is formed.
After the formation of island-like semiconductor layer, over an entire surface of the substrate, by means of a plasma CVD method or a sputtering method, an insulating film and a conductive layer are sequentially formed; a resist mask is disposed on a predetermined region; and the insulating film and the conductive film are etched to form a gate insulating film 703, a gate electrode 704 and a gate interconnection 705.
In the next place, by use of an ion doping method, impurity atoms that impart the n-type and impurity atoms that impart the p-type are doped in predetermined regions to form source/drain regions of an n-channel type TFT and a p-channel type TFT. In order to selectively dope in predetermined regions, a resist mask is used.
After the source/drain regions are formed, in order to electrically activate doped impurity atoms, a thermal annealing method, an RTA method or a laser annealing method is applied to activate. In some cases, the activation process is applied after the formation of an interlayer insulating film. Furthermore, in order to terminate dangling bonds at an interface between the active layer and the gate insulating film, with a silicon nitride film or a silicon nitride oxide film deposited, usually, the hydrogenation is applied. Subsequently, an interlayer insulating film 706 is formed.
After the interlayer insulating film 706 is formed, a resist mask is disposed in a predetermined region, followed by etching to form a contact hole in an interlayer insulating film on a source/drain region and a gate interconnection. The etching is carried out by means of a dry etching method or a wet etching method.
After the contact hole is formed, by means of a sputtering method, an interconnection metal is deposited, followed by disposing a resist mask on a predetermined region, and followed by etching to form a source interconnection 707. After the formation of the source interconnection, through the contact hole, the respective interconnections and the source/drain region and the gate interconnection are electrically connected.
Thus, manufacturing steps of the TFT manufacture are numerous and these can be never omitted, that is, these are indispensable processes. The TFT manufacturing process with a polycrystalline silicon film is explained as an example; however, even in the manufacturing process of a display device with amorphous Si in an active layer, the situation is the same.
For instance, in a TFT that is used in a large size liquid crystal display device and uses amorphous Si, in general, an inversed stagger structure or a stagger structure is adopted. In this case also, a TFT has to be formed according to a complicated manufacturing process that makes use of photolithography; accordingly, there is a problem similar to that in the TFT that uses a polycrystalline silicon film.
In view of the above problems, the present invention intends to find a method of manufacturing a TFT substrate at low costs. That the number of steps is numerous is at the heart of the problem; accordingly, how to reduce the number of steps is considered. In order to reduce the indispensable steps in the manufacture of the TFT, it is necessary to reconsider a TFT structure itself and to reconstruct a manufacturing process thereof.
Accordingly, the invention intends to proposes a novel TFT structure and a novel process for manufacturing the novel TFT structure to largely reduce TFT manufacturing steps, and thereby to largely reduce the manufacturing cost of a TFT substrate. Furthermore, the invention intends to reduce a photolithography process and thereby to reduce the number of masks that are used in the TFT manufacturing process.