Q:

What is the difference between structural Verilog and behavioural Verilog?

As in the title, what are the main differences between structural and behavioural Verilog?

A:

There is no strict definition of these terms, according to the IEEE Std.  However, customarily, structural refers to describing a design using module instances (especially for the lower-level building blocks such as AND gates and flip-flops), whereas behavioral refers to describing a design using always blocks.
Gate netlists are always structural, and RTL code is typically behavioral.  It is common for RTL to have instances of clock gates and synchronizer cells.

A:

Structural

Here functions are defined using basic components such as an invertor,
  a MUX, a adder, a decoder, basic digital logic gates etc..  It is just
  like connecting and arranging different parts of circuits available to
  implement a function.

Behavorial

The Behavioral description in Verilog is used to describe the function
  of a design in an algorithmic manner. Behavioral modeling in Verilog
  uses constructs similar to C language constructs. Further , this is
  divided into 2 sub categories .

(a) Continuous 

assignment of data to outputs are continuous.  This will be
  implemented using explicit "assign" statements   or   by assigning a
  value to a  wire during its declaration  . 
  In case of assign any change in input will
  immediately effect the output . Hence output is to be declared as
  wire

(b) Procedural

Here the data assignments are not carried out continuously instead it
  happens on specific events specified in sensitivity list. This type of
  modelling scheme is implemented using procedural blocks such as
  "always"or "initial" .
Here, output variables must be defined as reg because they need to
  keep hold of previous value until new assignment occurs after any change in specified sensitivity list.

Hope this helps  :)

