This invention relates to asynchronous systems and is more particularly concerned with communication between elements of a digital computer.
The need to ensure accurate and timely transfer of data between independent processes arises in a number of situations and is of particular importance in the exploitation of parallel architectures within distributed real time data processing systems. Conventionally systems for enabling communication between asynchronous processes running in different elements of a computer have used a region of shared memory to provide a buffer to which all the processes concerned have access and to which each process can read or write data in its own time. However known communication systems suffer the disadvantage that the data passing through the buffer can be corrupted if, for example, one process starts to read data from the buffer whilst another process is part way through writing data to the buffer. To overcome this difficulty known communications systems have relied upon mutual exclusion, that is one process is prevented from writing data to the buffer if the other process has already started to read data. Although this successfully avoids conflict between the writing and reading processes it results in a system which is not fully asynchronous since the action of one process in accessing the buffer can affect the timing of the other process.
British Patent No. 2039102 discloses one example of a prior art system for enabling communication between two asynchronous elements. The buffer memory is divided into two parts to enable data to flow simultaneously in both directions between the two asynchronous elements. As with other known devices the reading and writing processes are inherently susceptible to conflict and so the system described relies upon the transmission of interrupts to the different asynchronous elements to prevents conflict. As a result there is interference between the timing of the units so that they are not fully asynchronous.