There are a number of applications in integrated circuits where an on-chip voltage which exceeds the value supplied by an external power supply is useful. Two such applications, shown in FIGS. 1 and 2 respectively, are
(1) controlling pass transistors in field programmable gate array structures, and
(2) controlling isolation transistors in antifuse-programmable gate array structures.
FIG. 1 shows a circuit in which N-channel pass transistor M1 interconnects two logic units L1 and L2, the gate of pass transistor M1 being controlled by SRAM memory cell U1, which is in turn powered by memory cell power supply Vmem. Transistor M1 is used to form a user programmable connection between interconnect lines (nets) N1 and N2. If the power supply voltage to memory cell U1 is the same as the power supply voltage for the logic units L1 and L2, transistor M1 will not pass the full voltage level between the two nets N1 and N2. However, raising the logic high voltage to the gate of transistor M1 by an amount greater than the threshold voltage drop of transistor M1 will avoid the logic-high threshold drop and consequent loss of voltage swing. FIG. 2 shows an antifuse circuit which can benefit from a pumped voltage supply. Transistors M2 through M5 control transmission of logic signals between logic units L3 and L4. By applying a low isolation voltage V-ISO to gates of transistors M2 through M5, these transistors are held off while programming voltage control units P1 and P2 program selected ones of antifuses F1 through F4. During operation, transistors M2 through M5 are turned on through a high signal provided by V-ISO. The interconnection of logic units L3 and L4 is determined by the states of antifuses F1 through F4. Use of a high V-ISO voltage assures high performance by providing full voltage swings (no threshold drop) across transistors M2 through M5.
Further, maintaining the full voltage swing simplifies the receiving logic. For example, the logic circuit can be a typical 5-volt CMOS circuit using 5-volt logic signals. Further, the reduced resistance of transistor M1 in its on-state greatly increases the speed of passing logic signals between logic units L1 and L2. Thus, certain transistors in a circuit such as shown in FIGS. 1 and 2 can benefit from a high voltage at their control terminals.
In order to minimize on-resistance, the on-state voltage applied to gates of transistors such as M1 through M5 should be as high as possible without exceeding the breakdown voltage of the transistors. (Breakdown may consist of current flowing between the drain and substrate in the reverse direction, or less likely, through the insulating oxide between gate and channel, and may permanently change device characteristics, which causes unreliable performance.) A memory cell which is powered at a higher voltage than the power supply voltage can in turn supply a higher gate voltage to transistors such as M1 through M5.
Two common prior art voltage generators using a pumping technique, the voltage doubler and the voltage tripler, are shown in FIGS. 3 and 4, respectively. The names voltage doubler and voltage tripler are only roughly descriptive, and apply to the situation in which the diode drop is small with respect to the supply voltage (not always the case).
In FIG. 3, a steady state Vdd voltage is applied to the anode of diode D31 and generates a voltage at the cathode of diode D31 of at least Vdd minus VD31, where VD31 is the diode drop of diode D31. A square wave clock signal VCLK, which alternates between VDD and ground, is applied to plate C31b of capacitor C31. This varying signal on plate C31b drives current to or from plate C31a. However, when voltage on capacitor plate C31b is low, diode D31 allows current to flow from Vdd to plate C31a and prevents the voltage on plate C31a from going below Vdd-VD31. Likewise, if the voltage on plate C31a rises more than one diode drop above the output voltage VLOAD, current flows through diode D32 to node N31. Thus the voltage level on capacitor plate C31a varies between VDD - VD31 and 2Vdd-VD31, and maintains the voltage VLOAD on node N31 at approximately 2Vdd-VD31-VD32.
Similarly, FIG. 4 shows a voltage tripler in which three diodes D41, D42, and D43 are placed in series as shown, and capacitors C41 and C42 apply clock signals at intermediate points N41 and N42 between successive diodes. Importantly, inverter I41 inverts the polarity of the VCLK signal so that the signal applied to capacitor C42 is out of phase with the signal applied to capacitor C41. As above, the voltage on node N41 varies between Vdd-VD41 and 2Vdd-VD41. Diode D42 becomes conductive if the voltage on node N42 goes below this varying signal by more than VD42, the diode drop of diode D42. Therefore, the voltage on node N42 tends to rise to 2Vdd-VD42. When the voltage on VCLK goes high, current is driven from plate C41a of capacitor C41 through diode D42 and onto plate C42a of capacitor C42, which is being pulled to a low voltage by the low signal from inverter I41. Then as VCLK moves to a low (ground) voltage, the high voltage output from inverter I41 produces a corresponding high voltage on capacitor plate C42a, which in turn drives current through diode D43. Thus the voltage level of between Vdd-VD41 and 2Vdd-VD41 on node N41 results in a voltage level between approximately 2Vdd-VD41-VD42 and 3Vdd-VD41-VD42 on node N42, and a final load voltage of approximately 3Vdd-VD41-VD42-VD43. A load capacitor can smooth this output signal.
Practically, in a 5-volt system, the voltage tripler circuit of FIG. 4 typically produces an output voltage somewhat above twice the supply voltage, and the circuit of FIG. 3 produces a voltage somewhat less than twice the supply voltage. In a simulation of a pumped system using a 5-volt power supply with NMOS diodes having a threshold voltage of 0.55 volts, and a body factor of 0.33 root-volts (body factor relates to the oxide thickness and doping, and determines the threshold at varying substrate voltages), the pumped voltages were as follows:
1-stage pump (doubler) 7.34 volts PA1 2-stage pump (tripler) 10.71 volts PA1 3-stage pump (quadrupler) 13.81 volts However, the circuits of FIGS. 3 and 4 generate unregulated voltages. The voltages generated by these circuits can vary considerably with both integrated circuit process variations and operating conditions. Regarding process variations, the manufacturing conditions week to week or from manufacturer to manufacturer produce variation from chip to chip. Fast silicon (with smaller diode drops) may cause a voltage tripler to generate too high a voltage, for example. Regarding variation in operating conditions, high temperature causes variations in voltage drop and on-resistance, and power supply voltage may vary from day to day or from site to site, producing corresponding variation in voltage generated by an unregulated voltage pump.
Because of these variations, a voltage doubler may generate insufficient voltage to achieve the desired benefits of the voltage pump, and a voltage tripler may generate a voltage which exceeds the transistor breakdown voltage. Thus, a voltage generator having a more reliable output voltage is needed.