For many of today's high speed input/output (I/O) interfaces for integrated circuits, large variations of I/O drive (or termination) strength result principally from variations in IC parameters, like variations in processing, voltage, and temperature (PVT variations), for example. Consequently, many integrated circuit I/O designs have incorporated PVT variation compensation circuits in the I/O drivers to factor out these variations. This results in output drive or termination strength varying by only a few percent rather than the approximately 50 percent variation that may occur ordinarily without such compensation.
There are numerous PVT variation compensation methods which may be implemented in the driver circuits of the I/O interface, either with analog control or with digital control. In either of these implementations, some number of external resistors are employed to give a current or voltage drive strength reference(s). Digital control implementations have gained popularity for their relatively simple and effective designs.
FIG. 1 is a block diagram schematic of a typical digital implementation of a pull-up portion of a PVT variation compensation circuit for use in compensating a digitally controlled integrated circuit (IC) I/O driver using a parallel combination of p-type field effect transistors (PFETs). In the implementation of FIG. 1, one or more external resistors R of the desired drive or termination impedance may be disposed on a printed circuit board (PCB) 4 and connected between a pin P, which is referred to as the IC PVT pin, of the integrated circuit 6 (enclosed by dashed lines) and ground GND 8.
A reference network of digitally controlled parallel PFETs 10 may be connected internal to the IC from the IC PVT pin P to an IC voltage supply Vdd. Generally, the number of PFETs in the reference network 10 is commensurate with the PFETs of the corresponding I/O driver, shown by block 11, which may be controlled by the same digital control lines 12. However, any number of PFETs may be used for the reference network 10 with more PFETs giving greater precision. In the present embodiment, when a control line is set to binary “1”, the corresponding PFET is “on” and driving and when set to a binary “0”, the corresponding PFET is “off” and not driving. In this manner, the strongest drive or termination strength would be controlled by the 5-bit digital control lines 12 set as a binary number “11111” (i.e. strength 2N−1). Accordingly, the reference network 10 would provide no drive when the lines 12 were set to the binary number “00000” (i.e. all PFETs turned off and not driving).
For example, for a 5-bit digital compensation implementation, the PFETs of the reference network 10 would be sized from the most significant bit (MSB) PFET to the least significant bit (LSB) PFET with strengths “N”, “N/2”, “N/4”, “N/8”, and “N/16”, respectively, N being related to the actual drive (or termination) strength or impedance of the PFET network. So, if it is desired to have a network drive impedance of 10 ohms, for example, when the binary code is “11111”, the PFET strengths or impedances of the network, i.e. “N”, “N/2”, “N/4”, “N/8”, and “N/16”, are chosen accordingly. Likewise, if the PFET network impedance was chosen to be 50 ohms at a binary code of “11111”, then N would be set differently.
Included in the implementation is a comparator 14 with one input (+) coupled to the IC PVT pin P and another input (−) coupled a reference voltage. The voltage at the IC PVT pin P provides a measure of the drive strength of the corresponding I/O driver. In the present example, the reference voltage is generated on the IC by a resistor divider network of two resistors R2 of the same value coupled between the voltage supply Vdd and ground 13. The node of the divider network, which is at Vdd/2, is coupled to the (−) input of the comparator 14 which compares the voltage at the IC PVT pin P to the internally generated reference voltage Vdd/2. Coupled to the output of comparator 14 is binary counter logic 16 which may include an up/down counter 18 to produce the digital binary setting of lines 12.
In operation, if the voltage at the IC PVT pin P increases above the reference voltage Vdd/2, the comparator 14 results in a comparison state to control the up/down counter 18 in the PVT counter logic 16 to count down (i.e. the drive strength is becoming too strong). Similarly, if the voltage at the IC PVT pin P decreases below the reference voltage Vdd/2, the comparator 14 results in a comparison state to control the up/down counter 18 in the PVT counter logic 16 to count up (i.e. the drive strength is becoming too weak). In the present example, the up/down counter 18 may be controlled to count up or down by a sampling of the state of the output of comparator 14. Since, the “time constant” of temperature and voltage changes is relatively long, the sampling frequency the counter operates at may be set generally at some frequency lower than normal functional clocks of the IC. However, it is understood that more sophisticated “filter” circuits may be designed into the logic 16 such that some number of consecutive “count down” or “count up” samples of the output of comparator 14 would be filtered to actually change the counter 18.
The corresponding I/O driver may use the identical number of parallel PFETs as the reference network 10. That way, whatever binary code over lines 12 that resulted from a voltage comparison between the reference Vdd/2 and the voltage at the PVT pin P would also produce the proper impedance for each I/O driver. Of course, the digital control for the PFETs in the corresponding I/O driver may be further qualified with a functional control that determines whether a “1” or “0” should be driven. The sampling of the comparison result of comparator 14 may be performed periodically as noted above, and the drive strength of the I/O driver updated over lines 12 periodically as a result.
A drawback of the foregoing described implementation is that it provides one, and only one, operating point as determined by the chosen value of the external resistance R. Accordingly, the operating point cannot be further tuned for operational variations, such as bus loading, for example.