A typical circuit may distribute one or more clock signals to one or more local circuits that may be included in or separate from the typical circuit. Such circuits may be included on an Application Specific Integrated Circuit (ASIC), a Printed Circuit Board (PCB), or any circuit known to one skilled in the art. Each of these clock signals have a duty cycle, which may be defined as the fraction of the clock cycle's period in which the clock signal is active. Ideally, these clock signals have a duty cycle of 50 percent. However, these clock signals can become distorted due to various considerations, such as noise or physical process. As such, a technique is needed to correct the duty cycle of such clock signals to be closer to the ideal of 50 percent.