The present invention relates generally to semiconductor integrated circuits having redundant vias and, more particularly, to a method and system for performing accurate timing analysis of integrated circuits having redundant vias.
Vias are openings or conductive lines formed in dielectric layers of a semiconductor chip. The dielectric layers insulate conductive layers, which contain circuit elements, such as transistors. In present day chips, millions of vias may be used to form a complex system of interconnections for circuit elements located in stacks of conductive layers. FIG. 1 shows a single via 10 connecting a first metal layer 12 to a second metal layer 14.
To improve the speed and performance of a chip, engineers constantly strive to design circuits that are more compact so that more circuit elements may be placed in the chip. One way to achieve these goals is to increase via density and decrease via size. However, a major problem with shrinking via dimensions is that even the slightest manufacturing error may cause a via to fail. For example, if the via is too small, it may not provide a suitable electrical connection between two conductive layers. Integrated circuits typically include a number of critical vias. One example of a critical via is a via that provides the only electrical connection between two conductive layers. Such a via is also referred to as a “stand-alone” or “single transition” via. The failure of a critical via may render the entire integrated circuit inoperable and cause great financial loss.
One method of increasing the functional yield of the integrated circuit and reducing the risk of via failure is to add redundant vias to the circuit. Redundant via software may be used to scan the circuit to determine suitable locations for forming additional vias in close proximity to a critical via. If a suitable location is found, then a redundant via may be formed and connected in parallel with the critical via. Thus, if the critical via fails, the redundant via acts as a backup so that the critical electrical connection is not lost. FIG. 2 shows a redundant via 16 located proximate to the via 10.
Another method of reducing the risk of via failure is to form fat vias. FIG. 3 shows a fat via 18. The fat via 18 includes the via 10 as well as a metal extension 20. Though the use of redundant and fat vias has resulted in improved integrated circuit yield, the presence of the additional vias may have a number of adverse effects. For example, because each redundant via adds a metal track to the chip, the capacitance of the surrounding region may be undesirably altered. Additionally, redundant vias may disrupt the timing of the circuit, upon which many electronic devices rely, particularly since it is difficult to determine whether both or only one via is functioning after manufacturing is complete.
If both vias are functioning, then the resistance of the via pair would be only half of the resistance if only one via is functioning. In addition, the disparity between the two resistances varies throughout the circuit, particularly between maximum capacitance corners and minimum capacitance corners. For example, the difference between double and single vias is particularly pronounced at maximum capacitance extraction corners, where the ratio of metal to via resistance is smaller.
Because the number of functioning vias is difficult to predict when a via has been duplicated, it is likewise difficult to predict what effect the vias may have on various aspects of circuit timing, such as stage delay, output transition time, and ripple effect of signal slews. In some cases, circuit timing may be improved, but in other cases, the timing may be worse. Unfortunately, because the results are unpredictable, it is very difficult to compensate for timing problems and violations. In addition, because the addition of redundant vias typically occurs during design rule checking and chip finalization, most of the routes are frozen before the timing errors are discovered and thus difficult to correct.
After an integrated circuit is designed, it is typically tested and analyzed to ensure that the circuit will not violate the timing constraints of the design. One method commonly used to test and verify the timing performance of the circuit is static timing analysis (STA). To ensure proper circuit operation, the design is first subject to physical synthesis to lay out the circuit at the gate level, followed by interconnect routing and parasitic extraction. STA is then used to identify the various timing paths of the circuit and then analyze signal propagation delay over the paths.
Typically, a longest path analysis and a shortest path analysis are performed on the circuit to determine whether a signal arrives during the active pulse of a clock. If the signal arrives in time, then the timing constraints of the path are met and a timing violation is avoided. The amount of time by which the violation is avoided is referred to as the slack, which is also an indication of the margin of error from the timing violation. If the signal does not arrive in time, then there is a timing violation, which results in a negative slack.
As described previously, via doubling is generally used in locations of a semiconductor chip where the chances of via failure are high. However, via doubling has the disadvantages of it being difficult to predict how many vias are functioning and therefore the resistance of the vias, and the presence of redundant vias alters the capacitance of the circuit, which may affect signal propagation at certain circuit pathways. Thus, when an integrated circuit includes redundant or fat vias, which is increasingly common, the risk of timing violations is greatly increased.
Accordingly, it would be desirable to have a method and a system for performing accurate timing analysis on integrated circuits that have redundant and fat vias regardless of whether only one or both of the critical and redundant vias are functioning.
Those skilled in the art will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.