The present disclosure generally relates to using test cases to verify and validate a processor, and more specifically, to techniques for scheduling test cases without regeneration to verify and validate a computing system.
For many years, the performance of a computing system was typically increased by increasing the clock speed or processor frequency of the computing system. In recent years, however, with limitations in frequency scale up, increases in computing performance are now typically associated with increases in the number of cores in a chip and/or the number of chips in a given computing system. Most of these computing systems are symmetric multiprocessor (SMP) systems with distributed shared memory where each chip has its own local memory (e.g., cache). Shared memory systems usually contain a hierarchy of caches where the lowest cache levels are private to each individual processing unit and the last level cache is shared among all the processing units. In such memory systems, it is important to ensure the local caches are in sync, e.g., to prevent processing units from processing old data.
Before processors are shipped out to customer(s), chip manufacturers typically employ processor testing tools to screen for defective chips (or chips that do not meet performance requirements) that are produced from the manufacturing process. These testing tools typically use a wide variety of test patterns to verify and validate a system design for a processor. The goal of such tools is typically to generate the most stressful test pattern for a processor to ensure that the processor will meet the customer's performance requirements. In theory, the generated test pattern should provide maximum test coverage and should stress various timing scenarios on the processor. As such, a large amount of test cases are usually generated in order to sufficiently test a processor.
Verifying and validating a processor using test pattern(s) generally includes three stages: (1) a test pattern generation stage; (2) a test pattern loading stage; and (3) a test pattern execution stage. Each test pattern can include one or more test cases, and each test case can include one or more instructions. One challenge is that during the test pattern generation stage, it is typically difficult to create test generators that can efficiently verify and validate snoop filtering mechanisms for computing systems with multiple processors. For example, validating such mechanisms requires the generation of large amounts of test cases that can span the different states associated with the coherency protocol. Generating such a large amount of test cases requires a significant amount of test pattern generation time, which reduces the amount of time available for other stages (e.g., executing stage, etc.) of the testing process.