1. The Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection circuit. More particularly, the present invention relates to an ESD protection circuit, which can improve the response speed by detecting an ESD signal with a circuit technique, and can maintain the deep current path by using a gate-modulated field-oxide device, so that this design can effectively improve ESD robustness.
2. Description of the Related Art
Electrostatic discharge (ESD) can easily damage IC devices such as DRAMs and SRAMs during both manufacture and operation. A person walking on a carpet, for instance, can carry up to several thousand volts of electrostatic charge under high relative humidity (RH) conditions and over 10,000 volts under low RH conditions. If such a person touches an IC package, the electrostatic charge on his/her body is instantly discharged to the IC package, thus causing ESD damage to the internal circuitry of the IC package. A widely used solution to this problem is to provide an on-chip ESD protection circuit around each I/O pad of the IC package.
One drawback to the prior art, however, is that when the IC device is fabricated by scaled down technology, such as the deep-submicron CMOS process, the gate-oxide structure is reduced in thickness. This causes the breakdown voltage of the gate-oxide structure to be close to or below the breakdown voltage at the source/drain junction, thus degrading the ESD protection capability. The internal circuitry of an IC device is typically drawn in accordance with the Minimum Design Rules. Therefore, the various semiconductor components of an IC device are designed to have the minimum size. This practice, however, makes some components vulnerable to ESD stress, when these components are further scaled down. For this reason, a highly-integrated IC device fabricated at the deep-submicron process is particularly vulnerable to ESD. Therefore, in the IC industry, much research effort has been directed to ESD protection for integrated circuitry.
FIG. 1A is a circuit diagram for a conventional ESD protection circuit. As shown in FIG. 1A, in order to protect the internal circuit 10, the ESD current imported through an input port INP is discharged through an NMOS transistor 12 to a ground VSS. FIG. 1B is a schematic circuit diagram of another conventional ESD protection circuit. As shown in FIG. 1B, in order to protect the internal circuit 18, the ESD current can be discharged not only through an NMOS transistor 14 to the ground VSS but also through a PMOS transistor 16 to a voltage source Vdd.
The conventional ESD protection circuits as described above and shown in FIGS. 1A and 1B both utilize junction breakdown voltage to protect an internal circuit from damage. However, when the IC device is fabricated at a scaled down CMOS process and the gate-oxide structure is accordingly reduced in thickness, some problems arise; for example, the breakdown voltage of the gate-oxide structure happens earlier than the junction breakdown voltage at the source/drain junction. In other words, if the breakdown voltage of the gate-oxide structure happens earlier than the junction breakdown voltage at the source/drain junction, then the conventional ESD protection circuits as shown in FIGS. 1A and 1B lose their protection ability.
FIG. 2 is a circuit diagram for another conventional ESD protection circuit. As shown in FIG. 2, the ESD protection circuit 20 comprises NMOS transistors 22 and 24, a PMOS transistor 26, a resistor (R) 28 and a capacitor (C) 30. In NMOS transistor 22, the drain is coupled to a voltage source Vdd, the source is coupled to ground VSS, and the gate is coupled to a first node B. In NMOS transistor 24, the drain is coupled to the first node B, the source is coupled to the ground VSS, and the gate is coupled to a second node A. In PMOS transistor 26, the source is coupled to the voltage source Vdd, the drain is coupled to the first node B, and the gate is coupled to the second node A. The resistor 28 is connected between the voltage source Vdd and the second node A, while the capacitor 30 is connected between the second node A and the ground VSS.
The operation method for the conventional ESD protection circuit 20 as shown in FIG. 2 is described as follows. For example, a situation of positive ESD stress is considered. When the positive ESD stress occurs, because of the resistor-capacitor delay (RC delay), i.e. the ESD stress on the voltage source Vdd increases rapidly and is faster than the RC time constant, and the voltage on the node A increases very slowly corresponding to the voltage source Vdd, the node A is not yet established in the positive potential. As a result, PMOS transistor 26 is turned on. Meanwhile the ESD current can be drained from PMOS transistor 26 to the gate of NMOS transistor 22, so that NMOS transistor 22 can be turned on early and the ESD current is discharged through the NMOS transistor 22 to ground VSS. In spite of the protection of NMOS transistor 24, such design requires a device with larger dimensions and size. In addition, the relative applications can refer to U.S. Pat. No. 5,744,842.
The invention provides an electrostatic discharge protection circuit. The electrostatic discharge protection circuit comprises a gate-modulated field-oxide device, an NMOS transistor, a PMOS transistor, a resistor and a capacitor. In the gate-modulated field-oxide device, the drain is coupled to a voltage source, the source is coupled to ground, and the gate is coupled to a first node. In the NMOS transistor, the drain is coupled to the first node, the source is coupled to the ground, and the gate is coupled to a second node. In the PMOS transistor, the source is coupled to the voltage source, the drain is coupled to the first node, and the gate is coupled to the second node. The resistor is connected between the voltage source and the second node and the capacitor is connected between the second node and the ground. Additionally, the gate of the gate-modulated field-oxide device is further connected to the substrate so as to raise the substrate voltage.
Additionally, the invention provides an electrostatic discharge protection circuit, which comprises a gate-modulated field-oxide device, an NMOS transistor, a PMOS transistor, a resistor and a capacitor. In the gate-modulated field-oxide device, the drain is coupled to a voltage source, the source and the gate are coupled to the ground, and the substrate is coupled to a first node. In the NMOS transistor, the drain is coupled to the first node, the source is coupled to the ground, and the gate is coupled to a second node. In the PMOS transistor, the source is coupled to the voltage source, the drain is coupled to the first node, and the gate is coupled to the second node. The resistor is connected between the voltage source and the second node and the capacitor is connected between the second node and the ground.
The gate-modulated field-oxide device according to the present invention is formed on a substrate and comprises: an isolation structure formed in the substrate, a gate electrode formed over the isolation structure and isolated from the substrate by a gate oxide layer, a drain region in the substrate at one side of the gate electrode, a source region in the substrate at the other side of the gate electrode, a deep N-well region in the bottom of the substrate and an n-well region which is formed in the substrate between the source region and the deep N-well region.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides an electrostatic discharge protection circuit, which forms a field-oxide region between the drain region and the source region. The surface channel between the drain region and the source region is broken because of the field-oxide region, so the whole ESD current is then discharged via the substrate to the ground by using the gate-modulated field-oxide device of the present invention, and the potential endurance of ESD device can be improved. Additionally, the present invention utilizes circuit technology to detect an ESD signal so that the response speed can be increased. Furthermore, the present invention can maintain a deep current path due to the gate-modulated field-oxide device, therefore the device size used for ESD protection can be reasonably reduced. Moreover, the present invention also can be used with input or output pad protection circuits, so that the dimension and size of a device can be decreased and the input or output capacitor of a device can be reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.