Some computer systems incorporate multiple processors that run simultaneously on a common host bus. A host "chipset", which usually includes several host chips, is used for system control to connect (or "bridge") the processors to memory and various busses (e.g., PCI1, PCI2, IDE).
FIGS. 1A through 1C show dual-processor configurations with conventional host bus routing schemes. A host bus, which includes an address/control bus 8 and a data bus 9, interconnects processors 3 and chips 7 (from a host chipset) to one another. (Dashed lines 8 and darkened lines 9 generally represent bus routing paths for the address/control and data busses, respectively.) Each processor 3 has a contact grid which includes two rows of electrical contacts: A1-A121 and B1-B121. The electrical contacts are divided into an address/control section 4 and a data section 5. In turn, as is depicted in FIG. 1A and 1B with host chips 7 from an Intel 440FX.TM. chipset and an Intel Orion.TM. chipset, respectively, dedicated host chips, which connect either to the address/control bus 8 or to the data bus 9, are used with conventional dual-processor arrangements. The processors 3 are typically configured into a spaced-apart pair, with their contact grids oriented in the same direction. Between processors 3, host chips 7 are located proximate to their connected contact grid sections so as to minimize the data bus 9 and address/control bus 8.
As noted above, orienting the contact grids of a pair of processors in the same direction is conventional design. It appears that this design was chosen for two primary reasons.
First, it is logically somewhat simpler for a human designer to have two complex sets of contacts placed in a common orientation. The designer can count on the same pins being in the same location with no mental transformation required in planning the connections to both chips. That is, the array of data pins on each processor is aligned with the corresponding array on the other processor and individual pins are also aligned. Likewise, the arrays and the individual pins of the address/control sections are also aligned.
Second, as seen in FIGS. 1A and 1B, to the extent bus connections can run from the data section of one processor to the data section (or address/control section) of the other processor with only one or two connections to dedicated chips in between, the high level layout is easier to visualize.
However, improvements in chipset design have led to chipsets that incorporate multiple non-dedicated chips, which require connections to both the host data and host address/control busses. Unfortunately, as seen in FIG. 1C (with chips 5 from a Micron Samurai.TM. chipset) such chipsets cause bus routings to increase in length and become more congested, which results in multiple bus crossovers. Extra board layers may be needed to accommodate these crossovers. Moreover, longer bus traces not only consume excessive board space, but also increase noise problems that are associated with line reflections.
In addition, when dual processors are mounted in vertical packages (e.g., single edge cartridges) with their contact grids oriented in the same direction, their heat dissipation surfaces (along with associated heatsinks) will normally face the same direction. Cooling both heatsinks requires either a sufficiently wide fluid stream or two separate fluid streams to adequately encounter each processor's heatsink. Thus, excessive board space is consumed to accommodate a wide fluid propeller (or propellers) for generating such a fluid stream(s).
It will be evident that the conventional configuration of paired processors facing the same direction is just one possible choice. The processors could be placed in a variety of spacial configurations relative to each other, by selecting from all the different rotational, distance and angular options available. However, each selection has implications for thermal, mechanical, and electrical design.
Accordingly, what is needed in the art is a dual processor arrangement with improved host bus routings and an improved scheme for cooling the processors.