The electrical performance of an integrated circuit is influenced by several different parameters. Included in this parameter set for a metal-oxide-semiconductor device are effective gate length, gate dielectric thickness, and channel doping. Integrated circuit designers typically expect an integrated circuit to operate optimally when it is fabricated in the center of the electrical and physical design rule specifications. Frequently, however, experience has shown that integrated circuit designs tend to work best in other portions of the operating design space, sometimes even at the limits of the intended operating design space.
One of the parameters that has a dramatic effect on device performance is drive current, which is affected by effective gate length of the metal-oxide-semiconductor transistor. Since it is known that the operation of a new integrated circuit design tends to be heavily influenced by the effective gate length, a customer may sometimes request that the design prototype integrated circuits be produced with several different gate lengths, so as to determine the optimum gate length for the new integrated circuit design.
This typically requires that several wafers be processed, where the integrated circuits on the different wafers are fabricated with different gate lengths, so as to span the breadth of the critical dimension specification for gate length. After testing the integrated circuits with different gate lengths from the various wafers, the effect of gate length on the performance of the integrated circuit can be determined. In the past, and for a standard application specific integrated circuit, this method tended to be acceptable since all prototype integrated circuits were fabricated using unpatterned silicon wafers as the starting point of processing, with the entire fabrication process conducted as a part of the initial prototype product.
However, newer application specific integrated circuit designs, such as LSI Logic Corporation's RapidChip technology, are similar to a gate array technology in that they rely on customization of the metal interconnect layers to meet customers' complex design requirements. Thus, a new design of such an application specific integrated circuit starts with a base wafer having complex cells, memory arrays, and gate arrays that were previously characterized. This technology is called cell-based array, and provides dramatic benefits, including the sharing of at least the design and tooling cost for the fabrication of the base wafers up to the point of customer design customization, in that many customers can use the same base wafer design as a starting platform from which to design their customized products. This results in lower costs for design and manufacturing of customized product designs, and provides customers with more affordable solutions as mask costs continue to increase. This technology also enables the customized integrated circuit designs to be fabricated with a shorter lead time, since the customized integrated circuit design is created from the point where customized metallization begins.
For products such as gate array designs, cell-based array designs, and other designs that are configured relatively late in the fabrication process, performing critical dimension skews, such as on gate length, in the normal manner as described above would actually tend to result in both a longer lead time for completion of the customized design and a higher overall cost, since an increased number of masking layers would actually be required to complete the wafers, as compared to the baseline preprocessed wafers described above. As a point of fact, the metal-oxide-semiconductor transistor gate patterning step is performed very early in the fabrication process, so most of the benefits of speed and cost as described above would be lost by employing the conventional approaches described above to provide customized integrated circuits with different gate lengths that are distributed across the process design specification.
What is needed, therefore, is a system by which process skews can be created and evaluated without losing most of the cost and time savings benefits of the baseline preprocessed application specific integrated circuit technologies.