The present inventive concept relates to a semiconductor memory device and memory system. More particularly, the present inventive concept relates to a variable resistance memory device and memory system incorporating same.
Demand is increasing for a semiconductor memory device capable of randomly accessing non-volatile stored data and being highly integrated to yield large data storage capacity. A typical example of such a semiconductor memory device is flash memory commonly used in portable electronic devices, for example. As an alternative to flash memory, certain variable resistance memory devices providing non-volatile data storage have been proposed as replacements for volatile memory devices such as the conventional DRAM.
Exemplary variable resistance memory devices include the Ferroelectric RAM (FRAM) utilizing a ferroelectric capacitor, Magnetic RAM (MRAM) using tunneling magneto-resistive (TMR) layer, and phase change memory device using chalcogenide alloys. Of these, the phase change memory device enjoys relative advantages in its relatively simple fabrication process, large data storage capacity, and relatively low cost of fabrication.
FIGS. 1 and 2 schematically illustrate memory cells for variable resistance memory devices. Referring to FIG. 1, a memory cell 10 includes a memory element 11 and a select element 12. The memory element 11 is connected between a bit line BL and the select element 12, and the select element 12 is connected between the memory element 11 and a ground.
The memory element 11 includes a variable resistance material (e.g., an alloy of Ge—Sb—Te or “GST”). Such variable resistance materials exhibiting a resistance that varies in relation to an applied temperature. The variable resistance material is characterized by two stable states (a crystalline state and an amorphous state), each induced by a particular temperature application. The state of the variable resistance material may be varied according to a current supplied via the bit line BL. The variable resistance memory device programs data using the state-disparate resistance characteristics of the variable resistance material.
The select element 12 includes an NMOS transistor NT. A word line WL is connected to a gate of the NMOS transistor NT. When a predetermined voltage is supplied to the word line WL, the NMOS transistor NT is turned ON. When the NMOS transistor NT is turned ON, a current is supplied to the memory element 11 via the bit line BL. Referring to FIG. 1, the memory device 11 is connected between the bit line BL and the select element 12. However, the select element 12 may be connected between the bit line BL and the memory element 11.
Referring to FIG. 2, a memory cell 20 includes a memory element 21 and a select element 22. The memory element 21 is connected between the bit line BL and the select element 22, and the select element 22 is connected between the memory element 21 and ground. The memory element 21 is configured identically with the memory element 11 of FIG. 1.
The select element 22 is a diode D. The memory element 21 is connected to an anode of the diode D, and a word line WL is connected to a cathode thereof. When a voltage difference between the anode and cathode of the diode D becomes higher than a threshold voltage, the diode D is turned ON. When the diode D is turned ON, a current is supplied to the memory element 21 via the bit line BL.
FIG. 3 is a graph generally illustrating the respective temperature/time characteristics (or temperature conditions) for programming (i.e., changing the state) of the variable resistance material of FIGS. 1 and 2. In FIG. 3, a reference numeral 1 indicates a first temperature condition placing the variable resistance material into the amorphous state. Reference numeral 2 indicates a second temperature condition placing the variable resistance material into the crystalline state.
In the first temperature condition, the variable resistance material is heated by a temperature higher than its melting temperature (Tm) for a first time period (T1), then quickly quenched into the amorphous state. Conventionally, the amorphous state is assigned a reset data state, or a data value of ‘1’. The variable resistance memory device provides a so-called “reset current” to the variable resistance material in order to program it to the reset state.
In the second temperature condition, the variable resistance material is heated by a temperature higher than its crystallization temperature (Tc) but lower than the melting temperature (Tm) for a second time period (T2) longer than T1. Then the variable resistance material is cooled relatively slowly into the crystalline state. The crystalline state is conventionally assigned a set state, or a data value of ‘0’. The variable resistance memory device provides a so-called “set current” to the variable resistance material in order to program it to the set state.
Moving from the foregoing discussion of variable resistance memory devices, a NOR flash memory may generally be used to store frequently updated data, such as meta data. NOR flash memory thus supports random data using a relatively small unit (e.g., 16 bits) to enable rapid data access. Moreover, NOR flash memory is capable of accessing data without address mapping by means of a flash translation layer (FTL).
On the other hand, NAND flash memory may be used to effectively store large quantities of less frequently updated data, such as so-called user data. In order to access data stored in NAND flash memory, a FTL is required to map addresses. The FTL converts a physical address to a logical address, or vice versa. NAND flash memory performs access operations in page units and does not support random data access. Therefore, NAND flash memory is not suitable for use in accessing data in small unit sizes, but is advantageous in accessing large blocks of data. Due to such characteristics, NOR flash memory and NAND flash memory are used for different purposes, and NOR flash memory and NAND flash memory are typically both required to effectively store code data (or meta data) and user data.
FIG. 4 is a block diagram of a general computer system including both NOR flash memory and NAND flash memory. Referring to FIG. 4, a NOR flash memory 110 is connected to a system bus 150 via a NOR controller 120. A NAND flash memory 130 is connected to the system bus 150 via a NAND controller. As such, both the NOR controller 120 and the NAND controller 140 are required in a system having both the NOR flash memory 110 and NAND flash memory 120. This requirement increases the overall manufacturing cost for the semiconductor memory device, and adversely affects integration density of the device.