In a semiconductor memory having a C-MOS D-RAM, the address signal, which is applied through an external input pin, is applied at a TTL voltage level.
For an input voltage of the address logic being of a TTL level, a circuit changes the voltage of the address logic level of the incoming TTL level into a C-MOS address logic level capable of operating the inner semiconductor memory device on the address input end.
In general, the TTL typically defines a logic "0" as being less than 0.8 volts, and a logic "1" as being in excess of 2.4 volts.
Accordingly, for C-MOS operation, a logic level voltage of less than 0.8 volts incoming as TTL is made to be 0 volts, and a voltage in excess of 2.4 volts is changed into a level of 5 volts, but a given trip point is placed between above 2.4 volts and 0.8 volts, taking into consideration the change margin of the power source voltage.
In a semiconductor memory device having a C-MOS D-RAM as described above, the column address buffer, which had been used in the prior art, is provided for a circuit as shown in FIG. 1.
In a conventional C-MOS column address buffer, as shown in FIG. 1, the buffer structure will be described as follows.
A Schmitt trigger circuit is comprised of the connection of the P-MOS transistors 1 and 2, and the N-MOS transistors 3, 4, 5 and 6. Series connected P-MOS transistors 1 and 2 and the series connected N-MOS transistors 3 and 4 are connected at the node 24.
Further, the source of said P-MOS transistor 1 is connected with the power source voltage Vcc and that of the N-MOS transistor 4 is connected to ground voltage Vss (0 volt). The gates of the P-MOS transistor 2 and N-MOS transistors 3 and 4 are coupled to the input address signal Ai through the line 23, and the output line of the node 24 is connected with the gate of N-MOS transistor 5 for providing feedback, and, at the same time, with the drain and source of N-MOS transistor 6 coupled between the node 24 and the ground voltage Vss. The source of said N-MOS transistor 5 is connected to the series contact 25 of the N-MOS transistors 3 and 4.
Also, the drain of the transistor 5 is connected to the power source supply voltage Vcc, and the gates of the P-MOS transistor 1 and the N-MOS transistor 6 are connected to an input terminal of the Schmitt trigger circuit 100 and receiving an inverted input of the signal .phi..sub.CAL from inverter 110 comprised of series connection of the N-MOS transistors 7 and 8 coupled between the power source supply voltage Vcc and the ground voltage Vss. An inverter 120 comprised of the D-MOS transistor 9 and the N-MOS transistor 10 buffers the column address signal having a C-MOS level generated at the node 24 of said Schmitt trigger circuit 100. A transmission gate 130 which is comprised of the parallel connection of the P-MOS transistor 11 and the N-MOS transistor 12 transfers the output of the inverter 120 when a column address strobe signal CAS on line 36 becomes active. C-MOS inverters 150, 160 and 170 are connected in series to the output line 27 of the transmission gate 130.
Furthermore, the input line 28 of the inverter 160 is fed to the inverter 180 through the line 31, and the input line 29 of the inverter 170 is connected with the line 27 through the line 30 and the transmission gate 140 which is comprised of the parallel connection of the C-MOS transistor 13 and the N-MOS transistor 14.
Accordingly, when the column address strobe signal CAS on line 36 is not in the active or high state (.theta..sub.CAL equals "low" state), the transmission gate 140 is conductive. Thus the logic state on the line 33 is latched "low" and that on the line 32 "high" as shown in FIG. 2.
However, in a conventional C-MOS D-RAM, the column address signal Ai is fed from the column address input pin after said column address strobe signal CAS is fed from the input pin. Accordingly, a conventional column address input buffer circuit as shown in FIG. 1 has problems with glitches 34 and 35 of FIG. 2 which take place on output lines 32 and 33 before the column address signal Ai is outputted and after said column address strobe signal CAS becomes "low" as shown in the operation timing diagram of FIG. 2. That is, when the column address strobe signal CAS is in a "high" state (.phi..sub.CAL : "low" state), the output line 36 from the inverter 110 has a "high" state and the N-MOS transistor 6 is conductive. Accordingly, the input of the inverter 120 assumes a "low" state and output line 36 is held in a "high" state. Then, when the signal .phi..sub.CAL of the column address strobe signal is inverted and becomes a "high" state (then the signal CAS is in a "low" state), the output of said inverter 110 becomes a "low" state and the transmission gate 130 becomes conductive.
Thus, the signal of a "high" state on said line 26 is transferred on the line 27 and lines 32 and 33 have "low" and "high" states, respectively. Then, the P-MOS transistor 1 has an "ON" state according to the "low" state on line 36, the output signal of said inverter 110. The N-MOS transistor 6 is in an "OFF" state and the input line 23 has a "low" state.
Accordingly, the P-MOS transistor 2 has a saturated state and the node 24 is in a "high" state.
Thus, the output line 26 of the inverter 120 is in a "low" state and the signals of the lines 32 and 33 are in "high" and low" states, respectively, being applied through the transmission gate 130.
Accordingly, the Schmitt trigger circuit 100 becomes operative after said signal CAS is in a "low" state, and the glitches 34 and 35 of FIG. 2 are produced with like amounts of delay time until the node 24 is in a "high" state, and the address signal is produced and the undesired problems, which should be obviated, take place.