Memory devices are typically manufactured many at a time. After manufacture, they are typically packaged and tested. Many current mechanisms for testing memory devices rely on a set of serial operations performed one at a time using expensive memory testers. One such mechanism is illustrated by FIGS. 1A and 1B.
FIG. 1A is a prior art memory test configuration. Memory testing configuration 100 includes tester 110 and memory devices 102, 104, and 106. Memory tester 110 includes bidirectional channels and drive-only channels. Bidirectional tester channels are channels that can source and sink data, and drive-only tester channels are channels that only source data, and do not sink data. Drive-only channels include channels 112, 114, 116, 118, and 122. Each of these drive-only channels drive inputs on memory devices being tested. For example, drive-only channels 112, 114 and 116 drive “output enable” nodes of memory devices 102, 104, and 106, respectively. Drive-only channel 118 drives the “write enable” node on each of the memory devices in parallel. Drive-only channel 122 includes multiple physical channels, and drives the address bus.
Bidirectional tester channel 120 includes “n” physical channels, and is coupled to the data bus of each device to form a shared data bus. This configuration shares the data bus across all memory devices being tested, and allows the bidirectional tester channels to be time shared among multiple memory devices being tested.
FIG. 1B shows an example sequence of operations performed by the memory test configuration of FIG. 1A. The sequence of FIG. 1B include operations 152, 154, 156, 158, 160, and 162. Operation 150 represents the memory command being tested. For example, operation 152 can be a “write” command during which data is written to a location being tested. The data is written to all three memory devices in parallel by virtue of the shared data bus and write enable signal as described above. During operations 154, 156, and 158, the status of memory devices 102, 104, and 106, respectively, is read. The time taken to read the status registers is shown at 164.
Operation 160 repeats operations 154, 156, and 158 until all three memory devices report a status that indicates the command issued in operation 152 is complete. When all three memory devices report the appropriate status, operation 162 verifies that operation 152 was successfully executed. For example, for the case where operation 152 is a write command, operation 162 is a read operation that reads the data from the appropriate location, and compares it with the data written in operation 152.
One drawback of the configuration of FIG. 1A is shown by the serial polling of status shown at 164. The time taken by serial polling increases as more memory devices are added to the test, and the total time increases further for each time the polling sequence is repeated in operation 160.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternate methods and apparatus for testing memory devices.