Digital logic circuits are based on logic gates that adhere to mathematical logic and Boolean algebra. Mathematical logic provides tools to reason about the truth of a set of statements, each of which may be true or false. Boolean algebra is an algebraic system for manipulating logic statements. Logic gates are building blocks for integrated circuits that implement various logic operations, such as AND, OR, NOT, Not OR (“NOR”), and the like. These logic gates are themselves formed using basic electrical switches called transistors.
Logic gates may be formed using complementary metal oxide semiconductor (“CMOS”) technology or ratioed logic technology. CMOS logic gates provide good HIGH LEVEL and LOW LEVEL outputs, but tend to be slow. On the other hand, ratioed logic is faster but can generate detrimental non-zero LOW level outputs or poor HIGH level outputs, as the case may be.
FIG. 1 illustrates a known implementation of a four input ratioed NOR gate 100. A NOR gate implements the Boolean NOR logical operation that is true if all inputs are false, and false if any input is true. Ratioed NOR gate 100 is formed using ratioed-logic. A ratioed-logic NOR gate includes parallel pull up PMOS (positive type metal oxide semiconductor) transistors coupled to parallel pull down NMOS transistors. For various input combinations, one or more of the PMOS transistors and one or more of the NMOS transistors can be simultaneously ON. In other words, the pull up transistors can be in contention with the pull down transistors over the value of the output node.
During this contention state, the output node generates a non-zero LOW level, otherwise known as a contention level. The magnitude of this output contention level is directly proportional to the resistance ratio of the simultaneously ON pull up and pull down transistors. The duration of this contention state is equal to the time the inputs remain in a contention producing combination. For this reason the output of a ratioed NOR gate behaves like a DC (steady state) noise source when in the contention state. This DC noise source can compromise the signal integrity of downstream circuitry.
Typically, the output of a ratioed NOR gate is coupled to a gate terminal of a transistor in the next stage or receiving stage. If the non-zero LOW level is above the threshold voltage for the transistor, then the otherwise OFF transistor will turn ON resulting in the generation and propagation of an erroneous value. However, even if the ratioed NOR gate output contention level is below the threshold voltage for the receiving transistor, the non-zero LOW level or (DC noise source) may still detrimentally impact downstream circuitry. This detrimental impact results from transistor sub-threshold conduction. Contention induced non-zero LOW levels can account for significant conduction currents through an OFF receiving transistor. Contention induced currents are increasingly more problematic with each successive semiconductor process generation.
Currently, the magnitude of the output contention level is reduced by appropriate downsizing of the PMOS pull up transistors, thereby bring the contention induced non-zero LOW levels closer to zero. However, downsizing the PMOS pull up transistors detrimentally increases the pull up delay.