It is known to arrange a plurality of memory chips, e.g. chip M5M4256L manufactured by Mitsubishi, into a dynamic RAM array. The pin configuration of the known M5M4256L chip is shown in FIG. 1.
The M5M4256L chip is a 16 pin zigzag inline package (ZIP), including 9 address inputs A.sub.0 -A.sub.8, a data input D, a data output Q, a write control input (write enable/w), a column address strobe input CAS, a row address strobe input (C/RAS), a 5-volt input V.sub.cc and a ground input V.sub.ss. The block diagram of the M5M4256L chip is shown in FIG. 2.
To select one of the memory cells in the M5M4256L chip, an 18-bit address signal must be multiplexed into two 9 bit address signals, which are sequentially latched into the on-chip address buffer by two externally applied clock pulses. First, the negative-going edge A (see FIG. 3A) of the active low row address strobe input pulse latches the 9 row address bits; then the negative-going edge B of the active low column address strobe input pulse latches the 9 column address bits. The row and column strobe input pulses function to select the chip to be accessed. In other words, only certain chips (i.e. the selected chips) in an array of chips have both their row address bits and the column address bits latched into their on-chip address buffers.
in FIGS. 3A-3C the signal levels are denoted by voltage V.sub.H (the high level) and voltage V.sub.L (the low level). In the M5M4256L chip, V.sub.H is in the range 2.4 V to V.sub.cc (4.5-5.5 V) and V.sub.L is in the range 0 to 0.4 V. Also, its should be noted that the crosshatching in FIGS. 3A-3C indicates that the level of the signal does not matter, and the center line between the high and low levels for output Q indicates the high-impedance state.
In the write mode, data to be written into a selected cell is strobed by the later of the negative transition of the W input and the negative transition of the column address strobe input. In the case of the "early write" mode of the M5M4256L chip (see FIG. 3B), the write control input goes low (transition C in FIG. 3B) prior to the column address strobe input going low (transition B), so the date input D is strobed by the negative-going transition of the column address strobe input pulse. In other modes (i.e. the read-write and read-modify-write modes shown in FIG. 3C), the data input is strobed by the negative transition of the write control input (transition C in FIG. 3C).
The output of the M5M4256L chip is in the high-impedance state when the column address strobe input is high. In the read or read-write mode, the data output goes to the active conditin at the access time t.sub.acc and the data in the selected cell can be read. This data output will have the same polarity as the input data. Once the output has entered the active condition, this condition will be maintained until the column address strobe input goes high, irrespective of the condition of RAS.
The above-described M5M4256L chips are conventionally closely arranged in an array of rows and columns. A typical column of such an array is depicted in FIG. 4. In such an array each line of the row address strobe input driving circuit 20 is connected to all of the memory chips 21 in the column. For example, line 22 is connected to the row address strobe input terminals of the chips in the column. Each line of the column address strobe input driving circuit 40 is connected to the column address strobe input terminals of all of the memory chips in the column. For example, line 41 is connected to the column address strobe input terminals of all of the chips in the column. The column of chips conventionally comprises 8, 16, or 32 closely packed chips, for example, the chips of each group abutting one another to minimize the space required for the installation on a circuit board. Of course other numbers of chips may be completed in the group. The data terminals of the chips of each group are connected to separate lines of a data bus, whereby each group of chips corresponds to a byte or word. Any memory chip which receives both the row and column address strobe input signals is a selected chip. This chip selection enables the latching of the nine-bit address signals which are sent from the address driving circuit 50 to each of the memory chips along address bus 51. Further, the write enable control input driving circuit 30 is connected to each of the memory chips by way of line 31.
The circuit of FIG. 4 depicts a conventional manner in which memory chips are arrayed and connected to drivers. This conventional arrangement of chips is disadvantageous because of the limitation on the speed of switching of the address driving signals due to noise induced by the address driving signals in adjacent lines in the chips, e.g. the lines carrying the column address strobe, row address strobe and write control input pulses. For example, the address signals transmitted by address driver 50 induce noise signals of the same polarity in inductively coupled lines of the memory chips. For example, the noise signals induced in all portions of the column address strobe input line 41 add to produce a summed noise signal on line 41. This noise signal distorts the negative-going transition of the column address strobe input signal on line 41. Likewise, the noise signals induced in all portions of the line 22 add to produce a summed noise signal. Finally the noise signals induced in all portions of the write enable line 31 add to produce a summed noise signal on line 31.
The faster the switching speed, the greater is the magnitude of the induced noise. In the prior art arrangements the switching time (i.e. the time for the signal on an address line to make the transition from below V.sub.L to above V.sub.H or vice versa as shown in FIGS. 3A-3C) is about 20 nsec. If the switching speed is increased so that the switching time is 5 nsec, the noise amplitude increases on the on-chip lines carrying the column address strobe, row address strobe and write control input signals to a level such that false transitions of the signals on the column address strobe, row address strobe and write control input lines are possible. For example, a noise spike could be treated as a positive- or negative-going transition. Alternatively, it is possible that a noise spike will occur at the same time as a positive- or negative-going transition, thereby hindering accurate detection of the transition.
In particular, the column address strobe, for a switching time of 5 nsec, induces noise spikes in a column of chips which could overlap and partially cancel the negative-going transition of the column address strobe input signal. In addition, spikes also result from the capacitive coupling within the lead frame of the RAM chips themselves. To avoid this problem, the negative-going transition of the column address strobe input signal would have to be delayed. However, any delay in the column address signal defeats the purpose of the increased switching speed of the address signals, i.e. to speed up the storage and retrieval of information from the memory chip array by decreasing the data access time. Also, the delay between the RAS and CAS negative-going transitions must be less than a specific maximum value for the M5M4256L chips (e.g. 60 nsec for the M5M4256L-12 chip). Furthermore, with a large number of chips in each row such a delay prevents the cycle time from being effective since data can be lost due to fixed time constraints inherent in the chip. This problem limits the number of chips which can be included in a prior art dynamic RAM array.