1. Field of the Invention
Generally, the present disclosure relates to the field of manufacturing of integrated circuits and semiconductor devices, and, more particularly, to the testing of transistor devices, particularly, the detecting of gate-to-source/drain shorts of transistor devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of electronic circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced for forming field effect transistors, wherein, for many types of complex circuitry, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., N-channel transistors and/or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. Miniaturization and increase of circuit densities represent ongoing demands.
A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed between the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length.
With decreasing distances of the transistor gates in the course of aggressively downscaled (Fully Depleted) SOI manufacturing, for example, in the context of the 22 nm technology, device failures due to contact-gate shorts and, in particular, gate-to-raised source/drain shorts pose severe problems. Therefore, testing semiconductor devices for such electrical shorts is of great importance. FIG. 1 shows an example of a gate-to-source/drain short in a field effect transistor (FET) 1. The FET is formed over an FDSOI substrate comprising a base substrate 2 containing silicon, a buried oxide layer 3 formed on the silicon-containing base substrate 2 and a semiconductor layer 4 comprising silicon formed on the buried oxide layer 3.
The FET 1 comprises a gate electrode 5 with a sillicided portion 5′ and raised source/drain regions 6 with silicided portions 6′. As can be seen, the silicided portion 5′ of the gate electrode 5 and the silicided portions 6′ of the raised source/drain regions 6 merge over a sidewall spacer 7, thereby making electrical contact with each other, i.e., an electrical short (gate-to-raised source/drain short) is formed.
In the art, test structures are known that allow for detecting electrical shorts between regular contacts (CA) of source/drain regions and gates. Since the contacts are connected to raised source/drain regions, such a structure can also be used for detecting gate-to-raised source/drain shorts. However, it cannot be differentiated between CA-gate shorts and gate-to-raised source/drain shorts.
In view of the situation described above, the present disclosure provides techniques for detecting gate-to-raised source/drain shorts, in particular, detecting gate-to-raised source/drain shorts decoupled from the detection of contact-gate shorts.