When analogue and digital components are located on the same substrate in close proximity, such as is the case for ASIC devices, inevitably there will occur so called cross-talk between these components.
Capactive crosstalk can e.g. occur when digital signals are run near analog signals, the capacitance between the lines can cause the lines to couple and the signals become blurred due to coupling through the substrate underneath.
This problem can be eliminated by running the analog signals in a separate routing area than the digital, and by putting grounding shields between the analog and the digital.
The digital return currents return ground through a non-zero impedance, due to either resistive or inductive effects, which can cause the local “ground” to move up and down with the current. If this ground differs from the originator of the signal, this will cause voltage differences at the rate of the bits. This problem can be eliminated by improving grounding, or by understanding and controlling the paths that ground current flows in.
Some of the major problems induced by digital to analog and analog to analog cross talk are (1) high speed digital clocks cause severe interference with RF or IF front ends; (2) in digital portables, time-division-multiple-access (TDMA) may be used and power on/off cycles happen fairly frequently, causing additional transient noise on the power and ground planes; (3) in frequency division duplex systems, as well as in pixel based imaging devices, high-power transmit signals cause interference with weak receive signals since separation by filters is limited; (4) the leakage of the amplifier output to the input may cause the amplifier to oscillate.
A critical requirement for the development of low cost, wide-bandwidth telecommunications equipment is the close integration of both digital and analog microelectronic components. The physical interface between an IC and its environment is the IC package, and its performance is severely tested by the high speed and high frequencies encountered in wide-bandwidth systems. Single chip mixed signal ICs that combine directly both high frequency analog and high speed digital sub-sections will require proper electromagnetic understanding of capacitive, inductive, and radiative coupling between components, and their impact on high sensitivity analog sub-circuits.
Crosstalk and interference between devices in mixed signal ICs can be reduced when SOI wafers are used due to the isolation of devices from the substrate.
In the prior art where the cross talk problems have been addressed, several alternative solutions have been presented.
One way of dealing with it is so called counter junction doping, which entails reverse biased layers to prevent cross talk through the common substrate on which components are provided in combination with large physical separation between analogue and digital parts. The latter is of course limiting on the possibilities to reduce component size, which is disadvantageous.
Another approach is to use SOI substrates to bring about dielectric isolation/insulation across the substrate.
A still further prior art solution is to combine use of SOI and non-wafer through trenches. The usage of such trenches are well known in IC industry but then the normal approach is to make the trenches as a last step in the processing. Starting substrates (trench first approach) with filled isolated trenches through a device layer on an SOI wafer with limited trench depth are commercially available from for example IceMOS (Northern Ireland, United Kingdom; www.icemostech.com). The general problem with this type of solution is that trenches must be narrow enough to be able to be filled. The DeepReactive Ion Etching (DRIE) method often referred to as the Bosch process used to etch the trenches gives a practical maximum aspect ratio of about 1:40. The prior art methods which use typically 3 μm wide trenches that are fairly simple to fill limits the depth to which the trenches penetrate to approximately 100-150 μm. Such thin wafers are not possible to use as starting substrate. Hence a SOI wafer with a thick handle wafer is used to obtain robust enough substrates to allow further processing. The trenches are then made in a 100-150 thick device layer. The fabrication costs of an SOI wafer compared to conventional non-SOI substrates is approx 10 times higher. For several low cost devices with mixed analogue/digital or high frequency designs such as Bluetooth chips and alike that should gain improved performance with wafer through isolated trenches according to present invention, the extra cost of using trench filled SOI wafers as starting substrates is prohibitive.
It would be desirable 300 um
In WO 2004/084300 (Silex Microsystems) there is disclosed a method of making electrical through connections involving etching deep trenches, the contents of which is incorporated herein in its entirety.