1. Field of the Invention
The present invention relates generally to circuits and in particular to circuits having differential stages and which operate at relatively low voltages.
2. Background Art
There are a wide variety of electronic circuits which include one or more differential amplifier stages and which are capable of operating at power supply voltages of 5 or more volts. However, there is an increasing demand for circuits which perform the same functions, but which operate at even lower voltages.
The increased demand in low voltage circuits is created in part by the use of batteries as power sources. A typical battery supply voltage is 3 volts, which is provided by connecting two dry cells in series. Unfortunately, many conventional circuits will not operate properly at this low voltage.
Referring to the drawings, FIG. 1 depicts a conventional circuit, commonly referred to as the Gilbert cell, which is widely used to provide functions such as multiplication, frequency conversion, modulation and demodulation. These functions are related and, for purposes of convenience, are referred to collectively herein as multipliers. In the present example, the circuit is used a frequency converter for a radio receiver which converts an RF input signal V.sub.RF to an intermediate frequency signal V.sub.IF by mixing the RF signal V.sub.RF with a local oscillator signal V.sub.LO.
The converter includes a first differential pair of NPN transistors Q.sub.1 and Q.sub.2 and a second differential pair of NPN transistors Q.sub.1 and Q.sub.2 which drive a common load 20. The base electrodes of transistors Q.sub.1 and Q.sub.4 form the positive input for the differential oscillator input signal V.sub.LO and the base electrodes of transistors Q.sub.2 and Q.sub.3 form the negative input for the signal.
An NPN transistor Q.sub.5 has a collector connected to the common emitter connection of transistors Q.sub.1 and Q.sub.2 and a further NPN transistor Q.sub.6 has a collector connected to the common emitter connection of transistors Q.sub.3 and Q.sub.4. The common emitter connection of transistors Q.sub.5 and Q.sub.6 is connected to a current source I.sub.X1. The base electrodes of transistors Q.sub.5 and Q.sub.6 form the positive and negative inputs, respectively, for the differential RF input signal V.sub.RF.
The transconductance and, therefore, the gain of the differential pair Q.sub.1 and Q.sub.2 and differential pair Q.sub.3 and Q.sub.4 is controlled by varying the amount of current flow through the two pair. Thus, since transistors Q.sub.5 and Q.sub.6 control the current flow though the two differential pair, the gain varies with input V.sub.RF. Thus, the differential output V.sub.IF at the collectors of transistors Q.sub.1, Q.sub.2, Q.sub.3, and Q.sub.4 is a function of both V.sub.LO and V.sub.RF.
The voltage across the FIG. 1 circuit is the supply voltage Vcc. The minimum voltage can be determined by inspection and is set forth in the following equation. EQU V.sub.MIN =V.sub.CE(Q1/2/3/4) +V.sub.CE(Q5/6) +V.sub.ZL +V.sub.IX( 1)
where
V.sub.MIN is the minimum supply voltage; PA1 V.sub.CE is the minimum quiescent collector-emitter voltage; PA1 V.sub.ZL is the minimum quiescent load voltage; and PA1 V.sub.IX is the minimum quiescent current source voltage. PA1 V.sub.MIN is the minimum supply voltage; PA1 V.sub.CE is the minimum quiescent collector-emitter voltage; PA1 V.sub.BE is the minimum quiescent base-emitter voltage; PA1 V.sub.ZL is the minimum quiescent load voltage; and PA1 V.sub.IX is the minimum quiescent current source voltage.
Assuming that for reliable operation voltages V.sub.CE and V.sub.IX must be 0.75 volts and V.sub.ZL must be 1 volt, the minimum supply voltage is 3.25 volts. Thus, the FIG. 1 circuit cannot reliably operate on the 3 volts provided by two dry cells connected in series.
A further exemplary conventional circuit is the current mode logic circuit shown in FIG. 2, sometimes referred to as emitter coupled logic. The exemplary logic circuit is a latch which stores data present at the data input upon receipt of a clock input.
NPN transistors Q.sub.1 and Q.sub.2 form an input different pair and transistors Q.sub.3 and Q.sub.4. form an output differential pair. The input differential pair Q.sub.1 and Q.sub.2 is driven by the data input. The output differential pair are driven by the input differential pair through emitter-follower configured transistors Q.sub.7 and Q.sub.8. Both differential pairs utilize common load resistors R.sub.L1 and R.sub.L2.
The input and output differential pair are gated by a common gating circuit which includes a third differential pair made up of NPN transistors Q.sub.5 and Q.sub.6. The collector of transistor Q.sub.5 is connected to the emitters of transistors Q.sub.1 and Q.sub.2 and the collector of transistor Q.sub.6 is connected to the emitters of transistors Q.sub.3 and Q.sub.4. Finally, the common emitters of transistors Q.sub.5 and Q.sub.6 are coupled to a current source I.sub.X1. The output of the cell is at the emitters of transistors Q.sub.7 and Q.sub.8, with the emitters also being connected to current sources I.sub.X2 and I.sub.X3, respectively.
The operation of the conventional logic cell is well known. When the clock is in a first phase, transistor Q.sub.5 is on and transistor Q.sub.6 is off. Thus, the data input will switch transistors Q.sub.1 and Q.sub.2 to opposite states, depending upon the data. When the clock is in a second phase, transistor Q.sub.5 is off and Q.sub.6 is on. The data stored at the input pair will then be transferred to the output pair and to the output. Note that feedback is provided by transistors Q.sub.7 and Q.sub.8 which increases the switching speed. Since the input pair is disabled (Q.sub.5 is off), any further changes in the data input will not affect the circuit.
Again, the voltage across the FIG. 2 circuit is the supply voltage Vcc. By inspection, it can be seen that the minimum voltage is in accordance with the following equation: EQU V.sub.MIN =V.sub.CE(Q6/5) +V.sub.BE(Q7/8) +V.sub.BE(Q1/2/3/4) +V.sub.ZL +V.sub.IX ( 2)
where,
Assuming that the minimum voltage for V.sub.CE is 0.75 volts, V.sub.BE is 0.75 volts, V.sub.ZL is 0.25 and V.sub.IX is 0.75 volts, it can be seen that the minimum supply voltage will be approximately 3.25 volts. Thus, the FIG. 2 cell cannot reliably operate using two dry cells.
FIG. 7 depicts a conventional logic cell with the output transistors Q.sub.7 and Q.sub.8 (FIG. 2) and associated circuitry removed. As will be explained later in greater detail, the FIG. 7 circuit is capable of operating a lower supply voltage than the FIG. 2 circuit but even lower operating voltages would be desirable.
There is a need for circuits which can perform the functions of the conventional Gilbert cell of FIG. 1 and the logic cell of FIG. 2 and still operate reliably at the relatively small voltages provided by batteries. These and other shortcomings of the prior art are overcome by the present invention as described in the following Detailed Description of the Invention together with the drawings.