1. Field of the Invention
This invention relates to analog-to-digital converters and, more particularly, to an analog-to-digital converter system which combines a plurality of digital sample values to produce a digital output value.
2. Description of Related Art
Many physical devices generate output signals which are analog or continuously varying. Today, signal processing is often accomplished using digital methods. In many applications it is required to convert an analog signal into a digital form suitable for processing by a digital system. Many types of converters exist which act as interfaces between analog devices and digital systems. These converters are used in a variety of applications, including testing, measurement, process control, and communications. In converting analog signals to digital form, the analog signal is typically sampled and quantized. In a typical wireless communications system, a radio frequency (RF) signal comprised of information signals(s) modulated onto RF carrier(s) is received by an antenna. For example, for cellular communications in the United States, information signals are carried over frequency channels within 824-849 MHz and 869-894 MHz. In a Personal Communications System (PCS), information signals are carried over frequency channels on one or more PCS bands 1850 MHz-1910 MHz and 1930-1990 MHz. After some filtering and frequency down-conversion to an intermediate frequency (IF), the analog signals are provided to a low noise amplifier (LNA). The LNA amplifies the analog signals and provides the analog signals to an A/D converter for analog to digital conversion. The A/D converter provides the digital values to a bus which provides the digitized signals to the digital radio circuitry, for example digital downconverters connected to associated digital signal processors.
Today, a fast A/D converter can run at speeds of up to 1 Gigasamples per second (GSps). At the faster speeds, the signal to noise ratio (SNR) of the digital signal from the A/D converter can degrade when the A/D converter clock has imperfections, such as clock jitter. In any event, digital downconverters can only handle maximum data speeds at its input of up to 70 Megasamples per second (MSps). Frequency conversion stages can be used to frequency convert the analog signals to lower IF frequencies, but these add noise and cost. Furthermore, the data rate at the input to the digital downconverters can be reduced by discarding a subset of the digital sample values. However, such schemes fail to take advantage of the higher sampling speed of the A/D converter and introduce noise to the digital signal.
Accordingly, a need exists for analog to digital conversion at higher speeds where effects, such as clock jitter, are reduced and the higher speed sampling of the A/D converter can be taken advantage of in the lower speed digital signal processing circuitry, such as the digital downconverters.