EEPROMs and flash memories can be reprogrammed, more specifically, erased only a limited number of times. These memories containing data must be erased before they can be written with new data. It is well known that the number of times flash memories can be reprogrammed is much less than that of EEPROMs. EEPROMs are guaranteed for, e.g., approximately 100,000 cycles (reference value). Flash memories, on the other hand, are guaranteed for about 1,000 cycles (reference value). For these reasons, EEPROMs are used in applications where data is rewritten frequently while flash memories are typically used in applications other than the above.
EEPROMs permits a large number of write cycles but are much more expensive than flash memories. It is thus expected that data recording medium can be achieved at a lower cost in an information processor where an EEPROM is used as a data recording medium, if a flash memory can serve as an alternative to that data recording medium.
In order to use a flash memory as an alternative to an EEPROM, it is necessary to provide a mechanism to make the number of times flash memories can be reprogrammed comparable to that of EEPROMs. One technical approach for this purpose in the art is the one called “EEPROM emulation” which is described in, for example, the Non-patent-related Document 1. As described above, flash memories containing data must be erased before they are reprogrammed. EEPROM emulation (registered trademark) in flash memory erases multiple write cells simultaneously to reduce the number of erase cycles associated with operations to write data. This increases an apparent number of times flash memories can be reprogrammed to around that of EEPROMs.
However, the EEPROM emulation uses a different address architecture from that of EEPROMs. In order to achieve the number of reprogramming cycles in flash memories equivalent to that of EEPROMs, it is much better if the address architecture of the EEPROMs is also implemented. For this purpose, it is necessary to provide a mechanism to generalize management of the address architecture. More specifically, it is desirable to provide a technology for memory control with which addresses can be managed for each write cell, and the number of times non-volatile memories can be reprogrammed can be increased as compared to that obtained during their ordinary use.
In addition, the EEPROM emulation is typically designed to divide each write cell into multiple blocks (data write cells). If a problem such as an unexpected power failure arises during write operations with the write cells divided, it is difficult to determine after the recovery which part of the data is successfully written.
As a conventional art that can improve this, there is an approach wherein a first reference data representing a state at the beginning of writing and a second reference data representing a state at the completion of the write operation are stored for each block, and the first reference data is updated at the beginning of the write operation while the second reference data is updated at the completion of the write operation, thereby allowing to recognize the most recent version of the data that has written just before the occurrence of the problem of the type described above, as the latest data (Patent-related Document 1).
In addition, after occurrence of any problem, information representing the completion of the write operation is referred to upon recovery to reprogram the block that has been written already, thereby to recover the data appropriately (Patent-related Document 2).
The technique disclosed in the Patent-related Document 1 has an advantage that the data in the blocks that have been written successfully just before the occurrence of a problem can be used after the recovery by means of referring each reference data even when the write operation is interrupted and aborted due to, for example, a power failure. However, this technique requires some related processing to ensure the consistency of the already-written data when the data to be written is divided into and written as separate pieces. This is because non-volatile memories are reprogrammed on a block-by-block basis (and are erased before that), and because sectors that are available for writing can be wasted if precise consistency check is not made. A similar problem applies to the technique disclosed in the Patent-related Document 2. In addition, the blocks divided have a fixed size while the size of the data to be written is not fixed, which makes it difficult to achieve the related processing in a correct manner.
These problems are expected to be solved by using a memory access technology which ensures data having various sizes to be written atomically.
By the way, there is no difference between EEPROMs and EEPROM emulations from the viewpoint that they can be reprogrammed only a limited number of times. However, when focused on the address at which data is to be written, some addresses are used for writing data only one time. An example is given. It is assumed that addresses corresponding to 2048 bytes are classified into the following three types.
First address set: addresses corresponding to 256 bytes from 000H to 0100H;
Second address set: addresses corresponding to 1024 bytes from 0100H to 0500H;
Third address set: addresses corresponding to 768 bytes from 0500H to 0800H.
It is also assumed that the first and third address sets are frequently involved in reprogramming while the second address set is associated with a sector in which data such as a given fixed parameter will be read but not changed once it is written. When all address sets are used in a similar equivalent manner, the data to be rewritten has a size of 2048 bytes unless some kinds of efforts are made. This makes the number of times the memory can be reprogrammed much smaller than it really is, regardless of the fact that actually the size of 256+768=1024 bytes is enough.
It is expected that such a problem can be solved by using a characteristic memory control technology with which addresses can be managed for each write cell while the number of times the non-volatile memory can be reprogrammed can also be increased as compared to that obtained during their ordinary use.    [Non-patent-related Document 1] “Application Note U17057JJ3V0AN00”, third edition, NEC Electronics Corp., November 2004, p. 25-27.    [Patent-related Document 1] Japanese Patent Laid-open No. 8-287697.    [Patent-related Document 2] Japanese Patent Laid-open No. 2004-206381.
An object of the present invention is to provide a characteristic memory control technology with which addresses can be managed for each write cell while the number of times the non-volatile memory can be reprogrammed can also be increased as compared to that obtained during their ordinary use.
Another object of the present invention is to provide a memory access control technology which ensures data having various sizes to be written atomically into a non-volatile memory.