Packaging for microelectronics and MEMS are one of the most important production steps before bringing the product into the market. Various packaging technologies have been developed for integrated circuits and MEMS. Initial MEMS devices used the technologies developed by IC industry. On the other hand, advances in the MEMS technologies offer a tremendous contribution to microelectronic integration and packaging. Historically, all the newly introduced packaging technologies enabled lower footprint and lower cost. Chip scale packaging (CSP) is the latest development where the final footprint of the device is fundamentally determined by the active die itself.
CSP for ICS
The term chip scale package was first introduced in 1994. It is defined as a package that has an area which is no more than 1.2 times the area of the active die. CSPs offer many advantages such as smaller size, lesser weight, relatively easier assembly process, lower cost, improved electrical performance due to lower parasitics. Chip scale packaging combines the strengths of various packaging technologies. For example, it offers the size and performance advantage of bare die attachment and the reliability of encapsulated devices. The significant size and weight reduction makes the CSP ideal for use in portable devices like cell phones, laptops, pocket computers, and digital cameras.
Various CSP technologies have been developed by different companies. These can be grouped under four major categories according to CSP structure:
1. Rigid interposer type. The die is flip-chip attached to a rigid printed circuit board (PCB) fabricated using advanced technologies that can accommodate the pitch and clearance requirements of the die. The interposer translates the die pad pitch into a rather large interconnect pitch. Mini BGA (IBM), Small Form (LSI logic), Flip chip BGA (Sony) are some of the package names used by different companies.
2. Flexible interposer type. This type is very similar to the first type except the material used for the interposer. Common materials for the interposer are liquid-crystal polymer and polyimide. Some of the package names are chip on flex (GE), fine pitch BGA (Nec), F. GBA (Sharp).
3. Custom lead frame type. In this type, frame leads are directly attached to the die pads. Small outline non-lead (Fujitsu), Lead on chip (Hitachi), Bottom lead package (LG) are some of the package names introduced by various companies.
4. Wafer-level assembly type (Wafer Level Chip Scale Package) (WLCSP). This type of package is substantially or completely constructed before the wafers are sawed into dies. Obviously, packaging the ICs at the same IC manufacturing site has many economic advantages. It eliminates wafer probing tests since these can now be achieved at the part level. It reduces or eliminates the costs associated with individual packaging of the parts like shipping the wafer overseas for packaging. And finally, it provides manufacturers the complete control over IC production. The next section will discuss the WLCSP in more detail below.
Wafer Level Chip Scale Packaging for ICs
Wafer level Chip Scale Packaging is the latest packaging technology. This technology comes in a variety of types. There are basically four different Wafer Level Chip Scale Packaging technology classifications.
1. Redistribution layer and bump technology. This is the most widely used technology. In this technology, first the IC surface is repassivated by one or more layers of a photo patternable polymer such as BCB (benzocyclobutene). This later provides protection for the die from external environment. It also allows multiple metal traces for routing between the solder bumps and the IC pads. Next, the redistribution layer is defined through sputtered and evaporated metals followed by a lift-off process. This layer can also be defined by electroplating. Finally, solder bumps are formed using electroplating on a UBM stack on the redistribution layer.
2. Encapsulated copper post technology. This is very similar to the redistribution and bump technology except that the redistribution layer routes the connections from IC pads to copper posts defined by sputtering/etching or electroplating techniques. After defining the copper posts, the IC surface is encapsulated in low stress epoxy by transfer molding. The epoxy coating leaves the top portions of the copper posts exposed. Later, standard solder bumping process is applied to solder balls on top of these posts.
3. Encapsulated wire bond. Similar to the two previous techniques, a redistribution layer is used to increase the IO pitch to the desired level. Then, S-shaped gold wires are placed on the redistribution pads using a modified wire bonder. These wires are later soldered to the PCB during the assembly.
4. Encapsulated beam technology. The packaging process starts by attaching a glass plate to the IC by means of an adhesive layer such that the active surface of the CMOS faces the glass plate. The CMOS is diced into dies by using either chemical etching or mechanical cutting while the die is attached to the glass plate. Then, the second glass plate is attached on top by another adhesive layer, preferably epoxy, filling the dice channels. Wafer sawing the second plate and CMOS reveals the edges of the IC pads. The routes between these conducting edges and the solder balls that will be placed on the second plate are defined by metal sputtering, patterning and etching. In this approach, the solder balls are placed on the back side of the CMOS. This packaging method provides a clear view for the active CMOS surface where an image sensor or a light detector can be placed. With slight variations in the packaging process, solder balls can be placed on the top side of the CMOS.
Packaging for MEMS
Packing requirements for MEMS are much more complex than IC packaging requirements. For example, optical sensors require transparent packaging such that the package does not attenuate the optical signals. On the other hand, an acoustic sensor needs to be accessible from outside through a finely engineered opening that allows maximum transmission of sound waves while blocking dust and wind. MEMS inertial sensors require hermetic sealing. Therefore, packaging of MEMS devices reveals itself in many novel designs and techniques.
The simplest approach to package a MEMS device is to place the sensor in a housing and provide electrical connections through wire bonding between the leads of the housing and the MEMS die. The housing should protect the moving parts from environmental effect such as humidity and dust. Hermetical or non-hermetical packages can be used for these purposes. Typical housing materials are metal, plastic or ceramics. However, this approach results in relatively large footprints and these packages are not suitable for the consumer applications where reduction in size is very desirable. Moreover, for MEMS devices that require low pressure this approach is not practical.
Wafer Level packaging for MEMS
Above problems can be partially or completely solved by achieving some part of the packaging at the wafer level. Various techniques have been proposed for wafer level packaging of MEMS devices. For example, a silicon cap bonded at the wafer level has been used to provide triple-level polysilicon surface micromachined accelerometer. Low temperature glass frits have been used to achieve the bonding. The cap provides mechanical protection for the accelerometer such that the sensor can be later packaged in a conventional injection molded plastic package. VTI technologies from Finland use triple-stack anodic bonding for their commercial accelerometers. Three wafers are bonded together to form a hermetically sealed cavity at the center. The seismic mass is defined in the center wafer. Upper and lower wafers have a thin glass layer on their surfaces. The glass layers provide the anodic bonding. There are also other similar wafer level packaging technologies developed to companies such as ST, Bosch and ADI. But none of these achieves both packaging of MEMS and integration with CMOS electronics at the same time. The connections between the MEMS and CMOS are enabled through wire bonding. This results in increased cost. The most successful packaging and integration method for MEMS has been introduced by Nasiri et al. in U.S. Pat. Nos. 6,939,473 and 7,104,129 (hereinafter, the Nasiri-fabrication process). The Nasiri-fabrication process includes a special SOI wafer where recesses formed in the handle layer. The MEMS device is defined in the device layer using DRIE. Then, the SOI wafer with the device definition is bonded directly to the aluminum layer on the CMOS wafer, without addition of any other material layers on top of the aluminum. The bonding is performed at low temperature using eutectic metals. In one bonding step, the Nasiri-Fabrication provides for a wafer-scale integration, by making electrical interconnects between the MEMS and CMOS, and wafer-scale packaging by providing a fully hermetic sealing of the sensitive MEMS structures at the same time. The finished wafer then goes through yet another patented and proprietary pad opening step that uses a standard saving technique to remove unneeded MEMS silicon that covers electrical pads. Finished wafer are then tested on standard automated wafer probers. The subsequent packaging can readily be completed cost effectively in plastic packages at any industry standard contract assembly house, avoiding the need for more costly and customized ceramic and/or multichip packaging alternatives.
Although the Nasiri fabrication platform successfully addresses the most of the packaging needs of the consumer products, emerging applications and portable products are demanding further miniaturization of MEMS sensors. Portable electronic devices are getting smaller and more feature rich. This requires further size reductions for MEMS sensor ICs in height. The key requirement for portable electronics, especially for handsets, is a maximum of 1 mm device height which is difficult to achieve using plastic or ceramic packages for MEMS. In today's mobile handset market the trend is to provide high performance, low cost components with integration of functionality and small form factor. Wafer scale chip scale packaging provides smaller and very cost effective devices for these applications. Therefore, it is the technology of choice for handset market.
Wafer Level Chip Scale Packaging for MEMS
Wafer Level Chip Scale Packaging technologies can also be applied to the MEMS devices. For this purpose, various techniques have been developed. Shiv et al, in “Wafer Level Chip Scale Packaging for MEMS,” developed a cap wafer with micro vias and Au/Sn seal ring that will provide eutectic bond to the MEMS/CMOS wafer. The process starts with an SOI wafer. The cavity and the vias are defined in the device layer. Later the device layer is covered by a passivation layer (oxide). The seal ring and micro vias are coated by electroplated Au/Sn solder. The cap wafer is then soldered to the MEMS/CMOS wafer. The cap wafer is etched from the handle side to provide access to the micro vias. This opens the ends of the vias. The solder balls that are placed on the back side of the cap are connected to the open ends of the vias. This approach has some draw backs. The cavity in the cap wafer can not be too deep. This limits the use of this method mostly to the surface micromachined devices. Also the cap height can not be made too high since the solder balls need to be placed on this side. In addition, this technique does not address the stress issues due to the different thermal expansion coefficients of PCB and silicon.
At Philips, there has been development effort for Wafer Level Chip Scale Packaging for their RF-MEMS components. In this approach, the MEMS devices are capped by another thin silicon piece which has solder on it. However, the capping is not done at wafer level, rather chip-to-chip solder bonding is used. Later solder balls are placed on the MEMS wafer. Although, the solder bumping is done at the wafer level, this approach is not true wafer level chip scale packaging. Therefore, it results in increased manufacturing cost. Moreover, the cap and the solder balls are on the same side of the wafer. This imposes limits on the solder size and cap size.
Fraunhofer IZM has also developed a Wafer Level Chip Scale Packaging technology. First, the cavities are defined on the cap wafer. Then seal rings are defined by depositing solder on the wafer. The cap wafer and the MEMS/CMOS wafer are aligned together under an IR aligner. The sandwiched wafer is brought into a reflow oven for soldering. After the soldering, back side grinding is performed to reduce total package height. The pads on the MEMS/CMOS wafer are exposed either by a pre-structured cap wafer or controlled dicing of the cap wafer without damaging the MEMS/CMOS wafer. The connections between the device pads and the solder balls are achieved by wire bonding from the pads to the top of the cap. Later, the wire bonds are covered with a liquid encapsulant and the dies are singulated using a wafer saw. Although this technology uses mature techniques, it has some drawbacks. For example, wire bonding limits the minimum distance between the dies resulting in increased footprint. Moreover, it is suitable only in surface micromachined devices.
Shellcase uses WLCSP for ICs as well as optic components. Their packaging technology is also suitable for MEMS devices. In this approach, first cavities are defined in SU8 layer deposited on a packaging substrate. The channels between the SU8 cavities are filled with epoxy. These epoxy filled channels are aligned over the MEMS/CMOS pads and the two substrates are brought together under pressure. After the epoxy is cured, the MEMS/CMOS wafer is etched from the back side, until the device pads are exposed. At the end of this step, the MEMS/CMOS dies are also singulated. A second packaging substrate is glued on the back side of the CMOS. The second substrate and the MEMS/CMOS die are then sawed by a wafer saw such that the edges of the pads are exposed close to the bottom of the cavities. Later, metal deposition makes contacts between these edges and the solder balls on the top of the second substrate. The major drawback of this approach is that it cannot provide a true hermetic seal for MEMS. Moreover, it is only applicable for surface micromachined devices.
None of the above technologies can address the wafer level chip size packaging need for bulk micromachined integrated MEMS with electronics while keeping the size small at reduced cost. The present invention addresses such as need.