Major aims of circuit designs are to develop integrated circuits having increased speed, smaller size and lower power consumption. CMOS (Complementary Metal Oxide Semiconductor) circuits have lower power consumption and superior performance characteristics, as compared to NMOS (N-type MOS), PMOS (P-type MOS), or bipolar circuits. CMOS design technology serves as the technology of choice in designing complex monolithic systems having dense logic, low power dissipation, low supply voltage and highly automated synthesis.
CMOS static logic circuits, however, may be frequently operated in a manner where both of the PMOS and NMOS transistors forming a CMOS inverter are simultaneously turned on. Since this leads to large leakage current in the CMOS inverter, such CMOS static logic circuits are not suitable for high-speed operation with low power. Therefore, in high speed and low power applications, either operational speed or low power must be compromised to consider a CMOS design. Alternatively, a balance of both the low power and operational speed is required to design CMOS devices. This limits the design flexibility of the CMOS design.
In several applications, pass-transistor logic (PL) circuits have been used to substantially reduce circuit size without increasing power and reducing operational speed. Introducing such PL circuits eases the trade-offs as stated above.
FIG. 1 shows a 1-bit full adder as an example of the prior art PL circuit. As shown in FIG. 1, the 1-bit full adder has a functional block (FB) 2 and a level restoration block (LRB) 4. The functional block 2 is formed using only NMOS transistors so as to operate at high speed and with low power and to minimize it's chip area. It performs the addition operation of three input signals A, B and C to provide a sum signal SUM, a carry signal CARRY and complementary signals /SUM and /CARRY, respectively. (Note: In this specification, we will use the virgule "/" leading a signal name to indicate the complement signal.) The level restoration block 4 restores a marginally high level signal provided from the functional block 2 to a full high level--substantially the supply voltage V.sub.DD. The marginal high level signal has voltage V.sub.DD -V.sub.TN, where V.sub.TN represents the threshold voltage of the NMOS transistor.
Prior art level restoration circuits are illustrated in FIGS. 2A through 2D. The circuit of FIG. 2A is a level restoration circuit used in complementary pass-transistor logic (CPL). This level restoration block of the CPL is formed with a pair of CMOS inverters.
In this CPL level restoration block, for example, when a strong or full low level signal (i.e., a ground level signal V.sub.SS) is applied to an input terminal IN thereof, the PMOS transistor of the first inverter is made conductive. A high level signal V.sub.DD is then output from an output terminal of the level restoration block (i.e., the output terminal /OUT of the first inverter). When a marginal high level signal V.sub.DD -V.sub.TN is applied to the other input terminal /IN of the level restoration block, the NMOS transistor of the second inverter turns on so that the weak high level signal is output from the other output terminal of the level restoration block (i.e., the output terminal OUT of the second inverter). This phenomenon occurs because the PMOS transistor of the second inverter is not completely turned off due to the weak high level signal V.sub.DD -V.sub.TN. Therefore, since the PMOS transistor is not completely turned off, some leakage current normally flows through the PMOS transistor. Consequently, the operating speed of the CPL level restoration block can be improved, but at a penalty of increased power consumption.
To address the above mentioned problems of the CPL level restoration block, several circuits such as PMOS latched type CPL, standalone type and SRPL (swing restored pass-transistor logic) level restoration circuits, as shown in FIGS. 2B to 2D, respectively, have been proposed. Of these improved level restoration circuits, particularly the SRPL level restoration circuit is formed using only CMOS inverters, similarly to the CPL level restoration circuit of FIG. 2A. However, in FIG. 2D, one input terminal IN of the level restoration block is commonly connected to the output terminal /OUT of the first inverter and to the input terminal of the second inverter, and the other input terminal /IN thereof is commonly connected to the output terminal OUT of the second inverter and to the input terminal of the first inverter. In such a SRPL level restoration circuit, when a marginal high level signal V.sub.DD -V.sub.TN from the functional block 2 is applied to the input terminal thereof, the weak high level signal is output via one output terminal (i.e., the output terminal /OUT of the first inverter) of the level restoration circuit. The weak high level signal is also applied to the input terminal of the second inverter, so that the NMOS transistor of the second inverter is turned on. The other terminal of the level restoration block (i.e., the output terminal OUT of the second inverter) is then pulled down to a solid low level--substantially equal to V.sub.SS or ground, so that the PMOS transistor of the second inverter is completely turned off. As a result, no leakage current flows through the PMOS transistor.
However, while the SRPL level restoration circuit is excellent in restoring a weak high level signal to the V.sub.DD level, the output voltage thereof is discharged through the NMOS transistors of the functional block 2. In a logic circuit in which cascaded NMOS transistors are connected in series like a full adder, the discharging time is largely lengthened. This characteristic increases operational delay time.
It is imperative to improve floating-point performance in high performance microprocessors having operating frequencies, for example, of about 200 MHz or more. With the increase in demand for multimedia applications, high-speed multiplication is particularly critical in reduced instruction set computers (RISC), digital signal processing (DSP), graphics accelerators and the like. A high-speed 54.times.54-bit multiplier has been disclosed in the IEEE Journal of Solid-State Circuits entitled "A 4.4 ns CMOS 54.times.54-b Multiplier Using Pass-Transistor Multiplexer," Vol. 30, No. 3, pp. 251-257, March, 1995. The multiplier structure is shown in FIG. 3.
Referring to FIG. 3, the multiplier is constructed using Booth's algorithm and a Wallace tree configuration. The multiplier has a Wallace tree compressor 14 coupled to a modified Booth's encoder (MBE) 12 and a 108-bit conditional sum adder (CSA) 16. This adder 16 is called a conditional carry-selection adder or a "carry lookahead" adder. The Wallace tree compressor 14 comprises fifty-four 4-to-2 compression units. Fifty-four vertical data signals from the modified Booth's encoder 12 are provided to the fifty-four compression units, respectively. Each vertical data signal, which has a 32-bit partial product, is finally compressed to a 1-bit carry signal and a 1-bit sum signal by means of a corresponding compression unit. The carry and sum signals provided by each compression unit have the same delay time with respect to other compression units. The final carry and sum signals from the compressor 14 are provided to the 108-bit conditional sum adder 16. This 10-bit conditional sum adder 16 generates the final data signal of the (54.times.54)-bit multiplier. However, since the multiplier implements a modified Booth's encoder to produce vertical data signals, the multiplier hardware structure is complicated.
FIG. 4A shows a pass-transistor multiplexer used in both the 4-to-2 compressor and the 108-bit conditional sum adder. FIG. 4B is a detailed circuit diagram of the pass-transistor multiplexer of FIG. 4A. Referring to FIG. 4B, when a control signal S is at low level, data signal D0 is selected. When the control signal S is at high level, data signal D1 is selected. The output signal of the multiplexer is used as an input signal of a next stage multiplexer.
FIGS. 5A and 5B show the 108-bit conditional sum adder of FIG. 3 in greater detail. In FIGS. 5A and 5B, the prior art 108-bit conditional sum adder has fourteen half-adder blocks (HA), a first group of fourteen first carry lookahead adder blocks (CLA1's), a second group of seven second carry lookahead blocks (CLA2's), three multiplexers (MUX) and fourteen conditional sum selection blocks (CSS). One half-adder HA and one carry lookahead adder block CLA1 of the first carry lookahead adder blocks constitute one 8-bit moduled conditional carry selection block as seen in FIG. 6. One example of the second carry lookahead adder blocks is shown in FIG. 7.
Returning to FIGS. 5A and 5B, in the 108-bit conditional sum adder, the delay time caused by one multiplexer is t.sub.MUX, a time interval between the input and output signals of the conditional sum adder. Each input signal of the conditional sum adder is delayed by t.sub.MUX in the half-adder, further delayed by 4t.sub.MUX in the first lookahead adder block CLA1, further delayed by 3t.sub.MUX in the second lookahead adder block CLA2, further delayed by 3t.sub.MUX in the serially connected three multiplexers, and finally delayed by one more t.sub.MUX in the conditional sum selection block CSS. Thus, the delay time of all multiplexers is 12t.sub.MUX.
The critical path as stated above is caused by simultaneously generating the sum signal and the carry signal. Since carry propagation time is long relative to sum propagation time, the operating speed of the conditional sum adder is determined by the carry propagation signal.
In addition, however fast the propagation of the sum signal is up to the final output, since the carry and sum signals in the prior art conditional sum adder must be propagated to a next stage multiplexer, a final output signal is delayed by t.sub.MUX beyond the completion of the final carry signal.