Performance improvement of Si-CMOS devices, which form the most important building blocks in logic applications, is of significant importance. In specific, higher speed and lower power consumption together with miniaturization are essential requirements for future ULSI chips. One major deterrent against high speed performance is the low mobility of holes in Si. In addition, devices with 0.1-0.15 micron gates will have to be exposed using either electron-beam lithograph or x-ray lithography, both being more complicated and expensive techniques compared to optical lithography. Furthermore, device reliability, threshold voltage control, and yield problems become more pronounced on that scale. The choice of a material system fully compatible with Si technology, but having superior properties compared to Si would improve the power-delay product of CMOS. It is conceivable that similar or better performance than for 0.15 micron Si-CMOS can be achieved at 0.25 micron gate length, thus allowing the gates to be exposed by optical lithography.
One example of a material system compatible with Si technology, is described in U.S. Pat. No. 5,019,882 which issued on May 28, 1991 to P. M. Solomon entitled "Germanium Channel Silicon MOSFET" and assigned to the assignee herein. In U.S. Pat. No. 5,019,882, a channel having improved carrier mobility comprises an alloy layer of silicon and germanium which is grown above a silicon substrate. The alloy layer is kept thin enough for proper pseudomorphic dislocation free growth. A layer of silicon is formed over the alloy layer and is oxidized partially through to form a dielectric layer. A gate region is formed over the silicon dioxide.
In U.S. Pat. No. 5,155,571 which issued on Oct. 13, 1992 to K. L. Wang et al, complementary field effect transistors are described having strained superlattice structure. In U.S. Pat. No. 5,155,571 a silicon CMOS transistor structure is described utilizing an n-type strained Ge.sub.x Si.sub.1-x layer for the p-channel transistor whereby the mobility of the holes is increased to match the mobility of the electrons in n-channel transistor. Further, a complementary modulation doped field effect transistor is described using strained Si and GeSi alloy layers and a relaxed Ge.sub.x Si.sub.1-x to enhance the electron mobility in the n-channel transistor while a strained Si or a strained Ge.sub.x Si.sub.1-x alloy layer is used to enhance the hole mobility in the p-channel transistor. Regions for p-channel transistors and regions for n-channel transistors are separate regions with respective channels made of a different structure.
In Japanese patent 63-308966(a) which issued on Dec. 16, 1988 to K. Fujimori, n and p-channel transistors are described on a substrate which are formed by changing silicon and silicon-germanium mixed crystal layers in the vertical direction in the same composition and film thickness and making only impurity density to differ in structure under the gate electrodes.
In U.S. Pat. No. 5,006,912 which issued on Apr. 9, 1991 to C. Smith et al, a heterojunction bipolar transistor is described having an emitter which comprises an epitaxial layer of silicon grown on a silicon and germanium base layer. The active region of the transistor comprises a semiconductor having a silicon/silicon and germanium strained lattice, and the lattice strain being such as to produce a predetermined valence band offset at the emitter/base junction while maintaining commensurate growth. The advantage of the lattice strain is such as to enhance the effective mobility of electrons in the base. The germanium content of the silicon and germanium base layer lies within the range of from 12% to 20%
Another example of a field effect transistor having a high carrier mobility and suited for high speed operation is described in U.S. Pat. No. 5,241,197 which issued on Aug. 31, 1993 to E. Murakami et al. In U.S. Pat. No. 5,241,197 a strained control layer is provided beneath a germanium layer to impose a compressive strain on the germanium layer, and the composition of the strain control layer is used to generate the compressive strain. The carrier mobility in the strained germanium layer is large.