Magnetic random-access memories (MRAM) have been the object of a renewed interest with the discovery of magnetic tunnel junctions having a strong magnetoresistance at ambient temperature. These MRAM present many advantages such as speed (a few nanoseconds of duration of writing and reading), non volatility, and insensitivity to ionizing radiations. Consequently, they are increasingly replacing memory that uses more conventional technology based on the charge state of a capacitor (DRAM, SRAM, FLASH).
A conventional MRAM cell 1, in the simplest implementation, is represented in the example of FIG. 1. The cell 1 comprises a magnetic tunnel junction 2, formed from an insulating layer 22 disposed between a reference layer 23, having a fixed magnetization, and a storage layer 21, having a magnetization which direction can be changed upon writing of the memory cell. A first current line 4 is in communication with the storage layer 21, and a second current line 5 is placed orthogonal with the first current line 4, in communication with the reference layer 23. The MRAM cell 1 further comprises a CMOS select transistor 3, electrically connected to the magnetic tunnel junction 2, and which opening and closing is controlled by a word line 6 in order to address each MRAM cell 1 individually.
The reference and the storage layers, of different coercivity, are typically made of 3d metals such as Fe, Co or Ni or their alloys. Eventually, boron can be added in the layer composition in order obtain an amorphous morphology and a flat interface. The insulating layer typically consists of alumina (Al2O3) or magnesium oxide (MgO). Preferably, the reference layer consists of several layers forming a synthetic antiferromagnetic layer, as described in U.S. Pat. No. 5,583,725.
During a write operation, the transistor 3 is off and no current flows through the junction 2. A first field current 41 is passed through the first current line 4, generating a first magnetic field 42, and a second field current 51 is passed through the second current line 5, generating a second magnetic field 52. The intensity and synchronization of the first and second field currents 41, 51 are adjusted so that only the magnetization of the storage layer 21, located at the intersection of the two active current lines 4, 5, can switch, to write data, under the combined effect of the first and second magnetic fields 42, 52, respectively.
During a read operation, the transistor 3 is open allowing for a sense current (not shown) to flow through the magnetic tunnel junction 2 via the first current line 4, allowing for measuring the magnetic tunnel junction resistance R. When the respective magnetizations of the reference and storage layers 23, 21 are antiparallel, the junction resistance is high (Rmax) corresponding to a low logic state “0”. On the other hand, when the respective magnetizations are parallel, the resistance becomes low (Rmin) corresponding to a high logic state “1”. The logic state of the cell 1 is usually determined by comparing the junction resistance R to a reference cell, or an array of reference cells, each reference cell having a resistance of typically Rref=(Rmin+Rmax)/2, corresponding to a value in-between the high logic state “1” and low logic state “0”.
In order to ensure that the MRAM cell of FIG. 1 is working properly during the write operation, i.e., in order to obtain a bi-stable switching of the magnetization of the storage layer 21, the magnetic tunnel junction 2 must have an anisotropic form, preferably with an aspect ratio of 1.5 or higher. The anisotropic form of the junction 2 allows for good writing selectivity of the MRAM cell 1 located at the intersection of the two active current lines 4, 5, compared with other cells 1 in an array, addressed by only one of the lines 4, 5. Indeed, the switching of the magnetization of the storage layer 21 in the junction 2 with an anisotropic form is possible only under the influence of the two magnetic fields 42, 52, generated by the lines 4, 5. MRAM cells 1 having an anisotropic form also show good thermal and/or temporal stability of the written data.
Other exemplary configurations of conventional MRAM cells can be found in U.S. Pat. Nos. 4,949,039 and 5,159,513, while U.S. Pat. No. 5,343,422 is concerned with the implementation of a random-access memory (RAM) based on a MRAM cell structure.
A MRAM cell configuration with a thermally assisted switching (TAS) writing procedure is described in document US2005002228 and represented in FIGS. 2a and 2b. In the example of FIG. 2a, the TAS-MRAM cell 10 differs from the MRAM cell 1 represented in FIG. 1 by having a current line 7, electrically connected to the magnetic tunnel junction 2, and a field line 8, placed above and perpendicular to the current line 7 in communication with the ferromagnetic storage layer 21.
The magnetic tunnel junction 2, represented in more detail in FIG. 2b, comprises an antiferromagnetic reference layer 24, exchange biasing the adjacent ferromagnetic reference layer 23 in order to pin its magnetization below a temperature corresponding to the blocking temperature TBR of the antiferromagnetic reference layer 24. The junction 2 also comprises an exchange coupling antiferromagnetic storage layer 21b, able to pin the magnetization of the adjacent ferromagnetic storage layer 21 below a temperature corresponding to the blocking temperature TBS of the antiferromagnetic storage layer 21b. Typically, a blocking temperature TBR up to about 400° C. can be attained when the antiferromagnetic reference layer is made of a NiMn or a PtMn-based alloy, while a blocking temperature TBS of about 200° C. to 150° C. is achieved when the antiferromagnetic storage layer is made of an IrMn-based alloy or a FeMn-based alloy, respectively. The magnetic tunnel junction 2 also comprises an insulating layer 22 disposed between a ferromagnetic reference layer 23 and the ferromagnetic storage layer 21, as described above.
During a write operation of the TAS-MRAM cell 10, a heating current pulse 31 is sent through the magnetic tunnel junction 2 via the current line 7 when the select transistor 3 is on, in order to increase the temperature of the magnetic tunnel junction 2. Using a heating current 31 lasting several nanoseconds with a current density between 105 A/cm2 and 107 A/cm2, the junction 2 can be heated to a high temperature threshold between 120° C. and 200° C., lying between TBS and TBR. At such a temperature, the magnetic coupling between the ferromagnetic storage layer 21 and antiferromagnetic storage layer 21b disappears and the magnetization of the storage layer 21 can be freely adjusted. The heating current 31 is then turned off by setting the select transistor 3 off. During the cooling of the magnetic tunnel junction 2 a field current 81 is passed in the field line 4, in order to generate a magnetic field 82 capable of reversing the magnetization direction of the storage layer 21. The magnetization is then fixed in its reversed orientation once the junction 2 has cooled to a low temperature threshold at which the storage layer 21 is pinned.
In contrast with the MRAM cell configuration of FIG. 1, the TAS-MRAM cell 10 of FIGS. 2a and 2b is characterized by a considerably improved thermal stability of the storage layer 21, exchange biased by the antiferromagnetic storage layer 21b. An improved writing selectivity is also achieved due to the selective heating of the TAS-MRAM cell 10 to be written, in comparison with the neighboring cells remaining at ambient temperature. The TAS-MRAM cell 10 allows for a better stability in a zero magnetic field (retention) by using materials with high magnetic anisotropy at ambient temperature, and a higher integration density without affecting its stability limit. Moreover, reduced power consumption is achieved during the write operation of the TAS-MRAM cell 10, since the heating current 31 and the field current 81 required to heat the cell 10 and switch the magnetization of the storage layer 21, respectively, are lower than the respective first and second field currents 41, 51, used in the MRAM cell configuration of FIG. 1.
An improvement of the TAS-MRAM cell where the magnetic tunnel junction has a circular geometry is disclosed in the patent application having publication number US20060291276. Here, the field current is determined only by the magnetocrystalline anisotropy of the storage layer without contribution from the shape anisotropy, yielding to a further reduction in field current and to lower power consumption.
Another improvement with respect to the above MRAM architectures is the spin transfer torque (STT) architecture, represented schematically in FIG. 3 and initially described in U.S. Pat. Nos. 5,695,864 and 6,172,902. In contrast with the cell configuration of FIG. 2a, the STT-based MRAM cell 100 of FIG. 3 does not require the field line 8. Indeed, during the write operation of the cell of FIG. 3, instead of applying a magnetic field, a spin polarized current 32 is passed through the magnetic tunnel junction 2 when the select transistor 3 in the open mode (ON). The spin-polarized current 32 exerts a torque able to switch the magnetization of the storage layer 21 in a direction corresponding to the magnetization of the reference layer 23.
U.S. Pat. No. 6,950,335 describes a STT-based MRAM cell 100 with a TAS writing procedure using the cell configuration shown in FIG. 3 and the magnetic tunnel junction 2 represented in FIG. 2b. During the write operation of the STT-based TAS-MRAM cell 100, the heating current pulse 31 is sent through the magnetic tunnel junction 2 in order to heat the junction 2 to a high temperature threshold at which the magnetization of the storage layer 21 can be freely adjusted, as described above. The heating current 31 is then turned off by by turning off the select transistor 3 and, during the cooling of the magnetic tunnel junction 2, the spin polarized current 32 is passed through the junction 2 in order to switch the magnetization of the ferromagnetic storage layer 21.
The STT-based TAS-MRAM cell 100 is a promising route for high density MRAM because the write current, or spin polarized current 32, scales directly with the cell size, which is not the case in the previously described implementations. Indeed the spin polarized current 32 scales in an inversely proportional fashion with the area of the magnetic tunnel junction 2. Moreover, STT-based TAS-MRAM cells 100 allow for fast switching of the storage layer magnetization and for higher cell density since no magnetic field line is required.
The STT-based TAS-MRAM cell 100 described above involves a so-called longitudinal configuration where the spins of the spin-polarized current 32 are injected collinearly with the magnetization of the storage layer 23. Such longitudinal configuration is normally achieved during the fabrication process of the cell 100, by depositing the reference and storage layers 23, 21 in the presence of an external magnetic field, applied with a field direction during the deposition of the reference layer 23 that is collinear to the direction of the field applied during the deposition of the storage layer 21. This is illustrated in FIGS. 5a to 5b where the external magnetic field directions during the deposition of the reference layer 21 (FIG. 5a) and storage layer 23 (FIG. 5b), are represented by the plain arrow. In FIG. 5a-c, the circles represent schematically the magnetic tunnel junction 2 viewed from the top. FIG. 5c shows the direction of the external field (dashed arrow) applied during the annealing of the magnetic tunnel junction 2 after deposition of the layers. Annealing of the junction 2 is typically performed at a temperature higher than 300° C.
The STT-based TAS-MRAM cell 100 suffers from requiring high spin polarized current densities, typically in the order of 4 MA/cm2 for a pulse width of 10 ns, and increasing for shorter pulse width, in order to switch the magnetization of the storage layer 21. This results in large and unpractical cell sizes, due to large select transistors 3 necessary to drive such high currents. High currents may also yield high power dissipation, and possible wear and loss of the magnetic tunnel junction 2 reliability, in particular of the insulating layer 22. For small cell size, for example below 45 nm, simultaneous thermal stability and a small write spin polarized current is difficult to achieve. Moreover, the speed of the write operation is limited to the 10 ns range since the switching of storage layer magnetization is triggered by thermal activation which is stochastic in nature.
In order to decrease the spin-polarized current density, U.S. Pat. No. 6,603,677 proposes adding a “spin polarizing” layer or using a synthetic antiferromagnetic (SAF) multilayer. Improving the stability of the STT-based TAS-MRAM cell has also been addressed by Nakayama et al, Journ. Appl. Phys. 103, 07A710 (2008), who propose using perpendicularly magnetized magnetic layers, or in U.S. Pat. No. 6,950,335, disclosing a combination of TAS and STT. However, none of the above solutions allows for a significant reduction in the write current density.