1. Field of the Invention
The present invention relates to a semiconductor memory cell, in particular to a static random access memory cell (SRAM cell) formed by coupling seven transistors.
2. Description of the Related Art
Static random access memory (SRAM) has the advantages of quick access and low power consumption, and thus the SRAM is used extensively in electronic products including notebook computers, mobile devices and game players.
Wherein, a conventional static access memory cell with a six-transistor (6T) structure is formed by six metal oxide semiconductor field effect transistors (MOSFET) coupled to one another. With reference to FIG. 1 for a schematic view of a conventional six-transistor SRAM cell, the six-transistor SRAM cell (6T-SRAM Cell) 1 comprises a first inverter 11, a second inverter 12, a first transistor 13 and a second transistor 14. The first inverter 11 and the second inverter 12 are formed by cross-coupling a p-type metal oxide semiconductor (P-MOS) and an n-type metal oxide semiconductor (N-MOS) respectively, and a first input node 111 of the first inverter 11 is coupled to a second output node 122 of the second inverter 12, and a first output node 112 of the first inverter 11 is coupled to a second input node 121 of the second inverter 12 to form a latch circuit. The latch circuit is coupled between a power source and the ground, and the first output node 112 and the second output node 122 are two storage nodes of the memory cell respectively.
A gate of the first transistor 13 and a gate of the second transistor 14 are jointly coupled to a word line 100. A drain of the first transistor 13 and a drain of the second transistor 14 are coupled to the first output node 112 and the second output node 122 respectively. A source of the first transistor 13 and a source of the second transistor 14 are coupled to a pair of complementary bit lines 101 and 102 respectively. When the word line 100 is switched to a high voltage level of the memory cell, the first transistor 13 and the second transistor 14 are conducted to form a pass gate for controlling an operation of reading or writing data in the memory cell, and allowing the pair of complementary bit lines 101 and 102 to access the storage nodes. When the word line 100 is switched to a low voltage level of the memory cell, the first transistor 13 and the second transistor 14 are cut off, and the pair of complementary bit lines 101 and 102 are disconnected from the storage nodes, and no memory data can be accessed.
The conventional six-transistor SRAM cell adopts one word line to read and write data. When the memory cell is accessed, the pass gates of adjacent unselected memory cells are weakly turned on. As a result, the current is leaked, and data of adjacent unselected memory cells may be turned over in a serious case, and this phenomenon is called “half-selected disturb”. In addition, during the reading process, the pass gate of the memory cell is turned on, a data voltage in the memory cell rises or drops slightly, and the data in the memory cells may be turned over in a serious case, and this phenomenon is called “read disturb”.
To overcome the aforementioned problems, related manufacturers and designers provided an eight-transistor static random access memory cell (8T-SRAM Cell) formed by connecting six transistors in series with two transistors and adding another read word line and a pair of complementary read bit lines. The two serially connected transistors are provided for reading and writing data in the memory cell by different word lines and bit lines to eliminate the read disturb occurred when reading data in the memory cell and the half-selected disturb of the adjacent memory cells.
However, the eight-transistor static random access memory cell achieves the effect of having independent read port and write port by means of the additional two pass gates, the pair of complementary read bit lines and a read word line, so that the integrated circuit design of the eight-transistor static random access memory cell incurs a higher complexity, an increased unit area and a higher power consumption. In addition, the swing amplitude of the read bit line may be restricted by the data of the memory cells, so that the eight-transistor static random access memory cell may have a lower sensing margin, a lower read stability, a higher operation voltage and a higher power consumption.