Latched comparator circuits are used in various types of electronic circuitry, e.g. for comparing two input voltages. For example, in an analog-to-digital converter (ADC), one or more latched comparators may be utilized for comparing an input voltage with one or more reference voltages for generating a digital value based on the input voltage. Furthermore, in memory circuits, such as a random-access memory (RAM), e.g. a static RAM (SRAM) or a dynamic RAM (DRAM), or a read-only memory (ROM), a latched comparator may be utilized as or in a sense amplifier of a read-out circuitry of the memory circuit for determining whether a logic ‘0’ or ‘1’ is stored in a memory cell of the memory circuit.
A latched comparator may have a differential output port comprising two output terminals. A latched comparator typically operates in two clock phases; a reset phase and a compare-and-latch phase. During the reset phase, the latched comparator is reset, e.g. by balancing the two output terminals of the latched comparators. During the compare-and-latch phase, the latched comparator is operative to compare the two input voltages and generate a differential output voltage corresponding to a logic ‘0’ or ‘1’ based on the two input voltages.
A latched comparator typically includes one or more cross-coupled transistor pairs, such as a cross-coupled NMOS pair and/or a cross-coupled PMOS pair, operatively connected between two output terminals. The one or more cross-coupled transistor pairs provide a positive feedback loop. The positive feedback loop forces one of the output terminals to a first voltage level, such as the supply voltage, and the other output terminal to another voltage level, such as ground, during the compare phase based on the two input voltages.
A latched comparator may comprise a switch connected between the two output terminals. During the reset phase, the switch is closed for balancing the voltages at the two output terminals, e.g. by forcing the voltages to a common level. Alternatively or additionally, the latched comparator may comprise switches connected between each of the output terminals of the latched comparator and a common reference voltage level, such as the supply voltage or ground. Said switches are closed during the reset phase and open during the compare-and-latch phase.
The operational speed of a latched comparator may be a limiting factor for the operational speed of electronic circuits comprising the latched comparator. For example, the operational speed of a latched comparator may be a limiting factor for the maximum sampling frequency of an ADC comprising the latched comparator. As another example, the operational speed of a latched comparator utilized for sense amplification in a memory circuit may be a limiting factor for the maximum read-out rate of the memory circuit. Hence, there is a need for a latched comparator circuit having an improved operational speed.