An ESD (Electro-Static-Discharge) protection device as a type of semiconductor devices. The ESD protection device protects semiconductor ICs, etc. from static electricity, etc. Various electronic devices including mobile communication terminals, digital cameras, and laptop PCs are provided with semiconductor integrated circuits constituting logic circuits, memory circuits, etc. Such semiconductor integrated circuits are low-voltage drive circuits composed of micro wiring patterns formed on semiconductor substrates, and thus generally fragile against electrostatic discharge such as surge. Therefore, ESD protection devices are used for protecting such semiconductor integrated circuits from surge.
When an ESD protection device is provided in a high-frequency circuit, there is the problem of being affected by parasitic capacitance of a diode. More specifically, the insertion of the ESD device into the signal line shifts impedance under the influence of the parasitic capacitance of the diode, and as a result, loss of signal may be caused. In particular, ESD protection devices for use in high-frequency circuits are required to be low in parasitic capacitance, in order not to decrease high-frequency characteristics of signal lines connected or integrated circuits to be protected. Thus, Patent Document 1 discloses an ESD protection device with circuit characteristic degradation suppressed by reducing the influence of the parasitic capacitance of a diode.
Patent Document 1: WO 2012/023394 A.
In Patent Document 1, on a surface of a semiconductor substrate with an ESD protection circuit, an inorganic insulating layer of SiO2 is provided as a protection film, and the inorganic insulating layer is provided with an in-plane wiring of Cu. For this reason, Patent Document 1 has problems such as failure to prevent the capacitance of the ESD protection device itself from being increased, due to the fact that it is not possible to suppress the parasitic capacitance generated between the in-plane wiring and the semiconductor substrate even when it is possible to reduce the influence of parasitic capacitance of the diode.
In addition, in Patent Document 1, because the inorganic insulating layer is formed by a thin-film formation method such as sputtering, asperity appears at the surface of the inorganic insulating layer under the influence of the circuit pattern of the ESD protection circuit formed in the semiconductor substrate. For this reason, when the inorganic insulating layer with surface asperity is provided with the in-plane wiring, parasitic capacitance varies which is generated between the in-plane wiring and the semiconductor substrate. The generation of the varying parasitic capacitance causes problems such as difficulty in adjusting the shift in impedance for high-frequency circuits.