As semiconductor technology continues to scale, creating capacitors with acceptable capacitance values (e.g., >20 fF for dynamic random access memories (DRAMs)) becomes harder. Currently, the path for creating high capacitance structures on-chip is by employing deep trench structures or 3-D stacked structures to increase surface area, as shown in FIGS. 1A and 1B, respectively, with high dielectric constant material. Additionally, complex process integration is required to increase the surface area of the conducting plates as much as possible to increase the capacitance. Even with the complex designs and difficult process integration, for future scaling of DRAM devices (or other on-chip capacitor devices such as application-specific integrated circuits (ASICs)), high dielectric constant materials are required, and most DRAM foundries have begun implementing relatively high dielectric constant materials into their integration. However, such efforts are still not sufficient for continued scaling of DRAM capacitors and are not compatible with current semiconductor processing.
Therefore, there is a need for scalable capacitors that can be used in a variety of capacitance requirements, and particularly on-chip capacitance requirements, that would be useful for a wide range of electronics applications such as, but not limited to, ASICs, DRAM, and sensors.