The market for portable electronic devices, such as personal digital assistants (PDAs), mobile telephones, and portable computers, is increasing rapidly. This growth is due in large part to more powerful processors and expanded memory resources, both of which are required to support a proliferation of productive and entertaining applications. Unfortunately, performance enhancements tend to increase power consumption, a problem that is particularly troublesome for battery operated systems. Larger and extra batteries help, but are cumbersome and expensive. The demand for improved performance is therefore at odds with the demand for small, efficient, and inexpensive mobile devices.
Achieving peak performance in electronic devices generally requires relatively high supply voltages and data rates. Peak performance is not always required, however, in which case lower supply voltages and reduced data rates can be used to save power. For example, processing circuitry may recognize that a given task may be performed at a low data rate without interfering with the user's experience, and might therefore enter into a power-saving mode that employs a reduced supply voltage to convey data at a relatively low rate.
A number of techniques for regulating signaling rates and supply voltages have been implemented in mobile devices or proposed in the literature. Some such techniques, commonly known as Dynamic Voltage Scaling, control supply voltage according to performance requirements. Variations in computational or signaling-rate requirements can be exploited to reduce the average energy used by a device while maintaining an acceptable level of performance. Reducing the average energy relaxes battery requirements, allowing for longer life, smaller batteries, or both.
Processors are not alone in consuming undesirable levels of energy. Memory systems also consume energy, and the amount of energy consumed likewise increases with performance. However, dynamic voltage and frequency control has been difficult to implement in memory systems, particularly in dynamic random-access memory (DRAM) and Flash memory. This is because memory-cell voltages are hard to scale dynamically without severely impacting yield and latency. Furthermore, high-performance memory devices commonly use high-speed device interfaces that would suffer unacceptable latencies when voltage supplies are scaled. There is therefore a need for memories that support dynamic scaling of power and performance.