The multiplication of x-place multiplicands (x=0, 1, 2. . .m-1) by a y-place multiplier factor (y=0, 1, 2. . .n-1) (m and n are whole, positive numbers) that are represented as binary numbers can be implemented according to FIG. 1. This shows a matrix MA that contains the partial products PP that arise in the multiplication. The multiplicand is thereby referenced A and the multiplier factor is referenced B. The partial products can be generated from the multiplier factor place and the multiplicand place with AND circuits. A product place P is generated by summing up the partial products per column of the matrix. A carry from the next, less significant place of the product is thereby also to be taken into consideration. Three fields can be distinguished in FIG. 1. Field III recites the partial products that are necessary for the multiplication. Field I recites partial products that are not necessary in the multiplication; the same is also true of Field II. The places of the matrix are recited with 0 in these Fields I and II.
AND circuits that form the partial products and adder circuits that sum up the partial products per column are thus required in order to construct a multiplier that multiplies according to the matrix of FIG. 1. When such a multiplier is to be realized, it is necessary that the AND circuits and the adder circuits are arranged in an especially advantageous way in order to create a realization on one chip with optimally low space requirement and optimally favorable transit time conditions. It is also necessary that such a multiplier can be very easily tested.