This invention relates to a semiconductor memory device, and more particularly to technology which is effective when applied to, for example, an EEPROM (electrically erasable programable read only memory) that is electrically written and erased.
MNOS (metal nitride oxide semiconductor) is an insulated-gate field effect transistor which has a gate insulator film of double layer structure consisting of a comparatively thin silicon oxide film (oxide) and a comparatively thick silicon nitride film (nitride) formed thereon (hereinbelow, simply termed `MNOS transistor` or `MNOS`). It can electrically perform, not only the writing of data to be stored, but also the erasing of stored data.
By way of example, an N-type source region and drain region spaced from each other are formed in the surface of a P-type silicon region, and a gate electrode made of N-type polycrystalline silicon is formed on the surface of the P-type silicon region between the source and drain regions, through a gate insulator film which consists of, e.g., a silicon oxide film 20 .ANG. thick and a silicon nitride film 500 .ANG. thick. The P-type silicon region forms the substrate gate region of the MNOS.
In the erased state or in the state in which no storage data is written, the gate voltage-drain current characteristic of the MNOS is such that the threshold voltage is a minus voltage.
In order to write or erase the storage data, the gate insulator film is subjected to a high electric field under which the injection or emission of carriers arises owing to tunneling.
In the writing operation, the ground potential or circuitry substantially equal to 0 V, for example, is applied to the substrate gate, while a high voltage of, for example, +15 V is applied to the gate.
A low voltage substantially equal to 0 V or a high voltage, e.g., +12 V is applied to the source region and drain region in accordance with data to be written.
According to the plus high voltage of the gate, a channel is induced in the surface of the silicon region between the source region and the drain region. The potential of this channel becomes equal to that of the source region and drain region. When the voltage of 0 V is applied to the source region and drain region as described above, a high electric field corresponding to the high voltage of the gate acts on the gate insulator film. As a result, electrons as carriers are injected from the channel into the gate insulator film by tunneling. Thus, the threshold voltage of the MNOS changes from a minus voltage to a plus voltage by way of example.
In the case where +12 V is applied to the source and drain regions as described above, the potential difference between the gate and the channel decreases to several volts. Such a small voltage difference is insufficient for giving rise to the injection of electrons based on tunneling. Therefore, the threshold voltage of the MNOS does not change.
On the other hand, the erasing is performed in such a way that a high voltage, e.g., +15 V is applied to the substrate gate with the gate held at 0 V, whereby tunneling in the reverse direction is generated to bring electrons as carriers back to the substrate gate.
The substrate gate is made, for example, a P-type well region which is formed in an N-type semiconductor substrate. For this reason, the N-type semiconductor substrate has its potential changed according to the potential change of the well region in order to maintain the reverse-biased state relative to the well region. Accordingly, with the EEPROM performing such writing/erasing operations, the peripheral circuit thereof is inevitably constructed of only N-channel MOSFETs formed in a separate P-type well region to which no high voltage is applied even in the writing mode. The reason is as stated below. In order to construct a CMOS circuit, a P-channel MOSFET needs to be formed on an N-type semiconductor substrate. The inventors' study has revealed that, in this case, when the substrate is brought to a high potential, e.g., +15 V according to the change of the well potential as described above, the P-channel MOSFET formed thereon has its effective threshold voltage increased by a substrate effect attributed to the high voltage and becomes inoperative with an ordinary signal level (for example, 0-+5 V).