High-speed digital transmission systems and high-speed digital input/output (I/O) busses are often required to receive or regenerate data using a clocking signal that is recovered or extracted from the serial bit stream. Variation in the data rate, commonly known as jitter, can complicate the data recovery and data regeneration process. Various devices have been used to address jitter in these applications.
A typical serializer/deserializer (SerDes) device receives a serial bit stream on its serial input. The serial bit stream includes a serial data stream and a clocking signal. The SerDes device extracts the clocking signal that is embedded in the serial bit stream (a process also known as bit synchronization), deserializes the serial bit stream, and defines a character boundary in the resulting parallel bit stream (a process also know as character synchronization, framing, aligning, etc.).
The above-described process is reversed on the transmit side. For example, on the transmit side, the SerDes device receives a parallel bit stream, generates a serial transmit clock, time multiplexes the parallel bits into a serial bit stream, and drives the serial bit stream out of the serial outputs.
SerDes devices are configured as a commodity monolithic integrated circuit (IC), and there are a variety of them that support different bit rates (for bit synchronization) and protocols (for character synchronization).
One type of monolithic IC implements the serial advanced technology attachment (SATA) bus specification. The SATA specification is challenging in that it provides for the transmission of coded data with an embedded clock that also has spread spectrum modulation on it. Spread spectrum clocking (SSC) for such applications is difficult for any phase-locked-loop (PLL)-based clock recovery circuit to track, especially PLL-based circuitry found in the current population of commodity monolithic SerDes devices.
Another type of monolithic IC used for these high-speed applications, especially in the telecom industry, is a Clock and Data Recovery (CDR) circuit (or device). CDR devices are available to support a variety of bit rates and jitter tolerances. The telecom industry uses large networks spanning long distances. Multiple repeaters are often used, each of which comprise one or more CDRs to meet stringent jitter specifications aimed at preventing excessive jitter buildup throughout the network. For instance, Synchronous Optical Network/Synchronous Digital Hierarchy (SONET/SDH) has detailed specifications that a repeater must meet in terms of jitter tolerance, jitter transfer, and jitter generation. In order to meet these specifications, a SONET-compliant repeater usually uses a CDR.
A CDR includes the ability to output the clocking signal and re-timed data from its bit synchronization. Often, CDRs are employed in repeaters simply to control jitter accumulation across the network. These CDRs usually provide high jitter tolerance, transfer jitter frequencies only up to a cutoff frequency with little peaking (<0.1 decibel (dB)), and introduce very little jitter on their own. Also, CDR functionality is often employed in SerDes devices to provide a defined tolerance to jitter. However, this intrinsic CDR functionality for a SerDes device typically does not receive 100% of the design focus, and thus the resulting tolerance to jitter is often susceptible to design trade-offs. Further, switching often occurs in the same SerDes monolithic device that includes this intrinsic CDR functionality, often consuming some of the design jitter tolerance.
Thus, although jitter is often addressed to some degree by monolithic devices, they offer limited flexibility in design and/or operation of systems handling serial data. Thus, a need exists in the industry to address the aforementioned and/or other deficiencies and/or inadequacies.