In a constant voltage circuit converting an input voltage into an output voltage having a constant voltage and outputting the same, ordinarily, a voltage obtained from dividing the output voltage is compared with a reference voltage, and feedback control is carried out to an output transistor for outputting the output voltage, in such a manner as to minimize a voltage difference. Therefore, some time delay is required for returning the output voltage to a predetermined voltage value after the change in the output voltage is transmitted to the output transistor. Such a time delay required for the transmission corresponds to a response delay. When the response delay is large, the output voltage may change greatly for a case where, for example, the load electric current transitionally change greatly, and, in the worst case, the output voltage may lower under a guaranteed lowest operation voltage of a circuit connected to the output terminal, and thus, an apparatus using the circuit may have a trouble.
In many cases, such a response delay depends on an input capacitance of a transistor included in the constant voltage circuit, a phase compensating capacitance, and values of electric currents for charging or discharging these capacitances. Especially, an input capacitance of an output transistor used for outputting a large electric current or the phase compensating capacitance for phase compensation may be very large, and thus, it may cause a serious response delay. That is, in order to improve a response speed, the above-mentioned input capacitance should be reduced, or, the value of the electric current for charging or discharging the capacitance should be increased. However, the input capacitance is determined approximately by a size of the output transistor required for outputting a large electric current or a value of the capacitance required for keeping circuit stability. Therefore, actually a method by increasing the electric current value for charging or discharging the input capacitance may be used in common. In order to increase the charging or discharging electric current, a bias current value should be increased. As a result, an electric current consumption in the constant voltage circuit itself increases accordingly.
Recently, in consideration of an environmental problem, energy saving in electric appliances is required. In particular, as to a constant voltage circuit used in a portable device driven by a battery, energy saving in the constant voltage circuit must be achieved in order to elongate a possible continuous operation time of the device. For this purpose, it is preferable to lower, as much as possible, an electric current consumption required for operating a control circuit controlling an output transistor in the constant voltage circuit. Further, various applications are mounted in the portable device, the constant voltage circuit which can output a larger electric current, can operate with a reduced voltage, and can output a low voltage, is required, and thus, the size of the output transistor increases accordingly. As a result, serious degradation in the response speed may occur accordingly. Further, a circuit connected to the constant voltage circuit has a range of a guaranteed operation voltage, which is recently reduced due to miniaturization of the circuit which is recently demanded. As a result, further reduction in output voltage fluctuation of the constant voltage circuit is required.
In order to solve these problems, as a first method in the prior art to improve the output voltage response speed in response to a possible steep change in a load electric current, Japanese Laid-Open Patent Application 2000-47740 for example discloses a configuration in which, when the output voltage lowers, the reduction in the output voltage is transmitted to a non-inverted input end of a comparator via a capacitor, and, when a voltage in the non-inverted input end of the comparator thus lowers, a PMOS transistor controlled by an output signal of the comparator is turned on, and thus the output terminal is charged. Thereby, the reduction in the output voltage is controlled.
As a second method in the prior art, Japanese Laid-Open Patent Application 2005-47740 for example discloses a configuration in which, as shown in FIG. 7, normally an output voltage Vout is made constant by means of carrying out control of operation of an output transistor M101 by a first error amplifier AMPa having a superior linearity. When the output voltage Vout lowers steeply, before the first error amplifier AMPa responds thereto and carries out control of operation of the output transistor M101, a second error amplifier AMPb having superior response is used to carry out control of operation of the output transistor M101 for a predetermined duration, so as to make the output voltage Vout constant. By configuring so, it is possible to improve an output voltage response speed with respect to a possible steep change in an input voltage or a load electric current. As a result, it is possible to provide a constant voltage circuit having both superior linearity and superior response.
In a third method in the prior art, Japanese Laid-Open Patent Application 2006-18774 for example discloses a configuration in which an operation electric current of a voltage amplifying circuit is controlled with a detection of a change in a power source voltage, and thereby, an electric current consumption reduces during normal operation having no change in the power source voltage, while, in a transition response occasion in which the power source voltage changes, response improves with the increased electric current consumption.
However, in the above-mentioned first method, the PMOS transistor charging the output terminal should have sufficient capability for compensating a possible steep change in the load electric current. As a result, the size of the PMOS transistor should be very large. As a result, a capacitance in a gate of the PMOS transistor increases. Accordingly, in order to rapidly turn on the PMOS transistor for achieving rapid response, an electric current consumption in the comparator controlling the PMOS transistor should increase. As a result, the electric current consumption increases accordingly.
In the above-mentioned second method, the second error amplifier AMPb detecting sleep reduction in the output voltage is previously provided with an offset such that the second error amplifier AMPb should not influence the output transistor M101 when no steep reduction in the output voltage occurs. That is, a change in the output value cannot be detected when the change in the voltage is less than the offset voltage of the second error amplifier AMPb. In a common error amplifier, a random offset voltage occurring during a manufacturing process is on the order of ±15 mV. As a result, in consideration of a margin to the random offset, the offset voltage of the second error amplifier AMPb should be set on the order of 20 mV. When the random offset occurring during the manufacturing process is +15 mV for example, it is added to the previously set offset voltage and thus, the total offset amounts to 35 mV.
Further, variations in electric characteristics occur in the manufacturing processes in all devices included in the constant voltage circuit. As a result, the response characteristics may degrade twice accordingly. As a result, even if the second error amplifier AMPb has superior response, the second error amplifier AMPb may not respond until a voltage change in the output voltage amounts to 35 mV×2=70 mV, because of the above-mentioned variations in the manufacturing processes.
For example, assuming a logic circuit manufactured with a fine process not more than 90 nm, as a load of a constant voltage circuit for which high speed response is required, it is expected that the guaranteed operation voltage range may be 1 V±50 mV. In this case, it may be clearly seen that the response characteristics may not be sufficient in the second method. Further, although it is possible to correct the above-mentioned variations occurring in the manufacturing processes by means of trimming, a chip size may increase and also, a test process may increase as a result of a trimming device being disposed. Accordingly, the cost may increase.
In the above-mentioned third method, when the power source voltage lowers due to a steep increase in the load electric current, respective gate voltages of the two NMOS transistors having different threshold voltages are lowered via the capacitor, and the transistor having the large threshold is turned off. As a result, a drain voltage of the transistor increases. Response is improved as a result of an operation electric current being increased in response to the increase in the drain voltage. However, the operation electric current increases after the change level in the power source voltage reaches the voltage difference of the threshold voltage. Accordingly, the problem same as that in the second method may be involved.