The present embodiments relate to domino logic technology, and are more particularly directed to dynamic multiplexer circuits, systems, and methods having three signal inversions from input to output.
In many modern circuit applications, it is often desirable to increase the speed of operation of the circuit application. For example, in microprocessor design the circuits which make up speed-limiting portions or affect the speed of the microprocessor are constantly scrutinized and re-designed to increase the overall microprocessor speed. Increased speed increases performance and, therefore, permits more detailed and sophisticated processing capabilities in a shorter amount of time.
To increase the speed of microprocessors, as well as other circuits where speed is important, dynamic or so-called "domino" logic transistor circuits are currently used because they often provide increased speed as compared to static logic transistor circuits. A domino logic circuit is characterized by operating in two phases. First, a precharge node is set to a first potential during a precharge phase. Second, during an evaluate phase, if the logic condition represented by the circuit is satisfied, the precharge node is discharged, thereby changing the logic output of the circuit. In other words, at the conclusion of the precharge phase, the precharge node causes a first logic state to be output by the domino logic circuit. Thereafter, if the precharge node is discharged during the evaluate phase, the output of the domino logic circuit represents a second logic state differing from the first logic state. Moreover, the act of discharging to change states, when accomplished using one or more n-channel transistors to gate the transition from precharge to discharge, represents a speed increase over the prior operation of static circuits which in one instance accomplished a transition with a network of n-channel transistors while in another instance accomplished the opposite transition with a network of p-channel transistors.
One specific example of domino logic transistor circuits is known in the prior art as a dynamic multiplexer. In some contexts, the dynamic multiplexer is sometimes also referred to as a cascode multiplexer or cascode multiplexer logic. In any event, as presented in detail below, operation of the dynamic multiplexer generally follows the principles set forth above as characteristic of domino logic circuits. Additionally the dynamic multiplexer performs a multiplexer function in that any one of multiple data inputs may be selected by asserting a select signal to an input corresponding to the data input. More specifically, the dynamic multiplexer connects each data input to a source of a respective transistor, and a given data input is selected by asserting a signal to the gate of one of the respective transistors. While this implementation provides the functionality set forth above, it is shown below that it includes various drawbacks. For example, as a data transition is connected to a domino logic input, and then selected to an output of the dynamic multiplexer, it incurs a total of four inversions along its path. These four inversions necessarily introduce several drawbacks. For example, naturally there are hardware requirements to construct the inverting circuitry. As another example, each inversion introduces delay to the circuit. As yet another example, there is a financial cost in building each inverter as well as the space required to form the inverter on the semiconductor device used to form the dynamic multiplexer. The inventor of the present embodiments has recognized these above considerations aid below sets forth various embodiments which reduce the above-described drawbacks and improve performance as compared to the prior art.