1. Field of the Invention
The present invention relates to the timing of digital signals on an integrated circuit. More particularly, the present invention is directed to a method and an apparatus for synchronizing a signal with respect to two independent clocks.
2. The Background Art
The use of clocking systems is well known in the field of integrated circuits. Clock signals are used in synchronous circuits to direct elements of the circuit when to transition from the "current state" to the "next state." For example, determining when a particular register should sample or store input data. A clock literally sets the pace of, and provides the unit of measure for, the various stages of computations and operations on a chip. A clock signal normally transitions between a low and a high state, denoted 0 and 1 respectively, at a speed determined by the cycle time of the particular clock. Typically, it is the clock signal transition, either rising (rising edge) from 0 to 1 or falling (falling edge) from 1 to 0, that is used to pace the chip operations. In some situations both the clock signal transition and it's complement (the rising and falling edges) are used. A common operation in the field of integrated circuits is measuring how long a given signal is active, e.g., in the 1 state, as measured by the number of cycles of the clock.
In many applications, there are multiple clock signals on the same chip. Often there is a direct relationship between the multiple clock signals. Examples include: two clocks operating at the same frequency but out of phase and one clock operating at a frequency that is an integer multiple of another. Where the mathematical relationship between the clocks is known, transforming a signal from one clock domain to the other is relatively straightforward. This is not so when two clocks signals are not correlated, or when the relationship between them is unknown.
It would be desirable (for example in the field of video displays) to have an efficient way of converting an input pulse signal of a variable length X cycles, in terms of a first clock, into a pulse output signal, X cycles long in terms of a second clock, where the two clocks are operating at different frequencies. That is, to efficiently synchronize the input pulse signal across the two independent clock domains.
FIG. 1 shows a first clock signal 1 and an input pulse signal 2, which is three clock cycles long. The second clock signal 3 is slower than the first, it operates at a lower frequency. Thus, the synchronized output signal 4 is stretched, compared to the input pulse signal, in order to also be three clock cycles long, as measured by the second clock. The timing of samples in FIG. 1 are based on the rising edges of the clock signals. The falling edges could just as well have been used. There is no attempt made to resolve the input pulse signal any finer than an integer clock cycle, at both the beginning and the end of the signal.
As shown in FIG. 2, it is possible to use a circuit such as circuit 100, made up primarily of latches, to synchronize an input pulse with a pulse output signal. The input pulse signal 2 is latched by latching mechanism 10 when the first clock signal is active. Latching mechanism 10 operates as a filter for the input pulse signal. This latched signal is an output signal 20, that is latched by latching mechanism 11, on the rising edge of the second clock and output as signal 21. There is a possibility that signal 21 may be metastable, that is in an indeterminate state between 0 and 1 because the latching mechanism 11 is perfectly balanced between making a decision to resolve a 0 or a 1. The possibility that signal 21 maybe metastable depends on how the rising edges of the asynchronous clocks happen to line up, and this alignment could be changing with each clock cycle. To ensure a stable signal, a third latching mechanism 12 is used. Latching mechanism 12 reads signal 21, on the rising edge of the second clock signal 3. The latched signal from latching mechanism 12 is then output as signal 22, both to latching mechanism 13 and to AND gate 14. The complement of the latched signal from latching mechanism 12 is output as signal 23 to latching mechanism 15. Latching mechanism 13 operates as an integrator, it reads signal 22 on the rising edge of the second clock signal 3 and outputs the complement of the latched signal as signal 25 to AND gate 14. Latching mechanism 15 reads signal 23 on the rising edge of the first clock signal 1 and outputs the complement of that signal as signal 24. When signal 24 is high, latching mechanism 10 is reset. Signal 4, coming out of AND gate 14, is the synchronized output signal.
One disadvantage of the circuit shown in FIG. 2 is that this implementation introduces a recovery time. Time is required between sequential input pulse signals because the circuit must be idle before another input pulse can be processed. The circuit in FIG. 2 would require resetting the latch mechanisms 10 and 13 to the "0" state. This corresponds to a minimum recovery time equal to 2 cycles of clock 1 plus 3 cycles of clock 2. It would be desirable to minimize or eliminate the recovery time for time critical or real time applications, so that another input pulse signal could be quickly processed. Introducing a delay between sequential input pulse signals solves the problem, but does so at the expense of speed. In addition, this solution requires different minimum delay times for different clock combinations.
Another related problem with the type of circuit shown in FIG. 2 is that the implementation requires a series of latches, latching the input pulse signal on both the clock signals, to avoid metastable or transitional states in the circuit components. This series of latches introduces delays. It is well known to those of ordinary skill in the art that such metastable states may lead to erroneous output results and that these states are not always easily detected by logic simulators and other conventional design techniques. It would be desirable to have a proven generic design for use in all signal synchronization situations, that avoids the use of devices having potential metastable states.