The advanced manufacturing process has progressed into nm-scale thanks to rapid development of IC technology. While the functions of System on Chip (SoC) chips become more and more powerful, high performance and low power consumption remain two main goals to be achieved. However, the two goals are paradoxical in that too low power consumption could greatly degrade the performance. The researches show that, circuits in the advanced process usually achieve the lowest power consumption in the sub-threshold region, and achieve the highest energy efficiency in the near-threshold region; and when the supply voltage decreases from the normal voltage region (or super-threshold region, STC) through the near-threshold region down to the sub-threshold region, the circuit delay continually increases and decreases exponentially in the near-threshold region and sub-threshold region, while the energy efficiency increases at first and then decreases, and optimal energy efficiency is achieved in the near-threshold region. To balance the energy efficiency and performance, much attention has been paid to the wide-voltage-range circuits, which generally cover a range from the near/sub-threshold region to the normal voltage region and can switch in this wide voltage range to meet high performance or high energy-efficiency requirements on chips under different loads.
However, some unsolved critical problems still exist in SoC circuits when operating at near-threshold and wide-voltage-range region: in the normal voltage region, owing to process, voltage, temperature (PVT) variations caused by continual shrinkage in process size, certain timing margin has to be reserved in the conventional VLSI design to accommodate the timing constraint in the worst-case scenario. In addition, in the near-threshold voltage region, the PVT variations have greater impact on the circuit delay, leading to a multiplied path delay variation in addition to performance degradation (generally, 1/10 of that at a normal voltage) caused by the decreasing voltage of a circuit. Therefore, in the near-threshold or wide-voltage-range operation design, more timing margin than that of a conventional design has to be reserved to cope with timing variation in the near-threshold region. However, such timing margin may lead to excessively conservative setting of the operating voltage or frequency of a circuit, and may even counteract the energy efficiency benefits brought about by the wide-voltage-range operating.
The online monitoring techniques can use an on-chip monitoring unit to monitor critical path timing and scale in real time the voltage and frequency of a chip, thus becoming a powerful approach to address the bottleneck in the wide voltage range design. The online timing monitoring techniques can be mainly categorized into two types: error detection and correction, and timing warning. A timing warning-type monitoring unit is preferred because it does not need an additional system-level recovery mechanism, and predicts potential timing condition of a circuit by manually adding additional delays to critical data paths, thereby achieving voltage and frequency adjustment in advance and preventing recovery overheads incurred by real faults.
During adjustment for ultra-wide voltage range applications, the conventional online monitoring unit cannot cover the variations since the variations have greater impact on delay distribution at a low voltage. Further, to deal with greater variations at a low voltage, a larger speculation window needs to be reserved on the monitoring unit, and thus more delay units are added in the conventional monitoring unit to ensure an adequate size of the speculation window, which leads to greater area and power overheads and reduces the benefits from the online timing monitoring techniques. As a result, it is necessary to design an online monitoring unit with smaller area and lower power consumption.