Cobalt-sheated lines prevent electromigration in the 10nm

Connecting billions of transistors using conventional copper interconnects is getting tougher in today's sub-22nm chips. The quality of the copper lines is yielding open circuits instead of voids as the number of metallisation layers goes up from 9 to 15 or more. While there are existing proposals to address this problem, California-based Applied Materials Inc. suggests a technique that encapsulates copper interconnect lines in cobalt, thereby nixing electromigration and extending copper interconnects to the 10nm node.

"Today, chips have more than a thousand interconnects within the width of a human hair," Kavita Shah, global product manager for Applied Materials' Endura Volta platform tells EE Times in an interview. "At higher nodes we had room for redundant lines, but at sub-22nm nodes there is no room for redundancy—and a single void can render a chip useless—lowering yields."

Through years of research Applied Materials has come up with a solution that it believes can extend copper interconnects to the 10nm node—namely, encapsulating the copper lines in cobalt. Today Applied Materials Endura platform is used to manufacture copper interconnects on chips by first performing a cleaning step to remove particles left over after etching, then using physical vapor deposition (PVD) to add a tantalum nitride/tantalum (TaN/T) barrier layer to prevent copper diffusion into the dielectric. Then it uses PVD to deposit a copper seed—a thin continuous layer of copper alloy—onto the TaN/T barrier. Finally the wafer goes to electroplating and polishing.

Figure 1: The new Endura Volta CVD Cobalt tool encapsulates copper features in cobalt to prevent voids and electromigration.