Increasing demands to reduce the geometry of semiconductor devices while at the same time increasing the number of devices on a semiconductor chip has resulted in significant changes in the manufacturing process of semiconductors. For example, as the size of the individual semiconductor elements on a chip decrease and the number of elements increases, the capacitance between conductive lines connecting elements has become a significant problem. To help reduce the problem, copper, copper alloys and other highly conductive metals are being used instead of aluminum. Unfortunately, use of these metals in semiconductor devices presents their own problems. For example, whereas in the past aluminum could be deposited, patterned by a photoresist and then etched to produce a desired conductive line structure, such processes are not suitable for copper and most other high conductive materials. Therefore, the damascene and/or dual damascene processes are often used to form the conductive lines. In addition, reduction of line to line capacitance with present day devices also requires dielectric materials with very low k or dielectric constants. For example, less than about 3.0. Unfortunately, these dielectrics and especially the low k dielectrics are very susceptible to the migration of copper ions from the copper conductive lines into the dielectric. This, of course is disastrous if the material is to be used as a dielectric.
To stop the ion migration, there have been various attempts to passivate the copper/dielectric material interface wherein such low Ic materials are used to fill between the copper lines. For example, certain conductivc metals and metal compounds such tantalum. tantalum nitride, titanium, titanium nitride, and tungsten do not themselves create major migration problems and can be used as a barrier between the copper and the dielectric to stop the copper ions from migrating. Of course, being a conductivc material, these barrier metals must be carefully deposited so that they cover only the copper and not the dielectric material. Otherwise the conductive metal could cause shorts between conductive lines or components that require cicetrical isolation from each other. Therefore, referring to FIG. 1 and FIG. 2A, it is seen that this prior art technique has been used where the barrier metal 10 selectively adheres to the exposed copper sidewalls 12 of the conductive lines 14a, 14b, and 14c while at the same time the treated top surface 16 of the conductive lines 14a, 14b, and 14c and the top surface 18 of the substrate 20 selectively avoid the deposition of the baffler metal 10. Of course, if the “selectivity” of the substrate and areas not intended to receive the barrier metal 10 fails and the metal is unintentionally deposited in these areas, electric shorts will be created.
Another prior art technique, as illustrated in FIG. 2B, includes the depositing of a blanket layer of a high k dielectric material 22 aver the copper lines 14a, 14b, and 14c and the top surface 18 of the substrate 20. The high k dielectric material is selected to be sufficiently dense to stop the ion migration, yet thin enough so as not to significantly raise the over all dielectric constant of the combination dense layer 22 of dielectric and the low k dielectric that will fill between the conductive lines 14a, 14b, and 14c to an unacceptable high value. This approach unfortunately has several problems. First, there is poor adhesion between the metal (such as copper) forming the conductive lines and the dense dielectric. Second, a sufficiently dense dielectric will still noticeably raise the dielectric constant of the combination of materials. In addition, the deposition process is typically a high temperature process that causes SM (Stress Migration) issues. Therefore1 a process that retains a low k value That can be carried out at a low or room temperature and still possess good adhesion to metal would be advantageous.