Power MOS devices, including laterally diffused metal-oxide-semiconductor (LDMOS) devices, are employed in a variety of applications, such as, for example, power amplifiers in wireless communications systems. In applications where high-frequency operation is desired, such as in a radio frequency (RF) range (e.g., above about 1 gigahertz (GHz)), a conventional LDMOS device may employ a field plate structure, often referred to as a “dummy gate,” adjacent to the traditional gate in order to reduce Miller capacitance between the gate and a drain region of the device, and to reduce hot-carrier injection (HCI) degradation in the device.
HCI degradation in an MOS device generally results from heating and subsequent injection of carriers into the gate oxide of the device, which results in a localized and nonuniform buildup of interface states and oxide charges near and underneath a gate of the device. This phenomenon can produce variations in certain characteristics of the MOS device, including threshold voltage, transconductance, drain current, etc., thus undesirably affecting the operation and reliability of the device. It is well known that HCI degradation is a strong function of the internal electric field distributions at the interface of the MOS device.
The effectiveness of the dummy gate, which may be measured by, for example, a reduction in Miller capacitance and/or HCI degradation associated with the LDMOS device, can be improved by reducing a thickness of the dielectric layer (gate dielectric) underneath the dummy gate. However, reducing the gate dielectric thickness increases the gate-to-source capacitance Cgs (i.e., input capacitance) of the device, thereby undesirably affecting the high-frequency performance. The increase in the input capacitance of the device resulting from the reduction in gate dielectric thickness often significantly undermines any beneficial reduction in the Miller capacitance provided by the dummy gate. Moreover, reducing the gate dielectric thickness undesirably reduces a breakdown voltage of the device.
In a conventional LDMOS device, which typically includes a lightly-doped drain (LDD) region, the LDD region is often formed at or near an upper surface interface between the silicon and oxide of the device. Locating the LDD region in close relative proximity to the silicon/oxide interface, however, significantly increases the likelihood that ionized carriers will become trapped at the interface, thereby increasing HCI degradation in the device.
In many applications, such as, for example, power applications, it is desirable to minimize the on-resistance, RON, associated with the MOS device. In an LDMOS device, since the on-resistance is dominated primarily by the characteristics of the LDD region, one known methodology for reducing the on-resistance is to increase the doping concentration of the LDD region. However, since the LDD region is typically formed at the silicon/oxide interface of the device, increasing the doping concentration of the LDD region also undesirably increases HCI degradation in the device.
Other attempts at reducing the on-resistance of the MOS device have included increasing the junction depth of the LDD region. However, since the gate-to-drain capacitance, Cgd, of the device is generally proportional to the junction depth of the LDD region, as the depth of the LDD region increases the gate-to-drain capacitance also increases, thereby undesirably affecting the high-frequency performance of the device. Thus, prior attempts to improve the high-frequency performance of the MOS device have primarily involved a trade-off among gate-to-drain capacitance, gate-to-source capacitance, on-resistance, breakdown voltage and HCI degradation in the device.
There exists a need, therefore, for an MOS device capable of improved high-frequency performance, that does not suffer from one or more of the problems exhibited by conventional MOS devices. Moreover, it would be desirable if the improved MOS device were compatible with existing integrated circuit (IC) fabrication process technologies.