1. Field of the Invention
The present invention relates, for example, to a semiconductor circuit used as a buffer circuit having the function of compensating for a power source fluctuation and used for the amplification of a clock signal in a dynamic memory device.
2. Description of the Prior Art
A conventional buffer circuit which amplifies an input clock signal .phi..sub.0 (conversion of impedance) and supplies an output clock signal .phi..sub.1 comprises MOS transistors Q1 through Q12 (Q9 is a MOS capacitor), as shown in FIG. 1. The input stage of the buffer circuit is a delay circuit comprising transistors Q1 through Q4. During a standby period, the delay circuit holds the voltage of the node N2, which connects the source of transistor Q3 with the drain of transistor Q4, at a high level. This is possible because of the input clock signal .phi..sub.0 and the inverted input clock signal .phi..sub.0. The clock signal .phi..sub.0 is at a high level during an active period and is at a low level during the standby period. The clock signal .phi..sub.0, because of the inverted polarity, is at a low level during the active period and is at a high level during the standby period. During the stand-by period these clock signals turn off the transistor Q1, turn on the transistors Q2 and Q3, hold the node N1 which connects the source of the transistor Q1 with the drain of the transistor Q2 and the gate of the transistor Q4, at a low level, turn off the transistor Q4, and charge the node N2 to the voltage of (Vcc-Vth) through the transistor Q3. Vcc is the voltage on the high voltage side of the power source and is usually 5 volts, which is the standard value, allowing for an error of .+-.10%. Vth is a threshold value of the transistor. Since the gate of the transistor Q5 is connected to the power source Vcc, when the node N2 is charged to (Vcc-Vth) the node N3 is charged to the same voltage. The node N3, which connects the transistor Q5 with the gate of transistor Q6, is the gate terminal of the transistor Q6 in the bootstrap circuit including the transistors Q5, Q6 and Q7. By charging the node N3 to a high level during the standby period, the charged voltage of the node N3 drives, at a high speed, the output stage including the transistors Q8 through Q12 during the next active period. Since the clock signal .phi..sub.0 is at a high level during the standby period, the transistor Q7 turns on, the node N4, which connects the source of transistor Q6 with the drain of the transistor Q7, the MOS capacitor Q9, and the gate of transistor Q11, reaches a low level. In addition the transistors Q8 and Q11 turn off, the transistors Q10 and Q12 turn on, and the output clock signal .phi..sub.1 is at a low level which is equal to the low voltage side of the power source Vss (usually ground voltage).
At the start of the active period, the input clock signals .phi..sub.0 and .phi..sub.0 are inverted. In FIG. 2, waveforms are shown during the active period. This example shows a constant Vcc which is equal to 4.5 volts. Although, in this example, the voltage of the node N2 is equal to the voltage of the node N3 (4.5 volts-Vth) at the end of the standby period, when the clock signal .phi..sub.0 changes from Vcc to Vss and the clock signal .phi..sub.0 changes from Vss to Vcc, the voltage of the node N3 increases to more than (Vcc+Vth) and the voltage of the node N4 is charged to the voltage of .phi..sub.0, which is equal to Vcc, by means of the bootstrap effect. This bootstrap effect is due to the effects of the capacity between the gate and the drain of the transistor Q6 and between the gate and the source of the transistor Q6.
This results in the transistors Q8 and Q11 being turned on. At the same time, since the transistor Q1 turns on, the transistor Q2 turns off, and the node N1 is charged to a voltage of Vcc; then the transistor Q4 turns on and the voltage of the node N2 begins to decrease. Accordingly, the electric charges at the node N3 are attracted by the voltage of node N2 through the transistor Q5 and the voltage of the nodes N3 and N2 decreases to Vss. When the voltage of the node N2 decreases to (Vss+Vth), the transistors Q10 and Q12 turn off and the voltage of the node N5 increases to Vcc. At this time, since the voltage of the node N3 is Vss, the transistor Q6 turns off, the voltage of the node N4 is increased to more than (Vcc+Vth) through the capacitor Q9, and the output clock signal .phi..sub.1 increases to the maximum power source voltage level Vcc.
The above-mentioned operation is carried out when no fluctuation of the power source occurs. However, if fluctuation of the power source occurs during the standby period, as shown in FIG. 3, the output clock signal .phi..sub.1 is delayed, and delay of the output clock signal .phi..sub.1 signifies a problem. In FIG. 3 an example is shown in which the Vcc decreases from 5.5 volts (Vcc(U)) to 4.5 volts (Vcc(L)) during the standby period. The above-mentioned fluctuation occurs when the electrical constitution of the constant voltage power supply is simplified in order to reduce the cost of the device or when other devices connected to the same power source are operated. During the standby period, the voltage of the clock signal .phi..sub.0 is low, the voltage of the clock signal .phi..sub.0 is high and the voltage of Vcc is the upper limit Vcc(U), which is equal to 5.5 volts, causing both the nodes N2 and N3 to be charged to (5.5 volts-Vth). Further, if Vcc decreases to the lower limit Vcc(L) which is equal to 4.5 volts, during the standby period, the voltage of the nodes N2 and N3 (5.5 volts-Vth) does not change because there is no discharge path. The reason there is no discharge path is that the transistor Q4 is in the "off" state, and the gate of the transistor Q3 has a low voltage of 4.5 volts which is equal to .phi..sub.0 and Vcc. When the voltage of the nodes N2 and N3 is held, the clock signal .phi..sub.1 is delayed. In order to increase the clock signal .phi..sub.1, it is necessary that the transistors Q10 and Q12 be turned off; on the other hand, it takes time for the voltage of the node N2 to decrease to the low level (Vss+Vth) at which the transistors Q10 and Q12 are turned off because the initial voltage of the node N2 is (5.5 volts-Vth), that is, it is 1 volt higher than the voltage (4.5 volts-Vth) in FIG. 2. During the period of delay when the voltage is decreasing at the node N2, a delay in the clock signal .phi..sub.1 occurs. In FIG. 3 the waveforms indicated by the broken lines N2', N3', N5' and .phi.1' show the passages of the voltage changes at the nodes N2, N3 and N5 and the voltage of the clock signal .phi..sub.1 without a power source fluctuation, as compared with the solid lines N2, N3, N5 and .phi..sub.1 which show the passages of the voltage changes at the nodes N2, N3 and N5 when fluctuation occurs in the power supply.
The prior art regarding the above-mentioned method is disclosed in U.S. Pat. No. 4,061,933.
The present invention is proposed in order to minimize the above-mentioned problems.