Field Effect Transistors ("FETs") continue to be the devices of choice in the fabrication of high density integrated circuits. In particular, manufacturers have scaled down FET circuit features to the sub-quarter micron level to achieve the high densities required for gigabit Dynamic Random Access Memories (DRAMs). The reduction of device dimensions results in a number of short-channel effects. One short-channel effect that poses a primary obstacle to further reductions in scale is the "hot-carrier effect."
In an N-channel FET, the hot-carrier effect occurs when the voltage applied between the drain and source regions of the transistor increases to a level at which the high lateral electric field in the transistor channel induces impact ionization. During impact ionization, some electrons are accelerated from the source region to the drain region and collide with the silicon crystal lattice with sufficient kinetic energy to break chemical bonds in the lattice within the channel region of the transistor.
As a result, free hole-electron carrier pairs are generated. The free holes are attracted to the negatively-biased substrate, resulting in a substantial increase in substrate current. At the same time, the free electrons are attracted to the positively-biased transistor gate. Although most of the free electrons completely traverse the gate dielectric layer, some become trapped within the dielectric layer. While the channel-to-substrate and channel-to-gate current increases power dissipation, the injection and trapping of electrons in the gate dielectric is far more serious because it causes the threshold voltage to increase and the current drivability to decrease.
During the operational life of the device, more and more electrons become trapped, resulting in a cumulative degradation of device performance. Over time, the threshold voltage and current drivability characteristics may be degraded to levels that render the circuit inoperable.
Although an analogous process takes place in P-channel devices, it is of less concern in practical applications. In a P-channel device, holes, instead of electrons, are injected into and become trapped within the gate dielectric. The energy that must be imparted to a hole to cause it to be injected into the gate dielectric is substantially greater than the energy required for electron injection. The lower hole mobility further reduces this effect. Far fewer carriers become trapped in a P-channel device, as compared to an N-channel device operating under similar conditions. As a result, the hot-carrier effect is not as critical for P-channel devices. Accordingly, the discussion below focuses on N-channel devices, with the implicit assumption that analogous principles apply to P-channel devices.
As channel lengths, along with other device dimensions, decrease, the supply voltage does not decrease proportionately. As a result, the lateral electric field in the channel is stronger for a given applied voltage. The stronger lateral field makes the hot-carrier effect more pronounced. Accordingly, integrated circuit designers strive to reduce the hot-carrier effect in sub-quarter micron scale devices, while not degrading current drivability.
In the past decade, designers have taken a number of approaches to mitigate the hot-carrier effect, including: (1) increasing the resistance of gate oxide at the silicon ("Si")-silicon dioxide ("SiO.sub.2 ") interface through improved methods of dielectric processing, see Mathews et al., U.S. Pat. No. 5,393,683 (U.S. Class 437/42), issued Feb. 28, 1995, entitled "METHOD OF MAKING SEMICONDUCTOR DEVICES HAVING TWO-LAYER GATE STRUCTURE"; (2) reducing the power supply voltage to reduce the magnitude of the lateral fields, an often difficult or impossible approach; (3) utilizing Lightly-Doped Drain ("LDD") FETs; and (4) utilizing other field-reducing device structures.
The most prevalent approach is to use standard LDD FETs. With this approach, the drain and source regions are doped with two different implants, one self-aligned to the gate electrode and the other self-aligned to a sidewall spacer, which permits the implant to be offset from the gate edge. Although this structure results in smaller lateral fields, it often leads to reduced drive currents. Disadvantages of conventional LDD FETs include: (1) increased series resistance between the drain and source regions resulting from the existence of a relatively large lightly-doped region adjacent to the channel; (2) spacer-induced degradation, resulting from the injection of carriers into the spacer at the spacer-substrate interface, which results in increased threshold voltage and reduced drive current. Designers have suggested several modifications of the conventional LDD structure to improve its electrical characteristics, with limited success. See, e.g., Ahmad et al., U.S. Pat. No. 5,405,791 (U.S. Class 437/34), issued Apr. 11, 1995, entitled "PROCESS FOR FABRICATING ULSI CMOS CIRCUITS USING A SINGLE POLYSILICON GATE LAYER AND DISPOSABLE SPACERS"; Ahmad et al., U.S. Pat. No. 5,382,533 (U.S. Class 437/24), issued Jan. 17, 1995, entitled "METHOD OF MANUFACTURING SMALL GEOMETRY MOS FIELD-EFFECT TRANSISTORS HAVING IMPROVED BARRIER LAYER TO HOT ELECTRON INJECTION"; Gonzalez, U.S. Pat. No. 5,376,566 (U.S. Class 437/35), issued Dec. 27, 1994, entitled "N-CHANNEL FIELD EFFECT TRANSISTOR HAVING AN OBLIQUE ARSENIC IMPLANT FOR LOWERED SERIES RESISTANCE".