A network processor is one example of what is more generally referred to herein as a link layer device, where the term “link layer” generally denotes a switching function layer. Such link layer devices can be used to implement packet-based protocols, such as Internet Protocol (IP) and Asynchronous Transfer Mode (ATM), and are also commonly known as Layer-3 (L3) devices in accordance with the well-known Open System Interconnect (OSI) model.
Communication between a physical layer device and a network processor or other type of link layer device may be implemented in accordance with an interface standard, such as the SPI-3 interface standard described in Implementation Agreement OIF-SPI3-01.0, “System Packet Interface Level 3 (SPI-3): OC-48 System Interface for Physical and Link Layer Devices,” Optical Internetworking Forum, 2001, which is incorporated by reference herein.
A given physical layer device may comprise a multiple-port device which communicates over multiple channels with the link layer device. Such communication channels, also commonly known as MPHYs, may be viewed as examples of what are more generally referred to herein as physical layer device ports. A given set of MPHYs that are coupled to a link layer device may comprise multiple ports associated with a single physical layer device, multiple ports each associated with one of a plurality of different physical layer devices, or combinations of such arrangements. As is well known, a link layer device may be advantageously configured to detect backpressure (BP) for a particular MPHY via polling of the corresponding MPHY address on its associated physical layer device. The detected backpressure is used by the link layer device to provide flow control and other traffic management functions, thereby improving link utilization.
U.S. patent application Ser. No. 10/689,090 filed Oct. 20, 2003 and entitled “Traffic Management Using In-band Flow Control and Multiple-rate Traffic Shaping,” discloses improved techniques for communicating information between a link layer device and a physical layer device, so as to facilitate backpressure detection and related traffic management functions, particularly in high channel count (HCC) packet-based applications.
In a conventional arrangement based on the SPI-3 interface standard, a link layer device issues an address identifying a particular MPHY for which backpressure status is desired, and the physical layer device responds with the backpressure status of that MPHY. The backpressure status may be communicated, by way of example, as an indicator of one of two states, such as assertion of backpressure and de-assertion of backpressure, with assertion of backpressure indicating that there is backpressure at the MPHY, and de-assertion of backpressure indicating that there is no backpressure at the MPHY. The response should be provided to the link layer device as quickly as possible so that the link layer device does not overflow or underflow the physical layer device buffer corresponding to the particular MPHY.
Since the link layer device generally needs backpressure status from each of the MPHYs of the physical layer device, it polls the addresses of the various MPHYs in accordance with an established polling sequence.
A typical conventional arrangement involves polling all of the MPHYs of the physical layer device in a fixed polling sequence based on a linear numerical ordering of the MPHYs. For example, the polling sequence for an arrangement in which there is a total of four MPHYs denoted MPHY0, MPHY1, MPHY2 and MPHY3 would be MPHY0, MPHY1, MPHY2, MPHY3, MPHY0, MPHY1, MPHY2, MPHY3, MPHY0, and so on. The polling sequence will continue in this fixed linear manner regardless of the particular transfers that may be occurring on the interface bus between the link layer device and the physical layer device.
A problem arises in this conventional fixed linear polling approach when there are a large number of MPHYs. For example, certain arrangements may have 16, 32, 64 or up to 256 or more MPHYs. As indicated above, the backpressure response for a given MPHY should be provided to the link layer device as quickly as possible to prevent overflow of the associated buffer in the physical layer device. However, when there are a large number of MPHYs, the polling sequence may take an excessive amount of time to cycle through the full range of MPHYs. As a result, the time between receipt of updated backpressure status for any given one of the MPHYs by the link layer device is limited by the cycle time of the full polling sequence.
Previous attempts to overcome this problem generally either increase the buffer size in order to accommodate the maximum polling delay, or configure the interface bus to incorporate additional pins that may be used to relay backpressure status for a designated MPHY outside of the polling sequence.
One example of the latter approach in accordance with the SPI-3 standard is to configure the interface bus to include a direct transmit packet available (DTPA) pin for each MPHY. The DTPA feature provides a direct response to each MPHY, using one pin per MPHY, outside of the fixed linear polling sequence.
Another example of the latter approach in accordance with the SPI-3 standard is to configure the interface bus to include a selected transmit packet available (STPA) pin for each physical layer device interface. The STPA pin provides an indication of instantaneous first-in first-out (FIFO) buffer depth for a selected MPHY, again outside of the fixed linear polling sequence.
Unfortunately, the approaches which involve increasing buffer sizes or adding DTPA or STPA pins as described above fail to provide an adequate solution to the polling delay problem in that such approaches unduly increase the size, complexity and cost of the devices, particularly in applications involving large numbers of MPHYs. For example, with reference to the additional DTPA or STPA pin approach, an application involving 256 MPHYs would require up to 256 additional pins on the interface bus.
Accordingly, what is needed is an improved polling technique that overcomes the polling delay problem associated with fixed linear polling of a large number of MPHYs, while also avoiding the need for increased buffer sizes or additional interface pins.