Semiconductors and integrated circuit chips have become ubiquitous within many products due to their continually decreasing cost and size. In the microelectronics industry, there is a continued desire to reduce the size of structural features of the microelectronic devices and/or to provide a greater amount of circuitry for a given chip size. Miniaturization in general allows for increased performance (e.g., more processing per clock cycle and less heat generated) at lower power levels and lower cost. However, further size reductions appear to be approaching the physical limit of trace lines and micro-devices that are embedded upon and within their semiconductor substrates.
Basically, a FET is a transistor having a source, a gate, and a drain. The action of the FET depends on the flow of carriers along a channel between the source and drain that runs past the gate. Current through the channel, which is between the source and drain, is controlled by the transverse electric field under the gate. The length of the gate determines how fast the FET switches, and can be about the same as the length of the channel (i.e., the distance between the source and drain).
As the critical dimensions of CMOS devices are being aggressively scaled, forming contacts on those small devices is becoming more and more difficult due to the tight overlay tolerance. Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.