Arrangements of transistors in ICs to act as storage locations for binary bits (memory cells) are very well known in the art, and several different arrangements are used for different purposes. It is well known, as well, that memory cells have been integrated in many different ways in many kinds of IC devices. One such device is known as a programmable logic array (PLA), wherein memory cells are used to store bit strings that configure the PLA, that is, that program the PLA to one of the many purposes to which it may be applied. By storing different words in different patterns of memory cells in a PLA, the PLA can be configured to operate in a variety of different ways. Many reference books are available with information on both memory cells and PLAs.
In a PLA the characteristics of the memory cells are quite important. For example, the characteristics of the memory cell structure influence the power requirement and time for power up. Further, in operation of a PLA the state of the memory cells is frequently read for a variety of reasons. The characteristics of the cell structure determine the stability of cells during read operations. If a cell is relatively unstable, it may be flipped to the alternate state during a read operation.
In addition to the above, it is often desirable to alter the pattern of memory words stored in the memory cells in the PLA, to change the configuration of the PLA. In this process it is also desirable to reset the memory structure, that is, to drive all memory cells to a "1" condition, or all to a "0" condition, and then to write new data to the cells. The energy required to flip a single cell is vastly multiplied at reset because there are a very large number of memory cells in a state-of-the-art PLA. Flipping all cells results in a large current requirement. Without special design considerations in the memory system, current designs have a requirement that relatively small groups of cells may be written simultaneously.
What is clearly needed is a new and robust memory cell design that is stable for read operations, and at the same time requires a relatively low energy to flip the cell during a write operation. Just such a cell structure and operation is described in enabling detail below.