The present invention relates to simultaneous bi-directional data transfer over data lines.
Data transmission and reception techniques enabling simultaneous bi-directional signal transmission and reception over a single data line have heretofore been known, for example, those described in JP-A-98052-1981 and JP-A-186033-1991. A simultaneous bi-directional data transfer technology involves transmitting and receiving data signals simultaneously over the same data line. In JP-A-98052-1981, the output of a transmitter in a transceiver at one station is connected via a resistor to the data line that carries the output signal to another station having a similar transceiver. In addition, the output signal from the transmitter passes through a resistor, is combined with a base voltage, and is input to a differential receiver as a reference voltage. The signal transmitted over the data line is input to a differential receiver. In this previous technique, the differential receiver filters out the output signal generated by the home station and reproduces the input signal received from the remote station.
In JP-A-186033-1991, after signals transmitted by two stations are combined by signal combining means, signal separation means separates the combined signal into an output signal of the home station and an input signal of the remote station. The home station filters out the output signal and allows the input signal from the remote station to be inputted and processed by the circuits in the home station.
FIG. 2 is a block diagram showing the structure of bi-directional data transceiver at each station configured according to conventional techniques. FIG. 3 is a timing chart of signals transmitted and received at an input point 40 (Line_L) of the circuitry shown in FIG. 2, at where the rising and falling edges of an input signal received from the remote station (remote device) coincide with the corresponding edges of an output signal of the home station (host device). FIG. 4 is a timing chart of the above signals in which delay control is exerted, so that the corresponding edges of input and output signals do not coincide. In FIG. 2, numerals 2a and 2b denote transmitters, numeral 2c denotes a data line, and numerals 2d and 2e denote differential receivers.
As used herein, the host device refers to a device including a circuit or component being discussed, and the remote device refers to a device that is transmitting an input signal to the host device. Generally, the description provided herein uses the device on the left side as the reference point. Accordingly, the device on the left side is generally referred to as either “host device” or “home station,” and the device on the right side is generally referred to as either “remote device” or “remote station.” However, these terms are used merely for illustrative purposes and should not be used to limit the scope of the invention.
The bi-directional data transceiver in FIG. 2 supplies a variable reference voltage to the differential receiver. That is, the reference voltage Vref_L is obtained by combining a constant voltage with the output signal of the transmitter. Therefore, the reference voltage is dependent on the output signal. A transceiver 50 includes a transmitter 2a and a differential receiver 2d. A transceiver 52 includes a transmitter 2b and a differential receiver 2e. A data line 2c couples the two transceivers 50 and 52.
In the transceiver 50, the transmitter 2a outputs send data Sdata2_L via a resistor Rtt_L to the data line 2c. In the transceiver 52, the transmitter 2b outputs send data Sdata2_R via a resistor Rtt_R to the data line 2c. The resistances of the resistors Rtt_L and Rtt_R are set equally at characteristic impedance Zo of the data line 2c. The send data Sdata2_L and Sdata2_R output by the transmitters 2a and 2b are combined on the data line into a signal having three states or voltage levels: H, H/2, L.
A voltage source Vbb in the transceiver 50 is set at potential that is one half the amplitude level of the output signal of the transmitter 2a, namely, H/2. When a “0” signal is output from the transmitter 2a, a reference voltage Vref_L that is input to the differential receiver 2d will be a quarter of the amplitude of the output signal from the transmitter 2a, namely, H/4. When a “1” signal is output, the reference voltage Vref_L will be three quarter, namely 3H/4. As a result, the differential receiver 2d compares the reference voltage Vref_L and the triple-valued voltage signal transmitted over the data line 2c, cancels only the output signal transmitted by the host device, and reproduces the input data received from the remote device, thereby obtaining the receive data Rdata2_L as the input data from the remote device. The transceiver 52 including the transmitter 2b and the differential receiver 2e at the remote device performs similar operations. The simultaneous bi-directional data transfer technology is also described in U.S. Pat. No. 5,499,269, which is incorporated by reference.
The transceivers 50 and 52 can implement bi-directional data handling operations without problem if the corresponding edges of the signals transmitted by both host and remote devices do not coincide at the input point 40 or 42. However, such a situation frequently occurs in data transfer operations as illustrated in FIG. 3 unless specific precautions are taken. The falling and rising edges of the signals with respect to Line_L and Line_R are marked with circles.
FIG. 3 illustrates the voltage signal waveforms of the send data Sdata2_L of the transmitter 2a and the send data Sdata2_R of the remote transmitter received respectively at the input points 40 and 42 of the differential receivers 2d and 2e. FIG. 3 also illustrates the receive data Rdata2_L and the Rdata2_R at the input points 40 and 42. In addition, dotted lines denote the reference voltages Vref_L and Vref_R. Assume that the Sdata2_R signal output from the transmitter 2b of the right-hand station or device 52 is delayed by time “t” as it travels over the data line 2c and arrives at the input point 40 of the differential receiver on the left-hand station (host device or home station) when the falling edge of the Sdata2_R signal coincides with the falling edge of the Sdata2_L signal output from the host device 50.
At this time, the fall time of the signal Sdata2_R from the transmitter 2b of the device 52 becomes slow when it has arrived at the input point 40 of the differential receiver 2d of the host device. This falling edge coincides with the falling edge of the signal Sdata2_L output from the host device 50. Consequently, the Sdata2_R signal level changes from H to L without transition to ½H level. On the other hand, the reference voltage Vref_L sharply changes from 3H/4 to H/4.
As a result, the differential receiver 2d has difficulty in comparing the reference voltage Vref_L and the triple-valued voltage signal transmitted over the data line 2c for a period (indicated by a shaded portion 54) because of the difference between the fall time of the reference signal and that of the signal transmitted over the data line. This causes a delay variation, e.g., a temporary signal processing error during when it is difficult to determine the state of the signal. The above phenomenon also occurs at the rising edges of the input and output signals.
Accordingly, the transceivers 50 and 52 use delay control mechanisms to prevent the corresponding edges of the signals from coinciding. The delay variation resulting from the edge coinciding occurs in the receive circuit because there is a difference between the fall or rise time of the reference voltage signal that is input to the differential receiver and that of the signal transmitted over the data line as described above. Rise or fall time of the input signal at the home station becomes slow as a result of the line resistance and parasitic capacitance of the data line and the input capacitance of the receiver. On the other hand, the reference voltage of the home station does not experience such a delay so it changes fast from H/4 to 3H/4 or 3H/4 to H/4. Thus, when these two signals with different fall or rise time are input to the differential receiver, the receiver cannot compare them properly due to the jitter in the falling and rising edges.
To avoid the above-described problem, a delay control mechanism is applied to prevent the corresponding edges of signals from coinciding. FIG. 4 shows a timing chart of the signals for which delay control is exerted. As shown in FIG. 4, if coincidence of the corresponding edges of input and output signals is avoided at the input point, a delay variation does not occur in the receive circuit. Thus, the above problem described can be solved. However, a new problem arises.
As shown in FIG. 4, the timing at which both stations transmit data differs by a half cycle from the timing shown in FIG. 3, and delay control is exerted to prevent the corresponding edges of input and output signals from coinciding. As a result, the clock timing to receive a signal from the remote device, for example, the rising timing of CLK to transmit in parallel (L−>R) shown in FIG. 4, coincides with the timing to transmit a signal from the host device. When the home station transmits a signal, multiple parallel signals rise or fall simultaneously (since home station has many transceivers), resulting in fluctuation of the current flowing across the line. This current fluctuation produces simultaneous switching output (SSO) noise.
In other words, if multiple signal bits change in synchronization with the timing of level change of the Sdata2_L and Sdata2_R, the SSO noise may be added to the signal-receiving clock signals. This noise contributes to the deterioration of the waveform quality of the clock signals. Therefore, the delay control mechanism that does not add the SSO noise to the clock signals is needed when the circuitry shown in FIG. 2 is used.