1. Field of the Invention
The present invention relates to flash memory, and more particularly to methods and apparatus for reading NAND flash memory.
2. Description of Related Art
NAND Flash memory has become increasingly popular due to its significant cost advantage. One measure of cost of Flash memory is memory cell area, wherein the memory cell area is commonly expressed in terms of F*2. The F, commonly called feature size, is usually the technology node. In other words, F is 58 nm for 58 nm technology node and F is 46 nm for 46 nm technology node. The NAND Flash memory cell size of 4F*2 is significantly smaller than other competing technologies such as NOR Flash memory, which has a cell size in the range of about 12F*2 through 15F*2.
Another segment of Flash memory with good growth has been the Serial Peripheral Interface (“SPI”) segment. One reason for the popularity of serial NOR Flash memory with SPI is low pin count (e.g. pins CS/, CLK, DI, DO for single-bit SPI). The availability of serial NOR Flash with SPI in small and inexpensive packages such as the 8-pin package enables significant board space savings. Moreover, the serial NOR Flash products with SPI have been designed on NOR Flash technology to accommodate applications requiring fast data fetch from random address. The NOR Flash inherently provides fast random read speed due to larger cell current. In contrast, NAND Flash has large initial latency and therefore NAND Flash is better suited for applications with sequential access of data, including but not limited to code shadowing. The slow random read speed of NAND Flash is due to very small cell current inherent in NAND Flash, due to multiple cells (e.g. 32 cells) connected in series in a NAND string.
As scaling of NOR Flash technology has slowed down, serial NAND Flash products with SPI have become available because of the memory cell area advantage. FIG. 1 illustrates a NAND memory array 19 and associated page buffer 10 in a single-plane architecture. The page buffer 10 has two registers, a data register (“DR”) 16 and a cache register (“CR”) 14. The use of the cache register 14 along with the data register 16 allows for cache operation, which achieves increased read thru-put in the following manner.
On the issuance of a page read (“PR”) command, Page-0 data is transferred from the specified page, shown as page 18, to the data register 16, typically in about 20 μs. While successive PR commands may be used to read sequential pages from memory, each page read incurs a 20 μs delay. These successive 20 μs delays may be masked by using the page read cache mode (“PRCM”) command. ON the issuance of a PRCM command after the PR command, the Page-0 data in the data register 16 is very quickly transferred to the cache register 14, typically in a maximum time of 3 μs, from which it is read out to a data bus 11. Issuance of the PRCM command also starts a transfer of Page-1 data from the next sequential page (not shown) to the data register 16, simultaneously with the output of the Page-0 data from the cache register 14. After Page-0 data has been read out from the cache register 14, another PRCM command may be issued. This second PRCM command transfers Page-1 data from the data register 16 to the cache register 14 in typically a maximum time of 3 μs, from which the Page-1 data is read out onto the data bus 11. The second PRCM command also transfers the Page-2 data from the next sequential page (not shown) to the data register 16, simultaneously with the output of the Page-1 data from the cache register 14. In this manner, sequential pages are read out by issuing multiple PRCM commands. Although gaps of up to 3 μs are present between data read from successive pages, throughput is nonetheless greatly improved by cache read operation.
Unfortunately, cache read operation conflicts with on-chip implementations of Error Correction Code (“ECC”). ECC is commonly used in NAND Flash because the inherent cycling (endurance) of NAND Flash is not as good as that of NOR Flash. ECC may be performed on-chip or externally by a host controller. External ECC by a host controller is quite effective for masking random single (or few) bit error(s) in the NAND Flash. The number of bits which can be corrected depends on the choice of ECC algorithm (e.g. Hamming, BCH, Reed-Solomon, or another appropriate ECC algorithm) used by the host controller. However, external ECC provided by a host controller is a burden on the host. Some recent NAND Flash devices include ECC on the NAND Flash chip itself, referred from herein as “on-chip ECC.” The on-chip ECC performs ECC computation and provides the correction of wrong bit(s). However, in those implementations of NAND Flash memory which use the cache register for the ECC computation, read-out of page data from the cache register cannot be done while ECC computations are in process. While such ECC NAND Flash memory devices may be read using the standard PR command, a long wait is incurred which includes the time to transfer page data to the page buffer and the time for ECC to be performed. While ECC computation time varies depending on the algorithm and implementation, a 20 μs computation time is not uncommon. In such a case, every PR command, even for sequential pages, incurs a wait time of about 40 μs, specifically 20 μs for page data transfer to the page buffer and 20 μs for the ECC computation, before page data can be read out. This delay is a significant penalty in read thru-put due to on-chip ECC.