1. Field of the Invention
The present invention relates to a method of co-simulating a digital circuit. Such a method may be used as part of the design and manufacturing process of integrated circuits, for example of VLSI type.
2. Description of the Related Art
Non-trivial digital hardware circuits are usually designed using a synthesis-based approach where the circuit is described in a Hardware Description Language (HDL) and then synthesised into hardware using a synthesis tool. VHDL (for example as disclosed in IEEE Computer Society, “IEEE Standard VHDL Language Reference Manual” New York. USA, March 1988. IEEE Std 1076-1987 and IEEE Computer Society, “IEEE Standard VHDL Language Reference Manual” New York, USA, June 1994. IEEE Std 1076-1993) and Verilog HDL (for example as disclosed in IEEE computer Society, “IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language.” New York, USA 1996. IEEE Std 1364-1995) are commonly used hardware description languages. However, as circuit complexity continues to increase, there is a trend to use higher-level hardware description languages, usually based on programming languages such as C (for example as disclosed in, Brian
W. Kernighan and Dennis M. Ritchie, “The C Programming Language. Prentice-Hall, USA, second edition, 1988”) and C++ (for example as disclosed in Bjarne Stroustrup, “The C++ programming language.” Addison-Wesley series in computer science, Addison-Wesley, Reading, Mass., USA) instead of register transfers.
Such languages allow the design of hardware in terms of algorithms. High-level synthesis tools (for example as disclosed in Daniel Gajski, Nikil Dutt, Allen Wu, and Steve Lin, “High-Level Synthesis, introduction to Chip and System Design.” Kluwer Academic Publishers, Boston/Dordrecht/London, 1992) are then used to generate lower level HDL descriptions from the given algorithm-level descriptions. Similarly to software design, the use of a high-level language usually results in shorter design times.
In some systems, the high-level HDL used is simply a well known programming language. For Instance System C (for example as disclosed in Synopsys Inc. “Overview of the Open System C initiative,” datasheet available on the internet from www.systemc.org,1999) uses C++ as a system description language. In other cases, a programming language with extensions relevant to hardware design is used. Examples of such systems include the Tangrarn system (as disclosed in K. van Berkel, J. Kessel, M. Roncken, R. Saeijs, and F. Schalij, “The VLSI-Programming Language Tangram and its Translation into Handshake Circuits”, Proceeding of the European Design Automation Conference (EDAC 91), pages 384–389, Amsterdam, February 1991, IEEE, IEEE Computer Society Press and Kees van Berkel, “Handshake Circuits”, volume 5 of Cambridge International Series on Parallel Computation, Cambridge University Press, Cambridge, UK, 1993) and the Bach system (as disclosed in Akihisa Yamada, Koichi Nishida, Ryoji Sakurai Andrew Kay, Toshio Nomura and Takashi Kambe, ““Hardware synthesis with the BACH system”” International Symposium on Circuits and Systems, 1999 and in GB 231724S).
The language used by the Bach hardware compiler extends the C language with (amongst other features) constructs for expressing explicit parallelism and synchronous communication. The Bach language is based on the Communicating Sequential Processes (CSP) model, which is disclosed in C. A. R. Hoare, “Communicating sequential processes.” Communications of the ACM, 21 (8): 666–677, August 1978 and C. A. R. Hoare, “Communicating Sequential Processes.” Prentice-Hall International, Englewood Cliffs (N.J.), USA, 1990, first edition published in 1985 by Prentice-Hall and which is a model of computation which supports concurrency. The Tangram language is also based on CSP.
Another important advantage of using a high-level HDL is faster simulation speeds due to the level of abstraction of the design description. Very fast simulation speeds can also be achieved by compilation based simulation (see for example L. T. Wang, N. E. Hoover, E. H. Porter, and J. J. Zasio. “SSIM: A software levelised compiled-code simulator”, Proceeding of the 24th Design Automation Conference, pages 2–8, IEEE, IEEE Computer Society Press, 1987) where the hardware description is compiled into an executable format rather than interpreted by the simulation engine. In the case of using a sequential programming language (such as C++) as a HDL, a hardware description can be compiled and simulated simply by using a standard compiler for the particular language. If the programming language used is extended with hardware design relevant features such as parallelism, then a hardware description can be converted into a sequential program before being compiled. For example, in the Tangram system, a hardware description can be converted into a C program as disclosed in Kees van Berkel, “Handshake Circuits,” volume 5 of Cambridge University Press, Cambridge, UK, 1993. Also, JP 1121939 describes a simple mechanism for converting CSP features into a sequential language.
In systems comprising of one or more components, every component may be described in a language chosen for its particular strengths and expressiveness. For example. a hardware description language is used for hardware components and a software programming language is used for software components. It is therefore very common that the components in a system are described in several languages. FIG. 4 of the accompanying drawings shows an example of such a system description. The complete system description comprises a plurality of component model descriptions which communicate with each other. The Bach C Language mentioned hereinbefore is used at 2 and 3 to provide descriptions of a demodulator component and an error correction decoder component. The VHDL language mentioned hereinbefore is used at 4 and 5 to describe a RAM (random access memory) component and a Fast Fourier Transform (FFT) component. The C Language is used at 6 to describe a test bench component.
Since the verification of such a system is an essential part of its design process, it is required that the verification, or simulation, is fast as a lot of simulation data may have to be processed. This simulation process is often referred to as co-simulation because of the heterogeneous nature of the system. The different system component models need to communicate with each other during co-simulation, and known methods, such as that disclosed in U.S. Pat. No. 5,335,191, can be used. One method for the co-simulation of a hardware component designed in a high-level HDL is to synthesise the hardware description into a lower-level HDL using a high-level synthesis tool or simulation engine 8 as illustrated in FIG. 2 of the accompanying drawings, and then co-simulate the low-level description using the hardware simulation tool. However, this method does not take advantage of the fact that a high-level description can be used for simulation, and has the following disadvantages:                (a) synthesis time overhead;        (b) slower simulation due to the use of a lower-level HDL;        (c) applicable only to synthesisable descriptions.        
Hardware simulators presently available allow the simulation of models described in different HDLS, as well as foreign models, that is, models described using means other than the HDLS understood by the simulator. For instance, the latest standard of VHDL (for example as disclosed in IEEE Computer Society, “IEEE Standard VHDL Language Reference Manual,” New York. USA, June 1994. IEEE Std 1076-1993) allows the specification of foreign entities. The Synopsys VSS simulator (as disclosed in Synopsys Inc. VSS Reference Manual. USA, 1998) provides a C Language Interface (CLI) (as disclosed in Synopsys Inc. VSS Interfaces Manual. USA. 1998) for the implementation of foreign entities using the C language. Similarly the Model Technology ModelSim simulator (as disclosed in Model Technology Inc. ModelSim SE/EE User's Manual. USA.1999) provides a Foreign Language Interface (FLI) for the same reason. The simulation engine described in David A. Burgoon. A mixed-language simulator for concurrent engineering. In The Proceedings for the 1998 International Verilog HDL Conference and VHDL International Users Forum, US, March 1998. IEEE Computer Society is also capable of co-simulating C models with lower level Verilog Models. These particular methods apply only when the high-level hardware is described in a sequential language such as C. Further, the C code must be written in a special stimulus-response fashion, which is not purely algorithmic.