1. Field
This disclosure relates generally encoding a clock with data to be transmitted.
2. Related Art
Many electronic systems send data with an associated bus clock signal such as bus in a microprocessor. These buses can be relatively long and includes data bit lines and a bus clock line, each having an inherent impedance and coupling to adjacent lines of the bus that affects the speed at which data and the bus clock are transmitted. These impedances can interact with data bit patterns transmitted on the data bit lines and thus the data and bus clock timing may become skewed by the time they reach the processor. Particularly with very high speed buses the skewing of the data relative to the bus clock can cause erroneous data latching and processing and thus such electronic systems compensate for skewing by selective insertion of discrete time delays inserted into the data bit lines and bus clock line.
Variations in the length of the bus, ambient surroundings, and permutations of the data bit patterns may require a system to identify a maximum skew range and then selectively include discrete delays to compensate for the maximum skew. However, some compensation methods identify the maximum skew range by use of unnecessarily large numbers of data bit patterns and typically require all possible data bit pattern permutations. In addition, some compensation methods attempt to identify the maximum skew range with single static patterns that do not adequately identify the extremities of the skew range.