The continued scaling of semiconductor devices to ever smaller dimensions creates a number of manufacturing challenges. One process related to this trend involves the production of very thin semiconductor wafers used in integrated circuit (IC) fabrication. Some current approaches in the industry known to the inventors use “back-grinding” of semiconductor wafers to reduce their thickness. This practice involves the completion of the front (or “active”) side of a semiconductor wafer, followed by removal of excess substrate from the back side of the wafer.
During the back-grinding process, the wafer is placed on a chuck table and a grinding wheel grinds off the excess substrate. There are some systems that grind a wafer in an in-line fashion or sequential/serial, while others grind several wafers concurrently with several respective grinding wheels. Approaches known to the inventors for controlling the back-grinding process typically have involved measurement of related parameters, e.g., measuring the current used to drive the grinding wheel in combination with measuring the revolutions of the grinding wheel spindle. Such parameters reflect the friction between the wheel and wafer and are controlled to be within respective acceptable ranges. Other solutions have used a measured capacitance between the wafer and a capacitive plate above the wafer.