In order to reduce costs and time to market, current integrated circuit (IC) designs often incorporate several functionalities into a single chip. This is particularly true as IC fabrication technologies move towards ultra-deep sub-micron geometries, such as, for example, 40 nanometer (nm) or 28 nm. Such a design approach is typically referred to as a system on a chip (SoC).
In order to conserve power in a SoC design, it is important that different functional blocks in the SoC be capable of being independently turned off (i.e., powered down) when they are inactive. However, with smaller feature sizes (e.g., gate oxide thickness, gate channel width and length, etc.) in current technologies, there is a significant amount of leakage current (e.g., sub-threshold leakage current) even when a functional block is powered off. In order to overcome this leakage problem, power islands are often created that supply power to individual blocks, and the power supplied to an inactive block can be selectively turned off without interfering with the overall SoC operation. This approach, however, increases layout routing congestion and design complexity, among other disadvantages.
Conventionally, when the core power supply is turned off, an input/output (I/O) buffer circuit (typically used in a SoC design for performing interfacing functions) can be forced into a limited subset of operational modes; typically, tri-state mode, weak pull-up mode, or weak pull-down mode. This can be achieved, for example, with a core power detection circuit in conjunction with a plurality of I/O level control signals. However, a full set of modes that an I/O buffer may offer during normal operation is not realizable when the core power supply to the buffer circuit is removed (i.e., turned off or otherwise disconnected).
In order to maintain proper operation of a SoC even when one or more functional blocks are powered off, it is important that I/O buffers in the powered-off blocks be able to provide a full set of functional modes as are available when power is supplied to the buffer during a normal operation thereof. One known approach to achieve this objective is to provide an I/O level signal for each core level signal. Given the number and complexity of current I/O buffers employed in a given SoC design, however, it is simply impractical to provide as many I/O level signals as there are core level signals. This approach also increases design complexity, layout routing congestion, and characterization, verification and functional model complexities, and is therefore undesirable.