An erasable programmable logic device (EPLD), such as EPROM, EEPROM, a widely used semiconductor device, is capable to preserve digital information without supply of electric power and to erase the digital information in some ways. Commonly, the EPLD cell preserves digital information by biasing its control gate to drive electrons penetrating through a tunnel oxide layer into its floating gate. After the release of bias, the electrons would lack enough energy to escape form the energy barrier of oxide layer surrounded the floating gate thereby allowing the EPLD cell to preserve information. As for erasing the information, the electrons trapped in the floating gate could be evacuated form it by exposing the EPLD cell in an environment with a specific dose of ultraviolet or inputting extra voltages to specific electrodes of the EPLD cell. Since the EPLD cell has the feature of repeatedly recording information in a state out of supply of electric power, it is employed in many integrated circuits nowadays.
Referring to FIG. 1, an EPLD cell 100 includes a semiconductor substrate 102, in which a first device region 103 and second device region 101 are defined by isolation regions 104. A tunnel buried layer 108 with N-type dopant is formed under the surface of first device region 103. Similarly, a control gate 106 is formed under the surface of second device region 101 by implanting N-type dopant. Upon the control gate 106, a second oxide layer 116 is formed thereon. In addition, a first oxide layer 112 is formed upon the tunnel buried layer 108. The central region of first oxide layer 112 has a thickness thinner than that of the peripheral region of first oxide layer so as to serve as a tunnel oxide layer 114 for allowing the electrons of the tunnel buried layer 108 to pass through it. A polysilicon layer 110 is stacked completely over the first oxide layer 112 and tunnel oxide layer 114, and partially on the second oxide layer 116, wherein the uncovered region of second oxide layer 116 is remained for receiving input voltages.
When the EPLD cell records information, the control gate 106 would be biased in a potential by inputting a voltage through its uncovered region. Since the control gate 106, second oxide layer 116, and floating gate 110 are stacked as a capacitance structure, the potential of the control gate 106 would be coupled to the floating gate 110 to drive electrons of the tunnel buried layer 108 ejecting through the tunnel oxide layer 114 into the floating gate 110, and then trapped therein. The trapped electrons would affect the threshold voltage of the EPLD cell 100, thereby achieving the purpose of preserving information. Contrarily, for erasing the information preserved in the EPLD cell 100, electrically connecting the control gate 106 to ground and the tunnel buried layer 108 to positive voltage, the electrons trapped in the floating gate 110 would be driven out so as to clear the preserved information.
An indicator to evaluate the efficiency of EPLD cell is determined by the speed of driving electrons into the floating gate 110. However, the speed depends on the coupling potential of floating gate, which is responsive to the potential of control gate 106, and the potential of control gate 106 is related to the overlapped area between the floating gate 110 and control gate 106. Therefore, the larger overlapped area between the floating gate 110 and control gate 106, the better efficiency of the EPLD cell 100. Unfortunately, increasing the overlapped area would expand the horizontal area of the cell, thereby degrading the integration of integrated circuit employing this cell.
In light of the foregoing, the present invention proposes a novel design of EPLD cell and is fabricating method in order to resolve the dilemma between the integration and cell efficiency.