This invention relates generally to automatic test pattern generators used to develop test patterns for integrated circuits and particularly relates to automatic test pattern generators developing test patterns for integrated circuits using field effect transistors.
Before integrated circuits are delivered to customers, they are tested to insure that they operate correctly. This testing is essential to the quality of the final project; generating the patterns of test signals for conducting the testing, however, remains a tedious and unrewarding task.
Techniques have been developed for automating the generation of test signal patterns for each integrated circuit designed. Automating this generation relieves the engineer from manually determining the patterns of logical ones and zeros to be applied to the input pins of the integrated circuit and to be read from the output pins of the integrated circuit in testing each node or element of the integrated circuit. Customers demand products that have been tested to as close to one hundred percent of the circuit nodes as possible and customers also want to know if a node is untestable. These automation techniques have been joined together into programs known as the D algorithm, Podem and FAN. See Kirkland, Tom and Mercer, M. Ray, "Algorithms For Automatic Test Pattern Generation," IEEE Design and Test of Computers, June 1988, pages 43-54.
These know programs generate patterns of test signals, also known as vectors, automatically by selecting a node between gates or transistors in the integrated circuit. The program then assigns a hypothetical stuck-at fault of a logical one or zero to that node. The logical state at the node then becomes sensitized back to the primary input or input pins of the integrated circuit to determine if there exists a set of input logic signals to cause the desired stuck-at fault logical state at the selected node. The logical state at the selected node also becomes propagated forward to the outputs to determine whether a set of logical states at the outputs reflect the stuck-at fault state of the internal node. If a test of the selected node logical state exists, the program stores that set of logical states to be applied to the inputs and to be read from the outputs and indicates the node to be testable.
In the case of the program being unable to find a set of logical input and output states that reflect the selected logical state at the node, the program indicates to the user that the node is untestable. Often, however, the program unsuccessfully seeks to locate a pattern of input and output signals from all the available binary combinations or search space to test the selected node and, after a certain time, the program stops without giving the user information on the reason for failing to determine a test signal pattern.
One problem with these previous programs is their inadequacy and inability to test integrated circuits using field effect transistors. This results because these programs recognize only a logical one state or a logical zero state and do not recognize any other value-strength of the network forming the node that can exist between field effect transistors. These different value-strength numbers for networks using field effect transistors result from the different sizes of the field effect transistors, and their capacitive and resistive characteristics. For example, a stuck-at fault of a logical one state at a selected node comprising field effect transistors can have several different value-strength numbers. Also, a stuck-at fault might change the value-strength of that node.
Another problem with the previous programs was their inability to generate test patterns for bidirectional gates in which a stuck-at fault can occur at either side of the gate at different times depending upon whether that side of the gate is the load or the source. Another problem with the prior program was their inability to generate dynamic test pattern signals that deal with clock phases and sequential logic. These dynamic test patterns verify that the logic functions operate as expected within time interval specified by clock frequencies.