1) Field
Embodiments of the present invention are in the field of Semiconductor Processing. More particularly, embodiments of the present invention pertain to a fabrication method for a semiconductor mask.
2) Description of Related Art
For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of logic and memory devices on a microprocessor, lending to the fabrication of products with increased complexity.
Scaling has not been without consequence, however. As the dimensions of the fundamental building blocks of microelectronic circuitry are reduced and as the sheer number of fundamental building blocks fabricated in a given region is increased, the constraints on the lithographic processes used to pattern these building blocks have become overwhelming. In particular, there may be a trade-off between the smallest dimension of a feature patterned in a semiconductor stack (the critical dimension) and the spacing between such features. FIGS. 1A-C illustrate cross-sectional views representing a conventional semiconductor lithographic process, in accordance with the prior art.
Referring to FIG. 1A, a photoresist layer 104 is provided above a semiconductor stack 102. A mask or reticle 106 is positioned above the photoresist layer 104. A lithographic process includes exposure of the photoresist layer 104 to light (hv) having a particular wavelength, as indicated by the arrows in FIG. 1A. Referring to FIG. 1B, the photoresist layer 104 is subsequently developed to provide the patterned photoresist layer 108 above the semiconductor stack 102. The portions of the photoresist layer 104 that were exposed to light are now removed. The width of each feature of the patterned photoresist layer 108 is depicted by the width ‘x.’ The spacing between each feature is depicted by the spacing ‘y.’ Typically, the limit for a particular lithographic process is to provide features having a critical dimension equal to the spacing between the features, i.e. x=y, as depicted in FIG. 1B.
Referring to FIG. 1C, the critical dimension (i.e. the width ‘x’) of a feature may be reduced to form the patterned photoresist layer 110 above the semiconductor stack 102. The critical dimension may be shrunk by over-exposing the photoresist layer 104 during the lithographic step depicted in FIG. 1A or by subsequently trimming the patterned photoresist layer 108 from FIG. 1B. This reduction in critical dimension comes at the expense of an increased spacing between features, as depicted by spacing ‘y’ in FIG. 1C. There may be a trade-off between the smallest achievable dimension of each of the features from the patterned photoresist layer 110 and the spacing between each feature.
A method to triple the frequency of a semiconductor lithographic process is described herein.