1. Field of Invention
The present invention relates to a memory circuit. More particularly, the present invention relates to a memory control chip, control method and control circuit.
2. Description of Related Art
Most personal computer (PC) systems include a host board, an interface card and some peripheral devices. The host computer board is central to the operation of the computer system. Except for a central processing unit (CPU), memory control chip and slots for accommodating interface cards, the host computer board also has a plurality of memory module slots for inserting memory modules. According to system requirements, different types of memory modules may be inserted to the host board.
The most frequently used memories inside a personal computer includes synchronous dynamic random access memory (SDRAM) and double data rate dynamic random access memory (DDR SDRAM). In SDRAM, data access is triggered through the rising edge or the falling edge of a clocking signal. On the other hand, data access in DDR SDRAM is triggered through both the rising edge and the falling edge of the system clock so that DDR SDRAM has a data access rate doubles that of the SDRAM for the same clocking frequency.
At present, DDR SDRAM memory modules use memory module slots that adhere to the 184-lead CDEC standard. The number of data signaling leads provided by the standard is 64-bit wide and hence matches the 64-bit wide bus in the memory control chip. Therefore, each memory module can be defined as a memory bank and a batch of data 64-bit wide can be accessed at a time. To increase memory address space and reserve space for future expansion, a host board typically has an unequal number of memory module slots for plugging memory modules. Furthermore, memory modules plugged into different memory module slots often indicate memory modules belonging to a different memory bank.
FIG. 1 is a schematic block diagram of a conventional memory control circuit. The circuit in FIG. 1 includes a memory control chip 110, a clock buffer 140, a first memory module 120 and a second memory module 130. The first memory module 120 and the second memory module 130 are plugged into two memory module slots, which belong to different memory banks (not shown), so that data within the memory modules 120 and 130 can be accessed through the memory control chip 110. In FIG. 1, the number of data signaling leads (DATA) in the memory control chip 110 as well as the number of data signaling leads SD1 and SD2 in the first memory module 120 and the second memory module 130 are also 64. Hence, the memory control chip 110 is able to use a 64-bit wide data bus 115 to access data within those memory modules 120 and 130. The clock generator lead (DCLK0) in the memory control chip 110 is connected to the clock input terminal (CKI) of the clock buffer 140 for boosting the driving capacity of the clocking signal. The clock output terminal (ck01) of clock buffer 140 outputs a clocking signal to drive both the first memory module 120 and the second memory module 130 (the clock buffer 140 outputs a clocking signal capable of driving at most 4 banks of memory modules). Hence, clocking signals are transmitted to the first memory module 120 and the second memory module 130 as reference clock signals during a data access operation. The clock buffer 140 also has a clock feedback output terminal (CK02) for transmitting clocking signals back to a clock feedback input terminal (DCLKI) in the memory control chip 110. The memory control chip 110 also has a phase lock circuit (not shown) for adjusting the clocking phase of the signal transmitted from the clock signal output terminal (DCLKO). The memory modules on the memory module slots have 64-bit wide data signaling leads. Hence, when the clock generator lead (DCLKO) in the memory control chip 110 issues a clocking signal together with an address for accessing any one of the memory modules, a 64-bit data variation will appear on the data bus 115. Such variation on the data bus 115 may lead to the production of prodigious quantity of noise signals from the data signal leads (DATA) of the memory control chip, the so-called simultaneous switch output (SSO) noise. To reduce the noise, a large number of power/ground leads is set up close to the data signal leads (DATA) of the memory control chip 110. These power/ground leads increase the number of charge/discharge path when voltages at the data signal leads (DATA) vary. Consequently, the noise is controlled within an acceptable range.
With recent breakthroughs in semiconductor design, computational capability of a central processing unit has multiple fold improvements. Thus, width of buses from the memory control chip of a personal computer must increase to match the speed of execution of the central processing unit.
FIG. 2 is a block diagram of a conventional memory control circuit with a 128-bit wide bandwidth. The 128-bit wide data bus 155 receives signals from the memory module 162 and the memory module 164 with each memory module providing 64-bit of data signals. A host board having this type of circuit architecture requires an even number of memory modules. The circuit includes a memory control chip 150, a clock buffer 180, a third memory module 162 and a fourth memory module 164. The third memory module 162 and the fourth memory module 164 belong to the same memory bank 160 but plugged into separate memory module slots (not shown). The data signal bus leads (DATA) in the memory control chip 150 is 128-bit wide. Similarly, the sum of the number of data signal leads SD1 in the third memory module 162 and the number of data signal leads SD2 in the fourth memory module 164 is 128. Hence, the memory control chip 150 may access the data in the memory module 162 and 164 within the memory bank 160 simultaneously through the 128-bit data bus 155. The clock generator lead (DCLKO) in the memory control chip 150 is connected to the clock input terminal (CKI) of the clock buffer 180 for increasing the driving power of the clocking signal. The clock buffer 180 also has a clock output terminal (CK01) for outputting clock signals that drive both the third memory module 162 and the fourth memory module 164. Hence, clocking signals can be transmitted to the third memory module 162 and the fourth memory module 164 to serve as reference clock signals during a data access operation. The clock feedback output terminal (CK02) of the clock buffer 180 also transmits a clocking signal to the clock feedback input terminal (DCLKI) of the memory control chip 150 for adjusting the clocking phase of the signal transmitted from the clock generator lead (DCLKO).
For the newer DDR SDRAM memory module having a 128-bit wide data bus, each data access operation may result in a maximum change of 128 data bits in the data bus 155. With so many bit line changes concurrently, noise created at the data signal leads (DATA) of the memory control chip 150 will be considerably more than the transition of just 64 data bits. Thus, to reduce the noise that results from accessing 128 bits of data, the number of power/ground terminals set up close to the data signal leads (DATA) must be increased. However, the memory control chip is often enclosed within a 37.5 mm by 37.5 mm package to reduce production cost. Due to a limitation in pin positions for this type of package, the number of power/ground leads is virtually fixed. Yet, without additional power/ground leads in the package, the noise problem is going to aggravate.