Optimization of Silicon Heterojunction Interface Passivation on p‐ and n‐Type Wafers Using Optical Emission Spectroscopy

To increase the efficiency in p‐type wafer‐based silicon heterojunction (SHJ) technology, one of the most crucial challenges is the achievement of excellent surface passivation. Herein, chemical passivation techniques known for n‐type technology are successfully applied on p‐type float–zone (FZ) wafers, and wafer surface passivation quality is correlated with parameters from plasma diagnostics, namely crystallization rate and electron temperature indices. It is shown that plasma ignition at higher powers than deposition powers enhances effective minority carrier lifetimes τeff fourfold for p‐ (0.6–2.1 ms) and sixfold for n‐type (0.6–3.2 ms) wafers while giving opportunity to process under lower electron temperature indices during the nucleation phase. A subsequent hydrogen plasma treatment has a further beneficial effect on chemical passivation, leading to high effective minority carrier lifetimes of 4.5 and 3.1 ms, and implies open‐circuit voltages, i‐VOC, of 735 and 720 mV for p‐ and n‐type wafers, respectively. In particular, cell precursors built on p‐type wafers demonstrate excellent surface passivation with τeff and i‐VOC (4.1 ms and 745 mV). Using these process optimizations, SHJ cells on both p‐ and n‐type wafers are fabricated with efficiencies exceeding 21%.


Introduction
With a demonstrated record efficiency of 26.7% on large area (79 cm 2 ), [1] silicon heterojunction (SHJ) solar cells are approaching the theoretical limit of 29.4% for single-junction silicon solar cells. [2] Up to now, SHJ technology has been mainly developed on n-type crystalline silicon (c-Si) wafers due to 1) higher carrier lifetimes, 2) less influence of light induced degradation (LID), and 3) independence of bulk passivation improvement processes (e.g., gettering, hydrogenation) when compared with p-type wafers. [3] Nevertheless, substantial progress has been achieved on p-type wafer-based solar cells recently: 26.1% efficiency with an interdigitated back contact structure featuring tunnel oxide-doped polycrystalline silicon contacts on floatzone (FZ), [4] and conventional both side contacted SHJ with efficiencies of 23.8% on FZ and 23.6% on Czochralski-grown (CZ) p-type Si wafers have been demonstrated. [5] In addition to lowering the efficiency gap between n-and p-type wafers, and also considering that p-type Si wafers are %8% cheaper than their n-type counterparts, [6] it can be anticipated that p-type Si wafers might play an important role in SHJ solar market in the near future. A recent cost of ownership calculation [3] reveals that p-type wafers must be within 0.4% absolute efficiency compared with n-type wafers to claim a market share in SHJ technology. Recently, Ga-doped p-type wafers have become industrially available. This type of wafers does not suffer from boron-oxygen-related light-induced degradation (BO-LID). These wafers are predicted to dominate the p-type CZ wafer production in the next decade. [7] One of the key points in this performance development of SHJ solar cells is excellent surface passivation of the c-Si surface by plasma-enhanced chemical vapor deposition (PECVD) grown thin films of intrinsic hydrogenated amorphous silicon, a-Si: H(i). It is well known that such a-Si:H films can significantly reduce recombination losses by passivating interface defects, yielding high open-circuit voltages (V OC ) of up to 750 mV. [8] It is crucial to control the plasma processing conditions in order to achieve such excellent passivation on c-Si surface, and it was established previously that polymerization of the silane (SiH 4 ) precursor gas [9][10][11] as well as epitaxial growth of Si thin films [12][13][14][15][16] have detrimental effects on passivation quality.

DOI: 10.1002/pssa.202100511
To increase the efficiency in p-type wafer-based silicon heterojunction (SHJ) technology, one of the most crucial challenges is the achievement of excellent surface passivation. Herein, chemical passivation techniques known for n-type technology are successfully applied on p-type float-zone (FZ) wafers, and wafer surface passivation quality is correlated with parameters from plasma diagnostics, namely crystallization rate and electron temperature indices. It is shown that plasma ignition at higher powers than deposition powers enhances effective minority carrier lifetimes τ eff fourfold for p-(0.6-2.1 ms) and sixfold for n-type (0.6-3.2 ms) wafers while giving opportunity to process under lower electron temperature indices during the nucleation phase. A subsequent hydrogen plasma treatment has a further beneficial effect on chemical passivation, leading to high effective minority carrier lifetimes of 4.5 and 3.1 ms, and implies open-circuit voltages, i-V OC , of 735 and 720 mV for p-and n-type wafers, respectively. In particular, cell precursors built on p-type wafers demonstrate excellent surface passivation with τ eff and i-V OC (4.1 ms and 745 mV). Using these process optimizations, SHJ cells on both p-and n-type wafers are fabricated with efficiencies exceeding 21%.
To avoid these effects and thereby enable excellent surface passivation, plasma conditions such as hydrogen dilution ratio, deposition pressure, applied power, residence time of molecules etc. have to be tuned to enhance SiH 3 radical formation in the plasma. In addition to these plasma processing conditions, in situ hydrogen plasma treatment (HPT), [17] postannealing, [18] and a multilayer approach [19][20][21] have been exploited to enhance the chemical passivation.
In situ plasma diagnostics are very useful to investigate the plasma medium and deposition mechanisms of thin films. In the photovoltaics (PV) community, optical emission spectroscopy (OES) has been intensively used to identify correlations between layer characteristics and optical emission lines, mostly aiming at detecting the phase transition from amorphous to nanocrystalline silicon growth. [22][23][24][25][26][27][28][29][30] Recently, research has been conducted to determine the relation between optical emission spectra and surface passivation for SHJ solar cells. The main research areas can be classified as: quantification of the silane depletion fraction (or crystallization rate index), [31][32][33] postdeposition HPT, [34,35] predeposition treatments (i.e., tuning the background environment of the chamber), [36,37] and the impact of plasma ignition [38] on passivation quality.
In this study, surface passivation of double-side-textured (DST) c-Si wafers (both p-and n-type) by a-Si:H(i) is correlated with parameters determined from OES, namely the electron temperature index (Si*/SiH*) and crystallization rate index (H α /SiH*). It is shown that: 1) Increasing deposition power increases the crystallization rate index while improving effective minority carrier lifetimes up to the structural phase transition region from amorphous to nanocrystalline silicon. Exceeding a crystallization rate index (CRI) of unity yields epitaxial growth, and surface passivation deteriorates. 2) Plasma ignition at higher powers relative to the applied deposition powers during growth of the film bulk enhances effective minority carrier lifetimes fourfold for p-and sixfold for n-type wafers while giving opportunity to process under lower electron temperature indices at the film incubation phase. 3) HPT is proven to be beneficial for both wafer doping types; however, postdeposition annealing eliminates the HPT enhancement achieved on p-type wafers. 4) An additional buffer layer grown under silane-rich plasma and stacked between wafer and a-Si:H (i) layer does not provide further passivation enhancement to either type of wafers.
By using these passivation enhancement schemes, power conversion efficiencies exceed 21% for SHJ solar cells processed on both p-and n-type wafers.

Experimental Section
a-Si:H(i) layers with a texture adjusted thickness of~9 nm were deposited onto double side textured (DST) p-and n-type FZ wafers with, apart from doping type, identical technical specifications: 4 00 in diameter, thickness of 260 AE 20 μm and specific wafer resistivity of 1-5 Ωcm (resulting in a slightly higher doping concentration for p-type wafers). Prior to depositions, the samples underwent standard RCA cleaning. [39] Afterward, the chemical oxide grown during RCA was etched off in hydrofluoric acid (HF, 1% in H 2 O) for 180 s. The samples were then loaded into the PECVD cluster tool, which was pumped down to a pressure of 10 À7 mbar within 2 min, avoiding regrowth of a native oxide layer. a-Si:H(i) depositions were performed in a radio frequency (RF) driven (13.56 MHz) capacitively coupled, open electrodes geometry (i.e., no plasma box) PECVD system. The base pressure in this chamber is lower than 10 À6 mbar.
The optical emission from the bulk of the silane/hydrogen plasma was diagnosed by an Ocean Optics USB2000þ optical emission spectrometer. The window port is located 2 mm below the upper electrode (showerhead), thus it directly faces the plasma bulk. SiH*, Si* and H α optical emission peaks were monitored over time. OES data were taken in sampling intervals of 300 ms. Electron temperature index (ETI) (Si*/SiH*), [37] which is an indicator of undesired 'higher silane-related reactive species' (HSRS or Si n H 2nþ1 ) contribution in a-Si:H(i) films, and crystallization rate index (CRI) (H α /SiH*), [28] which is an indicator for nanocrystalline growth of Si, were calculated using intensities of the aforementioned optical emission peaks (see Results and Discussion section for more details).
Thickness measurements were conducted using optical data obtained with a Sentech SE850 DUV variable angle spectroscopic ellipsometer (SE) on films deposited on flat Si wafers that were fit using a Tauc-Lorentz model. The enlargement area factor of the textured surface was taken as 1.7 for adjusting the film thickness on DST wafers. [40] A Sinton Consulting WTC-100 photoconductance decay lifetime tester in transient mode was used to measure effective minority carrier lifetimes (τ eff ) and implied open-circuit voltages (i-V OC ) of chemically passivated samples. [41] In the following, τ eff is reported at an injection level of 1 Â 10 15 cm À3 .
Typically, when aiming at a-Si:H(i) with high passivation quality, the process window for the hydrogen dilution ratio (R ¼ H 2 / SiH 4 ) is relatively narrow. Therefore, as a first step, optimum values for R need to be determined. For this purpose, R was varied from 0 to 5 at constant plasma ignition power (18 W) and deposition pressure (0.8 mbar), and the highest minority carrier lifetime for n-type wafers was obtained at R ¼ 4 (data not shown here). According to our preliminary tests, RF deposition power density was kept at a minimum stable plasma density value of 26.5 mW cm À2 . Substrate temperature and electrodes spacing were fixed at 180 C and 16.5 mm (650 mils), respectively. At deposition pressures higher than 1.5 mbar, the silane polymerization (i.e., formation of Si n H 2nþn ) regime was encountered and powder formation occurred. Thus, the highest deposition pressure was selected as 1.5 mbar. Three different plasma ignition powers are selected: 18, 50, and 75 W; and the a-Si:H(i) bulk was grown at a constant power of 18 W. Higher ignition powers were applied for 2 s. Deposition conditions for these bulk a-Si: H(i) films are listed in Table 1. To further enhance chemical passivation, in some samples, an additional a-Si:H(i) buffer layer was deposited prior to the bulk a-Si:H(i) film under a silane-rich plasma composed of 13 sccm SiH 4 and 7 sccm H 2 gas fluxes (R ¼ 0.54), at 0.8 mbar deposition pressure. The remaining process conditions for buffer layers are identical to the bulk deposition parameters (180 C, 18 W, 16.5 mm). While depositing a 1 nm buffer layer, a linear behavior in deposition rate was assumed for adjusting the deposition time. After depositing bulk a-Si:H(i) layer, a HPT process was conducted for some samples for 3 min under the following conditions: 30 W, 1.5 mbar, 25.4 mm (1000 mils) electrodes spacing, and 30 sccm hydrogen flow. Postdeposition annealing was conducted in the same deposition chamber and at the same deposition pressure and temperature for 10 min under 50 sccm hydrogen flow.
Thin doped silicon layers were processed in a different cluster tool. The details regarding the PECVD of doped layers can be found elsewhere. [42] The samples were stored under nitrogen atmosphere except the characterizations and transportation between laboratories. The air exposure duration for characterizations after the deposition of bulk a-Si:H(i) layers was about twenty minutes and the transportation of the samples to the second PECVD system was about ten minutes. The depositions of boron-doped a-Si:H(p), phosphine-doped nc-Si:H(n), transparent conductive oxide (TCO) layers, a full-area silver (Ag) rear electrode as well as screen printing of an Ag front grid were done according to a baseline process optimized for n-type Cz wafers whose details are reported elsewhere. [19] Manufactured front (for p-type wafers) and rear junction (for n-type wafers) structures are illustrated in Figure 1.
Prior to TCO sputtering, τ eff and i-V OC of the precursors were measured once more with a Sinton Consulting WTC-120 photoconductance decay lifetime tester. Results are reported at an injection level of 1 Â 10 15 cm À3 . Every 4 00 wafer contains six cells with a designated illumination area of 2 Â 2 cm 2 . SHJ solar cells' current-voltage ( j-V ) characteristics were determined with a dual source Wacom WXS-155S-L2 AAAþ solar simulator under standard conditions of AM1.5G and 25 C. Only results of the best-performing solar cells are reported in the main text. The statistical analyses with respect to j-V characteristics can be found in Figure S3, Supporting Information. Series resistances of solar cells were calculated from comparing dark and illuminated j-V curves, as described elsewhere. [43] 3

. Results and Discussion
The SiH 4 /H 2 plasma bulk is monitored by OES under several plasma processing conditions. The optical emission spectrum for the SiH 4 /H 2 glow discharge under fixed process conditions at a constant ignition and deposition power of 50 W and 1.5 mbar deposition pressure are shown in Figure 2. The peaks of interest in this study are Si*, SiH*, and H α , which are located at 286, 414, and 656 nm, respectively. [26] The electron temperature index is defined as the optical emission intensity ratio of Si* to SiH* peaks. A reduction of the Si*/ SiH* optical emission ratio indicates lower electron temperatures in the plasma. [44] A low electron temperature index is related to less (undesired) contribution of higher silane-related reactive species (HSRS) to a-Si:H(i) film growth and enhanced stability against photo induced degradation of a-Si:H(i) films. [10] Higher electron temperatures in the reaction chamber lead to HSRS formation in the plasma and thereby favors undesired Si n H 2n radical formation. Details of the SiH 4 /H 2 discharge chemical reaction mechanisms can be found elsewhere. [44][45][46] Lowering the HSRS contribution during film growth enhances the desired SiH 3 contribution, which improves c-Si surface p assivation through growth of a low-defect a-Si:H layer. [47] Thus, it is related to passivation properties of Si surfaces.

Effect of Applied RF Power on Plasma Properties, Chemical Passivation of Silicon Surfaces, and PV Characteristics
To investigate plasma conditions, the applied RF power is varied in three levels: namely 18, 50, and 75 W (corresponding power densities of 26.5, 73.6, and 110.4 mW cm À2 ). The influence of   deposition power on crystallinity rate and electron temperature indices are shown in Figure 3. It can clearly be seen from Figure 3a that the applied power has a significant effect on the CRI: as the power increases, the steady-state CRI increases too, and reaches unity for 75 W, which is reported as the transition regime from amorphous to nanocrystalline growth. [28] An opposite effect is observed for the ETI during the very first seconds of plasma ignition, cf. Figure 3b: the higher the power, the lower the ETI. On the other hand, powers higher than 18 W show a less power-dependent behavior of ETI. Note that, the OES data are taken in relatively short sampling intervals of 300 ms. Therefore, recorded data exhibit pronounced noise. In order to analyze the data and clarify the trends in both electron temperature (Si*/SiH*) and crystallinity rate (H α /SiH*) indices, the data are smoothed using the Savitzky-Golay Method with a window size of 10 points and second polynomial order. The corresponding raw data can be found in Figure S1, Supporting Information. As seen in Figure 3, for powers higher than 18 W, the plasma shows an instability for about ten seconds indicating that the steady-state electrical properties of the plasma and chemical kinetics equilibrium cannot be reached within this duration. To overcome this issue, higher pressures are reported to be beneficial during plasma ignition; [48] however, powder formation regime is encountered for pressures higher than 1.5 mbar.
In Figure 4, j-V characteristics of the solar cells manufactured at different deposition powers are shown. The effective minority carrier lifetimes are given in the insets of Figure 4: as deposited (red), annealed (yellow), and after completion of the cell precursors (green). Effective minority carrier lifetimes and implied open-circuit voltage data are also listed in Table 2. It can clearly be seen that for both doping types of wafers, annealing improves the surface passivation and the addition of doped nc and a-Si:H layers further enhances effective minority carrier lifetimes.
As reported in literature, increasing the deposition power (thus CRI) leads to an increase in effective minority carrier lifetimes up to the point where the phase transition region is encountered. [31][32][33] The same trend is observed here: as deposition power increases (up to 50 W), effective minority carrier  www.advancedsciencenews.com www.pss-a.com lifetime increases. As can be seen from Figure 3a, 75 W leads to CRI values slightly above unity, which is reported to mark the phase transition region. The passivation quality deteriorates drastically for this condition, which has been ascribed to epitaxial Si growth. [32] This phenomenon is illustrated only for SHJ solar cells built on n-type wafers in Figure 4b. When compared with minimum deposition power conditions attainable for the PECVD used here, the electron temperatures are higher for 50 and 75 W [ Figure 3b]. The effect of a higher ETI reflects itself in the j-V curve as a flatter slope at V OC indicating a higher series resistance particularly on p-type wafers, as seen in Figure 4a, and thus a lower FF as listed in Table 2.
It has been observed that the plasma diagnostics, more specifically the CRI and ETI, play a reciprocal role in a-Si:H(i) film growth and surface passivation. A higher CRI (up to 1) reached by increasing the deposition power results in higher effective minority carrier lifetime values. On the other hand, higher powers favor high ETI, and thereby an increase in the HSRS contribution to the film, which leads to a similar trend in series resistance and lowers FF of final devices. This trade-off becomes apparent from Table 2, in particular for SHJ solar cells built on p-type wafers. In order to reduce ETI while keeping and further improving the passivation quality level, high-power plasma ignition and low-power film deposition are required.

Effect of High-Power Plasma Ignition on Plasma Properties, Chemical Passivation of Silicon Surfaces, and PV Characteristics
To investigate the impact of plasma ignition at high powers, the plasma is ignited at two different powers, 50 and 75 W, for 2 s, and is afterward reduced to the deposition power of 18 W. As seen from Figure 5a, for the first seconds, the CRI shows a similar power-dependent behavior as the deposition power set shown in Figure 3. It is expected that the plasma ignition phase strongly affects film incubation, nucleation, and growth mechanisms; thus, interface properties and surface passivation. As can be seen from Figure 5b, the plasma instability observed above ( Figure 4) as a fluctuating ETI at the very first seconds of plasma discharge is overcome by igniting the plasma at high powers and immediately reducing it to the lowest deposition power possible with the PECVD used here, namely 18 W. Plasma ignition at higher powers for 2 s leads to stable ETI; however, it does not reduce the stabilized ETI further. Nevertheless, the observed values are amongst the lowest ETI reported, [9,36,38,44,46] which is essential for reducing HSRS contribution to film growth. [10] Therefore, the HSRS content in the deposited a-Si:H(i) films here is considered to be minimized in the reaction chamber. Raw data can be found in Figure S2, Supporting Information. Series resistance of Table 2. Influence of deposition power on passivation properties and J-V characteristics of SHJ cells manufactured on both p-and n-type FZ wafers. Note that the chemical passivation implies double side deposited symmetrical 9 nm-thick (i)a-Si:H only, cell precursor stack is: nc-Si:H(n)/ a-Si:H(i)/ c-Si(p or n)/ a-Si:H(i)/ a-Si:H(p). For S-shaped j-V curves, the procedure from ref. [43] used to calculate R s is not valid. In these cases, R s is denoted as n/a.  Figure 5. Impact of high-power plasma ignition on a) crystallinity rate and b) electron temperature indices versus plasma discharge time.
www.advancedsciencenews.com www.pss-a.com these cells are also lower when compared with deposition power set (Table 2), particularly for p-type wafers and plasma ignition at 75 W ( Table 3).
The influence of plasma ignition at different RF power levels on Si*, SiH*, and H α optical emission peaks is monitored over time as illustrated in Figure 6. This figure is divided into three regions. In the first region (left), the plasma is ignited at 18 W and the power is kept constant during film growth. Both the SiH* and Si* peaks reach a stable emission just after plasma ignition whereas the H α peak needs around 20 s to stabilize. Between the regions, where the optical emission intensities almost vanish, the applied RF power is shut off; thus, there is no plasma present and only the detector noise is visible. In the second region (middle), the plasma is ignited at 50 W and the applied RF power is reduced to deposition power (18 W) after two seconds. After the ignition phase, all three emission levels (Si*, SiH*, and H α ) recover to their stable values identical to the first cycle in about 30 s. Assuming a constant growth rate, this instability affects the deposition of the first 3 nm of a-Si: H (i) layer. As stated earlier, both ignition phase and subsequent transient behavior strongly affect film incubation, nucleation, and growth mechanisms (i.e., surface passivation). The same impact can also be seen in the third region (right) where the plasma is ignited at 75 W. Although both CRI and ETI follow a similar trend in all cases, the concentrations of radicals that take part in film formation increase drastically in the plasma ignition phase. This condition is considered to have a similar effect as increasing the total flow rate in the chamber, which leads to a decrease in residence times of silane polymers in the plasma and thus a reduction in HSRS contribution to film growth. [10] Plasma ignition at higher powers has a significant impact on the passivation quality, as seen from the minority carrier lifetimes of cell precursors and V OC s of finished cells in Figure 7 and Table 3. For 50 W plasma ignition power, effective minority carrier lifetimes after postdeposition annealing are boosted fourfold from 0.6 to 2.1 ms for p-type and sixfold from 0.6 to 3.2 ms for n-type wafers. Although the best passivation (i.e., highest lifetime) is reached for 50 W ignition power for p-type, the best device performance is obtained for a plasma ignition power of 75 W. The highest PCEs obtained under 75 W ignition condition are 21.1% and 21.7% on SHJ solar cells built on p-type and n-type wafers, respectively.
To increase the FF of final solar cells, the intrinsic a-Si:H layers are grown thinner (6 nm). As can be seen from Table 4, although the surface passivation quality is reduced drastically (for p from 2.1 to 0.6 ms and for n-type wafers from 3.2 to 0.8 ms), solar cells with thinner passivation layers perform better when compared with their 9 nm-thick counterparts. By comparing Table 3 and 4, it is shown that high PCE values achieved with 75 W plasma ignition and 9 nm thick layers can also be obtained with 50 W ignition and 6 nm-thick a-Si:H layers.

Effect of an Additional Buffer Layer and HPT Treatment on Chemical Passivation of Silicon Surfaces, and PV Characteristics
To further increase the quality of chemical passivation, i.e., minority charge carrier lifetime, on symmetrical a-Si:H(i)/ c-Si(p/n)/a-Si:H(i) samples, HPT and additional buffer layer approaches are taken into account. HPT had been optimized Table 3. Effect of high-power plasma ignition on passivation properties and PV characteristics of SHJ cells manufactured on both p-and n-type FZ wafers. Note that, the chemical passivation implies double side deposited symmetrical 9 nm thick a-Si:H(i) only, cell precursor stack is as follows: nc-Si:H(n)/ a-Si:H(i)/ c-Si(p or n)/ a-Si:H(i)/ a-Si:H(p), and the j-V characteristics given correspond to final device. For S-shaped j-V curves, the procedure from ref. [43] used to calculate R s is not valid. In these cases, R s is denoted as n/a.  www.advancedsciencenews.com www.pss-a.com and proven to be crucial for surface passivation for the utilized PECVD chamber. [17] It can be seen from Figure 8 and Table 5 that the HPT-related lifetime boost is about sixfold for p-type (from 0.7 to 4.5 ms) and threefold (from 1.0 to 3.1 ms) for n-type wafers before annealing. The highest effective minority carrier lifetime value on p-type wafers in this study is 4.5 ms. However, the behavior of passivated p-type wafers upon annealing is not anticipated: the effective minority carrier lifetime of Table 4. Effect of a thinner a-Si:H(i) layer (6 nm) on passivation properties and PV characteristics of SHJ cells manufactured on both p-and n-type FZ wafers. Note that, the cell precursor stack is as described in Table 3.   www.advancedsciencenews.com www.pss-a.com this sample is reduced to 1.4 ms; in other words, annealing eliminates the boost obtained by HPT. It is recovered after completion of the cell precursor; however, this phenomenon is not observed on n-type wafers. A thinner, less dense and more porous a-Si:H(i) buffer layer has been shown to enhance the passivation quality if a dense a-Si: H(i) layer is deposited onto this few nm thick buffer layers. [20,21,49,50] However, including a 1 nm-thick additional a-Si:H(i) buffer layer prior to the bulk a-Si:H(i) film alone does not yield any further gain in terms of chemical passivation. However, when combined with HPT, surface passivation of n-type wafer reaches its maximum effective minority carrier lifetime of 4.3 ms before annealing. The same annealing induced elimination of the HPT effect is also observed for the combination of buffer and HPT on p-type wafers. The effective minority carrier lifetime is halved, and then recovers after completion of the cell precursor. It appears that the HPT effect is not stable upon annealing in p-type wafers whereas in n-type wafers no such degradation is observed. This aspect is as yet not fully understood and might be related to H 2 effusion caused by Fermi energy-dependent Si-H bond rupture. [51] Nevertheless, it needs further investigation. Although an additional buffer layer combined with HPT lead to the highest charge carrier lifetimes in cell precursors, this treatment caused S-shaped j-V curves and reduced PCEs in completed devices.
It can clearly be seen from Table 5 that the best passivation quality is reached with HPT or a combination of HPT and buffer layer. However, this enhancement is not reflected in the PV characteristics where low FFs can be observed, despite high-opencircuit voltages. The cause for this loss is assumed to be excess hydrogen introduced by HPT and hydrogen migration toward a-Si:H/c-Si(p/n) interface due to subsequent annealing. It was shown that higher hydrogen concentration in a-Si:H leads to an increase in valence-band offset (ΔE v ), [52] which in turn promotes S-shaped j-V characteristics. [53]

Conclusions
In this study, enhanced surface passivation techniques on double-side-textured (DST) p-and n-type c-Si wafers are compared and correlated with parameters determined from optical emission spectroscopy (OES), namely the electron temperature index (ratio of Si*/SiH* emission lines) and crystallization rate index (H α /SiH* emission). It is shown that passivation methods used for n-type wafers can successfully be replicated on p-type wafers. It is concluded that: 1) increasing the deposition power up to a CRI of unity improves effective minority carrier lifetimes. After this point, an epitaxial growth regime is encountered, and the surface passivation deteriorates; 2) low and stable electron temperature indices are necessary for excellent chemical passivation and low HSRS contribution; 3) plasma ignition at higher powers relative to applied deposition powers enhance effective minority carrier lifetimes fourfold on p-(0.6-2.1 ms) and sixfold on n-type (0.6-3.2 ms) wafers while opening up the opportunity to process under lower electron temperature indices at the film incubation phase; 4) HPT after the deposition of the bulk a-Si:H(i) layer is proven to be beneficial for both types of wafers; however, postdeposition annealing eliminates the HPT enhancement on p-type wafers, which is recovered after the completion of cell precursors; 5) an additional silane-rich plasma growth buffer layer does not provide further enhancement on either type of wafer.
After depositing symmetrical a-Si:H (i) layers, the highest implied open-circuit voltages (i-V OC ) approached 730 mV for both type of wafers. The best cell precursors reached i-V OC s of 745 and 733 mV for 260 AE 20 μm-thick p-and n-type wafers, respectively. However, when processed into cells, p-type wafers show significantly lower FFs as compared with n-type counterparts. This problem must be overcome to make SHJ on p-type wafers a viable option for the PV industry. Applying the mentioned optimizations allowed to process cells on both p-and n-type wafers with power conversion efficiency (PCE) values exceeding 21%.

Supporting Information
Supporting Information is available from the Wiley Online Library or from the author. Table 5. Effect of buffer layer and HPT on passivation properties and PV characteristics of SHJ cells manufactured on both p-and n-type FZ wafers. For S-shaped j-V curves, the procedure from ref. 43 used to calculate R s is not valid. In these cases, R s is denoted as n/a.