from myelin_kicad_mod import *

X = Module(
	identifier="intel_ubga169",
	description="UBGA169 for Intel Max 10 FPGAs"
)

# Intel recommends 0.34mm NSMD pads for 0.8mm UBGA chips:
# https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an114.pdf

# plastic chip is 11 mm x 11 mm
D = E = 11.0

W = 13
H = 13

# 0.8mm ball spacing, 0.5mm ball dia, 0.4mm pad dia
BALL_SPACING = 0.8  # ball pitch.  ball dia is 0.5
PAD_DIA = 0.34  # diameter of copper pad
MASK_DIA = PAD_DIA + 0.03  # diameter of opening in solder mask
PAD_CLEARANCE = 0.127  # 5 mil pad clearance, to push it out past the NSMD ring

# top left ball
x0 = -(BALL_SPACING * (W - 1.0) / 2)
y0 = -(BALL_SPACING * (H - 1.0) / 2)

# draw outline
X.add(Line(-D/2, -E/2, -D/2, E/2))
X.add(Line(-D/2, E/2, D/2, E/2))
X.add(Line(D/2, E/2, D/2, -E/2))
X.add(Line(D/2, -E/2, -D/2, -E/2))

# draw pin 1 ID bubble
X.add(Circle(-D/2 + 0.5, -E/2 + 0.5, 0.25))

for y in range(H):
	for x in range(W):
		X.add(Pad(
			name="%s%d" % ("ABCDEFGHJKLMN"[y], x + 1),
			x=x0 + x * BALL_SPACING,
			y=y0 + y * BALL_SPACING,
			w=PAD_DIA,
			h=PAD_DIA,
			shape='circle',
			solder_mask_margin=(MASK_DIA - PAD_DIA) / 2,
			pad_clearance=PAD_CLEARANCE,
		))

X.save()

"""
10M08SCU169 pinout:

Bank Number	VREF	Pin Name/Function	Optional Function(s)	Configuration Function	Dedicated Tx/Rx Channel	Emulated LVDS Output Channel	IO Performance	U169
"""

description_lines = """
1A	VREFB1N0	IO			DIFFIO_RX_L1n	DIFFOUT_L1n	Low_Speed	D1
1A	VREFB1N0	IO			DIFFIO_RX_L1p	DIFFOUT_L1p	Low_Speed	C2
1A	VREFB1N0	IO			DIFFIO_RX_L3n	DIFFOUT_L3n	Low_Speed	E3
1A	VREFB1N0	IO			DIFFIO_RX_L3p	DIFFOUT_L3p	Low_Speed	E4
1A	VREFB1N0	IO			DIFFIO_RX_L5n	DIFFOUT_L5n	Low_Speed	C1
1A	VREFB1N0	IO			DIFFIO_RX_L5p	DIFFOUT_L5p	Low_Speed	B1
1A	VREFB1N0	IO			DIFFIO_RX_L7n	DIFFOUT_L7n	Low_Speed	F1
1A	VREFB1N0	IO			DIFFIO_RX_L7p	DIFFOUT_L7p	Low_Speed	E1
1B	VREFB1N0	IO		JTAGEN				E5
1B	VREFB1N0	IO		TMS	DIFFIO_RX_L11n	DIFFOUT_L11n	Low_Speed	G1
1B	VREFB1N0	IO	VREFB1N0					H1
1B	VREFB1N0	IO		TCK	DIFFIO_RX_L11p	DIFFOUT_L11p	Low_Speed	G2
1B	VREFB1N0	IO		TDI	DIFFIO_RX_L12n	DIFFOUT_L12n	Low_Speed	F5
1B	VREFB1N0	IO		TDO	DIFFIO_RX_L12p	DIFFOUT_L12p	Low_Speed	F6
1B	VREFB1N0	IO			DIFFIO_RX_L14n	DIFFOUT_L14n	Low_Speed	F4
1B	VREFB1N0	IO			DIFFIO_RX_L14p	DIFFOUT_L14p	Low_Speed	G4
1B	VREFB1N0	IO			DIFFIO_RX_L16n	DIFFOUT_L16n	Low_Speed	H2
1B	VREFB1N0	IO			DIFFIO_RX_L16p	DIFFOUT_L16p	Low_Speed	H3

2	VREFB2N0	IO	CLK0n		DIFFIO_RX_L18n	DIFFOUT_L18n	High_Speed	G5
2	VREFB2N0	IO			DIFFIO_RX_L19n	DIFFOUT_L19n	High_Speed	J1
2	VREFB2N0	IO	CLK0p		DIFFIO_RX_L18p	DIFFOUT_L18p	High_Speed	H6
2	VREFB2N0	IO			DIFFIO_RX_L19p	DIFFOUT_L19p	High_Speed	J2
2	VREFB2N0	IO	CLK1n		DIFFIO_RX_L20n	DIFFOUT_L20n	High_Speed	H5
2	VREFB2N0	IO			DIFFIO_RX_L21n	DIFFOUT_L21n	High_Speed	M1
2	VREFB2N0	IO	CLK1p		DIFFIO_RX_L20p	DIFFOUT_L20p	High_Speed	H4
2	VREFB2N0	IO			DIFFIO_RX_L21p	DIFFOUT_L21p	High_Speed	M2
2	VREFB2N0	IO	DPCLK0		DIFFIO_RX_L22n	DIFFOUT_L22n	High_Speed	N2
2	VREFB2N0	IO	VREFB2N0					L1
2	VREFB2N0	IO	DPCLK1		DIFFIO_RX_L22p	DIFFOUT_L22p	High_Speed	N3
2	VREFB2N0	IO						L2
2	VREFB2N0	IO	PLL_L_CLKOUTn		DIFFIO_RX_L27n	DIFFOUT_L27n	High_Speed	M3
2	VREFB2N0	IO			DIFFIO_RX_L28n	DIFFOUT_L28n	High_Speed	K1
2	VREFB2N0	IO	PLL_L_CLKOUTp		DIFFIO_RX_L27p	DIFFOUT_L27p	High_Speed	L3
2	VREFB2N0	IO			DIFFIO_RX_L28p	DIFFOUT_L28p	High_Speed	K2

3	VREFB3N0	IO			DIFFIO_TX_RX_B1n	DIFFOUT_B1n	High_Speed	L5
3	VREFB3N0	IO			DIFFIO_RX_B2n	DIFFOUT_B2n	High_Speed	M4
3	VREFB3N0	IO			DIFFIO_TX_RX_B1p	DIFFOUT_B1p	High_Speed	L4
3	VREFB3N0	IO			DIFFIO_RX_B2p	DIFFOUT_B2p	High_Speed	M5