title: CodeV-R1: Reasoning-Enhanced Verilog Generation
summary: Large language models (LLMs) trained via reinforcement learning with
  verifiable reward (RLVR) have achieved breakthroughs on tasks with explicit,
  automatable verification, such as software programming and mathematical
  problems. Extending RLVR to electronic design automation (EDA), especially
  automatically generating hardware description languages (HDLs) like Verilog
  from natural-language (NL) specifications, however, poses three key challenges:
  the lack of automated and accurate verification environments, the scarcity of
  high-quality NL-code pairs, and the prohibitive computation cost of RLVR. To
  this end, we introduce CodeV-R1, an RLVR framework for training Verilog
  generation LLMs. First, we develop a rule-based testbench generator that
  performs robust equivalence checking against golden references. Second, we
  propose a round-trip data synthesis method that pairs open-source Verilog
  snippets with LLM-generated NL descriptions, verifies code-NL-code consistency
  via the generated testbench, and filters out inequivalent examples to yield a
  high-quality dataset. Third, we employ a two-stage "distill-then-RL" training
  pipeline: distillation for the cold start of reasoning abilities, followed by
  adaptive DAPO, our novel RLVR algorithm that can reduce training cost by
  adaptively adjusting sampling rate. The resulting model, CodeV-R1-7B, achieves
  68.6% and 72.9% pass@1 on VerilogEval v2 and RTLLM v1.1, respectively,
  surpassing prior state-of-the-art by 12~20%, while matching or even exceeding
  the performance of 671B DeepSeek-R1. We will release our model, training
  pipeline, and dataset to facilitate research in EDA and LLM communities.
paper_authors._id: 683e9a174de2ca71b8bc915b
paper_authors.name: Yaoyu Zhu
paper_authors.status: claimed_verified
paper_authors.statusLastChangedAt: 2025-06-03T08:39:09.237Z
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paper_authors.fullname: Yaoyu Zhu
paper_authors.type: user
paper_authors.user: zhuyaoyu
paper_authors._id: 683e9a174de2ca71b8bc915c
paper_authors.name: Di Huang
paper_authors.status: claimed_verified
paper_authors.statusLastChangedAt: 2025-06-03T08:37:07.655Z
paper_authors._id: 62c581177b48ba0bb8cdb737
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paper_authors.fullname: di huang
paper_authors.type: user
paper_authors.user: dihuang
paper_authors._id: 683e9a174de2ca71b8bc915d
paper_authors.name: Hanqi Lyu
paper_authors._id: 683e9a174de2ca71b8bc915e
paper_authors.name: Xiaoyun Zhang
paper_authors._id: 683e9a174de2ca71b8bc915f
paper_authors.name: Chongxiao Li
paper_authors._id: 683e9a174de2ca71b8bc9160
paper_authors.name: Wenxuan Shi
paper_authors._id: 683e9a174de2ca71b8bc9161
paper_authors.name: Yutong Wu
paper_authors.status: claimed_verified
paper_authors.statusLastChangedAt: 2025-06-07T05:49:44.882Z
paper_authors._id: 64e42be971139393aa3dd90a
paper_authors.avatarUrl: https://cdn-avatars.huggingface.co/v1/production/uploads/64e42be971139393aa3dd90a/N7CwgOiU6rx5FTIfLO1Yo.png
paper_authors.fullname: Yutong Wu
paper_authors.type: user
paper_authors.user: wyt2000
paper_authors._id: 683e9a174de2ca71b8bc9162
paper_authors.name: Jianan Mu
paper_authors._id: 683e9a174de2ca71b8bc9163
paper_authors.name: Jinghua Wang
paper_authors._id: 683e9a174de2ca71b8bc9164
paper_authors.name: Yang Zhao
paper_authors._id: 683e9a174de2ca71b8bc9165
paper_authors.name: Pengwei Jin
paper_authors._id: 683e9a174de2ca71b8bc9166
paper_authors.name: Shuyao Cheng
paper_authors._id: 683e9a174de2ca71b8bc9167
paper_authors.name: Shengwen Liang
paper_authors._id: 683e9a174de2ca71b8bc9168
paper_authors.name: Xishan Zhang
paper_authors._id: 683e9a174de2ca71b8bc9169
paper_authors.name: Rui Zhang
paper_authors._id: 683e9a174de2ca71b8bc916a
paper_authors.name: Zidong Du
paper_authors._id: 683e9a174de2ca71b8bc916b
paper_authors.name: Qi Guo
paper_authors._id: 683e9a174de2ca71b8bc916c
paper_authors.name: Xing Hu
paper_authors._id: 683e9a174de2ca71b8bc916d
paper_authors.name: Yunji Chen
paper_title: CodeV-R1: Reasoning-Enhanced Verilog Generation
paper_summary: Large language models (LLMs) trained via reinforcement learning with
  verifiable reward (RLVR) have achieved breakthroughs on tasks with explicit,
  automatable verification, such as software programming and mathematical
  problems. Extending RLVR to electronic design automation (EDA), especially
  automatically generating hardware description languages (HDLs) like Verilog
  from natural-language (NL) specifications, however, poses three key challenges:
  the lack of automated and accurate verification environments, the scarcity of
  high-quality NL-code pairs, and the prohibitive computation cost of RLVR. To
  this end, we introduce CodeV-R1, an RLVR framework for training Verilog
  generation LLMs. First, we develop a rule-based testbench generator that
  performs robust equivalence checking against golden references. Second, we
  propose a round-trip data synthesis method that pairs open-source Verilog
  snippets with LLM-generated NL descriptions, verifies code-NL-code consistency
  via the generated testbench, and filters out inequivalent examples to yield a
  high-quality dataset. Third, we employ a two-stage "distill-then-RL" training
  pipeline: distillation for the cold start of reasoning abilities, followed by
  adaptive DAPO, our novel RLVR algorithm that can reduce training cost by
  adaptively adjusting sampling rate. The resulting model, CodeV-R1-7B, achieves
  68.6% and 72.9% pass@1 on VerilogEval v2 and RTLLM v1.1, respectively,
  surpassing prior state-of-the-art by 12~20%, while matching or even exceeding
  the performance of 671B DeepSeek-R1. We will release our model, training
  pipeline, and dataset to facilitate research in EDA and LLM communities.
paper_ai_summary: CodeV-R1, an RLVR framework for Verilog generation, achieves state-of-the-art performance in EDA using a rule-based testbench, round-trip data synthesis, and adaptive RLVR training.
paper_ai_keywords: reinforcement learning with verifiable reward RLVR electronic design automation EDA hardware description languages HDLs Verilog natural-language NL testbench generator equivalence checking round-trip data synthesis dataset two-stage training pipeline distillation adaptive DAPO VerilogEval RTLLM