title: ChiseLLM: Unleashing the Power of Reasoning LLMs for Chisel Agile
    Hardware Development
summary: The growing demand for Domain-Specific Architecture (DSA) has driven the
  development of Agile Hardware Development Methodology (AHDM). Hardware
  Construction Language (HCL) like Chisel offers high-level abstraction features,
  making it an ideal language for HCL-Based AHDM. While Large Language Models
  (LLMs) excel in code generation tasks, they still face challenges with Chisel
  generation, particularly regarding syntax correctness and design variability.
  Recent reasoning models have significantly enhanced code generation
  capabilities through test-time scaling techniques. However, we found that
  reasoning models without domain adaptation cannot bring substantial benefits to
  Chisel code generation tasks. This paper presents ChiseLLM, a solution
  comprising data processing and transformation, prompt-guided reasoning trace
  synthesis, and domain-adapted model training. We constructed high-quality
  datasets from public RTL code resources and guided the model to adopt
  structured thinking patterns through prompt enhancement methods. Experiments
  demonstrate that our ChiseLLM-7B and ChiseLLM-32B models improved syntax
  correctness by 18.85% and 26.32% respectively over base models, while
  increasing variability design ability by 47.58% compared to baseline reasoning
  models. Our datasets and models are publicly available, providing
  high-performance, cost-effective models for HCL-Based AHDM, and offering an
  effective baseline for future research. Github repository:
  https://github.com/observerw/ChiseLLM
paper_authors._id: 68103c25ac29b7d5a594a328
paper_authors.name: Bowei Wang
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paper_authors.fullname: Wang Bowei
paper_authors.type: user
paper_authors.user: observerw
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paper_authors.name: Jiaran Gao
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paper_authors.fullname: 高佳然
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paper_authors.user: gaojiaran
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paper_authors.name: Yelai Feng
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paper_authors.fullname: xiuranli
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paper_authors.user: xiuranli
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paper_authors.name: Renzhi Chen
paper_authors._id: 68103c25ac29b7d5a594a32c
paper_authors.name: Shanshan Li
paper_authors.status: admin_assigned
paper_authors.statusLastChangedAt: 2025-04-29T12:29:13.085Z
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paper_authors.fullname: shanshan Li
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paper_authors.user: shanshanLi
paper_authors._id: 68103c25ac29b7d5a594a32d
paper_authors.name: Lei Wang
paper_title: ChiseLLM: Unleashing the Power of Reasoning LLMs for Chisel Agile
    Hardware Development
paper_summary: The growing demand for Domain-Specific Architecture (DSA) has driven the
  development of Agile Hardware Development Methodology (AHDM). Hardware
  Construction Language (HCL) like Chisel offers high-level abstraction features,
  making it an ideal language for HCL-Based AHDM. While Large Language Models
  (LLMs) excel in code generation tasks, they still face challenges with Chisel
  generation, particularly regarding syntax correctness and design variability.
  Recent reasoning models have significantly enhanced code generation
  capabilities through test-time scaling techniques. However, we found that
  reasoning models without domain adaptation cannot bring substantial benefits to
  Chisel code generation tasks. This paper presents ChiseLLM, a solution
  comprising data processing and transformation, prompt-guided reasoning trace
  synthesis, and domain-adapted model training. We constructed high-quality
  datasets from public RTL code resources and guided the model to adopt
  structured thinking patterns through prompt enhancement methods. Experiments
  demonstrate that our ChiseLLM-7B and ChiseLLM-32B models improved syntax
  correctness by 18.85% and 26.32% respectively over base models, while
  increasing variability design ability by 47.58% compared to baseline reasoning
  models. Our datasets and models are publicly available, providing
  high-performance, cost-effective models for HCL-Based AHDM, and offering an
  effective baseline for future research. Github repository:
  https://github.com/observerw/ChiseLLM
paper_ai_summary: ChiseLLM, an enhanced domain-adapted reasoning model, improves Chisel code generation by enhancing syntax correctness and design variability in Hardware Construction Languages.
paper_ai_keywords: Domain-Specific Architecture (DSA) Agile Hardware Development Methodology (AHDM) Hardware Construction Language (HCL) Chisel Large Language Models (LLMs) domain adaptation reasoning trace synthesis RTL code structured thinking patterns