CodeV-R1: Reasoning-Enhanced Verilog Generation
Large language models (LLMs) trained via reinforcement learning with
verifiable reward (RLVR) have achieved breakthroughs on tasks with explicit,
automatable verification, such as software programming and mathematical
problems. Extending RLVR to electronic design automation (EDA), especially
automatically generating hardware description languages (HDLs) like Verilog
from natural-language (NL) specifications, however, poses three key challenges:
the lack of automated and accurate verification environments, the scarcity of
high-quality NL-code pairs, and the prohibitive computation cost of RLVR. To
this end, we introduce CodeV-R1, an RLVR framework for training Verilog
generation LLMs. First, we develop a rule-based testbench generator that
performs robust equivalence checking against golden references. Second, we
propose a round-trip data synthesis method that pairs open-source Verilog
snippets with LLM-generated NL descriptions, verifies code-NL-code consistency
via the generated testbench, and filters out inequivalent examples to yield a
high-quality dataset. Third, we employ a two-stage "distill-then-RL" training
pipeline: distillation for the cold start of reasoning abilities, followed by
adaptive DAPO, our novel RLVR algorithm that can reduce training cost by
adaptively adjusting sampling rate. The resulting model, CodeV-R1-7B, achieves
68.6% and 72.9% pass@1 on VerilogEval v2 and RTLLM v1.1, respectively,
surpassing prior state-of-the-art by 12~20%, while matching or even exceeding
the performance of 671B DeepSeek-R1. We will release our model, training
pipeline, and dataset to facilitate research in EDA and LLM communities.
683e9a174de2ca71b8bc915b
Yaoyu Zhu
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2025-06-03T08:39:09.237Z
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Yaoyu Zhu
user
zhuyaoyu
683e9a174de2ca71b8bc915c
Di Huang
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2025-06-03T08:37:07.655Z
62c581177b48ba0bb8cdb737
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di huang
user
dihuang
683e9a174de2ca71b8bc915d
Hanqi Lyu
683e9a174de2ca71b8bc915e
Xiaoyun Zhang
683e9a174de2ca71b8bc915f
Chongxiao Li
683e9a174de2ca71b8bc9160
Wenxuan Shi
683e9a174de2ca71b8bc9161
Yutong Wu
claimed_verified
2025-06-07T05:49:44.882Z
64e42be971139393aa3dd90a
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Yutong Wu
user
wyt2000
683e9a174de2ca71b8bc9162
Jianan Mu
683e9a174de2ca71b8bc9163
Jinghua Wang
683e9a174de2ca71b8bc9164
Yang Zhao
683e9a174de2ca71b8bc9165
Pengwei Jin
683e9a174de2ca71b8bc9166
Shuyao Cheng
683e9a174de2ca71b8bc9167
Shengwen Liang
683e9a174de2ca71b8bc9168
Xishan Zhang
683e9a174de2ca71b8bc9169
Rui Zhang
683e9a174de2ca71b8bc916a
Zidong Du
683e9a174de2ca71b8bc916b
Qi Guo
683e9a174de2ca71b8bc916c
Xing Hu
683e9a174de2ca71b8bc916d
Yunji Chen
CodeV-R1: Reasoning-Enhanced Verilog Generation
Large language models (LLMs) trained via reinforcement learning with
verifiable reward (RLVR) have achieved breakthroughs on tasks with explicit,
automatable verification, such as software programming and mathematical
problems. Extending RLVR to electronic design automation (EDA), especially
automatically generating hardware description languages (HDLs) like Verilog
from natural-language (NL) specifications, however, poses three key challenges:
the lack of automated and accurate verification environments, the scarcity of
high-quality NL-code pairs, and the prohibitive computation cost of RLVR. To
this end, we introduce CodeV-R1, an RLVR framework for training Verilog
generation LLMs. First, we develop a rule-based testbench generator that
performs robust equivalence checking against golden references. Second, we
propose a round-trip data synthesis method that pairs open-source Verilog
snippets with LLM-generated NL descriptions, verifies code-NL-code consistency
via the generated testbench, and filters out inequivalent examples to yield a
high-quality dataset. Third, we employ a two-stage "distill-then-RL" training
pipeline: distillation for the cold start of reasoning abilities, followed by
adaptive DAPO, our novel RLVR algorithm that can reduce training cost by
adaptively adjusting sampling rate. The resulting model, CodeV-R1-7B, achieves
68.6% and 72.9% pass@1 on VerilogEval v2 and RTLLM v1.1, respectively,
surpassing prior state-of-the-art by 12~20%, while matching or even exceeding
the performance of 671B DeepSeek-R1. We will release our model, training
pipeline, and dataset to facilitate research in EDA and LLM communities.
CodeV-R1, an RLVR framework for Verilog generation, achieves state-of-the-art performance in EDA using a rule-based testbench, round-trip data synthesis, and adaptive RLVR training.
reinforcement learning with verifiable reward RLVR electronic design automation EDA hardware description languages HDLs Verilog natural-language NL testbench generator equivalence checking round-trip data synthesis dataset two-stage training pipeline distillation adaptive DAPO VerilogEval RTLLM