A semiconductor memory device which includes an internal voltage generator circuit for adjusting an external power supply voltage and generating first and second internal power supply voltages. The first internal power supply voltage is supplied to a memory cell array via a first power supply line, and the second internal power supply voltage is supplied to a peripheral circuit via a second power supply line. A control circuit controls the internal voltage generator circuit so that the levels of the first and second internal power supply voltages vary depending on a mode of operation.
본 발명은 반도체 집적 회로 장치들에 관한 것으로, 좀 더 구체적으로는 메모리 셀들의 신뢰성을 테스트할 수 있는 반도체 메모리 장치에 관한 것이다. The present invention relates to a semiconductor integrated circuit device, more particularly to a semiconductor memory device to test the reliability of the memory cells.
스태틱 랜덤 액세스 메모리 (static random access memory: SRAM) 장치는 일반적인 다이내믹 랜덤 액세스 메모리 (dynamic random access memory: DRAM)와 비교하여 볼 때 보다 많은 금속-산화물-반도체 전계 효과 트랜지스터들 (metal oxide semiconductor field effect transistors)을 사용하며, 따라서 메모리 셀들을 리프레쉬할 필요없이 데이터를 저장할 수 있다. Static random access memory (static random access memory: SRAM) device is a general dynamic random access memory (dynamic random access memory: DRAM) and to many metal than when viewed compare-oxide-semiconductor field effect transistor (metal oxide semiconductor field effect transistors ) the use, and thus can store data without the need to refresh the memory cells. 하지만, SRAM 셀의 교차 접속 특성 (cross-coupled nature)은 제조 결함이 메모리 셀 내에 존재하게 하지만, 최초로 테스트될 때 메모리 셀이 필연적으로 정상 동작 범위 내에서 부적절하게 동작하게 하지 않는다. However, cross-connected characteristic (cross-coupled nature) of the SRAM cell will not be produced defective memory cell is inevitably improper operation in the normal operation range when the present, but the first test in a memory cell. 하지만, 이는 이후 메모리 셀이 비정상적으로 동작하게 한다. However, it should be after the memory cells are operated abnormally. 이러한 셀을 이후 잠재적인 결함 특성을 갖는 메모리 셀이라 칭한다. Since such a cell is referred to as a memory cell having a potential defect characteristics.
잠재적인 결함 특성을 갖는 메모리 셀은 스태틱 노이즈 마진 (static noise margin: SNM)을 조절함으로써 검출될 수 있다. Memory cell having a potential defect characteristic is the static noise margin: can be detected by adjusting the (static noise margin SNM). 여기서, 스태틱 노이즈 마진이란 데이터를 읽을 때 메모리 셀이 자신의 데이터를 유지하는 능력을 말한다. Wherein, when reading the static noise margin is the data refers to the ability of the memory cell maintains its own data. 잠재적인 결함 특성을 갖는 메모리 셀은 정상적인 특성을 갖는 메모리 셀보다 더 낮은 스태틱 노이즈 마진을 갖는다. Memory cell having a potential defect characteristics has a lower static noise margin than the memory cell having a normal characteristic. 다시말해서, 메모리 셀이 더 큰 스태틱 노이즈 마진을 가지면 가질수록 읽기 동작 동안 저장 상태들이 변화될 가능성은 더 적다. In other words, the potential of memory cell is further stored states are changed over large static noise margin have more has the read operation is less.
메모리 셀의 스태틱 노이즈 마진을 나쁘게 함으로써 잠재적인 결함 특성의 메모리 셀(들)을 보다 빠르게 찾아내는 것이 가능하다. It is possible to find more quickly the memory cell (s) of the potential defect characteristics by badly the static noise margin of the memory cell. 예를 들면, 메모리 셀에 인가되는 동작 전압을 주변 회로들 (예를 들면, 행 디코더, 열 디코더, 비트 라인 프리챠지 및 등화 회로, 등등)에 인가되는 동작 전압보다 낮게 설정함으로써, 메모리 셀의 스태틱 노이즈 마진이 나빠진다. For example, the peripheral circuit to the operating voltage applied to the memory cells by setting lower than the operating voltage applied to the (e. G., Row decoder, column decoder, the bit line precharge and equalizing circuit, and so on), a static memory cell the noise margin deteriorates. 그러므로, 보다 빠른 시간 내에 잠재적인 결함 특성을 갖는 메모리 셀(들)을 찾아낼 수 있다. Therefore, it is possible to find a memory cell (s) having the characteristics of potential defect in a faster time. 웨이퍼 레벨에서 잠재적인 결함 특성을 갖는 메모리 셀을 찾아냄으로써, 그러한 메모리 셀은 리던던시 셀로 대체되거나 그러한 메모리 셀을 포함하는 칩이 폐기될 것이다. By finding a memory cell having a potential defect characteristics at the wafer level, that memory cell is to be discarded, the chip, or to replace the redundancy cell comprising such memory cells.
앞서 설명된 기술은 일본공개특허번호 제11-185498호 (Japanese Laid-open Patent Publication No. 11-185498)와 일본공개특허번호 제06-349298호 (Japanese Laid-open Patent Publication No. 06-349298)에 각각 개시되어 있다. The above-described technique is Japanese Laid-Open Patent No. 11-185498 call (Japanese Laid-open Patent Publication No. 11-185498) and Japanese Laid-Open Patent No. 06-349298 call (Japanese Laid-open Patent Publication No. 06-349298) respectively disclosed in. 앞서 언급된 특허들은 테스트 동작시 주변 회로에 인가되는 동작 전압을 그대로 유지하는 반면에 메모리 셀에 인가되는 동작 전압을 낮추는 기술들을 포함한다. The aforementioned patent comprise techniques to lower the operating voltage being applied to the memory cell while keeping the operating voltage applied to the peripheral circuit during the test operation.
이 분야의 통상적인 지식을 습득한 자들에게 잘 알려진 바와 같이, 패키지된 메모리 장치는 가속 라이프 테스트 (accelerated life testing)의 일종으로서 번인 테스트를 받는다. As is well known to those who have acquired a conventional knowledge in the art, the packaged memory devices are subjected to burn-in test is a kind of accelerated life testing (accelerated life testing). 번인 테스트는 증가된 온도 및 동작 전압에서 메모리 장치를 전기적으로 동작시킴으로써 잠재적인 결함을 조기에 검출하여 제거할 수 있다. The burn-in test may be removed by detecting the potential defects early by electrically operating the memory device in an increased temperature and operating voltage. 패키지된 장치의 번인 테스트시 과도한 전류 소모로 인해 동작 전압이 낮아지게 된다.번인 테스트시 동작 전압이 낮아지면, 메모리 셀들에 대한 번인 테스트가 정상적으로 수행되지 못하거나 메모리 셀들에 대한 번인 효과가 떨어질 수 있다. When the burn-in test of the packaged device, due to the excessive current consumption becomes a low operating voltage. If the burn-in operation voltage is lowered during the test, it is not a burn-in test on the memory cells is performed normally or be less burn-in effect for the memory cells .
본 발명의 목적은 번인 테스트 효과를 향상시킬 수 있는 반도체 메모리 장치를 제공하는 것이다. An object of the present invention is to provide a semiconductor memory device which can improve the effect of the burn-in test.
도 6e는 번인 테스트 동작 모드시 기준 전압들의 전압 변화를 보여주는 도면이다. Figure 6e is a voltage change of the reference voltage during the burn-in test mode of operation.
상술한 제반 목적을 달성하기 위한 본 발명의 특징에 따르면, 본 발명의 반도체 메모리 장치는 행들과 열들의 매트릭스 형태로 배열된 메모리 셀들의 어레이와; According to a feature of the present invention for achieving the above-described various objects, the semiconductor memory device of the present invention the array of memory cells arranged in a matrix form of rows and columns and; 상기 어레이에 데이터를 쓰거나 상기 어레이로부터 데이터를 읽는 데이터 기입/독출 회로와; And data writing / reading circuit or writing data to the array to read data from the array; 외부 전원 전압을 조절하여 제 1 내부 전원 전압 및 제 2 내부 전원 전압을 발생하는 내부 전압 발생 회로와; Controlling the external power supply voltage to the first internal voltage generating circuit for generating the internal supply voltage and the second internal power supply voltage; 상기 제 1 내부 전원 전압을 상기 어레이로 전달하는 제 1 전원 공급 라인과; A first power supply line to pass the first internal power supply voltage to the array, and; 상기 제 2 내부 전원 전압을 상기 데이터 기입/독출 회로로 전달하는 제 2 전원 공급 라인과; A second power supply line to pass into the second internal power supply voltage to the data write / read circuit and; 그리고 상기 제 1 및 제 2 내부 전원 전압들이 동작 모드에 따라 상이한 레벨들로 가변되도록 상기 내부 전압 발생 회로를 제어하는 제어 회로를 포함한다. And a control circuit for controlling the internal voltage generating circuit wherein the first and second internal power supply voltages to be variable in different levels depending on the operating mode.
본 발명의 실시예에 있어서, 번인 테스트 동작 모드시, 상기 제어 회로는 상기 제 2 내부 전원 전압이 상기 제 1 내부 전원 전압보다 낮은 레벨을 갖도록 상기 내부 전압 발생 회로를 제어하되, 상기 제 1 및 제 2 내부 전원 전압들은 상기 외부 전압 전압의 변화에 비례하여 변화된다. In the present embodiment, when the burn-in test mode of operation, the control circuit, but the second internal power supply voltage is to have the first level lower than the first internal power supply voltage controlling the internal voltage generating circuit, the first and the 2, the internal supply voltage are changed in proportion to changes in voltage of the external voltage.
본 발명의 실시예에 있어서, 메모리 셀의 스태틱 노이즈 마진을 제어하기 위한 테스트 동작 모드시, 상기 제어 회로는 상기 제 1 내부 전원 전압이 상기 제 2 내부 전원 전압보다 낮은 레벨을 갖도록 상기 내부 전압 발생 회로를 제어하되, 상기 제 1 및 제 2 내부 전원 전압들은 상기 외부 전압 전압의 변화에 관계없이 일정하게 유지된다. In the present embodiment, the time of a test operation mode for controlling the static noise margin of the memory cell, the control circuit generates the first the internal voltage internal power supply voltage is to have the first level lower than the second internal power supply voltage circuit but the control, the first and second internal power supply voltages is kept constant regardless of changes in voltage of the external voltage.
본 발명의 실시예에 있어서, 정상적인 동작 모드시, 상기 제어 회로는 상기 제 1 및 제 2 내부 전원 전압들이 동일한 레벨을 갖도록 상기 내부 전압 발생 회로를 제어하되, 상기 제 1 및 제 2 내부 전원 전압들은 상기 외부 전압 전압의 변화에 관계없이 일정하게 유지된다. In the present embodiment, during the normal operation mode, the control circuit of the first and second, but the internal power supply voltage to have the same level of control of the internal voltage generating circuit, the first and second internal power supply voltages It is kept constant irrespective of the change of the outer voltage voltage.
본 발명의 다른 특징에 따르면, 본 발명의 반도체 메모리 장치는 행들과 열들의 매트릭스 형태로 배열된 메모리 셀들의 어레이와; In accordance with another feature of the invention, the semiconductor memory device of the present invention the array of memory cells arranged in a matrix form of rows and columns and; 행 어드레스에 응답하여 상기 행들 중 적어도 하나를 선택하는 행 선택 회로와; A row selection circuit for selecting at least one of said rows in response to a row address and; 열 어드레스에 응답하여 상기 열들 중 일부를 선택하는 열 선택 회로와; In response to the column address and the column selection circuit for selecting some of the columns; 상기 선택된 행 및 열들에 배열된 메모리 셀들로부터 데이터를 감지 증폭하는 감지 증폭 회로와; The sense amplifier circuit for amplifying the detection data from the memory cells arranged in rows and columns and said selected; 상기 선택된 행 및 열들에 배열된 메모리 셀들에 데이터를 쓰는 기입 드라이버 회로와; The selected line and write write data to the memory cells arranged in rows and the driver circuit; 외부 전원 전압을 조절하여 제 1 내부 전원 전압 및 제 2 내부 전원 전압을 발생하는 내부 전압 발생 회로와; Controlling the external power supply voltage to the first internal voltage generating circuit for generating the internal supply voltage and the second internal power supply voltage; 상기 제 1 내부 전원 전압을 상기 어레이로 전달하는 제 1 전원 공급 라인과; A first power supply line to pass the first internal power supply voltage to the array, and; 상기 제 2 내부 전원 전압을 상기 행 선택 회로, 상기 열 선택 회로, 상기 감지 증폭 회로, 그리고 상기 기입 드라이버 회로로 각각 전달하는 제 2 전원 공급 라인과; Said second internal power supply voltage of the row selection circuit, the column selection circuit, the second power supply lines respectively is transferred to the sense amplifier circuit, and the write driver circuit and; 그리고 패키지/웨이퍼 번인 테스트 동작 모드시, 상기 제 2 내부 전원 전압이 상기 제 1 내부 전원 전압보다 낮은 레벨을 갖도록 상기 내부 전압 발생 회로를 제어하는 제어 회로를 포함한다. And when the package / wafer burn-in test mode of operation, the second internal power supply voltage is to have the first level lower than the first internal power supply voltage and a control circuit for controlling the internal voltage generation circuit.
본 발명의 실시예에 있어서, 상기 패키지/웨이퍼 번인 테스트 동작 모드시, 상기 제 1 및 제 2 내부 전원 전압들은 상기 외부 전압 전압의 변화에 비례하여 변화된다. In the present embodiment, when the package / wafer burn-in test mode of operation, the first and second internal power supply voltages are changed in proportion to changes in voltage of the external voltage.
본 발명의 실시예에 있어서, 상기 메모리 셀의 스태틱 노이즈 마진을 제어하기 위한 테스트 동작 모드시, 상기 제 2 내부 전원 전압이 가변되는 반면에 상기 제 1 내부 전원 전압은 가변되지 않는다. In the present embodiment, the time of a test operation mode for controlling the static noise margin of the memory cell, wherein the first internal power supply voltage whereas the second internal power supply voltage variable is not a variable.
본 발명의 실시예에 있어서, 상기 메모리 셀의 스태틱 노이즈 마진을 제어하기 위한 테스트 동작 모드시, 상기 제 1 내부 전원 전압이 가변되는 반면에 상기 제 2 내부 전원 전압은 가변되지 않는다. In the present embodiment, the time of a test operation mode for controlling the static noise margin of the memory cell, wherein said second internal power supply voltage to the internal power supply voltage while the first variable is not a variable.
본 발명의 실시예에 있어서, 상기 메모리 셀의 스태틱 노이즈 마진을 제어하기 위한 테스트 동작 모드시, 상기 제 1 내부 전원 전압과 상기 제 2 내부 전원 전압은 서로 상반되게 가변된다. In the present embodiment, the time of a test operation mode for controlling the static noise margin of the memory cell, the first internal supply voltage and the second internal power supply voltage is variable as opposed to each other.
본 발명의 또 다른 특징에 따르면, 본 발명의 반도체 메모리 장치는 행들과 열들의 매트릭스 형태로 배열된 메모리 셀들의 어레이와; In accordance with another feature of the invention, the semiconductor memory device of the present invention the array of memory cells arranged in a matrix form of rows and columns and; 상기 어레이에 데이터를 쓰거나 상기 어레이로부터 데이터를 읽는 데이터 기입/독출 회로와; And data writing / reading circuit or writing data to the array to read data from the array; 일정한 레벨을 갖는 기준 전압을 발생하는 기준 전압 발생 회로와; A reference voltage generating circuit for generating a reference voltage having a predetermined level; 상기 기준 전압과 외부 전원 전압을 공급받고, 제 1 제어 코드에 응답하여 제 1의 가변 가능한 기준 전압을 발생하는 제 1 가변 기준 전압 발생 회로와; And first variable reference voltage generating circuit for receiving the supply of the reference voltage and the external supply voltage, in response to a first control code, generating a variable voltage reference of claim 1; 상기 기준 전압과 상기 외부 전원 전압을 공급받고, 제 2 제어 코드에 응답하여 제 2의 가변 가능한 기준 전압을 발생하는 제 2 가변 기준 전압 발생 회로와; And a second variable reference voltage generating circuit for receiving the external power supply voltage and the reference voltage, a second response to the control code generated by the variable voltage reference of the second; 상기 외부 전원 전압을 공급받고, 상기 제 1의 가변 가능한 기준 전압에 응답하여 제 1 내부 전원 전압을 발생하는 제 1 내부 전압 발생 회로와; Receiving the external power voltage, and the first internal voltage generating circuit for generating a first internal power supply voltage in response to a variable reference voltage available in the first; 상기 제 1 내부 전원 전압을 상기 어레이로 전달하는 제 1 전원 라인과; The first power line to pass the first internal power supply voltage to the array, and; 상기 외부 전원 전압을 공급받고, 상기 제 2의 가변 가능한 기준 전압에 응답하여 제 2 내부 전원 전압을 발생하는 제 2 내부 전압 발생 회로와; Receiving the external power voltage, and the second internal voltage generating circuit for generating a second internal power supply voltage in response to a variable reference voltage available in the second; 상기 제 1 내부 전원 전압을 상기 데이터 기입/독출 회로로 전달하는 제 2 전원 라인과; A second power line to pass the first internal power supply voltage to the data write / read circuit and; 그리고 테스트 정보에 응답하여 상기 제 1 제어 코드와 상기 제 2 제어 코드를 각각 발생하는 제어 회로를 포함한다. And in response to the test information and a control circuit for generating said second control code to the first control code, respectively. 패키지/웨이퍼 번인 테스트 동작 모드시, 상기 제어 회로는 상기 제 1 내부 전원 전압이 상기 제 2 내부 전원 전압보다 높게 설정되도록 상기 제 1 및 제 2 가변 기준 전압 발생 회로들을 각각 제어하기 위한 상기 제 1 및 제 2 제어 코드들을 발생한다. When the package / wafer burn-in test mode of operation, the control circuit of the first the first and for respectively controlling the first and second variable reference voltage generating circuit so that the internal supply voltage is set the first above the second internal power supply voltage the generates a second control code. 여기서, 상기 제어 회로로의 테스트 정보 입력은 JTAG 코드, 명령 조합, 또는 정상 동작 모드에서 사용되지 않는 핀을 이용하여 수행된다. Here, the test information input to the control circuit is performed using the unused pins in JTAG code, instruction set, or the normal operation mode.
본 발명의 바람직한 실시예가 참조 도면들에 의거하여 이하 상세히 설명될 것이다. A preferred embodiment of the present invention will be described in detail below on the basis of the reference diagram.
도 1은 본 발명에 따른 반도체 메모리 장치를 개략적으로 보여주는 블록도이다. Figure 1 is a block diagram schematically showing a semiconductor memory device according to the present invention. 도 1을 참조하면, 본 발명에 따른 반도체 메모리 장치 (100)는 SRAM 장치이지만, 본 발명의 사상이 다른 메모리 장치들 (예를 들면, DRAM, FRAM, EEPROM, 등등)에 적용될 수 있음은 이 분야의 통상적인 지식을 습득한 자들에게 자명하다. 1, although the semiconductor memory device 100 includes a SRAM device according to the invention, that the inventive idea can be applied to other memory devices (e.g., DRAM, FRAM, EEPROM, etc.) is a field it is apparent to those of ordinary learned knowledge. 본 발명의 반도체 메모리 장치 (100)는 데이터 정보를 저장하는 메모리 셀 어레이 (110)를 포함하며, 전원 라인 (PWRL1)을 통해 제 1 내부 전압 발생 회로 (120)로부터 내부 전원 전압 (VDD1)을 공급받는다. The semiconductor memory device 100 of the present invention comprises a memory cell array 110 for storing data information, to power line (PWRL1), the first internal voltage generating circuit inside the power supply voltage (VDD1) from 120 through receive. 주변 회로 (130)에는 제 2 내부 전압 발생 회로 (140)에서 생성되는 내부 전원 전압 (VDD2)이 전원 라인 (PWRL2)을 통해 공급된다. The internal supply voltage (VDD2) is generated in a peripheral circuit 130, the second internal voltage generating circuit 140 is supplied through the power line (PWRL2). 주변 회로 (130)는 메모리 셀 어레이 (110)의 데이터 읽기/쓰기 동작을 제어하기 위한 회로이며, 이는 이후 상세히 설명될 것이다. A peripheral circuit 130 is a circuit for controlling data read / write operation of the memory cell array 110, as will be described in detail later.
계속해서 도 1을 참조하면, 본 발명의 반도체 메모리 장치 (100)는 기준 전압 발생 회로 (150), 제 1 가변 전압 발생 회로 (160), 제 2 가변 전압 발생 회로 (170), 그리고 제어 회로 (180)를 더 포함한다. Next referring to Figure 1, the semiconductor memory device 100 includes a reference voltage generating circuit 150 of the present invention, the first variable voltage generation circuit 160, a second variable voltage generating circuit 170, and a control circuit ( 180) further comprises a. 기준 전압 발생 회로 (150)는 정상적인 동작 범위에서 일정한 레벨의 기준 전압 (Vref)을 발생한다. A reference voltage generating circuit 150 generating a reference voltage (Vref) of a constant level in the normal operating range. 앞서 설명된 특성을 갖는 기준 전압 발생 회로 (150)는 이 분야의 통상적인 지식을 습득한 자에 의해서 쉽게 설계될 수 있을 것이다. A reference voltage generating circuit 150 having the above-described characteristics could be easily designed by a person who has learned the conventional knowledge in the art. 그러므로, 기준 전압 발생 회로 (150)에 대한특정 회로는 설명되지 않을 것이다. Therefore, the specific circuit for the reference voltage generating circuit 150 will not be described. 제 1 가변 전압 발생 회로 (160)는 기준 전압 (Vref)과 외부 전원 전압 (EXTVDD)을 공급받고, 제어 회로 (180)의 제어 하에 동작 모드에 따라 가변 가능한 기준 전압 (Vref_CELL)을 발생한다. First it generates a variable voltage generating circuit 160, a reference voltage (Vref) and a variable reference voltage available (Vref_CELL) in accordance with the operation mode under the control of the supply receiving an external supply voltage (EXTVDD), the control circuit 180. 그렇게 생성된 기준 전압 (Vref_CELL)은 제 1 내부 전압 발생 회로 (120)로 전달된다. The thus generated reference voltage (Vref_CELL) is transmitted to the first internal voltage generating circuit 120. 제 2 가변 전압 발생 회로 (170)는 기준 전압 (Vref)과 외부 전원 전압 (EXTVDD)을 공급받고, 제어 회로 (180)의 제어 하에 동작 모드에 따라 가변 가능한 기준 전압 (Vref_PERI)을 발생한다. The second generates a variable voltage generating circuit 170 is a reference voltage (Vref) and a variable reference voltage available (Vref_PERI) in accordance with the operation mode under the control of the supply receiving an external supply voltage (EXTVDD), the control circuit 180. 그렇게 생성된 기준 전압 (Vref_PERI)은 제 2 내부 전압 발생 회로 (140)로 전달된다. The thus generated reference voltage (Vref_PERI) is transmitted to the second internal voltage generating circuit 140.
본 발명에 따르면, 제어 회로 (180)는 내부 전원 전압들 (VDD1, VDD2)이 동작 모드에 따라 상이한 레벨들로 가변되도록 외부로부터의 테스트 정보에 따라 제 1 및 제 2 가변 전압 발생 회로들 (160, 170)을 제어한다. According to the invention, the control circuit 180 may be internal power supply voltages (VDD1, VDD2) generating first and second variable voltage according to the test information from the outside such that the variable to different levels according to the operating mode circuit (160 controls, 170). 예를 들면, 번인 테스트시, 제어 회로 (180)는 주변 회로 (130)에 인가되는 내부 전원 전압 (VDD2)이 메모리 셀 어레이 (110)에 인가되는 내부 전원 전압 (VDD1)보다 낮게 설정되도록 제 1 및 제 2 가변 전압 발생 회로들 (160, 170)을 제어한다. For example, the burn-in test when the control circuit 180 is first to be set lower than the peripheral circuit 130, the internal supply voltage (VDD2), the internal power supply voltage (VDD1) is applied to the memory cell array 110 to be applied to the and a second control variable to the voltage generating circuit (160, 170). 이는 번인 테스트시 주변 회로 (130)에 의해서 소모되는 전류가 감소되게 한다. This allows reducing the current consumed by the peripheral circuits 130, during the burn-in test. 따라서 메모리 셀들에 대한 번인 효과가 떨어지거나 메모리 셀들에 대한 번인 테스트가 수행되지 않는 것을 방지할 수 있다. Therefore, it is possible to prevent the fall or burn-in effects on memory cells that is the burn-in test for the memory cells is performed.
이 실시예에 있어서, JTAG 코드, 사용되지 않는 핀 (예를 들면, 설계자가 이용하는 핀), 또는 명령 조합을 이용하여 제어 회로 (180)에 테스트 정보가 인가될 수 있다. In this embodiment, JTAG code, unused pin is used (for example, fin designers to use), or command combination can be applied with the test information to the control circuit 180. 이는 반도체 메모리 장치가 웨이퍼 상태뿐만 아니라 패키지 상태에서도제어 회로 (180)를 통해 제 1 및 제 2 가변 전압 발생 회로들 (160, 170)을 제어할 수 있음을 의미한다. This means that the semiconductor memory device has first and second variable voltage generating circuit (160, 170) as well as the wafer state through the state control circuit in the package 180 to be controlled.
도 2는 도 1에 도시된 메모리 셀 어레이와 주변 회로의 일예를 보여주는 블록도이다. Figure 2 is a block diagram showing an example of a memory cell array and the peripheral circuit shown in Fig. 도 2에 도시된 바와 같이, 메모리 셀 어레이 (110)는 행들 (또는 워드 라인들)과 열들 (또는 비트 라인들)의 매트릭스 형태로 배열된 메모리 셀들 (MC0-MCm)을 포함한다. As shown in Figure 2, the memory cell array 110 includes the rows (or word lines) and columns (or bit lines) of memory cells (MC0-MCm) arranged in a matrix form. 메모리 셀들 (MC) 각각은 SRAM 셀로, 도 3에 도시된 바와 같은 회로 구성을 갖는다. Memory cells (MC) each have a circuit configuration as shown in the SRAM cell, Figure 3. 도 2 및 도 3에서 알 수 있듯이, 메모리 셀들 (MC0-MCm)에는 제 1 내부 전압 발생 회로 (120)로부터의 내부 전원 전압 (VDD1)이 공급된다. As can be seen in Figures 2 and 3, the memory cells (MC0-MCm), the internal power supply voltage (VDD1) from the first internal voltage generating circuit 120 is supplied. 행 선택 회로를 구성하는 행 디코더 (RDEC), 열 선택 회로를 구성하는 열 디코더 (YDEC) 및 열 패스 게이트 (YGATE), 그리고 감지 증폭 및 기입 드라이버 회로 (SA & WD)는 도 1의 주변 회로 (130)에 속한다. Row decoder constituting the row selection circuit (RDEC), a column decoder (YDEC) and column pass gates (YGATE) constituting the column selection circuit, and a sense amplifier and a write driver circuit (SA & WD) is a peripheral circuit of Figure 1 ( 130) belongs to. 주변 회로 (130)를 구성하는 회로들은 이 분야의 통상적인 지식을 습득한 자들에게 자명하며, 그것에 대한 설명은 그러므로 생략된다. Circuit constituting the peripheral circuits 130 are also apparent to those who have acquired a conventional knowledge in the art, description of it is therefore omitted. 행 디코더 (RDEC), 열 디코더 (YDEC), 열 패스 게이트 (YGATE), 그리고 감지 증폭 및 기입 드라이버 회로 (SA & WD)에는 각각 제 2 내부 전압 발생 회로 (140)로부터의 내부 전원 전압 (VDD2)이 공급된다. A row decoder (RDEC), a column decoder (YDEC), column pass gates (YGATE), and the sense amplifier and write driver circuit (SA & WD) are respectively the second internal power supply voltage (VDD2) from the internal voltage generating circuit 140 It is supplied. 즉, 메모리 셀 어레이 (110)의 전원 체계는 주변 회로 (130)의 전원 체계와 분리되어 있다. That is, the power system of the memory cell array 110 is separated from the power system, the peripheral circuit 130.
도 4는 도 1에 도시된 제 1 내부 전압 발생 회로와 제 1 가변 전압 발생 회로의 바람직한 실시예를 보여주는 회로도이다. 4 is a circuit diagram illustrating a preferred embodiment of the first internal voltage generating circuit and the first variable voltage generation circuit shown in Fig.
도 4를 참조하면, 제 1 내부 전압 발생 회로 (120)는 가변 가능한 기준 전압 (Vref_CELL)과 외부 전원 전압 (EXTVDD)을 공급받고, 메모리 셀 어레이 (110)에 공급될 내부 전원 전압 (VDD1)을 발생한다. 4, the first internal voltage generating circuit 120 has a variable potential reference voltage (Vref_CELL) and being supplied to the external power supply voltage (EXTVDD), the memory cell array, internal power supply voltage (VDD1) is supplied to the (110) Occurs. 제 1 내부 전압 발생 회로 (120)는 3개의 PMOS 트랜지스터들 (T10, T11, T15), 3개의 NMOS 트랜지스터들 (T12, T13, T14), 그리고 커패시터 (C1)로 구성되며, 도면에 도시된 바와 같이 연결되어 있다. The first internal voltage generating circuit 120 comprises three PMOS transistors (T10, T11, T15), the three NMOS transistors (T12, T13, T14), and consists of a capacitor (C1), shown in the figures described as connected. PMOS 트랜지스터들 (T10, T11)과 NMOS 트랜지스터들 (T12, T13, T14)은 비교기로서 동작하는 차동 증폭기를 구성하며, PMOS 트랜지스터 (T15)는 비교기의 출력에 응답하여 동작하는 드라이버를 구성한다. PMOS transistors (T10, T11) and the NMOS transistor (T12, T13, T14) constitutes a differential amplifier operating as a comparator and, PMOS transistor (T15) constitutes a driver which operates in response to the output of the comparator. 비교기 (T10-T14)는 기준 전압 (Vref_CELL)과 전원 라인 (PWRL1) 상의 내부 전원 전압 (VDD1)을 비교하고, 드라이버 (T15)는 비교 결과에 따라 전원 라인 (PWRL1)으로 공급되는 전류의 양을 조절한다. A comparator (T10-T14) is the amount of current compared to an internal power supply voltage (VDD1) on the reference voltage (Vref_CELL) and the power supply line (PWRL1) and driver (T15) is supplied to the power supply line (PWRL1) according to the comparison result controls.
계속해서 도 4를 참조하면, 제 1 가변 전압 발생 회로 (160)는 5개의 PMOS 트랜지스터들 (T16, T17, T21, T22, T23), 3개의 NMOS 트랜지스터들 (T18, T19, T20), 6개의 저항기들 (RU1, RU2, RU3, RD1, RD2, RD3), 5개의 스위치들 (SW1-SW5), 그리고 커패시터 (C2)를 포함하며, 도면에 도시된 바와 같이 연결되어 있다. Subsequently 4, the first variable voltage generation circuit 160 are the five PMOS transistors (T16, T17, T21, T22, T23), the three NMOS transistors (T18, T19, T20), 6 of resistors (RU1, RU2, RU3, RD1, RD2, RD3), and includes five switches (SW1-SW5), and a capacitor (C2), has been connected as shown in the drawing. 저항기들 (RU1-RU3, RD1-RD3)과 스위치들 (SW1-SW4)은 제어 신호들 (/UP1, /UP2, /DN1, /DN2)에 응답하여 출력 노드 (OUT) 상의 전압 (Vref_CELL)을 분배하는 전압 분배 회로를 구성한다. The resistors (RU1-RU3, RD1-RD3) and switch the voltage (Vref_CELL) on the (SW1-SW4) are control signals (/ UP1, / UP2, / DN1, / DN2) in response to an output node (OUT) constitute a voltage distribution circuit for distributing. PMOS 및 NMOS 트랜지스터들 (T16-T20)은 기준 전압 (Vref)과 분배 전압 (Vdiv)을 비교하기 위한 비교기를 구성하고, PMOS 트랜지스터 (T21)는 비교기의 출력에 응답하여 동작하는 드라이버를 구성한다. The PMOS and NMOS transistors (T16-T20) constitutes a comparator for comparing a reference voltage (Vref) and the distribution voltage (Vdiv) and, PMOS transistor (T21) constitutes a driver which operates in response to the output of the comparator. PMOS 트랜지스터들 (T22, T23)과 스위치 (SW5)는 제어 신호 (/DN3)에 응답하여 출력 노드 (OUT) 상의 전압 (Vref_CELL)을 풀업시키기 위한 풀업 회로를 구성한다. PMOS transistors (T22, T23) and the switch (SW5) in response to a control signal (/ DN3) constitutes a pull-up circuit for the pull-up voltage (Vref_CELL) on the output node (OUT).
도 4에는 제 1 내부 전압 발생 회로 (120)와 제 1 가변 전압 발생 회로(160)만이 도시되어 있다. 4 has a first internal voltage generating circuit 120 and the first variable voltage generation circuit 160 only is shown. 하지만, 도 4에 도시된 스위치들 (SW1-SW5)의 온-오프 상태들이 다르게 설정된다는 점을 제외하면, 제 2 내부 전압 발생 회로 (140)와 제 2 가변 전압 발생 회로 (170)는 도 4에 도시된 것과 실질적으로 동일하게 구성된다. However, the on of the switches (SW1-SW5) shown in Fig. 4, except that the OFF state are set differently, the second internal voltage generating circuit 140 and the second variable voltage generating circuit 170 includes 4 that is substantially the same configuration as shown in. 즉, 제 1 가변 전압 발생 회로 (160)에 인가되는 제어 신호들 (/UP1, /UP2, /DN1, /DN2, /DN3)의 로직 상태들은 동작 모드에 따라 제 2 가변 전압 발생 회로 (170)에 인가되는 제어 신호들 (/UP1, /UP2, /DN1, /DN2, /DN3)의 로직 상태들과 다르게 또는 동일하게 설정될 것이다. That is, the first control signals applied to the variable voltage generator (160) (/ UP1, / UP2, / DN1, / DN2, / DN3) logic states are the first variable voltage generation circuit 170 according to the mode of operation of the of the applied control signal (/ UP1, / UP2, / DN1, / DN2, / DN3) to be logic state and a different or the same settings. 이는 제 1 및 제 2 가변 전압 발생 회로들 (160, 170)에서 생성되는 가변 가능한 기준 전압들 (Vref_CELL, Vref_PERI)이 동작 모드에 따라 동일한 값들을 또는 다른 값들을 가짐을 의미한다. This means having a first and a second variable voltage generating circuit capable of varying the reference voltage (Vref_CELL, Vref_PERI) different values or the same value according to the operation mode that is generated from the (160, 170).
도 5는 도 4에 도시된 스위치들 중 하나의 바람직한 실시예를 보여주는 회로도이다. 5 is a circuit diagram showing one preferred embodiment of the switch shown in Fig. 도 5를 참조하면, 스위치 (SW1)는 PMOS 트랜지스터 (T25), NMOS 트랜지스터 (T24), 그리고 하나의 인버터 (INV1)를 포함하며, 도면에 도시된 바와 같이 연결되어 있다. 5, the switch (SW1) comprises a PMOS transistor (T25), NMOS transistors (T24), and one inverter (INV1), and is connected as shown in the drawing. PMOS 트랜지스터 (T25)의 벌크 영역은 외부 전원 전압 (EXTVDD)으로 바이어스된다. The bulk region of the PMOS transistor (T25) is biased by the external supply voltage (EXTVDD). 입력 신호 (/UP 또는 /DN)의 로직 상태에 따라 스위치 (SW1)의 양 단자들 (ND1, ND2)이 전기적으로 연결되거나 분리될 것이다. The input signal to the terminals of the switch (SW1) (ND1, ND2) in accordance with the logic state of (/ UP or / DN) will be electrically connected to or disconnected from each other.
본 발명에 따른 반도체 메모리 장치의 테스트 동작이 도 6a 및 도 6e에 의거하여 이후 상세히 설명될 것이다. The test operation of the semiconductor memory device according to the invention Figure 6a and will be described in detail later with reference to Fig 6e. 본 발명의 반도체 메모리 장치에 따르면, 동작 모드에 따라 내부 전원 전압들 (VDD1, VDD2)이 동일한 값들을 갖거나 다른 값들을 갖는다. According to the semiconductor memory device of the present invention, the internal supply voltage according to an operation mode (VDD1, VDD2) is has the same value or have different values. 본 발명의 반도체 메모리 장치는 정상 동작 모드와 테스트 동작 모드에서 동작할 것이다. The semiconductor memory device of the present invention will operate in a normal operating mode and a test mode of operation.
정상 동작 모드의 경우, 메모리 셀 어레이 (110)에 인가되는 내부 전원 전압 (VDD1)은 주변 회로 (130)에 인가되는 내부 전원 전압 (VDD2)과 동일하게 설정된다. For the normal operation mode, the internal supply voltage (VDD1) is applied to the memory cell array 110 is set equal to the internal supply voltage (VDD2) is applied to the peripheral circuit 130. 정상 동작 모드시, 외부 전원 전압 (EXTVDD)은 도 6a에서 V1과 V2 전압들 사이에 존재한다. In normal operation mode, the external power supply voltage (EXTVDD) is present between the voltage V1 and V2 in Fig. 6a. 내부 전원 전압들 (VDD1, VDD2)을 동일하게 설정하기 위해서, 제어 회로 (180)는 제 1 및 제 2 가변 전압 발생 회로들 (160, 170)의 스위치들 (SW1-SW4)이 스위치 온되도록 제어 코드들을 발생한다. To be set identical to the internal power supply voltage (VDD1, VDD2), the control circuit 180 includes a first and second variable voltage generating circuit to control so that the switches (SW1-SW4) is switched on (160, 170) and generate code. 즉, 제 1 및 제 2 가변 전압 발생 회로들 (160, 170)에는 각각 로직 하이 레벨을 갖는 제어 신호들 (/UP1, /UP2, /DN1, /DN2)이 인가된다. That is, the first and second there is applied to the control signals each having a logic high level (/ UP1, / UP2, / DN1, / DN2), the variable voltage generating circuit (160, 170). 이때, 제 1 및 제 2 가변 전압 발생 회로들 (160, 170)에 각각 인가되는 제어 신호 (/DN3)는 로직 하이 레벨을 갖는다. In this case, the first and second variable voltage generating circuit (160, 170), each supplying control signals (/ DN3) is a has a logic high level. 이때, 제 1 가변 전압 발생 회로 (160)에서 출력되는 전압 (Vref_CELL)은 ((1+RU/RD)*Vref) (RU는 RU의 저항값을 나타내며, RD는 RD1의 저항값을 나타냄)이 된다. At this time, the first voltage (Vref_CELL) outputted from the variable voltage generating circuit 160 is ((1 + RU / RD) * Vref) (RU represents a resistance value of the RU, RD represents the resistance of the RD1) is do. 제 2 가변 전압 발생 회로 (170)에서 출력되는 전압 (Vref_PERI) 역시 제 1 가변 전압 발생 회로 (160)의 그것과 동일한 방식으로 결정될 것이다. A second variable voltage generating voltage (Vref_PERI) output from the circuit 170 is also determined in the same manner as that of the first variable voltage generation circuit 160. 따라서 가변 가능한 기준 전압들 (Vref_CELL, Vref_PERI)은, 도 6a에 도시된 바와 같이, 정상 동작 모드시 동일한 값으로 설정된다. Therefore, the variable voltage reference (Vref_CELL, Vref_PERI) is, and is set to the same value as the normal operation mode as shown in Figure 6a.
제 1 내부 전압 발생 회로 (120)는 제 1 가변 전압 발생 회로 (160)에서 생성된 기준 전압 (Vref_CELL)에 응답하여 메모리 셀 어레이 (110)에 공급될 내부 전원 전압 (VDD1)을 발생한다. The first internal voltage generating circuit 120 generates a first variable voltage generation circuit inside the power supply voltage (VDD1) is supplied in response to a reference voltage (Vref_CELL) generated in the unit 160 in the memory cell array 110. 마찬가지로, 제 2 내부 전압 발생 회로 (130)는 제 2 가변 전압 발생 회로 (170)에서 생성된 기준 전압 (Vref_PERI)에 응답하여 주변 회로 (130)에 공급될 내부 전원 전압 (VDD2)을 발생한다. Similarly, the second internal voltage generating circuit 130 is a second generation of a variable voltage generator circuit inside the power source voltage (VDD2) is supplied to the peripheral circuits 130 in response to the reference voltage (Vref_PERI) created in 170. 정상 동작 모드시 (도 6a에서 "PRD1"으로 표기된 구간) 기준 전압들 (Vref_CELL, Vref_PERI)이 동일하기 때문에, 내부 전원 전압들 (VDD1, VDD2) 역시 동일하다. Because it is the same the normal operation mode (Fig interval indicated by "PRD1" at 6a) the reference voltage (Vref_CELL, Vref_PERI), the internal power supply voltage (VDD1, VDD2) is also the same.
정상 동작 모드시, 제 1 및 제 2 가변 전압 발생 회로들 (160, 170)에 각각 인가되는 제어 신호 (/DN3)가 로직 하이 레벨이기 때문에, 제 1 및 제 2 가변 전압 발생 회로들 (160, 170)의 각각의 출력 노드 (OUT)는 PMOS 트랜지스터 (T22)를 통해 외부 전원 전압 (EXTVDD)에 연결된다. In normal operation mode, the first and second because the variable voltage generator control signal (/ DN3) to be applied respectively to 160 and 170 is a logic high level, the first and second variable voltage generating circuit (160, 170. each of the output node (OUT) of a) is through the PMOS transistor (T22) connected to the external supply voltage (EXTVDD). 정상 동작 모드에서 기준 전압 (Vref_CELL/PERI)이 단지 PMOS 트랜지스터 (T21)를 통해 결정되도록 PMOS 트랜지스터 (T22)의 문턱 전압이 충분히 높다고 가정하자. Suppose high enough threshold voltage of the PMOS transistor (T22) the reference voltage (Vref_CELL / PERI) in the normal operating mode is to be determined only through the PMOS transistor (T21). 또는 정상 동작 모드에서 기준 전압 (Vref_CELL/PERI)이 단지 PMOS 트랜지스터 (T21)를 통해 결정되도록 외부 전원 전압 (EXTVDD)과 PMOS 트랜지스터 (T22) 사이에 보다 많은 다이오드-연결된 PMOS 트랜지스터들이 연결될 수 있다. Or more diodes between the normal operation mode, the reference voltage (Vref_CELL / PERI) only external power supply voltage of the PMOS transistor to be determined by the (T21) (EXTVDD) and the PMOS transistor (T22) in-can are connected PMOS transistor is connected.
잠재적인 결함 특성을 갖는 메모리 셀을 찾아내기 위해서 스태틱 노이즈 마진 (SNM)이 제어되는 테스트 동작 모드의 경우, 메모리 셀 어레이 (110)에 인가되는 내부 전원 전압 (VDD1)은 주변 회로 (130)에 인가되는 내부 전원 전압 (VDD2)보다 낮게 설정될 것이다. To find the memory cells having the potential defect characteristics static noise margin, if the test mode of operation is (SNM) is controlled, the internal power supply voltage (VDD1) is applied to the memory cell array 110 are applied to the peripheral circuit 130 which it will be set lower than the internal supply voltage (VDD2). 테스트 동작 모드시, 외부 전원 전압 (EXTVDD)은 도 6b에서 V1과 V2 전압들 사이에 또는 "PRD2"로 표기된 구간 내에 존재한다. When the test mode of operation, the external supply voltage (EXTVDD) is present in the section labeled or "PRD2" between V1 and the voltage V2 in Fig. 6b.
메모리 셀 어레이 (110)에 인가되는 내부 전원 전압 (VDD1)을 주변 회로 (130)에 인가되는 내부 전원 전압 (VDD2)보다 낮게 설정하기 위해서, 제어 회로 (180)는 제 2 가변 전압 발생 회로 (170)의 출력 전압 (Vref_PERI)이 증가되도록 제어 코드를 발생한다. To lower than the memory cell array 110, the internal supply voltage (VDD2) is applied to the peripheral circuit 130, an internal power supply voltage (VDD1) is applied to the control circuit 180 is a second variable voltage generating circuit (170 ) generates a control code such that the output voltage (Vref_PERI) is increased. 즉, 제어 회로 (180)는 제 2 가변 전압 발생 회로 (170)로인가되는 제어 신호들 (/UP1, /UP2) (또는 제어 신호들 중 하나 이상)을 로우로 활성화시킨다. That is, the control circuit 180 activates the second variable voltage generating circuit 170, the control signal roinga (/ UP1, / UP2) (or one or more of the control signal) to low. 이때, 제어 신호들 (/DN1, /DN2, /DN3)은 로직 하이 레벨을 갖는다. At this time, the control signals (/ DN1, / DN2, / DN3) has a logic high level. 여기서, 2개의 제어 신호들 (/UP1, /UP2)이 사용되었지만, 임의의 N개의 제어 신호들 (N은 자연수)이 사용 가능하며, 사용되는 제어 신호들의 수에 따라 출력 전압 (Vref_PERI)을 변화시킬 수 있는 정도로 제어 신호들의 수가 증가한다. Here, the change in the output voltage (Vref_PERI) according to 2 the two control signals (/ UP1, / UP2) the number of control signals are used, but, any of the N number of control signals (N is a natural number) is available and, as used and so it increases the number of control signals that can. 이러한 조건에 따르면, 제 2 가변 전압 발생 회로 (170)의 스위치들 (SW1, SW2)이 스위치 오프된다. According to this condition, the second switches of the variable voltage generator (170) (SW1, SW2) are switched off. 이때, 제 2 가변 전압 발생 회로 (170)에서 출력되는 전압 (Vref_PERI)은 ((1+RU/RD1)*Vref) (RU=RD1+RD2(/UP1이 로우인 경우)+RU3(/UP2가 로우일 경우))이 된다. At this time, the second voltage (Vref_PERI) outputted from the variable voltage generating circuit 170 is ((1 + RU / RD1) * Vref) (RU = RD1 + RD2 (when the / UP1 is low) + RU3 (/ UP2 when one row is a)). 정상 동작 모드와 비교하여 볼 때 RU의 총 저항값이 증가됨에 따라, 도 6b에 도시된 바와 같이, 제 2 가변 전압 발생 회로 (170)의 출력 전압 (Vref_PERI)은 제 1 가변 전압 발생 회로 (160)의 출력 전압 (Vref_CELL)보다 더 높아진다. As the total resistance value of the RU is increased when compared to the normal operation mode, as shown in Figure 6b, a second output voltage (Vref_PERI) of the variable voltage generating circuit 170 generates a first variable voltage circuit (160 ) becomes higher than the output voltage (Vref_CELL) of. 이와 동시에, 제 1 가변 전압 발생 회로 (160)의 출력 전압 (Vref_CELL)은, 도 6b에서 알 수 있듯이, 조정되지 않는다. At the same time, the first output voltage (Vref_CELL) of the variable voltage generating circuit 160 is, as can be seen in Figure 6b, is not adjusted. 즉, 제어 회로 (180)는 가변 가능한 기준 전압 (Vref_CELL)이 변화되지 않도록 제 1 가변 전압 발생 회로 (160)를 제어한다. That is, the control circuit 180 controls the variable reference voltage as possible so as not (Vref_CELL) change the first variable voltage generation circuit 160.
제 1 내부 전압 발생 회로 (120)는 제 1 가변 전압 발생 회로 (160)에서 생성된 기준 전압 (Vref_CELL)에 응답하여 메모리 셀 어레이 (110)에 공급될 내부 전원 전압 (VDD1)을 발생한다. The first internal voltage generating circuit 120 generates a first variable voltage generation circuit inside the power supply voltage (VDD1) is supplied in response to a reference voltage (Vref_CELL) generated in the unit 160 in the memory cell array 110. 마찬가지로, 제 2 내부 전압 발생 회로 (130)는 제 2 가변 전압 발생 회로 (170)에서 생성된 기준 전압 (Vref_PERI)에 응답하여 주변 회로 (130)에 공급될 내부 전원 전압 (VDD2)을 발생한다. Similarly, the second internal voltage generating circuit 130 is a second generation of a variable voltage generator circuit inside the power source voltage (VDD2) is supplied to the peripheral circuits 130 in response to the reference voltage (Vref_PERI) created in 170. 테스트 동작 모드시 (도 6b에서 "PRD2"으로 표기된 구간) 기준 전압 (Vref_CELL)이 기준 전압 (Vref_PERI)보다 낮기 때문에, 메모리 셀 어레이 (110)에 인가되는 내부 전원 전압 (VDD1)은 주변 회로 (130)에 인가되는 내부 전원 전압 (VDD2)보다 낮다. Because the test operation mode (period from Fig. 6b indicated as "PRD2"), the reference voltage (Vref_CELL) is lower than the reference voltage (Vref_PERI), the internal power supply voltage (VDD1) is applied to the memory cell array 110 is a peripheral circuit (130 ) is lower than the internal supply voltage (VDD2) is applied to. 메모리 셀 어레이 (110)에 인가되는 내부 전원 전압 (VDD1)이 주변 회로 (130)에 인가되는 내부 전원 전압 (VDD2)보다 낮게 설정됨에 따라, 메모리 셀들의 스태틱 노이즈 마진 (SNM)이 나빠진다. As the memory cell array 110, the internal power supply voltage (VDD1) is set lower than the internal supply voltage (VDD2) is applied to the peripheral circuit 130, which is to deteriorate the static noise margin (SNM) of the memory cells. 이러한 환경에서 읽기/쓰기 동작을 수행함으로써 잠재적인 결함 특성을 갖는 메모리 셀(들)을 보다 빠르고 쉽게 찾아낼 수 있다. By performing read / write operations in these environments it can be quickly and easily find potential memory cell (s) having the defect characteristics.
스태틱 노이즈 마진이 제어되는 테스트 동작 모드시 메모리 셀 어레이 (110)에 인가되는 내부 전원 전압 (VDD1)을 주변 회로 (130)에 인가되는 내부 전원 전압 (VDD2)보다 낮게 설정하기 위한 방법들은 다양하다. Method for setting the internal supply voltage (VDD1) is applied to the static noise test mode of operation when the memory cell array 110, which margin is controlled to be lower than the peripheral circuit 130, the internal supply voltage (VDD2) is applied to will vary. 예를 들면, 도 6c에 도시된 바와 같이, 제 1 가변 전압 발생 회로 (160)의 출력 전압 (Vref_CELL)은 변화되도록 그리고 제 2 가변 전압 발생 회로 (170)의 출력 전압 (Vref_PERI)은 변화되지 않도록 제 1 및 제 2 가변 전압 발생 회로들 (160, 170)을 제어할 수 있다. For example, as shown in Figure 6c, the first so that the output voltage (Vref_CELL) of the variable voltage generating circuit 160 is changed and the second output voltage (Vref_PERI) of the variable voltage generating circuit 170 is not to change first and second it is possible to control the variable voltage generating circuit (160, 170). 이는 제 1 가변 전압 발생 회로 (160)의 스위치들 (SW3, SW4)이 스위치 오프되게 그리고 제 2 가변 전압 발생 회로 (170)의 스위치들 (SW1-SW4)이 스위치 온되게 함으로써 이루어진다. This is achieved by making the first switch of the variable voltage generator (160) (SW3, SW4) is switched off and so the second switches of the variable voltage generator (170) (SW1-SW4) is switched on. 또는, 도 6d에 도시된 바와 같이, 제 1 가변 전압 발생 회로 (160)의 출력 전압 (Vref_CELL)이 제 2 가변 전압 발생 회로 (170)의 출력 전압 (Vref_PERI)과 반대 방향으로 변화되도록 제 1 및 제 2 가변 전압 발생 회로들 (160, 170)을 제어할 수 있다. Alternatively, the first and such that the first change in the output voltage (Vref_CELL) of the variable voltage generating circuit 160 to the output voltage (Vref_PERI) opposite to the direction of the second variable voltage generating circuit 170, as shown in Figure 6d 2 may control the variable voltage generating circuit (160, 170). 이는 제 1 가변 전압 발생 회로 (160)이 스위치들 (SW3, SW4)이 스위치 오프되게 그리고 제 2 가변 전압 발생 회로 (170)의 스위치들 (SW1, SW2)이 스위치 온되게 함으로써 이루어진다. This is accomplished by having the first variable voltage generation circuit 160, the switches (SW3, SW4) is switched off and so the second switches of the variable voltage generator (170) (SW1, SW2) is switched on. 출력 전압 (Vref_PERI/Vref_CELL)이 다양하게변화되도록 제 1 및 제 2 가변 전압 발생 회로들 (160, 170)에 각각 사용되는 스위치들의 수가 다양하게 조절될 수 있음은 자명하다. That the output voltage (Vref_PERI / Vref_CELL) the number of switches used for each of the first and second variable voltage generating circuit (160, 170) such that various changes can be variously adjusted, it is obvious.
번인 테스트 동작 모드의 경우, 주변 회로 (130)에 인가되는 내부 전원 전압 (VDD2)은 메모리 셀 어레이 (110)에 인가되는 내부 전원 전압 (VDD1)보다 낮게 설정될 것이다. For the burn-in test mode of operation, the internal power supply voltage (VDD2) is applied to the peripheral circuit 130 will be set to be lower than the internal supply voltage (VDD1) is applied to the memory cell array 110. 번인 테스트 동작 모드는 도 6e에서 "PRD5"로 표기된 구간에 속한다. Burn-in test mode of operation belongs to the section labeled "PRD5" In Fig. 6e. PRD5 구간에서 기준 전압들 (Vref_CELL, Vref_PERI)은 외부 전원 전압 (EXTVDD)을 따라 증가된다. The reference voltage (Vref_CELL, Vref_PERI) in PRD5 interval is increased as the external supply voltage (EXTVDD).
번인 테스트 동작 모드시, 제어 회로 (180)는 제 1 가변 전압 발생 회로 (160)로 로직 하이 레벨의 제어 신호 (/DN3)를 인가한다. When the burn-in test mode of operation, the control circuit 180 applies a control signal (/ DN3) of the logic high level to the first variable voltage generation circuit 160. 제어 신호들 (/DN1, /DN2, /UP1, /UP2)은 모두 로직 로우/하이 레벨을 갖는다고 가정하자. Assume that the control signals (/ DN1, / DN2, / UP1, / UP2) both have a logic low / high level. 번인 테스트 동작 모드시, 제 1 내부 전압 발생 회로 (120)에 인가되는 기준 전압 (Vref_CELL)은 제 1 가변 전압 발생 회로 (160)의 차동 증폭기의 비교 결과에 의해서 결정되는 것이 아니라 그것의 PMOS 트랜지스터들 (T22, T23)을 통해 결정된다. When the burn-in test mode of operation, first the reference voltage (Vref_CELL) applied to the internal voltage generation circuit 120 is a first variable voltage generation of its PMOS transistor instead of being determined by the comparison result of the differential amplifier of circuit 160 It is determined by the (T22, T23). 그러한 이유로, 가변 가능한 기준 전압 (Vref_CELL)은 외부 전원 전압 (EXTVDD)을 따라 증가한다. For that reason, the variable reference voltage available (Vref_CELL) increases with the external supply voltage (EXTVDD). 제어 신호 (/DN3)가 로직 하이 레벨이기 때문에, 기준 전압 (Vref_CELL)은 (EXTVDD-Vth) (Vth는 PMOS 트랜지스터의 문턱 전압)이 된다. Since the control signal (/ DN3) is a logic high level, the reference voltage (Vref_CELL) is the (EXTVDD-Vth) (Vth is the threshold voltage of PMOS transistor).
이와 동시에, 번인 테스트 동작 모드시, 제어 회로 (180)는 제 2 가변 전압 발생 회로 (170)로 로직 로우 레벨의 제어 신호 (/DN3)를 인가한다. At the same time, when the burn-in test mode of operation, the control circuit 180 applies a second variable voltage generating circuit control signal (/ DN3) of the logic low level to 170. 제어 신호들 (/DN1, /DN2, /UP1, /UP2)은 모두 로직 로우/하이 레벨을 갖는다고 가정하자. Assume that the control signals (/ DN1, / DN2, / UP1, / UP2) both have a logic low / high level. 번인 테스트 동작 모드시, 제 2 내부 전압 발생 회로 (140)에 인가되는 기준 전압(Vref_PERI)은 제 2 가변 전압 발생 회로 (170)의 차동 증폭기의 비교 결과에 의해서 결정되는 것이 아니라 그것의 PMOS 트랜지스터들 (T22, T23)을 통해 결정된다. When the burn-in test operation mode, first the second internal voltage generating circuit 140, a reference voltage (Vref_PERI) applied to the second variable voltage generating its PMOS transistor instead of being determined by the comparison result of the differential amplifier of circuit 170 It is determined by the (T22, T23). 제어 신호 (/DN3)가 로직 로우 레벨이기 때문에, 기준 전압 (Vref_PERI)은 (EXTVDD-2Vth)이 된다. Since the control signal (/ DN3) is a logic low level, the reference voltage (Vref_PERI) is the (EXTVDD-2Vth).
앞서의 설명에 따르면, 번인 테스트 동작 모드시, 기준 전압 (Vref_CELL)은 (EXTVDD-Vth)이 되고 기준 전압 (Vref_PERI)은 (EXTVDD-2Vth)이 된다. According to the foregoing description, when the burn-in test mode of operation, the reference voltage (Vref_CELL) is the (EXTVDD-Vth) reference voltage (Vref_PERI) is the (EXTVDD-2Vth). 도 6e에 도시된 바와 같이, 제 2 내부 전압 발생 회로 (140)의 기준 전압 (Vref_PERI)이 제 1 내부 전압 발생 회로 (120)의 기준 전압 (Vref_CELL)보다 낮게 설정됨에 따라, 주변 회로 (130)에 인가되는 내부 전원 전압 (VDD2)은 메모리 셀 어레이 (110)에 인가되는 내부 전원 전압 (VDD1)보다 낮게 설정될 것이다. The peripheral circuit 130, as the second reference voltage (Vref_PERI) of the internal voltage generating circuit 140 is set to be lower than the reference voltage (Vref_CELL) of the first internal voltage generating circuit 120, as shown in Figure 6e the internal supply voltage (VDD2) is applied to will be set lower than the internal supply voltage (VDD1) is applied to the memory cell array 110. 주변 회로에 인가되는 내부 전원 전압 (VDD2)을 낮춤으로써 번인 테스트 동작시 주변 회로에 의해서 소모되는 전류를 줄일 수 있다. By lowering the internal power-supply voltage (VDD2) is applied to the peripheral circuit can reduce the current consumed by the peripheral circuits when the burn-in test operation.
이상에서, 본 발명에 따른 회로의 구성 및 동작을 상기한 설명 및 도면에 따라 도시하였지만, 이는 예를 들어 설명한 것에 불과하며 본 발명의 기술적 사상 및 범위를 벗어나지 않는 범위 내에서 다양한 변화 및 변경이 가능함은 물론이다. In the above, although depicted in accordance with a description and drawings wherein the configuration and operation of the circuit according to the present invention, which is that various changes and modifications are possible in the example only and do not depart from the spirit and scope of the invention ranges to those described as a matter of course.
상술한 바와 같이, 제어 회로 (180)를 통해 내부 전압 발생 회로들 (120, 140)에 각각 인가되는 기준 전압들 (Vref_CELL, Vref_PERI)을 가변시킬 수 있다. As described above, the internal voltage generating circuit via the control circuit 180. The reference voltage to be applied to each (120, 140) (Vref_CELL, Vref_PERI) can be varied. 특히, 패키지 상태의 반도체 메모리 장치에 있어서, 제어 회로 (180)를 통해 기준 전압들 (Vref_CELL, Vref_PERI)을 가변시킴으로써 주변 회로에 의해서 소모되는 전류를 줄일 수 있다. In particular, in the state of the package the semiconductor memory device, it is possible to reduce the current consumed by the peripheral circuit by the reference voltage through a control circuit (180) (Vref_CELL, Vref_PERI) variable. 따라서, 번인 테스트 동작시 사용되는 내부 전원 전압의 감소를 줄임으로써, 반도체 메모리 장치의 웨이퍼 상태에서 번인 테스트를 정상적으로 수행하거나 그것의 번인 효과를 증가시킬 수 있다. Therefore, the burn-in test operation when by reducing the decrease in the internal power supply voltage is used, it is possible to perform the burn-in test properly in the wafer state of the semiconductor memory device, or increase its burn effect.
상기 제 1 및 제 2 내부 전원 전압들이 동작 모드에 따라 상이한 레벨들로 가변되도록 상기 내부 전압 발생 회로를 제어하는 제어 회로를 포함하는 것을 특징으로 하는 반도체 메모리 장치. A semiconductor memory device comprising: a control circuit for controlling the internal voltage generating circuit wherein the first and second internal power supply voltages to be variable in different levels depending on the operating mode.
번인 테스트 동작 모드시, 상기 제어 회로는 상기 제 2 내부 전원 전압이 상기 제 1 내부 전원 전압보다 낮은 레벨을 갖도록 상기 내부 전압 발생 회로를 제어하는 것을 특징으로 하는 반도체 메모리 장치. When the burn-in test mode of operation, the control circuit is a semiconductor memory device, characterized in that for controlling the internal voltage generation circuit and the second internal power supply voltage so as to have a lower level than the first internal supply voltage.
메모리 셀의 스태틱 노이즈 마진을 제어하기 위한 테스트 동작 모드시, 상기 제어 회로는 상기 제 1 내부 전원 전압이 상기 제 2 내부 전원 전압보다 낮은 레벨을 갖도록 상기 내부 전압 발생 회로를 제어하는 것을 특징으로 하는 반도체 메모리 장치. When the test operation mode for controlling the static noise margin of the memory cell, the control circuit includes a semiconductor, characterized in that for controlling the internal voltage generating circuit wherein the first internal power supply voltage to have the first level lower than the second internal power supply voltage memory device.
정상적인 동작 모드시, 상기 제어 회로는 상기 제 1 및 제 2 내부 전원 전압들이 동일한 레벨을 갖도록 상기 내부 전압 발생 회로를 제어하되, 상기 제 1 및 제 2 내부 전원 전압들은 상기 외부 전압 전압의 변화에 관계없이 일정하게 유지되는 것을 특징으로 하는 반도체 메모리 장치. When the normal operation mode, the control circuit related to the first and second internal power supply voltage will have the same level, but controls the internal voltage generating circuit, the first and second internal power supply voltages change in the external voltage voltage a semiconductor memory device characterized in that the constant without.
패키지/웨이퍼 번인 테스트 동작 모드시, 상기 제 2 내부 전원 전압이 상기 제 1 내부 전원 전압보다 낮은 레벨을 갖도록 상기 내부 전압 발생 회로를 제어하는 제어 회로를 포함하는 것을 특징으로 하는 반도체 메모리 장치. When the package / wafer burn-in test mode of operation, the semiconductor memory device of the second internal power supply voltage is to have the first level lower than the first internal power supply voltage characterized in that it comprises a control circuit for controlling the internal voltage generation circuit.
상기 패키지/웨이퍼 번인 테스트 동작 모드시, 상기 제 1 및 제 2 내부 전원 전압들은 상기 외부 전압 전압의 변화에 비례하여 변화되는 것을 특징으로 하는 반도체 메모리 장치. When the package / wafer burn-in test mode of operation, the first and second internal power supply voltages to the semiconductor memory device characterized in that it changes in proportion to changes in voltage of the external voltage.
상기 메모리 셀의 스태틱 노이즈 마진을 제어하기 위한 테스트 동작 모드시, 상기 제 2 내부 전원 전압이 가변되는 반면에 상기 제 1 내부 전원 전압은 가변되지 않는 것을 특징으로 하는 반도체 메모리 장치. A semiconductor memory device, characterized in that the time of a test operation mode for controlling the static noise margin of the memory cell, wherein the first internal power supply voltage whereas the second internal power supply voltage variable is not a variable.
상기 메모리 셀의 스태틱 노이즈 마진을 제어하기 위한 테스트 동작 모드시, 상기 제 1 내부 전원 전압이 가변되는 반면에 상기 제 2 내부 전원 전압은 가변되지 않는 것을 특징으로 하는 반도체 메모리 장치. A semiconductor memory device, characterized in that the time of a test operation mode for controlling the static noise margin of the memory cell, wherein said second internal power supply voltage to the internal power supply voltage while the first variable is not a variable.
상기 메모리 셀의 스태틱 노이즈 마진을 제어하기 위한 테스트 동작 모드시, 상기 제 1 내부 전원 전압과 상기 제 2 내부 전원 전압은 서로 상반되게 가변되는 것을 특징으로 하는 반도체 메모리 장치. When the test operation mode for controlling the static noise margin of the memory cell, the semiconductor memory device, characterized in that the first internal power supply voltage and the second internal power supply voltage which varies contrary to each other.
정상적인 동작 모드시, 상기 제어 회로는 상기 제 1 및 제 2 내부 전원 전압들이 동일한 레벨을 갖도록 상기 내부 전압 발생 회로를 제어하되, 상기 제 1 및제 2 내부 전원 전압들은 상기 외부 전압 전압의 변화에 관계없이 일정하게 유지되는 것을 특징으로 하는 반도체 메모리 장치. When the normal operation mode, the control circuit of the first and second, but the internal power supply voltage to have the same level of control of the internal voltage generating circuit, the first mitje second internal power supply voltages, regardless of the change of the external voltage voltage a semiconductor memory device characterized in that the constant.
패키지/웨이퍼 번인 테스트 동작 모드시, 상기 제어 회로는 상기 제 1 내부 전원 전압이 상기 제 2 내부 전원 전압보다 높게 설정되도록 상기 제 1 및 제 2 가변 기준 전압 발생 회로들을 각각 제어하기 위한 상기 제 1 및 제 2 제어 코드들을 발생하는 것을 특징으로 하는 반도체 메모리 장치. When the package / wafer burn-in test mode of operation, the control circuit of the first the first and for respectively controlling the first and second variable reference voltage generating circuit so that the internal supply voltage is set the first above the second internal power supply voltage a semiconductor memory device, characterized in that for generating the second control code.
메모리 셀의 스태틱 노이즈 마진을 제어하기 위한 테스트 동작 모드시, 상기 제어 회로는 상기 제 2 내부 전원 전압이 상기 제 1 내부 전원 전압보다 높게 설정되도록 상기 제 1 및 제 2 가변 기준 전압 발생 회로들을 제어하기 위한 상기 제 1 및 제 2 제어 코드들을 발생하되, 상기 제 1 및 제 2 내부 전원 전압들은 상기 외부 전압 전압의 변화에 관계없이 일정하게 유지되는 것을 특징으로 하는 반도체 메모리 장치. When testing for controlling the static noise margin of the memory cell operation mode, the control circuit controlling the first and second variable reference voltage generating circuit to the second internal power source voltage is first set to be higher than the internal supply voltage a semiconductor memory device characterized in that the first and second, but generate control codes, said first and second constant regardless of changes in the internal power supply voltages are the voltages for the external voltage.
상기 메모리 셀의 스태틱 노이즈 마진을 제어하기 위한 테스트 동작 모드시,상기 제 2 내부 전원 전압이 가변되는 반면에 상기 제 1 내부 전원 전압은 가변되지 않는 것을 특징으로 하는 반도체 메모리 장치. A semiconductor memory device, characterized in that the time of a test operation mode for controlling the static noise margin of the memory cell, wherein the first internal power supply voltage whereas the second internal power supply voltage variable is not a variable.
정상적인 동작 모드시, 상기 제어 회로는 상기 제 1 내부 전원 전압과 상기 제 2 내부 전원 전압이 동일한 레벨로 설정되도록 상기 제 1 및 제 2 가변 기준 전압 발생 회로들을 제어하기 위한 상기 제 1 및 제 2 제어 코드들을 발생하되, 상기 제 1 및 제 2 내부 전원 전압들은 상기 외부 전압 전압의 변화에 관계없이 일정하게 유지되는 것을 특징으로 하는 반도체 메모리 장치. When the normal operation mode, the control circuit of the first internal power supply voltage and the second of the first and second control for controlling the first and second variable reference voltage generating circuit so that the internal supply voltage is set to the same level but generates the code, the first and second internal power supply voltages to the semiconductor memory device being kept constant irrespective of the change of the outer voltage voltage.
상기 제어 회로로의 테스트 정보 입력은 JTAG 코드, 명령 조합, 또는 정상 동작 모드에서 사용되지 않는 핀을 이용하여 수행되는 것을 특징으로 하는 반도체 메모리 장치. Test information input to the control circuit, semiconductor memory device, characterized in that is carried out using an unused pin on the JTAG code, instruction set, or the normal operation mode.


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Seasonal accomodations
Labels and classification
Self harvesting
Chapel of Tanya
Mill of La Pave
Côte de la Place
The old electricity generating station
The church of Saint Félix
The Place de la République
The passageway of the kings of Majorca
The mill channel
La rue François Arago
In the immediate vicinity
At 20 - 30 minutes
At about 45 minutes
At about 1 hour
At about 1h30 - 2h00
South Catalonia
Bagà, town twinned with Laroque
Hiking in the department
Mountain guides and hike clubs
Accomodations and refuges
A walker
A gastronome
Accueil> Home> Tourist office> Explore> Laroque> La rue François Arago
Originally, this road was called the Road of the Hospital and was later named after François Arago.
· In the Middle Ages there was a hospital run by monks to accommodate both sick people and pilgrims, many from the route of Saint Jacques de Compostelle.
When the village was extended, after 1371, the hospital was divided up into separate houses, extending from number 15 to 53.
There is a covered passageway at number 17 which led to a mill, built after 1800 and the only mill which produced both oil and flour.
A little further along the road, just after number 3, in the corner you can see an arch in red bricks and behind it two smaller arches which mark the junction of the different water channels which supply the top of the village.
The large archway dates from the fourteenth century and the two smaller ones from the eighteenth.
FRANCOIS ARAGO
He was born on 26th February 1786 at Estagel and died in Paris on 2nd October 1853.
Dominique François Jean Arago was a french astronomer, physicist, and politician. He went to a secondary school at Perpignan (now the Lycée François Arago) and then went on to higher education at the Ecole Polytechnic of Paris.
In 1825, he researched into the pressure of water vapour. He devoted other studies to astronomy, magnetism and the polarisation of light. For example, he was able to measure the diametre of the planets and studied the light produced by stars.
His name is inscribed on the Eiffel Tower, on another Paris monument called 'Homage to Arago' as well as on medallions placed in the ground of the capital, along the Paris Meridian.
There are many towns in the Pyrénées-Orientales which have roads named after him, and in particular, this one in Laroque des Albères.
Tourism Office
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The (former) Willemsbrug in the heart of Rotterdam, with on the left hand the railway bridge.
The rail- and traffic bridges in the heart of Rotterdam were the main objectives of the small German air-landing company that landed on the Nieuwe Maas in sea-planes in the early hours of 10 May 1940. Possession of these bridges would mean that all crossings between the Moerdijk bridges in the south and these bridges in the north would be in German hands, so that the 9.Panzer Division would be able to roll straight into the heart of Fortress Holland.
These bridges were the swivel-point around which a blazing battle raged on for the full five days of the war. They would only fall in German hands after the devasting Luftwaffe raid on Rotterdam, whcih was followed by capitulation of Rotterdam. Many Dutch and German troops were killed during the fierce fights on and around these bridges and the adjacent Noordereiland.
The old Willemsbrug does no longer exist today. It was replaced in the last decade of the 20th century by the huge Erasmusbridge. Yet it is a major merit on the regimental colours of the Dutch Marines. It were especially these crack professional soldiers of the Dutch Marines Corps that played a key role in retaking much of the German northern stronghold and defending these bridges.
The few hundred Marines were assisted by the Rotterdam garrison comprising engineering-recruits, airforce and navy auxilary forces and a few battalions of regular infantry, mainly send in as off the second day of the invasion. On the German side the battle was fought by the 3rd battalion of Infantry Regiment 16 (22nd Airlanding Infantry Division), supported by one platoon of airbornes (of the 11./Fjr.1) and the additional support of only a few infantry guns and AT guns. Although many reports speak of over 1,000 Germans occupying the bridge area and the adjecent Noordereiland, in fact no more than around 500 men were present at any given moment during the battle. At the peak of the battle, the Dutch had more than a six fold of troops available along the Maas in Rotterdam.


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Epic's Gamble discusses studio closures
Disney buying Black Rock "made no sense".
News by	Wesley Yin-Poole, Deputy Editorial Director
Updated on 17 July 2011
Epic Games' European boss Mike Gamble has blamed the recent spate of high-profile triple-A game developer closures on "stupid acquisitions" made by publishers.
Gamble highlighted Disney Interactive's purchase of Pure and Split/Second developer Black Rock, which recently closed down, as an example.
"It's happened because of stupid acquisitions," he told Eurogamer at Epic Games' recent Unreal Engine University day in London.
"This is a personal view. In my person opinion, yeah, there have been acquisitions by publishers of developers they really had no right – well, they had a right because they had the money - but what was the point of a well-known children's IP holder buying a hardcore racing studio? It doesn't make sense."
Analysts suggested last week the closure of Black Rock had more to do with owner Disney's desire to get out of console game development than any deficiencies at the Brighton-based studio.
Disney's decision followed Activision's shuttering of Blur and Project Gotham Racing developer Bizarre Creations after it failed to find a buyer.
"A lot of the pain we've had in the last 18 months has been down to the economics of games development, which has changed," Gamble continued.
"Big publishers have had to pull back in money wise and the casualties of that are the studios that haven't performed for them because the industry has changed."
A number of small developers have formed from the ashes of both Bizarre and Black Rock.
Bizarre has spawned a handful of studios, including Hogrocket and Lucid Games.
Black Rock's death has led to the creation of three studios so far: Roundcube Entertainment, lead by Split/Second director Nick Baynes; ShortRound Games, formed by a quartet of previous Black Rock department directors; and BossAlien, fronted by Pure director Jason Avent.
"It is sad," Gamble, who this week met with a number of start-ups to discuss the merits of Unreal Engine for game development, commented.
"It's sad in a sense, but it's fantastic in a whole other way. Of course, a percentage of those people have left the industry. But most of them haven't. They're still in the industry. They're now just doing other cool stuff.
"The games I'm seeing from indies and small developers are brilliant. I love it. Really interesting and creative. They're not ticking boxes for publishers that say, we've got this gap in the portfolio, and there's this demographic, so we need to create this.
"They're playing with concepts, with how things are controlled. It's very creative."
Overall, Gamble believes UK and European game development is in a healthy state.
But, "It's healthy in a very different way than it has been. We've had Bizarre go pop. We've had Black Rock go pop. There's been a lot of bad news.
"But the fallout from that has been that there's now a whole bunch of really interesting studios doing cool stuff. And they all have a really good shot at being successful. A lot of them are really focused on not becoming big studios.
"They're focused on, we want to stay 12 guys doing cool stuff, we know there's a route to market, we can self publish, and we know we can make enough money to continue to do the good stuff we want to do.
"There's a sea change in the European industry. People are not looking to create companies where they're going to buy Ferraris. They're looking to create companies where they're having a great time and making nice money, but really doing the cool stuff."
Buy Blur from Amazon [?]
Blur Review
Split/Second: Velocity
Split/Second: Velocity Review
Wesley Yin-Poole
Deputy Editorial Director	| wyp100
Wesley is deputy editorial director of ReedPop. He likes news, interviews, and more news. He also likes Street Fighter more than anyone can get him to shut up about it.
The Rock is bringing "one of the biggest, most badass games" to the big screen
Official announcement coming later this year.
Next three Call of Duty games reportedly heading to PlayStation despite Microsoft acquisition
Including a Warzone 2.
More than 20 million have played Halo Infinite
Biggest launch in Halo history.
Little Big Adventure reboot is tweaking its name in light of Little Big Planet's success
And aiming to release in 2024.
Feature | Someone should make a game about: Deafness
We're not talking about The Quiet Man.
Crysis 4 image appears online
Suit up.
Aztech Forgotten Gods has a release date
And a new trailer.
Raven Software union bid pushes on, despite Activision Blizzard missing deadline to respond
Auto-upload of screenshots and videos to mobile coming to PS5
Previously tested feature now rolling out globally.


REC hosted the fourth annual Effective Committees Workshop for members of responsible investment committees nationwide. Representatives from Haverford College, NYU, Green Mountain College, and fifteen other schools were in attendance.
Committees at Carleton College, Macalester College, and the University of Louisville are exploring the development of their committees as well as different potential strategies for this year and the next.
The Brown University Open the Books Coalition hosted an open panel / forum on the eve of the Board of Trustees' decision to not reinvest in HEI, which REC attended. Besides the HEI decision, topics discussed included the recent transparency legislation in Massachusetts and the state of the national movement.
Loyola University of New Orleans is in the early planning stages for a responsible investment campaign and proposal, and is working with REC on developing their goals!
Mt. Holyoke College's responsible investment committee continues to develop and strengthen proposed responsible investment guidelines, while also planning an awareness-raising event for the community.
REC has been in touch with PEAR (Pomona for Environmental Activism and Responsibility) about potentially integrating responsible investment into an environmental campaign at their school.
Stanford University's chapter of STAND (Students Taking Action Now in Darfur) is hosting a conference in April that will bring both students and company representatives together in order to learn how to take action against the sale of conflict minerals. Following the passage of the first-ever proxy voting guideline specifically concerned with conflict minerals, STAND and attendees will be exploring other responsible investment tools.
At the University of Texas, the Longhorns for Investing Responsibly presented a proposal to the UT Investmnet Management Company to incorporate a responsible investment policy into their mission statement, which received significantly media coverage.
REC visited the University of California at Santa Barbara in March, speaking at a Social Entrepreneurship event and engaging in conversations about potentially bringing a responsible investment committee proposal to the administration before the end of the year.
The Penn Conflict Minerals Campaign at the University of Pennsylvania joined the Responsible Endowments Coalition and is working on taking action.
Vassar College hosted an event about hydraulic fracturing on campus ("fracking") bringing in representatives of different constituencies. You can read more about the event here.
Students at Wesleyan University are planning a responsible investment event and inviting REC! Contact us for more details.


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Ajinomoto ASEAN Victory Project®
AJINOMOTO CO, INC. (AJICO) is the only food company named as Platinum Sponsor in the historic 30th Southeast Asian Games (SEAG). The 2019 SEA Games likewise served as a milestone event for AJINOMOTO PHILIPPINES CORPORATION (APC) in its first venture to support Filipino athletes as part of the Ajinomoto ASEAN Victory Project program. Philippine Karate athlete Ms. Junna Tsukii and Philippine Pole Vault athlete Mr. Ernest John Obiena both clinched the much-coveted Gold Medals in their specific fields. Mr. Obiena is the first Filipino to qualify for the Tokyo 2020 Olympics, while Ms. Tsukii is on a race to qualify as an Olympian.
Ernest John "EJ" Obiena
30th SEA Games Gold Medalist – Pole Vault
First Filipino to Qualify in the Tokyo 2020 Olympics
Junna Tsukii, 30th SEA Games Gold Medalist – Karate,
and commissioner Mr. Ramón S. Fernández of
Philippine Sports Commission
In a bid to be a driving force in the advancement of food and health, Ajinomoto utilizes its expertise in Amino Science to expand its footprints in the area of sports nutrition. In 2003, the Tokyo-based company jointly formed the Victory Project® with the Japan Olympic Committee to stage series of events that highlighted sports nutritional guidance and amino acid conditioning of top-level Japanese athletes. This is done through Ajinomoto's Kachimeshi® ("Winning Meals") to support elite athletes in building winning physiques for optimum performance during international tournaments. This Victory Project® has contributed to the success of Japanese Athletes particularly in securing Olympic medals. As early as 2016, AJICO was named as one of the official partners in the Tokyo 2020 Olympics and Paralympics games.
The Ajinomoto ASEAN Victory Project was introduced in 2017 to impart Ajinomoto's Kachimeshi® ("Winning Meals") to ASEAN athletes. The contingents involved in this project also went on a winning streak during the 30th SEA Games. Among the 30th SEA Games medalists supported by this project are Thailand Women's National Volleyball Team, Singapore's Swimming Team and Indonesian Swimmer I Gede Siman Sudartawa.
Ajinomoto affiliates from Philippines, Thailand, Singapore and Indonesia organized different strategies and deployed support systems to assist sponsored athletes. With strong knowledge of food cultures, Ajinomoto created recipe menus targeted to satisfy nutrition and taste preference of respective national athletes. Nutritionist-Dietitians and Professional Chefs personally assisted some athletes to provide guidance in nutrition and supplementation.
According to APC President Tsutomu Nara, "Ajinomoto aims to realize greater wellness for people around the world. We are glad about the turnout of the 30th SEA Games and about the fact that we could help our national athletes achieve their full potentials. We are committed to support our Filipino Athletes and hope to see them thrive not only in SEA Games but also in Asian Games and the Olympics."
For more information about Ajinomoto and its products, visit www.ajinomoto.com.ph and facebook.com/CookmunitybyAjinomotoPH.
The Ajinomoto Group is a global company with specialties in the business of food and amino acids, guided by our leading-edge bioscience and fine chemical technologies.
Based on the corporate message "Eat Well, Live Well.", we have been scientifically pursuing the possibilities of amino acids in supporting the healthy lives of people all around the world. We aim for future growth and continuous contribution to greater wellness by creating value through sustainable and innovative solutions for communities and society.
The Ajinomoto Group has offices in 35 countries and regions, and sells products in more than 130 countries and regions. In fiscal 2018, sales were 1.1274 trillion yen (10.1 billion U.S. dollars). To learn more, visit www.ajinomoto.com.


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JAY-Z to Release Physical Copies Of '4:44' With Bonus Tracks
blame it on JES7 July 1, 2017
The power and reach of JAY-Z's thirteenth album, 4:44, and the viral campaign that was accompanied with it doesn't extend solely to the United States and Europe. I recently had a friend tell me his cousin whom lives in rural Philippines has been clamoring for a copy, and with no other means to find one, has been relegated to score a copy through other, frowned-upon means. Not to mention, the Philippines' internet service is ranked 108th.
Needless to say, since the release of the rap Elohim's "surprise" album — produced entirely by No I.D. with a lengthly list of incredible sample choices — has been on repeat here at the DopeHouse, and is arguably (is it really an argument though?) an AoTY contender.
The downside to all of this of course, is in order to listen to the album (without pirating it, tsk tsk), you'd either have to sign up through Sprint or have an already-existing TIDAL account. The good news is engineer extraordinaire Young Guru has revealed a few bonus tracks, including "Adnis" (which was teased a few weeks back), will appear on future physical copies.
A post shared by 2DOPEBOYZ.COM (@2dopeboyz) on Jul 1, 2017 at 9:59am PDT
No I.D. confirmed in a recent Rolling Stone interview:
"There's three more songs that are coming out as bonuses," I.D. said. "James Blake came in and joined into the process. There's more coming shortly that's equally as revealing."
According to a source at Billboard, "4:44 will be added to Apple Music/iTunes next week after its one-week exclusivity window on Tidal," continuing "A physical release is eventually planned, though no timetable has been set yet for that roll-out."
JAY-Z to Release Physical Copies Of '4:44' With Bonus Tracks was last modified: March 31st, 2018 by JES7
Tags:jay-z
Watch the Official Trailer For Marvel's 'Inhumans'
JAY-Z, Maturity & Why Dopeness Doesn't Expire


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Access to public information and freedom of information (FOI) refer to the right to access information held by public bodies also known as "right to know". Access to public information is considered of fundamental importance for the effective functioning of democratic systems, as it enhances governments' and public officials' accountability, boosting people participation and allowing their informed participation into public life. The fundamental premise of the right to access public information is that the information held by governmental institutions is in principle public and may be concealed only on the basis of legitimate reasons which should be detailed in the law.

Access to information, just as media independence and pluralism remain critical issues in the Republic of Moldova. Despite numerous calls for media legislation reform, the government of Moldova has not made significant steps to improve access to information according to the country's international obligations, including a convention with the Council of Europe. Public officials widely impede access to public information through refusals, delays or incomplete answers, without sanctions. In 2014, the Independent Journalism Center (IJC) presented to Parliament amendments to improve the law on access to information, provide additional guarantees for journalists and limit unjustified limitations of access to public information by public officials. However, the draft law has not yet been adopted. According to the Executive Director of the Association of Independent Press, Petru Macovei, overall the law on access to information is good, but it is compromised by a non-collaborative attitude of the public authorities.

Legal framework

The right to access public information in guaranteed by Article 34 of the Moldovan Constitution and is regulated by the Law on Access to Information which was adopted in 2000. The law establishes that information of public interest can be requested in writing or orally. Information can be consulted at the institution's premises or can be received stored in an electronic support or in hardcopy.  Viewing documents on the institution's premises is free of charge, while reasonable fees can be charged for the cost of photocopying, transcribing, translating or delivering the documents. According to the law, documents of public interest must be provided within 15 working days, which can be extended by five days in case of requests of large numbers of documents. If the request is rejected, the applicant can exercise its right of appeal to the relevant courts, and if the court decides on behalf of the applicant, the law imposes penalties in form of fines to the government body which has violated the law. Exceptions justifying limitation to the disclosure regime are specified in the law and include state secrets, information on the military, intelligence, economic, foreign policy or criminal proceedings, information concerning ongoing lawsuit, personal data, confidential business data, and preliminary results of scientific and technical research.

Access to information in practice

In practice, compliance with the Law on Access to Information remains weak just as its implementation which is not supported by the full authority of the bodies responsible for its enforcement. The Ombudsman in Moldova has the authority to supervise the implementation of the law, but this office lacks the capacity and the resources to exercise its role. Investigative journalists and civil society organisations face numerous difficulties when requesting access to public information, including obstruction by public officials, refusals and delays in replying to requests, as well as incomplete responses to requests for information. To justify their denials, public officials frequently cite laws that conflict with the Law on Access to Information, in particular the Law on State Secrets and the Law on Trade Secrets.

One of the problem in enforcing the right to access public information is impunity, meaning that the law establishes only insignificant fines on public offices who fail to provide due access to information. Also, in many cases, the information provided by state bodies is shaped in the officials' favor, giving the impression that authorities are behaving in compliance with the law, while in fact depriving the requester the information they are seeking. Moreover, in many cases officials do not provide public interest information without the approval from a supervisor and often refuse to answers telephone calls from journalists, thus increasing the time for getting the required information.

Another problem concerns the costs for obtaining public information and the fees charged to the requester, despite some improvements made recently, such as the introduction of a public register through the E-Government service in 2014. This affects in particular newsrooms and investigative journalists that must pay large sums of money for getting data useful for their investigative work.

See also
 Access to public information in Europe
 Freedom of information
 Freedom of information laws by country
 Transparency of media ownership in Europe
 Media of Moldova
 Transparency of media ownership in Moldova

References

Rights
Freedom of speech

redpajama_set_name: RedPajamaWikipedia


ULIP's and Traditional policies both work alike. A part of the premium is set aside for life cover and the rest is invested in a fund after deducting charges.
The main advantage of a ULIP is that the investor knows exactly about the break-up of his premium into life cover, the fees being paid and the amount being invested in a fund. The performance of the funds can also be tracked as the returns are linked to the market performance. On the other hand, in traditional policies, no information about the break-up of charges is shared with the investor. He also does not know whether the bonuses paid to him every year are all that his fund has made or whether the company is giving him only a share of the profits. Policies encourage savings whereas ULIPs take the investment path and hence have higher growth options.


HR KNIGHTS CONSULTING (OPC) PRIVATE LIMITED, passionate HR professionals, who has embarked on journey to be the preferred recruitment service provider to millions of corporate and make a mark on recruitment world.We are the staffing solutioning private company (One Person Company) incorporated on 16 November 2016. It is classified as Non-govt company and is registered at Registrar of Companies, Ernakulam.
Our Corporate Identification Number is (CIN) U74999KL2016OPC047286 and its registration number is 47286. Our registered office is based in Thiruvanthapuram.
As part of preliminary information collection & Know our esteemed customer, we suggest you to go through each section and provide us with the requested details as per the each field requirement.
Information shared through this application should be accurate and any false information provided to us will be considered as disqualification at any stage of the contract agreement.
Information & supporting document shared with us will be kept confidential and documents will be used only for the reference purpose only.


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fogbanking
Developing Organizations
Note: I am writing every Tuesday and Thursday now. I noticed much more Thursday traffic than Tuesday traffic this week…
I am currently barely starting A Thousand Years of Nonlinear History (had a turbulent few weeks- my reading time took a serious hit). I've encountered attempts at historical accounts at a different perspective than human agency, but never one that has succeeded at going so long, with so much detail, without ever using the vocabulary of human interaction as a crutch. I'm too scared to write about the book yet, I'll probably wait until I finish at least a part of it.
This post is about the evolution of artificial things over time.
Forced Moves and Good Tricks
I first read Daniel Dennett's "Darwin's Dangerous Idea" the same summer I read Herbert Simon's "Sciences of the Artificial", maybe six years ago. I generally see those two books as the starting point of my interest that informed my choices of college and majors and prospective career. The vocabulary of cranes and skyhooks and design space and satisficing and bounded rationality are permanently cached away as basic metaphors for understanding how I think about a bizarrely wide array of things. The fact that I haven't mentioned them, several thousand words into subjects where they would've been appropriate, was entirely accidental.
Anyway, I'm starting with Dennett today.
The world of physics is generally described as a world of what can happen, and is meant to be universal. By contrast, biology is more dependent on history, and is therefore more local and exists in the world of what did/does happen as opposed to what could happen. But Dennett also argues that in design space there often exist "forced moves" and "good tricks" that can often be discovered and rediscovered in the right conditions. This is the explanation for convergent evolution, wherein genetically distant species adapt similarly to similar niches across time and space. A "forced move" is an adaptation that is necessary to stay alive in a niche (failure to make a forced move results in extinction). A "good trick" is an adaptation that can be useful in several scenarios that may or may not occur, but would be nice to have if they do (they generally improve resilience). Historical contingency and environment are very powerful drivers in design space:
100 million years ago, when the Earth had its normal hothouse climate and reptiles were the dominant vertebrates, the icthyosaurs, a large and successful family of seagoing reptiles, evolved what we now think of as the basic dolphin look; when they went extinct and a cooling planet gave mammals the edge, seagoing mammals competing for the same ecological niche gave us today's dolphins and porpoises. Their ancestors, by the way, looked like furry crocodiles, and for good reason; if you're going to fill a crocodile's niche, as the protocetaceans did, the pressures that the rest of the biosphere brings to bear on that niche pretty much require you to look and act like a crocodile.
The lesson to be drawn from these examples, and countless others, is that evolution isn't free to do everything that, in some abstract sense, it could possibly do. Between the limits imposed by the genetics of the organism struggling to adapt, and the even stronger limits imposed by the pressures of the environment within which that struggle is taking place, there are only so many options available, and on a planet that's had living things evolving on it for two billion years or so, most of those options will have already been tried out at least once. Even when something new emerges, as happens from time to time, that doesn't mean that all bets are off; it simply means that familiar genetic and environmental constraints are going to apply in slightly different ways. That means that there are plenty of things that theoretically could happen that never will happen, because the constraints pressing on living things don't have room for them.
Keep in mind that "artificial" is a subset of "natural", and that is also true in design space.
Waste/Fertilizer
One interest of mine that has shown through on this blog is "how people organize". I'm interested in how institutions form and why some are generally more successful than others. While these kinds of sociological concerns aren't an exact science, I tend to think of them the same way I think about other past-sensitive subjects like history and biology. There are generally things that have worked in the past that are likely to work again. There are things that haven't worked in the past that could work this time, but that is a much riskier bet. I imagine there exist plenty of "good tricks" that can be mined out of history without necessarily knowing how sociological phenomenon work at an irreducible or "global" level.
There is one more vague, you-get-it-or-you-don't idea I want to air from some of the sources I've been returning to over and over in this blog so far, and that's the idea of older things becoming fertilizer for newer things, subtly changing the environment and allowing for new forms. Even allowing for forced moves/good tricks and the convergent evolution that they appear to make inevitable, historical dependency and environmental pressure are not universal across space and time. Environments are changed by their inhabitants. Organisms consume some things and excrete others, slowly transforming their own world and tuning the environment around them. Stars generate byproducts, too, and when they die they leave behind different stuff than existed before they were alive. Environments change, often in an unpredictable and nonlinear fashion. There may be periods of relative stability before some apparent change occurs suddenly. There is no static natural equilibrium. Older cultures may construct artifacts and ideas and then leave them behind for re-appropriation or re-combination by newer cultures that can salvage what "good tricks" that they discover there, and discard the rest. Living cultures can attempt to steal and copy from each other, as well. Competition is another environmental/historical variable that clearly changes over time, maybe gradually, or maybe in a series of détentes and arms races. The broad point I mean to make before continuing is that just because certain forms may occur and reoccur, they are by no means eternal or inevitable. They are just more likely than other forms that could occur (they are possible) but aren't particularly likely to (because of the constraints of precedent and environment).
One book in the past year that could be read from this [fertilizer/recombination] point of view is Francis Fukuyama's The Origins of Political Order, which outlined the development and combination of three elements of political order needed for a successful modern nation-state, presumably written with the goal of diagnosing states that have taken a different path and are failing (by metrics of human prosperity). The three elements he defines are a strong state, rule of law, and political accountability. He attempts to illustrate how historical contingency has allowed different peoples to experience and recombine some or all of the three elements effectively.
Tribes, Institutions, Markets, and Networks
I want to outline one more framework on this topic, called TIMN (Tribes, Institutions, Markets and Networks: A Framework About Societal Evolution).
All four forms co-exist and existed in some capacity for millenia, but the idea is that each successive form has been (or for Networks, will be) better developed and integrated into our political organizations over time. The earliest forms of human organization were almost exclusively tribal, a kin-ship based organization (T). Tribes are extremely resilient, but there are limitations of scale and stability. Agrarian empires of the ancient world used hierarchical structures to organize larger groups of less-related humans ("not common ancestors but a common ruler") to undergo larger-scale campaigns of conquest and resource allocation in systems we might call "T+I". Markets existed and were influential but were not grappled with and prioritized as political forms immediately. One limitation of "T+I" organizations is that they can't "handle complex exchanges and information flows well", which is especially problematic in the economic sphere. This problem allows for the innovation and maturation of Market organization. "T+I+M" societies arise after the market as a philosophical concept is developed and given a name (and can thus be deliberately manipulated), at the dawn of the Industrial era. Interestingly, other political innovations such as statist communism is treated as a backward development to T+I structures that would never be able to deal with the unique problems that the Market form solves. China's move towards capitalism is almost seen as a forced move in this view.
Yet, despite all its strengths and contributions to the advance of society, the market system has a key limitation of its own: It contributes to creating social inequities, and does not prove adept at addressing them. As in the case of the earlier forms, the sharpening and the recognition of this limitation takes us to the next form to arise.
And so, the paper argues, the byproducts of the Market form are fertilizer for the maturation of a fourth form, the Collaborative Network, enabled by new communication technologies, new languages and philosophies to describe and measure itself, and resources being poured into innovating it in order to address the limitations of the Market form, in the same way Markets addressed limitations of the Institutional form, in the same way that Institutions addressed the limitations of the Tribal form. Networks are flat, polycentric, and ideologically integrated. So the story goes, the Network is the next step forward (barring, of course, a weakened market and a decay in institutional trust causing some sort of regression to more tribal forms of organization, blah blah.)
Basic Underlying Forms. (Click to expand)
Comparison of the Forms (Click to expand)
There are other interesting details the paper considers that I enjoy.
Each form further stratifies society. Tribes loved blood- they have "kinsfolk" as the most crucial rank (you either are or are not) with perhaps a fluid sense of rank by other dimensions (maybe age, or centrality to the clan); Institutions love power- they funnel resources across dissimilar peoples through authority, creating a classes of "ruler" and "the ruled"; Markets love capital- they generate comparative senses of wealth as status, often in the form of the tripartite "upper, middle, and lower class"; we can presume that Networks generate some new form based around information access, and can (the paper rashly presumes!) be defined as a four-class system.
Each form has an unattainable ideal: even tribal societies dealt with markets and hierarchical structures in passing, accidentally. No form is pure. Mature forms have to deal with realities more complex than the abstraction of these forms can deal with. New forms also bear elements from previous forms that can stunt them (clannish relations at the top of institutions, for example).
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While Deontay Wilder prepares for his return to the ring, he and his team don't want to head into negotiations with Anthony Joshua, Eddie Hearn isn't looking to wait around.
Hearn, who acts as the promoter for IBF, IBO, WBA, WBO heavyweight champion Anthony Joshua, wants to establish a set of terms with Wilder's team prior to his December 1st fight against Tyson Fury.
"What I want his legacy to be, which is something he shares, is to be one of the greatest heavyweights of all time, to be the undisputed champion is the ultimate goal, it might happen as soon as April 13," Hearn told Sky Sports on a potential Wilder-Fury showdown at Wembley Stadium.
If Wilder's name is not on the bottom line, Dillian Whyte is next in line for a rematch of his 2015 knockout loss to Joshua.


In 'PM shelves Islamic group ban' (News, last week), we said Hizb ut-Tahrir 'campaigns for Britain to become a caliphate - a country subject to Islamic law' - and is 'banned in Germany, Russia, the Netherlands, Sudan and in almost every Arab country'. We should clarify that, while Hizb ut-Tahrir has lobbied for other nations to become caliphates, its UK wing does not campaign for Britain to become one. The movement maintains that it is not banned in the Netherlands or Sudan. In Germany, HT's public activities are proscribed, but membership of the party is not. This is currently the subject of a legal challenge.
Our TV guide last week illustrated BBC2's The Private Life of a Christmas Masterpiece - The Annunciation, with the wrong annunciation. It should have been Jan van Eyck's; instead, we chose an annunciation attributed to Petrus Christus. Apologies.
Contrary to the answer to question two of round five in Observer Magazine's Christmas quiz last week, 'Though this be madness, yet there be method in't' is said by Polonius of Hamlet, not by Hamlet.
'And so farewell...' (OM, last week) listed deaths during 2006 and included: 'Mary Wimbush, 1 Nov, Archers actor, 81.' However, the actor, who played Julia Pargetter in the series, actually died on 31 October in 2005. Apologies.


This is a heartbreaking yet overcoming and empowering book entitled Frida; about a woman, Frida Gashumba (Umuhoza) ; who found herself in the midst of one of the the World's most heinous crimes ever taken out on humanity, by humanity itself – the Rwandan genocide of 1994. The death toll was estimated at 800,ooo by the UN, this occurring over 100 days. This is a personal story that opens up the readers' eyes to the real life pain that continues in innocent victims' lives to this day; and how forgiveness and love can heal the soul. We do need to forgive, yet we do not need to forget. Frida (a Tutsi) watched as her family were massacred by Hutus with machetes. She was also bludgeoned, thrown into a mass grave and buried. Miraculously, she came out alive…read the rest, you won't regret it.
This is an inspiring true story about a young doctor who was spiritually and emotionally moved by street children in Bolivia. He has shared touching stories from some of these children's lives, and his time on the streets in Bolivia; and how he is now making a positive difference, by setting up children's homes in La Paz, Bolivia. We are so blessed in our country! We can all make a difference, no matter how little it may be, or how insignifcant we may think what we are doing is. Lots of 'Little Differences' can make 'Big Changes' to peoples' lives and the current state of the world. This is a really good read, I encourage anyone who enjoys reading from this genre to check it out.
Kaya, originally named the Bolivian Street Children Project (BSCP), began in 1997 as a volunteer effort initiated by Dr. Chi Huang and sponsored by Park Street Church of Boston. Taking a year off before entering his medical residency, Dr. Huang spent a year in La Paz, Bolivia, coordinating volunteers from a local church to provide outreach services to children living on the streets. If you are interested in donating to the organization which Dr. Chi Hiuang initiated, click on the donation link above!
This is an interesting book, a must read for people interested in science. Doctors took Henrietta's cells without her permission. The cells never died, they are better known as HeLa cells. They are the oldest and most commonly used cell line in scientific research, even today. The HeLa cell was vital in developing the polio vaccine, gene mapping, cloning to name just a few incredible medical research breakthroughs. These cells started a medical revolution and created a multi-million dollar industry, yet Henrietta's family can't afford health insurance, and she is almost anonymous; her physical death has saves lives, her cells live on more than 50 years later. Where's the justice?
What happens when you drop an American family with three small children into the post-Communist chaos of Outer Mongolia? There's a Sheep in my Bathtub chronicles the adventures of the Hogan family as they try to follow God's leading into one of the world's most remote and mysterious enclaves. Disarmingly honest and charmingly humorous, their tale will thrill you and bring tears to your eyes. An intensely personal memoir, this book still manages to pack a powerful dose of missionary insight and Biblical principles for seeing the Church explode into life among peoples that have never even heard of Jesus. Get comfortable. You will not be able to put it down.


What can you do about that mole?
Moles fall within a list of common and benign, meaning non-cancerous skin lesions that can appear anywhere on the skin alone or in clusters. Moles typically appear between early childhood and during the first 30 years of a person's life and it is normal to have 10 to 40 moles by adulthood. Throughout the years, it is not uncommon for moles to undergo slow changes, such as becoming raised and/or changing color, and even develop hair.
Moles occur when cells in the skin grow in a cluster instead of developing evenly and separately throughout the skin. These melanocyte cells are what gives skin its natural pigment, which is why they may darken after exposure to the sun, during the teen years, and during pregnancy.
The difference between the varying dangers of a mole depends on the type. Congenital nevi are moles that appear at birth and are more likely to develop into melanoma than moles that appear after birth. A mole or freckle should be checked if it is as big as the diameter of a pencil eraser or larger and also if it falls within any of the characteristics of melanoma's ABCDEs.
Dysplastic nevi are moles that are larger than average, which is larger than a pencil eraser, and irregular in shape. They tend to have uneven color with dark brown centers and lighter, uneven edges. People with dysplastic nevi may have more than 100 moles and have a greater chance of developing melanoma, a serious form of skin cancer. Any changes in a mole should be checked by a dermatologist to evaluate for skin cancer.
Most moles aren't dangerous, however moles that are of medical concern are ones that look different than other existing moles or those that first appear after age 30 or if they bleed, ooze, itch, or become tender or painful overtime. If you notice changes in a mole's color, height, size, or shape, you should have it properly evaluated by your dermatologist.
Pay special attention to areas of the skin that are often exposed to the sun, such as the hands, arms, chest, neck, face, and ears, because again, melanocytes are affected by the sun.
A mole of concern can be removed in one dermatologist visit. A few moles may require a second visit. Whether it's during 1 or 2 visits, a dermatologist can safely and easily remove a mole. A dermatologist will use 1 of these procedures: Surgical excision: The dermatologist cuts out the entire mole and stitches the skin closed. If the dermatologist suspects that the mole contains cancer, the dermatologist will send the mole to a lab and examined under a microscope to make sure the entire mole is removed. Surgical shave: The dermatologist uses a surgical blade to remove the mole.