Discussion in 'AVE40' started by Justin_ting, Mar 5, 2018.
2. Join the giveaway page to get more enters.
1. Reply me here which items features support you to get a vaping tool?
Squonk, which I suppose doesn't help here, but you asked. Size, small and comfortable. Honest wattage rating, 20700 battery.
3. tag 3 of your friends here.
I love the tesla nano 120 for many of its features such as the soft, normal or hard hit and tesla is a very accurate mod too... I really love it so I'd love this tesla punk... very awesome looking, and let's face it I like steampunk.
Very nice I have the tesla nano 120w I love that mod. I like the size of this one and the centered 510.
Adjustable wattage,power level,and looks,it has to look good too haha.
Post # 1. Reply me here which items features support you to get a vaping tool?
Post #2: Join the giveaway page to get more enters.
Although I have "Liked" your FB page . . .
Just as an FYI: Sorry to say this type of entry is Not applicable, since it is against ECF Contest rules . . .


Are GF fab sizes the same as intel though or do they exaggerate? I think latter.
There is still debate as to whether 5nm is feasible.
A lot of node naming is total BS. That article explains why.
You cant really go by a single number when it comes to ANY computer performance either. FLOPS is not enough, and when it comes to supercomputers this is especially true. HPL is not enough. HPCG and HPL and the ratio of performance of HPCG to HPL gives you a decent idea of a systems performance.
When assessing a node, however many nanometers they pretty much arbitrarily decide to name it is not a real indicator of anything at all though.
Some guys on forums thought that AMD being 14nm meant it would be "better" than NVidia at 16nm. I tried to tell them that there is no correlation, and that the time spent to optimizing the process is now the indicator of quality (read: you know how it performs once it is running).
That's a difference in architecture NOT process. The Apple A9 chip in 14nm Samsung form is a smaller die and has slightly lower power than the same chip made on TSMC 16nm.
If you calculate the gate pitch(distance between gates) and other gate geometry features, one 14nm process node can be different from another 14nm process node. but what gives the 14nm, or 16nm/other nm##, is its actual gate size and total gate geometry in three dimensions that makes a circuit able to use less power and have the better performance features. So a 14nm gate size with a larger pitch is still going to be the same 14nm gate size than a 14nm gates size process with a smaller gate pitch, the only difference is the one with the smaller pitch is going to be more densely packed with more circuits per unit area.
Apple's 14nm GF/Samsung process gate size is smaller than TSMC's 16nm gate size so the power usage on the 14nm process is going to be less, and Intel's 14nm process is in its second generation finfet stage with the actual Fins taller and a better overall gate contact surface area for better circuit features than the others 14nm gate processes. The circuit doping recipes are different so the various proportions of elements used may also be slightly different process to process.
The actual design(Automated mostly) libraries for any processor can also be different with some processors like GPUs made using high density designs libraries with the metal traces packed closer together on more layers allowing the circuits to be more densely packed. But for GPUs this comes at the cost of GPUs only able to be run at lower clock rates relative to CPUs that are laid out using low density design libraries that allow for less circuit density but more clock speeds relative to GPUs.
AMD did some creative engineering with its initial Carrizo CPU cores that where only going to be used for mobile usage and clocked lower anyways. AMD did this by using the GPU style high density design libraries in the layout of Carrizo's cores at 28nm, and this allowed for a 30% space savings for each Carrizo core while still using that very mature 28nm process node. So the Carrizo APU had more space available for more GPU/other resources and allowed AMD to get more circuits on that 28nm process without having have a process node shrink.
The good thing about this for AMD is that maybe for a Zen Mobile SKU that will not be clocked as high as a desktop/server Zen part AMD could still utilize the GPU style high density design libraries on a 14nm Zen mobile/lite core at get 30% space savings on top of a 14nm process node shrink space savings and get a low power/mobile Zen based APU with even more GPU/Ace units while having the whole part more densely packed with circuits, and mobile parts are going to be clocked lower anyways so why waste space using low density design libraries if the clocks are going to be lower to begin with.
"Some guys on forums thought that AMD being 14nm meant it would be "better" than NVidia at 16nm"
AMD's 14nm GF/Samsung process is not as mature as TSMC's 16nm process, and besides that AMD's GPUs at 14nm have more compute so that is going to be the reason for the higher power usage metrics, and not so much related to the 14nm process node being able to use less power than 16nm. 14nm gates use less power to be switched, but if the processor has many more transistors in active use for compute as AMD's GCN GPUs do then it's AMD's overall GPU processor design and not the 14nm GF/Samsung process that must be taken into account for the power usage metric. I like that AMD designs their consumer GPU SKUs to have more compute relative to Nvidia, as Nvidia's consumer GPU SKUs are not as good for some compute workloads, and Nvidia users will pay through the nose to get that extra compute by being forced to purchase Nvidia's very very costly pro GPUs to get more compute.
P.S. Nvidia has to overclock their GPUs to get the same numbers of FLOPS relative to AMD's lower clocked Polaris parts, so AMD's Polaris SKUs have more transistors dedicated to compute so that is where the power usage comes from. You can get 2 RX 480 for around $500 and their compute will match a $1200 Titan X(Pascal) SKU's total flops provided the Titan X is not using boost mode. Also if the 2 RX 480s are overclocked then they will match the Titan X(Pascal) boost mode even though the 2 RX480s are clocked lower relative to any Nvidia Pascal SKU!
AMD's gives more compute circuits for the dollar that Nvidia does and AMD does this on their consumer SKUs, so AMD's customers who use GPUs for other compute uses get a much better deal, GPUs are not all about gaming, but even for gaming that extra GCN compute is going to be used with DX12/Vulkan optimized games, and VR games!
Is that peak or max FLOPS? FLOPS has long been a useful performance indicator, but it really isn't anymore. This is especially true for gaming and supercomputers.
As systems get larger, having tons of FLOPS, even max FLOPS and not just peak theoretical, means less and less.
Memory and interconnects are the main bottlenecks in large scale supercomputers. Take the K computer for example. It is "only" 10 PFLOPS or so, but it still beats the 100 PFLOPS Taihu Light system and is #1 on Graph500.
Why? Its architecture is far better, despite being 5 years old. It has 93% computational efficiency, and one of the closest in HPCG to HPL ratios.
http://www.nextplatform.com/2016/06/21/measuring-top-supercomputer-perfo... see the graph and its explanation.
When it comes to gaming, color compression and other techniques that effectively allow GPUs to get away with lower memory bandwidth or FLOPS make that single number relatively useless. Nvidia makes three different GPUs that have about 10 TFLOPS SP, but for very different workloads(GP102 and GP104 are more similar than either is to GP100).
I havent looked at the specs for some of the AMD GPUs youre talking about, but DP FLOPS usually arent cheap, even from AMD.
DP flops are mostly used on Both AMD's and Nvidia's Pro/HPC GPU variants, but for consumer SKUs those AMD RX 480 SKUs offer up plenty of 32 bit FP flops for the around 250$, or lower per GPU costs. So that is why the coin miners always liked AMD more until the coin mining ASICs became available. So if you want to get Titan X(Pascal, at $1200) levels of FP(32) performance at lower clocks the RX 480 in a dual configuration is the way to go for $500 as that will get roughly the same numbers of 32 bit FP(SP) flops, for 32bit workloads.
Render farms with 2 or 4 RX 480s per board are a bit more affordable than Nvidia's higher cost solutions, and wait for Vega, and maybe some more Polaris variants. Maybe AMD/AIB partner could really make a Dual RX 480 GPU single PCI card variants and make some sales for single board options before Vega gets here in volume, and I'll bet they could get some home render farm business from a Dual RX 480s on single card solution. Non gaming graphics rendering for low cost in Blender(Cycles/other rendering on the GPU not the CPU) would be one reason to go with the RX 480, so 4 RX 480s at around $1000 would have 32GB of V-memory and twice the 32 Bit FP compute as a Titian X(Pascal) in which to accelerate the Ray interaction calculations for some very high resolution animation projects.
I'm waiting for Zen to arrive and AM4, or I'll even be looking at some single socket Opteron options if that means getting 16 Zen cores at a more affordable price than Xeon. But what I am really hoping that AMD will do at some future point is to begin to offer in shaders(hardware optimized for ray tracing) that can run full Ray Tracing algorithms without the need for any CPU assistance at all, so GPU users can be totally free of any CPU dependency for any and all Ray Tracing workloads for graphics uses. OpenCL Ray Tracing acceleration is good but not as efficient as doing Ray Tracing with a Ray Tracing ASIC block on the GPU or even on a dedicated Ray Tracing ASIC card.
Color compression is fine for gaming, but not for non gaming rendering unless it is totally lossless compression, and FPS does not matter for animation rendering, that is more or less not a concern for graphics(Non Gaming) rendering as the more Rays Traced mean better animation frame quality with realistic shadows, and AA/AO and reflection effects. Animations are going to be run at a constant rate after the frames are generated and its mostly single frames per minutes rendering for animation rather than the FPSs for gaming at Gaming's lower quality low resolutions. So the more 32bit Flops to accelerate the Ray Tracing calculations the better for animation rendering, and the RX 480 has plenty of 32 bit FLOPS for around $250.
Imagination Technologies' PowerVR(Wizard) GPUs have specialized Ray Tracing hardware on their GPUs with the IP, so that IP looks very interesting. I wish that some of that PowerVR wizard Ray Tracing IP would be adopted by Apple for a real Pro Graphics tablet SKU, and Apple sure needs to be focusing on some niche graphics oriented Tablet SKUs now that Tablet sales are like PC sales are not growing fast anymore, PC and Laptop sales are actually shrinking for the OEM market. Apple appears to now only think of its Tablet/Phone hardware and its laptop hardware more as portals for its online services and not really as functioning Tablet/laptop computers. Once AMD finally get out of its slump with Polaris, Zen, and Vega, maybe they can build a Reference Tablet with a Optimized 4 core Zen/Polaris low wattage APU, with the Zen cores taped out using High density design libraries for more Zen cores in less space.
I'm also very interested in the AMD K12 custom ARMv8A ISA running cores, as AMD could maybe go with a 6+ instruction issue custom AMD designed ARMv8A ISA running core, like Apple's A7, and maybe add SMT capabilities to K12 and get even better overall CPU core execution resources utilization from K12 than even Apple and really make and AMD custom ARM ISA based tablet APU that would have plenty of Polaris ACE units. AMD appears to have under Jim Keller designed Both Zen and K12 in a similar fashion with both Zen's X86 based cores, and K12's ARMv8A ISA cores having similar Caching systems, and other features and maybe even both having SMT capabilities, and SMT for an ARMv8A ISA custom core would be a first, if that is in fact what Jim Keller has done while overseeing both Zen's and K12's design teams.
With an HSA APU, it will be much lower latency to share work between the CPU and GPU components, so more specialized hardware may be unnecessary.
HSA only does something bebeficial if the fact that the CPU and GPU have a bottleneck and much like all the hype around asynchronous compute its bebefits are wildly overblown.
You need HMC/HBM and enough nonvolitile memory that is fast and close by for exascale, in order to support the fast checkpointing that exascale requires.
A lot of specialized hardware like FPGAs and ASICs exist because they are much better than CPUs or GPUs for certain tasks, which has nothing to do with CPU to GPU communication latency.
in case of mining it is not because of radeon have better peak compute performance. but simply the mining program works better with how AMD architecture are built. this has been discussed a lot in the past. high FLOPs numbers are useless if they can't really use them efficiently.
comparing compute performance(FLOPS)between AMD and nvidia is useless. if they represent real world performance why Fury X are not significantly faster than 980Ti? they said polaris is better than pascal because low clock polaris can match high clocked pascal but they forget that in case RX480 vs GTX1060 the latter also have much less shader cores compared to RX480. and look no further than top500 numbers if you want to know how efficient actually AMD designs are. look at SANAM (one of the super computer powered by AMD accelerator). they got impressive "theorical" peak performance but when running real application they can only get 50% from that peak performance.
also when it comes to VR it seems AMD have no definite advantage like many said it was before. actually even maxwell based card perform just as fine in VR.
Thanks much for this incredibly illuminating and instructive post. i assume the p.s. and the other post that followed that by Anonymous are also yours. They add a bunch more very useful insights and information. Thanks again.
In the past when Apple was manufacturing A9(?I think) at both Samsung's 14nm and TSMC's 16nm many sites where trying to see which was faster and more efficient. Some sites where showing Samsung's better, other TSMC's better.
Heh yeah i remember reading those articles. I think we did one on battery life between the two though in cant recall which one won.
Yeah part of the problem, as I understand it, is that there is no standard for naming among all the various fabs as far as process nodes and what part of the chips they measure to determine what nanometer they say their node is at. It is pretty confusing comparing across fabs and generations... and then marketing murks it up further (e.g. flash memory is "Xnm-class" heh). Aren't Samsung's 14nm FinFET and TSMC's 16nm closer in size than the Xnm numbers would suggest? I've been on vacation and can't remember off hand sorry :).
I will give that article a read later, I could use a refresher esp. since JoshTekk is gonig on vacation soon now hehe.
Im not sure about those specific nodes, but what it really comes down to is who has the overall better process and architecture overall.
The process is determined by the EDA that goes into it, the testing and refinement, and moost of that depends on machines that NONE of the fabs themselves make, but are rather created by what is likely the most technologically advanced company on Earth: Applied Materials.
Im pretty sure that all the fabs are using machines made by Applied Materials. I might be wrong about that, but Im fairly sure thats the case.
A lot of the node names are marketing, but it would be hard to sell chips, even to hyperscalers, without some easy reference naming scheme. Talking about bending light with resolution enhancement technologies and creative mask design doesnt resonate with consumers typically.
I havent read many details about the latest processes but it SOUNDS like AMD has something good with Zen and the node theyre using with that.
On a side note, i think that focusing too much on one thing, like the nanometer name of a node, is detrimental to the market overall. It allows for marketing to drive sales, rather than actual good product designs.
The problem in terms of computer performance right now, from a desktop to a pre exascale 100PFLOPS supercomputer is not really the size of the transistors. Its the fact that there are so many bottlenecks between CPUs and other parts of the system. In the case of desktops, thats CPU to RAM, GPU or storage. In the case of a supercomputer, its CPUs to RAM and other compute nodes or accelerators.
Fortunately some people have realized this and we are seeing the adoption of HMC, HBM, XPoint and NVMe NVMf etc.
Wait for AMD's HPC/Server/Workstation APU's on an interposer SKUs that will be the $/flops, Power/Flops, leaders that will have the widest parallel connection fabrics etched out on the interposer's silicon substrate. What AMD will be doing for the exascale computing market will be putting the connection fabric for CPU/GPU/FPGAs/DSPs on an active interposer and wiring up all these processors and HBM2 via the interposer and thousands of traces. Just Look at what AMD's Fury X SKUs are doing with HBM to GPU connection traces, and all that will be needed is to add some Zen cores with their own wide parallel traces from the Zen cores die/s to the Greenland/Vega GPU die.
Navi will be made up of modular GPU dies and HBM2 on an interposer. AMD will even be putting an FPGA compute die in the HBM2 memory stacks, see AMD's patent filings, so there can be dedicated distributed compute on some of AMD's HPC/Server/exascale SKUs, and all the wide power saving low clocked high effective bandwidth interconnects for the GPU, CPU, DSP, HBM, other dies will be etched on the interposer's silicon substrate. Interposers will be etched with active circuits instead of just passive traces so expect that at some future time that interposers of the future will have completely functioning fully coherent connection fabrics like multiple ring buses or complex butterfly/doughnut connection topologies etched into the interposer's silicon to wire up some every powerful power saving APU designs for complete systems on an interposer for the exascale market.
The power savings from having an interposer etched with thousands of traces is great and allows for much higher effective bandwidth to be sent at lower clocks over very wide connection fabrics, so for exascale computing's strict power usage regimens the interposer based APU/SOC will be very attractive proposition. U-Sam is offering billions in grants to get its exascale computing initiative going and get some exascale systems up and running by 2020-2024, and the power usage on any exascale system in measured in the megawatts, so there will be a big intrinsic advantage for some APU/SOC systems integrated on interposer, or MCM modules, with their Own CPU/GPU/Other compute in a more localized area with plenty of HBM2/NVM right on the HBM2, or on the MCM module, to keep the power usage from excessive data transfers down to a minimum. So some FPGA compute right in the HBM2/other memory and GPU accelerators/other accelerators right on the interposer, or MCM module will be what is used to make exascale computing practicable and possible.
Expect that all those government grants for the exascale research to lead to the same technologies being used for the consumer market, what with the government grants paying for most of the R&D for the exascale systems that the government needs. So just like that Apollo program that government sponsored R&D found its way quickly into the consumer market.
This isnt the same economic or political climate that put humans on the Moon. I think its proabably a good thing that the government is attempting to keep the US competetive in the race to exascale, but I really doubt that the USA, Europe or China will be first.
Much like the Earth Simulator and K showed the world the most advanced architectures and highest real performance, i think the Japanese will be the first to make a useful exadcale computer.
For one thing, they have had the most advanced pre exascale architecture available and in use since late 2014.
That is the successor to the K and FX10, which scaled to 10s of PFLOPS. FX100 scales to over 100 PFLOPS. It has been using HMC on its CPUs since 2014, while Intel, AMD and Nvidia were hyping up their still basically nonexistent HBM and HMC offerings.
Here are a few other things the Japanese have in their favor. They just bought ARM. And not long after, they announced the switch from SPARC to ARM for the Post K computer, which will be 10x the performance of FX100 and 100x the performance of K, or one exaflop.
Intel or AMD may be able to catch up, but i doubt they will. Its funny that most people dont think of Fujitsu as making the most advanced supercomputers, but they currently do. Not even the 100 PFLOPS Taihu Light can beat the ancient K in the Graph500 rankings, and Fujitsu's current architecture is a 32+2(for the OS) core homogenous CPU only with 1 TFLOPS DP 2 TFLOPS SP, 480GB/s HMC and an interconnect that allows for scaling to thousands of nodes with >90% computational efficiency.
First does not matter, It's getting APUs/SOCs on interposers with HBM2 available for the consumer market at affordable pries because U-Sam/other Sams need those exaflop computers for whatever! With U-Sam footing the bill for a lot of Interposer R&D, HBM2/next gen HBM, and FPGA compute on the HBM2/whatever stacks, and other technology that gets used in the consumer market quicker because of any government R&D funding. Hell, it could be the Chinese/French/Russians government grants, for all I care, as long as AMD/others get the grants and that technology gets into the consumer SKUs sooner rather than later. I do not care why/what they need the exaflops for as long as AMD/Others are getting the grants to Fund the R&D that will improve the consumer SKUs the quickest.
I want my laptop to have 8 Zen cores and a big fat Vega die and 32 GBs of HBM2, and some FPGA(On the HBM2 stacks) programmable compute for any new Vulkan API features not yet implemented in the Vega GPU's ASIC at the time of its release.
You do realize that all of those technologies currently exist and are in use right? HBM2 on interposers exist in GP100, Altera and Intel make FPGA parts that use EMIB which is better than interposers already.
Government grants are also not really necessary for the R&D. Its more for building a massive exascale system that you need a billion dollars, a lot of which is from private investments.
You forget that consumers dont drive the market for computing, with the exception of mobile chips either.
Then you have not been reading about the government exascale initiative and current Interposer usage is limited to GPUs and HBM using passive interposer designs! The real government research at the university/private enterprise levels of the Exacsale research will go into developing active interposer technology and complex on interposer interconnect topologies to keep as much work happening on the interposer module and its various CPU/GPU/HBM/FPGA and other specialized processor components including some form of NVM to keep the large data sets local to the interposer/module compute as much as possible to save on power usage. Interposer technology is expensive because of the current limited use of interposer technology is not good for the amortization of that interposer R&D so that is why Interposers cost too much currently, to pay for the R&D costs. More government grants for university and private R&D will be spent on the development of better and larger interposers and more efficient/power saving interconnect topologies that will allow for the power savings that the exascale power usage regimens require.
AMD has already submitted an Exascale APU proposal using 32 Zen cores and a large Greenland/Vega GPU on and interposer including HBM2 and some FPGA compute on the HBM2 stacks. Silicon interposer technology is still passive in nature so the R&D will mostly be for getting the costs of interposer production down and developing the active types of interposers with fully functioning interconnect networks on the interposer that have all the circuitry to manage the interconnect etched into the interposer's silicon. AMD is not the only one getting the grants, as Nvidia, Intel IBM, and others will all have their proposals and get some R&D grants. As far as the power saving needs of the exascale program go, a whole lot of that government funded R&D will find its way into consumer PC/Laptop products down to Tablets and phones, because using interposer technology and HBM/other memory technology as well as NVM in the DRAM technology will save plenty of power, as computing needs are going to put a stress on the whole world's power production capacity.
All the funding for government exascale R&D is there to apply for and will help with getting the power usage down and the Gflops/watts metric as efficient as possible, and just like IBM, Burroughs, Univac, and others benefited from Federal/Government mainframe R&D grants/contracts in the past for technologies that where used it the business side of computing, the Current companies that make processors will benefit also from the Exascale R&D grants with that technology being used in the business/consumer markets.
Modular and scalable GPUs are going to be made using interposers to wire up smaller more affordably fabricated GPU dies with higher yield efficiencies into larger and more powerful GPU systems that will appear to any software as a single GPU! Ditto for big fat APUs/SOC on an interposer made from separately fabricated CPU dies, and separately fabricated GPU/FPGA/DSP other processor dies and HMM/NVM(XPoint/other) dies using Active Interposers with whole coherent connection fabrics/circuits etched into the interposer's silicon substrate.
Actually i do read about it, and i also post about exascale topics on www.nextplatform.com a lot.
Ive read about AMDs exascale architecture. I dont think its as promising as Fujitsu's.
I don't see EMIB as being superior.
Oh and i forgot to mention that K and its AICS run by Riken cost $1.3 billion and they have set aside over $1 billion for Post K. Thats just for the computer and facility upgrades. Their overall spending on HPC and AI is huge. Japan also has HPCI, something much more coherent and cooperative than anyone else from what i can tell.
I'm honestly surprised something like "Extreme Ultra Violet Lithography" isn't more of a hyped thing. I get that science never gets hype, but the fact we're carving things with lasers that are so minute in scale we're almost at single digit nanometer wavelengths? :X definitely mind blowing!
Because its not in use yet?
Global Foundries don't really need 10nm, they have 22nm FD-SOI (22FDX), which should be as cheap as 28nm for design/production, about as low power as 10nm FF, and more than fast enough for mobile/IOT.
Sure, 'flagship' phone/tablet SoCs will probably go with 10nm. But GF will probably hoover up the rest. As ultra low power *and* cheap is going to be very popular.
AMD will do what Nvidia is already doing. They will go to Samsung. They are already testing Samsung's manufacturing, but they are behind Nvidia who are already getting ready to produce at least one GPU at Samsung(1080Ti?).
Look PCIe 4.0 and OCcLink external PCIe cables, and 300 Min Watts power on the PCIe connector.
"PCI Express 4.0 Brings 16 GT/s And At Least 300 Watts At The Slot"
That's OCuLink for 32Gbs in each direction for external boxes/etc. with a 4 lane connection!
Hot Chips starts today 8/21 and runs throug 8/23! 2016 and beyond is going to be fun at lower costs for some x86 with SMT cores from AMD! Man dig them crazy Threads, and they easy on the wallet!
More juicy details for that "New, High Performance x86 Core Design from AMD"!
GF is, as always, late with the next process iteration so they announce future plans to divert shareholders attention.
GF is licensing/using Samsung's 14nm process. And IBM, Samsung, GF have been in a chip fabrication technology IP sharing partnership/foundation for some years now! You do see that IBM is using GF for its fabrication needs. IBM licenses/transfers(In limited amounts) a lot of Chip Fab IP to its technology sharing partners. It costs Intel Billions to maintain its chip fabs, so even Intel is doing limited third party chip fabrication business. GF/Samsung/IBM, and others, have plenty of billions to spend for R&D to catch up to Intel and get down to 7nm even faster than Intel, and it's more about the costs of doing so than any special ability on Intel's part. There are about 6 companies world wide that supply the majority of the Chip Fabrication equipment and other IP to all the Chip makers, and Intel did not invent FINFET and a lot of that 14nm process from Intel is licensed from Universities/other IP sources.
GF worked on their own trying to come up with something better then their 28nm and failed miserably. Lucky for them, Samsung come up with 14nm and was willing to license the process. Seems like GF is again hoping for miracle to save them.
IBM had something to do with GF getting a license to use Samsung 14nm process, what with IBM just about gifting to GF IBM's foundry business. Both GF and Samsung will be in line to get some Power9 business from IBM(After GF's agreement with IBM expires) and the third party OpenPower Power9(Google others) licensees will be open to choose GF or Samsung. IBM is ONLY interested in keeping the Power ISA and Power IP going and growing, thus assuring IBM of more software/services penetration in the Power8/Power9 marketplace, and a supply of Power8+/Power9 parts for IBM's needs. IBM retains all of the Power IP that can be licensed to any OpenPower Licensee, IBM also retains all of its world class research facilities, including chip fabrication research facilities that IBM and its partners(GF, Samsung, others) will use to create a ready supply of advanced fab capacity for the OpenPower hardware ecosystem.
P.S. The Power9 processor will be revealed at Hot Chips this year along with AMD's New x86 High Performance CPU core design, and other new CPU/GPU IP like ARM Holdings'(SoftBank) new Bifrost GPU micro-architecture ans A73 cores, etc!
ARM is adding variable 128 up to 2,048 bit SVE to the ARMv8A ISA! Man I hope that AMD's K12 gets some of that.
"Hot Chips ARM is bolting an extra data-crunching engine onto its 64-bit processor architecture to get it ready for Fujitsu's Post-K exascale supercomputer.
"Little ARMs pump 2,048-bit muscles in training for Fujitsu's Post-K exascale mega-brain"
I can see such vector extensions being good for HPC, but not necessarily for consumer systems. They need to skew the front end towards high bandwidth at the cost of latency to support such units. For consumer systems, it is generally better to execute such code on the GPU (at higher latency) than to optimize the system for keeping such units fed on the CPU. HSA systems with a single pool of memory will reduce the latency for going out to be GPU significantly. This is similar to when the FPU was a separate, optional chip with high latency. Now the FPU is tightly integrated into the CPU.
Its for Fujitsu's Post K exascale computer.
"Noch mehr Offizielles zu Zen: Architekturdetails und Benchmark gegen Core i7-6900K [Update]"
Do we really expect 10 nm to be that much better than 14 nm? EUV has been talked about for so long that it is unclear whether it is even commercially feasible. I don't know how much of a gamble it is since what are the other options? A highly tweaked 14 nm process might be very close to a 10 nm process. The defect rate on 10 nm without EUV may be really high, so not going to EUV could be considered a gamble also. Scaling after 10 nm is not guaranteed. There could be another long wait for process improvements in the next few years.


We all know haroset. We all love haroset. And, come on, we all think that OUR family's haroset is the best, no? The Ashkenazim (at least here in the USA) tend to make theirs with chopped apple as its base, adding walnuts, cinnamon, a little sugar, and sweet wine, while the Sephardim generally use dates as their base, with cinnamon, wine or even vinegar, and perhaps apples or dried apricots depending upon the region. But what is most interesting to me right now is how many names exist in the Sephardic and Mizrahic (Middle Eastern) world for this sweet Seder treat. In Israel the spelling and pronunciation is "charoset" with a more guttural "ch" sound in place of the softer Ashkenazic "h" sound. In speaking with several individuals with Turkish roots the Ladino spelling "harósi" or "haróse" has been most common (although in a recipe by Elsie Menasce from South Africa, she spells it "jaróse" with a "j", which I have been told is more Castillian). Yemenites and Persians refer to it with a different name all together: "dukah" or "dukeh" (which supposedly means "pounded" or "ground" in the Yemeni Arabic dialect). But when the consistency or style of the haroset changes from that of a thick purée or paste to that of a syrup (made of dates to the texture of honey or molasses) the names become the following: "silan" for those originally from Baghdad, or mysteriously changes to "halech," "hallaq," or "halék" for those Baghdadis who later settled in parts of Asia, such as Singapore, China, or India. While looking through a Bukharian cookbook I noted that the charoset recipe was called "haleko" which makes me think that the word comes from an Asian/Central Asian root of some sort. In Curacao, the Sephardim (who have Dutch roots via Portugal) call their haroset "garosa." My latest discovery was the word, "aropi" from a community cookbook by the Sephardi Ladies of Zimbabwe. In old Greek the word is "sirópi" which sounds pretty close but with the initial letter "s". I can see the relationship between this spelling and the word, but have yet to really pinpoint the language.
Has anyone else heard of this spelling "aropi" to refer to any kind of syrup?
How do YOU say charoset in your family or community?
That's so interesting, thank you for the information about silan Nawal!
You asked about the word aropi for syrup. In Spanish the word is "jarobe" so there is a similarity. Perhaps that is how it developed.
Yes, thank you Eileen. I am guessing that aropi is an older word that jarobe derives from.


The Battle-Ready Game Show is a multimedia presentation that explores the entire 4500 year curriculum. It utilizes hands-on elements as well as physical activities and artifact exploration to give a wonderful understanding of this complex and diverse curriculum. Every early society is explored including Mesopotamia, Egypt, Greece, Persia, Rome, Indus Valley, China, Mesoamerica, the societies of the Mediterranean sea, Japan, the Vikings and the Medieval period.
This session also includes an optional archery demonstration where a select group of lucky students are selected to try our custom made bow while under strict supervision. This is available at no extra cost.
The Battle-Ready Game Show culminates with our two instructors dressing in reproduction armour and conducting a historical martial arts demonstration.


Meet the tag*a*long, a simple, fun way for kids to walk comfortably next to a stroller or Shopping Trolley.
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New Release Review [Shudder] - THE MORTUARY COLLECTION
A teenage girl coerces her town's mortician into telling grisly stories.
Review by Eric Hillis
Directed by: Ryan Spindell
Starring: Clancy Brown, Caitlin Custer, Barak Hardley, Christine Kilmer, Jacob Elordi
The Mortuary Collection is that rare horror anthology in which the wraparound segment is more engaging than any of the featured stories. That's down to the presence of actor Clancy Brown, who lends the wraparound a level of star power and presence absent from the tales spun by his character, Montgomery Dark, the mortician of Raven's End, a small weather beaten town that appears to be stuck in a hipster's vision of the 1950s, all Westinghouse tube TVs and rockabilly on the radio.
Following the funeral of a small boy, Dark is approached by Sam (Caitlin Custer), a smartass teen who wants to apply for the advertised position of his assistant. Suspiciously fascinated by his profession, Sam coaxes Dark into relating stories of how some of his "clients" ended up on his slabs, and thus the tales are unspooled.
First up is a brief single location story of a female thief (Christine Kilmer) who retires to a bathroom to empty the wallets she's just pickpocketed at a high society party. Something is waiting for her behind the medicine cabinet however.
[ READ MORE: New Release Review - Ravage ]
Next is the highlight of The Mortuary Collection's stories, which takes us to Raven's End's local college. There we meet Jake (Jacob Elordi), the fraternity's house stud, who has claimed the virginity of 66 female freshman students by spinning them a load of guff about his feminist sympathies. The 67th notch on his bedpost is the mysterious Sandra (Ema Horvath), who turns the tables on Jake when he refuses to wear protection. This one has an effective sense of place, a timely bit of social commentary and a memorably gruesome twist. It would work perfectly as an episode of Tales from the Crypt, a show to which The Mortuary Collection owes quite a stylistic debt (did I hear its theme tune referenced in Mondo Boys' score here?).
The last of Dark's tales introduces us to Wendell (Barak Hardley), a devoted husband who has committed himself to looking after his wife, Carol (Sarah Hay), since she entered a catatonic state on their wedding day. The toll of caring for Carol finally catches up with Wendell, who follows the advice of his doctor (Mike C. Nelson, who plays the character across three segments) in slipping untraceable but deadly pills into her gruel. Wendell's plan to mercy kill his wife doesn't go off so smoothly, and he finds himself attempting to dispose of a bloodied corpse. This one fails to live up to the darkly comic potential of its premise. There should be more uncomfortable laughs from Wendell's haphazard attempts to remove his wife's bloodied corpse from their apartment building without getting rumbled by his neighbours, but the initial tone of the short is too sober for the gags to ultimately land as easily as intended.
[ READ MORE: New Release Review - Saint Maud ]
After Dark tells his three tales, it's the turn of Sam, who it turns out has a story involving herself. I won't get into details as the segment is played as a twist, but the final story initially sets itself up as a homage to '80s slashers, and I was disappointed when this turned out to be a fake-out, instead evolving into a rather generic battle between a babysitter and her potential killer. If you've seen director Ryan Spindell's 2015 short The Babysitter Murders, this will be familiar to you.
Given the brevity of the first tale and how the final segment ties into the wraparound, The Mortuary Collection really only offers two substantial standalone stories. The mercy killing segment suffers from serious pacing issues and could really have been told in half the time, allowing for another story to make anthology devotees feel like they're getting their money's worth. At close to two hours, The Mortuary Collection is guilty of dragging in places, and only its college set story uses its running time efficiently.
The Mortuary Collection has the feel of a pilot for a '90s cable show that failed be picked up by a network. If that were really the case it might have value as a curiosity piece for portmanteau fans. But as a standalone feature it plays too much like an origin story to satisfy as a complete movie in its own right. That said, Brown is such a compelling presence as Dark - a sort of affable cousin to Angus Scrimm's Phantasm 'Tall Man' - that a TV series could well be spun off from The Mortuary Collection, which may be more pleasing in 30 minute episodes than the rambling feature it presently exists as.
The Mortuary Collection is on Shudder from October 15th.
Labels: By Eric Hillis, horror, New Releases, Shudder, VOD

redpajama_set_name: RedPajamaCommonCrawl


text:
Иккинг () — коммуна в Германии, в земле Бавария.

Подчиняется административному округу Верхняя Бавария. Входит в состав района Бад-Тёльц-Вольфратсхаузен. Население составляет 3690 человек (на 31 декабря 2010 года). Занимает площадь 16,99 км². Официальный код — 09 1 73 130.

Население

Примечания

Ссылки
 Официальная страница

Города Баварии

redpajama_set_name: RedPajamaWikipedia


The folks at Modiphius have blessed us with a great gaming system. But who are gurus who come up with these astonishing adventure systems?
I will have to admit, to track down Nathan was an ordeal taking me places I never thought I would have to go before. After months of painstaking search, I ended up on the most remote inhabited island in the entire world, Tristan da Cunha. It is over 2,000 miles away from South America and 1,700 miles away from the nearest coast of South Africa. Only 297 people currently live on the volcanic island and it's only reachable by a seven-day boat ride through hammerhead shark-infested waters. By the time I completed the ten-hour march through snake-ridden bush and forest, I found myself at a small village situated on the edge of a steaming volcano. The sulfur in the air mixed with the herby aromas the locals used to cook their bushrat meat. Nathan was having his hair braided by two tan-skinned native women while showing the loincloth-bearing kids how to play Star Trek Adventures.
Holding back his mild annoyance at my unexpected interruption, Nathan granted me ten minutes (or "twenty intervals" as he put it) for an interview as the smoke from the rat roast stung my eyes. I was not offered an overnight stay.
Nathan: I've been part of Modiphius for a few years now. I'd heard in conversations with Chris (Birch) that we were looking at the rights to a Star Trek RPG a while before it was all confirmed. I'd already brainstormed a number of ways I'd approach the game. When I was told that it was going ahead, I started work immediately turning my notes into a draft ruleset.
Michael: Wow! This is the second time that I heard a conversation with Chris Birch turned into STA history. (Making a note in a leatherbound journal to hunt for Chris Birch next.) What is your role at Modiphius?
I'm the 2D20 System Developer, so it's my job to oversee the RPGs that use the 2D20 System and to design additional elements for games to suit their specific genres and settings—like rules for cavalry in Conan, or Hacking and Vehicles in Infinity—as well as providing answers to rules questions. With Star Trek Adventures, I designed and wrote the version of the rules that the game uses, and interacted with the community during the playtest, making changes and amendments to the rules based on community feedback.
Michael: That's hella dope. It sounds like a lot of detail-oriented work. What is your favorite part of the Star Trek canon? Why?
Nathan: I started watching The Next Generation as a kid, so it (and the shows that followed) have always defined my view of Star Trek. With recent rewatches of the whole series—it arrived on Netflix just as I started work on Star Trek Adventures—I was provided with abundant "research material". It's cemented Deep Space Nine as my favorite of the shows, for the depth of story and character development it provided.
In a broader sense, I've always loved the technology of Star Trek. I pored over a copy of the TNG Tech Manual as a kid to the point where the binding fell apart and the book disintegrated and spent many an hour doodling my own classes of starship.
Michael: Haha! That's great! Who is your favorite character in Star Trek? Why?
Nathan: The Enterprise-D. The ships are characters too! In seriousness, I'd struggle to pick just one character, because it's their interactions that make the shows: Kirk doesn't stand out as much without Spock and Bones at his side; Data isn't the same without Picard's guidance and LaForge's friendship; Sisko is defined by his relationship with his son and his friendship with Dax.
But no one character is quite as memorable as Garak. Plain, simple Garak.
Michael: Wow! I mentioned before that Garak is possibly my favorite characters. What excites you the most about Star Trek Adventures?
Nathan: Aside from the fact that I got to give back to a franchise that helped shape my geekdom? The positive response we've had to the game. The community has been enthusiastic and eager, not just to play the game, but to dabble with their own content and their own take on it. I started RPG writing by making my own content for the RPGs I loved. It is a pleasure to share their passion in turn with actual plays, podcasts, and live-streamed games. Also, being contacted by Geek & Sundry because they wanted to run Star Trek Adventures in a weekly live game was a great experience.
Michael: What are we most likely going to find you doing if you aren't absorbed in Star Trek Adventures?
I'm just coming out of a year-long campaign set aboard the U.S.S. Thunderchild. We're finishing off our "first season" before taking a hiatus so someone else can GM for a while. Most of my work on Star Trek Adventures now is checking over the rules other people wrote for the sourcebooks (plus the occasional short section or sidebar) and answering rules questions. Most of my time at the moment is working on a new SRD for the 2D20 System. I am compiling all the lessons learned from the last few games into a new incarnation of the system that we can use going forward.
For all of your devotion to Star Trek Adventures, Nathan, you earn a Tribble-Rating!


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Fresh from King's and frustrated, 23-year-old Cedrik von Stumm spent 8 unsuccessful weeks applying for jobs in the financial district which would utilise his degrees in Mathematics (BSc) and Financial Mathematics (MSc).
Determined to get hired but bored of "waiting for [the] chance," for his one out of many, on-paper equivalent applications to be chosen, he opted to stand out. Literally. He stood outside of Canary Wharf tube station, with a placard emblazoned with a brief CV: his degrees, his languages, and an invitation to "Ask for a CV".
Cedrik's story has value on its own: a very student-paper friendly blend of self-deprecating and ambitious off-the-cuffmanship, as well as being emblematic of graduate prospects. As a mathematics undergraduate myself, Cedrik's story resonated with me beyond his affiliation with King's. Plainly speaking, I wasn't looking forward to job applications as it was; his experience and reaction both worried as well as amused me. To set myself at ease – and to see how Cedrik had fared since his panhandling stunt – I sat down with him and chatted about life as a graduate.
Cedrik's charisma is immediately apparent. He holds himself with confidence and the charm of his speech gave me the impression I was being interviewed, despite him having merely responded to my Facebook message asking for an interview (in the process potentially setting himself up for a bizarre Catfish experience). These are among the qualities he feels are important to his character as a person, and indeed an employee, but aren't conveyed easily by a CV or an application.
Some would argue Cedrik was paying his dues here anyway, only his were more publicly humiliating. The reception from passers-by was positive overall. The older, employer looking types wished him well and remarked on his bravery, offering high fives and hand shakes. Some even asked for a CV, including a man from Barclays who offered him a job, telling him he'd be "working on my team from Monday." Some, however, were less positive.
But what came of it? Is Cedrik still braving the financial districts of the world with a cardboard sign, a suit and a smile? Is he living off the dole? Had he abandoned his financial sector ambitions?


There are articles all over the place that tell us that successful people journal. They list all of the things that successful people do, but very few venture into why these things contribute to their success. Instead of adding to the successful people to-do list club, I'm going to share actual reasons that journaling, specifically, is related to a person's level of success.
So, why do successful people journal?
Successful people are always evaluating, analyzing, and looking for more efficient ways to do things. One of the things they continue to assess and improve upon is self. Self-improvement is imperative to accomplishing goals. Whether you want to build a business, adopt a healthier lifestyle, or learn a language, you will have to do some work on your inner self.
One of the best ways to keep track of the work you're doing is to journal. Successful people write down where they are, how they feel, what their goals are, etc. Then, they write down ways they believe they can achieve their goals. They track their progress, new findings, and conversations they have. Those things all directly contribute to the aha moments that ultimately lead to the actions that launch them into success.
I have said, time and again, that you don't have to journal daily, and you don't. You should never do whatyou don't actually want to do. That's no way to live. However, some things are worth changing your mind on. Although I sometimes miss a day or two, I do my best to journal regularly. Journaling has helped me grow tremendously.
Through journaling, I learned what my business should be. I learned how to structure certain things. I remember old conversations that I had with people. I changed my self-talk and beliefs. I am an all-around better person for it.
It's never too late to join the club and become a successful person. If you haven't already, will you start journaling daily?
Are You Reinforcing Negativity or Reinventing Your Experiences?


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text:
package com.sun.jini.discovery;

import java.io.IOException;
import java.net.DatagramPacket;

/**
 * Iterator for performing multicast encode operations on (potentially)
 * multiple discovery format providers.
 *
 * @author Sun Microsystems, Inc.
 * @since 2.0
 */
public interface EncodeIterator {

    /**
     * Performs a single multicast encode operation using the next encoder
     * provider of a {@link Discovery} instance, returning the resulting
     * datagram packets or throwing the resulting exception.
     *
     * @return datagram packets resulting from an encode operation
     * @throws IOException if the encode operation failed
     * @throws net.jini.io.UnsupportedConstraintException if the encode
     * operation is unable to satisfy its constraints
     * @throws java.util.NoSuchElementException if there are no more encoders
     * for this iterator
     */
    DatagramPacket[] next() throws IOException;

    /**
     * Returns true if this iterator has additional encoders, or
     * false otherwise.
     *
     * @return true if this iterator has additional encoders, or
     * false otherwise
     */
    boolean hasNext();
}

redpajama_set_name: RedPajamaGithub


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One thing we know, Andys work is top notch.
Not much progress on Antons zuk.
I'm waiting to hear that the rear axles done from richard.
The front axles is stripped and being cleaned and I will be moving the perches and building it when the rear arrives. Then it's just some trimming to clear upfront (spua) and get the old girl running.
Must say took me a while to get through the 50+ pages but was good reading material at the dentists .
I'm going to have to sell her.
The lights aren't working at the moment, not sure why, the fuel pump needs a new positive wiring into the loom, and the engine won't start for some reason. I managed to get the fuel tank back in, but because of my health problems, just doing that near killed me (I have Myocarditis, my heart isn't working right).
I can't keep it because I can't get it through an MOT, and I'm not well enough to work on it. Probably never will be. I'm getting yelled at because where I have it stored shouldn't have vehicles stored. Wife's out of patience, and I'm not seeing an end in sight.
A woman offered a guy at the garage where it's currently (illegally) stored £1500 for it the other day. Pretty sure I have no option but to take her offer (if it still stands).


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I carefully sculpted, rolled, formed and shaped by hand every small detail you see on this pendant, based on my design. I didn't use any molds.
After sculpting/adding details, the necklace was cured in an oven to harden, then I added a clear finish to protect the surface of the artwork.


text:
Education System in the USA
What is Conditional Admission in the USA?
By Jim Crawley
Many universities offer conditional admission to academically qualified students who need to improve their English proficiency.
Choosing to continue your education in the United States is an exhilarating decision. As you begin your search for the right U.S. school you may feel hope, excitement, motivation and a little intimidation.
Some of you may know exactly what you want to study, and possibly you have even chosen a university or college. Others of you are dreaming of being in an American university classroom, but are not sure how to make the dream come true.
When you learn about a school's English language requirements, and realize your English language skills are not at a high enough level to begin classes, you may feel frustrated. Your academic marks meet the college or university admission requirements and you have the financial means to study in the USA. The only problem is your English language proficiency. This may cause you to delay your plans to study in the U.S., or to give up on a prospective school.
But there's another way …
Many universities now offer "conditional admission" to international students who meet all other admission requirements, but need to improve their English language proficiency. Conditional admission provides talented and capable international students a pathway into university classrooms.
Step 1: Apply for conditional admission to a university
Not all universities and colleges offer conditional admission, so it is important to find out whether this option is available before applying for admission. Frequently, if the university has an intensive English program, or has an agreement with a local private intensive English program, applicants who are academically qualified may be considered for conditional admission. In this case, you would submit an application packet with all required original documentation, with the exception of the proof of English proficiency.
The university will evaluate your application documents and if you're academically admissible, the university could issue you a letter of conditional admission. This means that once you successfully complete the specified intensive English program and/or have the appropriate test score report (TOEFL or IELTS), you will be offered full admission to the university.
Step 2: Apply for admission to an intensive English program
Once you have been granted conditional admission, you will also need to apply for admission to the university approved intensive English program. All the appropriate application, fees, and verification of financial support need to be submitted. The intensive English program will then issue you an admission letter and the appropriate immigration form, usually a Form I-20.
Step 3: Apply for your student visa
To apply for a student visa, you will need to take the admission documents from the intensive English program, original financial support documentation, and the conditional admission letter from the university to the U.S. consulate or embassy.
Even though you may have limited English abilities, it is important that you are able to answer basic questions about the intensive English program and the university. Knowing the university and English program's location, what you want to study, and having the ability to briefly state why you want to attend that school can be very helpful in the visa interview. Although there are no guarantees in the visa interview, the more natural and comfortable you are with your answers, the more likely there will be a positive outcome.
Step 4: Confirm, confirm, confirm!
When you begin studying in the intensive English program it is important that you contact the university to which you've been conditionally admitted. You will want to confirm the conditions of the offer of admission, and the university will want to verify when you will complete the intensive English program. This will ensure that you start in the semester indicated in the letter of conditional admission.
Step 5: Success! You've completed your intensive English program and are gaining full university admission
Once you've completed the intensive English language program, you will be transferring to the university. Remember that your student visa will be transferring as well. Therefore, you might be required to provide updated verification of financial support before the transfer can take place. Be sure and check for any other items that were outlined in the offer of conditional admission—all requirements must be met before a full offer of admission will be extended to you.
One last tip …
The final word of advice is to take advantage of all the classes offered by the intensive English program and to speak English in and out of the classroom. You will not only become proficient in English during this time, but you will have practiced the study skills necessary for university success.
ELS Language Center
"I received a conditional acceptance to complete my Master's Degree, but I had to learn English first!"
—Alaa Alsabbah from Saudi Arabia first studied intensive English at an ELS Language Center in Portland, Oregon.
"I made a lot of progress in my one session in the IEP [Intensive English Program]. I was able to pass the TOEFL and enter my graduate program. My use of English, in terms of the skills, improved. My ability to read, write, and discuss in English improved so that I could take graduate classes."
—Ramiro Garcia Olano from Argentina completed the Intensive English Program at University of Nebraska, Lincoln, and is now a Ph.D. student in Spanish Literature.
"My English has improved a lot in reading and writing skills because I always do assignments about these skills. This program helped me to prepare presentations, to search, read and write essays."
—Ebru Ozkurt from Turkey plans to earn an advanced degree in psychology, studied intensive English at Georgetown University in Washington, DC.
Jim Crawley is the Director of Global Recruiting and Partnerships at Alma College in Alma, Michigan
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