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Silicon Nanowire FinFETs
C. Mukherjee and C. K. Maiti
Submitted: March 16th, 2012 Published: December 19th, 2012
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Nanowires Recent Advances Edited by Xihong Peng
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C. Mukherjee
Indian Institute of Technology, Kharagpur, India
C. K. Maiti
*Address all correspondence to: ckm@ece.iitkgp.ernet.in
Some of the fundamental problems of ultra-small MOSFETs beyond sub-10nm channel length are the electrostatic limits, source-to-drain tunnelling, carrier mobility degradation, process variations, and static leakage. The trend toward ultra-short gate length MOSFETs requires a more and more effective control of the channel by the gate leading to new device architecture. It appears that non-classical device architectures can extend the CMOS lifetime and provide solutions to continue scaling. In case of silicon-based CMOS technologies, planar MOSFETs are limited to scaling beyond 15 nm technology node. As simple scaling of silicon CMOS becomes increasingly complex and expensive, there is considerable interest in increasing performance by using strained channels which can improve carrier mobility and drive current in a device. Multi-gate MOSFETs based on the concept of volume inversion are widely recognized as one of the most promising solutions for meeting the ITRS roadmap requirements. A wide variety of multi-gate architectures, including Double-Gate (DG), Gate-All-Around (GAA), Pi-FET and Fin Field-Effect Transistors (FinFETs), rectangular or cylindrical nanowire MOSFETs has been proposed in the literature. In all cases, these structures exhibit a superior control of short channel effects resulting from an exceptional electrostatic coupling between the conduction channel and the surrounding gate electrode. The nanowire (NW) transistors can be seen as the ultimate integration of the innovative nanodevices and is one of the candidates which have gained significant attention from both the device and circuit developers because of its potential for building highly dense and high performance electronic circuits. Recent advances in nanoscale fabrication techniques have shown that semiconductor nanowires may become the candidate for next generation technologies. Si and Ge nanowire transistors are also important because of their compatibility with the CMOS technology.
Nanowires and FinFETs have attracted considerable attention due to their proven robustness against Short-Channel Effects (SCE) and relatively simple fabrication. Silicon nanowire FinFET (SNWFT) is being considered as the candidate for CMOS scaling beyond the 32 nm node due to its high performance, excellent gate control and enhanced carrier transportation properties. Thin and multi-gate controlled body provide FinFETs a superior short-channel effect control, electrostatic shielding from the body bias, relaxing channel doping or pocket implants, commonly needed in planar technologies to avoid threshold voltage (VTH) roll-off [1]. Adequate device VTH is now being achieved by using gate stack engineering. Metal-Gates with High-k (HKMG) dielectric stacks provide the desired VTH by work-function tuning as well as preserving low gate leakage [2]. Various process options are being attempted to affect carrier transport in a different manner. The use of metal gates as replacement for Poly-Si stacks eliminates the Poly-depletion effect, benefiting effective carrier mobility by reducing the transverse field [1]. Additionally, use of undoped channels improves low-field μ eff due to the reduction in the substrate impurity scattering [3]. Mobility degradation due to Coulomb scattering in short-channel devices should further be reduced in the absence of pocket implants [4]. However, high-k dielectrics are known to degrade mobility as a result of a combination of Coulomb and phonon scattering mechanisms [5]. In order to account for inversion layer mobility degradation mechanisms for FinFET devices, a robust μ eff extraction algorithm is necessary. The mobility extraction requires accurate measurement of both gate to channel capacitance and channel current, together with reliable estimations for the parasitic Source-Drain series resistance (RSD) and the effective channel length [4]. Unfortunately, the capacitance of short-channel length devices in the presence of large gate leakage is no longer characterized trivially. In multi-gate architectures like the FinFET, the carrier transport occurs in different crystallographic planes. For standard substrates, the current flow occurs in the (100)/(110) for the top surface and (110)/(110) for the sidewalls. The transport in these crystal planes and directions are characterized by different mobility primarily due to the anisotropy of the effective masses.
The most promising among various Si multi-gate MOSFET architectures such as double-gate and tri-gate FinFETs, are nanowire FinFETs due to their superior electrostatic control through gate-all-around structure. Superior gate control, immunity of threshold voltage from substrate bias and excellent carrier transport properties along with more aggressive channel length scaling possibility have made GAA architecture with semiconductor nanowire channel a potential candidate for post-planar transistor design. Two approaches are generally used to fabricate Si NWs as well as other semiconductor NWs: bottom-up and top-down. In the first method, NWs are usually grown using a metallic catalyst on a separate substrate, usually through a Vapor-Liquid-Solid (VLS) growth mechanism. After a chemical or mechanical separation step, the NWs are harvested and transferred to another substrate [6]. In the top down-approach, the NWs are fabricated using a CMOS compatible technology, such as lithography-based patterning and etching [7]. Unlike the bottom-up approach where the NWs are randomly distributed, the top-down method enables accurate positioning of the NWs across the wafer and facilitates the ultra-large-scale-integration (ULSI) for high performance nano-electronic circuits. Moreover, due to processing difficulties related to the length of grown NWs, NW release and gate-etch process, most of the VLS grown NW transistors have omega-shaped gate (Ω-gate) geometry and are thus not full gate-all-around [6]. Among all the promising post-CMOS non-conventional structures, the silicon nanowire transistor has the most unique advantage – it is based on silicon.
In a MOSFET, the carriers encounter various scattering mechanisms on their way towards the drain terminal. Carrier mobility is a well known benchmark to judge the intrinsic performance of a long channel MOSFET. The state-of-the art short channel devices do not operate in the fully ballistic regime (they are at roughly 60% of the ballistic limit) and mobility is related to velocity through effective mass and ballistic ratio. Therefore, understanding the carrier mobility is beneficial to design and engineer new devices for future CMOS generations. The presence of significant resistive and capacitive parasitics as well as lack of large capacitance due to the small size of the NW channel adds complexities to the extraction of the intrinsic NW device characteristics. Simplified assumptions or incomplete device charge simulations generally lead to inaccurate and unreasonable mobility extraction [9]. In the absence of a well-behaved top-down process (as compared to the bottom-up-fabricated NWs with smooth and near ideal sidewalls) results in significant mobility degradation for smaller NW sizes [8].
Noise is known as a fundamental problem in various fields such as telecommunication, nanoelectronics, and biological systems. The low-frequency noise, or 1/f noise, is the excess noise at low frequencies whose power spectral density (PSD) approximately depends inversely on the frequency and therefore escalates at low frequencies. The 1/f noise originating from the transistors is a major issue in analog circuit design. The 1/f noise is, for example, up converted to undesired phase noise in voltage controlled oscillator (VCO) circuits, which can limit the information capacity of communication systems.
In this chapter we shall present a detailed framework on gate-all-around nanowires and multi-gate FinFETs which will include process and device design and characterization, simulation, and low-frequency noise and tunnelling spectroscopy analyses. Carrier mobility extraction in nanowire and FinFETs using split-CV technique will be described. Channel orientation dependence of the electrical parameters such as current, low-frequency noise will be presented. Self-heating effects in nanowire transistors are also discussed. In Section 2, the growth and fabrication of silicon nanowire transistors and multi-gate FinFET devices will be covered. The detailed fabrication process steps for GAA nanowires as well as tri-gate FinFETs are discussed. 3D device simulation and electrical characterization will also be covered in this Section. Split CV measurement technique is employed for mobility calculation and detailed model equations are formulated for FinFET and nanowire structures. In Section 3, the low-frequency noise characteristics of the nanowire FinFETs will be taken up. Voltage dependence of flicker noise (1/f) and power spectral densities and corner frequencies will be discussed based on low-frequency noise measurements. Time-domain random telegraph signal (RTS) and existence of two-level or multi-level RTS noise in nanowire transistors will also be taken up. In section 4, the orientation dependence will be discussed and current-voltage characteristics are compared to show the effect of orientation on the drain current. The effect of channel orientation is also discussed for the nanowire FinFET noise spectral densities for (100) and (110) channel orientations. In section 5, the lattice structures of Si, SiO2 in the nanowire FinFET are analyzed via inelastic electron tunneling spectroscopy (IETS). The lattice dynamics and other molecular vibrations in silicon nanowire FinFETs are discussed using the IETS spectra.
2. Multi-gate FinFET and Nanowire Transistors
In order to control short channel effects in planar SOI MOSFETs and maintain reasonable electrostatics at a given gate length, LG, a critical Si thickness, tSi on the order of LG/3 is required [10]. Multi-gate devices have been suggested to significantly relax the critical Si dimension in fully depleted SOI (FD-SOI) device architectures and process technology. For this purpose, planar double-gate, vertical double-gate (FinFET), triple-gate (Tri-gate), omega-shaped gate (Ω-gate), penta-gate, inverted T-channel FET, Φ-FET, and GAA nanowires have been proposed by various research groups over the past decade.
While most of these multi-gate technologies have been experimentally shown to benefit from excellent electrostatics and short-channel effects, they commonly suffer from a complicated fabrication process technology compared to planar bulk or SOI technology. Figure 1. shows the device schematic of
double-gate FinFET
tri-gate and
GAA NW MOSFETs.
The critical Si dimensions to sustain acceptable electrostatics have been reported [11]. It can be seen that the criterion of Si film thickness may be relaxed for the nanowire MOSFET, which is naturally evolved from double-gate FinFET technology.
Schematics of device structures of (a) double-gate FinFET (b) tri-gate and (c) GAA NW MOSFETs.
2.1. 3D Quantum Simulation of Multi-Gate FinFETs
The simulation of tri-gate FinFET is performed using SILVACO ATLAS3D quantum simulator framework. The Bohm Quantum Potential (BQP) model is included to model the confinement effects in the simulation. Also, calibration of the BQP model against the 2D Schrödinger-Poisson simulation is done for describing the quantum effects in small geometry Si FinFET and nanowire transistors. To model the effects of quantum confinement, ATLAS allows the solution of Schrödinger's equation along with the fundamental device equations. The solution of Schrödinger's equation gives a quantized description of the density of states in the presence of quantum-mechanical confining potential variations. When the quantum confinement is in one dimension (along y-axis), the calculation of the quantum electron density relies upon a solution of a 1D Schrödinger equation solved for eigen-state energies Eiv (x) and wave-functions Ψiv (x, y) at each slice perpendicular to x-axis and for each electron valley (or hole band) v as described below:
− h 2 2 ∂ ∂ y ( 1 m v y ( x , y ) ∂ ψ i v ∂ y ) + E c ( x , y ) ψ i v = E i v Ψ i v E1
Here, m v y ( x , y ) is a spatially dependent effective mass in y-direction for the v-th valley and EC (x, y) is a conduction band edge. The equation for holes is obtained by substituting hole effective masses instead of that of electrons and valence band edge -EV(x,y) instead of EC (x,y). ATLAS solves the one-dimensional Schrödinger's equation along a series of slices in the y direction relative to the device. The location of the slices in the y direction is developed in two ways. For rectangular ATLAS-defined meshes, the slices will automatically be taken along the existing mesh lines in the ATLAS mesh. If the mesh is non-rectangular or not an ATLAS defined mesh or both, a rectangular mesh must be specified. The potential derived from the solution of Poisson's equation is substituted back into Schrödinger's equation. This solution process (alternating between Schrödinger's and Poisson's equations) continues until convergence and a self-consistent solution of Schrödinger's and Poisson's equations is reached.
For the BQP model, there are two advantages over the density gradient method. First, it has better convergence properties in many situations. Secondly, one can calibrate it against results from the Schrödinger-Poisson equation under conditions of negligible current flow. The model introduces a position dependent Quantum Potential, Q, which is added to the Potential Energy of a given carrier type. This quantum potential is derived using the Bohm interpretation of quantum mechanics and takes the following form [12]
Q = − h 2 2 γ Δ _ ( M − 1 Δ _ ( n α ) ) n α E2
where γ and α are two adjustable parameters, M-1 is the inverse effective mass tensor and n is the electron (or hole) density. The first part of the calibrating the BQP model against the Schrödinger-Poisson (S-P) Model, is to choose a suitable bias for the device. There should be negligible current flow and quantum confinement effects that manifest at the chosen biases. The second part of the calibration is to set the appropriate BQP parameters. The third part of calibration is to choose the quantity to compare with S-P results. The BQP equation is coupled with Poisson's equation using the charge density terms:
n = N C exp ( − E C + q Q k T ) , p = N V exp ( − q Q − E V k T ) E3
2.2. Tri-gate FinFETs
Typical p-type tri-gate FinFET is fabricated on 1000 Ǻ SOI layer. The FinFET has a fin height of 30 nm. The fin width and fin length are varied from 60-90 nm and 60 nm to 100 μm, respectively. A 50 Ǻ SiO2 gate oxide is grown. Polysilicon gate was deposited of thickness 1500 Ǻ, followed by pocket implantation and a 300 Ǻ SiO2 spacer deposition. A deep source/drain implant is followed. Silicidation is done for contact formation by 300 Ǻ Ni/400 Ǻ TiN depositions with RTA at 550-600°C for 1 minute. A 700 Ǻ - 1 μm thick Al-pad is deposited for contact formation. The final device is annealed in forming gas at 420°C for 30 minutes.
3D Device Simulation
The 3D device structure simulated in ATLAS3D framework [13] of the tri-gate bulk Si-FinFET with fin height of 30 nm, fin width and fin length of 60 nm and 160 nm, is shown in Fig. 2.The simulation takes into account the quantum effects using the BQP model and the Schrödinger-Poisson solver. The tri-gate structure includes a poly-Si gate and a Si-Fin as a channel on the buried oxide (BOX). A gate oxide thickness of 5 nm is used for device simulation. The energy band diagram is shown in Fig. 3. depicting the conduction and valence band energies as a function of the distance along the Si-fin channel.
Simulated 3D device structure of a silicon tri-gate FinFET.
Energy band diagram of a tri-gate Si-FinFET.
Current-Voltage Characteristics
Figure 4. shows the measured ID-VGS characteristics of the p-type tri-gate FinFET. Typical device dimensions used for measurements are fin length of 160 nm, and width of 60 nm and oxide thickness of ~5 nm. The device displays excellent performance in terms of near ideal subthreshold slope (SS) (~82 mV/dec), and high Ion/Ioff ratios (~106). Figure 5. compares the measured ID-VDS with the TCAD simulation results which shows an excellent agreement showing the need of quantum 3D device simulation.
Typical measured ID-VGS characteristics of a tri-gate p-type Si-FinFET for two drain voltages; the inset shows the transconductance (g m ) plot as a function of gate voltage.
Comparison of ID-VDS characteristics of a tri-gate p-type Si-FinFET for results of both measured data and TCAD simulation.
2.3. Gate-All-Around Nanowire Transistors
GAA MOSFET is one of the most promising multi-gate structures to extend the scaling of the CMOS devices as it provides the best channel electrostatic control, which improves further with the shrinking of channel thickness. GAA MOSFETs have potential to offer enhanced carrier transport properties compared to planar devices, because of the high carrier mobility on sidewall planes. Careful design and fabrication are critical for GAA MOSFETs for obtaining better transport properties in such structures. The basic nanowire transistor fabrication process flow is illustrated in Fig. 6.
Typical nanowire fabrication process flow (After P. Hashemi, Gate-All-Around Silicon Nanowire MOSFETs: Top-down Fabrication and Transport Enhancement Techniques, PhD dissertation, Massachusetts Institute of Technology, 2010 [14]).
After definition of e-beam lithography (EBL) alignment marks, Si nanowires along <110> direction and S/D pads are defined by hybrid lithography. After reactive-ion etching (RIE) of Si and stripping the resist, nanowires are locally released using a protective photo resist mask and a buffered-oxide etch bath. The suspended nanowires are then RCA cleaned and are subjected to hydrogen anneal process. Although thermally grown oxide benefits from excellent interface with Si nanowires, the facet dependence of the growth usually results in a non-uniform oxide thickness for various crystallographic planes. In addition, thermally grown oxide can induce a significant amount of stress in the nanowires which can alter their intrinsic carrier transport properties [15]. The ALD dielectric benefits from scalability to thinner effective-oxide-thicknesses (EOT) and its excellent conformality ensures that the entire perimeter of the Si nanowire is uniformly gated. The overlapped gate structures are designed for two reasons. First, it helps to minimize the S/D external resistance as the ion-implanted nanowires may exhibit very large series resistance. Second, it is technologically difficult to remove the metal gate stringers under the nanowires if the gate is under lapped. Moreover, any gate-first process to be used after vertical etching of the gate requires an isotropic etch of the gate metal stringers under the nanowires which also laterally etches the bottom gate and results in high extension resistance. After contact via opening and Ti/Al deposition and patterning, the fabrication is completed by a forming gas annealing at 450°C for 30 minutes.
The 3D device simulation is performed in ATLAS3D framework of SILVACO. The simulated device structure is shown in Fig. 7. depicting a cylindrical GAA FinFET structure with fin diameter ~10 nm and fin length of 100 nm wih a surrounding gate oxide thickness of 10 nm. Gate electrode is defined with 70 nm overlap on source/drain. (100) SOI wafer (p-type, 1015 cm-3) was the starting material with 200 nm Si on 150 nm buried oxide (BOX). The gate electrode deposition included 130 nm amorphous silicon (α-Si).
Simulated GAA nanowire FinFET structure.
a): ID-VDS characteristics of a GAA Si-nanowire; (b): ID-VGS characteristics of a GAA Si-nanowire at two different drain voltages.
Figures 8 (a) and (b)show the typical Id-Vds and Id-Vgs characteristics of a GAA n-FinFET, respectively. Typical device dimensions used for measurements are fin length of 100 nm, and diameter of 10 nm and oxide thickness of ~10 nm. The excellent subthreshold performance include a high subthreshold slope (SS) of ~90 mV/dec, and Ion/Ioff ratios ~106.
2.4. Carrier Mobility in FinFETs
Effective mobility extraction for the FinFET devices was based on an improved split C-V method, similar to planar device mobility extraction [4]. This technique relies on the accurate computation of the inversion charge (Q i ), as well as on the correct calculation of the channel conductance (g c ) along the different operation regimes. Effective channel mobility is defined as [16]:
μ e f f = L e f f W e f f . g c Q i E4
W e f f = ( W f i n + 2 * H f i n ) * N f i n s for a tri-gate structure and W e f f = 2 * ( W f i n + H f i n ) * N f i n s for a GAA structure; N fins is the total number of fins, H fin is the fin height. The inversion charge is obtained by integration of the accurate gate to channel capacitance data (Cgc).
Q i ( V g ) = ∫ V G V T V G C g c ( V ) d V E5
The transfer characteristics and the gate-to-channel capacitance were measured using the split C–V technique to calculate the effective mobility of devices with fin width (Wfin) being 60 nm and the height of the fins (Hfin) being 30 nm. The effective mobility can be expressed in terms of top, bottom and sidewall mobilities; µtop, µbottom, µsidewall, in tri-gate and GAA structures, respectively, as:
μ e f f W e f f = μ t o p W f i n + 2 * μ s i d e w a l l H f i n μ e f f W e f f = μ t o p W f i n + μ b o t t o m W f i n + 2 * μ s i d e w a l l H f i n E6
Extracted effective mobility in a p-type tri-gate Si-FinFET with gate length 160 nm, and gate width 60 nm; inset shows the inversion charge as a function of gate voltage.
A linear regression can be used to extract the sidewall and top-surface mobility. Eqs. (4) and (5) are used for calculating the effective mobility in the FinFET device from split C-V measurements. The inset of Fig. 9 shows inversion charge density as a function of gate voltage, as obtained from Eq. (5) using split C-V gate-to-channel capacitance. Figure 9 depicts the effective mobility of the FinFET as calculated using Eq. (4) as a function of inversion charge. The extracted mobility values agree well with the results of [16] for a p-FinFET of with gate length 160 nm.
2.5. Self Heating Effects in Nanowire Transistors
One of the significant challenges in future semiconductor device design is excessive power dissipation and rise in device temperature. With the introduction of new geometrically confined device structures like SOI, FinFETs, nanowires and incorporation of new materials with poor thermal conductivities in the device active region, the device thermal problem is expected to become more challenging in coming years. There is considerable degradation in the ON current due to self-heating effects in silicon nanowire transistors. However, insignificant current degradation is observed in nanowire transistors because of pronounced velocity overshoot effect. Placements of the source and drain contacts also play a significant role on the magnitude of self-heating effect in nanowire transistors. Self-heating and random charge effects simultaneously influence the magnitude of the ON current for both positively and negatively charged single charges. The self-heating affects the ON current in two ways:
by lowering the barrier at the source end of the channel, thus allowing more carriers to go through and
via the screening effect of the Coulomb potential.
There is larger current degradation because of self-heating due to decreased thermal conductivity. Crystallographic direction dependent thermal conductivity is also an important aspect of self heating effects. Larger degradation is observed in the current along the [100] direction when compared to the [110] direction.
In SOI devices, the low thermal conductivity of the underlying silicon dioxide layer, which is about two orders of magnitude less than that of silicon inhibits cooling in SOI devices and causes severe self-heating, resulting in a higher channel operating temperature. The temperature rise is significant and depends on the buried oxide thickness, silicon thickness, and channel/metal contact separation. The device mobility is reduced as a result of the elevated temperature and results in reduced maximum drain saturation current. Also, high channel temperature leads to increase in interconnect temperature at the silicon-metal contact and make conduction cooling through the source, drain, and interconnects important. It should also be noted that the thermal conductivity of the silicon films decreases as the film thickness is reduced due to boundary scattering of phonons which further exacerbates self-heating and hence device performance. In brief, as semiconductor technology approaches to two-dimensional and three-dimensional transistor structures and are more isolated from the substrate self-heating effects will become increasingly important.
3. Low-Frequency Noise in Nanowire Transistors
Among various options for multi-gate device architecture, such as double-gate, tri-gate, etc., the nanowire (NW) channel with a wrap-around gate, GAA, has the largest advantage in terms of electrostatic integrity. However, several undesired effects become prominent from the miniaturization of the device dimensions. One such unwanted effect is a strong increase in the low-frequency noise generated in the transistor as the size of the device decreases. With dimension-scaling, it is necessary to also scale the power supplies. Noise cannot be completely eliminated and with small signal strength, the accuracy and measurements are limited in electronic circuits in presence of the dominant noise sources. The low-frequency noise, or 1/f noise, is the excess noise at low frequencies whose power spectral density approximately depends inversely on the frequency and becomes pronounced at low frequencies. The 1/f noise originating from the transistors is a severe obstacle in analog circuit design. For example, it can be up converted to undesired phase noise in voltage controlled oscillator circuits, which can limit the information capacity of communication systems. The problems in down-scaled devices such as the nanowire FinFETs compel one to study noise sources, mechanisms and their physical origins in detail. In this Section, we shall briefly discuss the two fundamental low-frequency noise characteristics, random telegraph signal noise and 1/f noise.
3.1. Low-Frequency Noise Measurement Setup
The standard noise measurement setup included an E5263A 2-channel high speed source monitor unit, a SR 570 low noise amplifier (LNA) and a 35670A dynamic signal analyzer. E5263A 2-channel high speed source monitor unit provided the necessary gate-source and drain-source biases as shown in Fig. 10. The minute fluctuations in the drain-source voltage were amplified to the measurable range using low noise amplifier. The output of the amplifier is fed to 35670A dynamic signal analyzer that performs the fast Fourier transform on the time domain signal to yield the voltage noise power spectral density (SV) in the 1-100 kHz range after correcting for amplifier gain. In order to obtain a stable spectrum, the number of averages was set at 100 and a 90% sampling window overlap was used for optimal real time processing. A computer interface is connected with the measuring system through GPIB connection to control the dynamic signal analyzer and for noise data collection.
Low-frequency noise measurement setup.
3.2. Random Telegraph Signal (RTS)
RTS noise, also known as burst noise or popcorn noise is observed as random switching events in the time domain voltage or current signal. In a MOSFET, if a carrier is trapped in a single trap or localized defect state, the current or voltage signal displays a random shift in the level denoting a change in the channel resistance. The two-level RTS signal signifies only one active trap. However, when multiple traps are involved, the current (or voltage) can switch between two or more states resembling a RTS waveform due to random trapping and de-trapping of carriers and the phenomenon is much more difficult to explain in order to identify the trapping/de-trapping process. For simple two-level RTS pulses with equal height ∆I and Poisson distributed mean time durations in the lower state τ l and in the higher state τ h , the PSD of the current fluctuations is derived as [17].
S I ( f ) = 4 ( Δ Ι ) 2 ( τ l ¯ + τ h ¯ ) [ ( 1 / τ l ¯ + 1 / τ h ¯ ) 2 + ( 2 π f ) 2 ] E7
Mainly two types of traps are identified depending on the nature of trapping mechanism. They are donor and acceptor traps. The donor trap is charged when it emits and electron (i.e. empty) and is neutral when it captures. The acceptor trap is, contrary to the donor trap, charged when it captures an electron and neutral when empty. In MOSFETs, the channel resistance increases with the charged-trap state changing the current (or voltage) to a high state. Clearly, the donor trap causes high current level after emission of carriers, and the acceptor trap causes the high current level when it captures an electron.
Depending on the values of the mean time constants of the RTS, the traps can be characterized of two types. These are the slow traps with high values of time constants, and the fast traps, with the time constants being very small (order of few 0.1 milliseconds). From RTS noise characterizations, interesting information about the trap energy, capture and emission kinetics and spatial location of the traps inside the semiconductor device can be acquired. The multi-level RTS is due to the activation of multiple traps near the quasi-Fermi level. With smaller area devices, only single traps are active as number of traps is less and the RTS becomes a simple two-level signal, with a Lorentzian PSD (1/f 2).
3.3. 1/f Noise
1/f noise, also called flicker noise or pink noise, is the low-frequency noise with fluctuations with a PSD proportional to 1/f γ with γ close to 1, usually in the range 0.7-1.3. The PSD for 1/f noise takes the general form
S I ( f ) = K I β f γ E8
where K is a constant and β is current exponent. There are various theories regarding the 1/f noise mechanisms of which most prominent are the carrier number fluctuation (surface phenomenon) and mobility fluctuation theories (bulk phenomenon). The mechanisms behind flicker noise are still a topic of research. The generally accepted origins of the 1/f noise are attributed to conductivity fluctuations, damage in crystal structures, and traps due to defects in semiconductors. 1/f fluctuations in the conductance have been observed in the low-frequency part of the spectrum (10-6 to 106 Hz) in most conducting materials and a wide variety of semiconductor devices [18, 19]. There are essentially two physical mechanisms behind any fluctuations in the current: fluctuations in the mobility or fluctuations in the number of carriers. In 1957, McWorther presented a 1/f noise model based on quantum mechanical tunneling transitions of electrons between traps in the gate oxide and the channel [20]. The tunneling time varies exponentially with distance from the trap and the 1/f noise is obtained for a trap density that is uniform in both energy and distance from the channel interface. The McWorther model is widely accepted for simplicity and its excellent agreement with experimental data, especially for nMOS transistors. However, the mobility fluctuation noise model explains the 1/f noise in pMOS transistors better [21]. It was later explained by the unified flicker noise theory that a trapped carrier also affects the surface mobility through Coulombic interaction. This correlated mobility fluctuation model gave a correction to the number fluctuation noise model which resolves the deviations of the theory for pMOS devices. However, the correction factor was debated for being very high since screening was not accounted for. Also, the carrier mobility at the surface is reduced compared to the bulk mobility due to additional surface scattering (by acoustic phonons and surface roughness), which has an impact on the mobility fluctuations. Moreover, the Hooge mobility noise is sensitive to the crystalline quality, which is deteriorated close to the interface. The most feasible explanation for the higher 1/f noise with the carriers being in close proximity of the gate oxide surface is increased mobility fluctuation noise.
3.4. Low-Frequency Noise
Figure 11 shows the RTS of a p-FinFET in time domain in a large span of 60 ms time for V d = −50 mV and |V g − V th | = 0.1 V. For this particular RTS, two distinct sets of current switching levels are observed, each of which is consistent with trapping and de-trapping at a single discrete trapping site. A segment of the RTS is enlarged in the inset of Fig. 11 showing a distinct two-level RTS. This shows a fast varying RTS (wit smaller time constants) is superimposed on a slow-varying RTS (with higher time constants) which generates the four-level RTS shown in the figure. This RTS is due to a slow (with higher time constant) and a fast trap (with lower time constant). The corresponding drain current spectral density is plotted in Fig. 12, with a corner frequency f c and a Lorentzian 1/f 2 nature. The traps are either donor or acceptor types as described in section 3.2. The high level in current corresponds to the charged trap state. With increasing gate bias, the trap occupancy increases [22]. Also, the time in the high current level increases with gate voltage. So the high level is the occupied charged-trap state or the emission time. The low-current level is the capture time from the same interpretation. The charged trap state is the occupied state which makes the trap to be an acceptor trap. The emission and capture time constants are thus identified in Fig. 12. The mean emission (τ e ) and capture time (τ c ) constants of the RTS in Fig. 11 are shown in Fig. 13 as a function of gate bias. The ratio of capture to emission times (τ c / τ e ) shows a gradual decrease with gate voltage. The high current time being τ e and the low current time as τ c The following can be written [22]:
ln ( τ c τ e ) = − 1 k T [ ( E C o x − E T ) − ( E c − E F ) − ϕ 0 + q ψ s + q x T t o x ( V G S − V F B − ψ s ) ] E9
where E Cox is the conduction band edge of the oxide, EC is the conduction band edge of the silicon, Φ 0 is the difference between the electron affinities of Si and SiO2, t ox is the oxide thickness, V GS is the gate bias, V FB is the flat band voltage, ψ s is the surface potential and x T is the position of the trap measured from the Si/SiO2 interface. Differentiating in terms of the gate bias we can obtain the position of traps as:
d d V G S ln ( τ c τ e ) = − 1 k T [ q x T t o x ] E10
From Fig. 13, using Eq. (10), the trap depth is calculated as 0.172 nm from the Si/SiO2 interface. A Lorentzian expression, as expected for an RTS [23, 24], is obtained as
W L S I d ( f ) I d 2 = A [ 1 + ( f / f c ) 2 ] E11
where A is a constant independent of frequency, f c = (1/2π)(1/τ c + 1/τ e ), and τ c and τ e are the capture and emission times, respectively, of a single carrier by an interface trap. It can be seen that the corner frequency f c ∼ 1 kHz, which is consistent with the observed switching times in the order of 0.4–1.4 ms.
RTS of a p-FinFET in time domain for V ds = −50 mV and |V gs − V th | = 0.1 V, depicting four levels with at least two traps; the inset shows a zoom of the fast RTS with the capture and emission time constants shown in the waveform.
Drain current noise power spectral density with a corner frequency f c and a Lorentzian nature (1/f 2).
The mean emission (τ e ) and capture time (τ c ) constants and the ratio of τ c /τ e of the RTS are shown as a function of gate bias.
The entire FinFET channel is very thin and close to the interface and thus will be highly sensitive to interface defects. The defect potential perturbation, on the order of several nanometres, will have an effect on a significant cross section of the 10-nm-wide fin, hence producing a large current change when the trap is filled. The relative amplitude ΔI d /I d can be written as [25]
Δ I d I d = 1 W L [ 1 N ± α μ ] E12
where N is the carrier density, α is the scattering coefficient, and μ is the carrier mobility. Using the double lateral channel FinFET approximation [26], N = 2 C ox |V G − V TH |/q and μ = g m L/(2WC ox V d ). The mobility limited by Coulomb scattering is calculated as μ C = 1/αN t , where N t is the density of occupied traps [25].
4. Orientation Dependence: Nanowire FinFETs
Theory and measurements on planar transistors show a large difference in mobility for electrons and holes depending on the interface orientation and the direction of current flow in MOSFETs [27, 28, 29]. Figure 14 illustrates the measured drain currents (ID-VDS) for two different channel orientations; (100) and (110). It is observed that the current is higher in (100) orientation compared to the (110) orientation. The change in channel crystallographic direction (and thereby a change in the direction of current flow) greatly influences the carrier mobilities due to direction dependency of the heavy hole effective mass affecting the low field hole mobility. The effect of channel orientation is dominant in p-type devices due to different band curvatures along the <100> and <110> channel directions.
Comparison of the measured drain currents (ID-VDS) for two different channel orientations; (100) and (110) of a p-type tri-gate Si-FinFET.
Comparison of the measured gate voltage noise power spectral density for two different channel orientations; (100) and (110) of a p-type tri-gate Si-FinFET.
The input referred gate voltage noise power spectral density (PSD) of the FinFET is shown in Fig. 15 for two different channel orientations ((100) and (110)) as a function of the gate-source voltage. It is observed that the gate voltage PSDs are comparable in magnitude for both orientations. It is well known that technological factors such as gate oxide quality, gate oxide material, channel material, conduction path, annealing, etc. can be of great importance for the low-frequency noise properties [30, 31, 32, 33]. The gate oxide quality and other technological factors can be considered as unchanged by the channel rotation, which explains why the orientation displays a negligible influence on the low-frequency noise. If the mobility fluctutation noise becomes dominant, the channel orientation may play significant part in determining the noise PSD. This is due to the fact that the carrier mobiliy depends on channel orientation. The difference in noise PSD for the two orientation is large in the subthreshold region. This is due to the fact that the mobility-fluctuation noise generation mechanism is dominant in the subthreshold region, since in the number-fluctuation model, there is no dependence of noise PSD on mobility at a fixed drain-current level. The channel orientation dependence of noise is more dominant in pMOS devices as also reported in reference 34. Stronger current and mobility enhancement in certain orientations may also cause a higher LFN level in the corresponding orientation.
5. Lattice Dynamics: Nanowire FinFETs
Lattice vibrations in small geometry devices and its orientation-dependence are important, which however, have not been studied in detail. Inelastic electron tunneling spectroscopy (IETS) has gained importance for characterization of small-geometry devices and ultra-thin-insulators due to its high resolution and sensitivity and has been used by many previous researchers for studying defects and molecular vibrations in metal-insulator-semiconductor (MIS) structures [35, 36, 37, 38, 39, 40, 41].
The principle of IETS depends on the tunneling current through the ultra-thin dielectric layer of the MIS structures and becomes more sensitive as the tunneling current increases. Tunneling spectroscopy detects interaction of tunneling electrons (through the dielectric) with lattice vibrations of the substrate, dielectric, electrodes or other molecular species as inelastic peaks in the second derivative of the current-voltage characteristics. The application of tunneling spectroscopy was first demonstrated by Hall [36]. The technique of inelastic electron tunneling spectroscopy was properly introduced in 1966 by Jaklevic and Lambe [37]. With high sensitivity and resolution, IETS has been used for various applications including the determination of density of states, molecular vibrations, band gap of superconductors and semiconductors, defects in semiconductors and insulators [38, 39]. IETS has also been used for studying the traps and molecular vibrations in ultra thin oxides [40] and high-k gate dielectrics [41]. A tunneling spectrum reveals mainly the vibration energies of the molecules between the electrodes and phonon modes. Yanson et al. have shown that the intensity of the inelastic tunneling process is characterized by the relative change in Δg/g for conductance g at energy ħω. The quantity Δg/g is related to the observed I-V characteristics by the following expression [42]:
Δ g g = V ∫ V 1 V 2 1 I d 2 I d V 2 d V E13
where, V 1 and V 2 are the starting and ending voltages of the vibration band under consideration. This relation can be used to quantify the strength of the vibration modes, i.e. the change in the Δg/g ratio indicates the strength of the interactions. In the following, we present the experimental tunneling spectra of Si, SiO2 phonon modes obtained for p-type Al/SiO2/Si tri-gate FinFETs and study the influence of crystal orientation. A comparison of lattice vibration modes and dispersion characteristics for (100) and (110) silicon orientation in tri-gate FinFET is made. It is observed that the lattice dynamics of silicon and SiO2 changes for different crystal orientations.
The low temperature (77K) inelastic electron tunneling spectroscopy measurement setup includes an E5263A 2-channel high speed source monitor unit for dc biasing, and a SR830 DSP lock-in amplifier for capturing the tunneling spectra by measuring the second derivatives of the current-voltage characteristics. The setup is shown in Fig. 16. AC modulation signal generated from oscillator output of the lock-in amplifier with f = 890 Hz, peak amplitude of 2 mV, is superimposed on a slowly varying dc gate voltage. A time constant of 3 sec was used. A notch filter in the lock-in amplifier was used to remove the unwanted harmonic frequencies. A computer interface is connected with the measuring system through GPIB connection to control the dynamic signal analyzer and for noise data collection.
IETS measurement setup.
The phonon spectra of Si are observed in the 0-70 mV range. Figure 17(a)shows the inelastic peaks in the phonon spectra of Si for FinFET on (100) silicon orientation obtained from the average of six scans after de-convolution of the IETS spectra. The most intense peak is found at 60 mV (wave number 483.9 cm-1). The peak is due to optical phonons at the conduction band minima (X-point) of silicon in transverse optical (TO) mode. Other significant Si-phonons include longitudinal acoustical (LA) phonon peak towards the X point at 47.2 mV (380.6 cm-1), the longitudinal optical (LO) phonon towards X point at 53 mV (427.4 cm-1). The transverse acoustic (TA) mode was observed at 19.7 mV (158.9 cm-1). Phonons of Al-electrodes are observed at 26 and 33 mV. These findings are in well agreement with reported results for Si phonons with (100) orientation [35]. The values of phonon frequencies of unstrained silicon were calculated by Sui et al. using a modified Keating model [43]. The experimental values are compared with these theoretical values. We suspect the minor shifts in peak locations are due to the inherent strain in the small geometry structure of the FinFET. The TO and LO mode towards the Γ point, however, was not observed from the IETS. Figure 17(b)shows similar phonon modes of silicon for (110) orientation. From the Brillouin zone of the Si-crystal the dispersion in (110) direction is calculated along the main symmetry directions Γ→X through K point and X→X through W point [44]. The identified peaks include TO mode at Γ and W points, respectively, at 68 (548.4 cm-1) and 58 mV (467.7 cm-1). LO and LA mode towards X point are found at 54 (435.5 cm-1) and 45.6 mV (367.7 cm-1), and LA towards K point is observed at 41 mV (330.6 cm-1). The TA modes at X and W points are observed at 19.5 (157.3 cm-1) and 26 mV (209.7 cm-1), respectively. The peaks at W point or K point are mostly of weaker intensity compared to the peaks at Γ and X points, which are the conduction band minima for the lattice. Also, unlike the (100) orientation, the symmetry directions in (110) orientation reveal inelastic interactions at the K and W points along with the Γ and X points which describes the Brillouin zone for Si in more detail.
IETS spectra showing Si-phonons in a Al/SiO2/Si FinFET for (a) (100) channel orientation and (b) (110) channel orientation.
Figures 18 (a) and (b) show the SiO2 phonon modes (in the 129-170 mV range) for (100) and (110) orientations, respectively. The peaks exhibit almost the same energy position for both the Si (110) and Si (100) devices. These peaks include, TO3 mode at 134 mV, LO4 at 144.2 mV, TO4 at 149.8 and 153.4 mV for (100) device. The corresponding peaks for (110) devices are observed at 132, 144.2 148 and 159 mV, respectively. The main discrepancy between the two orientations comes in the magnitude of the phonons. The asymmetric stretch TO4 mode is theoretically found at 148.8 mV [45] which appears as a strong peak in the Si (110) device, and as a weak peak in the (100) orientation, as also described by [35]. The ratio of intensities of vibration modes may vary for different orientations of the molecular dipoles in the tunnel oxide barrier for different device orientations.
IETS spectra showing SiO2-phonons in a Al/SiO2/Si FinFET for (a) (100) channel orientation and (b) (110) channel orientation.
In this chapter, we have discussed silicon nanowire FinFETs in detail. Several important electrical characteristics such as mobility, self-heating, low-frequency noise, impact of channel crystallographic orientation and lattice dynamics are presented for nanowire FinFETs. The fabrication process flow of the nanowire and FinFETs are described. Application of split C-V measurement to calculate effective carrier mobilities is shown and mobility models for FinFETs including side and top-wall mobilities are developed. Low-frequency noise measurements are performed and results of 1/f noise and RTS in FinFET devices are presented. Effects of channel orientation on current drive and low-frequency noise are discussed. Lattice vibrations and phonon mode of Si and SiO2 are studied for (100) and (110) channel orientations and Brillouin zone boundaries of the semiconductor are explored. Crystal dynamics in FinFETs are explained via inelastic electron tunneling spectroscopy. It is expected that the combination of strain effects with NWs can lead to very high performance devices.
1. Kedzierski J. Nowak E. Kanarsky T. Zhang Y. Boyd D. Carruthers R. Cabral C. Amos R. Lavoie C. Roy R. Newbury J. Sullivan E. Benedict J. Saunders P. Wong K. Canaperi D. Krishnan M. Lee K. L. Rainey B. A. Fried D. Cottrell P. Wong H. S. P. Ieong M. Haensch W. 2002 Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation Proc. IEEE IEDM Tech. Dig.247 250
2. Daewon H. Takeuchi H. Choi Y. K. King T. J. Bai W. P. Kwong D. L. Agarwal A. Ameen M. 2004 Molybdenum gate HfO2 CMOS FinFET technology Proc. IEEE IEDM Tech. Dig.643 646
3. Takagi S. Toriumi A. Iwase M. Tango H. 1994 On the universality of inversion layer mobility in Si MOSFET's: Part II Effects of surface orientation IEEE Trans. Electron Dev 41 12 2363 2368
4. Romanjek K. Andrieu F. Ernst T. Ghibaudo G. 2004 Improved split C-V method for effective mobility extraction in sub-0.1-μm Si MOSFETs IEEE Electron Dev. Lett25 8 583 585
5. Zhu W. Jin-Ping H. Ma T. P. 2004 Mobility measurement and degradation mechanisms of MOSFETs made with ultrathin high-k dielectrics IEEE Trans. Electron Dev51 1 98 105
6. Cui Y. Zhong Z. Wang D. Wang W. U. Lieber C. M. 2003 High Performance Silicon Nanowire Field Effect Transistors Nano Lett3 2 149
7. Suk S. D. Lee S. Y. Kim S. M. Yoon E. J. Kim M. S. Li M. Oh C. W. Yeo K. H. Kim S. H. Shin D. S. Lee K. H. Park H. S. Han J. N. Park C. J. Park J. B. Kim D. W. Park D. Ryu B. I. 2005 High Performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) Fabrication on Bulk Si Wafer, Characteristics, and Reliability Proc. IEEE IEDM Tech. DigDec 735 738
8. Chen J. Saraya T. Miyaji K. Shimizu K. Hiramoto T. 2008 Experimental study of mobility in [110] and [100]-directed multiple silicon nanowire GAA MOSFETs on (100) SOI Proc. VLSI Symp. Tech. Dig32 33
9. Koo S. M. Fujiwara A. Han J. P. Vogel E. M. Richter C. A. Bonevich J. E. 2004 High Inversion Current in Silicon Nanowire Field Effect Transistors Nano Lett 4 11 2197 2201Sep
10. Young K. K. 1989 Short-channel effect in fully depleted SOI MOSFETs IEEE Trans. Electron Dev36 2 399 402Feb.
11. Yang F. L. Lee D. H. Chen H. Y. Chang C. Y. Liu S. D. Huang C. C. Chung T. X. Chen H. W. Huang C. C. Liu Y. H. Wu C. C. Chen C. C. Chen S. C. Chen Y. T. Chen Y. H. Chen C. l. Chan B. W. Hsu P. F. Shieh J. H. Tao H. J. Yeo Y. C. Li Y. Lee J. W. Chen P. Liang M. S. Hu C. 20045nm-Gate Nanowire FinFETProc. VLSI Symp. Tech. Dig.196 197
12. Patnaik V. S. Gheedia A. Kumar M. J. 2008 3D Simulation of Nanowire FETs using Quantum Models SILVACO simulation standardJuly, Aug, Sept.,6 12
13. SILVACO Inc. 2010 Patrick Henry Drive, Santa Clara, CA 95054 ATLAS User's Manual, April 20.
14. Hashemi P. 2010 Gate-All-Around Silicon Nanowire MOSFETs: Top-down Fabrication and Transport Enhancement Techniques. PhD Dissertation, Massachusetts Institute of Technology.
15. Najmzadeh M. Bouvet D. Dobrosz P. Olsen S. Ionescu A. M. 2009 Investigation of oxidation-induced strain in a top-down Si nanowire platform Microelectronic Engineering 86 7-9 1961 1964
16. Ramos J. Severi S. Augendre E. Kerner C. Chiarella T. Nackaerts A. Hoffmann T. Collaert N. Jurczak M. Biesemans S. 2006 Effective Mobility Extraction Based on a Split RF C-V Method for Short-Channel FinFETs Proc. Solid-State Device Research Conference, (ESSDERC) 363 366
17. Machlup S. 1954 Noise in semiconductors: spectrum of a two-parameter random signal J. Appl. Phys. 25 341 343
18. Van der Ziel A. 1986 Noise in solid state devices and circuits John Wiley & Sons
19. Hooge F. N. Kleinpenning T. G. M. Vandamme L. K. J. 1981 Experimental studies on 1/f noise Rep. Prog. Phys44 479 531
20. Mc Worther A. L. 1957 Semiconductor surface physics University of Pennsylvania Press.
21. Vandamme L. K. J. Li X. Rigaud D. 1994 1/f noise in MOS devices, mobility or number fluctuations? IEEE Trans. Electron Dev. 41 1936 1945
22. Amarasinghe N. V. Celik-Butler Z. 2000 Complex random telegraph signals in 0.06 μm2 MDD n-MOSFETs Solid State Electron44 6 1013 1019Jun.
23. Kirton M. J. Uren M. J. 1989 Noise in solid-state microstructures: A new perspective on individual defects, interface states and low-frequency (1/f) noise Adv. Phys38 4 367 468 Nov
24. Kleinpenning T. G. M. 1990 On 1/f noise and random telegraph noise in very small electronic devices Physica B 164 3 331 334Sep.
25. Hung K. K. Ko P. K. Hu C. Cheng Y. C. 1990 A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors IEEE Trans. Electron Dev. 37 3 654 665 Mar
26. Daugé F. Pretet J. Cristoloveanu S. Vandooren A. Mathew L. Jomaah J. Nguyen B. Y. 2004 Coupling effects and channels separation in FinFETs Solid State Electron48 4 535 542Apr.
27. Yang M. Gusev E. P. Ieong M. Gluschenkov O. Boyd D. C. Chan K. K. Kozlowski P. M. D'Emic C. P. Sicina R. M. Jamison P. C. Chou A. I. 2003 Performance Dependence of CMOS on Silicon Substrate Orientation for Ultrathin Oxynitride and HfO2 Gate Dielectrics, IEEE Electron Dev. Lett.24 5 339 341
28. Sverdlov V. Ungersboeck E. Kosina H. Selberherr S. 2006 Orientation Dependence of the Low Field Mobility in Double- and Single-gate SOI FETs Pro. 36th European Solid-State Device Research Conf. (ESSDERC) 178 181
29. Smirnov S. Kosina H. Selberherr S. 2003 Substrate Orientation-Dependence of Electron Mobility in Strained SiGe Layers Proc. International Conf. on Simulation of Semiconductor Processes and Devices (SISPAD) 55 58
30. Claeys C. Mercha A. Simoen E. 2004 Low-frequency noise assessment for deep submicrometer CMOS technology nodes J. Electrochem. Soc.151 G307 G318
31. Von Haartman. M. Malm B. G. Ostling M. 2006 Comprehensive study on low-frequency noise and mobility in Si and SiGe pMOSFETs with high-k gate dielectrics and TiN gate IEEE Trans. Electron Dev53 836 843
32. Von Haartman. M. Lindgren A. C. Hellstrom P. E. Malm B. G. Zhang S. L. Ostling M. 2003 1/f noise in Si and Si0.7Ge0.3 pMOSFETs IEEE Trans. Electron Dev50 2513 2519
33. Vandamme L. K. J. Oosterhoff S. 1986 Annealing of ion-implanted resistors reduces the 1/f noise J. Appl. Phys. 59 3169 3174
34. Wei C. Xiong-Z Y. Zhou X. Singh N. Rustagi S. C. Lo G. Q. Kwong D. L. 2009 Investigation of Low-Frequency Noise in Silicon Nanowire MOSFETs in the Subthreshold Region IEEE Electron Dev. Lett. 30 6June668 671
35. Petit C. Salace G. Vuillaume D. 2004 Aluminum, oxide, and silicon phonons by inelastic electron tunneling spectroscopy on metal-oxide-semiconductor tunnel junctions: Accurate determination and effect of electrical stress J. Appl. Phys96 9 5042 5049
36. Hall R. N. Racette J. H. Ehrenreich H. 1960 Direct observations of Polarons and Phonons during tunneling in group 3-5 semiconductor junctions Phys. Rev. Lett 4 456 458May
37. Jaklevic R. C. Lambe J. 1966 Molecular vibration spectra by electron tunneling Phys. Rev. Lett. 17 1139 1140
38. Giaever I. Megerle K. 1961 Study of superconductors by electron tunneling Phys. Rev122 1101 1111
39. Chynoweth A. G. Logan R. A. Thomas D. E. 1962 Phonon- Assisted Tunneling in Silicon and Germanium Esaki Junctions Phys. Rev125 877 881
40. Petit C. Salace G. 2003 Inelastic electron tunneling spectrometer to characterize metal-oxide-semiconductor devices with ultrathin oxides Rev. Sci. Instrum74 4462
41. He W. Ma T. P. 2003 Inelastic Electron Tunneling Spectroscopy Study of Traps in Ultra-thin High-k Gate Dielectrics Appl. Phys. Lett83 26 5461 5463
42. Yanson I. K. Bogatina N. I. Verkin B. J. Shklyarevskii O. I. 1972 Asymmetry of Tunnel Spectrum Intensities of Impurity Organic Molecules Sov. Phys. JETP 35 540
43. Sui Z. Herman I. P. 1993 Effect of strain on phonons in Si, Ge, and Si/Ge heterostructures Phys. Rev. B 48 17938 17953
44. Tubino R. Piseri L. Zerbi G. 1972 Lattice Dynamics and Spectroscopic Properties by a Valence Force Potential of Diamondlike Crystals: C, Si, Ge, and Sn J. Chem. Phys56 3 1022
45. Kirk C. T. 1988 Quantitative analysis of the effect of disorder induced mode coupling on infrared absorption in silica Phys. Rev. B 38 1255 1273
2.Multi-gate FinFET and Nanowire Transistors
3.Low-Frequency Noise in Nanowire Transistors
4.Orientation Dependence: Nanowire FinFETs
5.Lattice Dynamics: Nanowire FinFETs
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text:
The St Paul's Christmas Review 2020
With all the madness that 2020 has brought us it seems fitting that we should end the year with another kind of madness – The St Paul's Christmas Review.
This time honoured tradition of the Christmas Review dates back many years when junior doctors took this time of year to create a series of sketches that reviewed the year and laid bare the mannerisms and quirks of the Consultant staff and senior managers. Are there any consequences for such actions, you might ask? Not at all; all of the consultants consider it an honour to be mentioned. In fact, Prof Harding once complained when he felt he had got off lightly that year!
As well as mocking the Consultant and management staff, there are other sketches such as songs and quizzes. Some of the more memorable sketches include Professor David Wong playing the role of a short-sighted Kamikaze pilot back in 1992 or when the consultants sing songs much to the enjoyment of the audience; especially at the expense of those that are better at surgery than singing. Another memorable occasion was the year David Roberts, Dispensing Optician and Kobujitsu black belt, demonstrated his Samurai sword skills by cutting various size fruit - starting with a watermelon and working down in size - in half off the stomach of Clinical Director, Mark Batterbury. Despite David's best health and safety advice of "Don't move", it didn't allay Mr Batterbury's fears and he drew the line when one member of the audience, who were by now well into the spirit of this sketch, asked if David could cut a grape in half. Mr Batterbury's fears were also shared with his colleague, Prof Stephen Kaye, who happened to be treating David at the time for Diplopia (double vision)! They were probably the only two in the auditorium not laughing!
One of the driving forces in organising the Christmas Review for many years is St Paul's Business Manager, Jayne Bradley; writer of many scripts and songs. We caught up with Jayne to discover more about the Review.
Jayne explained, "I have been employed by St Paul's Eye Hospital/Unit since 1983 from enrolled nurse, to St Paul's A&E Sister, Matron, Deputy General Manager and now Business Manager.
"For a majority of the years I have worked here, we have traditionally performed a Christmas Revue. The tradition goes back to the junior doctors of all disciplines who traditionally performed a summary of the year through their eyes highlighting events that have happened and consultants/staff they have dealt with.
"I don't know when it the first Christmas Review began at St Paul's but it took place before my time. It was traditionally run by a senior registrar – and has, in the past, been led by Ian Rennie, Prof Harding, Anker Raj and Brendan Moriarty.
"The scripts are produced by the medics themselves and other contributions from anybody who wants to take part. In all the years I have been involved I have only ever known one consultant to be offended.
"When we were at Old Hall Street, the revue took place in the Out-patients Department and the last ever one performed there was held in the summer time on ward 1B which had been emptied for the move to the Royal in 1992. We now hire the Medical Institute, which has become home of the Review – although this year it is on Zoom. However, we have even written a song about people and meetings on Zoom."
"The review is always opened by the St Paul's Prayer, written by the cast which outlines the year's shenanigans, both in the world and within St Paul's. This year's prayer could be quite lengthy!
"Following the sad passing of Jim McGalliard in 2003, an award was created in his name and the winner of the best sketch/performance receives the award. The award is presented by the Clinical Director at the end of the show and the judging panel usually consists of former and current St Paul's staff. It's always a poignant reminder as Jim himself had been drafted into a hilarious sketch without prior knowledge and a week later he died at the end of a clinic. Jim was a very popular colleague and his passing was felt by the entire team.
"For the last ten years at least, I've been like a sheepdog, booking the venue, paying the bills, getting everybody to rehearsals and coordinating on the day. Prior to his leaving St Paul's, Martin Hodson was always very supportive on the technical side.
"With everything going on this year, I had thought that this year's Christmas Review would have to be cancelled, but you know what thought did!! In fact, I think if there's ever been a year that NHS staff needed a good laugh it has to be 2020!"
The St Paul's Christmas Review takes place today (23rd December) and staff can watch it by clicking the link that was sent.

redpajama_set_name: RedPajamaCommonCrawl


The blessing of the Lord – it makes [truly] rich, and He adds no sorrow with it [neither does toiling increase it].
1. A Positive Mental Attitude – purposefully think pleasant thoughts and these thoughts will exhibit "attraction power" that will draw good things into your life. For example, focus on finding that single perfect flower and when you do, buy it and display it on your table or desk for all to admire. Costs little, but pulls in positive vibrations.
2. Sound Physical Health – eat well, exercise daily, and move your body hourly for optimum results.
3. Harmony in Human Relations – talk less listen more. Condition yourself to consider another's point of view.
4. Freedom From Fear – exchange your fears for faith and refuse to worry about something that you cannot control.
5. The Hope of Future Achievement – set simple goals and live up to your expectations. Start small and work up!
6. The Capacity for Faith – read faith based stories for inspiration, and seek out similar experiences in your own life.
7. Willingness to Share One's Blessings – give from your current earnings, not only from your surplus.
8. A Labor of Love – do something that you enjoy for the PURE joy of doing it.
9. An Open Mind on All Subjects – challenge yourself to grow and exceed the space you now occupy in the world. Go beyond where you are and learn something new.
10. Self-Discipline – budget your time and money and create a daily plan for the maintenance of sound health. A little done each day adds up in a month's time.
11. The Capacity to Understand People – school yourself in the nine basic motives that inspire people to do things. Next consider your primary and secondary motives – good or bad. You are where you are in life because of the actions you take.
12. Economic Security – plan for your financial security by saving a set portion of your weekly income. Never become someone's servant or slave due to lack of personal finances.
When you acquire a "nose" for these twelve riches of life, you will truly be a blessing to yourself and others and also a success by the best ruler for measuring a life well lived. It's been said that success by the yard is hard, but by the inch it's a cinch.
Be Your Very Best Always!


text:
February Dinner Meeting Report
Do all editors have an aspiring writer buried somewhere inside? After all, we're really good at fixing up bad writing, so it should come naturally to us - or should it? In this meeting we heard from two editors who've had success with writing as well.
Kate Cuthbert has her dream job. It really does seem as if it was made for her and her life was a journey towards manifesting it. Kate described to us her transformation from embarrassed romance novel reader to out-and-proud proponent, and her battle against the stereotype that romance readers are intellectual lightweights.
Considering the staggering sales figures of romance novels - around 50 per cent of all fiction sold - you have to wonder where people are reading them. It was desperation that made Kate overcome her embarrassment of reading romance in public (all in the good cause of her master's thesis), on the train on the way to uni, although she admits she had a three-stop no-go zone in the vicinity of uni in case anyone saw her!
The struggle with her own embarrassment about reading romance in public prompted Kate to ask why - a topic she has explored in focus groups and in her writing. She reads them because she loves happy endings and she believes in the redemptive power of love (and the hot sex doesn't hurt).
Kate's fame in the romance game started with a letter to the editor of the Brisbane Courier Mail about the subversiveness of romance novels. They didn't print the letter but it prompted a phone call from the editor that led to a feature article and then a fortnightly column from 2006 to 2008. She has also written for All About Romance, Bookseller+Publisher, the New York Journal of Books, the Australian Romance Readers Association and Booktopia. Meanwhile, she kept on blogging and she feels that timing, at the advent of Web 2.0, contributed to her lucky break.
On her blog, Kate enjoyed the free reign to write whatever she wanted, developing her network of fans and contacts and encouraging readers to bring their romance novels out in public. She was soon Australia's 'go-to expert on romance writing'.
Now she works as acquisitions manager of the digital-first imprint for Escape Publishing, a division of Harlequin Australia. It was fascinating to hear about the sub-genres in romance, which include Christian, Amish, science fiction, fantasy and romantic suspense. Kate also explained to us how, except for historical romance, romance novels have to keep up with the times, explore current issues and reflect today's gender relations.
As Kate says, if you think about popular movies, there's always a love interest. That got me thinking about books that I've read and about what a romance novel actually is, because there's a love plot going on in so many of them ...
Kath Harper credits her writing success to her dog. Back in the mid-noughties, whenever Kath would get a bit too frustrated with a manuscript or author and start 'verbalising' at her computer, her dog would quietly get up and leave the room. Eventually Kath got the message and realised that leaving the room would do her good too, so she started taking breaks from the desk by walking around the neighbourhood.
On one of these walks, Kath spied a notice for a local theatre company and decided to give acting a go. After getting a few strange male roles in various productions, finding that doing pelvic floor exercises while on stage helped one look 'intense and concentrated' and doing a bit of work in production and backstage, it occurred to Kath to give playwriting a go. In 2006 she submitted a play that she'd written over two nights and it was accepted and produced by her company.
Kath's creative life has been characterised by trying new things, so next she wrote a short comedy, which won the Boroondara Theatre Company's National Playwright Competition.
Her most recent play, produced by her local theatre company in late 2012, was set in an aged care facility, reflecting a recent experience she'd had with her mother. For this effort, Kath became a cover girl - albeit on the cover of Australian Senior magazine, but that's one more cover than most of us!
Kath did a certificate course in Professional Writing and Editing at the CAE - brandishing her AE certificate to wangle her way out of having to do any of the editing units - and expanded her repertoire into short stories. Her story Grandad's Garden won a prize in the unpublished writers' category of the 2012 National Year of Reading competition and she blushingly received her $1000 cheque from hunky actor William McInnes. She also won first prize in the Odyssey House Short Story Competition in 2012 for her story Cry Baby.
Next she thought she'd have a bash at crime fiction for Sisters in Crime's annual Scarlett Stiletto competition. She entered in several categories and won in the Body in the Library category, one of 11 prizes from 182 entries. Kath's tablemate on the night, who had entered umpteen times with no recognition, asked Kath how many times she'd entered and Kath had to admit shamefacedly it was her first.
Seeing a pattern here? Whatever she tries is gold. I'd love for Kath to write a novel next; based on her form she'll probably win the Miles Franklin with her first attempt!
Jo Tayler


text:
Fujifilm camera news
Fujifilm mirrorless camera leaked, expect full outing at CES
Ben Crompton, Former contributing editor · 4 January 2012 ·
News Based on facts, either observed and verified firsthand by the reporter, or reported and verified from knowledgeable sources.
(Pocket-lint) - A new image has emerged from the depths of the web showing off the latest and greatest mirrorless camera from Fujifilm ahead of its rumoured official outing at CES 2012.
The camera itself was previously mentioned in early October during a press conference with Fujifilm president and chief executive officer Shigetaka Komori, who stated that: "Fujifilm will launch in spring 2012, a mirrorless system camera with interchangeable lenses. The clear objective in the development of lenses, sensor and processor technology to achieve the highest image quality."
And here it is, we think, looking extremely black with what appears to be the camera grip on the right side of the snapper and, um... well that's about it really. The photo was originally posted by omuser.com, but seems to have been removed.
However, Komori believes that the camera will have a "resolution and low noise [that] will surpass the 35mm full size sensor." This sort of claim is frequently made by CSC manufacturers and it seems unlikely, regardless of the technology, whether it will be able to match the performance in terms of image quality of larger cameras.
We've also included a rather nice mockup posted on PetaPixel, which was produced by Jonker Burger and published last November. Apparently it's a pretty decent likeness.
As with all rumours we'll have to wait in the wings for more details, but it's only a week until CES 2012 so you'll just have to be patient.
Writing by Ben Crompton.
Sections Gadgets Fujifilm Cameras


The Northern Lehigh Ring of Honor honors individuals and establishes pride and preserves the tradition of the Northern Lehigh athletic program by honoring those who have made a significant contribution to the athletic program. A member of the Athletic Ring of Honor can include an athlete, coach or any other individual who has made a significant contribution to promote Northern Lehigh High School athletics. Athletes must have graduated or left at least 10 years prior to selection to the Athletic Ring of Honor. Each member will be honored with a ring of honor plaque and a banner that will be displayed on the gym wall.
Nomination forms must be submitted by October 1st for consideration by the Ring of Honor committee for the upcoming year.
Nomination forms for Coaches, Contributors, and Players can be found by clicking on the links below. Please note that all documents are in Adobe PDF format, which requires Adobe Reader to view; you can download the free program here.
This form can be used to nominate an Athletic Coach for Northern Lehigh's Ring of Honor.
This form can be used to nominate an Athletic Contributor for Northern Lehigh's Ring of Honor.
This form can be used to nominate a Student-Athlete for Northern Lehigh's Ring of Honor.


text:
The underlying power we felt at Japan Expo - My Hero Academia: the new hit in France!?
This year saw the 20th Japan Expo in Paris. This event about Japanese culture is popular for enabling visitors to enjoy diverse content, including ones related to popular culture, such as anime, manga or games, but also martial arts and traditional arts.
This time, the pixivision editors' team also participated along with pixiv!
During this event, the biggest of this type in Europe with more than 250,000 visitors in 4 days and about 800 exhibition booths, we could collect data from a wide range of participants, from private creators to company booths. Let's see how Japanese content is received in Paris, the City of Lights!
◼ Let's check the local trends
The Parisians' favorite topic is "My Hero Academia"
Japan Expo is truly a "Japan Festival", where children and adult fans of Japan gather. From Aomori Nebuta Matsuri to bubble milk tea, from kendo to traditional taiko, visitors are able to experience a wide range of Japanese culture.
What's more, many people see Japan Expo as a place full of loving fans of idols, anime, and manga. Although past works such as Naruto or Attack on Titan are still popular, the most tremendous hit in France is currently My Hero Academia, that along with One Punch Man has many enthusiastic fans all over the world.
Personal booths are also very popular
There were a lot of personal booths selling fanart of My Hero Academia, and according to the circles we interviewed, it seems that the fan-made couple Katsuki Bakugou/Shouto Todoroki is particularly popular:
"These two are supported by fans of "buddies" couples. With the growing understanding of the strong bonds between same-sex partners in France, I feel that they are accepted both as friends and as a BL (Boys' Love) couple."
By the way, in France, personal booths are not divided into genres or categories, and most of them are presented as "private artists". Both original works and fanart are sold, and the mood feels more like a "design festival with fanart on the side" rather than what you get at Comiket.
Each booth is unique and different from the others, and the works lined up in them are very diverse, ranging from game controllers to perler beads representing game characters, horns and accessories, realistic portraits or even original manga.
▲ This is made of perler beads!
▲ The styles vary from Harajuku style to parodies...
"Straightforward reactions made me happy"
We then found other exhibitors from Japan.
It's the second time that Amanogamidai, whose exhibit mainly consists of books about Yamashiro from the game "Azur Lane", takes part in this event in France. According to this mangaka whose work has already been serialized and published in big magazines: "I decided to participate because lots of fans come to buy my works during Comiket in Japan, so I wanted to go out of Japan and reach out to overseas enthusiasts too."
About the differences with Japan, he also said: "I got more frank reactions than I expected, like lots of passionate declarations such as 'I love this character!'. I'm really glad I came here." says the author who was able to hear the reactions of a new layer of fans.
By the way, regarding the differences he noticed with Comiket, he says: "I was told not to put R18 works at the edge of the booth, but closer to my side of the table as little children may come to visit. (laughs)
I felt that erotic content in general, seem to be ok, but people aren't so keen on loli." A fundamental point!
Suprised by a lot of sexually explicit material
It seems that France is relatively smooth regarding sexually explicit material. Indeed, freedom seems to be important, with manga aimed at adults sold with no censorship, and naked action figures displayed as they are, where everybody can see them.
▲ Even adults-targeted content human-sized cardboards were displayed where everybody could see
The increasing popularity of genres for women, selling well even before the anime adaptation
◼ The exploding popularity of BL
Demands are increasing for genres aimed at women, such as BL.
This year, as always, a lot of publishing companies participated in the event. According to them, some works got sold-out on the first day, following unexpected popularity, and there were many questions from visitors about whether they would be re-stocked.
The most popular work at this booth which translates and sales many comics aimed at women is Given, which anime adaptation started this season. Some said that "maybe its particularly neat art is the reason it so popular among French fans", and although one would think that fans generally increase after the anime adaptation, we could see that local fans are getting their information early. (*The anime was not out yet at the time of the interview.)
"Trending genres here aren't different from Japanese trends, ranging from the Omegaverse to more common, happier stories". As this comment states, the image of a Country fond of dramatic love stories, conveyed by French movies, may now belong to the past.
By the way, in Paris there aren't any big specialized chain stores like Animate, but many privately-managed stores. That's why many people looking for abundant product lineups tend to buy via websites and at events. Therefore, occasions of buying a lot of items at once are welcomed very enthusiastically.
◼ Lots of unexpected discoveries at pixiv booth
Until this point, we discussed the creative side, so now let's talk about the many discoveries that happened at the pixiv exhibit.
This time at the pixiv booth, we made an exhibition in collaboration with Studio Chizu, which produced Summer Wars among other hits. We also brought along a presentation video of "OZ on VRoid" in collaboration with Summer Wars, some contest-winning illustrations, we also provided a monitor allowing visitors to browse pixiv for illustrations.
What's more, in the middle of the booth, there was an ema shrine, which pixiv values as a formative experience regarding Japanese drawings. In this space, visitors were able to write or draw anything on these ema (wooden plaques hanging at shrines for people to write their wishes on), from comments to graffiti!
People learn words like "Iromatsu oshi" on social media
A cosplayer who asked for a third season for the anime Osomatsu-san, along with a cute illustration, said she learned specific category names such as Iromatsu Oshi or Ichimatsu Girls (both terms referring to the Osomatsu-kun universe) on Twitter.
"By looking at the Twitter accounts of many artists I love, I noticed that the same words were often repeated in the descriptions of several works." ... What an incredible sense of observation!
We gave some wonderful Summer Wars fanart to the director himself
When we saw a visitor painting something with their own watercolor palette they brought, we had to talk to them! They said they had a dream: to become an animator at Studio Chizu! After drawing the first draft with a pencil, this person colored it with paint turning it into a wonderful masterpiece. Later, we gave that ema directly to the director himself, Mr. Hosoda!
The ema were used even more freely than we expected, with a lot of friendly and humorous messages. For instance, someone wrote "I want to marry Hatsune Miku" on an ema, and another person wrote "Do your best" in response. Moreover, a person who spent too much money wrote down their bank account number. Those were really unexpected and interesting ways of using ema!
▲ This drawing represents My Neighbor Totoro. We can see once again that both children and adults share a passion for drawing.
"I would like for artists to write their names in alphabet too"
In the space where visitors could use the pixiv search screen, we saw them deeply appreciating some works. Crossover parodies of well-known works seemed to be particularly well received by the local fans. Even the staff eagerly used the search screen during their free time.
However, it looks like it's still hard for users from foreign countries to search for content on pixiv. For instance, some fans told us: "I want to know the artist who drew this illustration, but I can't read their name". So, if artists would write their name in alphabet, maybe more people would come to look at their work!
▲ A happy visitor who found a fanart of a work he likes
◼ A place to receive power from passionate fans
Anime and games cultures are indeed strong
This year was Japan Expo's 20th anniversary, which brought even more visitors than usual, with many interesting things to see.
Like the projection of an extract of the new movie Evangelion: 3.0+1.0, which will be the final chapter of the series, and Yoko Takahashi's live performance. She enthusiastically sang the opening theme to the famous anime, meeting a particularly enthusiastic crowd. The footage appeared on Japanese news as well.
What's more, big booths about online games, like the Nintendo one, were constantly crowded with people and very busy with live performances and dances.
A "festival" where passions condensate
We thought it would have been a French version of Comiket, but we were surprised to see a great number of exhibits and booths offering first-hand experiences. Visitors could, for instance, do a zombie make-up as in a horror manga, or take photos as if they had been transported into a manga world.
More than often, we shared excited gazes with the crowd...
We highly recommend you Japan Expo, as a place where you can enjoy very diverse drawings, from analogic to digital, and as an event where you can share your love for Japanese content.
We would like to thank all the people who participated in our interviews and who visited our booth.
In which country are we going to investigate about the otaku situation next? Please look forward to it!
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1. Aladdin is psytrance DJ and producer Michael from Stockholm, Sweden. Aladdin started his career in 2000 and did his first track release 'Cyborg Eye Of Mine' in 2003 on Swedish 'Creon Records'. His debut album, Void Last Line, was released in 2008 on Meira Records.
3. One of junglist producer Aphrodite's pseudonyms.
4. An incorrect tag for Alan Menken who wrote the music to the 1993 Disney Animated Film.


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Dr. Charles Woodburn
https://www.baesystems.com
BAE Systems plc provides defense, aerospace, and security solutions worldwide. The company operates through five segments: Electronic Systems, Cyber & Intelligence, Platforms & Services (US), Air, and Maritime. The Electronic Systems segment offers electronic warfare systems, navigation systems, electro-optical sensors, military and commercial digital engine and flight controls, precision guidance and seeker solutions, military communication systems and data links, persistent surveillance systems, space electronics, and electric drive propulsion systems. The Cyber & Intelligence segment provides solutions to modernize, maintain, and test cyber-harden aircraft, radars, missile systems, and mission applications that detect and deter threats to national security; systems engineering, integration, and sustainment services for critical weapons systems, C5ISR, and cyber security; and solutions and services to intelligence and federal/civilian agencies. It also offers data intelligence solutions to defend against national-scale threats, protect their networks, and data against attacks; security and intelligence solutions to the United Kingdom government and allied international governments; anti-fraud and regulatory compliance solutions; and enterprise-level data and digital services. The Platforms & Services (US) segment manufactures combat vehicles, weapons, and munitions, as well as provides ship repair services and the management of government-owned munitions facilities. The Air segment develops, manufactures, upgrades, and supports combat and jet trainer aircraft. The Maritime segment designs, manufactures, and supports surface ships, submarines, torpedoes, radars, and command and combat systems; and supplies naval gun systems. It also supplies naval weapon systems, missile launchers, and precision munitions. The company was founded in 1970 and is based in Farnborough, the United Kingdom.
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