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//===-- llvm/CodeGen/MachineBasicBlock.cpp ----------------------*- C++ -*-===//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// Collect the sequence of machine instructions for a basic block.
//
//===----------------------------------------------------------------------===//

#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallString.h"
#include "llvm/CodeGen/LiveIntervalAnalysis.h"
#include "llvm/CodeGen/LiveVariables.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SlotIndexes.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/DataLayout.h"
#include "llvm/IR/ModuleSlotTracker.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/Format.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/Target/TargetSubtargetInfo.h"
#include <algorithm>
using namespace llvm;

#define DEBUG_TYPE "codegen"

MachineBasicBlock::MachineBasicBlock(MachineFunction &mf, const BasicBlock *bb)
    : BB(bb), Number(-1), xParent(&mf) {
  Insts.Parent = this;
}

MachineBasicBlock::~MachineBasicBlock() {
}

/// Return the MCSymbol for this basic block.
MCSymbol *MachineBasicBlock::getSymbol() const {
  if (!CachedMCSymbol) {
    const MachineFunction *MF = getParent();
    MCContext &Ctx = MF->getContext();
    const char *Prefix = Ctx.getAsmInfo()->getPrivateLabelPrefix();
    CachedMCSymbol = Ctx.getOrCreateSymbol(Twine(Prefix) + "BB" +
                                           Twine(MF->getFunctionNumber()) +
                                           "_" + Twine(getNumber()));
  }

  return CachedMCSymbol;
}

raw_ostream &llvm::operator<<(raw_ostream &OS, const MachineBasicBlock &MBB) {
  MBB.print(OS);
  return OS;
}

/// When an MBB is added to an MF, we need to update the parent pointer of the
/// MBB, the MBB numbering, and any instructions in the MBB to be on the right
/// operand list for registers.
///
/// MBBs start out as #-1. When a MBB is added to a MachineFunction, it
/// gets the next available unique MBB number. If it is removed from a
/// MachineFunction, it goes back to being #-1.
void ilist_traits<MachineBasicBlock>::addNodeToList(MachineBasicBlock *N) {
  MachineFunction &MF = *N->getParent();
  N->Number = MF.addToMBBNumbering(N);

  // Make sure the instructions have their operands in the reginfo lists.
  MachineRegisterInfo &RegInfo = MF.getRegInfo();
  for (MachineBasicBlock::instr_iterator
         I = N->instr_begin(), E = N->instr_end(); I != E; ++I)
    I->AddRegOperandsToUseLists(RegInfo);
}

void ilist_traits<MachineBasicBlock>::removeNodeFromList(MachineBasicBlock *N) {
  N->getParent()->removeFromMBBNumbering(N->Number);
  N->Number = -1;
}

/// When we add an instruction to a basic block list, we update its parent
/// pointer and add its operands from reg use/def lists if appropriate.
void ilist_traits<MachineInstr>::addNodeToList(MachineInstr *N) {
  assert(!N->getParent() && "machine instruction already in a basic block");
  N->setParent(Parent);

  // Add the instruction's register operands to their corresponding
  // use/def lists.
  MachineFunction *MF = Parent->getParent();
  N->AddRegOperandsToUseLists(MF->getRegInfo());
}

/// When we remove an instruction from a basic block list, we update its parent
/// pointer and remove its operands from reg use/def lists if appropriate.
void ilist_traits<MachineInstr>::removeNodeFromList(MachineInstr *N) {
  assert(N->getParent() && "machine instruction not in a basic block");

  // Remove from the use/def lists.
  if (MachineFunction *MF = N->getParent()->getParent())
    N->RemoveRegOperandsFromUseLists(MF->getRegInfo());

  N->setParent(nullptr);
}

/// When moving a range of instructions from one MBB list to another, we need to
/// update the parent pointers and the use/def lists.
void ilist_traits<MachineInstr>::
transferNodesFromList(ilist_traits<MachineInstr> &fromList,
                      ilist_iterator<MachineInstr> first,
                      ilist_iterator<MachineInstr> last) {
  assert(Parent->getParent() == fromList.Parent->getParent() &&
        "MachineInstr parent mismatch!");

  // Splice within the same MBB -> no change.
  if (Parent == fromList.Parent) return;

  // If splicing between two blocks within the same function, just update the
  // parent pointers.
  for (; first != last; ++first)
    first->setParent(Parent);
}

void ilist_traits<MachineInstr>::deleteNode(MachineInstr* MI) {
  assert(!MI->getParent() && "MI is still in a block!");
  Parent->getParent()->DeleteMachineInstr(MI);
}

MachineBasicBlock::iterator MachineBasicBlock::getFirstNonPHI() {
  instr_iterator I = instr_begin(), E = instr_end();
  while (I != E && I->isPHI())
    ++I;
  assert((I == E || !I->isInsideBundle()) &&
         "First non-phi MI cannot be inside a bundle!");
  return I;
}

MachineBasicBlock::iterator
MachineBasicBlock::SkipPHIsAndLabels(MachineBasicBlock::iterator I) {
  iterator E = end();
  while (I != E && (I->isPHI() || I->isPosition() || I->isDebugValue()))
    ++I;
  // FIXME: This needs to change if we wish to bundle labels / dbg_values
  // inside the bundle.
  assert((I == E || !I->isInsideBundle()) &&
         "First non-phi / non-label instruction is inside a bundle!");
  return I;
}

MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() {
  iterator B = begin(), E = end(), I = E;
  while (I != B && ((--I)->isTerminator() || I->isDebugValue()))
    ; /*noop */
  while (I != E && !I->isTerminator())
    ++I;
  return I;
}

MachineBasicBlock::instr_iterator MachineBasicBlock::getFirstInstrTerminator() {
  instr_iterator B = instr_begin(), E = instr_end(), I = E;
  while (I != B && ((--I)->isTerminator() || I->isDebugValue()))
    ; /*noop */
  while (I != E && !I->isTerminator())
    ++I;
  return I;
}

MachineBasicBlock::iterator MachineBasicBlock::getFirstNonDebugInstr() {
  // Skip over begin-of-block dbg_value instructions.
  iterator I = begin(), E = end();
  while (I != E && I->isDebugValue())
    ++I;
  return I;
}

MachineBasicBlock::iterator MachineBasicBlock::getLastNonDebugInstr() {
  // Skip over end-of-block dbg_value instructions.
  instr_iterator B = instr_begin(), I = instr_end();
  while (I != B) {
    --I;
    // Return instruction that starts a bundle.
    if (I->isDebugValue() || I->isInsideBundle())
      continue;
    return I;
  }
  // The block is all debug values.
  return end();
}

const MachineBasicBlock *MachineBasicBlock::getLandingPadSuccessor() const {
  // A block with a landing pad successor only has one other successor.
  if (succ_size() > 2)
    return nullptr;
  for (const_succ_iterator I = succ_begin(), E = succ_end(); I != E; ++I)
    if ((*I)->isEHPad())
      return *I;
  return nullptr;
}

bool MachineBasicBlock::hasEHPadSuccessor() const {
  for (const_succ_iterator I = succ_begin(), E = succ_end(); I != E; ++I)
    if ((*I)->isEHPad())
      return true;
  return false;
}

#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
void MachineBasicBlock::dump() const {
  print(dbgs());
}
#endif

StringRef MachineBasicBlock::getName() const {
  if (const BasicBlock *LBB = getBasicBlock())
    return LBB->getName();
  else
    return "(null)";
}

/// Return a hopefully unique identifier for this block.
std::string MachineBasicBlock::getFullName() const {
  std::string Name;
  if (getParent())
    Name = (getParent()->getName() + ":").str();
  if (getBasicBlock())
    Name += getBasicBlock()->getName();
  else
    Name += ("BB" + Twine(getNumber())).str();
  return Name;
}

void MachineBasicBlock::print(raw_ostream &OS, SlotIndexes *Indexes) const {
  const MachineFunction *MF = getParent();
  if (!MF) {
    OS << "Can't print out MachineBasicBlock because parent MachineFunction"
       << " is null\n";
    return;
  }
  const Function *F = MF->getFunction();
  const Module *M = F ? F->getParent() : nullptr;
  ModuleSlotTracker MST(M);
  print(OS, MST, Indexes);
}

void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST,
                              SlotIndexes *Indexes) const {
  const MachineFunction *MF = getParent();
  if (!MF) {
    OS << "Can't print out MachineBasicBlock because parent MachineFunction"
       << " is null\n";
    return;
  }

  if (Indexes)
    OS << Indexes->getMBBStartIdx(this) << '\t';

  OS << "BB#" << getNumber() << ": ";

  const char *Comma = "";
  if (const BasicBlock *LBB = getBasicBlock()) {
    OS << Comma << "derived from LLVM BB ";
    LBB->printAsOperand(OS, /*PrintType=*/false, MST);
    Comma = ", ";
  }
  if (isEHPad()) { OS << Comma << "EH LANDING PAD"; Comma = ", "; }
  if (hasAddressTaken()) { OS << Comma << "ADDRESS TAKEN"; Comma = ", "; }
  if (Alignment)
    OS << Comma << "Align " << Alignment << " (" << (1u << Alignment)
       << " bytes)";

  OS << '\n';

  const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
  if (!livein_empty()) {
    if (Indexes) OS << '\t';
    OS << "    Live Ins:";
    for (const auto &LI : make_range(livein_begin(), livein_end())) {
      OS << ' ' << PrintReg(LI.PhysReg, TRI);
      if (LI.LaneMask != ~0u)
        OS << format(":%08X", LI.LaneMask);
    }
    OS << '\n';
  }
  // Print the preds of this block according to the CFG.
  if (!pred_empty()) {
    if (Indexes) OS << '\t';
    OS << "    Predecessors according to CFG:";
    for (const_pred_iterator PI = pred_begin(), E = pred_end(); PI != E; ++PI)
      OS << " BB#" << (*PI)->getNumber();
    OS << '\n';
  }

  for (const_instr_iterator I = instr_begin(); I != instr_end(); ++I) {
    if (Indexes) {
      if (Indexes->hasIndex(I))
        OS << Indexes->getInstructionIndex(I);
      OS << '\t';
    }
    OS << '\t';
    if (I->isInsideBundle())
      OS << "  * ";
    I->print(OS, MST);
  }

  // Print the successors of this block according to the CFG.
  if (!succ_empty()) {
    if (Indexes) OS << '\t';
    OS << "    Successors according to CFG:";
    for (const_succ_iterator SI = succ_begin(), E = succ_end(); SI != E; ++SI) {
      OS << " BB#" << (*SI)->getNumber();
      if (!Weights.empty())
        OS << '(' << *getWeightIterator(SI) << ')';
    }
    OS << '\n';
  }
}

void MachineBasicBlock::printAsOperand(raw_ostream &OS,
                                       bool /*PrintType*/) const {
  OS << "BB#" << getNumber();
}

void MachineBasicBlock::removeLiveIn(MCPhysReg Reg, unsigned LaneMask) {
  LiveInVector::iterator I = std::find_if(
      LiveIns.begin(), LiveIns.end(),
      [Reg] (const RegisterMaskPair &LI) { return LI.PhysReg == Reg; });
  if (I == LiveIns.end())
    return;

  I->LaneMask &= ~LaneMask;
  if (I->LaneMask == 0)
    LiveIns.erase(I);
}

bool MachineBasicBlock::isLiveIn(MCPhysReg Reg, unsigned LaneMask) const {
  livein_iterator I = std::find_if(
      LiveIns.begin(), LiveIns.end(),
      [Reg] (const RegisterMaskPair &LI) { return LI.PhysReg == Reg; });
  return I != livein_end() && (I->LaneMask & LaneMask) != 0;
}

void MachineBasicBlock::sortUniqueLiveIns() {
  std::sort(LiveIns.begin(), LiveIns.end(),
            [](const RegisterMaskPair &LI0, const RegisterMaskPair &LI1) {
              return LI0.PhysReg < LI1.PhysReg;
            });
  // Liveins are sorted by physreg now we can merge their lanemasks.
  LiveInVector::const_iterator I = LiveIns.begin();
  LiveInVector::const_iterator J;
  LiveInVector::iterator Out = LiveIns.begin();
  for (; I != LiveIns.end(); ++Out, I = J) {
    unsigned PhysReg = I->PhysReg;
    unsigned LaneMask = I->LaneMask;
    for (J = std::next(I); J != LiveIns.end() && J->PhysReg == PhysReg; ++J)
      LaneMask |= J->LaneMask;
    Out->PhysReg = PhysReg;
    Out->LaneMask = LaneMask;
  }
  LiveIns.erase(Out, LiveIns.end());
}

unsigned
MachineBasicBlock::addLiveIn(MCPhysReg PhysReg, const TargetRegisterClass *RC) {
  assert(getParent() && "MBB must be inserted in function");
  assert(TargetRegisterInfo::isPhysicalRegister(PhysReg) && "Expected physreg");
  assert(RC && "Register class is required");
  assert((isEHPad() || this == &getParent()->front()) &&
         "Only the entry block and landing pads can have physreg live ins");

  bool LiveIn = isLiveIn(PhysReg);
  iterator I = SkipPHIsAndLabels(begin()), E = end();
  MachineRegisterInfo &MRI = getParent()->getRegInfo();
  const TargetInstrInfo &TII = *getParent()->getSubtarget().getInstrInfo();

  // Look for an existing copy.
  if (LiveIn)
    for (;I != E && I->isCopy(); ++I)
      if (I->getOperand(1).getReg() == PhysReg) {
        unsigned VirtReg = I->getOperand(0).getReg();
        if (!MRI.constrainRegClass(VirtReg, RC))
          llvm_unreachable("Incompatible live-in register class.");
        return VirtReg;
      }

  // No luck, create a virtual register.
  unsigned VirtReg = MRI.createVirtualRegister(RC);
  BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg)
    .addReg(PhysReg, RegState::Kill);
  if (!LiveIn)
    addLiveIn(PhysReg);
  return VirtReg;
}

void MachineBasicBlock::moveBefore(MachineBasicBlock *NewAfter) {
  getParent()->splice(NewAfter, this);
}

void MachineBasicBlock::moveAfter(MachineBasicBlock *NewBefore) {
  MachineFunction::iterator BBI = NewBefore;
  getParent()->splice(++BBI, this);
}

void MachineBasicBlock::updateTerminator() {
  const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
  // A block with no successors has no concerns with fall-through edges.
  if (this->succ_empty()) return;

  MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
  SmallVector<MachineOperand, 4> Cond;
  DebugLoc dl;  // FIXME: this is nowhere
  bool B = TII->AnalyzeBranch(*this, TBB, FBB, Cond);
  (void) B;
  assert(!B && "UpdateTerminators requires analyzable predecessors!");
  if (Cond.empty()) {
    if (TBB) {
      // The block has an unconditional branch. If its successor is now
      // its layout successor, delete the branch.
      if (isLayoutSuccessor(TBB))
        TII->RemoveBranch(*this);
    } else {
      // The block has an unconditional fallthrough. If its successor is not
      // its layout successor, insert a branch. First we have to locate the
      // only non-landing-pad successor, as that is the fallthrough block.
      for (succ_iterator SI = succ_begin(), SE = succ_end(); SI != SE; ++SI) {
        if ((*SI)->isEHPad())
          continue;
        assert(!TBB && "Found more than one non-landing-pad successor!");
        TBB = *SI;
      }

      // If there is no non-landing-pad successor, the block has no
      // fall-through edges to be concerned with.
      if (!TBB)
        return;

      // Finally update the unconditional successor to be reached via a branch
      // if it would not be reached by fallthrough.
      if (!isLayoutSuccessor(TBB))
        TII->InsertBranch(*this, TBB, nullptr, Cond, dl);
    }
  } else {
    if (FBB) {
      // The block has a non-fallthrough conditional branch. If one of its
      // successors is its layout successor, rewrite it to a fallthrough
      // conditional branch.
      if (isLayoutSuccessor(TBB)) {
        if (TII->ReverseBranchCondition(Cond))
          return;
        TII->RemoveBranch(*this);
        TII->InsertBranch(*this, FBB, nullptr, Cond, dl);
      } else if (isLayoutSuccessor(FBB)) {
        TII->RemoveBranch(*this);
        TII->InsertBranch(*this, TBB, nullptr, Cond, dl);
      }
    } else {
      // Walk through the successors and find the successor which is not
      // a landing pad and is not the conditional branch destination (in TBB)
      // as the fallthrough successor.
      MachineBasicBlock *FallthroughBB = nullptr;
      for (succ_iterator SI = succ_begin(), SE = succ_end(); SI != SE; ++SI) {
        if ((*SI)->isEHPad() || *SI == TBB)
          continue;
        assert(!FallthroughBB && "Found more than one fallthrough successor.");
        FallthroughBB = *SI;
      }
      if (!FallthroughBB && canFallThrough()) {
        // We fallthrough to the same basic block as the conditional jump
        // targets. Remove the conditional jump, leaving unconditional
        // fallthrough.
        // FIXME: This does not seem like a reasonable pattern to support, but
        // it has been seen in the wild coming out of degenerate ARM test cases.
        TII->RemoveBranch(*this);

        // Finally update the unconditional successor to be reached via a branch
        // if it would not be reached by fallthrough.
        if (!isLayoutSuccessor(TBB))
          TII->InsertBranch(*this, TBB, nullptr, Cond, dl);
        return;
      }

      // The block has a fallthrough conditional branch.
      if (isLayoutSuccessor(TBB)) {
        if (TII->ReverseBranchCondition(Cond)) {
          // We can't reverse the condition, add an unconditional branch.
          Cond.clear();
          TII->InsertBranch(*this, FallthroughBB, nullptr, Cond, dl);
          return;
        }
        TII->RemoveBranch(*this);
        TII->InsertBranch(*this, FallthroughBB, nullptr, Cond, dl);
      } else if (!isLayoutSuccessor(FallthroughBB)) {
        TII->RemoveBranch(*this);
        TII->InsertBranch(*this, TBB, FallthroughBB, Cond, dl);
      }
    }
  }
}

void MachineBasicBlock::addSuccessor(MachineBasicBlock *succ, uint32_t weight) {

  // If we see non-zero value for the first time it means we actually use Weight
  // list, so we fill all Weights with 0's.
  if (weight != 0 && Weights.empty())
    Weights.resize(Successors.size());

  if (weight != 0 || !Weights.empty())
    Weights.push_back(weight);

  Successors.push_back(succ);
  succ->addPredecessor(this);
}

void MachineBasicBlock::removeSuccessor(MachineBasicBlock *succ) {
  succ->removePredecessor(this);
  succ_iterator I = std::find(Successors.begin(), Successors.end(), succ);
  assert(I != Successors.end() && "Not a current successor!");

  // If Weight list is empty it means we don't use it (disabled optimization).
  if (!Weights.empty()) {
    weight_iterator WI = getWeightIterator(I);
    Weights.erase(WI);
  }

  Successors.erase(I);
}

MachineBasicBlock::succ_iterator
MachineBasicBlock::removeSuccessor(succ_iterator I) {
  assert(I != Successors.end() && "Not a current successor!");

  // If Weight list is empty it means we don't use it (disabled optimization).
  if (!Weights.empty()) {
    weight_iterator WI = getWeightIterator(I);
    Weights.erase(WI);
  }

  (*I)->removePredecessor(this);
  return Successors.erase(I);
}

void MachineBasicBlock::replaceSuccessor(MachineBasicBlock *Old,
                                         MachineBasicBlock *New) {
  if (Old == New)
    return;

  succ_iterator E = succ_end();
  succ_iterator NewI = E;
  succ_iterator OldI = E;
  for (succ_iterator I = succ_begin(); I != E; ++I) {
    if (*I == Old) {
      OldI = I;
      if (NewI != E)
        break;
    }
    if (*I == New) {
      NewI = I;
      if (OldI != E)
        break;
    }
  }
  assert(OldI != E && "Old is not a successor of this block");
  Old->removePredecessor(this);

  // If New isn't already a successor, let it take Old's place.
  if (NewI == E) {
    New->addPredecessor(this);
    *OldI = New;
    return;
  }

  // New is already a successor.
  // Update its weight instead of adding a duplicate edge.
  if (!Weights.empty()) {
    weight_iterator OldWI = getWeightIterator(OldI);
    *getWeightIterator(NewI) += *OldWI;
    Weights.erase(OldWI);
  }
  Successors.erase(OldI);
}

void MachineBasicBlock::addPredecessor(MachineBasicBlock *pred) {
  Predecessors.push_back(pred);
}

void MachineBasicBlock::removePredecessor(MachineBasicBlock *pred) {
  pred_iterator I = std::find(Predecessors.begin(), Predecessors.end(), pred);
  assert(I != Predecessors.end() && "Pred is not a predecessor of this block!");
  Predecessors.erase(I);
}

void MachineBasicBlock::transferSuccessors(MachineBasicBlock *fromMBB) {
  if (this == fromMBB)
    return;

  while (!fromMBB->succ_empty()) {
    MachineBasicBlock *Succ = *fromMBB->succ_begin();
    uint32_t Weight = 0;

    // If Weight list is empty it means we don't use it (disabled optimization).
    if (!fromMBB->Weights.empty())
      Weight = *fromMBB->Weights.begin();

    addSuccessor(Succ, Weight);
    fromMBB->removeSuccessor(Succ);
  }
}

void
MachineBasicBlock::transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB) {
  if (this == fromMBB)
    return;

  while (!fromMBB->succ_empty()) {
    MachineBasicBlock *Succ = *fromMBB->succ_begin();
    uint32_t Weight = 0;
    if (!fromMBB->Weights.empty())
      Weight = *fromMBB->Weights.begin();
    addSuccessor(Succ, Weight);
    fromMBB->removeSuccessor(Succ);

    // Fix up any PHI nodes in the successor.
    for (MachineBasicBlock::instr_iterator MI = Succ->instr_begin(),
           ME = Succ->instr_end(); MI != ME && MI->isPHI(); ++MI)
      for (unsigned i = 2, e = MI->getNumOperands()+1; i != e; i += 2) {
        MachineOperand &MO = MI->getOperand(i);
        if (MO.getMBB() == fromMBB)
          MO.setMBB(this);
      }
  }
}

bool MachineBasicBlock::isPredecessor(const MachineBasicBlock *MBB) const {
  return std::find(pred_begin(), pred_end(), MBB) != pred_end();
}

bool MachineBasicBlock::isSuccessor(const MachineBasicBlock *MBB) const {
  return std::find(succ_begin(), succ_end(), MBB) != succ_end();
}

bool MachineBasicBlock::isLayoutSuccessor(const MachineBasicBlock *MBB) const {
  MachineFunction::const_iterator I(this);
  return std::next(I) == MachineFunction::const_iterator(MBB);
}

bool MachineBasicBlock::canFallThrough() {
  MachineFunction::iterator Fallthrough = this;
  ++Fallthrough;
  // If FallthroughBlock is off the end of the function, it can't fall through.
  if (Fallthrough == getParent()->end())
    return false;

  // If FallthroughBlock isn't a successor, no fallthrough is possible.
  if (!isSuccessor(Fallthrough))
    return false;

  // Analyze the branches, if any, at the end of the block.
  MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
  SmallVector<MachineOperand, 4> Cond;
  const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo();
  if (TII->AnalyzeBranch(*this, TBB, FBB, Cond)) {
    // If we couldn't analyze the branch, examine the last instruction.
    // If the block doesn't end in a known control barrier, assume fallthrough
    // is possible. The isPredicated check is needed because this code can be
    // called during IfConversion, where an instruction which is normally a
    // Barrier is predicated and thus no longer an actual control barrier.
    return empty() || !back().isBarrier() || TII->isPredicated(&back());
  }

  // If there is no branch, control always falls through.
  if (!TBB) return true;

  // If there is some explicit branch to the fallthrough block, it can obviously
  // reach, even though the branch should get folded to fall through implicitly.
  if (MachineFunction::iterator(TBB) == Fallthrough ||
      MachineFunction::iterator(FBB) == Fallthrough)
    return true;

  // If it's an unconditional branch to some block not the fall through, it
  // doesn't fall through.
  if (Cond.empty()) return false;

  // Otherwise, if it is conditional and has no explicit false block, it falls
  // through.
  return FBB == nullptr;
}

MachineBasicBlock *
MachineBasicBlock::SplitCriticalEdge(MachineBasicBlock *Succ, Pass *P) {
  // Splitting the critical edge to a landing pad block is non-trivial. Don't do
  // it in this generic function.
  if (Succ->isEHPad())
    return nullptr;

  MachineFunction *MF = getParent();
  DebugLoc dl;  // FIXME: this is nowhere

  // Performance might be harmed on HW that implements branching using exec mask
  // where both sides of the branches are always executed.
  if (MF->getTarget().requiresStructuredCFG())
    return nullptr;

  // We may need to update this's terminator, but we can't do that if
  // AnalyzeBranch fails. If this uses a jump table, we won't touch it.
  const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
  MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
  SmallVector<MachineOperand, 4> Cond;
  if (TII->AnalyzeBranch(*this, TBB, FBB, Cond))
    return nullptr;

  // Avoid bugpoint weirdness: A block may end with a conditional branch but
  // jumps to the same MBB is either case. We have duplicate CFG edges in that
  // case that we can't handle. Since this never happens in properly optimized
  // code, just skip those edges.
  if (TBB && TBB == FBB) {
    DEBUG(dbgs() << "Won't split critical edge after degenerate BB#"
                 << getNumber() << '\n');
    return nullptr;
  }

  MachineBasicBlock *NMBB = MF->CreateMachineBasicBlock();
  MF->insert(std::next(MachineFunction::iterator(this)), NMBB);
  DEBUG(dbgs() << "Splitting critical edge:"
        " BB#" << getNumber()
        << " -- BB#" << NMBB->getNumber()
        << " -- BB#" << Succ->getNumber() << '\n');

  LiveIntervals *LIS = P->getAnalysisIfAvailable<LiveIntervals>();
  SlotIndexes *Indexes = P->getAnalysisIfAvailable<SlotIndexes>();
  if (LIS)
    LIS->insertMBBInMaps(NMBB);
  else if (Indexes)
    Indexes->insertMBBInMaps(NMBB);

  // On some targets like Mips, branches may kill virtual registers. Make sure
  // that LiveVariables is properly updated after updateTerminator replaces the
  // terminators.
  LiveVariables *LV = P->getAnalysisIfAvailable<LiveVariables>();

  // Collect a list of virtual registers killed by the terminators.
  SmallVector<unsigned, 4> KilledRegs;
  if (LV)
    for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
         I != E; ++I) {
      MachineInstr *MI = I;
      for (MachineInstr::mop_iterator OI = MI->operands_begin(),
           OE = MI->operands_end(); OI != OE; ++OI) {
        if (!OI->isReg() || OI->getReg() == 0 ||
            !OI->isUse() || !OI->isKill() || OI->isUndef())
          continue;
        unsigned Reg = OI->getReg();
        if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
            LV->getVarInfo(Reg).removeKill(MI)) {
          KilledRegs.push_back(Reg);
          DEBUG(dbgs() << "Removing terminator kill: " << *MI);
          OI->setIsKill(false);
        }
      }
    }

  SmallVector<unsigned, 4> UsedRegs;
  if (LIS) {
    for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
         I != E; ++I) {
      MachineInstr *MI = I;

      for (MachineInstr::mop_iterator OI = MI->operands_begin(),
           OE = MI->operands_end(); OI != OE; ++OI) {
        if (!OI->isReg() || OI->getReg() == 0)
          continue;

        unsigned Reg = OI->getReg();
        if (std::find(UsedRegs.begin(), UsedRegs.end(), Reg) == UsedRegs.end())
          UsedRegs.push_back(Reg);
      }
    }
  }

  ReplaceUsesOfBlockWith(Succ, NMBB);

  // If updateTerminator() removes instructions, we need to remove them from
  // SlotIndexes.
  SmallVector<MachineInstr*, 4> Terminators;
  if (Indexes) {
    for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
         I != E; ++I)
      Terminators.push_back(I);
  }

  updateTerminator();

  if (Indexes) {
    SmallVector<MachineInstr*, 4> NewTerminators;
    for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
         I != E; ++I)
      NewTerminators.push_back(I);

    for (SmallVectorImpl<MachineInstr*>::iterator I = Terminators.begin(),
        E = Terminators.end(); I != E; ++I) {
      if (std::find(NewTerminators.begin(), NewTerminators.end(), *I) ==
          NewTerminators.end())
       Indexes->removeMachineInstrFromMaps(*I);
    }
  }

  // Insert unconditional "jump Succ" instruction in NMBB if necessary.
  NMBB->addSuccessor(Succ);
  if (!NMBB->isLayoutSuccessor(Succ)) {
    Cond.clear();
    TII->InsertBranch(*NMBB, Succ, nullptr, Cond, dl);

    if (Indexes) {
      for (instr_iterator I = NMBB->instr_begin(), E = NMBB->instr_end();
           I != E; ++I) {
        // Some instructions may have been moved to NMBB by updateTerminator(),
        // so we first remove any instruction that already has an index.
        if (Indexes->hasIndex(I))
          Indexes->removeMachineInstrFromMaps(I);
        Indexes->insertMachineInstrInMaps(I);
      }
    }
  }

  // Fix PHI nodes in Succ so they refer to NMBB instead of this
  for (MachineBasicBlock::instr_iterator
         i = Succ->instr_begin(),e = Succ->instr_end();
       i != e && i->isPHI(); ++i)
    for (unsigned ni = 1, ne = i->getNumOperands(); ni != ne; ni += 2)
      if (i->getOperand(ni+1).getMBB() == this)
        i->getOperand(ni+1).setMBB(NMBB);

  // Inherit live-ins from the successor
  for (const auto &LI : Succ->liveins())
    NMBB->addLiveIn(LI);

  // Update LiveVariables.
  const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
  if (LV) {
    // Restore kills of virtual registers that were killed by the terminators.
    while (!KilledRegs.empty()) {
      unsigned Reg = KilledRegs.pop_back_val();
      for (instr_iterator I = instr_end(), E = instr_begin(); I != E;) {
        if (!(--I)->addRegisterKilled(Reg, TRI, /* addIfNotFound= */ false))
          continue;
        if (TargetRegisterInfo::isVirtualRegister(Reg))
          LV->getVarInfo(Reg).Kills.push_back(I);
        DEBUG(dbgs() << "Restored terminator kill: " << *I);
        break;
      }
    }
    // Update relevant live-through information.
    LV->addNewBlock(NMBB, this, Succ);
  }

  if (LIS) {
    // After splitting the edge and updating SlotIndexes, live intervals may be
    // in one of two situations, depending on whether this block was the last in
    // the function. If the original block was the last in the function, all
    // live intervals will end prior to the beginning of the new split block. If
    // the original block was not at the end of the function, all live intervals
    // will extend to the end of the new split block.

    bool isLastMBB =
      std::next(MachineFunction::iterator(NMBB)) == getParent()->end();

    SlotIndex StartIndex = Indexes->getMBBEndIdx(this);
    SlotIndex PrevIndex = StartIndex.getPrevSlot();
    SlotIndex EndIndex = Indexes->getMBBEndIdx(NMBB);

    // Find the registers used from NMBB in PHIs in Succ.
    SmallSet<unsigned, 8> PHISrcRegs;
    for (MachineBasicBlock::instr_iterator
         I = Succ->instr_begin(), E = Succ->instr_end();
         I != E && I->isPHI(); ++I) {
      for (unsigned ni = 1, ne = I->getNumOperands(); ni != ne; ni += 2) {
        if (I->getOperand(ni+1).getMBB() == NMBB) {
          MachineOperand &MO = I->getOperand(ni);
          unsigned Reg = MO.getReg();
          PHISrcRegs.insert(Reg);
          if (MO.isUndef())
            continue;

          LiveInterval &LI = LIS->getInterval(Reg);
          VNInfo *VNI = LI.getVNInfoAt(PrevIndex);
          assert(VNI &&
                 "PHI sources should be live out of their predecessors.");
          LI.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI));
        }
      }
    }

    MachineRegisterInfo *MRI = &getParent()->getRegInfo();
    for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
      unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
      if (PHISrcRegs.count(Reg) || !LIS->hasInterval(Reg))
        continue;

      LiveInterval &LI = LIS->getInterval(Reg);
      if (!LI.liveAt(PrevIndex))
        continue;

      bool isLiveOut = LI.liveAt(LIS->getMBBStartIdx(Succ));
      if (isLiveOut && isLastMBB) {
        VNInfo *VNI = LI.getVNInfoAt(PrevIndex);
        assert(VNI && "LiveInterval should have VNInfo where it is live.");
        LI.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI));
      } else if (!isLiveOut && !isLastMBB) {
        LI.removeSegment(StartIndex, EndIndex);
      }
    }

    // Update all intervals for registers whose uses may have been modified by
    // updateTerminator().
    LIS->repairIntervalsInRange(this, getFirstTerminator(), end(), UsedRegs);
  }

  if (MachineDominatorTree *MDT =
      P->getAnalysisIfAvailable<MachineDominatorTree>())
    MDT->recordSplitCriticalEdge(this, Succ, NMBB);

  if (MachineLoopInfo *MLI = P->getAnalysisIfAvailable<MachineLoopInfo>())
    if (MachineLoop *TIL = MLI->getLoopFor(this)) {
      // If one or the other blocks were not in a loop, the new block is not
      // either, and thus LI doesn't need to be updated.
      if (MachineLoop *DestLoop = MLI->getLoopFor(Succ)) {
        if (TIL == DestLoop) {
          // Both in the same loop, the NMBB joins loop.
          DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase());
        } else if (TIL->contains(DestLoop)) {
          // Edge from an outer loop to an inner loop.  Add to the outer loop.
          TIL->addBasicBlockToLoop(NMBB, MLI->getBase());
        } else if (DestLoop->contains(TIL)) {
          // Edge from an inner loop to an outer loop.  Add to the outer loop.
          DestLoop->addBasicBlockToLoop(NMBB, MLI->getBase());
        } else {
          // Edge from two loops with no containment relation.  Because these
          // are natural loops, we know that the destination block must be the
          // header of its loop (adding a branch into a loop elsewhere would
          // create an irreducible loop).
          assert(DestLoop->getHeader() == Succ &&
                 "Should not create irreducible loops!");
          if (MachineLoop *P = DestLoop->getParentLoop())
            P->addBasicBlockToLoop(NMBB, MLI->getBase());
        }
      }
    }

  return NMBB;
}

/// Prepare MI to be removed from its bundle. This fixes bundle flags on MI's
/// neighboring instructions so the bundle won't be broken by removing MI.
static void unbundleSingleMI(MachineInstr *MI) {
  // Removing the first instruction in a bundle.
  if (MI->isBundledWithSucc() && !MI->isBundledWithPred())
    MI->unbundleFromSucc();
  // Removing the last instruction in a bundle.
  if (MI->isBundledWithPred() && !MI->isBundledWithSucc())
    MI->unbundleFromPred();
  // If MI is not bundled, or if it is internal to a bundle, the neighbor flags
  // are already fine.
}

MachineBasicBlock::instr_iterator
MachineBasicBlock::erase(MachineBasicBlock::instr_iterator I) {
  unbundleSingleMI(I);
  return Insts.erase(I);
}

MachineInstr *MachineBasicBlock::remove_instr(MachineInstr *MI) {
  unbundleSingleMI(MI);
  MI->clearFlag(MachineInstr::BundledPred);
  MI->clearFlag(MachineInstr::BundledSucc);
  return Insts.remove(MI);
}

MachineBasicBlock::instr_iterator
MachineBasicBlock::insert(instr_iterator I, MachineInstr *MI) {
  assert(!MI->isBundledWithPred() && !MI->isBundledWithSucc() &&
         "Cannot insert instruction with bundle flags");
  // Set the bundle flags when inserting inside a bundle.
  if (I != instr_end() && I->isBundledWithPred()) {
    MI->setFlag(MachineInstr::BundledPred);
    MI->setFlag(MachineInstr::BundledSucc);
  }
  return Insts.insert(I, MI);
}

/// This method unlinks 'this' from the containing function, and returns it, but
/// does not delete it.
MachineBasicBlock *MachineBasicBlock::removeFromParent() {
  assert(getParent() && "Not embedded in a function!");
  getParent()->remove(this);
  return this;
}

/// This method unlinks 'this' from the containing function, and deletes it.
void MachineBasicBlock::eraseFromParent() {
  assert(getParent() && "Not embedded in a function!");
  getParent()->erase(this);
}

/// Given a machine basic block that branched to 'Old', change the code and CFG
/// so that it branches to 'New' instead.
void MachineBasicBlock::ReplaceUsesOfBlockWith(MachineBasicBlock *Old,
                                               MachineBasicBlock *New) {
  assert(Old != New && "Cannot replace self with self!");

  MachineBasicBlock::instr_iterator I = instr_end();
  while (I != instr_begin()) {
    --I;
    if (!I->isTerminator()) break;

    // Scan the operands of this machine instruction, replacing any uses of Old
    // with New.
    for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
      if (I->getOperand(i).isMBB() &&
          I->getOperand(i).getMBB() == Old)
        I->getOperand(i).setMBB(New);
  }

  // Update the successor information.
  replaceSuccessor(Old, New);
}

/// Various pieces of code can cause excess edges in the CFG to be inserted.  If
/// we have proven that MBB can only branch to DestA and DestB, remove any other
/// MBB successors from the CFG.  DestA and DestB can be null.
///
/// Besides DestA and DestB, retain other edges leading to LandingPads
/// (currently there can be only one; we don't check or require that here).
/// Note it is possible that DestA and/or DestB are LandingPads.
bool MachineBasicBlock::CorrectExtraCFGEdges(MachineBasicBlock *DestA,
                                             MachineBasicBlock *DestB,
                                             bool isCond) {
  // The values of DestA and DestB frequently come from a call to the
  // 'TargetInstrInfo::AnalyzeBranch' method. We take our meaning of the initial
  // values from there.
  //
  // 1. If both DestA and DestB are null, then the block ends with no branches
  //    (it falls through to its successor).
  // 2. If DestA is set, DestB is null, and isCond is false, then the block ends
  //    with only an unconditional branch.
  // 3. If DestA is set, DestB is null, and isCond is true, then the block ends
  //    with a conditional branch that falls through to a successor (DestB).
  // 4. If DestA and DestB is set and isCond is true, then the block ends with a
  //    conditional branch followed by an unconditional branch. DestA is the
  //    'true' destination and DestB is the 'false' destination.

  bool Changed = false;

  MachineFunction::iterator FallThru =
    std::next(MachineFunction::iterator(this));

  if (!DestA && !DestB) {
    // Block falls through to successor.
    DestA = FallThru;
    DestB = FallThru;
  } else if (DestA && !DestB) {
    if (isCond)
      // Block ends in conditional jump that falls through to successor.
      DestB = FallThru;
  } else {
    assert(DestA && DestB && isCond &&
           "CFG in a bad state. Cannot correct CFG edges");
  }

  // Remove superfluous edges. I.e., those which aren't destinations of this
  // basic block, duplicate edges, or landing pads.
  SmallPtrSet<const MachineBasicBlock*, 8> SeenMBBs;
  MachineBasicBlock::succ_iterator SI = succ_begin();
  while (SI != succ_end()) {
    const MachineBasicBlock *MBB = *SI;
    if (!SeenMBBs.insert(MBB).second ||
        (MBB != DestA && MBB != DestB && !MBB->isEHPad())) {
      // This is a superfluous edge, remove it.
      SI = removeSuccessor(SI);
      Changed = true;
    } else {
      ++SI;
    }
  }

  return Changed;
}

/// Find the next valid DebugLoc starting at MBBI, skipping any DBG_VALUE
/// instructions.  Return UnknownLoc if there is none.
DebugLoc
MachineBasicBlock::findDebugLoc(instr_iterator MBBI) {
  DebugLoc DL;
  instr_iterator E = instr_end();
  if (MBBI == E)
    return DL;

  // Skip debug declarations, we don't want a DebugLoc from them.
  while (MBBI != E && MBBI->isDebugValue())
    MBBI++;
  if (MBBI != E)
    DL = MBBI->getDebugLoc();
  return DL;
}

/// Return weight of the edge from this block to MBB.
uint32_t MachineBasicBlock::getSuccWeight(const_succ_iterator Succ) const {
  if (Weights.empty())
    return 0;

  return *getWeightIterator(Succ);
}

/// Set successor weight of a given iterator.
void MachineBasicBlock::setSuccWeight(succ_iterator I, uint32_t weight) {
  if (Weights.empty())
    return;
  *getWeightIterator(I) = weight;
}

/// Return wight iterator corresonding to the I successor iterator.
MachineBasicBlock::weight_iterator MachineBasicBlock::
getWeightIterator(MachineBasicBlock::succ_iterator I) {
  assert(Weights.size() == Successors.size() && "Async weight list!");
  size_t index = std::distance(Successors.begin(), I);
  assert(index < Weights.size() && "Not a current successor!");
  return Weights.begin() + index;
}

/// Return wight iterator corresonding to the I successor iterator.
MachineBasicBlock::const_weight_iterator MachineBasicBlock::
getWeightIterator(MachineBasicBlock::const_succ_iterator I) const {
  assert(Weights.size() == Successors.size() && "Async weight list!");
  const size_t index = std::distance(Successors.begin(), I);
  assert(index < Weights.size() && "Not a current successor!");
  return Weights.begin() + index;
}

/// Return whether (physical) register "Reg" has been <def>ined and not <kill>ed
/// as of just before "MI".
///
/// Search is localised to a neighborhood of
/// Neighborhood instructions before (searching for defs or kills) and N
/// instructions after (searching just for defs) MI.
MachineBasicBlock::LivenessQueryResult
MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI,
                                           unsigned Reg, const_iterator Before,
                                           unsigned Neighborhood) const {
  unsigned N = Neighborhood;

  // Start by searching backwards from Before, looking for kills, reads or defs.
  const_iterator I(Before);
  // If this is the first insn in the block, don't search backwards.
  if (I != begin()) {
    do {
      --I;

      MachineOperandIteratorBase::PhysRegInfo Analysis =
        ConstMIOperands(I).analyzePhysReg(Reg, TRI);

      if (Analysis.Defines)
        // Outputs happen after inputs so they take precedence if both are
        // present.
        return Analysis.DefinesDead ? LQR_Dead : LQR_Live;

      if (Analysis.Kills || Analysis.Clobbers)
        // Register killed, so isn't live.
        return LQR_Dead;

      else if (Analysis.ReadsOverlap)
        // Defined or read without a previous kill - live.
        return Analysis.Reads ? LQR_Live : LQR_OverlappingLive;

    } while (I != begin() && --N > 0);
  }

  // Did we get to the start of the block?
  if (I == begin()) {
    // If so, the register's state is definitely defined by the live-in state.
    for (MCRegAliasIterator RAI(Reg, TRI, /*IncludeSelf=*/true);
         RAI.isValid(); ++RAI) {
      if (isLiveIn(*RAI))
        return (*RAI == Reg) ? LQR_Live : LQR_OverlappingLive;
    }

    return LQR_Dead;
  }

  N = Neighborhood;

  // Try searching forwards from Before, looking for reads or defs.
  I = const_iterator(Before);
  // If this is the last insn in the block, don't search forwards.
  if (I != end()) {
    for (++I; I != end() && N > 0; ++I, --N) {
      MachineOperandIteratorBase::PhysRegInfo Analysis =
        ConstMIOperands(I).analyzePhysReg(Reg, TRI);

      if (Analysis.ReadsOverlap)
        // Used, therefore must have been live.
        return (Analysis.Reads) ?
          LQR_Live : LQR_OverlappingLive;

      else if (Analysis.Clobbers || Analysis.Defines)
        // Defined (but not read) therefore cannot have been live.
        return LQR_Dead;
    }
  }

  // At this point we have no idea of the liveness of the register.
  return LQR_Unknown;
}

redpajama_set_name: RedPajamaGithub


Hi, The lighting to the footpath adjacent to dents close was reported not working in early November, but the ticket has been removed from the site. The 3 lamposts from Marsh Lane towards Stockleys Road are still not working (as of last night). Footpath is very dark.
Hi, Thanks for coming back to me. Your map shows the footpath between Marsh Lane and Stockleys Road. In between the lamp posts indicated as 013 and 006 on the foot path (marked 'path' on the map) There are 3 more lamp posts these are all out of order at the moment. I hope that helps, Best, Matt Blurton.
Hi, Nothing seems to have happened yet on this one yet, first reported early November 2018. Took a photo to show that they are County Council lights, the effected are numbers 1,2 & 3. Thanks.


In this webinar, you will see how purple team tactics and tactical threat intelligence can be used to enhance your security team's capabilities against the next-generation cyber-attacks.
It has been proven that adding security technology cannot completely eliminate cyber-attacks however, training the human can definitely upgrade an organization's security posture. In this webinar, IT security managers and operators will witness how (advanced) adversary simulation, TTP reverse engineering and analysis, scenario-based training, red and blue team synergy and tactical threat intelligence can be used at the core of your training program, to create complete and fully up-to-date IT security professionals.
Purple team tactics and tactical threat intelligence have unfortunately become buzzwords. That's why a demonstration will also be provided regarding how purple team tactics and tactical threat intelligence could have been used to detect a new, undocumented antivirus evasion technique, that was recently uncovered by eLearnSecurity.
Dimitrios holds a B.Sc. in Computer Science from the Athens University of Economics and Business.
Before joining eLearnSecurity, he worked as a Business Information Security Engineer and Information Security Analyst for a major financial institution, and as a Penetration Tester within EY's practice.
Dimitrios specializes in advanced cyber threat simulation, threat intelligence and purple team tactics. He has been engaged on numerous penetration testing activities against critical infrastructure, web applications and mobile applications.
Dimitrios has presented at information security conferences such as BSides and has received acknowledgements from major companies such as IBM Trusteer and LG for finding and reporting vulnerabilities in their web applications.
In the context of his professional career, Dimitrios has received prestigious information security awards in highly competitive contests such as the Retail Banker International Awards.


text:
import logging

import gevent
from gevent.pool import Pool

from mongolock import MongoLockLocked

from . import models
from . import metrics
from . import constants

logger = logging.getLogger(__name__)

def completed_message_task(sleep=10.0, pool_size=10):

    pool = Pool(pool_size)

    while True:
        gevent.sleep(sleep)

        docs = models.MessageStore.objects(completed__ne=1)
        greenlets = []
        for doc in docs:
            greenlets.append(pool.spawn(doc._complete))

        if len(greenlets) > 0:
            pool.join()

def update_metrics_task(sleep=10.0):

    while True:
        gevent.sleep(sleep)
        try:
            metrics.update_metrics()
        except MongoLockLocked, err:
            logger.warning(str(err))
        except Exception, err:
            logger.error(str(err))

def run_all_tasks(completed_sleep=10.0, completed_pool=10, update_metrics_sleep=10.0):
    gevent.spawn(completed_message_task, sleep=completed_sleep, pool_size=completed_pool)
    gevent.spawn(update_metrics_task, sleep=update_metrics_sleep)


text:
More than 100m records potentially lost in huge telecoms breach
11 Jul 2017 0 Data loss, Privacy
Previous: Your gadget could save your life: smart device phones police
Next: Two-factor via your mobile phone – should you stop using it?
by Kim Crawley
India's newest telecoms provider is investigating what could be the country's biggest data breach, according to local reports, with the records of potentially more than 100m subscribers having been exposed online.
The data apparently belonging to Jio Reliance subscribers was posted on a website called magicapk, which has since gone offline, and included:
First, middle, and last names
Mobile numbers
Aadhaar numbers
Dates and times of SIM card activations
Jio is the newest player in India's wireless telecommunications sector. A subsidiary of Reliance Industries, it launched its 4G cellular network and services in September 2016, and at the end of the first quarter of 2017, had just over 108m subscribers out of India's total population of some 1.3bn.
The inclusion of Aadhaar numbers adds to the concern, as the scheme, set up by the Indian government in 2009 to register every citizen with a 12-digit number and their biometrics, has faced sharp criticism over its scope and reach, with critics calling it "Orwellian". The scheme now covers pretty much the entire population, having registered 1.15bn people.
Critics have included the National Advisory Council, Citizens Forum for Civil Liberties, and the Indian Social Action Forum. Now that these details seem to have been part of the data leaked from Jio, those concerns are starting to look prophetic.
Jio moved to reassure subscribers, insisting that the data that had been exposed was "unauthentic", adding:
Prima facie, the data appears to be unauthentic. We want to assure our subscribers that their data is safe and maintained with highest security. We want to assure our subscribers that their data is safe and maintained with highest security. Data is only shared with authorities as per their requirement.
However, many Indians on the /r/India forum on Reddit claimed that at least some of the details exposed were genuine, with one saying:
I used an unique email (address) which I have not used anywhere else and can confirm leaked data is from Jio's database.
Another added:
I got my number activated yesterday only, and it's in the leaked database which shows an email id which I haven't given to anybody else. So no, it's not three months old.
Another Reddit user shared a screenshot of a post on a forum hosted in the Onion network claiming to have the data for sale.
If the data has indeed come from Jio, it's a big setback for the company, which has grand plans to conquer India's mobile market.
Apple security updates are out – and not a Log4Shell mention in sight
Cryptocurrency startup fails to subtract before adding, loses $31m
S3 Ep60: Exchange exploit, GoDaddy breach and cookies made public [Podcast]

redpajama_set_name: RedPajamaCommonCrawl


Hi-Vis lightweight polyester mesh material.
Chest pocket with hook and loop closure.
Deep and wide inside pocket.
Vest: 105 gsm mesh polyester.
Reflective Striping: One 2" silver reflective stripe applied horizontally across lower chest.
Two 2" silver reflective stripes run vertically from top of horizontal stripes, over shoulders to top of back side horizontal stripe.
Pockets: 5.5" x 6.5" outside left chest pocket.
7.5" x 7.5" inside right patch pocket.


Additionally, the Ocmulgee River flows a mere ten miles north of the city limits. The Ben Hill County Landing on Mobley Bluff Road off of Highway 107 East is a wooded, natural setting for camping, barbecues, fishing, and boating (boat launch) with 20 primitive campsites and 15 campsites with water and electricity (30 amp). For more information on the Ocmulgee River Basin, visit Georgia River Network, Ocmulgee River Water Trail, or contact Fitzgerald's Cypress Slough Outfitters.


Just a reminder that Dr. Alpert will be back in the office on Tuesday, but our hygiene staff (on Monday) and front office crew are here if you need us! Have a wonderful weekend!
Next week July 18th through July 23rd, our office will be closed; however, we will have someone answering the phones. Have a great week!


text:
package com.alibaba.druid.bvt.filter;

import java.sql.Connection;
import java.sql.PreparedStatement;
import java.sql.ResultSet;
import java.sql.SQLException;

import org.junit.Assert;
import junit.framework.TestCase;

import com.alibaba.druid.mock.MockConnection;
import com.alibaba.druid.mock.MockDriver;
import com.alibaba.druid.mock.MockPreparedStatement;
import com.alibaba.druid.pool.DruidDataSource;
import com.alibaba.druid.stat.JdbcSqlStat;
import com.alibaba.druid.util.JdbcUtils;

public class StatFilterExecuteFirstResultSetTest extends TestCase {

    private DruidDataSource dataSource;

    protected void setUp() throws Exception {
        dataSource = new DruidDataSource();

        dataSource.setUrl("jdbc:mock:xxx");
        dataSource.setFilters("stat");
        dataSource.setTestOnBorrow(false);

        MockDriver driver = new MockDriver() {

            public MockPreparedStatement createMockPreparedStatement(MockConnection conn, String sql) {
                return new MyMockPreparedStatement(conn, sql);
            }
        };

        dataSource.setDriver(driver);

        dataSource.init();
    }

    protected void tearDown() throws Exception {
        JdbcUtils.close(dataSource);
    }

    public void test_stat() throws Exception {

        Assert.assertTrue(dataSource.isInited());
        final String sql = "select 1";

        Connection conn = dataSource.getConnection();

        PreparedStatement stmt = conn.prepareStatement(sql);
        boolean firstResult = stmt.execute();
        Assert.assertTrue(firstResult);

        ResultSet rs = stmt.getResultSet();
        rs.next();
        rs.close();

        stmt.close();

        conn.close();

        JdbcSqlStat sqlStat = dataSource.getDataSourceStat().getSqlStat(sql);

        Assert.assertEquals(1, sqlStat.getHistogramSum());

        Assert.assertEquals(1, sqlStat.getExecuteAndResultHoldTimeHistogramSum());
    }

    static class MyMockPreparedStatement extends MockPreparedStatement {

        public MyMockPreparedStatement(MockConnection conn, String sql){
            super(conn, sql);
        }

        public boolean execute() throws SQLException {
            return true;
        }

        public ResultSet getResultSet() throws SQLException {
            return getConnection().getDriver().executeQuery(this, getSql());
        }
    }
}


Pot Size 4.5" 3.5" 6"
This plants origin is from seed grown plants in the Imperial Garden in Vienna. It is almost certainly of hybrid origin. This plant has never been found in habitat. The plant grows best in full sun to partial sun. In full sun the stems take on a purple tone. Water in the summer but let it dry out during the winter (when dormant, this plant is prone to rot). The flower is a dark maroon.


text:
Q: stream an AWS S3 object in binary From what I found both libraries aws-sdk and aws-s3 (Ruby) provide methods to download S3 object data only in string chunks. I'd like to be able to read it in binary chunks, so that it resembles file I/O and be more efficient. Does anyone know if there is a supported way to do it? One hack that I thought about is creating an access URL for the S3 object (S3 functionality) and download the file with some HTTP client library. What's a good library for that in Ruby?
P.S.: I need to stream data, so that I can decrypt files on-the-fly. AWS has client-side encryption library only in Java SDK.

A: So, it turns out in ruby (since 1.9?) a string of encoding ASCII-8BIT is used as a binary block, so you have to work with that. P.S.: net/http is a ruby http client library that can be used to read response body.

redpajama_set_name: RedPajamaStackExchange


text:
Jean Winand (né à Liège le ) est un égyptologue belge. Il est maître de recherches honoraire du Fonds national de la recherche scientifique (FNRS), et professeur ordinaire à l'Université de Liège, où il dirige le service d'égyptologie. De 2010 à 2017, il a été doyen de la Faculté de Philosophie et Lettres de l'Université de Liège.

Biographie
Il est membre de l'Académie royale de Belgique, classe des lettres, depuis 2017.

Après des études de lettres classiques et des études en langues et littératures orientales (égyptien et akkadien), il soutient une thèse de doctorat consacrée à la morphologie verbale en néo-égyptien, puis une « thèse d'agrégation de l'enseignement supérieur » sur Temps et aspect en égyptien ancien. Une approche sémantique. Ses travaux portent actuellement sur la langue et les textes de l'Égypte ancienne.

Il est le fondateur et le co-directeur (avec Stéphane Polis) du projet Ramses, lancé en 2006.

En avril 2014, il se présente à l'élection rectorale de l'Université de Liège et échoue au premier tour avec 24,72% des suffrages.

Il a été le co-président du comité des programmes de la première conférence mondiale des humanités, qui s'est tenue à Liège, sous l'égide de l'UNESCO, du 6 au .

En , Jean Winand est élu Premier Vice-recteur de l'université de Liège pour un mandat de quatre ans. Il se présente comme un défenseur de la place de la recherche fondamentale à l'université et de son articulation avec l'enseignement.

En avril 2022, il se présente à nouveau à l'élection rectorale de l'Université de Liège. Il récolte 39,68% des suffrages au second tour et échoue à s'imposer face à Anne-Sophie Nyssen.

Prix et distinctions

Prix annuel de la Classe des Lettres de l'Académie royale de Belgique, 1988.
Prix des Amis de l'Université de Liège, 1993.
Prix des Alumni de la Fondation universitaire, 1998.
 de la Fondation von Humboldt, 2015.
Chevalier dans l'ordre des Palmes académiques (France).

Ouvrages

 Le Voyage d'Ounamon. Index verborum, concordance, relevés grammaticaux, collection « Ægyptiaca Leodiensia », , Liège, 1988.
 Les hiérothytes. Recherche institutionnelle, collection « Académie royale de Belgique - Classe des Lettres », -4, Bruxelles, 1990.
 Études de néo-égyptien.  : La morphologie verbale, collection « Ægyptiaca Leodiensia », , Liège, 1992.
 L'art du parfum, Éditions Le Temps Apprivoisé, Paris, 1993.
 (avec Michel Malaise), Grammaire raisonnée de l'égyptien classique, collection « Ægyptiaca Leodiensia », , Liège, 1999.
 Temps et aspect en ancien égyptien. Une approche sémantique, collection « Probleme der Ägyptologie », , Éditions Brill, Leyde, 2006.
 Les hieroglyphes égyptiens, Paris, 2013, Presses universitaires de France, coll. Que-sais-je ?, 3980.
 Aux origines de l'écriture. Le cas de l'Egypte ancienne, Bruxelles, Académie royale, 2013, coll. L'Académie en poche, 20.
 La réception des hiéroglyphes de l'Antiquité aux Temps modernes, Bruxelles, Académie royale, 2013, coll. L'Académie en poche, 21.
 Les Pharaons. Histoire personnelle, Paris, 2017, Presses universitaires de France.
 L'Université à la croisée des chemins : Plaidoyer pour une université de la culture, Bruxelles, Académie royale, 2018, coll. L'Académie en poche''.

Notes

Liens externes

 Jean Winand sur ulg.academia.edu
 Jean Winand sur academieroyale.be

Index égyptologique
Professeur à l'université de Liège
Égyptologue belge
Naissance en février 1962
Naissance à Liège

redpajama_set_name: RedPajamaWikipedia


text:
Official Journal of the European Communities, L 203, 03 August 1999
of the European Communities
English edition Legislation
Contents I Acts whose publication is obligatory
* Decision No 1719/1999/EC of the European Parliament and of the Council of 12 July 1999 on a series of guidelines, including the identification of projects of common interest, for trans-European networks for the electronic interchange of data between administrations (IDA) 1
* Decision No 1720/1999/EC of the European Parliament and of the Council of 12 July 1999 adopting a series of actions and measures in order to ensure interoperability of and access to trans-European networks for the electronic interchange of data between administrations (IDA) 9
* Council Regulation (EC) No 1721/1999 of 29 July 1999 laying down certain control measures in respect of vessels flying the flag of Non-Contracting Parties to the Convention on the Conservation of Antarctic Marine Living Resources 14
* Council Regulation (EC) No 1722/1999 of 29 July 1999 on the import of bran, sharps and other residues of the sifting, milling or other working of certain cereals originating in Algeria, Morocco and Egypt and the import of durum wheat originating in Morocco 16
Commission Regulation (EC) No 1723/1999 of 2 August 1999 establishing the standard import values for determining the entry price of certain fruit and vegetables 18
Commission Regulation (EC) No 1724/1999 of 2 August 1999 on the supply of cereals as food aid 20
Commission Regulation (EC) No 1725/1999 of 2 August 1999 on the supply of split peas as food aid 25
* Commission Regulation (EC) No 1726/1999 of 27 July 1999 Implementing Council Regulation (EC) No 530/1999 concerning structural statistics on earnings and on labour costs as regards the definition and transmission of information on labour costs 28
* Commission Regulation (EC) No 1727/1999 of 28 July 1999 laying down certain detailed rules for the application of Council Regulation (EEC) No 2158/92 on protection of the Community's forests against fire 41
* Council Directive 1999/74/EC of 19 July 1999 laying down minimum standards for the protection of laying hens 53
II Acts whose publication is not obligatory
1999/526/EC
* Commission Decision of 14 July 1999 laying down special conditions governing imports of fishery and aquaculture products originating in PanamaText with EEA relevance (notified under document number C(1999) 2058) (1) 58
* Commission Decision of 14 July 1999 laying down special conditions governing imports of fishery and aquaculture products originating in OmanText with EEA relevance (notified under document number C(1999) 2059) (1) 63
* Commission Decision of 14 July 1999 laying down special conditions governing imports of fishery and aquaculture products originating in YemenText with EEA relevance (notified under document number C(1999) 2060) (1) 68
* Commission Decision of 14 July 1999 amending Decision 94/766/EC laying down special conditions governing the import of fishery products originating in TaiwanText with EEA relevance (notified under document number C(1999) 2061) (1) 73
* Commission Decision of 14 July 1999 amending Decision 95/453/EC laying down special conditions for the import of live bivalve molluscs, echinoderms, tunicates and marine gastropods originating in the Republic of KoreaText with EEA relevance (notified under document number C(1999) 2062) (1) 76
* Commission Decision of 14 July 1999 amending Decision 97/427/EC laying down special conditions for the import of live bivalve molluscs, echinoderms, tunicates and marine gastropods originating in AustraliaText with EEA relevance (notified under document number C(1999) 2064) (1) 77
* Commission Decision of 14 July 1999 amending Decision 97/296/EC drawing up the list of third countries from which the import of fishery products is authorised for human consumptionText with EEA relevance (notified under document number C(1999) 2065) (1) 78


CLEVELAND – Genetics researchers from Case Western Reserve School of Medicine have identified a novel long non-coding RNA (lncRNA), dubbed DACOR1, that has the potential to stymie the growth of tumor cells in the second-most deadly form of cancer in the U.S. — colorectal cancer.
The researchers found that this lncRNA is present in cells of healthy colons, but becomes suppressed in those carrying the disease. More importantly, this lncRNA interacts with a key enzyme known as DNMT1 that has important functions in all healthy cells of the body. Thus, the authors applied a name to this novel lncRNA — DACOR1, which stands for DNMT1-Associated Colon Cancer Repressed lncRNA-1.
The scientists' next challenge is to determine how to deliver DACOR1 to tumors where it may be able to slow, or even stop, the spread of malignant cells. The researchers' initial findings appeared in this month's edition of Human Molecular Genetics.
DNA methylation affects the molecule's function, including gene expression. Whenever a biological process affects genetic expression, the potential exists to promote health or cause disease. To understand what factors decide which outcomes in humans, scientists first identify how different molecules are supposed to act — and, in turn, the elements that make their functions go awry.
Khalil, a member of the Case Comprehensive Cancer Center, began the journey to the team's discovery with a hypothesis — namely, that lncRNA molecules directly regulate the enzyme DNMT1 that adds methylation to DNA. This ongoing chemical modification of our DNA — a process known as DNA methylation — can help prevent cancer by maintaining a healthy level of gene expression, which in turn controls the extent of cell growth in the body.
During their research, investigators found that specific lncRNAs regulate DNA methylation in specific human genes. Researchers also sought clues on how lncRNAs affect normal tissue versus cancerous tissue and characterized one particular lncRNA, DACOR1, which is present in healthy colon tissue but missing from colon cancer tissue.
Methylation is a process where a methyl group is added into critical points along our DNA. In cancer, many regions of the DNA are not methylated, leading to untimely gene expression, and unwanted cell reproduction. In some instances, genes that trigger cancer, known as oncogenes, spring into action.
DNA methylation occurs through enzymes known as DNA methyltransferases (DNMTs), and there are only three of them in the human genome: DNMT1, DNMT3A and DNMT3B. DNMT1 is the most important one because of its activity in all cell types, so investigators focused on how a subset of lncRNAs might interact with DNMT1. Khalil's hypothesis was that a subset of lncRNAs interacts with DNMT1 and that cancer cells alter the expression of these specific lncRNAs to change the location of where the DNMT1 enzyme triggers methylation along the DNA.
In their research, Khalil's team first isolated 148 lncRNAs from 8,300 known lncRNAs. These 148 lncRNAs are associated with DNMT1 in colon cells. To test their hypothesis in depth, the researchers focused their study on a key lncRNA that becomes suppressed in colon cancer — DACOR1.
Then investigators obtained normal and cancerous colon tissue from public datasets and compared how DACOR1 acted within each. They found that DACOR1 is active in normal colon tissue but repressed in colon cancer tissue. Similar results were found in studying 21 colon cancer cell lines from the Markowitz Laboratory of Genetic Colon Cancer Research at Case Western Reserve — DACOR1 is suppressed in colon cancer.
Investigators also pondered whether returning DACOR1, and therefore, DNA methylation, to colon cancer cells would slow their growth. The answer was yes. In two colon cancer cell lines, the DNA methylation pattern changed when the lncRNA DACOR1 was injected into the cells. Additionally, investigators placed DACOR1 into cancer cells to track where this specific lncRNA went. DACOR1 returned to those cancer-suppressing regions of the DNA where it had been missing in the cancer cells.
"These experiments showed us that DNMT1-associated lncRNAs are regulating DNA methylation and subsequent gene expression, which controls cell growth," Khalil said.
Next steps for Khalil's team will be more research into DACOR1 and the effects of other lncRNAs believed to suppress colon cancer. Perhaps defects in a number of lncRNAs work in synergistic unison to drive the onset of colon cancer. Eventually, the potential is there to develop a therapy that would reactivate key lncRNAs in their job of maintaining normal, controlled cell growth and prevent unbridled cell growth leading to cancer. If nothing else, the lack of colon cancer-repressing genes could serve as an early-detection biomarker for colon cancer.
These studies were supported by new investigator startup funds from Case Western Reserve University School of Medicine and National Institutes of Health awards P50CA150964, UO1 CA152756, R37-DK060596, and RO1-DK053307. Also, the Clinical and Translational Science Collaborative of Cleveland distributed funds to this research from the Case Western Reserve University Core Utilization Pilot.
Joining Khalil in this research project from Case Western Reserve University School of Medicine were Callie R. Merry, Megan E. Forrest, Jessica N. Sabers, Victoria Moran, Xing-Huang Gao and Maria Hatzoglou and Zhenghe Wang, all of the Department of Genetics and Genome Sciences; Sanford Markowitz, Lydia Beard and Mark W. Jackson, all of the Case Comprehensive Cancer Center.
Founded in 1843, Case Western Reserve University School of Medicine is the largest medical research institution in Ohio and is among the nation's top medical schools for research funding from the National Institutes of Health. The School of Medicine is recognized throughout the international medical community for outstanding achievements in teaching. The School's innovative and pioneering Western Reserve2 curriculum interweaves four themes–research and scholarship, clinical mastery, leadership, and civic professionalism—to prepare students for the practice of evidence-based medicine in the rapidly changing health care environment of the 21st century. Nine Nobel Laureates have been affiliated with the School of Medicine.


OhKataKata will be share a new article Quotes About Love, for you need a word to be given to your partner. Can the boyfriend, girlfriend, wife, husband, your parent and other person. This article for what ? For you send to other person or someone special in your life, a love story can make happy because be found pair romantic in a world. Like a Romeo and Juliet, him make a story love very romantic, few story can make a study for we. Why? Because someone can make a story love with a partner have a problem and happy story. OhKataKata shared a little article which maybe can make your story love have a good tidings and no case in your story.
Love can make destiny changed, so that the birds can fly freely in the sky.
Love can make us turn to be arrogant and not to be outdone by our flaws.
Love is painful, and there is no cure in this world, except the precious and people who really we love.
Love like fire and love that can make us become someone very pendedam.
Only with love we can stop hunger.
Love is like a leaf, if it would fall fertilize the young shoots.
Love makes us protect and respect, even though we love violence and crime, which is expected at that time most of us hate to be the most useful.
With sincere love we could be people who understand and who can be trusted others.
True love is only for people who are willing to sacrifice and give something valuable to his partner even though it was very precious to him.
Love can make people do not have direction and purpose.
Love can make us silent with what he did even though we did not like it.
called pure love are those who are willing to sacrifice for the couple happiness.
Love can make us a trustworthy and always keep their promises.
Love can be something very scary and it could even be something very disgusting.
Love can make us believe with our spouses.
Love can turn, even if he is dead.
Love is something in common with him, and will Rifal for us.
Love can make us become a stronger person and sometimes makes us to be very shy.
Love can make everyone can understand and create peace.
Love can make us into a dark eye or into the light of hope for others.
Love can make peace and even an association.
If love has been betrayed then he will leave vengeance in the chest.
I hope my little article can make a someone and their spouses get a happy story and happy ending in your love with Quotes About Love. OhKataKata can be a new article at tomorrow and sometime again. Thanks before for you sharing this article, and give G+ and more for you to me.


text:
Help! They Are Ignoring My ...
Help! They Are Ignoring My Kid's IEP?
ESME's Anna Stewart
Key steps Solo Moms can take to ensure IEP compliance
I just got off the phone with yet another upset Solo Mom who reports that her 10th-grade son is not getting the services that are written into his individualized education program (IEP). "His IEP says he should be receiving direct special-education support for almost half of his school day," Nancy said. "But they aren't providing the paraprofessional support in his general-education classes. He doesn't need constant help but some support so he can access the instruction and activities."
I asked if she had gone to the special-education teacher/case manager with her concerns. She had. She showed the teacher the IEP with the hours and the accommodations. The teacher agreed that it should happen but told her, "We don't have any paraprofessionals to help. The district cut our hours, and we can't cover everyone."
Lesson 1: The IEP must be followed. Lack of resources (though a reality) is not a legitimate excuse. Directing staff's attention to the IEP as a guide is very appropriate.
Nancy moved on to the principal and told him what was going on. "We just don't have the help we need," he told her. "Sorry."
The teacher offered to have her son stay in the special-education classroom. But Nancy knows that her son, who has autism, is capable of learning and growing as long as his IEP is being implemented. He wants to work and be in with other students. She says to the teachers and administrators, "How will my son learn how to be with peers without disabilities if he is not in the room? If the district's goal is to prepare all students for success as adults, then why would you suggest he be separated from his future coworkers, employers, friends, landlords, and community?"
Lesson 2: Go to the school principal to share your concerns. That is the principal's job, and the principal can't direct staff if he or she doesn't know what is going on. It is also important to go through all the channels and document everything in writing in case you have to go outside the school for help.
After our phone call, Nancy sent an email (keeping a written record) to the special-education teacher and the principal voicing her concerns and her conversations and the lack of any change. She included an expectation that there would be action by the end of the week.
I talked to Nancy about her options if things were not resolvable at the school level.
Lesson 3: If things are not resolvable at the school level or within the district, you can file a complaint with your state department of education. Students with IEPs have three levels of dispute resolution:
State complaint. Complaints are designed to address whether the school is following the procedures of the law and if the IEP requirements are being followed. The bottom line is if the school is following the law closely enough for the student to receive some educational benefit, then the school is likely in compliance. Parents can file a complaint if there has been a specific violation of the Individuals with Disabilities Education Act, such as not following procedures or in implementation of the IEP (e.g., not providing the hours of direct therapy stated on the IEP). Lawyers can help parents write the complaint but are not required. A Solo Mom can write a detailed, fact-filled description of the issue and file it with the state. The state reviews it and decides whether to investigate. If the state decides to investigate, it will request more information from the school and the parent to make a decision.
Mediation. Mediation can be requested before or after a state complaint is filed. The state assigns an independently trained mediator to the case. The mediator can't make any decisions; the two parties must agree on a plan that becomes a binding agreement. Mediation issues can include assessments, related services, placement, location of program and services, or other procedural issues. It gives both parties a chance to talk through their concerns, listen to the other party, and, with the mediator's help, come to a mutual agreement. This option is free, though preparing for it will take a lot of time. Lawyers cannot represent either party in a mediation. Mediation does not focus on who is right or wrong but on reaching an agreement.
Due process. This is the most involved, expensive, and exhausting option to resolve issues. It involves lawyers, witnesses, and lots of paperwork, and it is contentious in nature. It is the last resort if you feel that your child's rights to a free and appropriate education are being substantially violated. The due-process hearing can address what should be in the IEP in addition to whether it is being followed correctly.
Nancy's concerns were that the hours stated on the IEP for direct support were not being provided. She could request a mediation or file a complaint. This is an issue of compliance.
The school told her that her son could spend his time in the special-education classroom instead of in general education. That becomes a placement issue and will likely not be resolved with a complaint but could be resolved through mediation, and, as a last resort, through a due-process hearing.
It's always better to try and resolve things at the school level, which Nancy was able to do. After her follow-up email, the school hired another aide and was able to then fully implement her son's IEP. Now she can go back to being mom, and her son can get his education.
Join our confidential community of Sisters to connect with other Solo Moms who are parenting kids with special needs.
Anna Stewart is ESME's Kids with Special Needs Resource Guide and the Solo Mom of a daughter and two sons on the brink of adulthood. She's a champion for the rights of people living with disabilities and those who love them.
IEP school special needs
Latest Special Needs
The Link Between ADHD and Substance Abuse
Suggestions for helping children with ADHD stay on a healthy path
Practical Advice When Transitioning from Special Education
When an IEP is suddenly taken away


International Terminal. After the Security Checkpoint, the lounge is located near Gate 3.
Relax in style and comfort at the Bangkok Airways Boutique Lounge, your oasis away from the hectic airport terminal. Savor a wide range of amenities designed to ease your travel pain, including a variety of snacks, wonton soup, beer, complimentary fast Wi-Fi, and internet terminals. NOTE: Access to this lounge is complimentary for all Bangkok Airways passengers. NOTE: Children under 2 years old are admitted free with an adult. NOTE: Beer is available, but not wine.


text:
#BrigsbyBear
Kyle Mooney, Claire Danes, Mark Hamill, Greg Kinnear, Matt Walsh, Michaela Watkins, Andy Samberg, Jane Adams, Beck Bennett, Jorge Lendeborg Jr., Kate Lyn Sheil, Ryan Simpkins
drug testing | dysfunctional family | elopement | independent psychiatric examination | insane | nervous | obsession | rolling | tripping | wasted
3,4-Methylenedioxymethamphetamine | ethyl alcohol | marijuana
James' sister Aubrey tells their parents Greg and Louise, referring to James, "You're like freaking him out." (0:21)
Family session with psychiatric professional Emily (0:25)
Aubrey's friend Merideth, on seeing James: "Crazy." (0:31)
Merideth tells James, "That's insane."
James: "It's insane." (0:34)
Merideth tells James, ""My first time rolling was intense too." (0:36)
James hallucinates. Sun Snatcher asks him, "How are you possibly this wasted right now.?" (0:38)
His friend Spencer tells James, "You just started tripping." (0:39)
Spencer tells James, "Dude, this is insane."
"... and I got a drug test coming up in a couple weeks... (0:50)
Spencer tells Merideth, "Logan is bringing weed." (0:59)
Merideth tells James, "You were wasted."
James: "I was so nervous." (1:01)
Aubrey tells James, "Dude, I'm obsessed with this song." (1:02)
Deputy Bander tells James, "Officers say they found marijuana and an open container of alcohol in the truck..."
James: "The marijuana smokings, the bad drinks: Those were mine." (1:06)
Family session with Emily (1:07)
Greg tells Louise, referring to James, "He's obsessed. (1:15)
James in a psychiatric hospital (1:15)
Emily meets with James. (1:17)
James elopes from the hospital. (1:19)
Louise tells James, "In a couple of weeks you're going to have an independent evaluation...." (1:22)


text:
Are there any movies based on Sidney Sheldon books?
Posted on September 14, 2022 by Mary Andersen
Films as writer
What should I read if I like Sidney Sheldon?
Is the author Sidney Sheldon still alive?
Is Tell Me Your Dreams based on a true story?
Who writes books like Jackie Collins?
What is the best Agatha Christie mystery?
Is Sidney Sheldon married?
What was Sidney Sheldon's last book?
Who is Daniel Cooper in if tomorrow comes?
What was Jackie Collins first book?
What are the best books by Sidney Sheldon?
When was Sidney Sheldon born?
When did Sidney Shelton pass away?
Mr. District Attorney in the Carter Case (1941)
She's in the Army (1942)
The Bachelor and the Bobby-Soxer (1947)
Easter Parade (1948)
The Barkleys of Broadway (1949)
Annie Get Your Gun (1950)
Nancy Goes to Rio (1950)
Three Guys Named Mike (1951)
Read-Alikes for Sidney Sheldon
Mary Higgins Clark. Mary Higgins Clark's books are world-wide bestsellers.
Iris Johansen.
Is Sidney Sheldon a good writer?
American writer and Hollywood producer, Sidney Sheldon has been a master thriller writer, an unsurpassed favourite among millions of readers.
January 30, 2007Sidney Sheldon / Date of death
Tell Me Your Dreams by Sidney Sheldon is a work of fiction, but is based on several actual cases.
Where can I watch if tomorrow comes?
Watch If Tomorrow Comes | Prime Video.
Authors similar to Jackie Collins
Danielle Steel. 11,601 followers.
Jacqueline Susann. Author of 22 books including Valley of the Dolls.
Minette Walters. Author of 51 books including The Sculptress.
Harold Robbins. 366 followers.
Judith Krantz. 269 followers.
Jilly Cooper. 521 followers.
Shirley Conran. 89 followers.
Tilly Bagshawe.
The top 10 Agatha Christie mysteries
The ABC Murders (1935)
And Then There Were None (1939)
Five Little Pigs (1943)
Crooked House (1949)
A Murder is Announced (1950)
Endless Night (1967)
Curtain: Poirot's Last Case (1975, but written during the second world war)
What genre is Dan Brown?
Genre Thriller, adventure, mystery, conspiracy
Notable works Digital Fortress Deception Point Angels & Demons The Da Vinci Code The Lost Symbol Inferno Origin
Spouse Blythe Newlon   ( m. 1997; div. 2019)
Relatives Gregory W. Brown (brother)
Alexandra Sheldonm. 1989–2007
Jorja Curtrightm. 1951–1985Jane Kaufman Hardingm. 1945–1948
Sidney Sheldon/Spouse
You Afraid of the Dark?
Sidney Sheldon (1917 – 2007) The Naked Face was published in 1970 when Sheldon was 53, and his last novel Are You Afraid of the Dark? (2004) was published just a few years before his death in 2007 just shy of his 90th birthday.
Is there a movie called If Tomorrow Comes?
If Tomorrow Comes is a 1971 American TV film.
Daniel Cooper is a clever sociopath who works as an insurance investigator. He is in charge of investigation of stolen 'Renoir' painting that Tracy was framed on. He seems to be the only one capable of matching Tracy's brilliance, although he never manages to catch her red-handed.
The World Is Full of Married Men
After minor appearances in such television series as Danger Man and The Saint, Collins gave up on pursuing an acting career, although she did play briefly on the television series Minder in 1980. Her first book, The World Is Full of Married Men (1968), became a best-seller.
Who writes like Dan Brown?
9 Authors Like Dan Brown
Daniel Silva.
Michael Crichton.
John Grisham.
Sidney Sheldon.
David Baldacci.
Ian Caldwell.
Jeffrey Archer.
Frederick Forsyth.
The Best Sidney Sheldon's Books 1 Tell Me Your Dreams by Sidney Sheldon 3. 9 Are You Afraid of the Dark? by Sidney Sh 10 The Naked Face by Sidney Sheldon 3.55 av 11 A Stranger in the Mirror by Sidney Sheld 12 Morning, Noon & Night by Sidney Sheldon
Sidney Sheldon (1917–2007) Sheldon was born in Chicago on February 17, 1917. He began writing as a youngster and at the age of ten he made his first sale of a poem for $10.
Who is Sheldon Sheldon?
Sheldon was born in Chicago on February 17, 1917. He began writing as a youngster and at the age of ten he made his first sale of a poem for $10. During the Depression, he worked at a variety of jobs and while attending Northwestern University he contributed short plays to drama groups.
Sidney Shelton passed away on January 30, 2007, less than two weeks away from what would have been his 90th birthday on February 11. See more »


Hempnall is one of those large, rather characterless villages you find either side of the Suffolk border. However, it is also centre of one of the friendliest group of parishes in the county - the seven Hempnall benefice churches are open every day, a warm welcome awaiting visitors. The group includes famous gems Shelton and Fritton, but most are just ordinary working churches, well-use and well-loved. All in all, the group is a delight.
St Margaret today is essentially the work of restorers. Nave aisles survived a fire in the late 14th century, but a fire in the 17th century scoured internal medieval survivals, and the Victorians rebuilt the east end, getting rid of the ruined chancel. The result is a building that is almost perfectly square. In the 1970s, the area beneath the tower was refitted, the new balcony accessed by a gorgeous spiral staircase.
When Mortlock came this way in the 1980s, he found this space filled with 19th century pews; but these have now gone, and the inside is stunningly beautiful, a wide, light space with modern chairs and the altar brought forward into the nave. In one corner there is a chapel dedicated to the patron Saint. It all reminded me very much of modern Catholic churches.
The medieval font survives, an Georgian pulpit is tucked away awkwardly up one corner, but the warmth, and the light, and the feeling of a living faith community infuses everything. A place to uplift the heart.


As last week, the words for this week are eat and taste, and see. For both weeks, the readings are similar. The context for the words is Eucharistic. What there is for which to be thankful is the LORD in his Eucharistic presence.
Pope John-Paul II's Apostolic Letter, Rosarium Virginia Mariae, does not cite any specific Scripture from the Twentieth Sunday in Ordinary Time. The following section fits no special readings. Mentioning flavor (below) relates to eat, taste, and see.
38. The Rosary can be recited in full every day, and there are those who most laudably do so. In this way it fills with prayer the days of many a contemplative, or keeps company with the sick and the elderly who have abundant time at their disposal. Yet it is clear—and this applies all the more if the new series of mysteria lucis is included—that many people will not be able to recite more than a part of the Rosary, according to a certain weekly pattern. This weekly distribution has the effect of giving the different days of the week a certain spiritual "color," by analogy with the way in which the Liturgy colors the different seasons of the liturgical year.
This indication is not intended to limit a rightful freedom in personal and community prayer, where account needs to be taken of spiritual and pastoral needs and of the occurrence of particular liturgical celebrations which might call for suitable adaptations. What is really important is that the Rosary should always be seen and experienced as a path of contemplation. In the Rosary, in a way similar to what takes place in the Liturgy, the Christian week, centered on Sunday, the day of Resurrection, becomes a journey through the mysteries of the life of Christ, and he is revealed in the lives of his disciples as the Lord of time and of history.
This section of Proverbs extols the virtue of Wisdom as a type of banquet of understanding. In other places, Proverbs sets out Wisdom herself.
Jerome uses ancillas for maidens, the same word Mary used in the Magnificat, the handmaid of the Lord.
Simple is parvulus in the Latin, carrying the sense of childlike, emotionally and intellectually undeveloped.
Jerome translates foolishness with infantiam, infant-like behavior. Jerome uses prudentiae, from which is derived prudence, for understanding.
Except for verses 7-8 and the antiphon, this is the same psalm used last Sunday. To refresh memories, this is an intellectual, alphabetical, acrostic hymn.
verse 9a Taste and see the goodness of the Lord.
This Psalm 34 is also used according to the following chart.
Jerome translates lowly with mansueti in the sense of easy to get along with.
Jerome translates poor with pauper in the sense of pauper or poor in the sense of without funds.
not as foolish persons but as wise.
Jerome translates live with ambuletis, offering the sense of walking-around; foolish with insipientes from which insipid is derived; wise with sapientes, the generally-used Latin for wise.
Jerome translates opportunity with tempus, offering a sense of trying to make good use of the time allotted the Faithful on earth.
Jerome translates ignorance with imprudentes, or impudence or im-prudence.
The word Jerome uses for debauchery is luxuria, the derivative for luxury.
The Order of Christian Funerals rightly notes that "… the calming effect of familiar prayers can comfort the mourners as they begin to face their loss."  Familiarization with Scripture readings, therefore, seems appropriate for the Sunday readings. Verses from this Gospel may be used at "13 Funerals for Adults," #13, John 6:51-58 and "14 Funerals for Baptized Children," #4, John 6:51-58.
A scholar includes these two verses among instances associating glory with the cross.
verse 58 This is the bread that came down from heaven.
In conclusion, Proverbs is about spreading the table of Wisdom and eating thereat; Psalm 34 continues about tasting and seeing the goodness of the Lord; Ephesians about giving thanks always and for everything; and the Fourth Gospel about eating the flesh of Jesus and thereby living his own very life, forever.
For an overview of sources used see the Appendix file.
 Paul Overland, "Did the Sage Draw from the Shema? A Study of Proverbs 3:1-12," the Catholic Biblical Quarterly, Vol. 62, No. 3 (July 2000) 441.
 Hanan Eshel and John Strugnell, "Alphabetical Acrostics in Pre-Tannaitic Hebrew," the Catholic Biblical Quarterly, Vol. 62, No. 3 (July 2000), 443.
 International Commission on English in the Liturgy: A Joint Commission of Catholic Bishops' Conferences, The Roman Ritual: Revised by Decree of the Second Vatican Ecumenical Council and published by Authority of Pope Paul IV: Order of Christian Funerals: Including Appendix 2: Cremation: Approved for use in the Dioceses of the United States of America by the National Conference of Catholic Bishops and Confirmed by the Apostolic See (New Jersey: Catholic Book Publishing Co., 1998), "Prayers after Death," page 49.
 Loren L. Johns and Douglas B. Miller, The Signs as Witnesses in the Fourth Gospel: Reexamining the Evidence, the Catholic Biblical Quarterly, Vol. 56, No. 3 (July 1994) 530.


E - Schmidt; Larson,  M. DP - Smittys 1. LOB - Smittys 7; Mitchell 7. 2B - Hearnen.
HBP - Piper. SH - Jordre(1); Loes 2; Piper; VanOverschel. SF - Schmidt.
HBP - by Heintzman (Piper). PB - Larson,  K 2.
M; VanOverschel. Walks - Morsching; Hearnen 2; Schmidt; Young; Larson,  M.
Win - Schmidt.  Loss - Morsching.  Save - None.
Aberdeen 1st - Anglin grounded out to 2b. Cunningham struck out looking.
ss. 0 runs, 2 hits, 0 errors, 2 LOB.
Hearnen advanced to third. Schmidt flied out to cf, SAC, RBI; Hearnen scored.
Young singled. Larson,  K struck out. 1 run, 2 hits, 0 errors, 1 LOB.
ball, unearned. Gosch grounded out to ss. 1 run, 0 hits, 1 error, 0 LOB.
flied out to lf. 0 runs, 1 hit, 0 errors, 1 LOB.
ss. Schmidt out at first 1b to p. 0 runs, 0 hits, 0 errors, 0 LOB.
out looking. Anglin reached on an error by 2b; Morsching advanced to second.
Cunningham out at first 1b to p. 0 runs, 0 hits, 1 error, 2 LOB.
looking. Larson,  M struck out. 0 runs, 0 hits, 0 errors, 0 LOB.
Piper out on the play. 0 runs, 0 hits, 0 errors, 0 LOB.
out to ss. 1 run, 1 hit, 0 errors, 1 LOB.
flied out to 3b. 0 runs, 0 hits, 0 errors, 0 LOB.
Mitchell Legion 7th - Larson,  M flied out to rf. Piper flied out to c.
rf. 0 runs, 1 hit, 0 errors, 1 LOB.
walked, RBI; Young advanced to second; Schmidt advanced to third; Loes scored.
1 run, 0 hits, 0 errors, 3 LOB.
Pitchers: Aberdeen - Sam Heintzman; Taylor Morsching(8). Mitchell Legion - Young; Schmidt(8).


Somehow, carpet owners can tell when it is time to replace them since there are evidences that show it. Unlike other floorings that are more durable, carpets are more easily replaced than most other types of floorings and relatively cheaper compared to most high end floor coverings. So if you want to make your floorings look nice again, there are many carpet replacements that you can by and you can choose from many styles, textures, and colors that are available today. Wanting to replace your carpet with still another carpet indicates that you value this kind of flooring which gives comfort, warmth, and is able to absorb noise.
Today, in order to make your carpet last longer, you only need to contact professional carpet cleaners and there are many companies offering carpet cleaning services today so you really won't have a hard time looking for one. However, despite the great cleaning services taking care of your carpets, they will still, one day, outgrow their usefulness and will need replacement. We now need to determine when the right time to replace your carpet is or when the carpet is no longer fulfilling its function. You can tell by signs that it is time to replace your carpets.
One way of telling that your carpet is already due for replacement is that it will have a bad smell from underneath even if it has just been cleaned by experts and it is very likely that the paddling underneath the carpet has already decayed and no longer usable or yet it can be molds and mildew that have grown deep into the carpet fibers. When this happens, it is time to have your carpet replaced by a carpet replacement company so that you don't face health hazards breathing in allergens each day.
When carpets are first installed you are like stepping on cushions but when this feeling is no longer there, then it must be time for replacement. When the padding has lost its bounciness, the floor starts to feel hard and unforgiving, leaving out that amenity or that touch of luxury found only in carpet floorings. Although the pads can be replaced, somehow it is best to get a new carpet instead.
One other indication that it is time to replace your carpets is when your stain-resistant treatment is no longer effective and the stains keep coming back. The treatment is not longer effective due to time and foot traffic, and it is expected the fibers will also start to wear. This is why you carpets get easily stained already. There is no doubt that an expert can remove some stains except for some obstinate stains, but the point is, how regular will you need to discard every spill off that turns into a stain.


text:
Richard-Jonathan Nelson
Exhibition Checklist (pdf)
2022 A Lacquered Egress
Extended Hours: Thursday, January 12, 10 AM - 8 PM
Richard-Jonathan Nelson Receives 21c Museum Hotels Acquisition Prize
Yossi Milo Gallery is excited to invite the public for an evening viewing of Richard-Jonathan Nelson's debut solo exhibition in New York City, A Lacquered Egress. The gallery will remain open late with extended hours on Thursday, January 12 from 10 AM - 8 PM. Nelson's multimedia tapestries combine Afrofuturist visions with reimagined ideas of handcraft, creating a speculative vision of safety and freedom for his subjects.
We are pleased to share that Richard-Jonathan Nelson is the 2022 recipient of the 21c Museum Hotels Acquisition Prize. 21c Museum Hotels, whose mission is to bring relevant global culture to the hospitality industry through contemporary art, awards this prize to an artist whose work speaks to the pressing issues of our time. As a recipient of this prize, Nelson is recognized as part of a new generation of textile artists reinventing tapestry for the modern age.


We are pleased to announce Bowe Digital are now formally associated with the Onesys group of companies, one of the UK's Leading Sage Platinum Partners.
The Association allows Bowe Digital to call upon the resources of the onesys group, with particular emphasis on an ability to access industry leading Sage Customer Support from the Onesys support centres in Newcastle, York, Mansfield and Coventry. Additional offices and staff are based in London, West Midlands and the East Midlands and there is the ability to draw on the unrivalled technical, customer care and consultancy skills in these centres.
The Onesys group of companies is a long established Sage partner with nearly 40 staff, 600 clients on support, providing services throughout the UK and internationally.
Onesys are fully qualified in all Sage 200 modules and have many of the largest and most demanding sites in the UK, our recently expanded Newcastle office in particular, has a number of former senior Sage plc consultants who have leading skills in sage software.
Our teams have great skills in project delivery and customer care.
We also provide consultancy and technical skills to Sage UK/Eire and their direct customers.
Uniquely, Onesys has one of the largest Sage development teams in the UK and have vast experience in small or large development projects.
Onesys also provide and support the fuller range of Sage software including Sage Live, Sage 50, HR Payroll, as well as the leading additions from Sicon, Dracir, Eureka, Panintelligence and Paperless.
The team and operation at Bowe will continue to operate as it is but now with an enhanced range of skills available, which will ensure you have an enhanced level of service and support.
If you have any questions regarding this arrangement please contact.


text:
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**awsKey** | **String** | AWS key (if subscriptionType is awsKinesis |  [optional]
**awsSecret** | **String** | AWS secret (if subscriptionType is awsKinesis |  [optional]
**createdOn** | **Long** | Creation timestamp |  [optional]
**awsKinesisStreamName** | **String** | AWS Kinesis stream name (if subscriptionType is awsKinesis |  [optional]
**uid** | **String** | User ID |  [optional]
**messageType** | **String** | Message type |  [optional]
**ddid** | **String** | Destination device ID |  [optional]
**subscriptionType** | **String** | Subscription type (either httpCallback or awsKinesis, default to httpCallback) |  [optional]
**name** | **String** | Name |  [optional]
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Call or e-mail The Spa Guy today! This is a nice used Arctic Spa featuring 2 Pumps, 46SS Jets, Blower, iPod Dock and 2(2) Speakers and (2) 12V LED Lights.
This Spa has a Nice Real Redwood Cabinet and a Good cover. Hurry...a spa this nice is a rare find!
93" X 93" x 39.25"