text:
In our Organize! columns we explore various lessons in organizing strategies and tactics, going beyond the outside story of a campaign to look at how it worked or what lessons it might have to teach us.
Tenant Organizing When Rising Rent Isn't the (Main) Issue
Organize! Julian Francis Park - January 22, 2020
Tenant organizing has been re-energized in coastal cities where housing costs are soaring. But tenants need a voice in the rest of the country too—and they are organizing to get one.
Gaining Ground by Holding Back
Organize! Steve Kest - March 1, 1997
Late last year, St. Louis ACORN members learned that Regional Hospital – the city's only "safety net" hospital that guaranteed care regardless of ability...
Tenant Organizing Wins One-for-One Replacement
Organize! James Tracy - January 1, 2000
In 1996, a small group of highly organized residents of North Beach public housing in San Francisco began to raise questions about the fate...
A Neighborhood in Brooklyn Says "No" to Worker Exploitation
Organize! Erin Sabra Fuchs - March 1, 2005
A language barrier, I believe, has muddled my conversation with Nieves Padilla. "We're fighting to get the workers on Knickerbocker Avenue the minimum wage,"...
New Jersey's Campaign Against Lead
Organize! Nicole Brown and Dana Natale - November 1, 2003
The effects of lead poisoning on a child's physical and emotional development and cognitive ability are well known. An investigation that ran two years...
Fighting Gentrification Through Collective Bargaining
Organize! Ethan Corey - October 16, 2015
For the past two years, the Crown Heights Tenant Union of Brooklyn has turned collective bargaining strategies on landlords—and policymakers.
Still Riding Route 61
Organize! Tony Pecinovsky - April 23, 2006
A labor/community partnership stops a fare hike and gives workers a boost
Occupy Makes Space for Community Advocates
Organize! Michael Kane - April 24, 2012
By smashing the wall of media silence about America's wealth and income divide, the Occupy movement has opened a dramatically new terrain for organizations...
A Radically Different Planning Process in Brownsville
Organize! Christina Patino Houle - October 14, 2019
In a year-long program that included bike rides, serenades, and Dragtivist performances, an art collective guided Brownsville, Texas, residents in reimagining how they could influence equity and justice in their city.
Don't Start Small
Organize! Miriam Axel-Lute - May 1, 2001
It's often said that organizers should begin with easily attainable goals to bolster their group's confidence. But Caroline Murray, executive director of the Anti-Displacement...
Organize! Majora Carter - November 1, 1999
The Bronx neighborhood of Hunts Point has one of the highest asthma rates in the world. Home to the world's largest food distribution center,...
Cross-Community Collaboration on NYC's Municipal ID Program
Organize! Rogers and Sam J. Miller - August 11, 2015
Lack of identification hurts many different groups in different ways—from the homeless to immigrants, and they all need to be considered in the fight for an alternative.
Organize! Rebecca Epstein - November 1, 2002
Josefina de la Cruz's migration history does not stop at her arrival from Mexico in 1972, but continues through five different Chicago neighborhoods, most...
Walking the Walk
Organize! Geraud Blanks - March 1, 2008
In a city full of problems and promise, I'm taking the first steps toward learning up close what community organizing can accomplish.
Organizing to Build a Movement
Organize! Billy Easton - March 1, 1996
In December 1994, President Bill Clinton proposed converting public housing and project-based Section 8 into vouchers. House Speaker Newt Gingrich and Congressman Rick Lazio...
From Brooklyn to Berlin: Organizing Schoeneweide
Organize! Tom Lenz - January 1, 2004
The scene looks familiar enough. In a foyer outside an elegant legislative chamber, a group of citizens is pigeonholing their local politicians. A vote...
Thirty-Five Years of Building Citizen Power
Organize! Steve Max - December 22, 2008
The 2008 presidential contest vaulted community organizing into the national limelight, as the McCain campaign sought to cast doubt on the legitimacy of Barack...
Housing Set-Asides: An Idea Whose Time Has Come
In August 2002, Kevin Jackson, director of the Chicago Rehab Network, sent a letter out to network members and supporters to introduce a campaign...
Winning a War, But Losing the Battle
Organize! Miriam Axel-Lute - January 1, 2003
Victory in a tenant organizing campaign is usually defined by improving conditions for the tenants involved – an egregious repair problem is fixed, landlord...
Fighting for Worker's Rights in Maine
Organize! Shelterforce Staff - January 1, 1997
Years of alleged wage, immigration, safety, and civil rights violations, environmental sanctions, and other infractions at the DeCoster egg farm in Turner, Maine, have...


text:
Malcouenant Surname Ancestry Results
Our indexes 1000-1999 include entries for the spelling 'malcouenant'. In the period you have requested, we have the following 2 records (displaying 1 to 2):
malcolm-wood malcolmsons malcolmtosh malcoln malcom malcomb malcombe malcomber malcombson malcome malcomen malcomsn malcomson malcomsone malcony malcor malcorn malcorne malcot malcott malcouronne malcovch malcove malcovsky malcoyenant malcplm malcus malcut malcuuinant malcuvenant malcvolm malcys malczewski mald mald' malday malde maldecombe maldecroft malden
Pipe Roll (1241-1242)
The Great Rolls of the Pipe are the central record of the crown compiling returns of income and expenditure from the sheriffs and farmers of the various English counties or shires. This is the oldest series of public records, and the earliest surviving instances of many surnames are found in the Pipe Rolls. This is the roll for the 26th year of the reign of king Henry III, that is, accounting for the year from Michaelmas 1241 to Michaelmas 1242. Most (but not all) of the entries in which names appear relate to payments for grants of land and fines or pardons arising from the proceedings of the justices. The text was edited by Henry Lewin Cannon for Yale Historical Publications and printed in 1918. The name of the county is given at the head of each page, and variant spellings, omissions and additions found in the duplicate Chancellor's Roll [C. R.] are given in the footnotes.
MALCOUENANT. Cost: £4.00.
Patent Rolls: entries for Lincolnshire (1275-1276)
Calendars of the patent rolls of the reign of king Edward I are printed in the Calendars of State Papers: but these cover only a fraction of the material on the rolls. From 1881 to 1889 the reports of the Deputy Keeper of the Public Record Office also include calendars of other material from the rolls - about five times as many entries as in the State Papers - predominantly mandates to the royal justices to hold sessions of oyer and terminer to resolve cases arising locally; but also other general business. The calendar for the 4th year of king Edward I [20 November 1275 to 19 November 1276], hitherto unindexed, is covered here.

redpajama_set_name: RedPajamaCommonCrawl


text:
//==================================================================================
// Copyright (c) 2013-2016 , Advanced Micro Devices, Inc.  All rights reserved.
//
/// \author AMD Developer Tools Team
/// \file LibDisassembler.cpp
///
//==================================================================================

#ifdef _WINDOWS
    #include <windows.h>
#else
    #include "typedefs_lin.h"
#endif

#if !defined(_WINDOWS)
    #define STDMETHODIMP    HRESULT
#endif

#include "Disasmwrapper.h"
#include "LibDisassembler.h"
#include <string.h>

/////////////////////////////////////////////////////////////////////////////
// LibDisassembler
LibDisassembler::LibDisassembler() : m_pWrapper(NULL), m_dbit(TRUE), m_lbit(FALSE), m_proctype(ANY)
{
    m_pWrapper = new CDisasmwrapper;

    if (m_pWrapper)
    {
        if (m_dbit)
        {
            m_pWrapper->SetDbit();
        }
        else
        {
            m_pWrapper->ClearDbit();
        }

        //set 64 bit mod
        if (m_lbit)
        {
            m_pWrapper->SetLongMode();
        }
        else
        {
            m_pWrapper->ClearLongMode();
        }
    }
}

LibDisassembler::~LibDisassembler()
{
    if (NULL != m_pWrapper)
    {
        delete m_pWrapper;
        m_pWrapper = NULL;
    }
}
HRESULT LibDisassembler::SetLongMode(BOOL DefaultIs32Bits)
{
    m_lbit = DefaultIs32Bits;

    if (m_pWrapper)
    {

        //set 64 bit mod
        if (m_lbit)
        {
            // If long mod bit is on, should set d bit off
            m_dbit = FALSE;
            m_pWrapper->ClearDbit();
            m_pWrapper->SetLongMode();
        }
        else
        {
            m_pWrapper->ClearLongMode();
        }
    }

    return S_OK;
}

HRESULT LibDisassembler::SetProcessorType(eProcType CurrentProcType)
{
    if (((CurrentProcType < K7) || (CurrentProcType > K8))
        && (CurrentProcType != ANY))
    {
        return S_FALSE ;
    }

    m_proctype = CurrentProcType ;

    return S_OK;
}

// *** TO DO *** return error code in HRESULT hr
HRESULT LibDisassembler::UIDisassemble(
    BYTE* rawcode,
    unsigned int* StrLength,
    BYTE* ASCIICode,
    UIInstInfoType* pDisasmInfo,
    BYTE* ErrorCode)
{
    char* pDisasmString;

    *ErrorCode = static_cast<BYTE>(-1);

    memset(ASCIICode, 0, *StrLength);

    pDisasmInfo->NumBytesUsed = 0x00;
    pDisasmInfo->NumOpCodeBytes = 0x00;
    pDisasmInfo->OpCodeByte = 0x00;
    pDisasmInfo->bHasDispData = FALSE;
    pDisasmInfo->DispDataValue = 0;

    pDisasmInfo->bIsPCRelative = FALSE;

    for (int ii = 0; ii < MAX_OPERANDS; ii++)
    {
        pDisasmInfo->bHasMemOp[ii] = FALSE;
        pDisasmInfo->MemAccessSize[ii] = 0;
    }

    if (m_pWrapper)
    {
        *ErrorCode = NoError;
        pDisasmString = m_pWrapper->Disassemble(rawcode);

        if (pDisasmString != NULL)
        {
            pDisasmInfo->NumBytesUsed = (BYTE)m_pWrapper->GetLength();

            pDisasmInfo->NumOpCodeBytes = (BYTE)m_pWrapper->GetNumOpcodeBytes();
            pDisasmInfo->OpCodeByte = m_pWrapper->GetOpcode(0);

            if (m_pWrapper->HasDisplacement())
            {
                pDisasmInfo->bHasDispData = TRUE;
                pDisasmInfo->DispDataValue = (unsigned int) m_pWrapper->GetDisplacement();
            }
            else
            {
                pDisasmInfo->bHasDispData = FALSE;
            }

            for (int i = 0; i < m_pWrapper->GetNumOperands(); i++)
            {
                int type = m_pWrapper->GetOperandType(i);

                if ((n_Disassembler::OPERANDTYPE_RIPRELATIVE == type)
                    || (n_Disassembler::OPERANDTYPE_PCOFFSET == type))
                {
                    pDisasmInfo->bIsPCRelative = TRUE;
                    //              break;
                }

                if ((n_Disassembler::OPERANDTYPE_RIPRELATIVE == type)
                    || (n_Disassembler::OPERANDTYPE_PCOFFSET == type)
                    || (n_Disassembler::OPERANDTYPE_MEMORY == type))
                {
                    if (pDisasmInfo->bHasMemOp[i])
                    {
                        continue;
                    }

                    pDisasmInfo->bHasMemOp[i] = TRUE;

                    switch (m_pWrapper->GetOperandSize(i))
                    {
                        case n_Disassembler::OPERANDSIZE_8:
                            pDisasmInfo->MemAccessSize[i] = 1;
                            break;

                        case n_Disassembler::OPERANDSIZE_16:
                            pDisasmInfo->MemAccessSize[i] = 2;
                            break;

                        case n_Disassembler::OPERANDSIZE_32:
                            pDisasmInfo->MemAccessSize[i] = 4;
                            break;

                        case n_Disassembler::OPERANDSIZE_48:
                            pDisasmInfo->MemAccessSize[i] = 6;
                            break;

                        case n_Disassembler::OPERANDSIZE_64:
                            pDisasmInfo->MemAccessSize[i] = 8;
                            break;

                        case n_Disassembler::OPERANDSIZE_80:
                            pDisasmInfo->MemAccessSize[i] = 10;
                            break;

                        case n_Disassembler::OPERANDSIZE_128:
                            pDisasmInfo->MemAccessSize[i] = 16;
                            break;

                        case n_Disassembler::OPERANDSIZE_256:
                            pDisasmInfo->MemAccessSize[i] = 32;
                            break;

                        case n_Disassembler::OPERANDSIZE_NONE:
                            pDisasmInfo->MemAccessSize[i] = 0;
                            break;

                        default:
                            pDisasmInfo->MemAccessSize[i] = 0;
                            break;
                    }

                    //              break;
                }
            }

            *ErrorCode = NoError;

            strncpy_s((char*)ASCIICode, *StrLength, pDisasmString, strlen(pDisasmString));
            *StrLength = static_cast<UINT>(strlen((char*)ASCIICode));
        }
        else
        {
            *ErrorCode = ErrInDE;
        }
    }

    if (*ErrorCode)
    {
        return E_FAIL;
    }
    else
    {
        return S_OK;
    }

}

void LibDisassembler::ResetEffectiveAddr()
{
    m_bEffAddrBaseRegPresent = FALSE;
    m_bEffAddrIndexRegPresent = FALSE;
    m_EffAddrBaseReg = 0x00;
    m_EffAddrIndexReg = 0x00;
    m_EffAddrScale = 0x01;
    m_EffAddrDisp = 0;
    m_EffectiveAddress = 0;
    m_OperandSize = evSizeNone;
    m_MemAccessType = nA;
}

// Write effective address in trace record
void LibDisassembler::WriteEffectiveAddr(UINT64* pEffAddr)
{
#pragma pack(1)
    struct _TraceRecord
    {
        BYTE Header ;
        unsigned int Low32BitsData ;
        unsigned int High32BitsData ;
    } * pRec ;
#pragma pack()
    pRec = (_TraceRecord*) m_pTraceRecords ;

    // calculate effective Address for both 64 bit and 32 bit format
    m_EffectiveAddress  = m_bEffAddrBaseRegPresent ?
                          m_pContextRegs[m_EffAddrBaseReg] : 0 ;
    m_EffectiveAddress += m_bEffAddrIndexRegPresent ?
                          m_pContextRegs[m_EffAddrIndexReg] * m_EffAddrScale : 0 ;
    m_EffectiveAddress += m_EffAddrDisp ;

    (*pEffAddr) = m_EffectiveAddress;
    m_EffectiveAddrCount++;

    // Set the access type, Header.7:4
    pRec->Header |= m_MemAccessType ;

    // Set the type of memory operand, Header.2:0
    switch (m_OperandSize)
    {
        case evSizeQWord  : pRec->Header |= 0x00 ; break ;

        case evSizeByte   : pRec->Header |= 0x01 ; break ;

        case evSizeWord   : pRec->Header |= 0x02 ; break ;

        case evSizeDWord  : pRec->Header |= 0x04 ; break ;

        // this case is for 64-bit trace format
        //case evSizeDQWord : pRec->Header |= 0x05 ; break ;

        case evSizeFWord  : pRec->Header |= 0x06 ; break ;

        case evSizeTByte  : pRec->Header |= 0x07 ; break ;

        default           : pRec->Header |= 0x04 ;
    }

    //According to the speedtracer 64 documentation, if we're running in
    //  compatibility mode (lma=1 && m_lbit = 0), the data length is usually
    //  4 bytes (32-bit format), but some hidden accesses to descriptor tables,
    //  page tables, etc will require 8 byte addresses.  As far as I can tell,
    //  the "hidden accesses" are actually from the 64-bit OS maintaining the
    //  32-bit compatibility.  As this disassembler is targeted mainly towards
    //  CodeAnalyst, and the applications traced will probably be either 32-bit
    //  or 64-bit, I don't think we have to worry about that exception here.
    if (m_lbit)
    {
        // 64 bit format
        // Header.3 = data length, 8-bytes equ 1;
        pRec->Header |= 0x08;

        if (evSizeDQWord == m_OperandSize)
        {
            pRec->Header |= 0x05;
        }

        pRec->Low32BitsData = (unsigned int) m_EffectiveAddress ;
        INT64 high32bits = m_EffectiveAddress >> 32;
        pRec->High32BitsData = (unsigned int) high32bits ;
        //Advance to the beginning of the next record to write, if any
        m_pTraceRecords += sizeof(pRec->Header) + sizeof(pRec->Low32BitsData) + sizeof(pRec->High32BitsData);

    }
    else
    {
        // 32 bit trace format

        //Header.3 = type of address, virtual equ 0; physical que 1;
        // default is virtual

        pRec->Low32BitsData = (unsigned int) m_EffectiveAddress ;
        //Advance to the beginning of the next record to write, if any
        m_pTraceRecords += sizeof(pRec->Header) + sizeof(pRec->Low32BitsData) ;
    }

    ResetEffectiveAddr();
}

HRESULT LibDisassembler::TGDisassemble(
    BYTE* RawCodeBytes,
    TgInstInfoType* pDisasmInfo,
    UINT64 ContextRegs[],
    unsigned int* pBuffSize,
    BYTE TraceRecs[],
    UINT64* pEffectiveAddrArray,
    DWORD* pEffectiveAddrCount,
    BYTE* ErrorCode)
{
    *ErrorCode = static_cast<BYTE>(-1);
    pDisasmInfo->NumBytesUsed = 0;
    pDisasmInfo->InstrPrefix = 0x00;
    pDisasmInfo->InstrPfxType = evNoPrefix;
    pDisasmInfo->NumOpCodeBytes = 0;
    pDisasmInfo->OpCodeByte = 0x00;
    pDisasmInfo->InstSpecies = evNASpecies;

    m_EffectiveAddrCount = 0;

    char* pDisasmString;

    if (m_pWrapper)
    {
        *ErrorCode = NoError;
        pDisasmString = m_pWrapper->Disassemble(RawCodeBytes);

        if (pDisasmString != NULL)
        {
            pDisasmInfo->NumBytesUsed = (BYTE)m_pWrapper->GetLength();

            pDisasmInfo->NumOpCodeBytes = (BYTE)m_pWrapper->GetNumOpcodeBytes();
            pDisasmInfo->OpCodeByte = m_pWrapper->GetOpcode(0);

            if (m_pWrapper->HasLockPrefix())
            {
                pDisasmInfo->InstrPfxType = evLOCK;
                pDisasmInfo->InstrPrefix = 0xF0;
            }

            if (m_pWrapper->HasRepnePrefix())
            {
                pDisasmInfo->InstrPfxType = evREPNE;
                pDisasmInfo->InstrPrefix = 0xF2;
            }

            if (m_pWrapper->HasRepPrefix())
            {
                pDisasmInfo->InstrPrefix = 0xF3;
                pDisasmInfo->InstrPfxType = evNoPrefix;

                if ((0xA6 == pDisasmInfo->OpCodeByte)
                    || (0xA7 == pDisasmInfo->OpCodeByte)
                    || (0xAE == pDisasmInfo->OpCodeByte)
                    || (0xAF == pDisasmInfo->OpCodeByte))
                {
                    pDisasmInfo->InstrPfxType = evREPE ;
                }
                else
                {
                    pDisasmInfo->InstrPfxType = evREP ;
                }

            }

            CInstr_ExtraCodes* extracodes = (CInstr_ExtraCodes*)(m_pWrapper->GetExtraInfoPtr());

            if (NULL == extracodes)
            {
                *ErrorCode = ErrInTableHookup;
            }
            else
            {
                pDisasmInfo->InstSpecies = extracodes->instr_table.InstSpecies;
                *ErrorCode = NoError;

                // Write TraceRecord;
                m_bEffAddrBaseRegPresent = FALSE;
                m_bEffAddrIndexRegPresent = FALSE;
                m_EffAddrBaseReg = 0x00;
                m_EffAddrIndexReg = 0x00;
                m_EffAddrScale = 0x01;
                m_EffAddrDisp = 0;
                m_EffectiveAddress = 0;
                m_TraceBuffSize = 0;
                m_OperandSize = evSizeNone;
                m_MemAccessType = nA;

                memset(TraceRecs, 0, *pBuffSize) ;
                m_pContextRegs = ContextRegs ;
                m_TraceBuffSize = *pBuffSize ;
                m_pTraceRecords = TraceRecs ;

                ////////////////////////////////////////////

                int NumOperandsInWrapper, NumOperandsInDE, numimplicit;
                NumOperandsInWrapper = extracodes->instr_table.NumOperands;
                NumOperandsInDE = m_pWrapper->GetNumOperands();

                if (NumOperandsInDE > NumOperandsInWrapper)
                {
                    *ErrorCode = ErrInTableHookup;
                }
                else if (NumOperandsInDE == NumOperandsInWrapper)
                {
                    for (int j = 0; j < NumOperandsInDE; j++)
                    {
                        if ((n_Disassembler::OPERANDTYPE_MEMORY == m_pWrapper->GetOperandType(j)) ||
                            (((n_Disassembler::OPERANDTYPE_RIPRELATIVE == m_pWrapper->GetOperandType(j)) ||
                              (n_Disassembler::OPERANDTYPE_PCOFFSET == m_pWrapper->GetOperandType(j))) &&
                             m_pWrapper->HasModrm()))
                        {
                            if (m_pWrapper->HasBase())
                            {
                                m_bEffAddrBaseRegPresent = TRUE;
                                m_EffAddrBaseReg = (BYTE)m_pWrapper->GetBaseRegister();
                            }

                            if (m_pWrapper->OperandHasIndex(j))
                            {
                                m_bEffAddrIndexRegPresent = TRUE;
                                m_EffAddrIndexReg = (BYTE)m_pWrapper->GetOperandIndexRegister(j);
                            }

                            if (m_pWrapper->HasScale())
                            {
                                m_EffAddrScale = 0x01 << m_pWrapper->GetSibScale();
                            }

                            if (m_pWrapper->HasDisplacement())
                            {
                                m_EffAddrDisp =  m_pWrapper->GetDisplacement();
                            }

                            //If needed, add the current ip to make pc relative
                            if (n_Disassembler::OPERANDTYPE_RIPRELATIVE == m_pWrapper->GetOperandType(j))
                            {
                                m_EffAddrDisp += m_pContextRegs[/*Rip*/16] + m_pWrapper->GetLength();
                            }

                            m_OperandSize = (eOperandSize)(m_pWrapper->GetOperandSize(j));

                            switch (j)
                            {
                                case 0:
                                    m_MemAccessType = extracodes->instr_table.OpField1.MemAccessType;
                                    break;

                                case 1:
                                    m_MemAccessType = extracodes->instr_table.OpField2.MemAccessType;
                                    break;

                                case 2:
                                    m_MemAccessType = extracodes->instr_table.OpField3.MemAccessType;
                                    break;
                            }

                            if (m_EffectiveAddrCount < *pEffectiveAddrCount)
                            {
                                WriteEffectiveAddr(&pEffectiveAddrArray[m_EffectiveAddrCount]);
                            }
                        }
                    }// end of for loop
                }
                else    // there is implicit reg/mem
                {
                    numimplicit = 0;

                    for (int i = 0; i < NumOperandsInWrapper; i++)
                    {
                        COperandField tempoperand;

                        switch (i)
                        {
                            case 0:
                                tempoperand = extracodes->instr_table.OpField1;
                                break;

                            case 1:
                                tempoperand = extracodes->instr_table.OpField2;
                                break;

                            case 2:
                                tempoperand = extracodes->instr_table.OpField3;
                                break;
                        }   // end of switch (i)

                        if (tempoperand.IsImplicit())
                        {
                            numimplicit += 1;
                            //This is implicit memory access, we are going to write trace recorder base on it's evInstSpecies later.
                        }
                        else
                        {
                            int j = i - numimplicit;

                            if (n_Disassembler::OPERANDTYPE_MEMORY == m_pWrapper->GetOperandType(j))
                            {
                                if (m_pWrapper->HasBase())
                                {
                                    m_bEffAddrBaseRegPresent = TRUE;
                                    m_EffAddrBaseReg = (BYTE)m_pWrapper->GetBaseRegister();
                                }

                                if (m_pWrapper->OperandHasIndex(j))
                                {
                                    m_bEffAddrIndexRegPresent = TRUE;
                                    m_EffAddrIndexReg = (BYTE)m_pWrapper->GetOperandIndexRegister(j);
                                }

                                if (m_pWrapper->HasScale())
                                {
                                    m_EffAddrScale = 0x01 << m_pWrapper->GetSibScale();
                                }

                                if (m_pWrapper->HasDisplacement())
                                {
                                    m_EffAddrDisp =  m_pWrapper->GetDisplacement();
                                }

                                //m_OperandSize = (eOperandSize) (m_pWrapper->GetOperandSize(j) - n_Disassembler::OPERANDSIZE_NONE);
                                m_OperandSize = (eOperandSize)(m_pWrapper->GetOperandSize(j));

                                switch (i)
                                {
                                    case 0:
                                        m_MemAccessType = extracodes->instr_table.OpField1.MemAccessType;
                                        break;

                                    case 1:
                                        m_MemAccessType = extracodes->instr_table.OpField2.MemAccessType;
                                        break;

                                    case 2:
                                        m_MemAccessType = extracodes->instr_table.OpField3.MemAccessType;
                                        break;
                                }

                                if (m_EffectiveAddrCount < *pEffectiveAddrCount)
                                {
                                    WriteEffectiveAddr(&pEffectiveAddrArray[m_EffectiveAddrCount]);
                                }
                            }
                        }
                    }
                }

                // The implicit operands which access memory
                switch (extracodes->instr_table.InstSpecies)
                {
                    case evPushaSpecies:        // 16 bits ignore now
                    case evPushaqSpecies:       // 64 bits
                    case evPushadSpecies:       // 32 bits
                        m_bEffAddrBaseRegPresent = TRUE ;
                        m_EffAddrBaseReg = 4;   // base register is ESP/RSP

                        if (evPushaqSpecies == extracodes->instr_table.InstSpecies)
                        {
                            // invalid for 64bits(from AMD menu), but Robert's Engine supprots. Leave it here for future
                            m_OperandSize = evSizeQWord;
                            m_pContextRegs[m_EffAddrBaseReg] -= 64;     // pre-decrement stack pointer by 64
                        }
                        else if (evPushadSpecies == extracodes->instr_table.InstSpecies)
                        {
                            m_OperandSize = evSizeDWord;
                            m_pContextRegs[m_EffAddrBaseReg] -= 32;     // pre-decrement stack pointer by 32
                        }
                        else
                        {
                            m_OperandSize = evSizeWord;
                            m_pContextRegs[m_EffAddrBaseReg] -= 16;     // pre-decrement stack pointer by 16
                        }

                        m_MemAccessType = WW;
                        m_pContextRegs[m_EffAddrBaseReg] -= (m_OperandSize == evSizeDWord) ? 32 : 16;

                        if (m_EffectiveAddrCount < *pEffectiveAddrCount)
                        {
                            WriteEffectiveAddr(&pEffectiveAddrArray[m_EffectiveAddrCount]);
                        }

                        break;

                    case evPushSpecies:
                        m_bEffAddrBaseRegPresent = TRUE ;
                        m_EffAddrBaseReg = 4;   // base register is ESP/RSP

                        if (0x6A == m_pWrapper->GetOpcode(0))
                        {
                            m_OperandSize = evSizeByte;
                            m_pContextRegs[m_EffAddrBaseReg] -= 1;          // pre-decrement stack pointer by 1 byte;
                        }
                        else if (!m_lbit)
                        {
                            if (!m_dbit)
                            {
                                m_OperandSize = evSizeWord;
                                m_pContextRegs[m_EffAddrBaseReg] -= 2;          // pre-decrement stack pointer by 2 byte;
                            }
                            else
                            {
                                m_OperandSize = evSizeDWord;
                                m_pContextRegs[m_EffAddrBaseReg] -= 4;          // pre-decrement stack pointer by 4 byte;
                            }
                        }
                        else
                        {
                            m_OperandSize = evSizeQWord;
                            m_pContextRegs[m_EffAddrBaseReg] -= 8;          // pre-decrement stack pointer by 8 byte;
                        }

                        m_MemAccessType = WW;

                        if (m_EffectiveAddrCount < *pEffectiveAddrCount)
                        {
                            WriteEffectiveAddr(&pEffectiveAddrArray[m_EffectiveAddrCount]);
                        }

                        break;

                    case evPushfqSpecies:
                        m_bEffAddrBaseRegPresent = TRUE ;
                        m_EffAddrBaseReg = 4;   // base register is RSP
                        m_OperandSize = evSizeQWord;
                        m_pContextRegs[m_EffAddrBaseReg] -= 8;          // pre-decrement stack pointer by 8 byte;
                        m_MemAccessType = WW;

                        if (m_EffectiveAddrCount < *pEffectiveAddrCount)
                        {
                            WriteEffectiveAddr(&pEffectiveAddrArray[m_EffectiveAddrCount]);
                        }

                        break;

                    case evPushfdSpecies:
                        m_bEffAddrBaseRegPresent = TRUE ;
                        m_EffAddrBaseReg = 4;   // base register is ESP
                        m_OperandSize = evSizeQWord;
                        m_pContextRegs[m_EffAddrBaseReg] -= 4;          // pre-decrement stack pointer by 4 byte;
                        m_MemAccessType = WW;

                        if (m_EffectiveAddrCount < *pEffectiveAddrCount)
                        {
                            WriteEffectiveAddr(&pEffectiveAddrArray[m_EffectiveAddrCount]);
                        }

                        break;

                    case evEnterSpecies:
                        m_bEffAddrBaseRegPresent = TRUE ;
                        m_EffAddrBaseReg = 4;   // base register is ESP

                        // No 16 bits support ENTER, PUSH[EBP]
                        m_OperandSize = evSizeDWord;
                        m_MemAccessType = WW;
                        m_pContextRegs[m_EffAddrBaseReg] -= 4;      // pre-decrement stack pointer by 4 ;

                        if (m_EffectiveAddrCount < *pEffectiveAddrCount)
                        {
                            WriteEffectiveAddr(&pEffectiveAddrArray[m_EffectiveAddrCount]);
                        }

                        break;

                    case evCallSpecies:
                        m_bEffAddrBaseRegPresent = TRUE ;
                        m_EffAddrBaseReg = 4;   // base register is ESP/RSP

                        if (m_lbit)
                        {
                            m_OperandSize = evSizeQWord;
                            m_pContextRegs[m_EffAddrBaseReg] -= 8 ;     // pre-decrement stack pointer by 8;
                        }
                        else
                        {
                            m_OperandSize = evSizeDWord;
                            m_pContextRegs[m_EffAddrBaseReg] -= 4 ;     // pre-decrement stack pointer by 4;
                        }

                        m_MemAccessType = WW;

                        if (m_EffectiveAddrCount < *pEffectiveAddrCount)
                        {
                            WriteEffectiveAddr(&pEffectiveAddrArray[m_EffectiveAddrCount]);
                        }

                        break;

                    case evPopSpecies:
                    case evPopadSpecies:
                    case evPopaqSpecies:
                    case evPopfdSpecies:
                    case evLeaveSpecies:
                    case evRetSpecies:
                    case evIretSpecies:
                        m_bEffAddrBaseRegPresent = TRUE ;
                        m_EffAddrBaseReg = 4;   // base register is ESP/RSP

                        if (m_lbit)
                        {
                            m_OperandSize = evSizeQWord;
                        }
                        else
                        {
                            m_OperandSize = evSizeDWord;
                        }

                        if (evPopaqSpecies == extracodes->instr_table.InstSpecies)
                        {
                            m_OperandSize = evSizeQWord;
                        }

                        if (evIretSpecies == extracodes->instr_table.InstSpecies)
                        {
                            m_MemAccessType = WW;
                        }
                        else
                        {
                            m_MemAccessType = RR;
                        }

                        if (m_EffectiveAddrCount < *pEffectiveAddrCount)
                        {
                            WriteEffectiveAddr(&pEffectiveAddrArray[m_EffectiveAddrCount]);
                        }

                        break;

                    case evXlatbSpecies:
                        m_MemAccessType = RR;
                        m_OperandSize = evSizeByte;
                        //The XLAT instruction implicitely accesses memory location DS:[(E)BX + AL]
                        m_EffAddrDisp = m_pContextRegs[3] + (unsigned int)(m_pContextRegs[0] & 0xFF) ;

                        if (m_EffectiveAddrCount < *pEffectiveAddrCount)
                        {
                            WriteEffectiveAddr(&pEffectiveAddrArray[m_EffectiveAddrCount]);
                        }

                        break;

                    case evBoundSpecies:
                        m_MemAccessType = RR ;  // Read access mode
                        m_OperandSize = evSizeDWord;
                        m_EffAddrDisp = *((INT64*)(m_pTraceRecords - 4)) + 4 ;     // Major kludge!!!

                        if (m_EffectiveAddrCount < *pEffectiveAddrCount)
                        {
                            WriteEffectiveAddr(&pEffectiveAddrArray[m_EffectiveAddrCount]);
                        }

                        break;

                    default:
                        break;      // break switch
                }

                *pBuffSize = static_cast<UINT>(m_pTraceRecords - TraceRecs) ;
            }
        }
        else
        {
            *ErrorCode = ErrInDE;
        }

        (*pEffectiveAddrCount) = m_EffectiveAddrCount;
    }

    if (*ErrorCode)
    {
        return E_FAIL;
    }
    else
    {
        return S_OK;
    }
}

HRESULT LibDisassembler::EtchDisassemble(
    BYTE* RawCodeBytes,
    InstructionType* pInstruction,
    BYTE* ErrorCode)
{
    memset(pInstruction, 0x00, sizeof(InstructionType));

    char* pDisasmString;

    *ErrorCode = static_cast<BYTE>(-1);

    if (m_pWrapper)
    {
        pDisasmString = m_pWrapper->Disassemble(RawCodeBytes);

        *ErrorCode = NoError;

        while (1)
        {
            if (pDisasmString == NULL)
            {
                *ErrorCode = ErrInDE;
                break;  // break while
            }

            pInstruction->NumBytesUsed = (BYTE)m_pWrapper->GetLength();

            pInstruction->NumOpCodeBytes = (BYTE)m_pWrapper->GetNumOpcodeBytes();
            pInstruction->OpCodeByte = m_pWrapper->GetOpcode(0);

            // Instruction prefix
            if (m_pWrapper->HasLockPrefix())
            {
                pInstruction->InstrPfxType = evLOCK;
                pInstruction->InstrPrefix = 0xF0;
            }

            if (m_pWrapper->HasRepnePrefix())
            {
                pInstruction->InstrPfxType = evREPNE;
                pInstruction->InstrPrefix = 0xF2;
            }

            if (m_pWrapper->HasRepPrefix())
            {
                pInstruction->InstrPrefix = 0xF3;
                pInstruction->InstrPfxType = evNoPrefix;

                if ((0xA6 == pInstruction->OpCodeByte)
                    || (0xA7 == pInstruction->OpCodeByte)
                    || (0xAE == pInstruction->OpCodeByte)
                    || (0xAF == pInstruction->OpCodeByte))
                {
                    pInstruction->InstrPfxType = evREPE ;
                }
                else
                {
                    pInstruction->InstrPfxType = evREP ;
                }

            }

            // segment prefix
            if (m_pWrapper->HasSegOvrdPrefix())
            {
                switch (m_pWrapper->GetSegmentRegister())
                {
                    case 0:
                        pInstruction->SegmentPrefix = 0x26; // ES
                        break;

                    case 1:
                        pInstruction->SegmentPrefix = 0x2E; // CS
                        break;

                    case 2:
                        pInstruction->SegmentPrefix = 0x36; // SS
                        break;

                    case 3:
                        pInstruction->SegmentPrefix = 0x3E; // DS
                        break;

                    case 4:
                        pInstruction->SegmentPrefix = 0x64; // FS
                        break;

                    case 5:
                        pInstruction->SegmentPrefix = 0x65; // GS
                        break;

                    default:
                        //error if go here
                        break;
                }
            }
            else
            {
                pInstruction->SegmentPrefix = 0x00;
            }

            // Address size override prefix
            if (m_pWrapper->HasAddressOvrdPrefix())
            {
                pInstruction->bAddrSizePrefix = TRUE;
            }
            else
            {
                pInstruction->bAddrSizePrefix = FALSE;
            }

            // operand size override prefix
            if (m_pWrapper->HasDataOvrdPrefix())
            {
                pInstruction->bOpSizePrefix = TRUE;
            }
            else
            {
                pInstruction->bOpSizePrefix = FALSE;
            }

            // ModRM
            if (m_pWrapper->HasModrm())
            {
                pInstruction->bModRMPresent = TRUE;
                pInstruction->ModRMValue = m_pWrapper->GetModrm();
            }
            else
            {
                pInstruction->bModRMPresent = FALSE;
            }

            // SIB
            if (m_pWrapper->HasSib())
            {
                pInstruction->bSIBPresent = TRUE;
                pInstruction->SIBValue = m_pWrapper->GetSib();
            }
            else
            {
                pInstruction->bSIBPresent = FALSE;
            }

            // Immediate data
            if (m_pWrapper->HasImmediateData())
            {
                pInstruction->bHasImmData = TRUE;
                pInstruction->ImmDataValue = m_pWrapper->GetImmediate();
                pInstruction->ImmDataOffset = (BYTE)m_pWrapper->GetImmediateOffset();
            }
            else
            {
                pInstruction->bHasImmData = FALSE;
            }

            if (m_pWrapper->HasDisplacement())
            {
                pInstruction->bHasDispData = TRUE;
                pInstruction->DispDataValue = (unsigned int) m_pWrapper->GetDisplacement();
                pInstruction->DispDataOffset = (BYTE)m_pWrapper->GetDisplacementOffset();
            }
            else
            {
                pInstruction->bHasDispData = FALSE;
            }

            CInstr_ExtraCodes* extracodes = (CInstr_ExtraCodes*)(m_pWrapper->GetExtraInfoPtr());

            if (NULL == extracodes)
            {
                *ErrorCode = ErrInTableHookup;
                break;  // break while
            }

            pInstruction->InstSpecies = extracodes->instr_table.InstSpecies;
            pInstruction->InstProcType = extracodes->instr_table.ProcessorType;
            strcpy_s(pInstruction->Mnemonic, MAX_MNEMONIC_LENGTH, extracodes->instr_table.Mnemonic);

            int NumOperandsInWrapper, NumOperandsInDE, numimplicit;
            NumOperandsInWrapper = extracodes->instr_table.NumOperands;
            NumOperandsInDE = m_pWrapper->GetNumOperands();

            if (NumOperandsInDE > NumOperandsInWrapper)
            {
                *ErrorCode = ErrInTableHookup;
                break;  // break while
            }
            else if (NumOperandsInDE == NumOperandsInWrapper)
            {
                pInstruction->NumOperands = (BYTE)NumOperandsInDE;

                for (int i = 0; i < NumOperandsInDE; i++)
                {
                    pInstruction->Operands[i].OpSize = (eOperandSize)(m_pWrapper->GetOperandSize(i));

                    switch (m_pWrapper->GetOperandType(i))
                    {
                        case n_Disassembler::OPERANDTYPE_REGISTER:

                            switch (pInstruction->Operands[i].OpSize)
                            {
                                case evSizeByte:
                                    pInstruction->Operands[i].BaseReg = (eRegType)(m_pWrapper->GetRegister(i)
                                                                                - evREG_EAX + evREG_AL);
                                    break;

                                case evSizeWord:
                                    pInstruction->Operands[i].BaseReg = (eRegType)(m_pWrapper->GetRegister(i)
                                                                                - evREG_EAX + evREG_AX);
                                    break;

                                case evSizeDWord:
                                    pInstruction->Operands[i].BaseReg = (eRegType)(m_pWrapper->GetRegister(i));
                                    break;

                                case evSizeTByte:
                                    pInstruction->Operands[i].BaseReg = (eRegType)(m_pWrapper->GetRegister(i));
                                    break;

                                default:
                                    pInstruction->Operands[i].BaseReg = (eRegType)(m_pWrapper->GetRegister(i));
                                    break;
                            }

                            pInstruction->Operands[i].AddrMode = evRegister;
                            break;

                        case n_Disassembler::OPERANDTYPE_IMMEDIATE:
                            pInstruction->Operands[i].AddrMode = evImmediate;
                            break;

                        case n_Disassembler::OPERANDTYPE_RIPRELATIVE:
                            pInstruction->Operands[i].AddrMode = evPCRelative;
                            break;

                        case n_Disassembler::OPERANDTYPE_NONE:

                            switch (extracodes->instr_table.InstSpecies)
                            {
                                case evRclSpecies:
                                case evRcrSpecies:
                                case evRolSpecies:
                                case evRorSpecies:
                                    pInstruction->Operands[i].AddrMode = evImmediate;
                                    pInstruction->bHasImmData = TRUE;
                                    pInstruction->ImmDataValue = 1;
                                    pInstruction->ImmDataOffset = 0;
                                    pInstruction->Operands[i].OpSize = evSizeByte;
                                    pInstruction->Operands[i].IsImplicit = TRUE;
                                    break;

                                default:
                                    break;
                            }

                            break;

                        case n_Disassembler::OPERANDTYPE_MEMORY:
                            pInstruction->Operands[i].AddrMode = evMemory;

                            if (m_pWrapper->HasBase())
                            {
                                pInstruction->Operands[i].BaseReg = (eRegType)(m_pWrapper->GetBaseRegister());
                                pInstruction->Operands[i].bBaseRegPresent = TRUE;
                            }
                            else
                            {
                                pInstruction->Operands[i].bBaseRegPresent = FALSE;
                            }

                            if (m_pWrapper->OperandHasIndex(i))
                            {
                                switch (pInstruction->Operands[i].OpSize)
                                {
                                    case evSizeDWord:
                                        pInstruction->Operands[i].IndexReg = (eRegType) m_pWrapper->GetOperandIndexRegister(i);
                                        break;

                                    default:
                                        pInstruction->Operands[i].IndexReg = (eRegType) m_pWrapper->GetOperandIndexRegister(i);
                                        break;
                                }

                                pInstruction->Operands[i].bIndexRegPresent = TRUE;
                            }
                            else
                            {
                                pInstruction->Operands[i].bIndexRegPresent = FALSE;
                            }

                            pInstruction->Operands[i].ScaleFactor = 0x01;

                            if (m_pWrapper->HasScale())
                            {
                                pInstruction->Operands[i].ScaleFactor = 0x01 << m_pWrapper->GetSibScale();
                            }

                            switch (i)
                            {
                                case 0:
                                    pInstruction->Operands[i].MemAccessType =
                                        extracodes->instr_table.OpField1.MemAccessType;

                                    if (nA == pInstruction->Operands[i].MemAccessType)
                                    {
                                        *ErrorCode = ErrInTableHookup;
                                    }

                                    break;

                                case 1:
                                    pInstruction->Operands[i].MemAccessType =
                                        extracodes->instr_table.OpField2.MemAccessType;

                                    if (nA == pInstruction->Operands[i].MemAccessType)
                                    {
                                        *ErrorCode = ErrInTableHookup;
                                    }

                                    break;

                                case 2:
                                    pInstruction->Operands[i].MemAccessType =
                                        extracodes->instr_table.OpField3.MemAccessType;

                                    if (nA == pInstruction->Operands[i].MemAccessType)
                                    {
                                        *ErrorCode = ErrInTableHookup;
                                    }

                                    break;
                            }   // end of swithc (i)

                            break;

                        default:
                            break;
                    } // end of switch
                }   // end of for
            }
            else        // there are implicit operands
            {
                numimplicit = 0;
                pInstruction->NumOperands = (BYTE)NumOperandsInWrapper;

                for (int i = 0; i < NumOperandsInWrapper; i++)
                {
                    COperandField tempoperand;

                    switch (i)
                    {
                        case 0:
                            tempoperand = extracodes->instr_table.OpField1;
                            break;

                        case 1:
                            tempoperand = extracodes->instr_table.OpField2;
                            break;

                        case 2:
                            tempoperand = extracodes->instr_table.OpField3;
                            break;
                    }   // end of switch (i)

                    if (tempoperand.IsImplicit())
                    {
                        numimplicit += 1;
                        pInstruction->Operands[i].OpSize = tempoperand.GetOperandFieldSize();
                        pInstruction->Operands[i].BaseReg = tempoperand.GetOperandFieldReg();
                        pInstruction->Operands[i].IsImplicit = TRUE;

                        if (nA == tempoperand.MemAccessType)
                        {
                            pInstruction->Operands[i].AddrMode = evRegister;
                        }
                        else
                        {
                            pInstruction->Operands[i].AddrMode = evMemory;
                            pInstruction->Operands[i].bBaseRegPresent = TRUE;

                            if (tempoperand.AddrMethod != _EBXAL)
                            {
                                pInstruction->Operands[i].bIndexRegPresent = FALSE;
                            }
                            else
                            {
                                pInstruction->Operands[i].bIndexRegPresent = TRUE;
                                pInstruction->Operands[i].IndexReg = evREG_AL;
                            }

                            pInstruction->Operands[i].MemAccessType = tempoperand.MemAccessType;
                        }
                    }
                    else
                    {
                        int j = i - numimplicit;        // operand index in DE
                        pInstruction->Operands[i].OpSize = (eOperandSize)(m_pWrapper->GetOperandSize(j));

                        switch (m_pWrapper->GetOperandType(j))
                        {
                            case n_Disassembler::OPERANDTYPE_REGISTER:

                                switch (pInstruction->Operands[i].OpSize)
                                {
                                    case evSizeByte:
                                        pInstruction->Operands[i].BaseReg = (eRegType)(m_pWrapper->GetRegister(j)
                                                                                - evREG_EAX + evREG_AL);
                                        break;

                                    case evSizeWord:
                                        pInstruction->Operands[i].BaseReg = (eRegType)(m_pWrapper->GetRegister(j)
                                                                                - evREG_EAX + evREG_AX);
                                        break;

                                    case evSizeDWord:
                                        pInstruction->Operands[i].BaseReg = (eRegType)(m_pWrapper->GetRegister(j));
                                        break;

                                    case evSizeTByte:
                                        pInstruction->Operands[i].BaseReg = (eRegType)(m_pWrapper->GetRegister(i));
                                        break;

                                    default:
                                        pInstruction->Operands[i].BaseReg = (eRegType)(m_pWrapper->GetRegister(i));
                                        break;
                                }

                                pInstruction->Operands[i].AddrMode = evRegister;
                                break;

                            case n_Disassembler::OPERANDTYPE_IMMEDIATE:
                                pInstruction->Operands[i].AddrMode = evImmediate;
                                break;

                            case n_Disassembler::OPERANDTYPE_RIPRELATIVE:
                                pInstruction->Operands[i].AddrMode = evPCRelative;
                                break;

                            case n_Disassembler::OPERANDTYPE_MEMORY:
                                pInstruction->Operands[i].AddrMode = evMemory;

                                if (m_pWrapper->HasBase())
                                {
                                    pInstruction->Operands[i].BaseReg = (eRegType)(m_pWrapper->GetBaseRegister());
                                    pInstruction->Operands[i].bBaseRegPresent = TRUE;
                                }
                                else
                                {
                                    pInstruction->Operands[i].bBaseRegPresent = FALSE;
                                }

                                if (m_pWrapper->OperandHasIndex(j))
                                {
                                    pInstruction->Operands[i].IndexReg = (eRegType)(m_pWrapper->GetOperandIndexRegister(j));
                                    pInstruction->Operands[i].bIndexRegPresent = TRUE;
                                }
                                else
                                {
                                    pInstruction->Operands[i].bIndexRegPresent = FALSE;
                                }

                                pInstruction->Operands[i].ScaleFactor = 1;

                                if (m_pWrapper->HasScale())
                                {
                                    pInstruction->Operands[i].ScaleFactor = 0x01 << m_pWrapper->GetSibScale();
                                }

                                pInstruction->Operands[i].MemAccessType = tempoperand.MemAccessType;
                                break;

                            default:
                                break;
                        } // end of switch
                    }
                }   // end of for
            }

            break;
        }   // end of while
    }

    if (*ErrorCode)
    {
        return E_FAIL;
    }
    else
    {
        return S_OK;
    }
}

HRESULT LibDisassembler::SADisassemble(
    BYTE* RawCodeBytes,
    SAInstInfoType* pDisasmInfo,
    unsigned int* StrLength,
    BYTE* ASCIICode,
    BYTE* ErrorCode)
{
    char* pDisasmString;

    memset(ASCIICode, 0, *StrLength);
    *ErrorCode = static_cast<BYTE>(-1);

    if (m_pWrapper)
    {
        pDisasmString = m_pWrapper->Disassemble(RawCodeBytes);

        *ErrorCode = NoError;
        pDisasmInfo->OpSize[0] = evSizeNone;
        pDisasmInfo->OpSize[1] = evSizeNone;
        pDisasmInfo->OpSize[2] = evSizeNone;
        pDisasmInfo->NumBytesUsed = 0x00;
        pDisasmInfo->NumOperands = 0x00;
        pDisasmInfo->InstSpecies = evNASpecies;
        memset(pDisasmInfo->Mnemonic, 0, MAX_MNEMONIC_LENGTH);

        if (pDisasmString != NULL)
        {
            // Get Operand size
            pDisasmInfo->NumOperands = (BYTE) m_pWrapper->GetNumOperands();

            for (int i = 0; i < m_pWrapper->GetNumOperands(); i++)
            {
                pDisasmInfo->OpSize[i] = (eOperandSize)(m_pWrapper->GetOperandSize(i));
            }

            pDisasmInfo->NumBytesUsed = (BYTE)m_pWrapper->GetLength();

            CInstr_ExtraCodes* extracodes = (CInstr_ExtraCodes*)(m_pWrapper->GetExtraInfoPtr());

            if (NULL == extracodes)
            {
                *ErrorCode = ErrInTableHookup;
            }
            else
            {
                pDisasmInfo->InstSpecies = extracodes->instr_table.InstSpecies;
                *ErrorCode = NoError;
                strcpy_s(pDisasmInfo->Mnemonic, MAX_MNEMONIC_LENGTH, extracodes->instr_table.Mnemonic);
            }

            strcpy_s((char*) ASCIICode, *StrLength, pDisasmString);
            *StrLength = static_cast<UINT>(strlen(pDisasmString));
            *ErrorCode = NoError;
        }
        else
        {
            *ErrorCode = ErrInDE;
        }
    }

    if (*ErrorCode)
    {
        return E_FAIL;
    }
    else
    {
        return S_OK;
    }
}

HRESULT LibDisassembler::SetDefaultSegSize(BOOL DefaultIs32Bits)
{
    m_dbit = DefaultIs32Bits;

    if (m_pWrapper)
    {

        if (m_dbit)
        {
            // if D bit is On, long mod bit should be off
            m_lbit = FALSE;
            m_pWrapper->ClearLongMode();

            m_pWrapper->SetDbit();
        }
        else
        {
            m_pWrapper->ClearDbit();
        }
    }

    return S_OK;
}

redpajama_set_name: RedPajamaGithub


Agastya Mala also known in various names like Agasthyakoodam, Agastyarkoodam or Agathiyar Malai is a 1,868 meters (6,129 ft) peak within Neyyar Wildlife Sanctuary, Kerala. Agasthyakoodam is a pilgrimage centre for devotees of the Hindu sage Agastya, who is considered to be one of the seven rishis (Saptarishi) of Hindu Puranas.
The shrine was installed under the auspices of the Chenkottukonam Madathipathi Jagadguru Swami Sathyananda Saraswathi Thiruvadikal who entered the forests with Hindu Aikya Vedi activists and his followers especially from the Kani Tribe demolished the cross erected by Christians.The Tamil language is considered to be a boon from Agasthya. There is a full-sized statue of Agathiyar at the top of the peak and the devotees can offer pujas themselves.
The mountain lies on the border between the States of Kerala (in Kollam and Thiruvananthapuram District) and Tamil Nadu (in Kanyakumari district, Tirunelveli District). The perennial Thamirabarani River originates from the eastern side of this hill and flows into the Tirunelveli District of Tamil Nadu. Other major rivers which originate from the mountain are the Karamana River, which flows through the Thiruvananthapuram District and is the major source of drinking water to the city, and the Neyyar River (also in the Thiruvananthapuram District).
The peak of Agathiyarmalai can be reached only by trekking up to it. While The Tamil Nadu government allows certain number of applications even though they have strict rules within the wildlife sanctuary. The Kerala government has been favorable to the pilgrims wanting to visit the peak. Every year in the month of May, Sundarampillai (late) from Papanasam used to organize a big group of pilgrims to go on a devotional trek.


Touch Paneel MOB.IQ, add your devices to a group. Then you can switch more devices together in the group that you want.
Beautiful touch panel from MOB.IQ. This touch panel is numbered from 1 to 9. U can add more devices to a number. Than you can use the number and switch more devices together on and off. Very handy to use!


text:
CES Highlights
'Best of CES' Awards
Gadgets You Can Get Now
Trend: 'Rollable' Phones
Trend: Clean Tech
More From CES
Fast Forward Newsletter
Virginia Heffernan
Just Google It: A Short History of a Newfound Verb
The world's most popular search engine became a verb, at the cost of the romance of the early internet.
Google, verb, did instantly seem like a fragment of verse we'd needed since the information superhighway of the 1990s first threatened us with vertigo.Ben Wiseman
A brand reaches its apotheosis when it slips into the vernacular as a generic noun—Band-Aid, Kleenex, even Dumpster. Anyone else's dad still say "Dempster Dumpster," for the brothers who patented it in 1939, and alas, aren't around now to copyright Dempster Dumpster Fire?
To become a verb is even less common. "To Hoover" for "to vacuum" comes to mind. "To Skype," meaning to make a video call, shows modest promise, but since video chatters need to agree on software, it's unlikely Skype can ever stand in for FaceTime or WhatsApp. The rare tech company to achieve verbal dominion over a whole category of digital experience is of course Google, with "to Google."
Larry Page used the verb form two months before the company launched in September 1998. The cutie-pie locution showed up on a listserv for Google-Friends when the search engine lived at http://google.stanford.edu/. (Don't bother; it's too late to join Google-Friends.) After a brief update to his new product, Page signed off to his merry crew, "Have fun and keep googling!" His company's search index is now more than 100 million gigabytes. Evidently, we did.
And thus for insiders, "to Google" started as an intransitive verb; a pastime without an object; search for search's sake; a Sunday drive through cyberspace. But by 2002 we layfolk had gotten our mitts on it and knew what Google was really for—forensics, stalking, the transitive stuff. "Have you Googled her yet?" Willow asks Buffy in the final season of Buffy the Vampire Slayer. "She's 17!" cries Xander, finding some nice prurience in the word. Corrects Willow: "It's a search engine." The next year, the American Dialect Society named Google, transitive verb, "the most useful" word of 2002. The Oxford English Dictionary minted it in June 2006.
Google, verb, did instantly seem like a fragment of verse we'd needed since the information superhighway of the 1990s first threatened us with vertigo. Supplying the illusion of order to the jerry-built tubes and their effluvium has long been the role of the big commercial tech companies. Google's mission is "to organize the world's information." It's Faustian. But "to Google," of course, does not mean "to organize"; it means to submit to Google's organization while pretending you're blazing a bespoke passage through the information Schwarzwald, over the information Rockies, and around the information Horn.
Part of the shared pretending done by Google and anyone who uses it is to act as if "information" on the web already existed in some kind of natural state prior to Google's mission to organize it. Instead, information in its present form is, in fact, a product of Google and would be nothing without the company's decision to recognize it as Googleable, rank it in the algorithm's esoteric hierarchy, and incentivize its renovation so it might make itself prettier to Google. "To Google" something, therefore, is to accept the fiction that Google is both the whole information world—and the only path through it.
What a racket. How did we ever start believing that a highly limited set of visual and symbolic data—words, numbers, and images without depth—make up the entirety of the "world's information"? You can't Google taste, scent, or touch; sound searches are janky. Google engages barely two of the five human senses and tells us that's the whole world.
China's search engine, Baidu, while benighted by censorship, nonetheless has the far better name. "Baidu" derives from "Green Jade Table in the Lantern Festival," a Song dynasty poem by Xin Qiji about the annual festival during which maidens left their houses to be seen and courted. The poem's last line is, "Hundreds and thousands of times, for her I searched in chaos / Suddenly, I turned by chance, to where the lights were waning, and there she stood."
As the Baidu corporate site explains, the company's name evokes "the search for a retreating beauty amid chaotic glamour."
Organizing the world's information sounds ambitious. On the other hand, searching for retreating beauty amid chaotic glamour partakes of the romance that the frayed old internet once used to suggest. But it sometimes seems we have organized and Googled that romance out of existence. And the beauty we once searched expectantly for has retreated for all time.
Virginia Heffernan (@page88) is the author of Magic and Loss: The Internet as Art.
This article appears in the November issue. Subscribe now.
Virginia Heffernan (@page88) is a contributor at WIRED. She is the author of Magic and Loss: The Internet as Art. She is also a cohost of Trumpcast, an op-ed columnist at the Los Angeles Times, and a frequent contributor to Politico. Before coming to WIRED she was a staff writer... Read more
Vsauce Answers the 100 Most Googled Questions
Michael, Kevin, and Jake from Vsauce attempt to answer the 100 most Googled questions.
Topicsgooglelanguages


text:
Northrop receives flight hardware for BAMS UAS programme
Northrop Grumman has received the first complete ship set of flight hardware from Aurora Flight Sciences for the US Navy's broad area maritime surveillance unmanned aircraft system (BAMS UAS) programme.
The delivery of the composite structures package that includes aft fuselage, forward nacelle, mid nacelle, aft nacelle and V-tail assemblies is part of a contract awarded to Northrop in April 2008.
The MQ-4C BAMS UAS is the naval version of the US Air Force's RQ-4 Global Hawk aircraft and is designed to support various missions when operating independently or in collaboration with fleet assets.
The long-endurance system incorporates a 360° multifunction active sensor (MFAS) active electronically scanned array along with navy-specific groundstations.
The multi-mission maritime intelligence, surveillance and reconnaissance system is capable of conducting maritime surveillance, collection of enemy order of battle information, battle damage assessment and port surveillance missions.
The aircraft also provides communication relay and support of maritime interdiction, surface warfare, battlespace management and targeting for maritime and littoral strike missions to the Maritime Patrol and Reconnaissance Force (MPRF).
Additionally, the UAS will enable military commanders to efficiently patrol a wide range of open ocean and littoral regions by providing reliable intelligence information about potential maritime surface threats.
As a member of Northrop's Q-4 Enterprise team since 1995, Aurora's Global Hawk activities include manufacturing complete composite components of the aircraft except the wing and radomes.
Currently in the development and demonstration stages, the aircraft system is expected to make its first flight in 2012.
The MQ-4C BAMS UAS programme is managed by the US Naval Air Systems Command's (NAVAIR) Persistent Maritime Unmanned Aircraft Systems Program Office.
Counter-Unmanned Aerial System (C-UAS) in Aerospace and Defense - Thematic Research
Drones in Aerospace and Defense - Thematic Research
Current Trends and Future Business Dynamics - Unmanned Aerial Vehicles/Unmanned Aerial Systems (UAV/UAS)
Space Systems in Aerospace and Defense - Thematic Research
Military Unmanned Aerial Vehicle (UAV) Market Size and Trend Analysis including Segments (Combat Aerial Vehicle, Medium-Altitude Long-Endurance, High-Altitude Long-Endurance, Vertical Take-Off and Landing and Others), Key Programs, Competitive Landscape and Forecast, 2021-2031
Northrop Grumman Corp
Aurora Corp


Networking company Cisco said Wednesday that it is challenging Microsoft's $8.5 billion takeover of Skype at the European Union's top court to ensure Microsoft won't block other video conferencing services.
Microsoft completed the deal in October shortly after the European Commission, the EU's competition regulator, cleared the takeover. Microsoft Corp. hopes that owning Skype will allow it to better compete with other tech giants including Apple Inc. or Google Inc.
But for Cisco Systems Inc., the world's largest maker of computer networking equipment, the Skype deal creates a serious challenger to its video conferencing systems.
"Cisco does not oppose the merger, but believes the European Commission should have placed conditions that would ensure greater standards-based interoperability," Marthin De Beer, the head of Cisco's video conferencing division, wrote in a blog post.
Video conferencing equipment is a relatively small part of Cisco's overall sales, but it's growing rapidly. Cisco's latest major acquisition was of Tandberg, a Norwegian maker of video conferencing equipment. Cisco spent $3.4 billion for the company in 2010.


text:
Ps Business Parks Incca (PSB) SEC Filing 8-K Material Event for the period ending Tuesday, October 23, 2018
Home SEC Filings Ps Business Parks Incca (PSB) 8-K Material Event Wed Oct 24 2018
Ps Business Parks Incca
Ticker: PSB CIK: 866368
PS Business Parks, Inc.
701 Western Avenue
psbusinessparks.com
For Release:
Jeff Hedges
(818) 244-8080, Ext. 1649
PS Business Parks, Inc. Reports Results for the Quarter Ended September 30, 2018
GLENDALE, California—PS Business Parks, Inc. (NYSE:PSB) reported operating results for the three and nine months ended September 30, 2018.
Operating Results for the Three Months Ended September 30, 2018
Net income allocable to common shareholders was $25.1 million, or $0.92 per diluted common share, for the three months ended September 30, 2018, an increase of $7.0 million, or 38.6%, from $18.1 million, or $0.66 per diluted common share, for the same period in 2017. The increase was mainly due to a charge related to the redemption of preferred stock incurred during the third quarter of 2017 that did not recur in the third quarter of 2018 and an increase in net operating income ("NOI"–described below) with respect to our real estate facilities. The increase in NOI includes a $2.5 million increase for our Same Park facilities (described below) due primarily to an increase in rental rates and occupancy combined with increased NOI from our non-Same Park and multifamily assets, partially offset by reduced NOI generated from facilities we sold before the third quarter of 2018.
Operating Results for the Nine Months Ended September 30, 2018
Net income allocable to common shareholders was $141.4 million, or $5.16 per diluted common share, for the nine months ended September 30, 2018, an increase of $72.1 million, or 104.1%, from $69.3 million, or $2.53 per diluted common share, for the same period in 2017. The increase was mainly due to gain on sale of two office parks in Orange County, California, and an industrial park in Dallas, Texas, during 2018, a charge related to the redemption of preferred stock incurred in the third quarter of 2017 that did not recur in 2018 and an increase in NOI with respect to our real estate facilities. The increase in NOI includes a $4.4 million increase for our Same Park facilities due primarily to an increase in rental rates and occupancy combined with increased NOI from our non-Same Park and multifamily assets, partially offset by reduced NOI generated from facilities we sold in 2018.
Funds from operations ("FFO") per share was $1.64 for the three months ended September 30, 2018, as compared to $1.36 for the same period in 2017, an increase of $0.28 per share. FFO per share was $4.81 for the nine months ended September 30, 2018, an increase of $0.38 per share from the nine months ended September 30, 2017 of $4.43.
FFO is a non-GAAP (generally accepted accounting principles) measure defined by the National Association of Real Estate Investment Trusts and generally represents net income before depreciation and amortization expense, gains and losses from sales and impairment charges with respect to real estate assets.
We also present "Core FFO per share," a non-GAAP measure that represents FFO per share excluding the impact of (i) charges related to the redemption of preferred stock and (ii) separation settlement payments, as well as charges or reversals related to stock based compensation, due to the departure of senior executive. We believe our presentation of Core FFO assists investors and analysts in evaluating our comparative operating performance between reporting periods. However, Core FFO per share is not a substitute for net income per share. Because other real estate investment trusts ("REITs") may not compute Core FFO per share in the same manner as we do, may not use the same terminology or may not present such a measure, Core FFO per share may not be comparable among REITs.
The following table reconciles FFO per share, as reported, to Core FFO per share for the three and nine months ended September 30, 2018 and 2017:
For The Three Months
For The Nine Months
Ended September 30,
FFO per share
Charge related to the redemption of preferred stock
Net impact due to departure of senior executive
Core FFO per share
Property Operations–Same Park Portfolio
To evaluate the ongoing performance of the Company's portfolio over comparable periods, management analyzes the operating performance of properties owned and operated throughout both periods (the "Same Park" facilities). The Same Park portfolio includes all properties we owned and operated as of September 30, 2018 that were acquired prior to January 1, 2016, excluding a held for sale property as of September 30, 2018. As of September 30, 2018, the Same Park facilities constitute 26.9 million rentable square feet, representing 95.1% of the 28.3 million rentable square feet in the Company's total portfolio.
The following table presents the unaudited operating results of the Company's Same Park facilities for the three and nine months ended September 30, 2018 and 2017 (in thousands, except per square foot amounts):
Adjusted cost of operations (1) (3)
Net operating income (2) (3)
Selected Statistical Data
Gross margin (4)
Weighted average square foot occupancy
Annualized rental income per occupied
square foot (5)
(1)Adjusted cost of operations excludes Long-Term Equity Incentive Plan ("LTEIP") amortization, which can vary significantly period to period based upon the performance of the Company.
(2)We evaluate the performance of our business parks primarily based on NOI, a non-GAAP financial measure, because we believe NOI is an important measure of the value and performance of our real estate. We believe investors utilize NOI in a similar manner and for similar reasons. We define NOI as rental income less adjusted cost of operations. NOI excludes depreciation and amortization expense because management and investors do not consider it important in valuing real estate or evaluating real estate performance, because depreciation and amortization expense assumes the value of real estate declines ratably from its historical cost based upon the passage of time, while we believe the value of real estate changes based upon cash flow and other market factors.
(3)Our calculation of adjusted cost of operations and NOI may not be comparable to those of other companies and should not be used as an alternative to measure performance calculated in accordance with GAAP. See "Reconciliation of Selected non-GAAP Measures to Analogous GAAP Measures" below for reconciliations of each of these measures to their closest analogous GAAP measure on our income statements.
(4)Computed by dividing NOI by rental income.
(5)Computed by dividing rental income during the period by weighted average occupied square feet.
The following table summarizes selected unaudited quarterly financial data with respect to the Same Park facilities (in thousands, except per square foot amounts):
Adjusted Cost of Operations
Annualized rental income per occupied square foot
The cost of snow removal and utilities are included in Adjusted Cost of Operations and are broken out here separately for information purposes only.
Property Dispositions
We have two multi-tenant office buildings totaling 107,000 rentable square feet located in Orange County, California, held for sale as of September 30, 2018. As we are under contract, we expect to close on the sale during the quarter ended December 31, 2018.
Distributions Declared
On October 23, 2018, the Board of Directors declared a quarterly dividend of $1.05 per common share. Distributions were also declared on the various series of depositary shares, each representing 1/1,000 of a share of preferred stock. Distributions are payable on December 27, 2018 to shareholders of record on December 12, 2018.
PS Business Parks, Inc., a member of the S&P SmallCap 600, is a REIT that acquires, develops, owns and operates commercial properties, primarily multi-tenant industrial, flex and office space. As of September 30, 2018, the Company wholly owned 28.3 million rentable square feet with approximately 5,050 commercial customers in six states and held a 95.0% interest in a 395-unit apartment complex.
When used within this press release, the words "may," "believes," "anticipates," "plans," "expects," "seeks," "estimates," "intends" and similar expressions are intended to identify "forward-looking statements." Such forward-looking statements involve known and unknown risks, uncertainties and other factors, which may cause the actual results and performance of the Company to be materially different from those expressed or implied in the forward-looking statements. Such factors include the impact of competition from new and existing commercial facilities which could impact rents and occupancy levels at the Company's facilities; the Company's ability to evaluate, finance and integrate acquired and developed properties into the Company's existing operations; the Company's ability to effectively compete in the markets that it does business in; the impact of the regulatory environment as well as national, state and local laws and regulations including, without limitation, those governing REITs; the impact of general economic conditions upon rental rates and occupancy levels at the Company's facilities; the availability of permanent capital at attractive rates, the outlook and actions of Rating Agencies and risks detailed from time to time in the Company's SEC reports, including quarterly reports on Form 10-Q, reports on Form 8-K and annual reports on Form 10-K.
Additional information about PS Business Parks, Inc., including more financial analysis of the third quarter operating results, is available on the Company's website at psbusinessparks.com.
A conference call is scheduled for Wednesday, October 24, 2018, at 10:00 a.m. PDT (1:00 p.m. EDT) to discuss third quarter results. The toll free number is (800) 901-5382; the conference ID is PSBQ318. The call will also be available via a live webcast on the Company's website. A replay of the conference call will be available through November 7, 2018 at (800) 839-5124, as well as via webcast on the Company's website.
Additional financial data attached.
Real estate facilities, at cost
Buildings and improvements
Accumulated depreciation
Properties held for sale, net
Land and building held for development
Investment in and advances to unconsolidated joint venture
Rent receivable, net
Deferred rent receivable, net
LIABILITIES AND EQUITY
Accrued and other liabilities
Preferred stock called for redemption
PS Business Parks, Inc.'s shareholders' equity
Preferred stock, $0.01 par value, 50,000,000 shares authorized,
38,390 shares issued and outstanding at
September 30, 2018 and December 31, 2017
Common stock, $0.01 par value, 100,000,000 shares authorized,
27,346,562 and 27,254,607 shares issued and outstanding at
September 30, 2018 and December 31, 2017, respectively
Paid-in capital
Accumulated earnings (deficit)
Total PS Business Parks, Inc.'s shareholders' equity
Total liabilities and equity
CONSOLIDATED STATEMENTS OF INCOME
(In thousands, except per share amounts)
Cost of operations
General and administrative
Total operating expenses
Interest and other income
Interest and other expense
Equity in loss of unconsolidated joint venture
Gain on sale of real estate facilities
Gain on sale of development rights
Allocation to noncontrolling interests
Net income allocable to PS Business Parks, Inc.
Allocation to preferred shareholders based upon
Allocation to restricted stock unit holders
Net income allocable to common shareholders
Net income per common share
Computation of Funds from Operations and Funds Available for Distribution
Computation of Funds From Operations (1)
Gain on sale of real estate facilities and development rights
Depreciation from unconsolidated joint venture
Net income allocated to noncontrolling interests
Net income allocated to restricted stock unit holders
FFO (income) loss allocated to joint venture partner
FFO allocable to common and dilutive shares
Weighted average outstanding:
Operating partnership units
Restricted stock units
Common share equivalents
Total common and dilutive shares
Net income per common share—diluted
Depreciation and amortization expense, including amounts
from unconsolidated joint venture
FFO per share (1)
Computation of Funds Available for Distribution ("FAD") (1)
Recurring capital improvements
Lease commissions
Straight-line rent
In-place lease adjustment
Tenant improvement reimbursements, net of lease incentives
Non-cash stock compensation expense
Cash paid for taxes in lieu of shares upon vesting of
Capitalized interest
Charge related to the redemption of preferred securities
Distributions to common shares and units
Distribution payout ratio
(1)FFO and FFO per share are non-GAAP measures defined by the National Association of Real Estate Investment Trusts and, along with the non-GAAP measure FAD, are considered helpful measures of REIT performance by REITs and many REIT analysts. FFO represents net income before real estate depreciation and amortization expense, gains or losses and impairment charges, which are excluded because they are based upon historical real estate costs and assume that building values diminish ratably over time, while we believe that real estate values fluctuate due to market conditions. FFO per share represents FFO allocable to common and dilutive shares, divided by aggregate common and dilutive shares. FAD represents FFO adjusted to (a) deduct capital expenditures that maintain the real estate values, tenant improvements and lease commissions and (b) eliminate certain non-cash expenses or income such as straight-line rent and non-cash stock compensation expense. We utilize FAD in evaluating our ongoing cash flow available for investment, debt repayment and common distributions. We believe investors and analysts utilize FAD in a similar manner. FFO and FFO per share are not a substitute for net income or earnings per share. FFO and FAD are not substitutes for GAAP net cash flow in evaluating our liquidity or ability to pay dividends, because they exclude investing and financing activities presented on our statements of cash flows. In addition, other REITs may compute these measures differently, so comparisons among REITs may not be helpful.
Reconciliation of Selected non-GAAP Measures to Analogous GAAP Measures
(Unaudited, in thousands)
Same Park
Non-Same Park
Assets sold or held for sale
Total rental income
LTEIP amortization
Total cost of operations
2,541.6%
View differences made from one to another to evaluate Ps Business Parks Incca's financial trajectory
Compare this 8-K Corporate News to its predecessor by reading our highlights to see what text and tables were removed , added and changed by Ps Business Parks Incca.
https://last10k.com/sec-filings/report/866368/000086636818000020/psb-20181023x8k.htm
https://last10k.com/sec-filings/report/866368/000086636818000020/psb-20181023xex99_1.htm
PSB Valuations
PSB Annual Reports
PSB Quarterly Reports
10-Q Quarterly Report April 2021
10-Q Quarterly Report July 2019
PSB Corporate News
Event for Officers January 2022
Other Events December 2021
Financial Exhibit May 2021
Vote of Security Holders May 2021
Ps Business Parks Incca provided additional information to their SEC Filing as exhibits
Ticker: PSB
Submitted to the SEC: Tue Oct 23 2018 6:12:36 PM EST
Period: Tuesday, October 23, 2018
Industry: Real Estate Investment Trusts
https://last10k.com/sec-filings/psb/0000866368-18-000020.htm


Brasilia (Brazil), July 17 : During his visit to Brazil to attend the VIth BRICS Summit, Prime Minister Narendra Modi also inaugurated the Indian Embassy building in Brasilia with the aim of establishing the country as a new global business centre.
Modi left Brazil on Thursday after attending the five-nation BRICS summit in the coastal city of Fortaleza.
During his visit, Modi met and held bilateral talks with Chinese and Russian President, Xi Jinping and Vladimir Putin, on the sidelines of the BRICS summit.
Modi also met a group of South American leaders to foster cooperation between the two regions.
Fortaleza: Prime Minister Narendra Modi on Tuesday congratulated Brazil for successfully hosting the Football World Cup, saying the "beautiful game" has brought the world together.
"I convey my profound gratitude to our gracious host, President Dilma Rousseff, the people, and the Government of Brazil," Modi said at the BRICS Summit in this Brazilian sea-side city.
"Madam, I congratulate you for successfully hosting the Football World Cup. Truly, the 'beautiful game' brings the world together," he told Rousseff.
Fortaleza (Brazil): Prime Minister Narendra Modi will launch his first multilateral engagement in this seaside city of Brazil, meeting Russian President Vladimir Putin and Chinese President Xi Jinping ahead of Tuesday's BRICS Summit at which India will press for equal shareholding for its five member countries in the proposed USD 50 billion BRICS Development Bank so that no shareholder dominates.
Brasilia (Brazil), July 14 - Germany were crowned world champions for the fourth time on Sunday, after Mario Gotze's extra-time winner beat Argentina in the 2014 World Cup final.
Gotze demonstrated perfect technique and commendable calm to chest down Andre Schurrle's pass and sweep in a left-foot finish with the prospect of a penalty shootout only seven minutes away.
With this win, Germany claimed their first World Cup since they beat the same opponents in Rome 24 years ago.
Sao Paulo: India's largest two-wheeler maker, Hero MotoCorp, plans to set up a plant in South India, its sixth overall, to cater to the domestic market and take its overall annual capacity to 12 million units.
"We are looking to set up a plant in South India. It will be utilised to service the market there. We are scouting for land at the moment," Hero MotoCorp Manging Director and CEO Pawan Munjal said.
He, however, did not share the details regarding the timeline for the completion as well as the location of the plant.
Sao Paulo: Hero MotoCorp, India's largest two-wheeler maker, is looking to start selling bikes in the US next year, hoping to create a niche market for its products.
"For the developed western markets (US) currently, we are not that much focused on bigger motorcycles. Right now, what we are looking at is taking some of our current products and try creating a niche market," Hero MotoCorp Managing Director and Chief Executive Officer Pawan Munjal said here.
Sao Paulo: India's largest two-wheeler maker Hero MotoCorp is planning to enter Brazil by 2016 as it looks to consolidate position in the fast growing South American market.
It also plans to begin work on its manufacturing facility in Columbia in the next two months, investing USD 70 million.
"We are looking to enter Brazilian market around the Olympics in 2016. We are developing some engines specifically for this market. Its an attractive market for us," Hero MotoCorp Managing Director and CEO Pawan Munjal.
Rio de Janeiro, May 15 - Brazilian authorities have agreed to cooperate with Portugal over a criminal case involving Brazil's football coach Luiz Felipe Scolari.
Scolari is being investigated for tax fraud after allegedly failing to declare seven million euros of income.
The attorney general's office in Brazil (PGR) confirmed Wednesday it had agreed to cooperate with its Portuguese counterpart, reported Xinhua.
No further details were given by the PGR due to the "confidential" nature of the investigation.
Rio de Janeiro, May 14 - Brazil coach Luiz Felipe Scolari has named Atletico Madrid defender Miranda among seven reserves for the FIFA World Cup in Brazil.
The 29-year-old former Sao Paulo centre-half will be joined by his Atletico teammate Filipe Luis, who is on standby at left-back, reports Xinhua.
Bayern Munich right-back Rafinha was also named, as was Liverpool's Lucas Leiva, Paris Saint-Germain's Lucas and Fluminense goalkeeper Diego Cavalieri.
Rio de Janeiro, May 10 : Brazil's October presidential elections may feature a second round, as support for incumbent President Dilma Rousseff falters and her contenders gain strength, according to an opinion poll.
The latest Datafolha poll, the results of which were declared Friday, showed that support for Rousseff has slid to 37 percent from 38 percent in the previous poll, while Aecio Neves, candidate of the main opposition Brazilian Social Democracy Party, gained four percentage points to 20 percent.
Support for Brazilian Socialist Party candidate Eduardo Campos gained one point to 11 percent, Xinhua reported.
Rio de Janeiro, April 29 : Brazilian president Dilma Rousseff has lent her support to Dani Alves, saying the Barcelona defender was "brave and strong" for eating a banana thrown at him by a fan.
Rousseff said Sunday's incident reinforced the need to "champion the fight against racism in sport" during the World Cup, to be played in Brazil from June 12 to July 13, reports Xinhua.
"We are going to show that our strength in football, and in life, comes from our ethnic diversity and that we are proud of it," Rousseff wrote on her official Twitter account Monday.
Sao Paulo, April 24 : Brazilian President Dilma Rousseff said at a gathering here Wednesday that no country can have "more weight than another" in governing cyberspace.
She made her remarks at the opening of the NETMundial international conference, where delegations from more than 85 countries will debate internet regulation issues and try to reach agreement on a new oversight model.
Sao Paulo, April 23 - Kaka's former club Sao Paulo has expressed interest in signing the playmaker in the next transfer window.
"I would really like to have Kaka here," Xinhua quoted Sao Paulo's new president Carlos Miguel Aidar as saying Tuesday, although admitting the club where Kaka began his career in 2001 might not be able to afford the midfielder's wage demands.
Kaka has shown glimpses of his best form since returning to AC Milan last September after a turbulent four-year spell at Real Madrid.
Rio de Janeiro, April 17 : The Brazilian government will ensure security in the FIFA World Cup which will take place in 12 Brazilian cities in June, President Dilma Rousseff said.
According to the president, the government has beefed up security for the World Cup and will not allow the tournament to be disturbed by violent episodes, reports Xinhua.
Rio De Janeiro, April 9 : Cuban-American rapper Pitbull joins Jennifer Lopez and Brazil's Claudia Leitte in the official World Cup football song released by FIFA.
The track, "We Are One (Ole, Ola)", featuring an acoustic guitar and an upbeat rhythm with lyrics promoting peace and unity, was released Tuesday reports Xinhua. A video-clip filmed in Florida is expected to debut later this month.
Pitbull, Lopez and Leitte will perform the song before the opening World Cup match between Brazil and Croatia in Sao Paulo June 12.
Rio de Janeiro, April 9 - Napoli defender Bruno Uvini has started training with Brazilian outfit Santos following his arrival on a nine-month loan.
The 22-year-old is expected to make his debut for the club in its Copa do Brasil fixture against Mixto next week, reported Xinhua.
Uvini has struggled for first-team opportunities since being signed by Napoli from Sao Paulo in 2012.
Santos secured him just before the close of Brazil's international transfer deadline April 1.
Rio de Janeiro, April 3 - Brazilian giants Fluminense have announced Cristovao Borges as their new coach, replacing former Brazil international winger Renato Gaucho.
Gaucho was dismissed Wednesday following the team's elimination from the Rio de Janeiro state championship by rivals Vasco da Gama, reported Xinhua.
Borges, 54, who last year coached Bahia, began his managerial career at Vasco da Gama in 2011.
He is a former player at Fluminense, and helped the club win the Rio championship in 1980.
Rio de Janeiro, March 23 - Brazil assistant coach Carlos Alberto Parreira said Ronaldinho lacked the "dedication" needed for an international recall ahead of this year's World Cup.
Ronaldinho, 34, has not played for the Selecao since April 2013 and is struggling to recapture his best form for Atletico Mineiro this year, Xinhua reported citing a Brazilian newspaper Sunday.
"It isn't that he has lost his focus, he just hasn't been able to continue his career in the way that is needed to play with the Selecao with complete and total dedication," said Parreira.
Rio de Janeiro, March 13 - World Cup winner Lilian Thuram says players are partly responsible for continued racism in football.
Thuram was speaking at the the Programa Africa Hoje anti-racism campaign here and admitted he was dismayed by a spate of recent incidents in Brazil, reported Xinhua.
"When all players decide to walk off the pitch because of racist abuse, the situation might improve," the former France defender said.
Rio de Janeiro, March 8 - Santos and Brazil midfielder Arouca has described as "unacceptable" and "serious" the racist taunts directed at him during his team's 5-2 victory over Mogi Mirim in a Sao Paulo state championship match.
The fan's abuse, which came as Arouca walked off the pitch Thursday night, was captured by television microphones.
The 27-year-old urged Brazilian authorities to take swift and "severe" action against the fan, reported Xinhua.