If you could find out whether your newborn baby is at risk of developing treatable early-onset genetic diseases, would you want to know? A recent poll, commissioned by Sema4 and conducted online by Harris Poll, found that nine out of ten Americans would want this knowledge. Similarly, 87% of Americans said that they would likely request a supplemental non-invasive DNA test if their state's newborn screening panel test did not cover many of the treatable conditions that could affect a child in their first years of life. I recently sat down with two new moms who did just that, ordering Sema4 Natalis, our new supplemental newborn screening test which screens for 193 early onset genetic diseases – around five times the number tested for on a typical state-mandated "heel prick" screen – all of which are treatable. The test also includes a genetic analysis of how a child is likely to respond to 38 medications commonly prescribed during childhood. This pharmacogenetic information can help pediatricians personalize treatment for a child and avoid adverse effects or incorrect doses of drugs, including antibiotics.
Once a physician has approved the order on the basis of answers to a brief medical survey, the Natalis kit is sent out in the mail so that DNA samples can be collected at home. A gentle cheek swab is used to obtain the DNA, a procedure that's easy on the babies and the parents. "Eva didn't mind; we didn't mind. It was a very easy process," said Michelle. "I've never done an at-home DNA test, so it was totally foreign, but it couldn't have been easier. The instructions were very clear." Kathryn's son, Asher, was also completely onboard with the genetic sampling going on in his mouth: "He thought it was a pacifier," she joked.
While neither baby's disease screen indicated the need for further action, the results of the accompanying pharmacogenetic screen gave the moms useful, actionable information on how their children would respond to a variety of medications commonly prescribed during the early years. The medication report provides descriptions of what the different drugs are and how they are used, outlines how the child is likely to respond to each, and includes a summary that a parent can print out to give to their child's pediatrician, as well as keeping in his or her wallet.
In addition to providing information on which drugs should be used with caution or, if possible, avoided, the medication screen also lets parents know which medications can be used with just standard precautions. Eva, for example, is predicted to respond normally to thiopurines, a class of anticancer drugs, as is Asher. This information will be valuable to them and their pediatricians growing up, should they ever need these medications.
Kathryn would like to see supplemental newborn screening, like that provided by Natalis, become increasingly common "for diseases that are treatable. For the minimum amount of effort, you can actually get results that are actionable. That makes a big difference," she told me.
Kathryn and Michelle were provided access to Natalis free of charge.


SPY Kids, a program of fellowship and service designed for 4th and 5th graders, will celebrate the end of another fun year on Sunday, April 28 with a picnic and games at Maumelle Park. We will bless and "say good-bye" to our graduating 5th graders and will welcome our rising 4th graders.
Hot dogs, chips, cookies, and drinks will be provided. Parents and siblings invited!
Please RSVP to Jeannie Ford, jeannieford@secondpreslr.org.


Well, the holidays have pretty much come and gone and we've got one last hoorah before we transition into a new year – 2017, please be good to us.
With the New Year comes a metaphorical refresh; a chance for people to start over, set goals and better themselves. Inevitably for most however, those goals and self-improvement efforts fail miserably after just the first few weeks.
We've done a little research and found seven secrets, according to Forbes, of people who succeed in keeping their new year's resolutions. We've picked our three favorites and shared them with you here.
It's so easy to say "I'm going to be a better person this year." –But being more specific in your resolutions (so long as they're realistic) will make your goals seem more attainable. Instead, elaborate on how you can be a better person. Promise to call a relative or friend once a week or visit home twice a year and go ahead and schedule those things.
The more people who know what you intend to do with yourself in 2017, the more awkward it will be if you fail. Seriously though, make your goals known to the people closest to you and whoever you want to see you succeed. Not only will you want to impress these people, they can help motivate you and cheer you on along the way.
You're not going to change who you are long term overnight and you can't expect to achieve your goals with total ease. You're going to backtrack a little or slip up along the way but the important thing is that you keep moving forward when you do. Learn from your mistakes and use them to motivate you even more to become the person you want to be in 2017 and for years to come.
No matter your personal goals, we hope that you will take these tips to heart and use them to achieve whatever it is you're hoping to accomplish, big or small. To read the entire Forbes article, click here.


text:
NASA's SL-8 Rocket Becomes Spaceport America's 20th Launch
Source: Spaceport America
©Spaceport America
SL-8 Rocket
New Mexico Spaceport Authority (NMSA) officials announced the launch today of the second NASA "Flight Opportunities Program" rocket from Spaceport America.
The public launch of SpaceLoft(TM) XL 8 (SL-8), which was designed to reach sub-orbital space, took place this morning from Spaceport America's Launch Complex-1.
Today's liftoff marks the 20th launch at Spaceport America and the 12th flight conducted by UP Aerospace, a long-term spaceport long term customer.
The successful launch of NASA's SL-8 commercial-space, researchpayload rocket took place at approximately 9:15 AM (MDT), which was within the dedicated 2.25-hour launch window, and flight data indicates the rocket attained a maximum altitude of approximately 116 km or 72.2 miles. The parachute recovery system brought the SpaceLoft(TM) rocket and its payload safely back and it was recovered intact 40 km approximately 25 miles downrange on White Sands Missile Range as planned.
"It is great to have NASA back at Spaceport America and to have the opportunity to support their second 'Flight Opportunities' sub-orbital launch today," said NMSA Executive Director Christine Anderson. "We also want to congratulate UP Aerospace, who has been launching with us since the beginning, on their 12th launch from the spaceport."
The SL-8 sub-orbital sounding rocket, provided by UP Aerospace, is part of the NASA "Flight Opportunities Program," which is designed to provide sub-orbital payload launch resources for NASA and other government agencies, as well as for educational institutions and the private sector. Some of the "Flight Opportunities" payload customers for this launch include: New Mexico State University, New Mexico Tech, FAA, NASA, SatWest and the Department of Defense.
Payload integration services for today's SL-8 launch were provided by Schafer Corporation of Albuquerque, NM.
TAGS: Spaceport America
FILED UNDER: Spaceport America
New Mexico Spaceport Authority (NMSA) officials announced the launch today of the second NASA \"Flight Opportunities Program\" rocket from Spaceport America.

redpajama_set_name: RedPajamaCommonCrawl


text:
2 x 2 Simulation
Explore the accuracy of the Chi Square test.
Determine the extent to which the Yate's correction affects the accuracy of the test.
The Chi Square Test is an approximate not an exact test. This simulation allows you to examine the accuracy and power of the Chi Square Test in a variety of situations. The significance of the difference between the proportion who succeed in Condition 1 and the proportion who succeed in Condition 2 is tested.
With the default parameters, the probability of success is the same (0.60) in both conditions so the null hypothesis is true. The default sample size is 10 per condition and the default significance level is 0.05.
Some authors have suggested that a correction called the "Yates Correction" be done whenever the expected frequency of any cell is below five. A test without this correction and one with the correction (if a cell has an expected frequency bellow five) is conducted for each simulated experiment.
If you click the "Simulate 1" button, one simulated experiment will be conducted. The observed and expected frequencies are presented as well as the Chi Square Test with and without the Yates correction. A tally of the number of times the tests were significant is shown below.
If you click the "Simulate 1000" (or 5000) button then 1000 (or 5000) simulated experiments are conducted and the numbers of significant and non-significant tests are shown.
1. Using the default values, click on the "Simulate 1" button. Note the number of successes and failures in each of the two conditions. Note the value of the Chi Square with and without the Yate's correction. Was either significant? Check the lower sectioon that shows the count of the number significant. Most likely, it will show one nonsignificant.
2. Test whether the Type I error rate is close to the nominal significance level of 0.05. Do this by clicking the "Simulate 5000" button several times. Compare the proportion significant to 0.05. Look at the results both when the Yates correction is never used and when it is used when an expected cell frequency is less than 5. Is the test conservative (proportion significant < 0.05) or is it liberal (proportion significant > 0.05)
3. Redo the previous simulations when the probability of success is .50 for each condition. Are the results similar? Try making one of the sample sizes 10 and the other one 6.
4. Try to find a set of parameters such that the proportion significant is greater than 0.06. (Make sure the null hypothesis is always true -- that the probability of success is the same for both conditions.) Could you find such a set of parameters? Are there many circumstances in which the test is that liberal? Do you think the Yates correction is a good procedure?
5. Now consider cases in which the probability of success is different for the two conditions. Here the null hypothesis is false so the higher the proportion significant the better. What is the effect of using the Yates correction on rejecting a false null hypothesis?
The demo begins by running a single simulation, which turns out to be not statistically significant. The video concludes by running 1,000 simulations and then 5,000 simulations.
Try changing the proportions of the conditions?
We recommend you answer the questions even if you have to guess. Then use the simulation to help you verify your answers. After interacting with the simulation click the "Check Answer" button.
You can change the proportions of the conditions as well as the sample size of the simulation parameters.


Presenting in front of a panel of unknowns can be intimidating. How do you differentiate YOU from other SalesPeople/ServiceProviders? This is an effective tool I use to "humanize" myself when presenting to groups both large and small to establish a personal connection. Let me know what you think in the comments!!!
How To Establish a Relationship of Trust in 90 Seconds!


text:
Q: Do not understand the work of the regular expression "She's the one!".match(/['"](.+?)['"]/g);

Why is the result of Null? The idea is to be a coincidence "She'?

A: It matches text between two quote mark or apostrophe characters. The string only has one in it. (The " that are used to delimit the string literal are not part of the data in the string).

A: You're trying to match the outer quotes, which is unneeded
You can get your desired answer by using:
"She's the one!".match(/(.+?)['"]/g);

redpajama_set_name: RedPajamaStackExchange


text:
A.G. challenged to a public debate
By Sarafina Sanerivi • 29 March 2017, 12:00AM
A former Senior Sergeant, Siripa Uelese, has dared the Attorney General, Lemalu Hermann Retzlaff, to a public debate over the handling of the case, which led to the first lot of charges against the Police Commissioner.
The challenge from Siripa is made in a statement she issued to the Samoa Observer in relation to the Attorney General's Office handling of the case of the Police Commissioner.
"The Attorney General is still in denial of all these, and I challenge him to a public debate and let the people of Samoa decide," she said.
Siripa also challenged the decision by the private prosecutor hired by the Attorney General, Paul Dacre, to withdraw the charges.
She questioned his role as a prosecutor.
According to Siripa's statement, she strongly questions the relationship between the Attorney General and the Police Commissioner.
She also questioned the decision by Mr. Dacre to drop the charges without considering the evidence she had worked so hard to collect to prepare for the Court.
She insists that the Attorney General should have recommended to Cabinet for a Tribunal to look into the conduct of the Police Commissioner in relation to Suitupe Misa's case, just as he did with the former Director and Assistant Director of the National Prosecution Office (N.P.O), Mauga Precious Chang and Muriel Lui.
Last night, Attorney General Lemalu rejected the challenge from Siripa in a letter to the Samoa Observer.
Written in Samoan, he said there is no valid reason for the Office of the Attorney General to be engaged in a debate with a former public servant, in this case a Police officer, who has resigned from her job.
Lemalu added that his Office has nothing to do with the reasons behind Siripa's resignation.
He said the matters raised by Siripa have already been dealt with by the Court and Cabinet and therefore are officially closed.
Lastly, he said the Office of the Attorney General has moved on to fulfill it's calling and he prays for peace upon Siripa and her family.
Siripa was suspended last month and when she was asked to report back to work, she tendered her resignation instead. She then broke her silence during an interview with the Samoa Observer, about some of the things she believed were not handled properly during the case.
Sergeant Siripa Uelese interviewed and compiled a file of witnesses in the case where a member of the public was wrongfully arrested at the Fugalei Market, which was the beginning of the charges against the Police Commissioner.
She claims to have all copies of documents to prove her argument.
Siripa said she wants people to know the "other side of the story."
She claimed that there is far more behind the decision to suspend her which is why she has decided to speak up.
Siripa had been working at the National Prosecution Office as an Investigation Officer. It was there she became involved in the Misa Suitupe case, where the man was wrongfully arrested at gunpoint at the Fugalei Market.
An investigation by the Ombudsman proved this.
As the Investigation Officer who was there from the beginning, Siripa said there were developments, which saddened her. At one point during the hearing of the first lot of charges against the Commissioner, Siripa said they were looking for people who were present at the time the gun was pointed at Suitupe's head.
"I was shocked," said Siripa. "How was that possible? I was the Investigating Officer and I prepared all the documents and statements of all the witnesses."
She said all this was ready for Court.
"What I didn't get was why this lawyer who is representing the A.G's office is saying that they need to find witnesses when I already put together everything from the beginning in a file."
"How can they say that there are no witnesses, when I was the one who conducted the investigation and compiled the file?"
"The investigation was the confirmation of statements of those who were involved in the case. The Ombudsman's report was the foundation of the investigation," she said.
"My instructions were to confirm all the statements included in the report, including the victim (Suitupe Misa) and everyone who were at the market and witnessed what happened on the 18th of August, 2015."


text:
Archibald Constable (24 de Fevereiro de 1774 — 21 de Julho de 1827), foi um editor escocês. Em 1812 comprou os direitos autorais da Enciclopédia Britânica.

Encyclopædia Britannica
Constable, Archibald
Naturais de Fife

redpajama_set_name: RedPajamaWikipedia


text:
Zaječar (; deutsch veraltet Zatitscher; ) ist  eine Stadt in Ostserbien, gelegen in der sogenannten Timočka Krajina. Sie ist der Verwaltungssitz der Gemeinde Zaječar sowie des Bezirks Zaječar. In der Stadt leben heute schätzungsweise 40.000 Einwohner.

Zaječar wird vom Crni Timok durchflossen, der sich nördlich Zaječars mit dem Beli Timok zum (Veliki) Timok vereinigt. Die Stadt ist Sitz der Eparchie Timok der Serbisch-Orthodoxen Kirche.

Name

In der serbischen Sprache ist die Stadt als Зајечар oder Zaječar bekannt. In der rumänischen Sprache wird die Stadt Zăii-cer, Zăiceri oder Zăicear genannt.

In der serbischen, bulgarischen und torlakischen Sprache wird der Name vom Hasen abgeleitet, serb. Zec, bulgarisch заек (zaek), torlakisch Zajec. Der Name Zăii-cer auf Rumänisch bedeutet wiederum Götter sind (für die Opfer) gefragt.

Geschichte

Die Stadt Romuliana befand sich im 3. Jahrhundert nach Christus in der Nähe von Zaječar. Die gleichnamige Ausgrabungsstätte verfügt über ein kleines Besucherzentrum. Zu besichtigen sind Reste der Befestigungen sowie Säulenfragmente und Bodenmosaike. Weitere Fundstücke befinden sich im Museum der Stadt.

Das erste Mal wird die Stadt unter ihrem heutigen Namen im Jahre 1466 in osmanischen Aufzeichnungen erwähnt. Damals lebten hier nur acht Familien. 1834 wurde die Serbisch-orthodoxe Mariä-Geburt-Kathedrale erbaut.

In der Stadt findet alljährlich die Gitarriade von Zaječar statt. 2006 wurde die serbische Triathlon-Meisterschaft hier abgehalten.
Darüber hinaus verfügt die Stadt über eine ausgedehnte Freizeit- und Erholungsanlage am Timokufer mit gepflegtem Strand und Bühne sowie Plätzen für die unterschiedlichsten Ballsportarten, darunter eine große parkähnlich angelegte Bahnengolfanlage.

Verkehr

Zajecar liegt an Europastraßen wie E 761 sowie E 771 mit folgenden Verbindungen:
 Paraćin – Zaječar – Bulgarien
 Paraćin – Zaječar – Negotin – Kladovo – Rumänien
 Paraćin – Zaječar – Knjaževac – Niš
 Negotin – Zaječar – Knjaževac – Niš.

Söhne und Töchter der Stadt

Svetozar Marković (1846–1875), Politiker
Veljko Petrović (1780–1803), serbischer Heiducke und Woiwodenführer
Nikola Pašić (1845–1926), serbischer Premierminister
Zoran Radmilović (1933–1985), Schauspieler
Jo Mikovich (1940–2014), Jazzmusiker
Živorad Smiljanić (* 1942), Politiker
Mirko Cvetković (* 1950), ehemaliger Premierminister
Nena Lekovic (* 20. Jahrhundert), Liederschreiberin
Živojin Juškić (* 1969), Fußballspieler
Saša Živulović (1972–2023), griechisch-serbischer Handballspieler
Ivana Sert (* 1979), Fernsehmoderatorin
Suzana Dinić (* 1986), Sängerin
Boban Marjanović (* 1988), serbischer Basketballspieler
Dragan Stanković (* 1985), serbischer Volleyballspieler

Römische Herrscher
 Galerius
 Maximinus Daia
 Licinius

Einwohner

Laut Volkszählung 2002 (Eigennennung) gab es 39.491 Einwohner, davon waren die meisten serbisch-orthodoxe Serben.

Weitere Volkszählungen:

Klimatabelle

Partnerstädte

  Widin, Bulgarien
  Calafat, Rumänien

Galerie

Einzelnachweise

Ort in der Opština Zaječar


People in London like to live in a clean and hygienic environment. At the same time, lives are also getting hectic and most Londoners have to deal with tight deadlines which leave them with little time to carry out their daily domestic cleaning. In times such as these, professional service providers are making lives a lot easier for people. One such essential domestic chore is the periodic cleaning of the carpets.
Professional carpet cleaners in London have done a lot to make this chore really easy for people. An unclean carpet can be quite a nuisance. It can spoil the look of your house and can also harbour various germs and disease causing bacteria which can severely bring down the hygiene levels of your home. Professional carpet cleaning will ensure that your carpet gets deep cleaned and all the disease causing bacteria get completely eliminated.
Professional carpet cleaning in London is the best way to ensure that your carpet stays clean and germ-free. The cleaners will also make sure that your carpet gets cleaned according to its fabric requirements. Professional carpet cleaning companies make use of customised equipment to ensure proper cleaning of the carpet, so you will be able to keep your carpets clean and get the desired hygiene levels in a convenient manner.


text:
JP2007043661A - Delay circuit - Google Patents
Delay circuit Download PDF
JP2007043661A JP2006147587A JP2006147587A JP2007043661A JP 2007043661 A JP2007043661 A JP 2007043661A JP 2006147587 A JP2006147587 A JP 2006147587A JP 2006147587 A JP2006147587 A JP 2006147587A JP 2007043661 A JP2007043661 A JP 2007043661A
mos transistor
pmos
Fumiaki Kuramori
文章 倉盛
Oki Electric Ind Co Ltd
沖電気工業株式会社
2005-06-30 Priority to JP2005190964 priority Critical
2006-05-29 Application filed by Oki Electric Ind Co Ltd, 沖電気工業株式会社 filed Critical Oki Electric Ind Co Ltd
2006-05-29 Priority to JP2006147587A priority patent/JP2007043661A/en
230000036887 VSS Effects 0 abstract 1
238000000034 methods Methods 0 abstract 1
H03—BASIC ELECTRONIC CIRCUITRY
H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
H03H11/00—Networks using active elements
H03H11/02—Multiple-port networks
H03H11/26—Time-delay networks
A delay circuit capable of compensating for a variation in delay time due to a process variation and a power supply voltage variation is provided.
A delay PMOS is connected to a delay circuit in which normal CMOS type inverters 10 and 30 and modified inverters 20P and 40P in which a delay PMOS is added to a power supply voltage VDD terminal are alternately connected in cascade. , 43 is provided with a correction circuit 60 for supplying a control signal VP. The correction circuit 60 includes a PMOS 61 diode-connected in the forward direction and resistors 62 and 63 that connect the drain of the PMOS 61 to the terminal side of the ground voltage VSS, and is controlled from an internal node N60 between the resistors 62 and 63. The signal VP is output. As a result, when the power supply voltage VDD rises, the voltage of the control signal VP also rises, the gate-source voltages of the delay PMOSs 23 and 43 are kept constant, the drain current does not change, and the delay time is kept constant. .
[Selection] Figure 1
The present invention relates to compensation for power supply voltage fluctuation and temperature fluctuation in a delay circuit.
Conventionally, as a delay circuit for signal delay constituted by using a plurality of stages of inverters, for example, there are those described in the following documents.
JP-A-7-38394 JP-A-9-214306
FIG. 2 is a circuit diagram showing a configuration example of a conventional delay circuit described in Patent Document 1. In FIG.
The delay circuit shown in FIG. 2 has a desired delay time when the input signal VI transitions from a high level (hereinafter referred to as "H" level) to a low level (hereinafter referred to as "L" level). This is a circuit that produces and outputs an output signal VO. This delay circuit includes a P-channel MOS transistor (hereinafter referred to as "PMOS") and an N-channel MOS transistor (hereinafter referred to as "NMOS"), and delays the input signal VI to output an output signal VO. An inverter circuit; a correction circuit 1 for supplying a control signal NO for delay time correction to the NMOS constituting the four-stage inverter circuit; and a delay time correction for the PMOS constituting the four-stage inverter circuit. And a correction circuit 2 for supplying a control signal NO.
The four-stage inverter circuit includes a first-stage modified inverter I1 that outputs the delayed signal Va by inverting the input signal VI, and a second-stage modified inverter that outputs the delayed signal Vb by inverting the signal Va. I2 and a third-stage modified inverter I3 that outputs the delayed signal Vc by inverting the signal Vb, and a fourth-stage modified inverter I4 that outputs the delayed output signal VO by inverting the signal Vc. ing.
The first-stage modified inverter I1 includes a PMOS p2 whose gate electrode (hereinafter simply referred to as "gate") is controlled by a control signal PO output from the correction circuit 2, a PMOS p1 whose gate is controlled by an input signal VI, The NMOS n1 whose gate is controlled by the input signal VI, and the source electrodes (hereinafter simply referred to as "source") and the drain electrodes (hereinafter simply referred to as "drain") of the PMOSs p2 and p1 and the NMOS n1, respectively. A power supply terminal to which the power supply voltage VDD is applied (hereinafter referred to as "VDD terminal") and a ground terminal to which the ground voltage VSS is applied (hereinafter referred to as "VSS terminal") are connected in series.
The second-stage modified inverter I2 includes a PMOS p3 whose gate is controlled by the signal Va, an NMOS n3 whose gate is controlled by the signal Va, and an NMOS n2 whose gate is controlled by the control signal NO output from the correction circuit 1. The sources and drains of these PMOSp3 and NMOSn3 and n2 are connected in series between the VDD terminal and the VSS terminal.
The third-stage modified inverter I3 includes a PMOS p5 whose gate is controlled by a control signal PO, a PMOS p4 whose gate is controlled by a signal Vb, and an NMOS n4 whose gate is controlled by a signal Vb. The sources and drains of p4 and NMOS n4 are connected in series between the VDD terminal and the VSS terminal.
The fourth-stage modified inverter I4 includes a PMOS p6 whose gate is controlled by a signal Vc, an NMOS n6 whose gate is controlled by a signal Vc, and an NMOS n5 whose gate is controlled by a control signal NO. The sources and drains of the NMOSs n6 and n5 are connected in series between the VDD terminal and the VSS terminal.
The correction circuit 1 includes a resistor r1, an internal node N1 that outputs a control signal NO, and an NMOS n7 whose gate is controlled by a signal CE. The resistor r1, the internal node N1, and the NMOS n7 are connected to a VDD terminal and a VSS terminal. Are connected in series. The signal CE applied to the gate of the NMOS n7 becomes the power supply voltage VDD during operation, and becomes the ground voltage VSS during standby.
The correction circuit 2 includes a PMOS p7 whose gate is controlled by a signal / CE, an internal node N2 that outputs a control signal PO, and a resistor r2. The PMOS p7, the internal node N2, and the resistor r2 are connected to the VDD terminal and the VSS. It is connected in series between the terminals. The signal / CE applied to the gate of the PMOS p7 becomes the ground voltage VSS at the time of operation, and becomes the power supply voltage VDD at the time of standby.
Next, the operation of the delay circuit shown in FIG. 2 will be described.
When the input signal V1 falls from the "H" level to the "L" level, the input signals Va and Vc of the modified inverter I2 and the modified inverter I4 transition from the "L" level to the "H" level. At this time, the dimensions of the NMOSn2 and NMOSn5 and the voltage of the control signal NO of the correction circuit 1 are set so that the NMOSn2 and NMOSn5 determine the current values that the modified inverter I2 and the modified inverter I4 pass to the VSS terminal side, respectively. ing.
Here, when the NMOS threshold voltage Vtn is decreased due to process variations, the voltage of the control signal NO of the correction circuit 1 is decreased, and therefore the on-resistance value is reduced due to the decrease of the threshold voltage Vtn of the NMOSn2 and NMOSn5. The effect of increasing the on-resistance value due to the decrease in the gate voltage is canceled (cancelled), and the delay time of the modified inverter I2 and the modified inverter I4 is almost the same as the case where the threshold voltage Vtn is the standard value. Further, when the threshold voltage Vtn is large, the effect of increasing the on-resistance value due to the increase in the threshold voltage Vtn of the NMOSn2 and NMOSn5 and the effect of decreasing the on-resistance value due to the increase of the gate voltage are canceled, and the delay time is the threshold value. There is almost no difference from the case where the voltage Vtn is a standard value. As a result, even if the threshold voltage Vtn varies due to process variation, there is almost no difference in delay time between the modified inverter I2 and the modified inverter I4.
Further, when the ambient temperature is low, the effect of decreasing the on-resistance values of the NMOS n2 and NMOS n5 and the effect of increasing the on-resistance value due to the lower control signal NO are cancelled. When the ambient temperature is high, the effect of increasing the on-resistance values of the NMOS n2 and the NMOS n5 and the effect of decreasing the on-resistance value due to the increase in the control signal NO are cancelled. As a result, there is almost no difference in delay time between the modified inverter I2 and the modified inverter I4 depending on whether the ambient temperature is low or high.
Further, the modified inverter I1 and the modified inverter I3 also have the same effect as the modified inverters I2 and I4 by the correction circuit 2, so that there is almost no difference in delay time due to process variations and ambient temperature variations.
Therefore, in the conventional delay circuit shown in FIG. 2, the delay time due to the process variation and the ambient temperature variation is compensated, and a constant delay time is always obtained.
However, the conventional delay circuit as shown in FIG. 2 compensates for delay time fluctuations due to process fluctuations and ambient temperature fluctuations, but there is a problem that the delay time also fluctuates when the power supply voltage VDD fluctuates. It was.
It is an object of the present invention to provide a delay circuit that can compensate for variations in delay time due to process variations and power supply voltage variations.
The delay circuit of the present invention includes a modified inverter and a correction circuit.
The modified inverter includes first and second MOS transistors of first conductivity type connected in series between a first power supply terminal to which a first power supply voltage is applied and an output node, and the output node. A third MOS transistor of the second conductivity type connected between the second power supply terminal to which the second power supply voltage is applied, and the gate electrodes of the first and third MOS transistors are input A control signal for delay control is applied to the gate electrode of the second MOS transistor connected to the node. The correction circuit further includes a fourth MOS transistor and a first resistor of the first conductivity type connected in series between the first power supply terminal and an internal node that outputs the control signal, The fourth MOS transistor has a second resistor connected between an internal node and the second power supply terminal, and the fourth MOS transistor is diode-connected in the forward direction.
According to the delay circuit of the present invention, a voltage lower than the first power supply voltage by the threshold voltage is generated by the fourth MOS transistor diode-connected in the forward direction, and this is divided by the first and second resistors. A control signal is generated, and the gate of the delay second MOS transistor is controlled by this control signal. Thereby, for example, when the first power supply voltage rises, the voltage of the control signal also rises, and the gate-source voltage of the second MOS transistor is held substantially constant. Therefore, the ON resistance value of the second MOS transistor is held substantially constant, and the delay time is not changed.
The delay circuit includes a modified inverter and a correction circuit.
The modified inverter includes first and second PMOSs connected in series between a VDD terminal and an output node, and a third NMOS connected between the output node and a VSS terminal; The gates of the first PMOS and the third NMOS are connected to an input node, and a control signal for delay control is applied to the gate of the second PMOS. Further, the correction circuit is connected between the internal node and the VSS terminal, and a fourth PMOS and a first resistor connected in series between the VDD terminal and the internal node that outputs the control signal. The fourth PMOS is diode-connected in the forward direction.
(Configuration of Example 1)
FIG. 1 is a circuit diagram of a delay circuit showing a first embodiment of the present invention.
The delay circuit shown in FIG. 1 is used for a memory control circuit, for example, and is a circuit that generates a timing adjustment signal having a predetermined pulse width from a narrow pulse signal generated when an address signal is switched. is there. The delay circuit includes a five-stage inverter circuit that generates a desired delay time and outputs an output signal OUT when the input signal IN transitions from an "L" level to an "H" level, and the five-stage inverter circuit. And a correction circuit 60 for supplying a control signal VP for delay time correction.
The five-stage inverter circuit includes a first-stage inverter 10 that outputs a signal S10 that is delayed by inverting the input signal IN input from the input node, and a signal S10 that is input from the input node, and is delayed. A second-stage modified inverter 20P that outputs the processed signal S20 from the output node, a third-stage inverter 30 that outputs the delayed signal S30 from the output node by inverting the signal S20 input from the input node, and an input node A fourth-stage modified inverter 40P that outputs the signal S40 that is delayed by inverting the input signal S30 from the output node, and an output signal OUT that is delayed by inverting the signal S40 input from the input node is output from the output terminal 5 The inverter 50 of the stage is comprised.
The first-stage, third-stage, and fifth-stage inverters 10, 30, and 50 are normal CMOS type inverters. Among them, the first-stage inverter 10 includes a first conductivity type MOS transistor (for example, PMOS) 11 and a second conductivity type MOS transistor (for example, NMOS) 12. A first power supply terminal (for example, VDD terminal) to which one power supply voltage (for example, power supply voltage VDD) is applied and a second power supply terminal (for example, ground voltage VSS) to which a second power supply voltage (for example, ground voltage VSS) is applied. For example, the input signal IN is input to the gate-side input node of the PMOS 11 and the NMOS 12, and the signal S 10 is output from the drain-side output node of the PMOS 11 and the NMOS 12. .
Similarly, the inverter 30 at the third stage includes a PMOS 31 and an NMOS 32. These PMOS 31 and NMOS 32 are connected in series between the VDD terminal and the VSS terminal, and are connected to the input node on the gate side of the PMOS 31 and NMOS 32. The signal S20 is input, and the signal S30 is output from the output node on the drain side of the PMOS 31 and NMOS 32. The fifth-stage inverter 50 includes a PMOS 51 and an NMOS 52. The PMOS 51 and the NMOS 52 are connected in series between the VDD terminal and the VSS terminal. The output signal OUT is output from the drain side output terminals of the PMOS 51 and NMOS 52.
The second-stage and fourth-stage modified inverters 20P and 40P are inverters in which delay MOS transistors are combined with normal CMOS inverters. Among them, the second-stage modified inverter 20P has first and second conductivity type MOS transistors (for example, PMOS) 21 and 23 and second conductivity type MOS transistor (for example, NMOS) 22. The PMOSs 21 and 23 and the NMOS 22 are connected in series between a first power supply terminal (for example, VDD terminal) and a second power supply terminal (for example, VSS terminal), and the gate sides of the PMOS 21 and NMOS 22 are connected. The signal S10 is input to the input node of the PMOS 23, the signal S20 is output from the output node on the drain side of the PMOS 21 and the NMOS 22, and the control signal VP is supplied to the gate of the PMOS 23.
Similarly, the fourth-stage modified inverter 40P includes PMOSs 41 and 43 and an NMOS 42, and these PMOSs 41 and 43 and NMOS 42 are connected in series between the VDD terminal and the VSS terminal. A signal S30 is input to an input node on the gate side, a signal S40 is output from an output node on the drain side of the PMOS 41 and the NMOS 42, and a control signal VP is applied to the gate of the PMOS 43.
The correction circuit 60 includes a first conductive type fourth MOS transistor (for example, PMOS 61) diode-connected in the forward direction, a first resistor 62, an internal node N60 that outputs a control signal VP, And a resistor 63. The source of the PMOS 61 is connected to a first power supply terminal (for example, VDD terminal), the gate and drain of the PMOS 61 are connected to one end of the first resistor 62, and the other end of the first resistor 62 is connected to the internal node N60. And the other end of the second resistor 63 is connected to a second power supply terminal (for example, a VSS terminal).
(Operation of Example 1)
First, the general operation of the five-stage inverter circuit shown in FIG. 1 will be described.
When the input signal IN is at "L" level, the output signal S10 of the first-stage inverter 10 becomes "H" level and is given to the gates of the PMOS 21 and NMOS 22 which are input nodes of the second-stage modified inverter 20P. As a result, the PMOS 21 is turned off, the NMOS 22 is turned on, and the output signal S20 of the modified inverter 20P is set to the "L" level.
Here, when the input signal IN transitions from the "L" level to the "H" level, the output signal S10 of the inverter 10 becomes the "L" level, the PMOS 21 of the modified inverter 20P is turned on, and the NMOS 22 is turned off. As a result, the output node of the modified inverter 20P is connected to the VDD terminal via the PMOSs 21 and 23. However, since the output node of the modified inverter 20P is charged through the delay PMOS 23, the output signal S20 does not immediately go to "H" level, but goes to "H" level after a certain delay time.
Such a delay similarly occurs in the fourth-stage modified inverter 40P, and the output signal S40 of the modified inverter 40P is inverted and waveform-shaped by the fifth-stage inverter 50 and output as the output signal OUT. Therefore, when the input signal IN changes from the "H" level to the "L" level, the input signal IN immediately changes from the "L" level to the "H" level, and the input signal IN changes from the "L" level to the "H" level. In this case, an output signal OUT that transitions from the "H" level to the "L" level after a predetermined delay time is obtained.
Next, delay time variation compensation by the correction circuit 60 will be described.
When the threshold voltage of the PMOS 61 is Vtp and the resistance values of the resistors 62 and 63 are R62 and R63, respectively, the voltage of the control signal VP output from the correction circuit 60 is expressed by the following equation. Therefore, the voltage of the control signal VP varies substantially in proportion to the power supply voltage VDD.
VP = (VDD−Vtp) × R63 / (R62 + R63)
When the power supply voltage VDD rises, the gate voltages of the delay PMOSs 23 and 43 in the modified inverters 20P and 40P also rise. Therefore, the gate-source voltage Vgs of the PMOSs 23 and 43 is kept almost constant, and the drain current Ids can be made constant. When the power supply voltage VDD is lowered, the gate voltages of the PMOSs 23 and 43 are also lowered, the gate-source voltage Vgs is kept substantially constant, and the drain current Ids is kept constant. Thereby, the fluctuation of the delay time can be suppressed with respect to the fluctuation of the power supply voltage VDD.
When the PMOS threshold voltage Vtp decreases due to process variations, the voltage of the control signal VP output from the correction circuit 60 increases. Therefore, the ON resistance value can be reduced by reducing the threshold voltage Vtp of the PMOSs 23 and 43. The effect of increasing the on-resistance value due to the rise of the gate voltage is canceled, and the delay time of the modified inverters 20P and 40P is almost the same as the case where the threshold voltage Vtp is the standard value. Further, when the threshold voltage Vtp is large, the effect of increasing the on-resistance value due to the increase of the threshold voltage Vtp of the PMOSs 23 and 43 and the effect of decreasing the on-resistance value due to the decrease of the gate voltage are canceled, and the delay time is the threshold voltage. There is almost no difference from the case where Vtp is a standard value. As a result, even if the threshold voltage Vtp varies due to process variations, the difference in delay time hardly occurs.
(Effect of Example 1)
For example, in the conventional delay circuit shown in FIG. 2, the pulse width could not be guaranteed with respect to the fluctuation of the power supply voltage VDD. However, in the first embodiment, the pulse width can be guaranteed by solving this. The reason for this will be described below.
(I) The reason why the conventional delay circuit shown in FIG. 2 cannot guarantee the pulse width against the fluctuation of the power supply voltage VDD FIGS. 3A and 3B show the pulse width guarantee against the fluctuation of the power supply voltage VDD in the conventional delay circuit. 2A is a circuit diagram in the case of the PMOS type showing the main part of FIG. 2, and FIG. 2B is a case of the NMOS type showing the main part of FIG. It is a circuit diagram.
(I-1) In the case of the PMOS type When the on-resistance of the PMOS p7 shown in FIG.
Ip (Rp + r2) = VDD
VDD-Vp = Ip * Rp
When the control voltage Vp is solved, the following equation is obtained.
Vp = r2 * VDD / (r2 + Rp)
For example, by keeping constant the gate-source voltage Vgs of the PMOS p2 corresponding to the delay element, the delay width becomes constant.
VDD-Vp = constant (α)
Is a desirable voltage (VDD-Vp).
VDD-Vp = Rp * VDD / (r2 + Rp)
If the on-resistance Rp satisfies the following expression (1) with respect to the power supply voltage VDD, the voltage can be guaranteed.
Rp = α * r2 / (VDD−α) (1)
Where α = gate-source voltage Vgs of PMOS p2 corresponding to the delay element
= Constant value
In the circuit shown in FIG. 3A, the PMOS p7 that is on-resistance is in the non-saturation region, as shown below.
Vds <Vgs−Vt (Vp> Vt)
At this time, the following formula is established for the current Ip flowing through the PMOS p7.
Ip = β * [(Vgs−Vt) −0.5 * Vds] * Vds
The on-resistance Rp of the PMOS p2 can be expressed by the following equation.
Rp = (VDD−Vp) / Ip = 2 / (VDD−2Vt + Vp) * β
2 / β = α * r2,
α = 2Vt−Vp
Is satisfied, the expression (1) is satisfied. However, since the control voltage Vp depends on the power supply voltage VDD,
Is not true. Therefore, (1) does not hold, and it can be proved that the circuit shown in FIG.
(I-2) NMOS Type When the on-resistance of the NMOS n7 shown in FIG. 3B is Rn, the current flowing through the circuit is In, and the voltage of the control signal NO is Vn, the following equation is established.
In (Rn + r1) = VDD
VDD-Vn = In * r1
When the control voltage Vn is solved, the following equation is obtained.
Vn = Rn * VDD / (r1 + Rn)
For example, by keeping the gate-source voltage Vgs of the NMOS n2 corresponding to the delay element constant, the delay width becomes constant.
Vn = constant (α)
Is desirable. If the on-resistance Rn satisfies the following expression (2) with respect to the power supply voltage VDD, the voltage can be guaranteed.
Rn = α * r1 / (VDD−α) (2)
Where α = gate-source voltage Vgs of NMOS n2 corresponding to a delay element
= Constant value = Vn
In the circuit shown in FIG. 3B, the NMOS n7 that is on-resistance is in the non-saturation region, as shown in the following equation.
Vds <Vgs−Vt (Vn> Vt)
At this time, the following formula is established for the current In flowing through the NMOS n7.
In = β * [(Vgs−Vt) −0.5 * Vds] * Vds
On-resistance Rn is
Rn = Vn / In = 1 / (VDD−Vt−0.5 * Vn) / β
1 / β = α * r1
In the formula
α = Vt + 0.5Vn
Is satisfied, the expression (2) is satisfied. Since Vn = α in the above equation, the voltage can be guaranteed if the following equation (3) is established.
α = Vn = 2Vt
r1 = 1 / (2Vt * β) (3)
However, r1 is a resistance element, and can only have the same resistance value at a certain threshold voltage Vt. That is, it cannot be changed corresponding to the change in threshold voltage Vt due to temperature dependence. Therefore, when considering temperature dependence, equation (3) does not hold, and it can be proved that the voltage cannot be guaranteed.
As described above, in the conventional delay circuit, it can be proved that the voltage cannot be guaranteed with the PMOS type, and further, the voltage guarantee and the temperature guarantee cannot be achieved with the NMOS type. Such a conventional problem can be solved in the first embodiment and has the following effects.
(II) Effects of First Embodiment According to the delay circuit of the first embodiment, the voltage (VDD−Vtp) is generated by the diode-connected PMOS 61, and this voltage is divided by the resistors 62 and 63 to control the signal VP. And modified inverters 20P and 40P having delay PMOSs 23 and 43 whose gates are controlled by the control signal VP. Therefore, it is possible to suppress delay time fluctuations due to process fluctuations and fluctuations in the power supply voltage VDD, and to guarantee the pulse width.
(Modification of Example 1)
The first embodiment is not limited to the circuit configuration shown in FIG. 1, and other usage forms and modifications are possible. Examples of this modification include the following (i) to (iv).
(I) The number of stages of the inverter circuit shown in FIG. 1 is not limited to five. It is sufficient if at least one modified inverter is provided.
(Ii) The normal CMOS type inverter 10 is provided in the first stage. However, if the inverter 10 is deleted and the input signal IN is applied to the modified inverter 20P, the input signal IN is at the "H" level. When transitioning from "L" level to "L" level, a desired delay time can be created to output the output signal OUT.
(Iii) The delay PMOSs 23 and 43 may be provided not between the PMOSs 21 and 41 and the output node but between the PMOSs 21 and 41 and the VDD terminal.
(Iv) In the correction circuit 60, the connection order of the PMOS 61 and the resistor 62 may be reversed.
FIG. 4 is a circuit diagram of a delay circuit showing a second embodiment of the present invention. Elements common to those in FIG. 1 showing the first embodiment are denoted by common reference numerals.
The delay circuit shown in FIG. 4 is a circuit for generating a timing adjustment signal having a predetermined pulse width from a narrow pulse signal generated when the address signal is switched, for example, as in FIG. The delay circuit includes a five-stage inverter circuit that generates a desired delay time and outputs an output signal OUT when the input signal IN transitions from an "L" level to an "H" level, and the five-stage inverter circuit. And a correction circuit 70 for supplying a control signal VN for delay time correction.
The five-stage inverter circuit inverts the input signal IN input from the input node and inverts the signal S10 delayed from the output node, and inverts the signal S10 input from the input node. A second-stage inverter 20 that outputs the delayed signal S20 from the output node, a third-stage modified inverter 30N that inverts the signal S20 input from the input node and outputs a delayed signal S30 from the output node, and an input node The fourth stage inverter 40 that outputs the signal S40 that is delayed by inverting the signal S30 input from the output node, and the output signal OUT that is delayed by inverting the signal S40 input from the input node is output from the output terminal 5. The inverter 50 of the stage is comprised.
The first-stage and third-stage modified inverters 10P and 30P are inverters in which delay MOS transistors are combined with normal CMOS inverters. Among them, the first-stage modified inverter 10N includes a first conductivity type first MOS transistor (eg, PMOS) 11 and second conductivity type second and third MOS transistors (eg, NMOS) 12, 13. These PMOS 11 and NMOS 12 and 13 are connected in series between a first power supply terminal (for example, VDD terminal) and a second power supply terminal (for example, VSS terminal), and the PMOS 11 and NMOS 12 The input signal IN is input to the input node on the gate side, the signal S10 is output from the output node on the drain side of the PMOS11 and NMOS12, and the control signal VN is applied to the gate of the NMOS13.
Similarly, the third-stage modified inverter 30N includes a PMOS 31 and NMOSs 32 and 33. These PMOS 31 and NMOSs 32 and 33 are connected in series between the VDD terminal and the VSS terminal. A signal S20 is input to an input node on the gate side, a signal S30 is output from an output node on the drain side of the PMOS 31 and NMOS 32, and a control signal VN is applied to the gate of the NMOS 33.
The second-stage, fourth-stage, and fifth-stage inverters 20, 40, and 50 are normal CMOS type inverters. Among them, the second-stage inverter 20 includes a first conductivity type MOS transistor (for example, PMOS) 21 and a second conductivity type MOS transistor (for example, NMOS) 22, and these PMOS 21 and NMOS 22 are connected to the first conductivity type MOS transistor (for example, NMOS) 22. A first power supply terminal (for example, VDD terminal) to which one power supply voltage (for example, power supply voltage VDD) is applied and a second power supply terminal (for example, ground voltage VSS) to which a second power supply voltage (for example, ground voltage VSS) is applied. For example, the signal S10 is input to the gate-side input node of the PMOS 21 and the NMOS 22, and the signal S20 is output from the drain-side output node of the PMOS 21 and the NMOS 22.
Similarly, the fourth-stage inverter 40 includes a PMOS 41 and an NMOS 42, and these PMOS 41 and NMOS 42 are connected in series between the VDD terminal and the VSS terminal, and are connected to the input node on the gate side of the PMOS 41 and NMOS 42. The signal S30 is input, and the signal S40 is output from the output node on the drain side of the PMOS 41 and NMOS. The fifth-stage inverter 50 includes a PMOS 51 and an NMOS 52. The PMOS 51 and the NMOS 52 are connected in series between the VDD terminal and the VSS terminal. The output signal OUT is output from the drain side output terminals of the PMOS 51 and NMOS 52.
The correction circuit 70 includes a first resistor 73, an internal node N70 that outputs a control signal VN, a second resistor 72, and a second MOS transistor of the second conductivity type that is diode-connected in the forward direction (for example, NMOS 71). The first resistor 73 is connected between a first power supply terminal (for example, VDD terminal) and the internal node N70, and one end of the second resistor 72 is connected to the internal node N70. The other end of the second resistor 72 is connected to the drain and gate of the NMOS 71, and the source of the NMOS 71 is connected to a second power supply terminal (for example, VSS terminal).
First, the schematic operation of the five-stage inverter circuit shown in FIG. 4 will be described.
When the input signal IN is at the "L" level, the PMOS 11 of the first-stage modified inverter 10N is turned on, the NMOS 12 is turned off, and the output signal S10 of the modified inverter 10N is at the "H" level. Here, when the input signal IN transitions from the "L" level to the "H" level, the PMOS 11 is turned off and the NMOS 12 is turned on. As a result, the output node of the modified inverter 10N is connected to the VSS terminal via the NMOSs 12 and 13. However, since the output node of the modified inverter 10N is discharged through the NMOS 13 for delay, the output signal S10 does not immediately become "L" level but becomes "L" level after a certain delay time.
Such a delay similarly occurs in the third-stage modified inverter 30N, and the output signal S30 of the modified inverter 30N is waveform-shaped by the fourth-stage and fifth-stage inverters 40 and 50 and output as the output signal OUT. Is done. Therefore, when the input signal IN changes from the "H" level to the "L" level, the input signal IN immediately changes from the "L" level to the "H" level, and the input signal IN changes from the "L" level to the "H" level. In this case, an output signal OUT that transitions from the "H" level to the "L" level after a predetermined delay time is obtained.
Assuming that the threshold voltage of the NMOS 71 is Vtn and the resistance values of the resistors 72 and 73 are R72 and R73, respectively, the voltage of the control signal VN output from the correction circuit 70 is expressed by the following equation.
VN = (VDD × R72 + Vtn × R73) / (R72 + R73)
Therefore, the voltage of the control signal VN varies according to the power supply voltage VDD. However, by setting the resistance value R72 small and the resistance value R73 large, the dependence of the control signal VN on the power supply voltage VDD can be reduced and the threshold voltage Vtn dependence can be increased.
Thus, when the power supply voltage VDD rises, the gate voltages of the delay NMOSs 13 and 33 in the modified inverters 10N and 30N rise smaller than the rise width of the power supply voltage VDD, and the gate-source voltage Vgs is constant to some extent. The drain current Ids can be kept substantially constant. When the power supply voltage VDD is lowered, the gate voltages of the NMOSs 13 and 33 are also lowered, the gate-source voltage Vgs is kept constant to some extent, and the drain current Ids is kept almost constant. Thereby, the fluctuation of the delay time can be suppressed with respect to the fluctuation of the power supply voltage VDD.
Note that the influence of the process variation of the NMOS threshold voltage Vtn is also canceled by the opposite effect generated in the NMOS 71 and the delay NMOSs 13 and 33 in the correction circuit 70 as described in the first embodiment, and the delay time is increased. There is almost no difference.
According to the delay circuit of the second embodiment, the correction circuit 70 that generates the control signal VN according to the power supply voltage VDD and the threshold voltage Vtn by the diode-connected NMOS 71 and the voltage dividing resistors 72 and 73, and the control signal VN Since the modified inverters 10N and 30N having the delay NMOSs 13 and 33 whose gates are controlled are provided, the same effects as those of the first embodiment can be obtained.
The second embodiment is not limited to the circuit configuration shown in FIG. 4, and other usage forms and modifications are possible. Examples of such modifications include the following (i) to (iii).
(Ii) The delay NMOSs 13 and 33 may be provided between the output node and the NMOSs 12 and 32 instead of between the NMOSs 12 and 32 and the VSS terminal.
(Iii) In the correction circuit 70, the connection order of the resistor 72 and the NMOS 71 may be reversed.
FIG. 5 is a circuit diagram of a delay circuit showing a third embodiment of the present invention. Elements common to those in FIG. 1 showing the first embodiment and FIG. 4 showing the second embodiment are denoted by common reference numerals. ing.
The delay circuit shown in FIG. 5 is a combination of FIG. 1 and FIG. 4, and the first, second, third, and fourth modified inverters 10N, 20P, 30N, and 40P and the normal CMOS type A five-stage inverter circuit composed of the fifth-stage inverter 50, a correction circuit 60 for supplying the control signal VP to the modified inverters 20P and 40P, and a correction circuit 70 for supplying the control signal VN to the modified inverters 10N and 30N It is comprised by.
The operation of the delay circuit of the third embodiment is a combination of the operations of the delay circuits of FIGS. 1 and 4 described in the first and second embodiments, and has substantially the same operational effects. In addition, in the delay circuit according to the third embodiment, since four delay PMOSs 23 and 43 and four NMOSs 13 and 33 are provided, a long delay time can be set.
6 (a) and 6 (b) are circuit diagrams of a correction circuit showing a fourth embodiment of the present invention. FIG. 6 (a) is a correction circuit 60A provided in place of the correction circuit 60 in FIG. 1 or FIG. 4B shows a correction circuit 70A provided in place of the correction circuit 70 in FIG. 3 or FIG. 6 (a) and 6 (b), the same reference numerals are given to the same elements as those in FIG. 1 showing the first embodiment and FIG. 4 showing the second embodiment.
The correction circuit 60A shown in FIG. 6A outputs a first conductivity type fourth MOS transistor (for example, PMOS) 61, a first resistor 62, and a control signal VP that are diode-connected in the forward direction. It has an internal node N60A, second and third resistors 63a and 63b, and a first conductivity type fifth MOS transistor (for example, PMOS) 64. The PMOS 61 has a source connected to a first power supply terminal (for example, a VDD terminal), and a gate and a drain connected to one end of the first resistor 62. The other end of the first resistor 62 is connected to the internal node N60A. The internal node N60A is connected to a second power supply terminal (for example, a VSS terminal) via the second resistor 63a and the third resistor 63b. The source and drain of the PMOS 64 are connected in parallel to the second resistor 63a and the third resistor 63b, and the gate of the PMOS 64 is connected to the connection point of the resistors 63a and 63b.
The correction circuit 70A shown in FIG. 6B includes first and second resistors 73b and 73a, a second conductivity type fourth MOS transistor (for example, NMOS) 74, and an internal node that outputs a control signal VN. N70A, the 3rd resistance 72, and the 5th MOS transistor (for example, NMOS) 71 of the 2nd conductivity type diode-connected in the forward direction. The first and second resistors 73b and 73a are connected in series between the first power supply terminal (for example, VDD terminal) and the internal node N70A. The drain and source of the NMOS 74 are connected in parallel to the first and second resistors 73b and 73a, and the gate of the NMOS 74 is connected to the connection point of the resistors 73b and 73a. One end of a third resistor 72 is connected to the internal node N70A, the other end of the third resistor 72 is connected to the drain and gate of the NMOS 71, and the source of the NMOS 71 is connected to a second power supply terminal (for example, VSS terminal).
First, the operation of the correction circuit 60A shown in FIG.
6A, the resistance values of the resistors 62, 63a, and 63b are R62, R63a, and R63b, respectively, the current flowing through the resistor 62 is I62, the current flowing through the resistors 63a and 63b is I63, and the current flowing through the PMOS 64 is I64, When the voltage at the connection point of the resistors 63a and 63b is V63, the following equation is established.
VDD-Vtp-VP = R62 × I62
I62 = I63 + I64
VP = (R63a + R63b) × I63
V63 = R63b × I63
VP-V63 = R63a × I63
When these equations are used as simultaneous equations and the voltage of the control signal VP is solved, the following equation is obtained.
VP = (R63a + R63b) / (R62 + R63a + R63b)
× (VDD−Vtp−R62 × I64)
Therefore, when the power supply voltage VDD rises, the voltage of the control signal VP also rises, the delay PMOS gate-source voltage Vgs is kept substantially constant, and the drain current Ids can be made constant. When the power supply voltage VDD decreases, the gate voltage of the delay PMOS also decreases, and the drain current Ids is kept constant. Thereby, the fluctuation of the delay time can be suppressed with respect to the fluctuation of the power supply voltage VDD. Further, since the voltage of the control signal VP moves in a canceling direction with respect to the fluctuation of the threshold voltage Vtp, the influence of the process fluctuation can be suppressed.
Further, in the PMOS 64 of the correction circuit 60A,
Vds (= VP)> Vgs (= VP−V63) −Vtp
Vds: drain-source voltage of PMOS 64
Vgs: A voltage between the gate and the source of the PMOS 64. Since the PMOS 64 operates in a saturation characteristic region, the following equation is established.
I64 = β / 2 × (VP−V63−Vtp) 2
= Β / 2 × (I63 × R63a−Vtp) 2
= Β / 2 × {VP × R63a / (R63a + R63b) −Vtp} 2
However, β = W / L × μCox
W; PMOS 64 gate width
L: Gate length of PMOS 64
When this equation is solved with respect to the voltage of the control signal VP, the following equation is obtained.
VP = (R63a + R63b) / R63a × (√ (2 × I64 / β) + Vtp)
Therefore, in order to increase the influence of the threshold voltage Vtp and reduce the influence of the current I64, the value of β may be set large. Since β is proportional to the gate width W, there is a method of setting the gate width W large. When the threshold voltage Vtp decreases as the temperature rises, the voltage of the control signal VP also decreases, and the gate voltage of the delay PMOS also decreases. As a result, the drain current Ids of the delay PMOS is kept constant. Further, when the threshold voltage Vtp rises due to the temperature drop, the voltage of the control signal VP also rises, the gate voltage of the delay PMOS also rises, and the drain current Ids is kept constant.
Next, the operation of the correction circuit 70A shown in FIG.
In FIG. 6B, the resistance values of the resistors 72, 73a, 73b are R72, R73a, R73b, respectively, the current flowing through the resistor 72 is I72, the current flowing through the resistors 73a, 73b is I73, and the current flowing through the NMOS 74 is I74, When the voltage at the connection point of the resistors 73a and 73b is V73, the following equation is established.
VN−Vtn = R72 × I72
VDD-VN = (R73a + R73b) × I73
VDD-V73 = R73b × I73
V73−VN = R73a × I73
When these equations are used as simultaneous equations and the voltage of the control signal VN is solved, the following equation is obtained.
VN = R72 / (R72 + R73a + R73b) × VDD
+ (R73a + R73b) / (R72 + R73a + R73b) × Vtn
+ R72 × (R73a + R73b) / (R72 + R73a + R73b) × I74
Therefore, by setting the resistance R72 to be small and the resistance (R73a + R73b) to be large, the influence of fluctuations in the power supply voltage VDD can be reduced. Further, since the voltage of the control signal VN moves in a canceling direction with respect to the fluctuation of the threshold voltage Vtn, the influence of the process fluctuation can be suppressed.
In the NMOS 74 of the correction circuit 70A,
Vds (= VDD−VN)> Vgs (= V73−VN) −Vtn
Since this NMOS 74 operates in the saturation characteristic region, the following equation is established.
I74 = β / 2 × (V73−VN−Vtn) 2
= Β / 2 × (I73 × R73a−Vtn) 2
= Β / 2 × {(VDD−VN) × R73a / (R73a + R73b) −Vtn} 2
When this equation is solved for the voltage of the control signal VN, the following equation is obtained.
VN = VDD− (R73a + R73b) / R73a
× (√ (2 × I74 / β) + Vtn)
Therefore, in order to increase the influence of the threshold voltage Vtn and reduce the influence of the current I74, the value of β may be set large. When the threshold voltage Vtn decreases as the temperature increases, the voltage of the control signal VN increases, the delay NMOS gate voltage also increases, and the drain current Ids is kept constant. Further, when the threshold voltage Vtn increases due to a decrease in temperature, the voltage of the control signal VN decreases, the gate voltage of the delay NMOS also decreases, and the drain current Ids is kept constant.
7A to 7D are waveform diagrams showing simulation results of Example 4 of the present invention. This simulation waveform is obtained by using the correction circuits 60A and 70A of FIG. 6 as the correction circuit in the delay circuit of FIG. 7A shows the waveform of the input signal IN, FIG. 7B shows the waveform of the output signal OUT when the ambient temperature is −10 ° C., and the power supply voltage VDD is 3.6V, 3.3V, 3 This shows four cases of 0.0V and 2.7V. In FIG. 7B, for comparison, a simulation result when the correction circuits 1 and 2 in the conventional delay circuit shown in FIG. 2 are used as the correction circuit of the delay circuit in FIG. Is shown. FIGS. 7C and 7D show similar simulation results when the ambient temperature is 25 ° C. and 80 ° C., respectively.
As is clear from the simulation results, in the delay circuit using the conventional correction circuits 1 and 2 shown in FIG. 2, the compensation for the temperature change is relatively good, but the delay time is changed when the power supply voltage VDD fluctuates. It can be seen that there is a significant change and no compensation is made for fluctuations in the power supply voltage VDD. On the other hand, in the delay circuit using the correction circuits 60A and 70A of the fourth embodiment, it is apparent that the delay time hardly changes regardless of the ambient temperature and the power supply voltage.
The fourth embodiment is not limited to the circuit configuration shown in FIG. 6, and other usage forms and modifications are possible. Examples of this modification include the following (i) and (ii).
(I) The connection order of the PMOS 61 and the resistor 62 in the correction circuit 60A may be reversed. That is, the resistor 62 may be provided on the VDD terminal side. Similarly, the connection order of the NMOS 71 and the resistor 72 in the correction circuit 70A may be reversed. Even with this configuration, substantially the same effects as those of the fourth embodiment can be obtained.
(Ii) The PMOS 61 in the correction circuit 60A and the NMOS 71 in the correction circuit 70A may be deleted. In such a configuration, the effect on the fluctuation of the power supply voltage VDD is reduced, but the effect on the fluctuation of the ambient temperature and the process fluctuation can be sufficiently obtained.
It is a circuit diagram of a delay circuit showing Example 1 of the present invention. It is a circuit diagram of a conventional delay circuit. It is a figure which shows the reason the pulse width cannot be guaranteed with respect to the fluctuation | variation of a power supply voltage in the conventional delay circuit. It is a circuit diagram of the delay circuit showing Example 2 of the present invention. It is a circuit diagram of the delay circuit showing Example 3 of the present invention. It is a circuit diagram of the correction circuit showing Example 4 of the present invention. It is a wave form diagram which shows the simulation result of Example 4 of this invention.
Explanation of symbols
10, 20, 30, 40, 50 Inverter 10N, 20P, 30N, 40P Modified inverter 60, 60A, 70, 70A Correction circuit 61, 64 PMOS
62, 63, 63a, 63b, 72, 73, 73a, 73b Resistance 71, 74 NMOS
First and second MOS transistors of the first conductivity type connected in series between a first power supply terminal to which a first power supply voltage is applied and an output node, the output node and a second power supply voltage A third MOS transistor of the second conductivity type connected between the second power supply terminal to which is applied, and the gate electrodes of the first and third MOS transistors are connected to the input node, A modified inverter in which a control signal for delay control is applied to the gate electrode of the second MOS transistor;
A first MOS transistor of the first conductivity type and a first resistor connected in series between the first power supply terminal and an internal node that outputs the control signal; the internal node; A correction circuit having a second resistor connected between the power supply terminal and the fourth MOS transistor diode-connected in the forward direction;
A delay circuit comprising:
A first MOS transistor of a first conductivity type connected between a first power supply terminal to which a first power supply voltage is applied and an output node, and a first MOS transistor to which the output node and a second power supply voltage are applied. A second conductive type second and third MOS transistors connected in series between two power supply terminals, the gate electrodes of the first and second MOS transistors being connected to an input node, A modified inverter in which a control signal for delay control is applied to the gate electrode of the third MOS transistor;
A first resistor connected between the first power supply terminal and an internal node for outputting the control signal; and a second resistor connected in series between the internal node and the second power supply terminal. A correction circuit having a resistor and a fourth MOS transistor of the second conductivity type, the fourth MOS transistor being diode-connected in the forward direction;
A first resistor connected between the first power supply terminal and an internal node that outputs the control signal; a second resistor connected in series between the internal node and the second power supply terminal; A fourth MOS of the first conductivity type connected in parallel to a third resistor and the second and third resistors, and having a gate electrode connected to a connection point of the second and third resistors A correction circuit having a transistor;
A first MOS transistor of the first conductivity type and a first resistor connected in series between the first power supply terminal and an internal node that outputs the control signal; the internal node; A second and a third resistor connected in series with the power supply terminal; and a fifth MOS transistor of the first conductivity type connected in parallel with the second and third resistors. The fourth MOS transistor is diode-connected in the forward direction, and the fifth MOS transistor is a correction circuit having a gate electrode connected to a connection point of the second and third resistors;
A first and second resistor connected in series between the first power supply terminal and an internal node that outputs the control signal, a parallel connection to the first and second resistors, and a gate electrode A fourth MOS transistor of the second conductivity type connected to a connection point of the first and second resistors, and a third resistor connected between the internal node and the second power supply terminal. A correction circuit having
The first and second resistors connected in series between the first power supply terminal and the internal node that outputs the control signal, and the second connected in parallel to the first and second resistors. A fourth MOS transistor of conductivity type, a third resistor connected in series between the internal node and the second power supply terminal, and a fifth MOS transistor of the second conductivity type; A correction circuit in which a gate electrode of the fourth MOS transistor is connected to a connection point of the first and second resistors, and the fifth MOS transistor is diode-connected in a forward direction;
The delay circuit according to claim 1, wherein the first conductivity type is a P-channel type, and the second conductivity type is an N-channel type.
The delay according to any one of claims 1 to 7, wherein the first power supply voltage is higher than the second power supply voltage, and the second power supply voltage is a ground voltage. circuit.
JP2006147587A 2005-06-30 2006-05-29 Delay circuit Pending JP2007043661A (en)
JP2005190964 2005-06-30
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US11/476,900 US7528641B2 (en) 2005-06-30 2006-06-29 Delay circuit having a correction circuit
JP2007043661A true JP2007043661A (en) 2007-02-15
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2011-10-12 A02 Decision of refusal


text:
New car trivia: Next-gen Volkswagen Polo
Published By: Droom
Here are the key talking points about Volkswagen's latest.
After an eight-year production run, the carmaker is set to replace the current Polo with an all-new one. The all-new Polo features a more grown-up appearance and is larger than the outgoing car. The new VW is built on an all-new platform as well. Here are the key talking points.
1. Larger than its predecessor
The new Polo is measures 4,053mm in length, is 1,751mm wide, and its height is 1,446mm, while the car's wheelbase is 2,564mm - the car is larger and wider than its predecessor. The new car will provide a more spacious cabin than the outgoing model, however, when it comes to India, this increase in length will mean it cannot reap the benefits of being a sub-four metre model.
2. Underpinned by VW's MQB platform
The previous Polo was built on VW's PQ25 platform, and the next-gen model is built on the company's modular MQB platform. This will mean that the car could be lighter than its predecessor.
3. Look like a mini Golf
The car shares a lot of components with its larger sibling, the Golf. Inside, the dashboard, seats and control surfaces could be shared with the larger Golf as well.
4. Choice of petrol and diesel engines
There will be a range of new and updated petrol and diesel engines on offer. The petrol line-up includes a 1.0-litre TSI unit in four different states of tune, along with a new 1.4-litre TSI unit in two states of tune. The diesel line-up is available as a 1.6-litre unit with two different power outputs.
5. No news on India launch
VW's alliance with Tata Motors over the use of Tata's AMP platform to develop indigenous cars for the market could be the reason why. While the company does want to replace the current Polo that's sold here, we're not sure if it will bring a reengineered version of the new Polo or launch an indigenously developed alternative here.


text:
http://www.digitaljournal.com/tech-and-science/technology/another-first-spacex-launches-spy-satellite-lands-booster/article/491578
Another first — SpaceX launches spy satellite, lands booster
Posted May 1, 2017	by Karen Graham
SpaceX added another first to its growing list of accomplishments, breaking up the U.S. spy satellite launch monopoly with its own launch of a spy satellite for a government agency this morning, and it successfully landed the Falcon 9 booster.
Falcon 9 launch at Cape Canaveral, Florida.
The private launch company sent up a spy satellite for the National Reconnaissance Office (NRO), designated NROL-76, at 7:15 a.m. ET Monday from Cape Canaveral Launch Complex 39, About nine minutes later, the Falcon 9 booster successfully touched down on a landing pad on Florida's Space Coast.
The launch was another historic first for SpaceX, marking the first time it has executed a government contract, reports the Orlando Sentinel, breaking a monopoly held for the past 10-years by United Launch Alliance (ULA).
In addition to the classified NRO launch today, SpaceX has won two Air Force contracts to launch global positioning system satellites in 2018 and 2019. The $82.7 million contract was awarded by the Pentagon on April 27, with SpaceX being the only bidder because ULA sat out the bidding process, saying they couldn't compete with SpaceX.
Launch had a 24-hour delay
The launch had originally been scheduled 7:00 a.m. ET on Sunday, but one of the hundreds of sensors on the rocket was acting up, prompting a halt to the launch, according to USA Today.
"While this particular sensor did have a redundancy, readings were out of tolerance so out of an abundance of caution, we opted to hold launch, said John Federspiel, a lead mechanical design engineer at SpaceX who served as a broadcaster for the launch.
And while there is now a healthy competition between ULA and SpaceX, launching a package for the government doesn't come cheap for the launch company. Because the launch took place on a civilian government range, the FAA was involved. This means SpaceX had to get an FAA Launch License.
Under the terms of the launch license, SpaceX had to purchase $160 million worth of insurance to cover any claims resulting from the flight of the Falcon 9 from Kennedy Space Center and $12 million to cover potential damages during preflight activities.
SpaceX was also required to buy $100 million worth of insurance to cover any damages to government property in the event of a launch accident and one more $63 million insurance policy that covered government property claims resulting from the prelaunch activities.


text:
About DNSSEC-resolver-check
===========================

This project consists of DNSSEC-resolver-check, implemented in java, and
pyDRC, a subset of DNSSEC-resolver-check, implemented in python.

java
----
DNSSEC-resolver-check (the java code) is a set of java classes that implement
an application that evaluates how well a resolver supports DNSSEC as seen from
the location at which the applicaiton runs.

The evaluation is submitted to a central server operated by us.

This collection depends on dnsjava
please put a recent dnsjava jar file (>2.1.3) in the current directory
and update the Makefile to reflect it.

Usage of command line tool: UI_DRC
----------------------------------

         java UI_DRC <options> <resolver candidates>
    or   java -jar UI_DRC-0.5.5.jar <options> <resolver candidates>
         options:
          -a # Aborts on first error for each resolver
          -d # prints lots of debug info
          -h # prints help and exits
          -l # Lists the locally configured resolvers and exits
          -r # detailed report on screen
          -S # DO not SUBMIT results
          -T # Show compact from of test results
          -m <string> # A string that gets added to the report as an identifier
   	Example: starbucks
             #  No resolvers listed, use configured resolvers
      resolvers can be addresses or names

New report format:

    Tests=<str>.NS=<ip1/name>.Resolv=<ip2>.Me=<ip3>.Version=<str>.Msg=<str>.submit.dnssecready.net

    Tests= <str>      reports the result of the 13 tests
    NS=<ip1/name> 	   is the name or address being tested
    Resolv=<ip2> 	   is the IP address the resolver reports for itself
    Me=<ip3>  	   is the public IP address my servers see
    Version=<string>  The version of the test program
    Msg=<string>	   An indicator where the test was performed (optional)

The DRC Applet and Server
=========================

The Applet and javascript can be served by a php server, if the following files are
present:

   - dnsjava-2.1.4.jar             (dns stub forwarder, MUST BE SIGNED)
   - DNSSEC_Check_Help.php         (content of the hover text help for behaviors)
   - DNSSEC_Check_Test_Help.html   (content of the help for the tests)
   - DSC-3.php                     (the main php file that outputs the GUI)
   - lc.min.js                     (a jquery control used by the GUI)
   - UI_DRC-0.5.5.jar              (the main DRC class jar, MUST BE SIGNED)
   - DNSSEC_Check-1.0.2.jar        (the applet jar, MUST BE SIGNED)

If all these files are present in a php server folder, and you point a browser at DRC-3.php,
you should get the DRC web page.

python
------
The python code is a set of python classes that implements the DNSSEC-resolver-check
functionality as a library, along with a simple, console user interface. See UI_DRC.py
for usage.

redpajama_set_name: RedPajamaGithub


One thing I had to figure out was how to change an AD user's account expiration date via a web page written in VB.NET. Sounds easy, right? So I logged into the DC, installed the support tools, and opened ADSI Edit. I found a user and went to it's properties. I was looking for accountExpirationDate. I found it, but the value was weird. The type was a Large Integer and the value looked to be a bunch of random numbers. After a bit of researching I found that it's a 64 bit integer. But it's not a regular 64 bit integer, it's a special AD 64 bit integer object. What's the difference? Well, you can't directly set the value of this special object like you would if it was a regular integer. Previously, I had to figure out how to decode this number to get a real date. That was difficult. Turns out, there are two properties of this object, HighPart and LowPart. So I researched what I needed to do with these and figured out how to convert those 2 "parts" (each a 32 bit integer) into one date. So great, I can decode it. How about encoding?
I looked for days and found nothing that worked. Finally I found the solution. I don't have to do any math at all. There is a method of a DirectoryEntry that I can call (assuming _strUser contains the username and _strExpDate contains the new expiration date in string format).
Viola! So you're probably wondering just what that 64 bit integer actually means. Well, it's the number of 100 nanosecond intervals from January 1, 1601 (http://msdn2.microsoft.com/en-gb/library/ms675098.aspx). Thank you Microsoft!


text:
Recollections of a Victorian Police Officer Chapter XIII page 1
1 Recollections of a Victorian Police Officer by Sup John Sadleir
2 CHAPTER XIII - MELBOURNE IN 1864
2.1 See previous page / next page
3 the previous chapter / next chapter . . . Recollections of a Victorian Police index
Recollections of a Victorian Police Officer by Sup John Sadleir
CHAPTER XIII - MELBOURNE IN 1864
Leopold Kabat, Inspector of Police, was my senior by a few days. We were not much thrown together at any time, but yet there were many coincidences in our careers. On several different occasions it was our lot to change places, until it became a sort of superstition with me, that when Kabat was about to be removed it was time that I, too, should prepare for a change. So it happened, in May, 1864, that, seeing mention in the press of his trouble through some ill-advised mining speculations, I took it as a warning that I too should prepare for a move. I was not surprised therefore when a few mails later I received orders to proceed to Melbourne . A journey by coach to Ballarat, occupying some eighteen consecutive hours in mid-winter, our family now consisted of four young children - was not a pleasant prospect; but our fellow-travellers were kind, especially Mr. Tom (perhaps better known as 'Pop') Seymour, who might be seen with a child on each arm to save them from the tossing about of the coach, as it bumped over the unformed roads.
When I reached Melbourne I found there had been many changes since I had left it nearly eight years before. Captain Macmahon was no longer Chief Commissioner. His place had been taken by Captain F C Standish; while Superintendent S E Freeman was succeeded by T H Lyttelton as officer in charge of the Metropolitan Police District; and Frank Hare, whom I first met at Beechworth in 1856, was Inspector in charge at Russell Street - the most important division in the district. Freeman had died some eighteen months before my return to Melbourne , and I soon discovered that the good work he had commenced and carried on was forgotten, and his ideals of duty altogether lost sight of.
UNREST AND INSUBORDINATION
It is necessary to go back a few years, even at the risk of some repetition, if this modest history of the Police Force of Victoria is to be in any sense complete.
In 1858 Captain (after Sir Charles) Macmahon was succeeded by Captain F. C. Standish as already noted; and about the same time, or shortly after, Superintendent Freeman began to show signs of failing powers, so much so that early in 1859 he was allowed six months leave of absence. For various reasons his illness was a grave misfortune, and led indirectly to some very serious results. The police service may be said to have been still in the making, and the withdrawal from actual duty at this critical time of the most competent officer the service had ever seen, seemed to put an end to further progress. The new Chief Commissioner lost a loyal and capable adviser, and was left in his inexperience to the influence of officers who were disloyal or incompetent, or worse. Freeman's mantle had not fallen on any of those junior officers who had served under him. Inspector Page, who had accompanied him from London , was certainly a good useful officer, but he had not the qualities to fit him for a leading position. As for the others, they were not of the material of which anything very useful could be made.
During the absence on leave of Freeman, P H Smith, Inspecting Superintendent, was placed in charge of the city police and son after troubles began, that within a year or two ended in open insubordination, in which the inspecting superintendent himself was involved; but, as so often happens, punishment fell on the lesser fry, in the persons of some sergeants who were ignominiously dismissed from the service.
Matters were not allowed to settle down without the usual parliamentary squabble. Mr Fraser, the member for Creswick, exercising the privilege of Parliament, made use of some very fierce and uncomplimentary language, to which some one retorted in the press by calling Mr Fraser a 'privileged ruffian.' Backed by parliamentary influence, the malcontents in the service raked over every dustheap to find accusations against the head of the police force; and then followed successive parliamentary inquiries, as futile as these inquiries usually are. The whole proceedings furnish very painful study, and are redeemed only by the splendid ability with which Captain Standish, the Chief Commissioner, met the badgering of politicians, angry at finding themselves beguiled into a false position.
It is not contended here that these were the only troubles of the period, for there were other grave scandals. Two officers at the police depot were punished for irregularities in their public accounts, and some grave misconduct in connection with the management of the police hospital was brought to light. These matters had, however, all been dealt with by departmental inquiry before the parliamentary committee sat.
While the investigation of all these scandals failed altogether to show any personal connivance on the part of the Chief Commissioner, it cannot be said that he was wholly free from blame, for these troubles might have been avoided had he made a more careful choice of officers for positions of special importance.
the previous chapter / next chapter . . . Recollections of a Victorian Police index
KellyGang
Retrieved from "https://kellygang.asn.au/index.php?title=Recollections_of_a_Victorian_Police_Officer_Chapter_XIII_page_1&oldid=11105"
Sup Sadlier
Recollections of a Victorian Police Office
John Sadlier


View your reports on the go!
Spending by Envelope Report. This colorful report shows what you spent on each category for this month, last week, last month…or whatever time range will help you understand your spending. Tap on your Food, Fun, or Vacation Envelope to highlight it.
A fresh, new look for the app you love.
Goodbudget for Android gets a Material design facelift! Check out the vibrant new color scheme, and the new Add Transaction button. Now, adding expenses is just a thumb's reach away — and staying on budget just got easier!
Go to the Google Play Store to update!
Great job guys! My wife and I enjoy using your software every day and appreciate that you keep things fresh and up to date!
Hi Ben – Thanks for the encouragement, and I'm glad to hear you're enjoying the new look and reports!


Thank you for your contacting us. Your service request ID is #46757. This is an automated response. Notification and follow-up by the appropriate department will be made Monday thru Friday between 8AM and 4:30PM. If this is an emergency, please call 911.
This is private and is referred to code enforcement.
This issue was recategorized from Debris in Street or Sidewalk to Request for Service.
Please add that the resident needs to trim all the greens off the walkway.


text:
Murray Campaign Releases New Ad on Threats to Democracy from Extreme MAGA Republicans Like Tiffany Smiley: "Our Democracy Is In Real Danger"
Press Release | August 17, 2022
Smiley has "serious questions" about the 2020 election; thinks it would be "awesome" to have Trump's endorsement
Murray was one of the first to call for former President Trump's removal under the 25th Amendment following Jan 6 insurrection
ICYMI: Murray recounts harrowing experience hiding from violent rioters during Jan 6 attack on U.S. Capitol
**Watch Rewrite History HERE**
(Seattle, WA) — Today, U.S. Senator Patty Murray (D-WA) launched a new TV ad titled Rewrite History, which focuses on the January 6th attack on the U.S. Capitol — which Murray witnessed firsthand — and the continued threats MAGA Republicans pose to our democracy:
"I will not let anyone rewrite history," Murray says in the ad. "On January 6th, I will never forget the pounding at the door. We barricaded ourselves in a small office in the Capitol. The MAGA mob did everything they could to stop the peaceful transfer of power.
"MAGA Republicans want to seize power in this year's election. Our democracy is in real danger. It's up to all of us to save it. I'm Patty Murray and I approve this message because democracy is on the ballot."
According to a recent analysis by FiveThirtyEight, 49 percent of Republican nominees advancing to the 2022 general election fully deny the results of the 2020 election. As Trump's "Big Lie" about the 2020 election takes hold — a whopping 70 percent of Republicans do not believe Joe Biden was the legitimate winner of the 2020 election — a recent NPR/Ipsos poll found that 64 percent of Americans believe U.S. democracy "is in crisis and at risk of failing."
According to her campaign website, MAGA Republican Tiffany Smiley has "serious questions about the integrity of our elections," and believes "that courts have an obligation to give all evidence of voter fraud a full and fair hearing." Allegations of voter fraud have been repeatedly and systematically debunked, and voter fraud is proven to be exceptionally rare.
Senator Murray voted to impeach former President Trump for his role in inciting violence and attempting to prevent the certification of the 2020 election; she was also one of the first to call for former President Trump's removal under the 25th Amendment after the January 6th insurrection. Murray previously recounted her escape from the violent mob in the U.S. Capitol on January 6th in a lengthy interview with PBS NewsHour.


In O2 we minimized the number of available partitions (or queues) to simplify the job submission process.
You can use the flow chart below to find out which partition is best for the type of jobs you plan to run.
Note 1: all partitions can currently be used to request interactive sessions; the interactive partition has a dedicated set of nodes and higher priority.
See File Transfer for more information.