2011-09-06 Assigned to SHARP KABUSHIKI KAISHA reassignment SHARP KABUSHIKI KAISHA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ADVANCED LCD TECHNOLOGIES DEVELOPMENT CENTER CO., LTD.
A thin-film transistor circuit includes a crystallized semiconductor thin film two-dimensionally partitioned into crystal-grain-defining areas each of which accommodates a crystal grain larger than a predetermined size, thin-film transistors each of which has a channel region placed at the center position of a corresponding one of the crystal-grain-defining areas, and wirings which interconnect the thin-film transistors.
This application is based upon and claims the benefit of priority from prior Japanese Patent Applications No. 2004-172647, filed Jun. 10, 2004; and No. 2005-138732, filed May 11, 2005, the entire contents of both of which are incorporated herein by reference.
The present invention relates to a thin-film transistor circuit that uses a crystallized semiconductor thin film having crystal grains of relatively large size, a design method for the thin-film transistor circuit, a design program for the thin-film transistor circuit, a design program recording medium, a design library database, and a display device.
Flat-panel display devices have found use in various fields because of their features of thinness, lightness, and low power dissipation. Above all, active-matrix flat-panel display devices have been widely used in OA equipment in which high resolution and high picture quality are required. This type of display device includes a number of thin-film transistors (TFTs) each of which is placed adjacent to a respective one of pixels arranged in the form of a matrix and connected to it as a pixel switching element. With the recent development of multimedia communication technology, a function-intensive flat-panel display device has attracted attention as a display device for next generation personal uses. This flat-panel display device has a structure, called a system on panel, in which diversified peripheral circuits including a driver circuit, a memory circuit, a DA conversion circuit, and a image processing circuit, which are associated with image display, are integrated together with the pixel array.
In order to realize the function-intensive display device, it is required to constitute peripheral circuit components, such as logic circuits, memory elements, analog amplifiers, etc., by thin-film transistors using a semiconductor thin film of high carrier mobility formed on an insulating substrate made of glass or the like. Heretofore, various techniques have been proposed to form such a thin film at low temperatures.
With a recrystallization method using laser light, it is possible to obtain a silicon film having crystal grains of, say, a rectangular shape as a crystallized semiconductor thin film (see, for example, Japanese Unexamined Patent Publications Nos. 2002-237455 and 2003-22969).
Transistors are individually placed in crystal grains of a crystallized semiconductor thin film obtained by the recrystallization method using laser light (see, for example, Japanese Unexamined Patent Publications Nos. 2003-86604, 2003-31497, 2003-124230, 2003-318127, 2003-197521, 2003-197527).
The above-mentioned Patent Publications disclose techniques to obtain crystal grains sufficiently large in size to accommodate the channel regions of thin-film transistors, but do not disclose techniques to properly and efficiently design a thin-film transistor circuit, such as a peripheral circuit, on a crystallized semiconductor thin film having such crystal grains.
In the manufacture of a thin-film transistor circuit, it is required to prepare various photomasks for patterning a crystallized semiconductor thin film and wiring layers. The aforementioned conventional techniques will not be sufficient to prepare practical photomasks.
In preparing photomasks, it is required to determine the arrangements of thin-film transistors and wirings necessary for a thin-film transistor circuit and reflect these arrangements in various photomasks. With a large-scale thin-film transistor circuit, however, laying out all the thin-film transistors and wirings artificially would inevitably increase the design period and the frequency of occurrence of erroneous wirings, resulting in an accelerative increase in design cost.
Conventionally, there exists a design tool which is a computer that simulates a thin-film transistor circuit. The use of this design tool allows the layout of thin-film transistors and wirings to be automated. This layout result allows for the channel regions of thin-film transistors to be placed in portions of poor crystallinity of a crystallized semiconductor thin film. It is therefore difficult to apply the automated layout to photomasks for a thin-film transistor circuit using a crystallized semiconductor thin film.
In the aforementioned Patent Publication No. 2003-31497 or 2003-318127, methods are disclosed which form crystal grains of large area through the use of a phase-shifting laser-based crystallization method. When this method is used in forming an actual thin-film transistor circuit, in order to form crystallized areas corresponding in arrangement to thin-film transistors constituting the transistor circuit, it is required to specially design the pattern of a phase-shifting mask for phase-modulation of laser light. The disclosed contents of the aforementioned known documents are not sufficient to efficiently prepare a practical phase-shifting mask.
It is an object of the present invention to provide a design method for a thin-film transistor circuit, a design program for a thin-film transistor circuit, a recording medium storing a design program, a design library database, a thin-film transistor circuit, and a display device, each of which allows the fabrication of photomasks suitable and effective for a crystallized semiconductor thin film.
According to a first aspect of the present invention, there is provided a design method for a thin-film transistor circuit using a crystallized semiconductor thin film, the method comprising the steps of: defining in a computer a crystallization array-pattern representing the arrangement of crystal-grain-defining areas which are arrayed for two-dimensional partitioning of the crystallized semiconductor thin film and each of which accommodates a crystal grain larger than a predetermined size; and causing the computer to, on the basis of the crystallization array-pattern, create a device pattern of thin-film transistors each of which has a channel region placed at a position fixed in a corresponding one of the crystal-grain-defining areas and a wiring pattern of wirings which interconnect the thin-film transistors.
According to a second aspect of the present invention, there is provided a design program for a thin-film transistor circuit using a crystallized semiconductor thin film, which causes a computer to carry out the processes of: defining a crystallization array-pattern representing the arrangement of crystal-grain-defining areas which are arrayed for two-dimensional partitioning of the crystallized semiconductor thin film and each of which accommodates a crystal grain larger than a predetermined size; and, on the basis of the crystallization array-pattern, creating a device pattern of thin-film transistors each of which has a channel region placed at a position fixed in a corresponding one of the crystal-grain-defining areas and a wiring pattern of wirings which interconnect the thin-film transistors.
According to a third aspect of the present invention, there is provided a design program recording medium recorded with a design program for a thin-film transistor circuit using a crystallized semiconductor thin film, which causes a computer to carry out the processes of: defining a crystallization array-pattern representing the arrangement of crystal-grain-defining areas which are arrayed for two-dimensional partitioning of the crystallized semiconductor thin film and each of which accommodates a crystal grain larger than a predetermined size; and, on the basis of the crystallization array-pattern, creating a device pattern of thin-film transistors each of which has a channel region placed at a fixed position within a corresponding one of the crystal-grain-defining areas and a wiring pattern of wirings which interconnect the thin-film transistors.
According to a fourth aspect of the present invention, there is provided a design program for a thin-film transistor circuit using a crystallized semiconductor thin film, which causes a computer to carry out the processes of: defining a crystallization array-pattern representing the arrangement of crystal-grain-defining areas which are arrayed for two-dimensional partitioning of the crystallized semiconductor thin film and each of which accommodates a crystal grain larger than a predetermined size; on the basis of the crystallization array-pattern, creating a device pattern of thin-film transistors each of which has a channel region placed at a position fixed in a corresponding one of the crystal-grain-defining areas and a wiring pattern of wirings which interconnect the thin-film transistors; and determining a phase-shifting mask pattern according to the crystallization array-pattern to define the crystal-grain-defining areas which are adapted to the device pattern of the thin-film transistors and realized on a semiconductor thin film by means of a laser-based crystallization method.
According to a fifth aspect of the present invention, there is provided a design program recording medium recorded with a design program for a thin-film transistor circuit using a crystallized semiconductor thin film, which causes a computer to carry out the processes of: defining a crystallization array-pattern representing the arrangement of crystal-grain-defining areas which are arrayed for two-dimensional partitioning of the crystallized semiconductor thin film and each of which accommodates a crystal grain larger than a predetermined size; on the basis of the crystallization array-pattern, creating a device pattern of thin-film transistors each of which has a channel region placed at a position fixed in a corresponding one of the crystal-grain-defining areas and a wiring pattern of wirings which interconnect the thin-film transistors; and determining a phase-shifting mask pattern according to the crystallization array-pattern to define the crystal-grain-defining areas which are adapted to the device pattern of the thin-film transistors and realized on a semiconductor thin film by means of a laser-based crystallization method.
According to a sixth aspect of the present invention, there is provided a design library database for a thin-film transistor circuit using a crystallized semiconductor thin film, containing at least one of standard cells representing various logic gate circuits and macrocells each representing a combination of some of the logic gate circuits, wherein each logic gate circuit includes two or more thin-film transistors each having a channel region placed at a position fixed in one of the crystal-grain-defining areas, and wirings which interconnect the two or more thin-film transistors.
According to a seventh aspect of the present invention, there is provided a thin-film transistor circuit comprising: a crystallized semiconductor thin film two-dimensionally partitioned into crystal-grain-defining areas each of which accommodates a crystal grain larger than a predetermined size; thin-film transistors each of which has a channel region placed at a position fixed in a corresponding one of the crystal-grain-defining areas; and wirings which interconnect the thin-film transistors.
According to an eighth aspect of the present invention, there is provided a display device comprising: an active-matrix circuit having pixels arrayed in a matrix form; a drive control circuit connected to the active-matrix circuit; and a thin-film semiconductor substrate which supports the active-matrix circuit and the drive control circuit, wherein the drive control circuit includes a thin-film transistor circuit comprising a crystallized semiconductor thin film two-dimensionally partitioned into crystal-grain-defining areas each of which accommodates a crystal grain larger than a predetermined size; thin-film transistors each of which has a channel region placed at a position fixed in a corresponding one of the crystal-grain-defining areas; and wirings which interconnect the thin-film transistors.
In the design method, the design program, the design program recording medium, the design library database, the thin-film transistor circuit, and the display device, a crystallized semiconductor thin film is partitioned into crystal-grain-defining areas each of which accommodates a crystal grain larger than a predetermined size and the channel region of each thin-film transistor is placed at a position fixed in a corresponding one of the crystal-grain-defining areas. Thus, by laying out the thin-film transistors and the wirings in units of crystal-grain-defining areas, the positional relationship between the channel regions and the crystal grains can be optimized. Further, a layout condition of crystal-grain-defining areas units allows the layout to be automated using a computer as a design tool. Thus, it becomes possible to fabricate photomasks suitable and effective for the crystallized semiconductor thin film, allowing the design cost to be reduced.
Moreover, by automatically determining the phase-shifting mask pattern according to the crystallization array-pattern, the time taken to design the phase-shifting mask can be reduced significantly.
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate an embodiment of the invention, and together with the general description given above and the detailed description of the embodiment given below, serve to explain the principles of the invention.
FIG. 22 is a flowchart illustrating the flow of a modification of the design process shown in FIG. 5.
A thin-film transistor circuit according to an embodiment of the present invention will be described hereinafter with reference to the accompanying drawings.
FIG. 1 shows a sectional structure of a thin-film semiconductor substrate 1 used in manufacturing the thin-film transistor circuit, and FIG. 2 shows a planar structure of the thin-film semiconductor substrate 1. The thin-film semiconductor substrate 1 is composed of a transparent dielectric substrate 2 such as of no-alkali glass, an SiNx film 3 formed on the transparent dielectric substrate 2, an SiO2 film 4 formed on the SiNx film, and a crystallized semiconductor thin film 5. The crystallized semiconductor thin film 5 is obtained, for example, by crystallizing an amorphous silicon film, and comprises crystal grains SX arrayed at regularly spaced intervals in the form of a matrix and amorphous silicon or polycrystalline silicon of fine grain size to surround the crystal grains SX. That is, the crystallized semiconductor thin film 5 is two-dimensionally partitioned into crystal-grain-defining areas 10 each of which accommodates a respective one of the crystal grains SX larger than a predetermined size. Each of the crystal grains SX is monocrystalline silicon of a nearly rectangular shape of about 4 by 4 μm. Each of the crystal-grain-defining areas 10 is slightly larger than the crystal grains SX and has dimensions of about 5 by 5 μm.
FIG. 3 shows an electron-microscopic image of one of the crystal drain defining areas 10 shown in FIG. 2. In each crystal-grain-defining area, a grain boundary GB is present in a portion of about 0.5 μm in width from the periphery. This portion forms an electrically active faulty region which act as the generation/recombination center of carriers; therefore, it is desirable to exclude the portion from the channel region of a thin-film transistor. The predetermined size is referenced to the size of the channel region of each thin-film transistor.
The aforementioned crystallized semiconductor thin film 5 is monocrystalline only in portions corresponding to the crystal grains SX located inside the faulty regions and hence greatly differs from a normal monocrystalline semiconductor substrate which is monocrystalline overall. In manufacturing the thin-film transistor circuit using such a crystallized semiconductor thin film 5, it is effective that the specific crystal structure of the crystallized semiconductor thin film 5 is reflected in the layout of the thin-film transistor, in order to obtain high-performance and uniform characteristics.
FIG. 4 schematically shows the structure of a computer which simulates a thin-film transistor circuit as a design tool. This computer includes a CPU 11 which controls the overall operation, a ROM 12 which stores various pieces of fixed data, a RAM 13 which temporarily stores data input to and output from the CPU 11, a display device 14 which displays various images under the control of the CPU 11, a keyboard 15 which enters various pieces of data into the CPU 11, an auxiliary input device 16, such as a pointing device, which specifies a coordinate position in an image displayed on the display device, a peripheral-device interface 17 which receives data from and sends data to external peripheral devices, and a hard disk drive 18 which stores a design program to be executed by the CPU 11, a library database and so on.
The computer performs a process of designing a thin-film transistor circuit by executing the design program stored in the hard disk drive 18. In this design process, the CPU 11 defines a crystallization array-pattern 10A representing the arrangement of the crystal-grain-defining areas 10 which are arrayed for two-dimensional partitioning of a crystallized semiconductor thin film 5 and each of which accommodates a respective one of the crystal grains SX larger than a predetermined size. On the basis of the crystallization array-pattern 10A, the CPU 11 creates a device pattern of thin-film transistors each of which has its channel region placed at a position fixed in a corresponding one of the crystal-grain-defining areas and a pattern of wirings which interconnect the thin-film transistors. The crystallization array-pattern 10A is configured such that the crystal-grain-defining areas 10 are arrayed in the form of a matrix and each accommodate a crystal grain of a nearly rectangular shape.
The hard disk drive 18 stores a library database containing standard cells and macrocells registered therein. The standard cells represent various logic gate circuits. Each logic gate circuit includes two or more thin-film transistors each of which has a channel region placed at a position fixed in one of the crystal-grain-defining areas 10, and wirings which interconnect the two or more thin-film transistors. The macrocells represent combinations of the various logic gate circuits. In creating the device pattern and the wiring pattern, the CPU 11 refers to the library database on the basis of externally input circuit information. The library database may contain only the standard cells; however, it is more efficient for it to further contain the macrocells.
It is desirable that, in the device pattern, the channel length and width of each of the thin-film transistors be set to less than the length of one side of the crystal-grain-defining area 10. Thereby, it becomes possible to accommodate the entire channel region of each of these thin-film transistors within one crystal grain SX.
The thin-film transistors are arranged in the device pattern at intervals of integral multiples of the length of one side of the crystal-grain-defining area. That is, these transistors are arranged in units of crystal-grain-defining areas.
Supposing that the length of one side of the crystal-grain-defining area is LC, the dimension of the larger one of the channel length and width of each transistor is LG, and alignment tolerance between the crystallization array-pattern 10A and the device pattern is LA, it is important to satisfy a relationship such that LC≧(LG+2×LA).
FIG. 5 illustrates the flow of a thin-film transistor circuit design process actually carried out by the computer shown in FIG. 4.
When, prior to circuit design, processing rules applied to a thin-film transistor circuit manufacturing process, the number of wiring layers and a pattern of a phase shifter used in crystallization are prepared as specifications of the crystallization array-pattern 10A, process technology specifications are determined from the specifications of the crystallization array-pattern 10A. Then, a library of the standard cells in which the pattern arrangements, the gate delay times, the driving abilities, and the like of various logic gate circuits are specified in accordance with the process technology specifications are registered as a library database in the hard disk drive 18. The standard cell library depends on the pattern arrangement of the crystal-grain-defining areas. Thus, the cell structure is made scalable by introduction of scaling parameters for automatically adjusting the layout positions of the thin-film transistors according to the pattern arrangement. Accordingly, reconfiguration of the standard cell library will not be required for a change in the dimensions of the crystal-grain-defining areas 10.
In the actual circuit design, the function of a thin-film transistor circuit to be implemented is described in step ST1 in the hardware description language HDL or the C language higher in the level of abstract than HDL. Logic circuit composition is performed in step ST2 on the basis of the contents of the description. At this time, a reference is made to the aforementioned standard cell library. The function of the thin-film transistor circuit are verified in step ST3 by performing a test simulation. If the results of simulation are satisfactory, the results of the logic circuit composition is acknowledged in step ST4 and then a network list is created in step ST5. Subsequently, the cell arrangement of logic gate circuits is determined based on the network list and the cell library information in step ST6, and wirings between cells are then determined in step ST7. The arrangement of cells is verified again in step ST8. If desired specifications are satisfied, the thin-film transistor circuit is acknowledged. In step S9, the layout data of the thin-film transistor circuit obtained virtually in the above manner is stored into the hard disk drive 18. Further, the layout data is converted into photomask data for the thin-film transistor circuit and output to an external TFT mask data storage.
The aforementioned design process, while being common in many respects to the design processes of commercially available semiconductor automated design tools, defines and registers not only standard cells forming a general-purpose library but also a standard cell of the crystallization array-pattern 10A representing the arrangement of crystal-grain-defining areas 10 which are arrayed for two-dimensional partitioning of the crystallized semiconductor thin film 5 and each of which accommodates a respective one of crystal grains SX larger than a predetermined size. By preparing the standard cell of such a crystallization array-pattern 10A as a layout condition, it becomes possible to automatically lay out the thin-film transistors and associated wiring layers.
In the thin-film transistor circuit design process, such a circuit symbol as shown in FIG. 6 is used to stand for a CMOS inverter which is a logic gate circuit that forms part of a thin-film transistor circuit. The CMOS inverter is composed, as shown in FIG. 7, of a P-channel MOS transistor P and an N-channel MOS transistor N, which are thin-film transistors formed using different crystal grains SX. Each crystal grain SX has a square shape and measures 4 μm on a side. The configuration of the CMOS inverter is registered as a standard cell shown in FIG. 8. With this standard cell, the CMOS inverter occupies 7×4 crystal-grain-defining areas 10 arranged in the Y and X directions. The MOS transistors P and N are formed using two semiconductor islands SI which is obtained by patterning the crystallized semiconductor thin film 5 and each has source and drain regions arranged in the X direction within a corresponding semiconductor island SI, a channel region CH placed between within the corresponding semiconductor island SI, and a gate electrode GM placed above the channel region CH. The gate electrode GM extends in the Y direction. The length of the channel region CH is set to 1 μm for each of the P- and N-channel transistors P and N. The width of the channel region is set to 2 μm for the P-channel transistor and 1 μm for the N-channel transistor. The channel region CH of each of these transistors is placed with the center portion of one crystal-grain-defining area 10 as a target (fixed portion). Thus, the channel regions CH of the transistors are arranged in either of the X and Y directions in units of 5 μm, the array pitch of the crystal-grain-defining areas 10.
In FIG. 8, VSS denotes a ground wiring which is part of a first-level Al (aluminum) wiring layer, VDD denotes a power source wiring which is another part of the first-level Al wiring layer, CONT1 denotes through holes for connecting the first-level Al wiring layer to the semiconductor island SI and the gate electrode GM, and CONT2 denotes through holes for connecting the first-level Al wiring layer to a second-level AL wiring layer for wiring between cells. The contact holes CONT1 are formed on the source and drain regions whose impurity concentration are set higher than that of the channel region CH in the semiconductor islands SI. Each of the source and drain regions is placed across the grain boundary GB. As long as the source and drain regions exhibit a desired low resistance, the presence of the drain boundary GB offers no problem in transistor operation.
In the design process, the wiring between standard cells is determined by recognizing the arrangement of a signal input portion VIN and a signal output portion VOUT shown in FIG. 8.
In this embodiment, the alignment tolerance LA between the crystallization array-pattern 10A and the device pattern is 0.5 μm, the length LC of one side of each crystal-grain-defining area 10 is 5 μm, and the dimension LG of the larger one of the transistor channel length and width is 2 μm; thus, LC=5 and (LG+2×LA)=2+2×0.5=3, which satisfy the abovementioned relationship LC≧(LG+2×LA).
With the use of a standard cell of the crystallization array-pattern 10A described above, the channel regions CH of the thin-film transistors are located only in the crystal grains SX which are surrounded by polycrystalline semiconductor of fine grain size in the crystallized semiconductor thin film 5. Thus, a high-performance circuit is attainable.
Furthermore, in the thin-film transistor circuit design process, such a circuit symbol as shown in FIG. 9 is used to stand for an AND circuit which is a logic gate circuit that forms part of the thin-film transistor circuit. The AND circuit has a CMOS structure shown in FIG. 10, for example, and comprises P-channel transistors P1 to P3 and N-channel transistors N1 to N3, which are thin-film transistors formed using different crystal grains SX. The logical product of input signals at first and second signal inputs VIN1 and VIN2 is output at a signal output VOUT. The configuration of the AND circuit is registered as a standard cell shown in FIG. 11. The channel length of the channel region CH is set to 1 μm for all the transistors P1 to P3 and N1 to N3. The channel width is set to 2 μm for the N-channel transistors N1 to N3 and the P-channel transistors P1 and P2 and 4 μm for the P-channel transistor P3. As in the standard cell shown in FIG. 8, the channel region CH of each of these transistors is placed with the center portion of one crystal-grain-defining area 10 as a target. For the transistor P3 having a particularly large channel width, it is formed of two sub-transistors which have channel regions assigned to the crystal-grain-defining areas 10 in different semiconductor islands so as not to contain the grain boundary GB and are connected in parallel so as to obtain the channel width in total.
To operate the pair of sub-transistors as the transistor P3, the channel regions of the sub-transistors are formed in the surface of crystal grains having identical crystal plane indexes, and the connection of the sub-transistors is set to have main current directions identical to each other.
Moreover, in the thin-film transistor circuit design process, an XOR circuit, for example, is used as a logic gate circuit which forms part of the thin-film transistor circuit. The XOR circuit has a CMOS structure shown in FIG. 12, for example, and comprises P-channel MOS transistors P1 to P4 and N-channel MOS transistors N1 to N4, which are thin-film transistors formed using different crystal grains SX. The exclusive logical sum of input signals from first and second signal inputs VIN1 and VIN2 is output at the signal output VOUT. The configuration of the XOR circuit is registered as a standard cell shown in FIG. 13. The length of the channel region CH is set to 1 μm for all the transistors P1 to P4 and N1 to N4. The channel width is set to 2 μm for the transistors N1 to N4 and 4 μm for the transistors P1 to P4. The channel region CH of each of these transistors is placed with the center of one crystal-grain-defining area 10 as a target. As in the AND circuit shown in FIG. 11, each of the P-channel transistors P1 to P4 is formed of two sub-transistors connected in parallel, and its channel width (=4 μm) is obtained as the total channel width (=2 μm×2) of the sub-transistors.
The standard cells shown in FIGS. 8, 11 and 13 are part of the standard cell library used in circuit design. Standard cells for many other logic gate circuits are actually registered in the standard cell library. Like the standard cells shown in FIGS. 8, 11 and 13, all the standard cells for logic gate circuits have a feature of occupying seven crystal-grain-defining areas 10 arrayed in the Y direction within the planar circuit pattern. The number of crystal-grain-defining areas occupied in the X direction may vary with the circuit scale.
FIG. 14 shows a half-adder including the inverter circuit, AND circuit and XOR circuit whose equivalent circuits are shown in FIGS. 7, 10 and 12. Specifically, two inverters INV, one AND circuit AND, and one XOR circuit XOR are provided in the half-adder. FIG. 15 shows a macrocell cell for the half-adder which is a combination of the standard cells shown in FIGS. 8, 11 and 13. This macrocell can be registered in the library database together with the standard cells. In the macrocell, the standard cells are interconnected by wirings automatically determined in the design process.
The dimension in the Y direction is normalized for all the standard cells. Thus, by arranging the standard cells in the X direction and automatically laying power-source and ground wirings on these cells, a logic circuit block of a desired function can be obtained virtually. The cells are interconnected through the first-level Al wirings placed outside the cell placed area and parallel to the ground wiring, the second-level Al wirings placed to extend from input and output contacts of the cells in the direction perpendicular to the ground wiring, and through holes CONT2 connecting the first-level and second-level Al wirings. The cells are placed relative to each other so that the regular placement of the channel regions of the respective thin-film transistors are maintained as a whole and moreover on the basis of the standard cell of the crystallization array-pattern. As a result, all the thin-film transistors constituting a thin-film transistor circuit can be placed to conform to the array pitch of the crystal grains SX.
FIG. 16 shows the sectional structure of the half-adder taken along line I-I′ of FIG. 15. As described above, the thin-film semiconductor substrate 1 is formed from the transparent dielectric substrate 2 such as of no-alkali glass, the SiNx film 3 formed on the transparent dielectric substrate 2, the SiO2 film 4 formed on the SiNx film 3, and the crystallized semiconductor thin film 5 such as crystallized silicon. The SiNx film 3 is formed as a buffer dielectric film to prevent the diffusion of impurities from the transparent dielectric substrate 1. The thicknesses of the SiNx film 3, the SiO2 film 4 and the crystallized semiconductor thin film 5 are 50, 100, and 200 nm, respectively. The crystallized semiconductor thin film 5 is covered with a gate dielectric film 20 of SiO2 which has a thickness of 30 nm. A gate electrode GM of MoW alloy is formed on the gate dielectric film 20.
The entire structure is covered with a first interlayer dielectric film 21 of SiO2. The contact through holes CONT1 are formed in the interlayer dielectric film 21. The power source wiring VDD, the ground wiring VSS and the in-cell wirings 22 are formed on the interlayer dielectric film 21 and connected via the though holes CONT1. Each of the wirings VDD, VSS, and 22 is a three-layered metal film of Mo/Al/Mo.
The entire structure is covered with a second interlayer dielectric film 23 of SiO2. The contact through holes CONT2 are formed in the interlayer dielectric film 23. The wirings 24 between the standard cells are an Al layer formed on the interlayer dielectric film 23, and the in-cell wirings 22 are connected via the contact through holes CONT2 to the wirings 24.
The entire structure is then covered with a protective dielectric film 25 of SiNx.
Here, the method for obtaining an array of crystal grains SX each of which has a nearly rectangular shape of about 4 by 4 μm in the semiconductor thin film 5 will be described in more detail.
When the transparent dielectric substrate 1 is a glass substrate having no high-temperature resistance as in the case where a monocrystalline silicon wafer is manufactured, it is most desirable to perform a laser annealing process for melting and recrystallizing an amorphous silicon by applies pulses of ultraviolet laser light, thereby obtaining the crystallized semiconductor thin film 5 in which the amorphous silicon is partially crystallized. At this time, in order to obtain crystal grains SX having the largest possible area, it is desirable to adopt a technique to make the laser beam intensity at the surface of the thin-film semiconductor substrate 1 have a spatial distribution using a phase shifter having a suitable pattern to thereby cause a lateral temperature gradient. Thereby, lateral crystal growth is induced, allowing an array of crystal grains each having a nearly rectangular shape of about 4 μm on a side to be obtained.
Next, a specific example of an annealing process using a phase shifter will be described with reference to FIG. 17.
The phase shifter 50 shown in FIG. 17 is formed of a transparent medium, such as quartz and has a pattern in which first and second strip portions (phase-setting portions) 50 b and 50 c of different thicknesses are arranged side by side. Incident laser light beams are diffracted and interfere with each other at the step boundaries (phase-shifting lines) 50 a between the portions 50 b and 50 c. Thus, the phase shifter 50 imparts a periodical spatial distribution to the intensity of incident laser light beams. The laser light beam of phase π comes out from the first strip portion 50 b, and the laser light beam of phase 0 comes out from the second strip portion 50 b. Thus, the phase of the laser light beam from the first strip portion 50 b is reversed to that of the laser light beam from the second strip portion 50 c (a phase difference of 180° is obtained). Each of the strip portions 50 b and 50 c has a width of 10 μm. As an example, the phase shifter 50 is formed using a rectangular quartz substrate whose refractive index is 1.5 to obtain the above-mentioned phase difference with respect to laser light having a wavelength of 248 nm. In this case, the quartz substrate is etched for the strip portion 50 b, thereby forming the strip portion 50 b thinner than the strip portion 50 c. The depth of etching is determined to 248 nm corresponding to phases . In addition, the quartz substrate is not etched for the strip portion 50 c.
In the phase shifter 50 thus fabricated, the laser light beam passed through the second strip portion 50 c is delayed by 180° relative to the laser light beam passed through the first strip portion 50 b smaller in thickness than the second ones. As the result, interference and diffraction occur between the laser light beam passed through the first strip portion 50 b and the laser light beam passed through the second strip portion 50 c, yielding such a laser light intensity distribution as shown in FIG. 18. Since the laser light beams from adjacent strip portions are reversed in phase, the intensity of the laser light at a position corresponding to the phase-shifting line between the adjacent strip portions becomes minimum, say, 0. Part in which the light intensity is minimum or the nearby part thereof forms nucleus that grow into crystal grains in crystallization of a semiconductor. Although, in the above example of the phase shifter 50, the phase-shifting lines extend in a form of parallel straight lines as shown in FIG. 17, this is not restrictive.
For example, it is also possible to array the phase-setting portions of phase 0 and of phase π in a checkered pattern, thereby causing the phase-shifting lines to cross at right angles. In this case, a grid-like pattern of light intensity 0 is obtained along the phase-shifting lines. For this reason, the crystalline nuclei are produced in arbitrary positions on the lines, leading to a difficult problem of control of the position and shape of crystal grains. For this reason, to control the production of crystalline nuclei, it is desirable that a point of intensity 0 is provided. For this reason, the amount of phase shift is set to less than 180° on the phase-shifting lines crossing at right angles. Thereby, the intensity is reduced but does not completely become 0 in positions corresponding to the phase shifting lines. At the same time, the intensity in positions corresponding to intersections can be made 0 by making the sum of complex transmittances around the intersection 0.
This will be described with reference to FIGS. 19 and 20. A mask 50 has a set of square patterns each comprised of four square portions 50 e, 50 f, 50 g and 50 h which are arranged side by side and are different in thickness as shown in FIG. 19. The square patterns are arranged side by side as shown in FIG. 20. The first square portion 50 e is the thinnest and has its phase set to 0. The fourth square portion 50 h is the thickest and has its phase different from the first square portion 50 e by 3π/2. The second and third portions 50 f and 50 g have thicknesses between those of the square portions 50 e and 50 h, and have their phases different from the first square portion 50 e by π/2 and π, respectively.
In such a mask, the location at which the first to fourth square portions adjoin, i.e., the center of the square pattern, forms a point of intensity 0. Therefore, the nuclei of a crystal grain grows from this point, allowing easy control of the position and shape of the crystal grain. A technique using such a phase shifter is described in the International Application No. PCT/JP03/03366, filed Mar. 19, 2003, by the same assignee as this application on the basis of the Japanese Patent Application No. 2002-120312.
FIG. 21 schematically shows the structure of an active-matrix liquid crystal display device into which thin-film transistor circuits designed through the design process shown in FIG. 5 are incorporated. This liquid crystal display device is equipped with an active matrix circuit AMX having liquid crystal pixels PX arrayed in a matrix form, a drive control circuit CNT, and a thin-film semiconductor substrate 1 that supports the active matrix circuit AMX and the drive control circuit CNT.
On the thin-film semiconductor substrate 1, the TFT active matrix circuit AMX has scanning lines 61 and video signal lines 62 which are arranged to intersect at right angles, and switching elements W each of which is formed of a thin-film transistor and is connected to the liquid crystal pixel PX placed in a respective one of the rectangular pixel areas defined by the lines 61 and 62. The drive control circuit CNT is composed of a scanning circuit 63, a signal supply circuit 64, a DC-DC converter 65, and a controller 66. These are integrated on the thin-film semiconductor substrate 1 using thin-film transistor circuits each comprised of a crystallized semiconductor thin film two-dimensionally partitioned into crystal-grain-defining areas each of which accommodates a crystal grain larger than a predetermined size, thin-film transistors each of which has a channel region placed at a position fixed in a corresponding one of the crystal-grain-defining areas, and wirings which interconnect the thin-film transistors. The controller 66 receives video data DATA and control signals from outside and performs required digital data processing to apply a scanning signal and a video signal to the scanning circuit 63 and the signal supply circuit 64. The DC-DC converter 65 converts a supply voltage DC from outside into voltages necessary for the scanning circuit 63 and the signal supply circuit 64. The scanning circuit 63 and the signal supply circuit 64 drive the liquid crystal pixels PX through the switching elements W.
The controller 66 depends to a large degree on customer specifications of the external interface and internal drive system, and is demanded to have an operation speed exceeding a specific speed. It is therefore desirable that the thin-film transistor circuit designed by the computer shown in FIG. 4 be mainly applied to the controller 66. By adopting the aforementioned design process using standard cells, the productivity is improved markedly in comparison with the conventional method in which all the thin-film transistor circuits are custom designed. Furthermore, by using standard cells in the crystallization array-pattern which reflect the specificity of crystal planar patterns as in the invention, substantially the same performance as when a monocrystalline semiconductor wafer is used can be obtained, allowing a higher-function and performance display device to be implemented. Moreover, the aforementioned thin-film transistor circuit design method exhibits a greater advantage in products in which not only the controller 66 but also more complicated digital logic circuits are integrated on a thin-film semiconductor substrate.
The thin-film transistor circuit design process shown in FIG. 5 may be modified as shown in FIG. 22, for example. In this modification, a phase-shifting mask pattern is automatically produced using the layout data of the thin-film transistor circuit.
Steps ST1 to ST9 of this modification is identical to those of the design process shown in FIG. 5. That is, the function of a thin-film transistor circuit to be implemented is described in step ST1 in the hardware description language HDL or the C language higher in the level of abstract than HDL. Logic circuit composition is performed in step ST2 on the basis of the contents of the description. At this time, a reference is made to the aforementioned standard cell library. The function of the thin-film transistor circuit are verified in step ST3 by performing a test simulation. If the results of simulation are satisfactory, the results of the logic circuit composition is acknowledged in step ST4 and then a network list is created in step ST5. Subsequently, the cell arrangement of logic gate circuits is determined based on the network list and the cell library information in step ST6, and wirings between cells are then determined in step ST7. The arrangement of cells is verified again in step ST8. If desired specifications are satisfied, the thin-film transistor circuit is acknowledged. In step S9, the layout data of the thin-film transistor circuit obtained virtually in the above manner is stored into the hard disk drive 18. Further, the layout data is converted into photomask data for the thin-film transistor circuit and output to an external TFT mask data storage and phase-shifter mask data storage.
Thereafter, automatic production of a phase-shifting mask pattern is carried out in step ST10. The phase-shifting mask pattern is determined according to the crystallization array-pattern to define the crystal-grain-defining areas which are adapted to the device pattern of the thin-film transistors and realized on a semiconductor thin film by means of a laser-based crystallization method. When the phase-shifting mask pattern is obtained virtually in step ST10 and acknowledged in step ST11, the phase-shifting mask pattern is converted into photomask data for the phase shifter and output to the external phase-shifter mask data storage.
In addition, the above-mentioned phase-shifting mask pattern may include a portion for crystallizing a part of the semiconductor thin film as an alignment mark of a specified shape that is used to align the photomask for the thin-film transistor circuit with the semiconductor thin film after crystallization.
causing the computer to, on the basis of the crystallization array-pattern, create a device pattern of thin-film transistors each of which has a channel region placed at a position fixed in a corresponding one of the crystal-grain-defining areas and a wiring pattern of wirings which interconnect the thin-film transistors.
2. The design method according to claim 1, wherein the crystallization array-pattern is configured such that the crystal-grain-defining areas are arrayed in a matrix form and accommodate crystal grains each of which is nearly rectangular in shape.
causing the computer to refer to the library database on the basis of circuit information input externally, to create the device pattern and the wiring pattern.
4. The design method according to claim 3, wherein the library database further contains macrocells each of which represents a combination of some of the logic gate circuits.
5. The design method according to claim 2, wherein the thin-film transistors are determined in the device pattern to have a channel length and channel width not exceeding the length of one side of each crystal-grain-defining area.
6. The design method according to claim 2, wherein the thin-film transistors are arranged at intervals of integral multiples of the length of one side of each crystal-grain-defining area.
7. The design method according to claim 2, wherein the length, LC, of one side of each crystal-grain-defining area, the dimension, LG, of the larger one of the channel length and channel width of each thin-film transistor, and the alignment tolerance, LA, between the crystallization array-pattern and the device pattern are set so as to satisfy a relationship LC≧(LG+2×LA).
on the basis of the crystallization array-pattern, creating a device pattern of thin-film transistors each of which has a channel region placed at a position fixed in a corresponding one of the crystal-grain-defining areas and a wiring pattern of wirings which interconnect the thin-film transistors.
9. The design program according to claim 8, wherein the crystallization array-pattern is configured such that the crystal-grain-defining areas are arrayed in a matrix form and accommodate crystal grains each of which is nearly rectangular in shape.
referring to the library database on the basis of circuit information input externally, to create the device pattern and the wiring pattern.
11. The design program according to claim 10, wherein the library database further contains macrocells each representing a combination of some of the logic gate circuits.
on the basis of the crystallization array-pattern, creating a device pattern of thin-film transistors each of which has a channel region placed at a fixed position within a corresponding one of the crystal-grain-defining areas and a wiring pattern of wirings which interconnect the thin-film transistors.
13. The recording medium according to claim 12, wherein the crystallization array-pattern is configured such that the crystal-grain-defining areas are arrayed in a matrix form and accommodate crystal grains each of which is nearly rectangular in shape.
15. The recording medium according to claim 14, wherein the library database further contains macrocells each representing a combination of some of the logic gate circuits.
determining a phase-shifting mask pattern according to the crystallization array-pattern to define the crystal-grain-defining areas which are adapted to the device pattern of the thin-film transistors and realized on a semiconductor thin film by means of a laser-based crystallization method.
17. The design program according to claim 16, wherein the phase-shifting mask pattern includes a portion for crystallizing a part of the semiconductor thin film as an alignment mark of a specified shape.
19. The design program according to claim 18, wherein the phase-shifting mask pattern includes a portion for crystallizing a part of the semiconductor thin film as an alignment mark of a specified shape.
wherein each logic gate circuit includes two or more thin-film transistors each having a channel region placed at a position fixed in one of the crystal-grain-defining areas, and wirings which interconnect the two or more thin-film transistors.
wirings which interconnect the thin-film transistors.
22. The thin-film transistor circuit according to claim 21, wherein the thin-film transistors and the wirings form logic gate circuits each of which has a common structure occupying a predetermined number of crystal-grain-defining areas.
23. The thin-film transistor circuit according to claim 21, wherein the crystal-grain-defining areas are arrayed in a matrix form and accommodate crystal grains each of which is nearly rectangular in shape.
24. The thin-film transistor circuit according to claim 21, wherein at least one of the thin-film transistors includes a pair of sub-transistors which have channel regions formed in the surface of crystal grains having identical crystal plane indexes, and are connected to have main current directions identical to each other.
wherein the drive control circuit includes a thin-film transistor circuit comprising a crystallized semiconductor thin film two-dimensionally partitioned into crystal-grain-defining areas each of which accommodates a crystal grain larger than a predetermined size; thin-film transistors each of which has a channel region placed at a position fixed in a corresponding one of the crystal-grain-defining areas; and wirings which interconnect the thin-film transistors.


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Three establishments face sanctions as Manila Bay rehab kicks off
By CNN Philippines Staff
Published Jan 27, 2019 11:35:38 PM
Metro Manila (CNN Philippines, January 27) — The water sources of at least three establishments along Manila Bay were cut off after being found violating environmental laws.
The Laguna Lake Development Authority (LLDA) issued cease and desist orders Sunday to Aristocrat Restaurant along Roxas Boulevard, Gloria Maris Shark's Fin Restaurant within the Cultural Center of the Philippines Complex, and San Miguel by the Bay at the Esplanade for discharging wastewater directly to the Manila Bay.
Deparment of Environment and Natural Resources (DENR) Secretary Roy Cimatu and Department of Interior and Local Government Secretary Eduardo Año led the delivery of the cease and desist orders for closure of water supply.
However, the DENR said no one was stopping the businesses from operating.
LLDA General Manager Jaime Medina said the owners of the establishments could lose their mayor's permit and environmental compliance certificate should they fail to correct their violations.
There was also no deadline given for them to do so.
Meanwhile, a crew member of the Aristocrat Restaurant told CNN Philippines they are still open for business.
Cimatu said the government will exert all efforts to win what he called "The Battle of Manila Bay" and restore it to its "former glory."
In an earlier statement, Cimatu said, "This is a battle that will be won not with force or arms but with the firm resolve to bring Manila Bay back to life... With the commitment and determination of every Filipino to do his share in this rehabilitation effort, we have already won the battle for Manila Bay."
The DENR earlier said ₱47 billion will be alloted for the bay's cleanup.
The budget will also be used to look for relocation sites of affected families living near the bay.
Along with the ceremonial launch, simultaneous cleanup activities will be held in parts of Las Piñas and Navotas, and towns in Bulacan, Bataan and Pampanga.
In a speech on January 9, President Rodrigo Duterte threatened to close down restaurants near the Manila Bay without proper water treatment systems, following his order to rehabilitate the polluted body of water.
On January 22, the Manila Zoo — another Manila landmark — was ordered temporarily closed by city authorities pending improvements in line with the Manila Bay rehabilitation.
Manila City Hall Administrator Ericson Alcovendaz said Mayor Joseph "Erap" Estrada issued the order to give way for the construction of sewer lines for zoo waste. He said it will be closed until the construction is finished.
CNN Philippines correspondent Xianne Arcangel contributed to this report.
QC isolates 143 individuals following PH's first case of new COVID-19 variant
Tourism dept. gives Makati hotel 15 days to appeal revoked permit
DILG to rehire only 15,000 out of 50,000 contact tracers due to budget constraints
Govt. may need more funds for free accommodation of returning OFWs

redpajama_set_name: RedPajamaCommonCrawl


Obituary for Racheal Durski | Shore Point Funeral Home and Cremation Services, Inc.
Racheal Durski, 38 of Jersey City, New Jersey passed away peacefully at home surrounded by her loving family on October 24, 2018. Racheal was born on February 28, 1980 in Perth Amboy, New Jersey. She graduated from East Brunswick Vocational Technical High School in East Brunswick, at which time she lived in Helmetta, New Jersey. She was the proprietor of Aire Salon in Jersey City, New Jersey. Racheal was predeceased by her grandparents Elizabeth and Edward Durski, Frank Clementi, Rosetta Giacomozzi and her uncle Joseph Clementi. She is survived by her partner Terry Cheung, her beloved daughter Elizabeth Cheung, her loving parents Martin D. Durski and his wife Jo-Ann of Jackson, New Jersey, Deborah Clementi Fortner and her husband Robert of Freeville, New York, her dear brother Richard Thomas Clementi and his wife Amanda, her loving uncle and God Father Robert Durski and his wife Patricia, dear aunts and uncles Edward Durski and his wife Kathleen, Frank Clementi, Patricia Clementi and her husband Harry, Dora Auld, Ann Giacomozzi, and her dear sisters and brother in law, Tinny Cheung and her wife Jenna, Timothy Cheung and his wife Winnie, and Tiffany Cheung. She will be dearly missed, but never forgotten.
Family and friends are invited to visit on Friday October 26, 2018 from 2:00 to 4:00 and 7:00 to 9:00 PM and Saturday October 27, 2018 from 9:45 to 10:30 AM. A prayer service will take place at the funeral home Saturday 10:00 AM. Interment will follow at Sacred Heart Cemetery in Sayreville, New Jersey. For information, directions, or to send condolences to the family, please visit, www.shorepointfh.com.


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HomeCelebritiesActors
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Jim Carrey Net Worth | Bio, Age, Height, Weight & Career 2022
Jim Carrey Net Worth
Jim Carrey Introduction
Jim Carrey Early Life
Jim Carrey Personal Life
Jim Carrey Age, Height, & Weight
Jim Carrey Career
Jim Carrey Awards
6 ft 1 inch (1.88m)
James Eugene Carrey is a comedian and actor from Canada and the United States. Carrey rose to prominence in 1990 after securing a recurring part in the American comedy series television show In Living Color. He is well known for his hyperactive slapstick performances.
Jim Carrey was born in 1962, on the 17th, of January, Carrey grew up in Toronto, Canada, and had a difficult upbringing. Jim Carrey's family was impoverished and even homeless when he was a youngster. For several months, he and his brother John had to live in a tent at Charles Daley Park on Lake Ontario.
Things would improve when his father was hired as an accountant at the Titan Wheels tire plant. Even yet, it wasn't enough to sustain his family. To make ends meet, Jim and John had to work for the corporation as cleaning staff and security guards.
Jim Carrey left high school on his sixteenth birthday and spent his leisure time doing comedy in downtown Toronto and working at the factory.
Jim Carrey has been married several times in his personal life. From 1987 to 1995, he was wedded to Melissa Womer. Jane Erin Carrey, an American Idol contestant, is a Carrey family member. He wedded his Dumb & Dumber co-star, who was also his bride-to-be, in 1996.
It was just a question of time until the pair ended their relationship. He was supposed to be in a romantic relationship with Jenny McCarthy, an actress, and model, from 2005 until 2010.
Being born in 1962, on the 17th, of January "Jim Carrey" age is 61 years old as of today date and his height is 6 feet 1 inch tall, (1.88 m) and his weight is 83 kilograms and (185 lbs) in pounds as of 2022.
Carrey had a difficult time getting into the entertainment world at first. Despite his father's best efforts, his performance was not well received in any of the Toronto comedy clubs where he performed. Despite this, he was welcomed back on stage and earned a slew of favorable feedback after getting experience and honing his performance. He'd gotten to the stage where he could secure paid television appearances.
Jim Carrey values visual inventiveness and promotes it in his works. In fact, before earning a reputation for himself in the profession, he handed himself a $10 million check. You may also look at Bradley Cooper's Net Worth.
Jim has garnered over 40 big awards during his lifetime.
Jim Carrey has an approximate net worth is estimated to be around $180 million as of 2022. From 1994 to 2008, Carrey made a total of $200 million in salary and incentives. During his best years in the mid-1990s and early 2000s, he was earning about $20 million each feature. However, Jim Carrey made the most money when he demanded 36.2 percent of Yes Man's back-end revenues.
While the film wasn't one of his highest-grossing, grossing just $223 million in total, it still netted him a tidy sum. Carrey managed to get away with $32 million when everything was said and done.
Jim has a lot of properties throughout the United States. His principal property has always been a huge complex in Los Angeles' Brentwood neighborhood. He purchased the first residence in his complex in 1994 for $3.8 million (about $6.6 million today). He paid $1.7 million for the 1-acre site next door in 2000. The property now includes a spacious guest house, a pool house, and a tennis court.
In 2002, he paid $9.75 million on a Malibu seaside house. In 2011, he offered the house for sale for $18 million. In 2013, he eventually found a buyer for $13.4 million. Jim also has a New York City apartment.
Jim Carrey has an approximate net worth is estimated to be around $180 million as of 2022.
After the publication of Ace Ventura: Pet Detectives in 1994, he rose to international prominence. Over the next two decades, he rose to become one of the world's highest-paid actors, routinely earning $20 million or more for a single film.
He was the first performer to make $20 million for a film and has amassed an estimated $300 million in film pay and incentives to date.


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László Gergely ist der Name folgender Personen:

* László Gergely (Eishockeyspieler) (1916–1946), ungarischer Eishockeyspieler
 László Gergely (Fußballspieler) (* 1941), rumänischer Fußballspieler

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If you've taken a career break to raise children, reentering the workforce can be a challenge. Though motherhood is arguably the most difficult—and important—job on the planet, it isn't a paid position. And the gap it leaves on your resume often seems to erase the experience you had before becoming a mom.
How do you rebuild your confidence as a competent and capable career woman? And how do you prepare yourself emotionally for the transition back to work?
Rita Kakati Shah is on a mission to support women in returning to the workforce through Uma, a startup that gives mothers the tools to rediscover themselves and find jobs that match their credentials—and their lifestyle commitments.
Today, Rita joins me to explain how her own frustration around going back to work served as the inspiration for Uma. She shares Uma's mission to empower women with the confidence and emotional readiness to reenter the workforce, offering advice around developing your swagger and scenario planning for childcare. Listen in for Rita's insight on how entrepreneurship is just a different kind of motherhood and learn how society benefits when moms are supported in returning to the workforce!
Rita Kakati Shah is the Founder and CEO of Uma, a professional training and coaching firm that empowers women to reenter the workforce after taking time off to raise children. Rita began her career as an investment banker, working for Goldman Sachs in London for a decade before transitioning to the healthcare industry. She is a fierce advocate for diversity and equality issues, earning the prestigious Excellence in Citizenship and Diversity Award for her outstanding contributions to diversity initiatives at Goldman Sachs.
This podcast is made possible by Alavita Nutrition, a tremendous resource when it comes to food, health, and wellness. The Alavita team is on a mission to make eating good food and understanding nutrition easier for busy moms. Head to https://www.alavitanutrition.com/ and use the code 'startup pregnant' for 20% off their self-paced programs or a nutrition consultation.


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Mr. Abdullah Gul, President of Republic of Turkey will be honored guest of the IBU new premises opening ceremony
Burch International University has a great honor to welcome Mr. Abdullah Gul, a President of the Republic of Turkey on the third of September 2010 at 10:30. In the presence of numerous guests, President Gul will honor Bosna Sema Educational Institutions and International Burch University attending the opening ceremony and cutting the red ribbon which will officially mark the opening of new modern University facilities.
New building, including four floors and 9600 m2 of space, meets the most demanding criteria based on the number of students appointed by the Bologna process. The building is equipped with modern laboratories for Department of Genetics and Bioengineering and Department of Architecture, includes library, a large number of classrooms, work spaces and other facilities for students.
The eleventh President of the Republic of Turkey Mr. Abdullah Gul will officially open the new premises of International Burch University whose construction cornerstone is laid by His Excellency Koksal Toptan, The Speaker of Turkish Parliament during his visit in April last year.
Opening ceremony will be open for public.
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The available titles are listed below, and can be requested for pickup at your nearest Library branch simply by clicking the cover images and then Place Request. All Great Courses DVDs and audiobooks are loaned out for three weeks so you can learn at your own pace. Only two DVDs and two audiobooks may be borrowed at a time.
Let us know what you think about the Great Courses. Did you enjoy any specific titles? Are there other topics you'd like us to try to obtain? Send us your feedback here.


Hello! My name is Natalia. I'm looking for a man. As to my appearance I am a brunette with medium-sized straight hair, brown eyes and a slender figure. I'm rather tall and slim. Speaking about my character I think that I'm even tempered, rather reserved and calm. I have my own likes and dislikes. In my free time I like to study foreign languages (English, German and French). I know English very good. I study German. And recently I started to learn French. Also I'm fond of reading books. And I like to do sports (gymnastics, jogging). I find interesting to travel around the world. As for me I appreciate people's honesty, kindness and politeness. I don't like when people are rude and aggressive. I am single, not married, have no children. I have a degree of Master of Economics. Sometimes it seems to me that the devil is walking next to me... But I still believe in destiny and in love. Please message me if you are interested in me.


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Peter Vanderbank or Vandrebanc (1649–1697) was a French-English engraver.

Life
Vanderbank was born in Paris in 1649, and studied his art there under Nicolas Poilly. About 1674 he accompanied Henri Gascar to England, and gained a reputation as an engraver of portraits, which he executed on a larger scale than any previously produced in this country.  He appears to have had five sons, including the painter John Vanderbank. On his prints his name is always spelt Vandrebanc. He received little remuneration for his work, and at the end of life was in reduced circumstances. He died in 1697 at Bradfield, Hertfordshire, the residence of John Forester, whose sister he had married, and was buried on 4 October in the church of Cottered-cum-Bradfield.

A mezzotint by George White, inscribed 'Peter Vanderbank, engraver,' has been assumed to be a portrait of him, and copied by Ambrose William Warren for the 1849 edition of Horace Walpole's Anecdotes; but the costume is of a somewhat later date, and it may represent one of his sons, who is said to have practised engraving, though his works are not known.

Works
They include portraits of Charles II, James II, Mary Beatrix, the Prince and Princess of Orange, Louis XIV, the Duke of Monmouth, Sir William Temple, Sir Edmund Berry Godfrey, and other prominent persons, chiefly from pictures by Peter Lely, Godfrey Kneller, and Gascar; also a 'Holy Family' and 'Christ on the Mount of Olives,' after Sébastien Bourdon, and three plates from Antonio Verrio's ceilings at Windsor Castle. Vanderbank engraved, from drawings by Edward Lutterell, the earlier portraits in White Kennett's History of England.  After his death his widow sold his plates to Abraham Browne, a print-dealer.

References

External links

1649 births
1697 deaths
17th-century engravers
French engravers
French emigrants to the Kingdom of England
English engravers
Artists from Paris


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SummaryEdit
DescriptionMémoires du maréchal Joffre (1910-1917) (...)Joffre Joseph bpt6k208186x.pdf
English: This document is the reproduction of the Memoirs of Marechal Joffre (t. 2).
Source This document comes from the french website "Gallica" (French National Library). Link : https://gallica.bnf.fr/ark:/12148/bpt6k208186x/f1.image.r=M%C3%A9moires%20du%20mar%C3%A9chal%20Joffre%20(1910-1917)
Joseph Joffre (1852–1931)
Alternative names Marshal Joseph Jacques Césaire Joffre; Marshal Joseph Jacques Cesaire Joffre
Description French military personnel and military engineer
Date of birth/death 12 January 1852 3 January 1931
Location of birth/death Rivesaltes Paris
NAID: 10572352
creator QS:P170,Q207958
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Joffre, Joseph (1852-1931)
Mémoires du maréchal Joffre (1910-1917)
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Wang Zhao—AFP/Getty Images
A model looks at her mobile phone while backstage during China Fashion Week 2015 in Beijing.
Smarter, Sexier State Media: There's an App for That
A Popular Government-Funded Start-Up is Like Vox with a Side of Propaganda
By Tabitha Speelman, a freelance correspondent based in Shanghai. This article was first published by Foreign Policy's China channel, Tea Leaf Nation.
Before the Internet age, it used to be relatively straightforward for authoritarian regimes to dictate popular news consumption: just control all the major newspapers, as China's ruling Communist Party has done since the founding of the People's Republic in 1949. But the advent of the Internet, particularly the rise of the social web, has broken that monopoly. Stiff online competition for the attention of China's more than 600 million Internet users has become a major challenge for state media and its traditionally stolid reporting style. In response, the country's leaders are looking for new ways to control how citizens produce and consume news; in the last two years, Chinese President Xi Jinping has stepped up this effort by restricting online freedom of speech, launching a central leading group on Internet affairs, and repeatedly calling for "proactive" and "effective" Communist Party-led responses to a changing media environment.
Enter the Paper, or Pengpai in Chinese, a web-based media outlet headquartered in Shanghai promising to provide news on "politics and thought" and one of the most successful answers to Xi's call thus far. A start-up launched in July 2014 with enough government funding to now reach over 300 staff members, the Paper is the first Chinese web-based news organization to create a mobile news application featuring its own content. (Other larger online news apps like Today's Headlines typically don't have a government license allowing them to produce their own news, instead curating the content of licensed outlets.) And while some state outlets do have a large mobile presence—Party mouthpiece People's Daily operates a huge public account on mobile messaging platform WeChat—the Paper has distinguished itself by successfully integrating into the media diet of many young Chinese, most of whom would normally not follow or share state media's often stodgy coverage.
The popular and slick-looking app offers over 100 news and background stories a day in 49 categories that range from rule of law to real estate to art. It is already a staple in WeChat feeds and web portal repostings, greatly amplifying its influence. The quantity and range of content attracts readers, most of whom are young and educated. Bruce Bo Ding, 26, a Guangdong native who now works in an art gallery in Shanghai, said the Paper is the only news app left on his phone. "I only have so much time," said Ding. "Pengpai offers a lot of content in one place. I can just pick and choose."
Pulitzer's 'Lookout on the Bridge' vs. China's 'News Ethics Committees'
David Bandurski
In a recent harangue on the imperative of better journalism, a website run by the Chinese Communist Party's Central Propaganda Department tore a jagged page from the wisdom of American newspaper publisher Joseph Pulitzer: "A journalist is the...
How did the Paper—which, according to its deputy editor in chief, Wei Xing, receives about 20 million page views a day—manage to establish itself in the middle of the hypercompetitive Chinese social media landscape so quickly? For many readers, their first introduction to the platform, months before its official WeChat launch, came via the Paper's aggressive coverage of Xi's anti-corruption campaign. The nationwide graft sweep, tackling an issue that had long been at the top of the list of citizens' concerns, has been a hugely popular cornerstone of the Chinese president's tenure so far. The Paper reported extensively on the lives of fallen "tigers," official slang for high-ranking officials, all across the country. "Part of that was marketing," said Wei Xing in an interview with Foreign Policy. "There is a huge demand in China today for high-quality political news. People are no longer content with simple stories about local events. They want to know why."
But it was also timing. "Because of the campaign, we had all this material to report on," said Wei Xing, referring to China's political environment, in which many topics are strictly off-limits to the media unless government permission is granted. "Without that background, we would not have been able to do it, even if there was demand." It was during the anti-graft sweep that Xu Liangliang, a 23-year-old university graduate working in finance in Shanghai, started reading the Paper. "I am interested in politics," said Xu, "and their news on the crackdown was different from that of traditional media. It was a better read." The Paper's writings on the campaign sometimes read like a mix between novels and gossip magazines. One influential article on former official Ling Zhengce, the brother of former President Hu Jintao's top aide Ling Jihua now accused of corruption, opened with an allusion to Gabriel García Márquez's celebrated novel One Hundred Years of Solitude.
From the start, the Paper, which is part of the state-owned Shanghai United Media Group, had a difficult mission. The expectations from the leadership were clear: gain influence without making anyone up top look too bad. To do so, the start-up had to appeal to online readers, many of whom have an appetite for in-depth news without overt propaganda. "You have the right to know more," goes one of the Paper's advertising slogans. The platform's viral opening essay by CEO Qiu Bing discusses the summer of 1990, which he spent at university and during which "the air was filled with the smell of departure." Meant to evoke the idealism of China's 1980s (which came to an abrupt end with the 1989 Tiananmen Square massacre, not mentioned in Qiu's essay), it was dedicated to "everyone who still harbors ideals." Some hoped that the new media venture, with its ample funding and ambitious aim of becoming China's premier political news platform, would revive an otherwise ailing media climate. Others, however, pointed to the endorsement of Shanghai Communist Party chief Han Zheng and Internet czar Lu Wei, which suggested the outlet would adopt a more conservative approach.
So far, it seems a bit of both, with the Paper running both critical exposés on social issues that are sometimes deleted post-publication, indicating censors believed them too politically sensitive, as well as propaganda-like pieces. This past summer, an especially popular article series discussed a gay university student's lawsuit against the Ministry of Education over allegedly discriminatory language in the curriculum. The Paper was the first media outlet to report that the student was being pressured by her university to drop the lawsuit. But the Party hand remains readily apparent in other coverage on the platform. As with other state media, the Paper's main headlines are almost invariably reserved for Xi, broadcasting anything from his comments on reform to what he eats during state visits. "Why do university students born after 1990 choose Xi Jinping as their idol?" was the title of a piece the Paper reposted on its app. One article last June, praising rescue divers searching for survivors in the Yangtze River after a ferry boat carrying more than 400 had sunk, drew heavy criticism for its uncritical coverage of the government's rescue operation.
Such variety leaves the new outlet's ideological leaning up to interpretation. "That is up to the reader to discern," Ding said. "Yes, the Paper might have things that look like the Global Times"—a reliably nationalist state-run publication—"but it also has other things. You have to make your own judgment call." To Li Shen, a 29-year-old Chengdu native, the mixed messages make the Paper hard to pin down. "The quality is quite uneven. It looks like they are trying a bit too hard to attract young readers," said Li, who works in publishing. "But at the same time, they do often really go the extra mile in their coverage." Li enjoys the Paper's history and social issues channels but stated that she doesn't "really read their news."
"It is a bit of a jumble," Wei Xing, the deputy editor, acknowledged. He likes to think of the Paper as standing in the middle of the Chinese media landscape, both in terms of its size ("smaller than web portals like Tencent, bigger than financial media like Caixin") and its ideology.
Since its launch, the Paper's rapid growth and emphasis on quantity has led to a number of quality control issues. In September 2014, the Paper published a partial Chinese translation of an article from the Economist, leaving out negative references to China's political system and changing the tenor of the article. Chinese journalist and blogger Fang Kecheng discovered in October 2014 that the Paper had plagiarized an article on CNPolitics, a website he founded dedicated to popularizing academic studies on China to a Chinese public. The Paper later posted an apology below the revised piece. A former political reporter at the Paper, who asked to remain anonymous as she is still working in Shanghai media, relayed how she was sent to the southern province of Yunnan to pursue stories of corrupt officials about a month after accepting the job. "It was exciting, but the work pressure was high and there was little guidance," she recalled. "As a new media platform, we had to work ourselves into people's news feeds. Quantity was very important. But most reporters were young and inexperienced."
Despite these incidents, the Paper is doing quite well, Fang told Foreign Policy. "Quality control is not a priority, it seems. But they work hard and have lots of talent on board," he said. "And they are the first to offer such a comprehensive online news app. They don't really have any competitors." Still, Fang emphasized that the Paper should be classified as a Party platform: "They can be very pro-government and clearly don't need to worry about being commercially viable."
Shen Yachuan, a veteran journalist writing under the pen name Shi Feike, doesn't need to be reminded of the Paper's Party backing. In July, he wrote a widely read online essay criticizing its sometimes uncritical attitude and explaining why he had deleted its news app from his phone. Shi confessed that he was "confused" about some of the Paper's content, which he describes as "classical Global Times," a marked contrast to the Oriental Morning Post, the local Shanghai paper from which the platform grew. "I hope I will reinstall the app one day," he concluded.
But Wei Wuhui (no relation to Wei Xing), a scholar of media development based at Shanghai Jiao Tong University, is more upbeat. He had previously voiced his criticisms of the Paper's model. But now he says he is largely impressed. "It is very rare for Shanghai's traditionally conservative and locally focused media to have a national impact on public opinion," he said. "That privilege is usually reserved for the central government media or, previously, the Southern Media Group. But the Paper has established a national presence."
In the current media environment, you could say they have been pushing the envelope where they can. Especially when it comes to reporting abuses in other localities.
"In the current media environment, you could say they have been pushing the envelope where they can," said Wei Wuhui. "Especially when it comes to reporting abuses in other localities." But in China's tightly controlled press, in which the bounds of politically acceptable criticism are constantly changing, even a state-run publication may not always know where the line is. An early series of critical articles about legal miscarriages in other provinces resulted in a warning from Beijing. Still, during the first months of the Paper's existence, the platform seemed to enjoy a bit more leeway in order to make an impact. During those months, several exposés were published one after the other, and three local courts even publicly announced their intent to look into court cases the Paper had investigated. Last July, one of the investigated cases was overturned. The platform was also the first to report on the details surrounding the arrest of Rui Chenggang, a well-known anchor at state broadcaster China Central Television (CCTV).
Scoops and openly critical essays have been rarer this year. That does not mean there have not been attempts. "When will Chinese-style 'convictions outside the courtroom' end?" an article that can no longer be found on the Paper's website asked in March, referring to the phenomenon of parading criminal suspects on CCTV to plead guilty before their trial. In July, a series of three articles on the environmental and social impact of the massive Three Gorges Dam was censored soon after it came online. And on December 1, the Paper took down a news article announcing an investigation against an official in Hunan province, only to republish it online after the government had made a formal announcement.
Apart from its continuous—if not as bold—news reporting this year, the platform distinguished itself by compiling online dossiers on topics of public interest, leaning toward the "thought" part of the Paper's mission statement. An article from September 2015 asking whether China's feminism was too theoretical, for example, attracted responses both on and outside the platform. Last month, a recently added question-and-answer section featured gender studies scholar Fang Gang, who led an online discussion on why men should be feminists. The Paper also reserves more room for a diverse range of book, film, and art critiques than most Chinese media offers.
According to media scholar Wei Wuhui, this shift from in-depth investigations to other types of content should also be blamed on the exodus of experienced investigative journalists, both at the Paper and across the Chinese media landscape. Pay tends to be low while tightening government control of the media scares away those with a passion for the profession. Peking University communications expert Wu Jing recently lamented this, stating that even media students no longer read the news. But if they do, she added, they read the Paper.
The people from the State Internet Information Office are quite satisfied.
So far, the government's strategy of cultivating online media start-ups as a way to reach new audiences, in addition to boosting the social media presence of state outlets such as People's Daily and CCTV, seems successful. Already, outlets across the country are copying the Paper's model. In the past half-year, media groups have launched similar online platforms in the provinces of Sichuan, Henan, Hubei, Guangdong, and Xinjiang, as well as in the capital Beijing. The Paper itself is working on an English-language platform that will be launched in the first half of 2016. "It is another sign of the Paper's success," said Wei Wuhui. "The people from the State Internet Information Office are quite satisfied." And even after leaving the Paper to pursue other interests, the anonymous reporter working in Shanghai remains an avid reader. Caixin, the Beijing-based publication famous for its investigative journalism, is probably better, she said, "but reading a Caixin long-read takes a lot of time and dedication. The Paper is faster and more accessible."
To deputy editor Wei Xing, the Paper's growing influence is a sign that even government-funded media, with its limitations, can make a journalistic contribution in China. "Yes, all our money comes from the government. But we can still make different news as well. Or rather," he paused, seeking a description of content that doesn't have a clear propaganda slant, "normal news."
Media, State Media, Media Control, Internet, Journalism, News


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AHRA Board of Directors endorses the efforts of Are You Dense Advocacy, Inc.
Communication and organizational resources allow members to play important role in early breast cancer diagnosis.
Sudbury, MA (April 8, 2013) — AHRA: The Association for Medical Imaging Management (AHRA) Board of Directors has endorsed Are You Dense Advocacy, Inc. and its efforts to standardize the communication of dense breast tissue. This includes support of breast density notification laws and expanded insurance coverage screening legislation. Connecticut was the first state to enact both laws. Other states, including Texas, Virginia, New York, and California, now have breast density notification laws. Fifteen state breast density bills have been introduced in 2013 and the reintroduction of the federal breast density bill is forthcoming.
"With a strong national footprint, representing nearly 5000 medical imaging leaders, the AHRA board felt that it was our duty to support the development of these laws throughout the United States to effectively reduce the mortality rate among women with dense breast tissue," said Carlos Vasquez, RT(R), CRA, FAHRA, FACHE, AHRA President. "By creating an effective communication process and leveraging the resources available through our respective imaging centers, hospitals, and health systems, we can provide this high risk population with access to a potential early diagnosis."
In the interest of public health, safety, and prevention, the AHRA Board of Directors supports Are You Dense Advocacy's mission to use regulatory, state, and federal legislative efforts to standardize the communication of dense breast tissue to women across the country. "Most women are unaware of the fact that they have dense breasts, as well as the potential risk factors associated with their situation," said Luann Culbreth, RT(R)(MR)(QM), CRA, FSMRT, FAHRA, AHRA Past President. "By ensuring there is a process for breast density notification, as well as insurance to cover appropriate screenings, our members who facilitate screening mammography can play a significant role in identifying cancers in early stages and ultimately save lives."
"We are thrilled to have the expertise of AHRA and its members as they join us to ensure that all women, regardless of where they live or who their doctor is, understand the risks and screening challenges of dense breast tissue. Having the endorsement of medical imaging leaders will provide women with strong legislative advocacy to standardize the communication of dense breast tissue across this country," added Dr. Nancy Cappello, President and founder of Are You Dense Advocacy, Inc. More information on state, federal, and regulatory efforts initiated by Are You Dense Advocacy, Inc. can be found at www.AreYouDenseAdvocacy.org.
AHRA: The Association for Medical Imaging Management is the professional organization representing management at all levels of hospital imaging departments, freestanding imaging centers, and group practices. Founded in 1973, AHRA's 5000 members reach across the country and around the world. AHRA offers a complete slate of professional development programs including a comprehensive selection of educational conferences and seminars, networking opportunities, award winning publications, and the Certified Radiology Administrator (CRA) credential. www.ahraonline.org
About Are You Dense Advocacy, Inc.
Are You Dense Advocacy, Inc. is a 501(c)(4) nonprofit charity with the mission of employing regulatory, state, and federal legislative efforts to standardize the communication of breast tissue to women. The charity was founded by Nancy M. Cappello, PhD in 2011, after her successful landmark legislative advocacy as Connecticut became the first state in the country to standardize the communication of dense breast tissue through the mammography report. Additionally, Connecticut has also enacted expanded insurance screening coverage for women with dense breast tissue. www.areyoudenseadvocacy.org
Dr. Cappello also founded Are You Dense Inc.
Are You Dense Inc., a 501(c)(3) public charity, after her advanced stage breast cancer diagnosis within weeks of a normal mammogram report and a decade of normal reports preceding her diagnosis. Its mission is to educate the public about the risks and screening challenges of dense breast tissue. www.areyoudense.org
Mike Suddendorf – msuddendorf@ahraonline.org
Nancy M Cappello Ph.D. – nancy@areyoudenseadvocacy.org
Are You Dense Advocacy, Inc.
President and Founder


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Q: Is there a name for this pipelining-like parallelization method? Recently, I was trying to optimize a single-threaded loop that at its core boils down to something like
while (true)
{
   a = A(x)
   b = B(a)
   c = C(b)
}

In other words, every step depends on the result of the previous step. Each of these functions performs CPU intensive operations.
I ended up creating 2 queues and 2 new threads and decoupled it so that the original thread does
/* on existing thread */ while (true) queue1.Enqueue(A(x))
/* on new thread #1 */   while (true) queue2.Enqueue(B(queue1.Dequeue()))
/* on new thread #2 */   while (true) c = B(queue2.Dequeue()))

Now the 3 functions can run in parallel, making better use of multiple cores.
It seems so basic, there must be a name for it. I cannot find it though. It highly resembles what pipelining does, only this is a parallelization technique for threads.

A: A bit more thorough web searching revealed it is called Pipeline Parallelism by some. Which is a descriptive name.
On one of the pages linked to above, there's also an intuitive visualization of the method:

redpajama_set_name: RedPajamaStackExchange


Receptor-activated non-selective calcium permeant cation channel involved in detection of noxious chemical and thermal stimuli. Seems to mediate proton influx and may be involved in intracellular acidosis in nociceptive neurons. May be involved in mediation of inflammatory pain and hyperalgesia. Sensitized by a phosphatidylinositol second messenger system activated by receptor tyrosine kinases, which involves PKC isozymes and PCL. Acts as ionotropic endocannabinoid receptor with central neuromodulatory effects. Triggers a form of long-term depression (TRPV1-LTD) mediated by the endocannabinoid anandamine in the hippocampus and nucleus accumbens by affecting AMPA receptors endocytosis (By similarity).


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The Rental Market
The Open House Scorecard: Seventieth Heaven
By Sara Alessi | May 20, 2013 - 2:38PM
Apartments in the East and West 70s drew a lot of attention this week, with a trio of apartments there making this edition of the Open House Scorecard--the 10 open houses those perusing StreetEasy this weekend saved to their open-house calendars more often than any others.
Take in Lenox Hill from the private terrace (pictured) of a $1.695m three-bedroom, two-bathroom postwar co-op on East 70th Street (between First and Second Avenues). The thoroughly renovated corner unit is located on a tree-lined block in a full service building that offers a storage room, bike storage, a discounted garage, a common roof deck and a common laundry room. The apartment itself has an L-Shaped living room/dining area leading into the kitchen. Pets are allowed, but in-unit washer-dryers are not.
On the Upper East Side, on the corner of East 78th Street and Third Avenue, you'll find a west-facing two-bedroom, two-bathroom co-op on the market for $950k. Located in a postwar doorman building, the apartment features an L-shaped living room, and the dining area is currently being used as a third bedroom, but can be reconverted. There's a walk-in closet and en-suite master bath, but the apartment needs some TLC.
Over on the Upper West Side, on 77th Street, is an $875k two-bedroom, two-bathroom condo with a washer-dryer, built-ins and overhead storage, as well as a Murphy bed, which all help save on space. Located between Columbus and Amsterdam Avenues on Museum Block, the building has a new roof deck and hallways, bike storage and a central laundry room. One downside: it's a three-flight walk-up.
Check out the rest of the Scorecard below.
204 West 10th Street—1-bed condop, $595k
349 16th Street—2-bed condo, $800k
22 Leroy Street—2-bed co-op, $750k
355 Saint Johns Place—3-bed condo, $750k
102 East 22nd Street—1-bed co-op, $778k
200 East 78th Street—2-bed co-op, $950k
105 West 77th Street—2-bed condo, $875k
11 East 29th Street—2-bed condo, $1.749m
2373 Broadway—2-bed condop, $1.5m
310 East 70th Street—3-bed co-op, $1.695m
Moving to NYC? Here's a crash course in finding an apartment here
How to buy a NYC apartment
What's included (and what's not) when you buy a NYC apartment (sponsored)
StreetEasy Open House Scorecard buying Gramercy Park Park Slope Prospect Heights Upper East Side Upper West Side West Village
Thinking about selling in today's market? Then you should already be in The Agency's Pre-Market Program [ SPONSORED ]
The best websites for finding a no-fee rental apartment in NYC
By Austin Havens-Bowen
Can I get a rebate on the real estate commission when I buy an apartment in NYC? Is the commission negotiable?
Sponsored By Prevu