text:
Q: how to check if a TCP port is available in c socket? i am writing a program that 2 players wants to connect to the server to play rock, paper and scissors.The first player connects to the port 60000 and when the second player want to connect it tries to connect to port 60000. if it fails, it will connect to port 60001. At this moment i am not sure how to implement the second player.
Client:
int sock = 0;
char *hostname = "127.0.0.1";
struct sockaddr_in serv_addr;
char buffer[1024] = {0};
if ((sock = socket(AF_INET, SOCK_STREAM, 0)) < 0)
{
    printf("\n Socket creation error \n");
    return -1;
}

memset(&serv_addr, '0', sizeof(serv_addr));

serv_addr.sin_family = AF_INET;

// Clear this field; sin_zero is used for padding for the struct.
memset(&(serv_addr.sin_zero), 0, 8);
// Lookup host IP address.
struct hostent *hp = gethostbyname(hostname);
if (hp == NULL) {
    fprintf(stderr, "unknown host %s\n", hostname);
    exit(1);
}
serv_addr.sin_addr = *((struct in_addr *) hp->h_addr);

serv_addr.sin_port = htons(PORT);

if (connect(sock, (struct sockaddr *)&serv_addr, sizeof(serv_addr)) < 0)
{
    printf("\nConnection Failed \n");
    return -1;
}

//getting the user name
printf("please enter your name:");
scanf("%s",buffer);
send(sock , buffer , strlen(buffer) , 0 );

//initializing the game
read( sock , buffer, 1024);

//playing the game until the user enters e
do{
    printf("%s",buffer);
    memset(buffer,0,sizeof(buffer));
    scanf("%s",buffer);
    while(check_input(buffer)==0){
        printf("wrong input,try again:");
        memset(buffer,0,sizeof(buffer));
        scanf("%s",buffer);
    }
    send(sock , buffer , strlen(buffer) , 0 );//sending the input to the server
    printf("client:sent %s\n",buffer);
    read( sock , buffer, 1024);
    printf("client:received %s\n",buffer);
}while(is_over(buffer)==2);
return 0;

in server:
char player1Name[1024];
char player2Name[1024];
int p1_score = 0;
int p2_score = 0;
char buffer[1024] = {0};
int server_fd;
int server_fd2;
int player1_socket;
int player2_socket;
struct sockaddr_in player1;
struct sockaddr_in player2;
int opt = 1;
int opt2=1;
int player1len = sizeof(player1);
int player2len = sizeof(player2);

// Creating socket file descriptor for player 1
if ((server_fd = socket(AF_INET, SOCK_STREAM, 0)) == 0){
    perror("socket failed");
    exit(EXIT_FAILURE);
}

// Creating socket file descriptor for player 2
if ((server_fd2 = socket(AF_INET, SOCK_STREAM, 0)) == 0){
    perror("socket failed");
    exit(EXIT_FAILURE);
}

// making the first socket reusable
if (setsockopt(server_fd, SOL_SOCKET, SO_REUSEADDR | SO_REUSEPORT,&opt, sizeof(opt))){
    perror("setsockopt");
    exit(EXIT_FAILURE);
}

// making the second socket reusable
if (setsockopt(server_fd2, SOL_SOCKET, SO_REUSEADDR | SO_REUSEPORT,&opt2, sizeof(opt2))){
    perror("setsockopt");
    exit(EXIT_FAILURE);
}

//specifying the address of the first player
player1.sin_family = AF_INET;
player1.sin_addr.s_addr = INADDR_ANY;
player1.sin_port = htons( PORT1 );

//specifying the address of the second player
player2.sin_family = AF_INET;
player2.sin_addr.s_addr = INADDR_ANY;
player2.sin_port = htons( PORT2 );

// Forcefully attaching socket to the port 6000
if (bind(server_fd, (struct sockaddr *)&player1, sizeof(player1))<0){
    perror("bind failed");
    exit(EXIT_FAILURE);
}

if (listen(server_fd, 1) < 0){
    perror("listen");
    exit(EXIT_FAILURE);
}

if ((player1_socket = accept(server_fd, (struct sockaddr *)&player1,(socklen_t*)&player1len))<0){
    perror("accept");
    exit(EXIT_FAILURE);
}

get_playerName(player1Name,&player1_socket);

// Forcefully attaching socket to the port 6001
if (bind(server_fd2, (struct sockaddr *)&player2, sizeof(player2))<0){
    perror("bind failed");
    exit(EXIT_FAILURE);
}

if (listen(server_fd2, 1) < 0){
    perror("listen");
    exit(EXIT_FAILURE);
}

if ((player2_socket = accept(server_fd2, (struct sockaddr *)&player2,(socklen_t*)&player2len))<0){
    perror("accept");
    exit(EXIT_FAILURE);
}

get_playerName(player2Name,&player2_socket);
char input1;
char input2;
do{
        input1=get_nextMoves(player1Name,buffer,&player1_socket);
        printf("%c\n",input1);
        input2=get_nextMoves(player2Name,buffer,&player2_socket);
        printf("%c\n",input2);
        evaluate(input1,input2,&p1_score,&p2_score);
}while(input1!='e' && input2!='e');
strcpy(buffer,result(1,p1_score,p2_score));
send(player1_socket , buffer , strlen(buffer) , 0 );
strcpy(buffer,result(2,p1_score,p2_score));
send(player2_socket , buffer , strlen(buffer) , 0 );
return 0;

At this moment, i am running this code for both the player 1 and player 2 for the sake of experiment.When i run player 2 code, it just get stuck.
I was hoping for an error(EADDRINUSE more specifically).What is going on? how can i go further with my code?

A: In order for you to get an error, the server has to close the socket that's listening on port 6000 when the first client connects. Otherwise, your connection will succeed, but hang because the server doesn't call accept() a second time.
If the server does this, then the second client should get the error ECONNREFUSED, and it can try the second port.
if (connect(sock, (struct sockaddr *)&serv_addr, sizeof(serv_addr)) < 0)
{
    if (errno == ECONNREFUSED) {
        serv_addr.sin_port = htons(PORT + 1);
        if (connect(sock, (struct sockaddr *)&serv_addr, sizeof(serv_addr)) < 0)
        {
            printf("\nConnection Failed \n");
            return -1;
        }
    } else {
        printf("\nConnection Failed \n");
        return -1;
    }
}

Note, however, that this has a potential failure mode due to a timing window. If both clients try to connect at about the same time, the second client's connection request might arrive before the server has closed the listening socket, so the call to connect() will still succeed, even though the server never processes that connection.
The solution to that requires a more elaborate server design, where it accepts the second connection and returns a response saying that the port is already being used. Although if it could do this, you wouldn't need two ports in the first place.


60 Minutes also interviewed former Congressman Bruce Morrison who authored the H-1B visa legislation in 1990.
One H-1B worker agreed to be interviewed and admitted that most of the time the replaced American workers are more skilled than the foreign worker that takes their job. "I have to take all of their knowledge in –basically I have to steal it. That's my job description," the foreign worker said.
Mukesh Aghi, an executive at an India-based outsourcing company also acknowledged that the reason that American workers were losing these jobs was because it is cheaper to hire foreign workers.
You can watch the full report at CBSNews.com.


Main Blog > NeatoGeek > Why Did the Star Trek and Star Wars Universes Turn Out So Differently?
Why Did the Star Trek and Star Wars Universes Turn Out So Differently?
Tyler Cowen is an economist at George Mason University. Recently, he mused about why the settings of Star Trek and Star Wars are so different. There are advanced technologies in both--far beyond our own reality--but enormous differences in the politics, economies, and cultures between them.
1. The armed forces in Star Trek seem broadly representative of society. Compare Uhura, Chekhov, and Sulu to the Imperial Storm troopers.
2. Captains Kirk and Picard may be overly narcissistic, but they do not descend into true power madness, unlike various Sith leaders and corrupted Jedi Knights.
3. In Star Trek, any starship can lay waste to a planet, whereas in Star Wars there is a single, centralized Death Star and no way to oppose it, short of having the rebels try to blow it up. That seems to imply stronger checks and balances in the world of Star Trek. No single corrupt captain can easily take over the Federation, and so there are always opposing forces.
I think that the core difference is that Star Trek (at least in The Next Generation era) is highly utopian. The Federation at the center of the Star Trek story is prosperous, peaceful, and incorruptible. Factionalism, let alone tribalism, is rare. Hundreds of species with radically different cultures and even biological systems live together without serious disagreement. Material wants and injustice are almost unknown.
I love Star Trek and prefer it to Star Wars, but it's quite unrealistic. The reason why Star Wars is so savage and tragic compared to Star Trek is because real life is savage and tragic.
New Microbe Named After Star Wars' Midichlorians.
I would say the difference is that Star Wars is more reflective at its roots. It was a throwback to the old Saturday serials, with a world that borrowed from foreign historical movies. For all of its innovations, it is at its heart nostalgic.
Star Trek had the explicit mission of being speculative. The government on Earth was explicitly never mentioned, the details were supposed to be vague. Instead, it was to concentrate more on what life could be like, combined with some Gulliver's Travels reflections on the world the series was made in.
Wow. I tell you it's fiction, and that is me being RUDE????
Holy crap. Are we a little bit CONTROLLING here? Mother of god.
Have a nice life, asking questions about fiction as if it is real life.
I get your point, but that depended on the planet. The Queen of Naboo was an elected position, and there were term limits. Padme served her term as queen, but was elected (or maybe appointed) senator later. Alderaan had a "hereditary" royalty, but apparently genes didn't matter that much because Princess Leia was adopted.
"Why Did the Star Trek and Star Wars Universes Turn Out So Differently?"


Multiple Sclerosis (MS) is a frightening disease for many reasons. Primarily, humans are terrified of MS because we do not fully understand it. It is also problematic because it affects many people differently. It is even unpredictable in how it affects individuals on a daily basis.
Additionally, it continues to grow worse and becomes more difficult to manage as time passes. Multiple Sclerosis affects all types of people, and shows little mercy when it attacks. It can make life very difficult, sometimes impossible. The fatigue is often overwhelming. As well there are the weakness, balance and mobility issues. The simple tasks of any given day become impossible and sometimes even dangerous. It tries the loyalty and commitment of friends and family. It can truly put the promise of "for better or worse" and "in sickness and health" to the test.
When you're faced with a challenge like this, you have two choices, give up, or fight hard at every turn for any and everything that will make your life better. As humans, this is among the things we do best—fighting hard and long for what we believe is rightfully ours.
Humans often take the most important things in life for granted until they are gone. Sleep is a prime example of this. Over the course of a lifetime, the average person will spend 233,592 hours sleeping. Most people don't even think about it until getting even a few hours of sleep becomes very difficult.
That's where the problem begins for most people. They do not think about lack of sleep until it becomes an issue, people do not understand how quality of your sleep affects dramatically your quality of your life. The relationship between sleep quality and quality of life is particularly true in people who have disease challenges like Multiple Sclerosis (MS). Recently, Austrian researchers at the University of Vienna conducted a study on the effect of sleep on MS patients. They found that inadequate sleep quality was nearly twice as frequent in MS patients compared to people who did not have MS.
Sleep Hygiene And Sleep Debt: What is it?
Sleep Hygiene (SH) is the various practices one uses to achieve quality sleep. SH is essential in order for the brain to conduct its routine repairs from processing the day's events, in order to prepare for following day's events.
Sleep Debt (SD) occurs when you start getting less sleep than you need or poor quality sleep. It's like a financial debt that accrues over time from paying only a portion of a monthly bill.
SH and SD affects learning and memory. During sleep the brain organizes and files away all of the memories of the day. There is a huge amount of research showing that people who have better sleep hygiene perform better on memory and learning tasks. This is because the brain has had sufficient time and resources to better manage its constant rewiring.
Chronic poor sleep affects how your body processes and stores carbohydrates. It alters chemicals in the body that are known to affect appetite as well.
Obviously, Sleep Hygiene and Sleep Debt affect energy levels. When you don't get proper sleep you have less energy, you become irritable and impatient. While we all know this, the important thing to consider here is that as adults there are things that we must do in our days and things that we like to do. Since we are adults the things that we must do come first—that's the difference between being an adult and a child (again, typically and hopefully). Having less energy translates into having less fun. While you're putting the things you like to do on hold to honor your responsibilities and commitments, you're using up your energy supply.
Day in and day out, of not having the energy to do the things you like and want can lead to depression. There have been hundreds of studies confirming this. There's another key element to understand about poor sleep. Understanding it involves understanding what drives brain behavior, and how important sleep is to the brain. The brain views itself as the most important organ. So it behaves as if its needs are the most important. Thus, because sleep is vital to the brain, when your sleep is compromised, the brain processes it as a serious threat.
While this works fine for zebras, it can be problematic for modern day humans. The reason is even though the old part of our brain hasn't changed since we were cave people, human lifestyles and technology has changed a great deal. This is a problem for the old brain, because it processes all threat the same: "survive now ask questions later".
"Survive now, ask questions later," in terms of sleep debt, when translated in the old mammal brain, becomes, "go to sleep, right here, right now." That's fine if you're in a cave, or wandering the Serengeti. However, if you're driving on the freeway, or working as an Air Traffic Controller—the consequences are potentially devastating.
Sleep Hygiene and Sleep Dept are also bad for your heart. Since the brain processes a sleep dept as stress, it naturally responds with the standard human stress response. That is, it prepares for fight-or-flight. To do this it raises the blood pressure to increase blood flow and oxygen to the large limbs to prepare them to run or to do battle.
That's good in the short term. However, when your blood pressure is continuously increased, you develop "high blood-pressure", which is dangerous.
Lack of sleep and poor sleep can also cause your heart to beat irregularly, which is one of the leading causes of strokes.
You move the least when you sleep. At this time, gravity is the major force affecting your body, and particularly your spine. Good back support evenly distributes the stress on your spine while you sleep.
Most orthopedists agree that mattresses should adapt to the body's curves, while remaining flat. Having a pleasant spring action, good ventilation, and not being too warm or too cold is also important. Adapting to your body's natural curves, while remaining flat and having good spring action is the difference between a good mattress and a great mattress. This is because these factors seriously affect your spine during sleep. The spine is like the main highway in your body for the transmission of nerve impulses between the brain and the body. So the integrity of the spine will affect the integrity of the information flowing between your brain and body. As you know all too well, there is a big difference between a fast moving efficient highway and one that is not.
When you are lying on your side on a hard mattress, only your hip and your shoulder are supported and your spine is curving outward from the mattress. A soft mattress will cause your hip and shoulder to sink creating a sideways bending of your spine away from the mattress. When you are lying face up, your pelvis and upper back are in contact with the mattress, while the small of your back receives minimal support. This is not good spine support.
In a survey of orthopedic surgeons, 95% believed that mattresses played a part in the management of low-back pain, with 76% recommending a firm mattress. Additionally, most physicians who regularly treat lower back pain patients advise against the use of soft mattresses.
People who have chronic low-back pain are more sensitive to the firmness of mattresses than healthy people. People with MS are twice as likely to have lower back pain as people who do not have MS.
The bottom line is that more uniform body support reduces back pain and produces a more uniform sleep. More uniform sleep makes you healthier on multiple levels.
All of the research, the theory, and the physician opinions aside, let's just draw on some common sense. If you're about to bake something, it helps to have a good oven and the right pan. Having a good oven and the right pan won't make you a pastry chef; however, not having a good oven and the right pan can easily result in a flop. You sleep in a bed, so the first step of getting good sleep is getting a good bed. Therefore, having a bed that easy to get in and out of, that promotes uniform spine support is one of the fundamental currencies of good sleep for people enduring MS.
As we said in the beginning, enduring Multiple Sclerosis is an all out war, all day, every day. Humans are animals, and there are certain basic truths about animals. They need to eat, breath, drink water, and sleep. Everything else is want not need. When you are in a war, you have to pay particular attention to your basic needs. The better you attend to your basic needs, the better positioned you are to do battle. A hungry soldier, a thirsty soldier, or a soldier gasping for breath, is not the best soldier that he or she could be. Arguably a soldier who is weary because he or she has not slept well is perhaps the least effective soldier of all. When the battle is constant, as it is in MS, the preparation needs to be equally as consistent. Eat good food, drink pure water, breath deeply and most of all sleep well through the night. You'll find our best sleep solutions at the links these links, memory foam mattresses, latex mattresses and adjustable beds.


Cockney, Devonshire, Geordie, Liverpool, Yorkshire, London, Somerset, Welsh, Scottish, Southern Irish, Northern Irish.
Neutral Californian, Alabama, Boston, Southern, New York, Bronx, Boston and mid-Atlantic.
French, German, Spanish, Russian, Eastern European, Italian, Dutch and Swiss.
Australian, Jamaican, South African (Africaans), Kiwi New Zealand and Canadian.
Get that audition. Work on your accent today!
We will work on an audition script or a role that you have been cast in. Break down the accent or dialect and get you sounding perfect. I do not rest until you get the sounds and intonation 100%. Go for 1 hour first and then we can decide where to go from there.
If you are ready to book me, go to the bottom of the page and check my booking schedule. Click the SCHEDULE TIME WITH ME button. Check to see if there is a time that suits. If so then select the time and then pop back to the payment screen.
Feel free to book and then email me for a time.
The session is made up of 10 minutes each of preparation, recording and uploading the file. I will record the entire script with little or no intonation so that you can learn the words straight off the recording. I will record line by line leaving a gap between each line so that you can listen and repeat.
Once you have those lines down and want to take it to the next level, you can book in for another 30-minute session. This can be a phone call or Skype session and we can then iron out any difficulties you may be experiencing.
Accents available: English RP, Standard American, Southern American, Cockney, Liverpool, Scottish, Welsh, Irish, Devonshire/Somerset, German English, French English, and Russian/Eastern European.
If you'd like to hear a professional dialect coach say your lines in the accent for you, you can send us a copy of your lines, and we'll record them in the correct accent with some further explanations of pronunciation and terms. All prices are in NZ Dollars.
Payment is via PayPal or you can use your VISA or MasterCard. After payment you will be redirection to complete your booking details and upload your script.
If you are on set and require me to come and work with multiple actors please email me on sarah@actorsaccentcoach.com to discuss rates, location and accents. I'm available to travel anywhere in the world.
Accents available: English RP, Standard American, Southern American, Cockney, Liverpool, Scottish, Geordie, West Country, Birmingham, Lancashire, Manchester, South African, Indian, Jamaican, Welsh, Irish, Devonshire/Somerset, German English, French English, and Russian/Eastern European.


text:
module Main where
import qualified Core

main :: IO ()
main = Core.main

redpajama_set_name: RedPajamaGithub


Gpprefcl.dll file is part of Group Policy Preference Client product developed by Microsoft® Windows® Operating System. It is responsible for Microsoft Corporation functionality. This part is required for Group Policy Preference Client to function. If you are planning on replacing gpprefcl.dll with a new version make sure that you backup your old file. Replacing gpprefcl.dll file with a diffent version can cause Group Policy Preference Client to malfunction.


"You can connect direct to our account with SIP registration. As long as the poly coms can have the details amended to SIP extension and password for our service."
I am trying to figure out whether the Polycom 650 can do what they are asking. Can anyone tell me if this is possible with the 650? I tried looking at the user guide but didn't see anything about setting an SIP extension or password.
Please also check out QT 44011 from the Quick Tip section of our website. This has instructions for a basic SIP registration, configured from the phone's web interface. As per their knowledgebase, Gradwell should have provided pertinent SIP account information in your welcome email; this will be needed to complete the registration. This article on Gradwell's knowledgebase discusses settings for the IP 320; similar steps can be applied to other Polycom IP phones.


text:
Photo: Alexis Courcoux
2013 Solitaire du Figaro route announced
France's sixth largest city to host the start for the first time
Thursday December 6th 2012, Author: James Boyd, Location: France
The route for next year's 44th Solitaire du Figaro-Eric Bompard Cashemire has been part-announced at Paris Boat Show.
The organisers, Pen Duick, unveiled a course including in three French cities, two of whch have never previously been associated with the Figaro class' premier event.
Once again divided into four leg, La Solitaire in 2013 will start on 2 June from Bordeaux, the first time the city has hosted the race. The fleet will descend on the port up the Gironde River on 24 May where the population of France's sixth largest city will be able to take part in the 10 day long build-up to the start. On 1 June, the competitors leave Bordeaux's Port de la Lune and will take part in a parade of sail up the Gironde visiting Pauillac where the start will take place the following day.
Two legs will follow visiting Spain and Portugal before the race returns to France with the final leg running along the Channel from Roscoff on the northeast coast of Finistere. The rock-strewn Bay of Morlaix with its strong currents is very familiar to the majority of Figaro sailors and some of the greatest names in the class come from this area such as Nicolas Troussel.
The finish of next year's Solitaire du Figaro, on 26 June, will be further up the Channel in the Normandy port of Dieppe, which hosted the race for its 2009 and 2011 editions.
Jean-Marie Liot
Categories include: Chandelers , Marinas and berthing, Weather routing / forecasting, Finance

redpajama_set_name: RedPajamaCommonCrawl


text:
Peter Ligeglad paa Eventyr er en film instrueret af Carl Alstrup.

Referencer

Eksterne henvisninger

Film fra Danmark (administrationskategori)
Stumfilm fra Danmark
Danske film fra 1923

redpajama_set_name: RedPajamaWikipedia


It's a crisp and sparkling, sunny morning and in my Sigma office overlooking Plymouth's Royal William Yard, the water's looking particularly enticing. It's a gorgeous spot and silently I pat my husband and business partner on the back for his enlightened suggestion to buy premises here 13 years ago, when Cremyll Street was still something of an 'interesting' area. I can't help daydreaming, admiring the nautical view.
Right, I must gather my thoughts. Keeping up with news at the moment, let alone getting on top of my workload and the other activities I seem to get involved in, is beginning to make my head spin.
Like my inquisitive Springer spaniel retrieving the (headless) dead pigeon during this morning's walk, I can't seem to stop myself seeking out the national news, regional issues and local stories.
Then there's my Twitter feed and I seem to be on the receiving end of an unprecedented number of party political e-mails too - maybe I should just take a quick look? I've been tuning in to the car radio between appointments, checking in with the national TV news when I stumble home at night….
Each day, another political initiative or is it reconstituted news? My life seems to be punctuated with pithy soundbites and schmoozing Ministers during whistle-stop visits. Why, it's a miracle - we've morphed into the 'backbone of the economy'! I'm on a rollercoaster of financial facts and figures to assimilate, lots of what ifs, buts and maybes.
The FSB Business Manifesto for the 2015-2020 Government is glistening in the sunlight on my desk…am I up to speed on its contents? If I were a sponge, I could soak up all the salient points, but middle-aged memory loss is definitely taking its toll.
When did I start believing that everyone else knows the score? Didn't I start a business 23 years ago from my garden shed and haven't I developed it since using a combination of hard graft, reasonable intelligence, a supportive team and gut instinct?
I think about the real business issues I have on my plate – finding that elusive person to fill a skills gap in my company, weighing up the financial pros and cons of renovating this lovely old building, wondering if our latest pitch will be successful. The list goes on.
I relax. I know I will respond to whatever's thrown at me with the same flexibility, dogged determination and true grit my fellow SME colleagues must exhibit every day.
Lesley Shorrocks is Managing Director of a full service marketing and advertising agency sigma-marketing.co.uk and is Chair of Plymouth Federation of Businesses, representing 900 members.


In 2010, there were 12 new posts, growing the total archive of this blog to 47 posts. There were 42 pictures uploaded. That's about 4 pictures per month.
The busiest day of the year was March 30th. The most popular post that day was Smart Pills to Smart Scans: The future of Medical Devices.
The top referring sites in 2010 were facebook.com, bx.businessweek.com, linkedin.com.
Some visitors came searching, mostly for virtual, smart grid, social entrepreneurship, smartphone growth, and virtual world.
In the process of advising my two cousins who are in college now and third who is preparing to get into one, I have learned a lot. The one thing that has shocked me is the cost of getting the degree (Avg of $40,000/year, it costs $160,000). For those, whose parents can foot the bill, it may not seem like a big deal but for an average American, it is a lot. Assuming that you are able to earn $50 – $60k after graduation and you are able to pay $10,000/year, it will take 16 years to repay the principle (incl. the interest, it will be a life-long ordeal or worst-case need to file a Chapter 7 to get out of it).
Have you ever wondered what some of the Logos mean? Companies spend huge amounts of money and tons of hours in coming up with these Logos, which not only convey what the company is all about but also reinforce their mission, culture and guide their employees. More importantly Logos establish the brand for the company.
Did you notice there is a hidden arrow in the FedEx logo (between the E and the X)? Apparently it is a hidden sign symbolizing speed and precision of this courier office. Also it is a motivator for their employees to look ahead.
If you look at the center of this logo, you can see two people enjoying a Tostitos chips with a bowl of salsa. This logo conveys an idea of people connecting with each other and sharing.
I was pleasantly surprised and honored when I was recognized with an Award at the Analog Devices General Technical Conference, an annual internal conference where the entire ADI community comes together. The Award which was instituted this year recognizes innovation that enhances ADI products' value and most often results in customers selecting those products. Being among the three recipients in a $2 Billion company with approx 8000 employees definitely gives a feeling of some accomplishment.
Receiving the Award from Sam Fuller, CTO of Analog Devices Inc.


An image sensor may include a symmetrical imaging pixel with a floating diffusion region. The floating diffusion region may be formed in the center of the imaging pixel. A shallow p-well may be formed around the floating diffusion region. A transfer gate configured to transfer charge from a photodiode to the floating diffusion region may be ring-shaped with an opening that overlaps the floating diffusion region. Isolation regions including deep trench isolation and a p-well may surround the photodiode of the imaging pixel. A p-stripe may couple the shallow p-well around the floating diffusion region to the isolation regions. The floating diffusion regions of neighboring pixels may be coupled together with additional conductive layers to implement shared configurations.
Ma et al., "Jot Devices and the Quanta Image Sensor"; Proceeding of the IEEE International Electron Devices Meeting; Dec. 2014; pp. 10.1.1-10.1.4. cited by applicant .
Mamdy et al., "A low-noise, P-type, vertically-pinned and back-side-illuminated pixel structure for image sensor applications"; Proceeding of the IEEE International Image Sensor Workshop; Jun. 2015. cited by applicant .
Hynecek, U.S. Appl. No. 62/252,767, filed Nov. 9, 2015. cited by applicant .
Hong, U.S. Appl. No. 14/877,722, filed Oct. 7, 2015. cited by applicant .
Velichko et al., U.S. Appl. No. 14/836,599, filed Aug. 26, 2015. cited by applicant.
Attorney, Agent or Firm: Treyz Law Group, P.C. Guihan; Joseph F.
1. An imaging pixel comprising: a photodiode with a center; isolation regions that at least partially surround the photodiode; a floating diffusion region formed over the center of the photodiode; a transfer transistor configured to transfer charge from the photodiode to the floating diffusion region, wherein the transfer transistor comprises a transfer gate with an opening, and wherein the floating diffusion region is formed below the opening in the transfer gate; and a p-type doped region between the isolation regions and the floating diffusion region, wherein the p-type doped region comprises a p-type doped strip that extends over the photodiode and divides the photodiode into first and second symmetric halves.
2. The imaging pixel defined in claim 1, further comprising a shallow p-well formed around the floating diffusion region, wherein the p-type doped strip couples the isolation regions to the shallow p-well formed around the floating diffusion region.
3. The imaging pixel defined in claim 2, wherein the isolation regions comprise deep trench isolation.
4. The imaging pixel defined in claim 3, wherein the isolation regions further comprise a p-well.
5. The imaging pixel defined in claim 1, wherein the transfer gate is donut shaped.
6. The imaging pixel defined in claim 1, wherein the photodiode, the isolation regions, the floating diffusion region, and the p-type doped region between the isolation regions and the floating diffusion region are formed in a first substrate, the imaging pixel further comprising an interconnect layer that couples the floating diffusion region in the first substrate to a node in a second substrate.
7. The imaging pixel defined in claim 6, further comprising: a reset transistor formed in the second substrate that is coupled to the node; and a source follower transistor formed in the second substrate that is coupled to the node.
8. The imaging pixel defined in claim 1, further comprising a contact in the isolation regions that is coupled to ground.
9. The imaging pixel defined in claim 1, further comprising: a gate oxide formed underneath the transfer gate; and an additional p-type doped region, wherein the gate oxide is interposed between the transfer gate and the additional p-type doped region.
10. An imaging sensor comprising an array of imaging pixels that are formed in at least first and second substrates, each imaging pixel of the array of imaging pixels comprising: a photodiode formed in the first substrate; a floating diffusion region formed in the first substrate; a transfer transistor configured to transfer charge from the photodiode to the floating diffusion region, wherein the transfer transistor comprises a transfer gate with an opening that overlaps the floating diffusion region; a shallow p-well that surrounds the floating diffusion region; isolation regions; and a p-stripe that couples the shallow p-well that surrounds the floating diffusion region to the isolation regions, wherein the p-stripe of each imaging pixel extendalong a longitudinal axis that defines an axis of symmetry for that imaging pixel.
11. The imaging sensor defined in claim 10, wherein each imaging pixel further comprises: an interconnect layer that couples the first substrate to the second substrate.
12. The imaging sensor defined in claim 11, wherein each imaging pixel further comprises: a node formed in the second substrate, wherein the interconnect layer couples the floating diffusion region in the first substrate to the node in the second substrate.
13. The imaging sensor defined in claim 12, wherein each imaging pixel further comprises: a reset transistor formed in the second substrate that is coupled to the node; and a source follower transistor formed in the second substrate that is coupled to the node.
14. The imaging sensor defined in claim 10, wherein the isolation regions of each imaging pixel comprise deep trench isolation.
15. The imaging sensor defined in claim 14, wherein the isolation regions of each imaging pixel further comprise a p-well.
16. The imaging sensor defined in claim 15, wherein the p-stripe of each imaging pixel comprises a strip of p-type doped silicon that extends along the longitudinal axis.
17. The imaging sensor defined in claim 10, further comprising: an additional conductive layer that connects at least first and second floating diffusion regions of respective first and second imaging pixels.
18. The imaging sensor defined in claim 10, further comprising: an additional conductive layer that connects at least first, second, third, and fourth floating diffusion regions of respective first second, third, and fourth imaging pixels.
19. The imaging sensor defined in claim 18, wherein the first, second, third, and fourth imaging pixels are arranged in a 2.times.2 grid.
This relates generally to imaging systems and, more particularly, to imaging systems that have symmetrical pixels.
Modern electronic devices such as cellular telephones, cameras, and computers often use digital image sensors. Image sensors (sometimes referred to as imagers) may be formed from a two-dimensional array of image sensing pixels. Each pixel includes a photosensitive layer that receives incident photons (light) and converts the photons into electrical charge. Image sensors are sometimes designed to provide images to electronic devices using a Joint Photographic Experts Group (JPEG) format.
Conventional image sensors may include imaging pixels with floating diffusion regions. Charge generated in the photosensitive layers may be transferred to the floating diffusion regions for subsequent readout. In conventional imaging pixels, floating diffusion regions are typically formed in the corner of imaging pixels. However, this leads to asymmetries in the pixel, which can cause image artifacts and reduced versatility of the pixels. Additionally, in conventional image sensors it can be difficult to enclose photodiodes with deep trench isolation (DTI).
It would therefore be desirable to provide improved imaging pixels for image sensors.
FIG. 1 is a schematic diagram of an illustrative electronic device that may include an image sensor in accordance with an embodiment of the present invention.
FIG. 2 is a diagram of an illustrative pixel array and associated readout circuitry for reading out image signals from the pixel array in accordance with an embodiment of the present invention.
FIG. 3 is a perspective view of an image sensor with multiple substrates bonded together in accordance with an embodiment of the present invention.
FIG. 4 is a circuit diagram of an illustrative imaging pixel with multiple substrates in accordance with an embodiment of the present invention.
FIG. 5 is a top view of an illustrative symmetrical imaging pixel with a centrally located floating diffusion region in accordance with an embodiment of the present invention.
FIG. 6 is a cross-sectional side view of an illustrative imaging pixel taken along line 80 of FIG. 5 in accordance with an embodiment of the present invention.
FIG. 7 is a cross-sectional side view of an illustrative imaging pixel taken along line 82 of FIG. 5 in accordance with an embodiment of the present invention.
FIG. 8 is a cross-sectional side view of an illustrative imaging pixel with a pinning layer in accordance with an embodiment of the present invention.
FIG. 9 shows illustrative method steps for forming an imaging pixel of the type shown in FIGS. 5-7 in accordance with an embodiment of the present invention.
FIGS. 10A, 10B, and 10C show cross-sectional side views of an imaging pixel during the method steps of FIG. 9 in accordance with an embodiment of the present invention.
FIG. 11 is a top view of four illustrative imaging pixels that are arranged adjacent to each other in a 2.times.2 grid and that have a 2.times.1 shared configuration in accordance with an embodiment of the present invention.
FIG. 12 is a top view of four illustrative imaging pixels that are arranged adjacent to each other in a 2.times.2 grid and that have a 2.times.2 shared configuration in accordance with an embodiment of the present invention.
FIG. 13 is a top view of an illustrative imaging pixel with a floating diffusion region shifted towards the periphery of the pixel in accordance with an embodiment of the present invention.
FIG. 14 is a top view of an illustrative group of imaging pixels that share a reset gate in accordance with an embodiment of the present invention.
Embodiments of the present invention relate to image sensors with pixels that may be back side illuminated pixels. An illustrative electronic device that may include back side illuminated pixels is shown in FIG. 1. Electronic device 10 may be a digital camera, a computer, a cellular telephone, a medical device, or other electronic device. Camera module 12 (sometimes referred to as an imaging device) may include image sensor 16 and one or more lenses 14. During operation, lenses 14 focus light onto image sensor 16. Image sensor 16 includes photosensitive elements (e.g., pixels) that convert the light into digital data. Image sensors may have any number of pixels (e.g., hundreds, thousands, millions, or more). A typical image sensor may, for example, have millions of pixels (e.g., megapixels). As examples, image sensor 16 may include bias circuitry (e.g., source follower load circuits), sample and hold circuitry, correlated double sampling (CDS) circuitry, amplifier circuitry, analog-to-digital (ADC) converter circuitry, data output circuitry, memory (e.g., buffer circuitry), address circuitry, etc.
Still and video image data from image sensor 16 may be provided to processing circuitry 18. Processing circuitry 18 may be used to perform image processing functions such as automatic focusing functions, depth sensing, data formatting, adjusting white balance and exposure, implementing video image stabilization, face detection, etc.
Processing circuitry 18 may also be used to compress raw camera image files if desired (e.g., to Joint Photographic Experts Group or JPEG format). In a typical arrangement, which is sometimes referred to as a system on chip (SOC) arrangement, image sensor 16 and processing circuitry 18 are implemented on a common integrated circuit. The use of a single integrated circuit to implement image sensor 16 and processing circuitry 18 can help to reduce costs. This is, however, merely illustrative. If desired, image sensor 16 and processing circuitry 18 may be implemented using separate integrated circuits. Processing circuitry 18 may include microprocessors, microcontrollers, digital signal processors, application specific integrated circuits, or other processing circuits.
As shown in FIG. 2, image sensor 16 may include pixel array 20 containing image sensor pixels 22 arranged in rows and columns (sometimes referred to herein as image pixels or pixels) and control and processing circuitry 24 (which may include, for example, image signal processing circuitry). Array 20 may contain, for example, hundreds or thousands of rows and columns of image sensor pixels 22. Control circuitry 24 may be coupled to row control circuitry 26 and image readout circuitry 28 (sometimes referred to as column control circuitry, readout circuitry, processing circuitry, or column decoder circuitry).
Row control circuitry 26 may receive row addresses from control circuitry 24 and supply corresponding row control signals such as reset, row-select, charge transfer, dual conversion gain, and readout control signals to pixels 22 over row control paths 30. One or more conductive lines such as column lines 32 may be coupled to each column of pixels 22 in array 20. Column lines 32 may be used for reading out image signals from pixels 22 and for supplying bias signals (e.g., bias currents or bias voltages) to pixels 22. If desired, during pixel readout operations, a pixel row in array 20 may be selected using row control circuitry 26 and image signals generated by image pixels 22 in that pixel row can be read out along column lines 32.
Image readout circuitry 28 may receive image signals (e.g., analog pixel values generated by pixels 22) over column lines 32. Image readout circuitry 28 may include sample-and-hold circuitry for sampling and temporarily storing image signals read out from array 20, amplifier circuitry, analog-to-digital conversion (ADC) circuitry, bias circuitry, column memory, latch circuitry for selectively enabling or disabling the column circuitry, or other circuitry that is coupled to one or more columns of pixels in array 20 for operating pixels 22 and for reading out image signals from pixels 22. ADC circuitry in readout circuitry 28 may convert analog pixel values received from array 20 into corresponding digital pixel values (sometimes referred to as digital image data or digital pixel data). Image readout circuitry 28 may supply digital pixel data to control and processing circuitry 24 and/or processor 18 (FIG. 1) over path 25 for pixels in one or more pixel columns.
FIG. 3 shows an illustrative image sensor such as image sensor 16 in FIG. 1. Image sensor 16 may be formed with one or more substrate layers. The substrate layers may be layers of semiconductor material such as silicon. The substrate layers may be connected using metal interconnects. An example is shown in FIG. 3 in which substrates 42, 44, and 46 are used to form image sensor 16. Substrates 42, 44 and 46 may sometimes be referred to as chips or wafers. Upper chip 42 may contain photodiodes in pixel array 20. Charge transferring transistor gates may also be included in upper chip 42. However, to ensure that there is adequate room for the photodiodes in upper chip 42, much of the pixel circuitry for the pixels may be formed in middle chip 44.
Middle chip 44 may be bonded to upper chip 42 with an interconnect layer at every pixel. For example, pixel circuitry 34 in middle chip 44 may be bonded to a Floating Diffusion (FD) that is connected to a charge transfer transistor formed in upper chip 42. Bonding each pixel in upper chip 42 to corresponding pixel circuitry in middle chip 44 (e.g., floating diffusion to floating diffusion) may be referred to as hybrid bonding. Middle chip 44 and lower chip 46 may not be coupled with hybrid bonding. Only peripheral electrical contact pads 36 of each chip may be bonded together (e.g., chip-to-chip connections 38). Each chip in image sensor 16 may include relevant circuitry. The upper chip may contain photodiodes, floating diffusion nodes, and charge transferring transistor gates. The middle chip may include pixel circuitry (e.g., floating diffusion node, source follower transistor, reset transistor etc.). The bottom chip may include one or more of clock generating circuits, pixel addressing circuits, signal processing circuits such as the CDS circuits, analog to digital converter circuits, digital image processing circuits, and system interface circuits. The example of FIG. 3 where image sensor 16 has three substrates is merely illustrative. If desired, image sensor 16 may be formed from one, two, three, or more than three substrates.
FIG. 4 is a circuit diagram of an illustrative image pixel 22. As shown in FIG. 4, pixel 22 includes a photosensitive element such as photodiode 52. A positive power supply voltage Vaa may be supplied at positive power supply terminal 54. A second power supply voltage Vaa may be supplied at second power supply terminal 56. Incoming light may be collected by photodiode 52 after passing through a color filter structure. Photodiode 52 generates charge (e.g., electrons) in response to receiving impinging photons. The amount of charge that is collected by photodiode 52 depends on the intensity of the impinging light and the exposure duration (or integration time).
Before an image is acquired, reset control signal RG may be asserted. Asserting signal RG turns on reset transistor 58 and resets charge storage node 60 (sometimes referred to as floating diffusion region FD) to a voltage close to Vaa. Reset control signal RG may then be deasserted to turn off reset transistor 58.
Pixel 22 may include a transfer gate (transistor) 62. Transfer gate 62 may have a gate terminal that is controlled by transfer control signal TG. Transfer signal TG may be pulsed to transfer charge from photodiode 52 to charge storage region 61. Charge storage region 61 may be a floating diffusion region. Floating diffusion region 61 may be a doped semiconductor region (e.g., a region in a silicon substrate that is doped by ion implantation, impurity diffusion, or other doping process). Floating diffusion region 61 may be formed in an upper wafer (e.g., upper wafer 42 in FIG. 3) while floating diffusion region 60 may be formed in an additional wafer (e.g., middle wafer 44 in FIG. 3).
Floating diffusion regions 60 and 61 may be connected by interconnect layer 64. Interconnect layer 64 may be formed from a conductive material such as metal. In certain embodiments, the interconnect layer may include solder. The interconnect layer may also be a through silicon via (TSV). In certain cases, floating diffusion regions 60 and 61 may collectively be referred to as a charge storage region.
If desired, pixel 22 may have additional storage regions for temporarily storing charge transferred from photodiode 52. For example, an intermediate memory node such as a diffused diode and intermediate transfer gate or any other suitable in-pixel memory configuration may be located between transfer transistor 62 and source follower transistor 66. The configuration of FIG. 4 is merely illustrative.
Pixel 22 may include readout circuitry. The charge readout circuit may include row-select transistor 68 and source-follower transistor 66 (SF). Transistor 68 may have a gate that is controlled by row select signal RS. When signal RS is asserted, transistor 68 is turned on and a corresponding signal Vout (e.g. an output signal having a magnitude that is proportional to the amount of charge at floating diffusion node 60), is passed onto output path 70.
In a typical image pixel array configuration, there are numerous rows and columns of pixels 22. A column readout path such as output line 70 may be associated with each column of pixels 22 (e.g. each image pixel 22 in a column may be coupled to output line 70 through an associated row-select transistor 68). Signal RS may be asserted to read out signal Vout from a selected image pixel onto column readout path 70. Image data Vout may be fed to processing circuitry 18 for further processing. The circuitry of FIG. 4 is merely illustrative. If desired, pixel 22 may include other pixel circuitry.
In the illustrative example of FIG. 4, wafer 42 includes photodiode 52, transfer gate 62, and floating diffusion region 61. Wafer 44 includes reset transistor 58, floating diffusion region 60, source follower transistor 66, and row select transistor 68. This example is merely illustrative. If desired, the entire pixel circuit may be formed in a single wafer. In another embodiment, additional circuitry (e.g., reset transistor 58) may be formed in wafer 42. In general, the pixel circuit may be split between any number of wafers in any desired combination.
FIG. 5 is a top view of an illustrative symmetrical imaging pixel with a centrally located floating diffusion region. As shown, pixel 22 may include isolation regions that surround the pixel. The isolation regions may be formed from deep trench isolation 74 and p-well 72. Deep trench isolation structures 74 may be a p-type doped oxide (e.g., boron doped glass). In some embodiments, deep trench isolation structures 74 may instead be a p-type doped polysilicon (e.g., boron doped polysilicon). In other embodiments, deep trench isolation structures 74 may be a p-type doped polysilicon (e.g., boron doped polysilicon) having a liner (e.g., a phosphorous doped oxide liner). In yet other embodiments, deep trench isolation structures 74 may be a refractory metal (e.g., tungsten, molybdenum or other metals having a resistance to high heat, corrosion and wear) having a p-type oxide liner (e.g., boron doped oxide). P-well 72 may be formed from p-type doped silicon.
Pixel 22 may also include transfer gate 62. Transfer gate 62 may be configured to transfer charge from a photodiode to floating diffusion region 61. Floating diffusion region 61 may be coupled to interconnect layer 64. As shown in FIG. 5, floating diffusion region 61 may be formed in the center of pixel 22. This ensures that pixel 22 is symmetrical. Pixel 22 may also include a p-stripe 78 that runs through the pixel. P-stripe 78 may be a p-type doped region that is connected to the p-type isolation regions (e.g., p-well 72), which are grounded using ground contact 65.
FIG. 6 is a cross-sectional side view of pixel 22 taken along line 80 of FIG. 5. As shown in FIG. 6, floating diffusion region 61, transfer gate 62, and photodiode 52 may be formed in upper wafer 42. Isolation regions formed from deep trench isolation 74 and p-well 72 may surround photodiode 52. P-well 72 may be formed from shallow p-well 72-1 and deep p-well 72-2. Photodiode 52 may be formed form a shallow n-type photodiode region 52-2 and a deep n-type photodiode region 52-1. The photodiode may be a vertically pinned photodiode. During operation of the pixel, the doping profile of photodiode 52 may result in charge generated in the photodiode moving vertically towards the front side of the pixel (e.g., the charge may follow path 84). Then, when the transfer transistor is asserted, the charge may be transferred laterally to floating diffusion region 61.
Pixel 22 may include gate oxide 86 that separates transfer gate 62 from threshold adjustment layer 88. Threshold adjustment layer 88 may be a p-type doped layer. When transfer signal TG is pulsed to assert transfer transistor 62, at least part of threshold adjustment layer 88 may create a channel enabling charge to be transferred from photodiode 52 to floating diffusion region 61. Pixel 22 may also include a reflective layer. Reflective layer 90 may be formed from any desired material and may improve quantum efficiency in pixel 22. A region accumulated with holes 92 may be formed over photodiode 52.
If desired, photodiode 52 may be formed with a doping gradient from the back of the pixel to the front of the pixel. The back of the pixel may be the side of the pixel with the region accumulated with holes 92, while the front of the pixel may be the side of the pixel with transfer gate 62. The pixel may be illuminated by light that passes through the back side of the pixel. Pixel 22 may therefore be referred to as a back side illuminated pixel. Photodiode 52 may also have a doping gradient from the center of the pixel to the edges of the pixel. The doping gradients of photodiode 52 may act to ensure charge is fully transferred from photodiode 52 to floating diffusion 61 during charge transfer.
The use of deep trench isolation regions 74 in FIG. 6 is merely illustrative. If desired, pixel 22 may have isolation regions formed entirely from p-well 72. However, the deep trench isolation may enable a narrower p-well region and can therefore be used to decrease pixel size.
FIG. 7 is a cross-sectional side view of pixel 22 taken along line 82 of FIG. 5. The cross-section of pixel 22 along line 82 is similar to the cross-section of pixel 22 taken along line 80 shown in FIG. 6. However, FIG. 7 shows p-stripe 78. P-stripe 78 may be a thin strip of p-type doped silicon that connects the central p-well 72-1 that surrounds floating diffusion 61 to ground. As discussed in connection with FIG. 5, p-stripe 78 may be connected to the p-type isolation regions. Accordingly, p-stripe 78 may couple the central shallow p-well to the p-type isolation regions which are grounded with ground contact 65. This effectively grounds the shallow p-well formed in the center of the pixel.
As shown in FIGS. 6 and 7, transfer gate 62 may have an opening that serves to define floating diffusion region 61. Transfer gate 62 may sometimes be described as having a donut shape or a ring shape. The example in FIG. 5 where transfer gate 62 is a square with a square shaped central opening is merely illustrative. Transfer gate 62 may have any desired shape (e.g., rectangular, circular, etc.) and may have an opening with any desired shape (e.g., rectangular, circular, etc.).
Although not explicitly shown in FIGS. 6 and 7, pixel 22 may also include a microlens formed over the photodiode. The microlens may be formed on the back side of the imaging pixel. If desired, a color filter structure and/or planarization layer may be included between the microlens and the photodiode. The microlens may be circularly shaped or elliptically shaped if desired. Alternatively, a toroidal microlens may be used to focus light on the portions of the photodiode that are not overlapping the floating diffusion region. In yet another embodiment, multiple microlenses may be used to focus light on the single photodiode in pixel 22.
In an alternate embodiment, imaging pixel 22 may include a pinning layer to aid with suppressing dark current in the imaging pixel. FIG. 8 is a cross-sectional side view of an illustrative imaging pixel with a pinning layer. As shown in FIG. 8, pinning layer 89 may extend across the pixel from deep trench isolation 74 towards floating diffusion region 61. Pinning layer 89 may be a p-type doped layer and may be more heavily doped than threshold adjustment layer 88.
FIG. 9 shows illustrative method steps for forming an imaging pixel of the type shown in FIGS. 5-7. As shown, at step 802 a p-type epitaxial silicon layer may be formed on a substrate. The substrate may be a p+ substrate. Also at step 802, an oxide layer may be formed on the p-type epitaxial silicon layer. These features are also shown at step 802 in FIG. 10A, which shows a cross-sectional side view of pixel 22 during formation. As shown in FIG. 10A, p-type epitaxial silicon layer 900 may be formed on p+substrate layer 902. Additionally, oxide layer 904 may be formed on p-type epitaxial silicon layer 900.
At step 804, a deep n-type photodiode may be implanted into the p-type epitaxial silicon. As shown in FIG. 10A, deep n-type photodiode region 906 is formed in silicon layer 900. Next, at step 806, a shallow n-type photodiode may be implanted. As shown in FIG. 10A, shallow n-type photodiode region 908 may be formed such that shallow n-type photodiode region 908 and deep n-type photodiode region 906 form a continuous photodiode region. A thin layer of p-type epitaxial silicon 900 may remain adjacent to deep n-type photodiode 906. If desired, the shallow n-type photodiode and deep n-type photodiode may be formed using a blanket implant (e.g., an implant across the entire pixel array without using masking layer).
Next, deep trench isolation (DTI) may be formed at step 808. Deep trench isolation 910 (shown in FIG. 10A) may be formed via etching. For example, a masking layer may be formed over the pixel array in the areas that are not intended for deep trench isolation. The deep isolation regions may then be exposed to an etchant to form trenches. The trenches may subsequently be filled with an isolation material. If desired, oxide layer 904 may be stripped before the formation of deep trench isolation regions 910. In these embodiments, an additional oxide layer may be formed over the wafer after the deep trench isolation regions are formed. The additional oxide layer may be formed immediately after the deep trench isolation regions are formed or after another step in the method (e.g., after step 810, after step 812, after step 814, etc.).
At step 810, a threshold adjustment layer may be implanted into the wafer. The threshold adjustment layer may be a p-type doped layer. In FIG. 10B, threshold adjustment layer 912 is shown at step 810. Next, p-stripe 914 may be implanted at step 812. P-stripe 914 may be formed using photoresist 916. Photoresist 916 may act as a masking layer that ensures that the p-type implant that forms p-stripe 914 is only implanted in the central portion of the pixel. P-stripe 914 may form an elongated stripe of p-type doped silicon that extends across the pixel (as shown in FIG. 5, for example). After p-stripe 914 has been implanted into the pixel, photoresist 916 may be removed.
At step 814, a gate polysilicon layer such as gate polysilicon 918 in FIG. 10B may be formed. Gate polysilicon layer 918 may form the gate for a transfer transistor (e.g., transfer transistor 62 in FIGS. 4-7). Also at step 814, a hard mask may be formed over polysilicon layer 918. If desired, hard mask 920 may be formed to assist in the patterning process that forms openings 922 in polysilicon layer 918. Oxide layer 904 (which may have been formed at a previous step or during step 814) may act as a gate oxide layer. Next, a deep p-well region such as deep p-well 924 in FIG. 10B may be formed at step 816. Deep p-well 924 may be formed from a p-type implant. Photoresist 926 may be formed as a mask to ensure that the deep p-well is only implanted in peripheral openings in gate polysilicon layer 918 (e.g., openings 922-1). Photoresist 926 may cover an opening 922-2 in the central portion of polysilicon layer 918.
At step 818, shallow p-well regions may be formed. FIG. 10C shows shallow p-well regions 928 formed at step 818. Shallow p-well regions 928 may be formed such that shallow p-well regions 928 and deep p-well regions 924 form a continuous p-well region that surrounds deep trench isolation 910. Additionally, a shallow p-well region 928 may be formed in the central portion of the pixel around a portion of the p-stripe. Shallow p-well regions 928 may be formed using a blanket implant (i.e., without formation of an additional masking layer).
At step 820, an n-type lightly doped drain (LDD) region may be formed in the wafer. As shown in FIG. 10C, photoresist 930 may be deposited and patterned to cover the peripheral openings in the gate polysilicon layer. N-type lightly doped drain region 932 may then be implanted in the central opening in the gate polysilicon layer. Next, at step 822, photoresist 930 may be stripped. Hard mask layer 920 may also be stripped at this step. Additionally, a dielectric material 934 may be formed in the openings of gate polysilicon layer 918. The dielectric material may be etched to form sidewall spacers 934. After formation of the sidewall spacers, an additional photoresist layer 936 may be formed over the peripheral openings in the gate polysilicon layer. Subsequently, an n+ source/drain region 936 may be implanted in n-type lightly doped drain region 932. The n-type doped region 936 may act as the floating diffusion region for the pixel. Finally, at step 824, photoresist 936 may be stripped, as shown in FIG. 10C. This results in the final structure for the pixel.
If desired, a p+ source/drain region may be implanted in the corner of the pixel to form a ground contact (e.g., ground contact 65 in FIG. 5). To form this ground contact, an additional photoresist layer may be formed over the entirety of the pixel except for the portion where the ground contact will be located. The region may then be implanted with a p-type implant to form the ground contact. Additionally, substrate 902 may be thinned before, during, or after step 824. In certain embodiments, substrate 902 may be completely removed during the thinning process.
One advantage of the pixels shown in FIGS. 4-10 is that the pixels are easy to use with various shared pixel architectures. In certain applications, it may be desirable for neighboring pixels to share certain components (e.g., a floating diffusion region, a reset transistor, etc.). Because the pixels described herein are symmetrical, the pixels may be used in a variety of different shared architectures without having to change the structure of the pixel. For example, the pixels shown in FIGS. 5-7 may be arranged in a 2.times.1 shared configuration, as shown in FIG. 11. FIG. 11 shows four imaging pixels (22-1, 22-2, 22-3, and 22-4) that are arranged adjacent to each other in a 2.times.2 grid. Each pixel may include deep trench isolation 74, p-well 72, transfer gate 62, floating diffusion region 61, and interconnect layer 64. The floating diffusion regions of adjacent pixels 22-1 and 22-2 may be coupled together with conductive layer 94 that connects respective contacts 64 in each pixel together. Pixels 22-3 and 22-4 may similarly be coupled together to share a floating diffusion region. The pixels may also share ground contacts if desired. As shown in FIG. 11, ground contacts 65 may be positioned between multiple pixels so that multiple pixels share the ground contact.
FIG. 12 is a top view of illustrative image pixels with a 2.times.2 shared configuration. Because the structure of each pixel 22 is symmetrical, the structure of the pixels in FIG. 12 can remain the same as the structure of the pixels in FIG. 11 but have different sharing characteristics. As shown in FIG. 12, a conductive layer 94 can be connected to the contacts on the floating diffusion regions of pixels 22-1, 22-2, 22-3, and 22-4. Pixels 22-1, 22-2, 22-3, and 22-4 will therefore effectively share a floating diffusion region.
As shown in FIGS. 11 and 12, the symmetrical structure of pixels 22 enables pixels 22 to be very versatile. Arrays of pixels can be designed and manufactured so that the pixels have the structure shown in FIGS. 5-7. This allows the pixels to be designed with the same structure regardless of the sharing architecture, thus saving design time and costs, as well as to be manufactured in the same way, greatly saving on manufacturing costs. Optional additional conductive layers 94 may then be added to the array to form any level of shared architecture that is desired for the specific application of the image sensor. In contrast, in conventional pixel arrays the doping and design and layout of the pixels themselves must be designed specifically for the eventual shared configuration of the image sensor.
FIG. 13 is a top view of an illustrative imaging pixel. The pixel of FIG. 13 may be similar to the pixel shown in FIGS. 5-7. However, in FIG. 13 the floating diffusion region may be shifted towards the periphery of the pixel. This enables the p-well in the isolation regions (which is grounded by ground contact 65) of the pixel to cover the floating diffusion region. Because the p-well is already grounded, there is no need for the p-stripe that is included in the pixel of FIGS. 5-7. This saves on material and manufacturing costs while producing the pixel.
If desired, neighboring pixels on wafer 42 may share additional components in order to improve certain aspects of pixel performance such as floating diffusion dark current. For example, FIG. 14 is a top view of an illustrative group of imaging pixels that share a reset transistor. Four imaging pixels may each have respective transfer gates (62-1, 62-2, 62-3, and 62-4) that are coupled to respective floating diffusion regions (61-1, 61-2, 61-3, and 61-4). Each floating diffusion region may be coupled to a central reset gate 58 with respective n-type lightly doped drain (nLLD) regions. A drain region may be enclosed by the reset gate 58.
In various embodiments of the invention, an imaging pixel may include a photodiode, isolation regions that at least partially surround the photodiode, a floating diffusion region, a transfer transistor configure to transfer charge from the photodiode to the floating diffusion region, and a p-type doped region between the isolation regions and the floating diffusion region. The transfer transistor may include a transfer gate with an opening, and the floating diffusion region is formed below the opening in the transfer gate.
The imaging pixel may also include a shallow p-well formed around the floating diffusion region. The p-type doped region may include a p-stripe that couples the isolation regions to the shallow p-well formed around the floating diffusion region. The isolation regions may include deep trench isolation. The isolation regions may also include a p-well. The transfer gate may be donut shaped. The photodiode, the isolation regions, the floating diffusion region, and the p-type doped region between the isolation regions and the floating diffusion region may be formed in a first substrate. The imaging pixel may also include an interconnect layer that couples the floating diffusion region in the first substrate to an additional floating diffusion region in a second substrate. The imaging pixel may also include a reset transistor formed in the second substrate that is coupled to the additional floating diffusion region and a source follower transistor formed in the second substrate that is coupled to the additional floating diffusion region. The imaging pixel may also include a contact in the isolation regions that is coupled to ground.
In various embodiments, an imaging sensor may include an array of imaging pixels that are formed in at least first and second substrates. Each imaging pixel of the array of imaging pixels may include a photodiode formed in the first substrate, a floating diffusion region formed in the first substrate, a transfer transistor configured to transfer charge from the photodiode to the floating diffusion region, a shallow p-well that surrounds the floating diffusion region, isolation regions, and a p-stripe that couples the shallow p-well that surrounds the floating diffusion region to the isolation regions. The transfer transistor may include a transfer gate with an opening that overlaps the floating diffusion region.
Each imaging pixel may also include an interconnect layer that couples the first substrate to the second substrate and an additional floating diffusion region formed in the second substrate. The interconnect layer may couple the floating diffusion region in the first substrate to the additional floating diffusion region in the second substrate. Each imaging pixel may also include a reset transistor formed in the second substrate that is coupled to the additional floating diffusion region, and a source follower transistor formed in the second substrate that is coupled to the additional floating diffusion region. The isolation regions of each imaging pixel may include deep trench isolation and/or a p-well. The p-stripe of each imaging pixel may include a strip of p-type doped silicon that extends across the imaging pixel.
The imaging sensor may also include an additional conductive layer that connects at least first and second floating diffusion regions of respective first and second imaging pixels. The imaging sensor may also include an additional conductive layer that connects at least first, second, third, and fourth floating diffusion regions of respective first second, third, and fourth imaging pixels. The first, second, third, and fourth imaging pixels may be arranged in a 2.times.2 grid.
In various embodiments, a method of forming an imaging pixel with a width may include forming a p-type epitaxial silicon layer on a substrate, implanting n-type dopants into the p-type epitaxial silicon layer to form a photodiode, forming deep trench isolation to surround the photodiode, implanting a p-stripe that runs across the width of the imaging pixel, forming a transfer gate polysilicon layer over the photodiode, and implanting additional n-type dopants to form a floating diffusion region. The imaging pixel may have first and second opposing sides, the deep trench isolation may be formed on the first and second opposing sides of the imaging pixel, and implanting the p-stripe that runs across the width of the imaging pixel may include implanting the p-stripe such that the p-stripe couples the deep trench isolation on the first side of the imaging pixel to the deep trench isolation on the second side of the imaging pixel.


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Carriera
Arrivò in finale agli Australian Championships nel 1933 ma ne uscì sconfitto da Jack Crawford. Fu, comunque, un buon doppista, capace di trionfare due volte nei tornei dello Slam.

Finali del Grande Slam

Perse (1)

Collegamenti esterni


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Testimony: K.W.H.B.
Name: K.W.H.B.
Location: Beit Ummar, West Bank
Accusation: Throwing stones
On 13 February 2019, a 15-year-old youth from Beit Ummar is arrested by Israeli soldiers at midnight after he said he would not comply with a summons. He was accused of throwing stones but released without charge 13 hours later.
I walked home at around midnight after visiting a friend. When I got home I went to my bedroom and was about to check my smart phone when I heard loud banging at the front door. I then heard military jeeps around our house.
My father asked me to answer the door so I went downstairs and my father followed me. I opened the door and the Israeli commander walked in with a group of soldiers. He asked me how I was and wanted to shake hands with me but I refused.
Then the commander and the soldiers went upstairs and went straight to my bedroom and took some of my clothes; my trousers, a T-shirt, a pair of boots and a baseball cap. I later realised the commander had a photograph of me wearing similar clothes.
The commander wanted to give me a summons to turn myself in but I told him I was not going to comply. He then told me he was going to arrest me.
I was then taken outside and the soldiers walked me a short distance. Along the way they kicked me and beat me with the back of their guns. Then I was blindfolded and tied to the front with 3 plastic ties: one on each wrist and another connecting the two. The ties were unbearably painful.
Then I was taken to the back of a troop carrier where I was dumped on the metal floor. Inside the troop carrier soldiers slapped me on the back of my head and kicked me.
The troop carrier drove to a place I think somewhere around Jerusalem, possibly a settlement or a military base, where a doctor was going to examine me, but then he refused to examine me because the soldiers did not allow him to remove the ties and the blindfold.
I was then taken outside and left in the troop carrier for a couple of hours after which I was driven to the police station in Etzion settlement for interrogation. At Etzion I waited in a room until around 10:00 a.m. when I was taken for interrogation.
The interrogator called me by my name and asked me how I was. He removed the ties and blindfold and told me I was causing him a lot of trouble, so much so that his hair was turning white. Then he accused me of throwing stones at soldiers during clashes in the village. I told him I had already spent time in prison for that charge.
Then I told the interrogator I wanted to speak to my lawyer and he allowed me to via phone. After I spoke to my lawyer she spoke to the interrogator and told him I had already been in prison for that charge. I could hear that she was agitated and her voice was assertive.
After to speaking to the lawyer the interrogator asked me whether I had a suspended sentence from the time I had spent in prison and I told him I did. I felt he wanted to lock me up in prison no matter what. Throughout the interrogation the interrogator did not say anything about my right to silence but my lawyer told me to remain silent when I spoke to her.
The interrogation lasted for about 10-15 minutes. In the end the interrogator showed me documents in Hebrew and asked me to sign them but I refused to sign. Then I was taken to another room where I remained until around 1:30 p.m.
At around 1:30 p.m. the interrogator came to the room, patted me on the back and told me to be sensible and not cause any more trouble, otherwise I was going to waste my life. He claimed I threw stones and Molotov cocktails in the area and told me to stop such acts. Then he told me I could go home.
I went home with people from my village who were at the police station who agreed to give me a lift home.
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Members of the American Sabbath Tract and Communication Council (TCC) will be meeting this weekend at the SDB Center in Janesville, Wis. We covet your prayers for travel safety and a productive time.
Of course no meeting would be complete without future planning! We look forward to the work the Lord has for us and pray His vision be revealed in a clear way during the meetings.


The building is really impressive, and after registration I wanted to meet also the other guys who came to the event. I saw a lot of volunteers working around the booth and immediately thought that co-hosting the conference with GNOME.Asia was a very good idea, because it made the event much bigger.
After the Welcome Speech and a short overview of GNOME 3.12 held by Tobias Mueller, it was the turn of Jaroslav's and Jiri's Fedora Keynote. There were a lot of people who weren't contributors, so talking about Fedora.next was not very easy for them, but I think they presented it the right way and I really enjoyed it.
Once the Keynotes finished I went to another room where Nitesh talked about Fedora Videos. The talk was interesting although I already saw his talk at FLOCK in 2013.
After Nitesh it was my turn, I talked about Fedora Websites, what the websites team does and how the sites work. I explained also the build process and Internationalization, trying to keep the discussion as easy as possible to involve also the non-contributors who were listening. At the end I talked about the changes due to Fedora.next and showed some screenshots of how the Fedora websites will probably look like. People seemed very impressed and I was somewhat happy they appreciated the work we are doing.
In the afternoon I listened to Aditya's talk about Ansible and Zamir Sun's brief introduction to firewalld. The last two talks I wanted to hear were in chinese, so I jumped from one to the others and finished with the lightning talks.
In the evening we went to a nice place near the University, therefore many young people were there and we had a lot of fun. The Steps Bar had probably the biggest pizza in Beijing, some nice Chicken Burgers and obviously....a lot of beer (the glass in the foto contains 3 liters)!!!
Evening was short, we had to catch the last subway, but I was also very tired.
The morning was all dedicated to two important talks, the first one about Systemd, the second about Computing, Freedom and Privacy. Lennart Poettering did a generic talk about what systemd is and added some practical examples, he also kept his talk easly to understand for everyone.
After a short break and some lightning talks it was the turn of Richard Stallman, it's always nice to hear him speaking about free software.
In the afternoon I helped Ankur during his GPG key signing workshop, as the half of the attendees hadn't even a key or were using other operating systems...we had a lot of fun during this session and it's true that a GPG key signing party is a cool social event.
Once finished we all went to the main room for the closing speech and the group foto. It was a big event because it was co-hosted, maybe it's a good idea to do the same also in the future, because not only organisators did a great work, but the whole event benefited from this.
After the closing of day 2 we went to the near Vision Hotel, where we had a great dinner. From noodles, to rice dishes, hotpot and Beijing duck, all you wanted to eat was there. It was really a very good ending dinner of one of the best FUDCons of the last years.
For me Beijing lasted another 2 days, I did some sightseeing in the next days and enjoyed the local meals and chinese friendliness. Hopefully I can return to Beijing soon, I liked it very much!
It happened all at the last moment, I decided to attend FUDCon APAC a lot after the official deadline, dropped an email to the organizers and as there were only a few days left before the event, I had to put together all my papers to obtain the visa for China.
I decided to stay in another hotel, still quite good but less expensive, because I would have been reimbursed only partially for the flight. The problem was...I was not able to find it! Obviously I tried to ask but people were not really able to help me. The decision to print the address of my hotel in chinese turned out a very wise thought. At the end, and after more than 2 hours, a nice chinese girl accompanied me to the hotel and gave me also her business card. She was my salvation!
After I checked in I had the whole day to discover this amazing city, so I took a shower and went to the center.
Distances are quite big and I had to learn this first, but chinese people are very helpful, and although they often are not able to understand, they try to help you in every situation.
I decided to visit the Lama Temple (Yonghe Gong) and it was quite impressive, it's not a very big place but I enjoyed this temple. The big buddha statue, 18 m high, is a must when you come to Beijing.
My first lunch in Beijing also was very curious, I discovered a small place were a lot of chinese people was eating, so it was a promising place. I asked for the menu and got it after seconds, but it was only in chinese...never mind I thought, and indeed a chinese guy who also spoke a bit of english asked if he could order for me and I let him do so.
What I got was a spicy soup and a good and cold Tsingtao beer, 25CYN were ok and after it I returned to the hotel, because I wanted to relax a bit before FUDPub.
The first social event also means the start of every FUDCon, so I moved to the 雕刻时光, (Sculpture in Time Cafè), where I met some of the other Fedora guys and GNOME folks.
Jiri, Jaroslav, Ankur, Alick, Nitesh, Somvannda were only a few, there was also Emily, who heads the GNOME stuff, Tobias from Germany and Lennart Poettering.
The evening was really good, we had pizza and rice with meat. Almost all of us wanted a beer, but unfortunately they had only a warm one...no problem, after FUDPub we took also a couple of well cooled beers in the hotel at 3CYN (!!!).
Subways in Beijing close at 23:00, so the evening was a bit short, but I was also very tired and I fell in the bed exhausted, looking forward to the first day of FUDCon APAC.
Last Saturday we held a Fedora 20 release party in Perugia (Italy). This time, I decided to use my own office space to host the party, even if the furniture is not 100% complete (release early!) so I could determine whether I can use it again (release often!) for other parties/courses.
This had pro and cons, but overall I am very happy with the results.
Since I was not really sure who would join me, I had ready a couple slide decks: the generic introduction to the project, and another one about Fedora.Next (based on the Flock slides from +Matthew Miller).
As I mostly expected, the Fedora.Next topic was where I spent most of the time: I received many questions and comments about the plan, and people looked very interested and eager to know more details (which unfortunately I had not, since everything is still in early stages).
However, I will probably redo it next week at the traditional Linux Night dinner the local LUG organizes monthly.
As usual, I would like to thank the Fedora Project for sponsoring the party, and everyone that joined me to celebrate another great Fedora release.
È un po' che non pubblico nulla sul blog, visto che di questi tempi la maggior parte delle mie farneticazioni su Linux e dintorni si sono spostate in Google+.
Mi fa quindi molto piacere tornare a scrivere per segnalare che il prossimo 18 Gennaio alle 16.30 faremo un bel party a Perugia per festeggiare il recente rilascio di Fedora 20.
Ovviamente, se avete qualche idea per un tema da trattare, accetto suggerimenti!
Per regolarmi sulla quantità di cibo/bevande per favore fatemi sapere, nei commenti oppure sulla pagina Google+ dell'evento, se pensate di partecipare.


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Find out what's On In Oxford with our comprehensive guide to getting out and about in this lively city.
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AE1 * Latitude: 46.645833 * Longitude: 7.543333 * Date/Time: 1986-06-30T00:00:00 * Elevation: 989.0 m * Location: Aegelsee, Switzerland * Device: Livingstone piston corer (LPC) * Comment: Core diameter: 4.8 cm. Raised bog with small lake.
This dataset was archived on 2010-05-11 from the EPD database.


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Ian Murray MP
'We never gave up hope': Edinburgh family celebrates as great-grandparents allowed to stay in UK
The elderly couple are originally from Iran, but they've lived in Edinburgh since the 1970s
Hilary MitchellEditor
The couple were all smiles when they heard the news (Image: PA)
A 'frail' Iranian couple whose family all live in the UK have won their battle against deportation.
Mozaffar Saberi, 83, and Rezvan Habibimarand, 73, have been granted leave to remain in the UK by the Home Office.
The great-grandparents' case was previously raised in the House of Commons and more than 127,000 people had signed an online petition calling for the couple to be allowed to stay in the UK.
Mr Saberi and Mrs Habibimarand bought a flat in Edinburgh in the late 1970s and have four children, 11 grandchildren and a great-grandchild who are all British citizens.
Concern for Edinburgh man missing from his home since last week
The couple spent time in the UK on visitor visas over the years but after visiting in November 2012 they made an application to remain on human rights grounds which was refused by the Home Office.
A second application was also refused and they had been appealing against the decision, with the case due to be heard later this month.
The couple's family and legal team previously spoke of the pair's distress at the prospect of being separated from their family who all live in Edinburgh.
The couple also look after their severely autistic grandson who is non-verbal in order to help their daughter, an NHS nurse who is a single mother.
More than 127,800 people had signed a petition on change.org calling on the Home Office to allow the couple to stay in the UK and they have now been given leave to remain.
This West Lothian woman makes beautiful cribs for premature 'angel babies'- and she needs your help
A Home Office spokeswoman confirmed: "Following a review of the case, during which supplementary evidence was provided and considered, Mr Saberi and Mrs Habibimarand have been granted 30 months' leave to remain."
Writing on Facebook, their son Navid Saberi said: "You did it folks, you did it, thank you does not sound/feel enough but thank you. My parents will not be deported, just received the confirmation.
"Thank you for all your efforts, likes, shares and signatures."
He continued: "I should thank John Vassiliou, our solicitor, and his team who stuck with us in the last six years and never gave up hope and kept us motivated.
"In addition, I would like to thank our MP Ian Murray who worked incredibly hard, raising the issue in the House of Commons and in the Council of Europe. He has been amazing.
"Many thanks also go to the Scottish Minister for Europe, Migration and International Development Ben Macpherson MSP and regional MSPs Alison Johnstone and Andy Wightman who all wrote letters on our behalf, and also to David Lammy MP and Diane Abbott MP for helping to raise the case's profile on social media."
Top news stories on Edinburgh Live
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Woman lost thousands in phone scam
Amazing dinosaur exhibition arrives
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Edinburgh City Centre
Food and DrinkThe five best coffee shops in Edinburgh, according to Tripadvisor
Looking for the best place to go for a wee cup of coffee in Edinburgh? Here are the top rated places to get your caffeine fix in the Scottish capital.


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Чайнат:

 Чайнат — провінція в центральній частині Таїланду.
 Чайнат — місто в Таїланді, столиця однойменної провінції.


My next installment of the "Where Are They Now" feature is on one of the BCHL's longest serving franchises – the Cowichan Valley Capitals.
This entry was posted in alumni, BCHL, Cowichan Valley by Brian Wiebe. Bookmark the permalink.