【産業上の利用分野】本発明は記憶装置に係り、特に半導体を用いた記憶装置に関するものである。 The present invention relates relates to a memory device, and more particularly to a storage device using a semiconductor.
等の記憶装置は、小型、軽量、低パワーで大きな記憶容量をもち、かつ高精度な記憶読出しを高速でできる点で、多方面の機器に使用されている。 Storage device etc., small size, light weight, has a large storage capacity at low power, and in that a high-precision memory read can be fast, and is used in the device of various fields.
【0003】また近年、フラッシュメモリの愛称で呼ばれる、プログラム可能、かつ情報が保持可能な記憶装置が注目されている。  In recent years, the nickname of the flash memory, programmable, and information is noted retainable storage device. この記憶装置は、集積度の点において、上記DRAMよりも、向上することが指摘されている。 The storage device, in terms of integration density, than the DRAM, it is pointed out that improved.
−Si層を介して、配線金属が接続されている。 Through the -Si layer, a wiring metal is connected. そして、a−Si層を高抵抗状態から低抵抗状態に変化させることにより記憶動作を行う。 Then, the store operation by changing the a-Si layer from a high resistance state to the low resistance state.
M等の半導体を用いた記憶装置は、以下に示す問題点を有している。 Storage device using a semiconductor of M etc., has the following problems.
D−ROMに比較して、ビットコストが高く、記憶媒体として使用できるまでには至っていない。 Compared to the D-ROM, high bit cost, it does not reach the to be used as a storage medium.
【0007】2.  2. 現状、研究開発レベルでも記憶容量は、256Mビットレベルで、画像をとり扱う情報量としては不十分である。 Currently, the storage capacity in research and development level, at 256M bit level, it is insufficient as the amount of information that deals with the image.
【0008】3.  3. DRAM、SRAMにおいて、情報を記憶しておく場合、電源投入が必要で、携帯用機器への応用は、難しい。 DRAM, if the SRAM, stores the information, required power up, application to portable equipment, difficult. 現状、このような用途へはバッテリー内蔵型となっている。 Status quo, and has a battery built-in type to such applications.
【0009】また、上記DRAM等よりも集積度の点で優れるフラッシュメモリについても、以下に示す問題点を有している。  As for the flash memory is excellent in terms of degree of integration than the DRAM, and has the following problems.
【0010】1.  1. フローティングゲートに電荷の書き込み、消去をFNトンネル電流もしくはホットエレクトロン注入等で行うために、電荷の出入を行う絶縁層の信頼性が使用回数とともに劣化する。 Writing charge on the floating gate, an erase in order to perform at FN tunnel current or hot electron injection or the like, the reliability of the insulating layer to deteriorate with use count to and out of charge.
約100μs〜10msと長く、記憶装置の使い勝手が悪い。 About 100μs~10ms a long, bad usability of the storage device.
【0012】3.  3. 上記FNトンネル電流は、上記絶縁層の膜質、膜厚に強く依存し、サンプル間各ビット間で適正な書き込み時間、消去時間がばらつく問題がある。 The FN tunnel current, the film quality of the insulating layer, strongly depends on the film thickness, the sample between the proper write time between each bit, there is a problem that erasing time varies. このため、現実には、チップ作製後、検査工程で複数のグループに分類選別を行い、それぞれに適したタイミングで動作させることを実行している。 Therefore, in reality, after the chip is manufactured, it performs classification sorted into a plurality of groups in the inspection process, running to operate at a timing suitable for each. これにより、検査工程の負荷は重く、コスト高をまねいている問題点を有している。 Thus, heavy load of the inspection process, has a problem that led to high cost.
【0013】4.  4. 大容量化にともない、上記フローティングゲート面積も減少する。 With capacity also reduces the floating gate area. これにより、フローティングゲート容量は比例して小さくなり、わずかなリーク電流でもフローティングゲート電位の変化が大きくなる。 Thus, the floating gate capacitance is reduced in proportion, the change in floating gate potential is increased even small leakage currents.
したがって所望の容量を確保するためにフローティングゲートの面積を縮小する限界が存在し、大容量化への律速要因となっている。 Therefore the limit for reducing the area of the floating gates is present in order to ensure the desired capacitance has become a rate-limiting factor to the capacity.
【0014】さらに、一度だけ書き込みが可能な上記のOT−PROMについても、書き込み後の状態が永久的に変化せず、安定化している点で優れているが、1ビットに1つづつa−Si層及び上記a−Si層と配線とのコンタクト領域が必要となる。 Furthermore, for the above OT-PROM can be written only once, the state after writing is not changed permanently, it is superior in that it stabilizes, one for one bit a- Si layer and a contact area between the a-Si layer and a wiring is required. 半導体プロセスにおいて、コンタクトホール形成は、ライン状パターンより難しく、仮に0.8μmルールプロセスを用いる場合でもコンタクトサイズは約2割増しの1μm 2レベルとなる。 In the semiconductor process, the contact hole formation is more difficult line pattern, if the contact size even when using a 0.8μm rule process becomes 1 [mu] m 2 level of about 2 premium. コンタクトホールに対して配線幅はさらに広くしなければならないため、1bit当りの面積が縮小できなくなり、これらの提案されているメモリでは、大容量化が困難になるという問題点がある。 Since the wiring width relative to the contact hole must more widely, can no longer shrink area per 1bit, in these proposed memory has a problem that a large capacity is difficult. 又、書き込み動作時に、上記a−Si層に大電流が流れるため、消費電力が高く、携帯用機器への適応が難しい等の問題点も有していた。 Moreover, during the write operation, a large current flows in the a-Si layer, the power consumption is high, also had problems such adaptation is difficult to portable devices.
書き込み、読出しスピードが早く、高信頼性、低消費電力が実現できる記憶装置を提案することにある。 Write, fast read speed, high reliability, is to provide a storage device that low power consumption can be realized.
【課題を解決するための手段】以上の目的は以下に示す装置により実現できる。 Means for Solving the Problems The above object can be achieved by the apparatus described below.
の電極との間の抵抗を高抵抗から低抵抗に変化させることにより情報の書き込みがなされることを特徴とする。 Wherein the writing of the resistance from the high-resistance information by changing the resistance between the electrodes is made.
【0018】本願第2の記憶装置は、上記第1の記憶装置において、前記抵抗値の変化を第2の電極に印加する電圧により行うことを特徴とする。 The second aspect of the storage device, in the first storage device, and performs the voltage applied changes in the resistance value to the second electrode.
番目の第3又は第2の半導体領域とが電気的に接続されていることを特徴とする。 And th third or second semiconductor region is characterized by being electrically connected.
【0020】本願第4の記憶装置は、上記第1の記憶装置において、前記記憶装置を複数個有し、該複数個の記憶装置の第2の半導体領域どうし及び第3の半導体領域どうしを互いに接続したことを特徴とする。 The fourth aspect of the memory device, in the first storage device includes a plurality of said storage device, each other second semiconductor regions each other and the third semiconductor region to each other of the plurality of storage devices characterized in that the connection.
【0021】本願第5の記憶装置は、上記第1の記憶装置において、前記基板は絶縁層上にSi層を有する基板であることを特徴とする。  The present fifth storage device, in the first storage device, the substrate is characterized by a substrate having a Si layer on an insulating layer.
配列の一方向について各第2の電極を共通に接続した配線を設け、該配線に直交する方向に設けられた前記記憶装置の第1の半導体領域を共通に接続し、かつ各配列の第1の半導体領域を電気的に分離した構造としたことを特徴とする。 The wiring to connect each second electrode to the common one direction of the array is provided, the first of the first semiconductor region is connected to a common, and each array of the storage device provided in a direction perpendicular to the wiring characterized in that a semiconductor region and an electrically isolated structure.
【0023】本願第7の記憶装置は、上記第1の記憶装置において、前記第1の電極が第1、第2、第3の半導体領域を有する半導体領域と対向する面積が、第2の電極が第1の電極と対向する面積より大きいことを特徴とする。  The present seventh storage device in the first storage device, wherein the first electrode and the first, second, area facing the semiconductor regions having a third semiconductor region, the second electrode There being larger than an area facing the first electrode.
【0024】本願第8の記憶装置は、上記第1の記憶装置において、前記第1の電極は、前記第1の半導体領域をはさみ、2つの対向部分を少なくとも有することを特徴とする。 The application of the eighth storage device in the first storage device, said first electrode, said first semiconductor region scissors, and having at least two opposing parts.
【0025】本願第9の記憶装置は、上記第1の記憶装置において、前記第1の電極が多結晶Siを含む材料からなることを特徴とする。 The present ninth storage device in the first storage device, wherein the first electrode is made of a material containing polycrystalline Si.
【0026】本願第10の記憶装置は、上記第1の記憶装置において、前記第1、第2、第3の半導体領域を含む半導体領域と前記第1の電極との間の絶縁層がSiとNとOとからなる膜から構成されていることを特徴とする。 The present tenth storage device, in the first storage device, the first, second, insulating layer between the semiconductor region comprising a third semiconductor region first electrode and the Si characterized in that it is composed of a film consisting of N and O.
【0027】本願第11の記憶装置は、上記第1の記憶装置において、前記記憶装置の一部に、それ以外の構造の記憶装置を有することを特徴とする。 The application 11 of the storage device, in the first storage device, a portion of the storage device, characterized by having a storage device of the other structure.
【0028】本願第12の記憶装置は、上記第1の記憶装置において、前記記憶装置の周辺回路がCMOS回路により構成されることを特徴とする。 The application 12 of the storage device, in the first storage device, a peripheral circuit of the memory device is characterized in that it is constituted by a CMOS circuit.
【0029】本願第13の記憶装置は、上記第1の記憶装置において、前記記憶装置はカードに実装されたものであることを特徴とする。 The application 13 of the storage device, in the first storage device, wherein the storage device is one that is mounted on the card.
の電極と第2の電極と間の抵抗値を高抵抗状態から低抵抗状態に変化させる領域を設けたことを特徴とする。 Wherein the electrodes and the resistance between the second electrode from the high resistance state to the provision of the region to be changed to the low resistance state.
【0031】本願第15の記憶装置は、上記第1の記憶装置において、前記憶装置を複数個有し、情報を書き込む記憶装置では前記第1の半導体領域を所望の電源と接続し、情報を書き込まない記憶装置では前記第1の半導体領域をフローティング状態としたことを特徴とする。 The present fifteenth memory device, in the first storage device includes a plurality of pre-storage device, the storage device writes information to connect the first semiconductor region and the desired power, the information It is a storage device that is not written, characterized in that said first semiconductor region in a floating state.
よりも大きくしたことを特徴とする。 Characterized in that greater than.
【0033】本願第17の記憶装置は、上記第8の記憶装置において、前記第1の半導体領域の不純物濃度より高い半導体領域が前記第1の半導体領域と接して設けられていることを特徴とする。 The application storage device of the seventeenth, and characterized in that the memory device of the eighth, higher semiconductor region than the impurity concentration of said first semiconductor region is provided in contact with the first semiconductor region to.
【0034】本願第18の記憶装置は、上記第11の記憶装置において、書き込みデータを前記記憶装置及び前記それ以外の構造の記憶装置に書き込み、両者の記憶装置から該書き込みデータを読出し、両者の読出し結果を照合することを特徴とする。 The application 18 of the storage device, in the storage device of the eleventh, writes write data in the storage device and the storage device of the other structures, from both the memory device reads out the write data, both characterized by collating the read result.
【0035】本願第19の記憶装置は、上記第12の記憶装置において、前記周辺回路の少なくとも一部に、フローティングゲートを介して複数のゲート電極を有する回路が設けられていることを特徴とする。 The application 19 of the storage device, the storage device of the first 12, at least a portion of said peripheral circuit, wherein the circuit having a plurality of gate electrodes via the floating gate is provided .
【0036】本願第20の記憶装置は、上記第13の記憶装置において、前記カードに読出し専用記憶装置を設けたことを特徴とする。 The application twentieth storage device, the storage device of the first 13, characterized in that a read-only memory in the card.
【0037】本願第21の記憶装置は、上記第13の記憶装置において、前記カードに、発光素子及び受光素子を設けたことを特徴とする。 The application 21 of the storage device, the storage device of the first 13, the card, characterized in that a light-emitting element and a light receiving element.
【数2】 [Number 2] となることを特徴とする。 Characterized in that it comprises a.
【0040】本願第23の記憶装置は、上記第18の記憶装置において、前記照合結果を書き込む領域を前記記憶装置に設けたことを特徴とする。 The application storage device of the 23, in the memory device of the eighteenth, characterized in that a region for writing the verification result to the storage device.
2,33,34,41,42,43,44はメモリセルで本実施例では説明上4×4セル構造の場合を示している(なお、メモリセルの詳細な構造については後述する。)。 2,33,34,41,42,43,44 In this embodiment the memory cell shows the case of a description on 4 × 4 cell structure (will be described later in detail the structure of a memory cell.).
【数3】 [Number 3] を意味するものとし、以下同様に記する。 Shall mean a, similarly to the serial below.
【0044】次に本記憶装置の動作について説明する。  Next will be described the operation of the storage device.
Sを高レベルから低レベルへ入力してチップ内に列アドレスを取り込む。 Enter the S from the high level to the low level capturing column address in the chip. 次に行アドレスを確定した後、26に示す ̄RASを高レベルから低レベルに入力してチップ内に行アドレスを取り込む。 Then after determining the row address, fetches a row address into the chip by entering ¯RAS shown in 26 from the high level to the low level. これにより、アドレスのピン数を半減できる。 This allows half the number of pins of the address. 28に示す ̄WE信号が高レベルか低レベルかによりチップが読出し状態か書き込み状態かを決定する。 ¯WE signal shown in 28 chip by either high level or low level to determine whether the read state or write state.
30に示すD OUT端子より有効な出力データが得られる。 Valid output data is obtained from the D OUT terminal shown in 30. 書き込みの場合、29に示すD IN端子からデータを書き込む。 For a write, write data from the D IN terminal shown in 29.
【0046】次に、書き込み動作について、図2に示すタイミングチャートを用い、詳細に説明する。 Next, the writing operation, using the timing chart shown in FIG. 2 will be described in detail. 本チップの電源電圧は3.3Vとし、低消費電力化を図った。 Supply voltage of the chip and 3.3V, tried to lower power consumption.
〜第4列のウエル電位はフローティング状態になる。 Well potential of to the fourth column in a floating state.
ND電位に固定される。 It is fixed to the ND potential.
のCG2に示す如く、ワード線電位をOVにもどす。 As shown in CG2 of the, return the word line potential to OV.
【0049】以上説明したように、本発明の記憶装置は、セルに設けられたトランジスタのゲート構造をフローティングゲートとコントロールゲートとの積層構造とし、コントロールゲートに印加するパルスによりフローティングゲートとコントロールゲートとの間の抵抗値を変化させる(低抵抗化する)ことにより書き込みを行う全く新規なものとなっている。  As described above, the storage device of the present invention, the gate structure of the transistor provided in the cell has a stacked structure of a floating gate and a control gate, a floating gate and a control gate by a pulse applied to the control gate is quite a novel perform writing by changing the resistance value between the (resistance reduction) that.
【0050】次に、本発明の読出し動作について図3に示すタイミングチャートを用いて説明する。 Next, it will be described with reference to a timing chart shown in FIG. 3 for the read operation of the present invention. 各セルを構成しているトランジスタはp型MOSFETとし、そのしきい値は−1.8Vとなっている。 Transistor constituting each cell is a p-type MOSFET, the threshold has a -1.8 V. 本実施例ではセル部をp型MOSFETとしたがn型でも良い事は言うまでもない。 Although cell unit is a p-type MOSFET of course also be possible in the n-type in this embodiment.
【0051】読出しを行う列は図1の第1列とし、その列において、セル21のみ書き込みが行われており、その他のセル11,31,41は、書き込まれていない状態とする。 The sequence of reading is the first column of Figure 1, in the column, only the cells 21 and writing is performed, other cells 11,31,41 is an unwritten state.
の場合、固定されるウエル電位は最低電位であることは言うまでもない。 For, it is needless to say the well potential is fixed is the lowest potential.
図3の36に示す如く高レベルのままとなり、書き込まれていることがわかる。 Remains at a high level as shown in 36 of FIG. 3, it can be seen that are written. 同様の操作をくり返すことによりセル31,41の出力は図2の37,38に示す如く低レベルで書き込まれていない。 The output of the cell 31 and 41 by repeating the same operation is not written at a low level as shown in 37 and 38 in FIG. 2.
【0054】読出し最終後、φ2,φ3,φ4パルスを高レベル、φ1,φ5パルスを低レベルにすることによりセルのコントロールゲートだけでなく、ソース、ドレイン、ウエルを0Vとした。  reading the last post, .phi.2, .phi.3, high level φ4 pulse, .phi.1, not only the control gate of the cell by the low level of φ5 pulse and the source, drain, and well as 0V. これによりフローティングゲート電位は安定に初期状態の0Vとなって誤動作を生むことが防止できた。 Thus the floating gate potential is prevented that produce a malfunction becomes 0V of stable initial state. すなわちスタンバイ時、ソースドレイン、コントロールゲート、ウエルはすべて0Vとなっており、フローティングゲートへのリークがわずかにあっても常に0Vに自動的にリセットされ、動作の安定化が図れる利点がある。 That standby has become all the source drain, control gate, wells 0V, always automatically reset to 0V even slightly in leakage to the floating gate, there is an advantage that stable operation can be achieved.
【数4】 [Number 4] となるようにすれば、より安定した書き込みをすることができる。 If so that it is possible to more stable writing.
X 1 ′断面、Y 1 Y 1 ′断面を図5(a),(b)に示し、図4と同一箇所に関しては、同一番号を記し、説明は省略する。 X 1 'section, Y 1 Y 1' 5 a cross-section (a), shows (b), the respect to the same portions as FIG. 4, denoted by the same numbers, and description thereof is omitted.
00Å形成して絶縁層を形成とした。 It was formed an insulating layer and 00Å formed.
書き込みパルス印加により、コントロールゲートとフローティングゲートとの間に所望の電圧が印加されることになる。 The writing pulse application, a desired voltage between the control gate and the floating gate is applied.
同一番号を記す。 It referred to the same number.
0 14 〜10 17 cm -3レベルのものを用いることができるが、分割すべきウエル間の幅、ウエルに形成される容量の点からすると10 16 cm -3レベルのものが望ましい。 0 14 can be used to 10 17 cm -3 level ones, but the width between to be resolved well, from the viewpoint of the capacitance formed in the well 10 16 cm -3 level it is desirable.
lySiに不純物ドープするためのイオン注入及びアニールを行った後、n型MOSFETのソースドレインとなるn +層65、p型MOSFETのソースドレインとなるp +層54をそれぞれ形成する。 After ion implantation and annealing for impurity doped lysI, to form a p + layer 54 serving as the source and drain to become n + layer 65, the source and the drain of the p-type MOSFET of the n-type MOSFET, respectively. 微細化を行った時のソースドレイン端での電界を緩和するため、それぞれ低温度を設けたLDD,GOLD構造にすることは好適である。 To reduce the electric field at the source drain end when subjected to refining, respectively LDD provided with a low temperature, it is preferable to GOLD structure.
〜50Åの化学的酸化膜を形成し、500℃〜600℃ Forming a ~50Å chemical oxide film, 500 ° C. to 600 ° C.
これに限定されず、n型ウエル、p型ウエルの2重ウエル構造のもの、又、分離部には、チャネルストップ層を設けるもの、トレンチ分離も場合により有効であることは言うまでもない。 Not limited thereto, those of the double well structure of the n-type well, p-type well, also, the separation unit, which provided a channel stop layer, it is needless to say that effective when also trench isolation.
層目のpolySi表面に酸素のイオン注入層を形成すると、酸素を含んだ欠陥層を有する酸化膜となり、さらに耐圧が制御性よく低下する。 When forming an ion implantation layer of oxygen polySi surface of the layer first becomes the oxide film having an oxygen or defect layer, further the breakdown voltage is lowered with high controllability. この場合は、化学的酸化膜でなく、熱酸化し、約100Åレベルの膜厚としても、所望の耐圧が確保でき、又、膜厚が厚くできる分容量が下げられる利点を有する。 In this case, rather than chemical oxide film, thermal oxidation, even a thickness of about 100Å level, the desired breakdown voltage can be ensured, also has the advantage that the minute volume is lowered the thickness can be thickened.
Nしないように基板のバイアスをコントロールしておけば良い。 It is sufficient to control the bias of the substrate so as not to N. セル部のトランジスタは、76に示す如く、それぞれ島状に分離されている。 Transistor of the cell portion, as shown in 76, are separated into an island shape.
【0065】これによりワード線にそった方向の分離幅73は、従来の選択酸化、もしくは変形選択酸化を用いたものよりも狭く形成でき、1bit当りの面積は、さらに縮小できる。  Thus the separation width direction along the word line 73, the conventional selective oxidation or narrower can be formed than those using a modified selective oxidation, the area per 1bit can further reduced. これによりチップサイズが小さく、低コスト、高歩留り化がさらに図れる。 Thus small chip size, low cost, high yield of more reduced.
【0066】又ウエル間は、完全に絶縁層により分離され、動作の安定化が図れた。  Also between wells is completely separated by the insulating layer, was Hakare the stable operation.
【0067】図7からわかるように、セル部のTFTのチャネル部76及びフローティングゲート56部は、縦に積層されているため、セル間との段差が大きくなってしまう。  As can be seen from Figure 7, the channel 76 and the floating gate 56 parts of the TFT of the cell portion, because it is vertically stacked, step between between cells is increased. そのために、セル間には平坦化用絶縁層74を設け、ワード線75は平坦に配置できる工夫がなされている。 Therefore, the planarizing insulating layer 74 provided between the cells, the word lines 75 have been made to devise capable placed flat.
bulk基板を使用する時に比べて、小さくなり、書き込み時に非書き込みビットでのコントロールゲートとフローティングゲートとの電圧が小さくなり、書き込み不良を起しにくく、構造プロセスのマージンが広大する利点を持っている。 Compared to when using bulk substrate becomes smaller, the voltage between the control gate and the floating gate of the non-write bit is reduced at the time of writing, hardly causes a writing error, has the advantage that the margin of the construction process is vast .
最も高いフローティングゲート57の上部を露出させる。 Exposing the highest top of the floating gate 57. 露出後、希フッ酸で、第1polySi表面の酸化膜を一担除去した後、化学的酸化もしくは低温熱酸化により、上記表面に薄い絶縁層を形成し、ワード線51を形成する。 After exposure, a dilute hydrofluoric acid, after the oxide film of the 1polySi surface is Ichi担 removed, by chemical oxidation or low-temperature thermal oxidation, to form a thin insulating layer on the surface to form a word line 51. これにより平坦化構造となり、上部68の金属配線のパターンサイズ縮小しても高歩留りのものが実現できた。 Thus becomes flattened structure, even if the pattern size reduction of the metal wiring of the upper 68 is of a high yield can be realized. (第3実施例)次に、本発明の第3実施例について、図9を用いて説明する。 (Third Embodiment) Next, a third embodiment of the present invention will be described with reference to FIG.
98,99は上記MOSFETのn型ウエル層、81はp型基板、82,83はn +埋め込み層、101はフローティングゲート表面に形成されたメタル層でたとえば、Ta系金属層(Ta,TaN)、102は、上記メタルを含む絶縁層である。 98,99 n-type well layer of the MOSFET, the p-type substrate 81, 82 and 83 n + buried layer, 101 is for example a metal layer formed on the floating gate surface, Ta-based metal layer (Ta, TaN) , 102 is an insulating layer including the metal. なお図9(b),(c)から明らかなように、フローティングゲート96,97はウエル層98,99をはさみ、対向部分を有している。 Note FIG. 9 (b), the as is clear from (c), the floating gates 96 and 97 of the well layer 98 and 99 scissors, has a facing portion.
【0071】本構造の第1、第2実施例に対する特徴は、フローティングゲート96,97の平面サイズが小さく形成され、事実上、1ビット当りのセル面積がさらに縮小化が図れ、高集積に適している点である。  A first aspect of the present structure, wherein for the second embodiment is formed planar size of the floating gate 96 and 97 is small, virtually Hakare is further reduction cell area per bit, suitable for high integration and the point has. この構造が実現できた理由は、図9の(b)に示す如く、セル部のトランジスタが立体的構造を有し、上記トランジスタの上部103だけでなく、側壁部104も利用することにより、フローティングゲート容量を大きくできた事により達成された。 The reason this structure can be realized, as shown in (b) of FIG. 9, the transistors of the cell unit has a three-dimensional structure, not only the upper portion 103 of the transistor, by side wall portion 104 is also utilized, floating it has been achieved by that was able to increase the gate capacitance.
【0072】本第3実施例の第2の特徴について以下説明する。  The second feature of the third embodiment will be described below.
【0073】本構造は、チャネル部98,99を平行に配置されたフローティングゲート96,97により制御するために、通常のbulk型FETと異なりSOI型の動作となる。  This structure, in order to control the floating gates 96 and 97 which are arranged in parallel with the channel portion 98, 99, the operation of the SOI type Unlike conventional bulk type FET. これにより、実効的移動度が高く、高速、読出し等が達成されるばかりでなく、トランジスタの微細化が進められた時に生じる短チャネル効果も抑制され、より小型化が容易に実現できる。 Thus, the effective mobility is high, fast, not only read and the like are achieved, the short channel effect that occurs when the miniaturization of transistors is advanced is suppressed, more compact can be easily realized. それは、両側ゲートで制御し、高電界が印加されにくく、ポテンシャルの制御ができる事による。 It controls at both sides of the gate, hardly a high electric field is applied, due to the ability to control the potential. よって、単純に平面サイズを小さくしたままフローティングゲート容量を大きくでき、微細化されるばかりでなく微細化に最適なトランジスタ構造であると言える。 Therefore, simply possible to increase the floating gate capacitance while reducing the planar size, it said to be ideal transistor structure finer as well be miniaturized.
【0074】又、SOI型トランジスタでの問題として、トランジスタがONからOFFにスイッチした直後、チャネル部に残留する少数キャリアによりOFFがおくれることが指摘されているが、本構造の場合、チャネル直下にn +層が設けられ、その少数キャリアの残留が防止できるため、さらに高速なメモリ動作が実現できる。  Also, a problem with SOI transistors, immediately after the transistor is switched to OFF from ON, but it is pointed out that delayed OFF by minority carriers remaining in the channel portion, in this structure, the channel immediately below the n + layer is provided, since the residual of the minority carriers can be prevented, can be realized even faster memory operations.
【0075】本発明の第3実施例の構造の第3の特徴は、フローティングゲート96,97のオーバーサイズでワード線91〜93のパターニングがなされている事である。  The third feature of the structure of a third embodiment of the present invention is that the patterning of the word lines 91 to 93 have been made in oversize floating gates 96 and 97. これにより、ワード線パターニング時にフローティングゲート表面がエッチングプラズマ等にさらされる事がなくなり、フローティングゲートとワード線との間の絶縁耐圧の信頼性がさらに向上した。 This eliminates the possible floating gate surface during the word line patterning is exposed to the etching plasma or the like, the reliability of the withstand voltage between the floating gate and the word line is further improved.
上記フローティングゲートの表面層に上記金属を含む良質な絶縁層をセルフアラインで形成した事による。 According to that the formation of the high-quality insulating layer including the metal on the surface layer of the floating gate in a self-alignment. 本発明のメモリ構造は、所望の耐圧たとえば、5Vで、確実にワード線とフローティングゲートとが、低抵抗化され、3Vでは確実に高抵抗状態が維持される必要がある。 Memory structure of the present invention, the desired breakdown voltage for example, in 5V, certainly where the word line and the floating gate is low resistance, it is necessary to ensure the 3V high-resistance state is maintained. 絶縁層を薄くして、所望の耐圧を得るように調整すると、リーク電流が流れ始めてしまうことが生じる。 By reducing the insulating layer, when adjusted to obtain a desired breakdown voltage, it occurs that a leakage current would begin to flow.
2層目のpolySi形成前に上記金属層を含む絶縁層を設けた。 Before polySi formation of the second layer is provided with an insulating layer comprising the metal layer. これにより所望の耐圧でしかも、リークの従来に比較して50%以上少ない良好な絶縁層が形成できた。 Thus Moreover a desired breakdown voltage, as compared to conventionally more than 50% less good insulating layer of the leak could be formed.
【0078】これにより、メモリのエラーレートはさらに少なくなり、高信頼、高安定なメモリが実現できた。  As a result, the error rate of the memory is even less, reliable, highly stable memory can be realized.
ulkSi基板上に形成した例を示したが、SOI基板でも同等の構造が形成でき、かつ、第2実施例で説明した如く、素子分離が容易となるため、図10〜図16の作製方法の説明は、SOI基板の場合とする。 Although the example of forming the ulkSi substrate, also can be formed equivalent structure SOI substrate, and, as described in the second embodiment, since it becomes easy isolation, the manufacturing method of FIGS. 10 16 description, the case of an SOI substrate. 又説明の簡約化を図るためにセルp型TFTのみとする。 The only the cell p-type TFT in order to simplification of the description.
05で、p型MOSFETを作製する領域に、n型埋め込み層となるn +層を形成する。 05, in a region to produce a p-type MOSFET, to form an n + layer serving as n-type buried layer. この形成にあたっては、106に示すようにイオン注入による方法、又、貼り合せSOIウエハを作る時点で、不純物をドープしておく方法等を用いることができる。 In this form, the method according to the ion implantation, as shown in 106, also at the time of making cemented SOI wafer, it is possible to use a method or the like to be doped with impurities. 上記n +層を形成するSi層の膜厚は、数1000Åと極力薄く形成することが望ましい。 The film thickness of the Si layer to form the n + layer is preferably a number 1000Å as thin as possible forms.
【0081】次に、図11に示す如く、n +層107上に、1μmのエピタキシャル膜108を成長させた。  Next, as shown in FIG. 11, on the n + layer 107 were grown epitaxial film 108 1 [mu] m. 成長にあたっては、n +層からの不純物のわき上がり、またはオートドープを防止するために、低温かつ高速の成膜が望ましい。 In the growth, in order to prevent the sides up or auto-doping, the impurity from the n + layer, the low-temperature and high-speed film formation is desirable. 又、エピタキシャル工程は、コスト高を生じるため、エピタキシャル膜108の濃度のいかんに応じて必要ない場合もあることは言うまでもない。 Further, an epitaxial process is to produce a cost, also it goes without saying that when there is no need according to the transfer of the concentration of the epitaxial film 108.
B抽画等もさらに微細パターニングには有効である。 B 抽画 like is effective for finer be patterned.
【0083】その後、図13に示す如く、109の表面に酸窒化膜110を形成した。  Thereafter, as shown in FIG. 13, to form an oxynitride film 110 on the surface 109.
金属を含むTaポリサイドができた。 I was able to Ta polycide, including metal.
【0085】次に図14の112に示す如く、フローティングゲートのパターニングを行い、そのレジストマスクを用いて、113に示すように、ボロンをイオン注入し、ソース、ドレインを形成する。  As shown below in 112 of FIG. 14, patterning is performed for a floating gate, using the resist mask, as shown in 113, boron is ion-implanted to form the source and drain.
cm、圧力30mtorr温度450℃で行った。 cm, it was carried out at a pressure of 30mtorr temperature 450 ℃.
SG等の層間絶縁層を設け、コンタクトホール、配線用メタル、パシベーション用絶縁層、パットのエッチングを行いチップを試作した。 An interlayer insulating layer of SG or the like is provided, contact holes, wiring metal, passivation insulation layer, was fabricated chips by etching the pad.
【0088】本説明では、フローティングゲート表面に金属層を積層する構造について行ったが、第1、第2実施例と同様にpolySi単層でpolySi上の酸化膜でも良い。  In the present description has been made on the structure of laminating a metal layer on the floating gate surface, first, it may be an oxide film on the second embodiment similarly to polySi with polySi monolayer.
は、各列に設けられたp型ウエル層で、各列間は分離されている。 It is a p-type well layer provided in each column, between the columns are separated.
並列書き込みできることも言うまでもない。 Parallel It is also needless to say that you can write.
25をOFFし、選択ワード線を2Vにする。 OFF the 25, to the selected word line to 2V. 書き込まれたセルは、実質ゲート バイアスは2Vとなり、チャネルはONし、ビット線はソース電位たとえば0Vになる。 The written cell, substantially gate bias be 2V, the channel is turned ON, the bit line becomes the source potential eg 0V. 一方、非書き込みセルはフローティングゲートとの間で容量分割をうけ、実質ゲートバイアスは1.2Vとなり、しきい値以下により、上記セルのトランジスタはOFF状態でビット線はV DDのままとなる。 On the other hand, the non-write cell undergoes capacitance division between the floating gate, substantially gate bias 1.2V, and the below the threshold, the bit line transistors of the cell is OFF state remains at V DD. これらのビット線の電位変化を第1実施例と同様センスアンプで読出す。 It reads the change in potential of the bit lines in the same sense amplifier in the first embodiment.
はX X is 4 X 4 ′断面図、図21はY 3 Y 3 ′断面図である。 4 X 4 'sectional view, FIG. 21 is Y 3 Y 3' is a cross-sectional view.
と接続されている。 And it is connected to the. 140〜143はフローティングゲートである。 140-143 is a floating gate.
9は2段目のCMOSインバータの出力で前記制御回路154に入力されている。 9 is input to the control circuit 154 by the output of the second-stage CMOS inverter. 170,171,172はワード線で、本発明のメモリセル部及びSRAMメモリ部に共通に配置されている。 170, 171 and 172 is a word line, are arranged in common to the memory cell portion and the SRAM memory unit of the present invention.
0に正しく書き込まれ正しく読出されているかをチェックすることができる。 0 written correctly been able to check whether it is correctly read.
【0096】153に示すEXOR回路は、フローティングゲートを介して多入力ゲートを有するCMOS回路であり、150のメモリ領域と同等の構造から作製でき、かつ、少ないトランジスタ数で高機能の処理が可能となる。  EXOR circuit shown in 153 is a CMOS circuit having multiple input gates via the floating gates, 150 memory can be manufactured region and the equivalent structures, and can be processed highly functional with a small number of transistors and Become. 本実施例では、EXOR論理演算を実行したが、フローティングゲートを介して、入力8ビット分の入力ゲートを設け、上述と同様CMOSインバータを構成すると、入力データの多数決論理が2コのトランジスタ(n型MOS及びp型MOS)で可能になる。 In this embodiment, performing the EXOR logic operation, via the floating gates, it provided the input gate of the input 8 bits, configuring the same manner as described above CMOS inverter, majority logic of the input data is 2 co transistors (n allowing the type MOS and p-type MOS). この多数決論理を用して、入力データ8ビットのパリティーと読出し8bitのパリティーチェックを行うことも可能である。 And use this majority logic, it is also possible to perform the parity check of the input data 8-bit parity and the read 8bit.
【0097】図22の動作説明をひきつづき説明する。  continue explaining the operation description of FIG. 22.
169の出力結果で誤動作が確認できた場合、150のメモリの次の列に上記SRAMデータを再度書き込む。 If the output result in malfunction of 169 was confirmed, writes again the SRAM data to the next row of 150 memory.
これにより書き込みエラー、読出しエラーを補正する動作が可能になった。 This enabled to operate to correct the writing error, read error.
【0098】又、データ列の少なくとも1bitを各列データの正誤判定ビットとして割りあてておき、読出し時に確認できるようにすることも行った。  Also, at least 1bit data sequence has been assigned as a right or wrong decision bits of each column data, it was also to be able to see at the time of reading.
【0099】又、図13の構成では、SRAMのメモリは、150のメモリの1列分のものになっているがこのサイズに限定される事なく、バッファメモリとするレベルまでメモリサイズを増やし、高速なランダムアクセス、書き込みもできる工夫も図れる。  Also, in the configuration of FIG. 13, the memory of the SRAM, without it has become that of one column of 150 memory is limited to the size, increase the memory size to a level that a buffer memory, high-speed random access, thereby also devised that can also write. 又、バッファメモリをSRAMを例に説明したが、DRAMやフラッシュメモリ等を同一チップ上に配置し上記動作を行っても良い事は言うまでもない。 Also it has been described a buffer memory SRAM as an example, be a DRAM or a flash memory may be performed positioned above operates on the same chip of course.
AM、フラッシュ等)を内蔵しており、高速なランダムアクセス・書き込みが実現する。 AM, has a built-in flash, etc.), high-speed random access and writing can be realized. (第6実施例)本発明の第6実施例は、本発明の記憶装置をパソコン等の外部記憶用カード(PCカード)に応用したものである。 Sixth embodiment of (Sixth Embodiment) The present invention is applied to an external memory card such as a personal computer storage device of the present invention (PC card).
【0101】次に、本発明の応用例について説明する。  Next described is an application example of the present invention.
図23は本発明をPCカードに応用したときのカードとシステムとの関係を示す図である。 Figure 23 is a diagram showing the relationship between the card and the system when the present invention is applied to a PC card.
これらの容量が多く動かせないものがでることがあった。 There was that thing that these capacity not move much comes out.
nformation−structure)つまりカードの種類や容量、カードの識別やコンフィギュレーション情報なども格納し、カードが、主体に挿入された時、図12に示す如くカード挿入の通知又、デバイスドライバーダウンロードの支持にしたがい、ダウンロードを実行する機能をそなえた。 nformation-structure) that is card type and capacity, also stored such as identification and configuration information of the card, the card, when inserted into principal, the notification of the card insertion as shown in FIG. 12 also, the supporting device driver download Therefore, it equipped with a function to perform the download.
それ以外はすべて197ボート上に設けられた制御回路186により実行する。 Otherwise executed by the control circuit 186 provided in every 197 on the boat.
をマトリックス状に配置しておき、AND回路とOR回路とを多数並べておき、マトリックスの交点の上記配線間を高抵抗状態から低抵抗状態にかえ、実質的に接続することにより、各ユーザーの使用目的により自由に論理を設定できるプログラマブル論理アレーを内蔵した記憶装置である。 The advance arranged in a matrix form, leave an array of a number of AND circuit and OR circuit, changing between the wiring intersections of the matrix from the high resistance state to the low resistance state, by substantially connection, the use of each user a storage device with a built-in programmable logic array that can configure a logical freely depending on the purpose. 配線間の低抵抗化の箇所は、マトリックス状に配置された配線に印加するバイアスにより実現できる。 Portions of low resistance between the wires can be realized by the bias applied to the wiring arranged in a matrix.
【0106】本プログラマブル論理アレーを記憶に内蔵することにより、ユーザーの仕様にあった動作がマスク変更なしに実現でき、低コスト、ユーザーへの給期短縮が図れる。  By integrating the storage of this programmable logic array, the operation that was in the user specifications can be realized without a mask change, low cost, supply period shorter to the user attained.
高速書き込み、読出し可能、低エラーレート、使用環境が広い、作製工程が短く、高歩留り、周辺回路として他方式の記憶装置、論理回路等を同一チップ上に集積できチップの高機能化が図れる、等の効果があり、一般的にコンピュータ用記憶装置のみならず、オーディオ用映像情報記憶媒体としても使用でき、現状市販されているオーディオテープ、ビデオテープ、CD−ROM等を以上の高性能特性をいかし置き換え使用することもできる。 Speed writing, readable, low error rate, is wide environment, short manufacturing steps, high yield, storage device of another type as peripheral circuits, thereby the high performance of the chip can be integrated on the same chip logic circuit, has the effect of an equal, generally not only computer storage device, it can be used as a video information storage medium for audio, audio tapes that are currently commercially available, video tapes, high performance characteristics described above the CD-ROM, etc. it is also possible to use replacement taking advantage.
X、コピー機からの出力を本発明の記憶装置から構成されるカードに書き込み、簡単に映像データが持ち運びできるシステムにも好適である。 X, the write to the card and a storage device of the present invention the output from the copier, easily video data is also suitable for systems that can carry.
【図1】本発明の第1実施例の等価回路図である。 1 is an equivalent circuit diagram of a first embodiment of the present invention.
【図2】本発明の第1実施例の書き込み動作のタイミングチャートである。 2 is a timing chart of the write operation of the first embodiment of the present invention.
【図3】本発明の第1実施例の読出し動作のタイミングチャートである。 3 is a timing chart of the read operation of the first embodiment of the present invention.
【図4】本発明の第1実施例のセル部の平面図である。 4 is a plan view of a cell unit of the first embodiment of the present invention.
【図5】(a),(b)は本発明の第1実施例のセル部の断面図である。  (a), a cross-sectional view of a cell unit of the first embodiment of (b) the present invention.
【図6】(a)〜(d)は本発明の第1実施例の作製方法を示す工程図である。 6 (a) ~ (d) are process diagrams showing a manufacturing method of the first embodiment of the present invention.
【図7】(a),(b)は本発明の第2実施例のセル部の断面図である。 7 (a), a cross-sectional view of a cell unit of Example 2 (b), the present invention.
【図8】(a)〜(c)は本発明の第2実施例の作製方法を示す工程図である。 8 (a) ~ (c) are process diagrams showing a manufacturing method of the second embodiment of the present invention.
【図9】(a)〜(c)は本発明の第3実施例のセル部の平面図と断面図である。 9 (a) ~ (c) is a plan view and a sectional view of a cell unit of the third embodiment of the present invention.
【図10】本発明の第3実施例の作製方法を示す工程図である。 Is a process diagram showing the manufacturing method of the third embodiment of the present invention; FIG.
【図11】本発明の第3実施例の作製方法を示す工程図である。 11 is a process diagram showing the manufacturing method of the third embodiment of the present invention.
【図12】本発明の第3実施例の作製方法を示す工程図である。 12 is a process diagram showing the manufacturing method of the third embodiment of the present invention.
【図13】本発明の第3実施例の作製方法を示す工程図である。 13 is a process diagram showing the manufacturing method of the third embodiment of the present invention.
【図14】本発明の第3実施例の作製方法を示す工程図である。 14 is a process diagram showing the manufacturing method of the third embodiment of the present invention.
【図15】本発明の第3実施例の作製方法を示す工程図である。 FIG. 15 is a process diagram showing the manufacturing method of the third embodiment of the present invention.
【図16】本発明の第3実施例の作製方法を示す工程図である。 FIG. 16 is a process diagram showing the manufacturing method of the third embodiment of the present invention.
【図17】本発明の第4実施例のセル部等価回路である。 17 is a cell portion equivalent circuit of the fourth embodiment of the present invention.
【図18】本発明の第4実施例のセル部の平面図である。 18 is a plan view of a cell portion of the fourth embodiment of the present invention.
【図19】本発明の第4実施例のセル部の断面図である。 19 is a cross-sectional view of a cell portion of the fourth embodiment of the present invention.
【図20】本発明の第4実施例のセル部の断面図である。 20 is a sectional view of a cell portion of the fourth embodiment of the present invention.
【図21】本発明の第4実施例のセル部の断面図である。 21 is a cross-sectional view of a cell portion of the fourth embodiment of the present invention.
【図22】本発明の第5実施例の等価回路である。 Figure 22 is an equivalent circuit of a fifth embodiment of the present invention.
【図23】本発明の第6実施例のPCカード応用時のシステムブロック図である。 FIG. 23 is a system block diagram of when a PC card applications of the sixth embodiment of the present invention.
【図24】本発明の第7実施例の記憶装置を示す図である。 Is a diagram showing the storage device of the seventh embodiment of FIG. 24 the present invention.
されることを特徴とする記憶装置。 Storage device characterized in that it is.
【請求項2】 請求項1記載の記憶装置において、前記抵抗値の変化を第2の電極に印加する電圧により行うことを特徴とする記憶装置。 2. A memory device according to claim 1, wherein the storage device and performs the voltage applied changes in the resistance value to the second electrode.
【請求項3】 請求項1記載の記憶装置において、前記記憶装置を複数個有し、該複数個の記憶装置のi番目の第2又は第3の半導体領域と、i+1番目の第3又は第2の半導体領域とが電気的に接続されていることを特徴とする記憶装置。 3. A storage device according to claim 1, further comprising a plurality of said storage device, and the i-th second or third semiconductor region of the plurality of storage devices, i + 1-th third or storage apparatus characterized by the second semiconductor region are electrically connected.
【請求項4】 請求項1記載の記憶装置において、前記記憶装置を複数個有し、該複数個の記憶装置の第2の半導体領域どうし及び第3の半導体領域どうしを互いに接続したことを特徴とする記憶装置。 4. A memory device according to claim 1, wherein a plurality of storage devices, and connected to the second semiconductor region of the plurality of storage devices each other and third semiconductor regions each other to each other to the storage device.
【請求項5】 請求項1記載の記憶装置において、前記基板は絶縁層上にSi層を有する基板であることを特徴とする記憶装置。 5. The memory device of claim 1, wherein the substrate is a storage device which is a substrate having an Si layer on an insulating layer.
【請求項6】 請求項1記載の記憶装置において、前記記憶装置をマトリックス状に配置し、配列の一方向について各第2の電極を共通に接続した配線を設け、該配線に直交する方向に設けられた前記記憶装置の第1の半導体領域を共通に接続し、かつ各配列の第1の半導体領域を電気的に分離した構造としたことを特徴とする記憶装置。 6. The memory device of claim 1, said storage device are arranged in a matrix, the wiring connecting the respective second electrodes to a common one direction of the array is provided, in the direction perpendicular to the wiring the first semiconductor region is connected to a common, and the storage device, wherein a first semiconductor region of each array was electrically isolated structure provided with the storage device.
【請求項7】 請求項1記載の記憶装置において、前記第1の電極が第1、第2、第3の半導体領域を有する半導体領域と対向する面積が、第2の電極が第1の電極と対向する面積より大きいことを特徴とする記憶装置。 7. A memory device according to claim 1, wherein the first electrode is a first, second, an area facing the semiconductor regions having a third semiconductor region, the second electrode and the first electrode storage device being greater than the area facing the.
【請求項8】 請求項1記載の記憶装置において、前記第1の電極は、前記第1の半導体領域をはさみ、2つの対向部分を少なくとも有することを特徴とする記憶装置。 8. A memory device according to claim 1, wherein the first electrode, the first semiconductor regions scissors, storage device, characterized in that it comprises at least two opposing parts.
【請求項9】 請求項1記載の記憶装置において、前記第1の電極が多結晶Siを含む材料からなることを特徴とする記憶装置。 9. The memory device of claim 1, a storage device, characterized in that said first electrode is made of a material containing polycrystalline Si.
【請求項10】 請求項1記載の記憶装置において、前記第1、第2、第3の半導体領域を含む半導体領域と前記第1の電極との間の絶縁層がSiとNとOとからなる膜から構成されていることを特徴とする記憶装置。 10. A memory device according to claim 1, wherein the first, and a second, insulating layer is Si, N, and O between the semiconductor region comprising a third semiconductor region first electrode storage apparatus characterized by being constituted of a film made.
【請求項11】 請求項1記載の記憶装置において、前記記憶装置の一部に、それ以外の構造の記憶装置を有することを特徴とする記憶装置。 11. A storage device according to claim 1, wherein, in a part of the storage device, the storage device characterized in that it comprises a storage device of the other structure.
【請求項12】 請求項1記載の記憶装置において、前記記憶装置の周辺回路がCMOS回路により構成されることを特徴とする記憶装置。 12. The memory device of claim 1, storage device peripheral circuit of the memory device is characterized in that it is constituted by a CMOS circuit.
【請求項13】 請求項1記載の記憶装置において、前記記憶装置はカードに実装されたものであることを特徴とする記憶装置。 13. The memory device according to claim 1, wherein the storage device is a storage device which is characterized in that which has been implemented on the card.
【請求項14】 請求項1記載の記憶装置において、前記第1の電極と前記第2の電極とをマトリックス状に配置し、該マトリックスの交差部の第1の電極と第2の電極と間の抵抗値を高抵抗状態から低抵抗状態に変化させる領域を設けたことを特徴とする記憶装置。 14. A memory device according to claim 1, wherein the first electrode and the second electrode are arranged in a matrix, between a first electrode and a second electrode intersections of the matrix memory device according to claim the resistance value from the high resistance state to the provision of the region to be changed to the low resistance state.
【請求項15】 請求項1記載の記憶装置において、前記記憶装置を複数個有し、情報を書き込む記憶装置では前記第1の半導体領域を所望の電源と接続し、情報を書き込まない記憶装置では前記第1の半導体領域をフローティング状態としたことを特徴とする記憶装置。 15. A storage device according to claim 1, further comprising a plurality of said storage device, said first semiconductor region is a storage device for writing information to connect to the desired power, a storage device that does not write the information storage device being characterized in that said first semiconductor region in a floating state.
【請求項16】 請求項2記載の記憶装置において、前記記憶装置に情報を書き込む時の第2の電極に印加する第1の電圧V 1を、前記記憶装置から情報を読出す時の第2の電極に印加する第2の電圧V 2よりも大きくしたことを特徴とする記憶装置。 16. A method according to claim 2 in storage device, wherein the storage device to a first voltage V 1 applied to the second electrode when writing information, the second time reads information from the storage device memory device characterized by being larger than the voltage V 2 second to be applied to the electrodes of the.
【請求項17】 請求項8記載の記憶装置において、前記第1の半導体領域の不純物濃度より高い半導体領域が前記第1の半導体領域と接して設けられていることを特徴とする記憶装置。 17. A memory device according to claim 8, memory device higher semiconductor region than the impurity concentration of said first semiconductor region, characterized in that it is provided in contact with the first semiconductor region.
書き込みデータを前記記憶装置及び前記それ以外の構造の記憶装置に書き込み、両者の記憶装置から該書き込みデータを読出し、両者の読出し結果を照合することを特徴とする記憶装置。 Write the write data in the storage device and the storage device of the other structure, reading the write data from both the storage device, and wherein the matching both the read result storage unit.
前記周辺回路の少なくとも一部に、フローティングゲートを介して複数のゲート電極を有する回路が設けられていることを特徴とする記憶装置。 At least a portion, a storage device, wherein the circuit is provided with a plurality of gate electrodes via the floating gate of the peripheral circuit.
前記カードに読出し専用記憶装置を設けたことを特徴とする記憶装置。 Storage device characterized by providing a read only memory in the card.
前記カードに、発光素子及び受光素子を設けたことを特徴とする記憶装置。 To the card, the storage device characterized by providing the light-emitting element and a light receiving element.
前記第1の電極と前記第2の電極との抵抗値が高抵抗状態から低抵抗状態になるときの第1の電極と第2の電極との間の電圧をV BDとし、前記第2及び第3の半導体領域を主電極領域、前記第1の半導体領域を制御電極領域、第1の電極を制御電極としたときに形成される絶縁ゲート型トランジスタのしきい値をV thとし、 前記第1の電極と第1、第2、第3の半導体領域との間に形成される容量をC The voltage between the first electrode and the second electrode when the resistance value between the second electrode and the first electrode is made of a high-resistance state to the low resistance state and V BD, the second and the main electrode region a third semiconductor region, said first semiconductor region a control electrode region, the threshold value of the insulated gate transistor is formed when the first electrode and the control electrode is V th, the first first electrode and the first, the capacitance formed between the second, third semiconductor regions C FGとし、第1の電極と第2の電極との間に形成される容量をC CGとした場合、 【数1】 And FG, if the capacitance formed between the first electrode and the second electrode and the C CG, Equation 1] となることを特徴とする記憶装置。 Storage device characterized by comprising a.
前記照合結果を書き込む領域を前記記憶装置に設けたことを特徴とする記憶装置。 Storage device characterized by providing an area for writing the verification result to the storage device.
IT1311314B1 (en) * 1999-12-14 2002-03-12 St Microelectronics Srl Method of reprogramming optimized for non-volatile memory cells, in particular of flash type EEPROM.


text:
City Commission v. State ex rel. Nichols, 75 N.M. 438, 405 P.2d 924 (1965)
Sept. 20, 1965 · Supreme Court of New Mexico · No. 7813
The CITY COMMISSION OF ALBUQUERQUE, New Mexico, and Archie Westfall, Sam Brown, Luther Heilman, Ralph Trigg and Emmanuel Schifani, Members of the City Commission, Plaintiffs in Error, v. STATE of New Mexico upon the relation of Homer P. NICHOLS, Defendant-In-Error, John McMullan, William M. Campbell, Jr., Jack Stahl, Don Weagley, Lillie Bailey, Peter F. McCanna, Theodore Van Soelen, I. T. Williams and Allen D. Herhold, Intervenors
The CITY COMMISSION OF ALBUQUERQUE, New Mexico, and Archie Westfall, Sam Brown, Luther Heilman, Ralph Trigg and Emmanuel Schifani, Members of the City Commission, Plaintiffs in Error, v. STATE of New Mexico upon the relation of Homer P. NICHOLS, Defendant-In-Error, John McMullan, William M. Campbell, Jr., Jack Stahl, Don Weagley, Lillie Bailey, Peter F. McCanna, Theodore Van Soelen, I. T. Williams and Allen D. Herhold, Intervenors.
Sept. 20, 1965.
*439Hannett, Hannett & Cornish, Frank L. Horan, Albuquerque, for plaintiffs in error.
Grantham, Spann & Sanchez, Albuquerque, for defendant in error.
CHAVEZ, Justice.
Writ of error was issued by this court directed to the Honorable John B. Mc-Manus, Jr., district judge of the second judicial district for Bernalillo County, New Mexico. The writ of error issued as the result of an order granting a peremptory writ of mandamus commanding that plaintiff s-in-error provide, within 30 days from January 18, 1965, for an election to permit the qualified voters of the city of Albuquerque to vote for or against the municipal *440ordinance, which provides for a If! per gallon tax on gasoline sold within said City, and to'make all necessary arrangements and provisions for the holding of said election as required by law.
The proceedings in the district court originated on January 22, 1965, with the filing of a petition by defendant-in-error Homer P. Nichols, hereinafter referred to as "Nichols," against plaintiffs-in-error, hereinafter referred to as the "City," praying for an alternative writ of mandamus. On said date an order was entered granting the alternative writ of mandamus and the writ issued, returnable on January 29, 1965. The alternative writ alleged that on January 18, 1965, there was filed with the City petitions signed by in excess of 24,500 qualified voters of Albuquerque, requesting an election to permit the qualified voters to vote for or against the ordinance which provided for said gasoline tax; that the petitions were in all respects proper and filed in accordance with the laws of New Mexico and the charter of the City; that the City, through its employees, publicly announced that any one wishing to vote "for" or "against" the ordinance would have until January 22, 1965, to file petitions for an election; and that petitioners who filed petitions on January 18, 1965, were relying, among other things, upon such representations.
The trial court, in its order granting the alternative writ of mandamus, directed the City to provide for an election within 30 days from January 18, 1965. The trial court concluded that, under the laws of New Mexico and the charter of the City, it became the clear duty of the City to call an election within 30 days from the date of the filing; that the City, at a meeting held January 19, 1965, refused to call an election; and that there was no speedy and adequate remedy at law whereby Nichols' rights and those of 24,500 voters, who signed the petitions, can be enforced.
On January 28, 1965, the City filed an "Answer to Petition for Alternative Writ of Mandamus," which was accepted by the court as a response to the alternative writ of mandamus. The answer admitted receiving certain petitions on January 18, 1965, and admitted the passage of the ordinance; admitted that the City refused to call an election and submit the matter to a vote, but denied that such refusal was unlawful or that they made any misrepresentations; alleged that the petitions for referendum do not contain the signatures of 20% of the qualified voters in the City; and that the petitions were not filed within the time provided by law.
On January 28, 1965, a motion to intervene was filed by John McMullan and others, to which was attached a complaint in intervention alleging that the petitions for referendum were not timely filed and that said petitions contained an insufficient number of signatures of qualified voters.
*441The trial court allowed the intervention and the complaint was filed.
At the close of Nichols' case, the City-moved to quash the writ on the ground that •the petitions were not timely filed, which motion was denied.
The trial court's findings of fact and conclusions of law appear in the order and peremptory writ of mandamus entered February 1, 1965, as follows:
"That Flomer P. Nichols, relator herein, is now and has been at all times material hereto a citizen and qualified voter of the City of Albuquerque, Bernalillo County, New Mexico, and is beneficially interested in the relief being sought herein; and,
"That the respondent City of Albuquerque is a municipal corporation existing under the laws of the State of New Mexico; the respondents Archie Westfall, Sam Brown, Luther Heilman, Ralph Trigg and Emmanuel Schifani are the duly elected and acting Commissioners of the said City; and
"That on January 18, 1965, there were filed with the respondent City Commission petitions signed by in ex- • cess of 24,500 presumed qualified voters of the City of Albuquerque, New Mexico, petitioning said Commission to provide for an election to permit the quali- . ified voters to vote for or against an Ordinance which provided for a gasoline tax of one cent (1^) per gallon-on gasoline sold within the municipality, a copy of said Ordinance being attached to the petition herein as 'Exhibit A' and adopted as a part hereof; and said petitions were in all respects presumed valid and timely filed in accordance with the statutes of the State of New Mexico in such cases made and provided, and in accordance with the charter of the City of Albuquerque; and
"That on or about the time the described Ordinance became effective, the respondent City Commission, by and through its duly appointed and acting employees and representatives, publicly announced to the citizens and qualified voters of the City of Albuquerque that anyone wishing to vote for or against the Ordinance would have until January 22, 1965, to file petitions for an election; and the petitioners, who filed the hereinabove described petitions on January 18, 1965, were relying, among other things, on the described representations so made by the respondents; and
"That under the laws of the State of New Mexico and the charter of the City of Albuquerque and upon the filing of the described petitions, it became the clear duty of the respondent City' Commission to call an election . within thirty (30) days from the date of filing; and ■ ;
*442"That notwithstanding the herein-before representation made by the respondent Commission as to the date o'f filing, and contrary to the laws of the Státe of New Mexico and to the charter of the City of Albuquerque, the respondent City Commission at a meeting held on January 19, 1965, refused to call an election and submit the matter to a vote of the people of the City of Albuquerque; and
"That there is no plain, speedy and adequate remedy in the ordinary course of the law whereby relator's rights and those of 24,500 voters, who signed the hereinbefore mentioned petitions, can be enforced; and
"WHEREAS, by Order of this Court duly issued and made it was ordered that a peremptory writ of mandamus issue to you, and each of you.
"THEREFORE, THE COURT COMMANDS you, and each of you, that you provide, within thirty (30) days from January 18, 1965, for an election to permit the qualified voters of the'City of Albuquerque, New Mexico, to vote for or against the municipal ordinance which provides for a one cent (lj!) per gallon tax on gasoline sold within said City, and that you make all arrangements and provisions for the holding of said election as are required by law."
Under their point I, the City contends that the peremptory and alternative writs of mandamus were improvidently issued because there was no clear legal duty incumbent upon them to perform that which was ordered, and that the court did not have jurisdiction to issue the writ. Subsection (a) under this point is that the petitions filed with the city clerk on January 18, 1965, were not filed within the time prescribed by the Albuquerque city charter and the laws applicable thereto.
The ordinance in question was adopted on December 15, 1964, and § 11 thereof declares it to be an emergency ordinance, and that it shall take effect forthwith on its passage and publication. Section 14 — 10-13, N.M.S.A., 1953 Comp., and Albuquerque city charter Art. Ill, § 2(a), are as follows :
"(a) No act, ordinance or resolution or order of the governing body of the city shall, unless it be declared an emergency measure on the ground of urgent public need, go into effect until thirty [30] days after its passage. If at any time within the thirty [30] days, a petition signed by twenty [20] per cent of the qualified voters is presented to the governing body, asking that the measure in question be submitted to a vote of the people for adoption or rejection, said measure shall not go into effect until an election shall have been held as petitioned. It shall be the duty of the governing body of the city to provide *443for such election within thirty [30] days of the filing of the petition."
Section 14-10-14, N.M.S.A., 1953 Comp., ■•and Albuquerque city charter, Art. Ill, § 3(a) (b), read:
"(a) At such an election the ballot shall contain the text of the measure in question, and below the same phrases 'for the above measure' and 'against the above measure,' followed by spaces for marking with a cross the phrase desired. If a majority of the votes cast are against the measure, it shall be of no effect. If a majority of the votes cast be not against the measure it shall go into effect forthwith.
"(b) If a measure be declared an emergency measure, as provided above, it shall go into effect at once, subject to repeal by an adverse majority at the recall election."
Sections 14-10-13 and 14-10-14, supra, were originally enacted as Laws 1919, Ch. 121, Art. 3, §§ 2, 3. These provisions remain identical to the original enactments of 1919. •
Under § 14-10-13, supra, a non-emergency ordinance does not go into effect until 30 days after its passage, and during said period qualified voters may petition for a referendum election. If a petition signed by the required number of voters is filed, then the measure is not effective until an election is held. Section 14-10-14(b), suT pra, provides that emergency measures shall go into effect at once, subject to repeal by an adverse majority at the recall election. No time limit is set out for the filing of referendum petitions on emergency measures.
Provisions reserving to the people the power of initiative and referendum are to be given a liberal construction to effectuate the policy thereby adopted. Albuquerque Bus Co. v. Everly, 53 N.M. 460, 211 P.2d 127; 5 McQuillin 3d Ed., Municipal Corporations 246, § 16.51; 62 C.J.S. Municipal Corporations § 451b, page 870.
We do not believe that §§ 14-10-13 and 14 — 10-14, supra, impose a limitation period on the time within which petitions must be filed to referendum an emergency ordinance, but sets out a limitation period under § 14 — 10-13 within which petitions must be filed to suspend a non-emergency ordinance.
We are of the opinion that § 14 — 10— 14, supra, contemplates the referendum of emergency measures, but it does not provide the time within which the petitions must be filed. Reading the two statutes together there is merit to the New that the 30-day period referred to in § 14-10-13 also applies to the emergency provision in § 14-10-14. This is evident, we think, because § 14— 10-14 refers to the election mentioned in § 14-10-13 by saying: "(a) At such,an elec*444tion the ballot shall contain the text of the measure in question, * * * " and specifically refers to § 14-10-14 by the wording. "(b) If a measure be declared an emergency measure, as provided above, it shall go into effect at once, subject to repeal by an adverse majority at the recall election."
From the wording of these provisions we do not believe the legislature intended emergency measures to be subject to referendum for an indefinite period of time. We also believe that the only reason emergency measures were excluded from § 14-10-13, supra, was because the legislature intended the effective dates to be different and not because emergency measures could be repealed at any time. That this reasoning is correct seems to be emphasized by the purpose of an emergency measure, which is to have an early effective date. Further evidence of this construction appears in § 14-10-13, supra, where the exclusion of emergency measures from that provision is found only in the declaration of the effective date. This exclusion is not found in the next sentence which allows 30 days for the filing of referendum petitions.
We believe that § 14-25-7, N.M.S.A., 1953 Comp., should also be considered in our determination of the time limit to be applied to the petitions under consideration. The pertinent portions of that enactment are:
"All ordinances shall, as soon as may be after their passage, be recorded in a book kept for that purpose, * * *; and all by-laws of a general or permanent nature, * * * shall be published in some newspaper of general circulation in the municipal corporation, * * *; and such by-laws and ordinances shall not take effect and be in force until the expiration of five [5] days after they have been publish-g^J H? 4* ^
This provision was first enacted in Laws 1884, Ch. 39, § 25, and is substantially the same today.
Section 14 — 10—14(b), supra, provides that emergency measures go into effect at once, subject to repeal at the recall election. However, § 14-25-7, supra, provides that all ordinances go into effect five days after their publication. Section 14-25-7, supra, was enacted in 1884 and was in force when § 14 — 10—14(b), supra, was enacted in 1919.
In interpreting a statute this court may presume that the legislature was informed as to existing law, and that the legislature did not intend to enact a law inconsistent with any existing law or not in accord with common sense or sound reasoning. State ex rel. Maryland Cas. Co. v. State Highway Commission, 38 N.M. 482, 35 P.2d 308; McDonald v. Lambert, 43 N.M. 27, 85 P.2d 78, 120 A.L.R. 250. This court has the duty to construe acts so that all of the acts of the legislature will be operative. State ex rel. Rives v. Herring, *44557 N.M. 600, 261 P.2d 442. Statutes should be construed in the most beneficial way of which their language is susceptible to prevent absurdity, hardships or injustice, to favor public convenience, and to oppose all prejudice to public interests. Cox v. City of Albuquerque, 53 N.M. 334, 207 P.2d 1017.
In line with our rules of construction we will presume that the legislature, in enacting § 14-10-14 (b), supra, was fully aware of § 14-25-7, supra, and that § 14 — 25— 7 was intended to complement § 14 — 10—14(b) and not conflict with this later enactment. In construing the two provisions together we believe that the emergency measure in question did not take effect until five days after it was published on December 18, 1964. In addition, the ordinance itself provided in § 11 that it "shall take effect forthwith on its passage and publication." The City recognized the applicability of § 14-25-7, supra, because it had the emergency measure published and the City's attorney publicly stated that the 30-day period for referendum began to run five days after publication of the protested ordinance. This gave Nichols 35 days within which to file the petitions and extended the time limit to file the petitions until January 22, 1965. The petitions were filed on January 18, 1965, well within the time limit prescribed by our statutes and the Albuquerque city charter. We believe that this construction of our referendum statute does not unduly strain our rule of liberal construction where referendum statutes are involved.
Under subsection (b) of their first point, the City says that assuming, without conceding, that the petitions were timely filed, the district court had no jurisdiction to order the City to provide for and hold an election, since their duty was to first check the validity of the petitions. The City argues that it is their duty to determine the sufficiency, validity and legality of the signatures on the petitions before calling the election.
We find nothing in our statutes or in the Albuquerque city charter which sets forth the duties and obligations of the City in determining the sufficiency of the petitions. The only applicable provision is found in § 14-10-13, supra, which states in part:
" * * * If at any time within the thirty [30] days, a petition signed by twenty [20] per cent of the qualified voters is presented to the governing body, asking that the measure in question be submitted to a vote of the people for adoption or rejection, said measure shall not go into effect until an election shall have been held as petitioned. * * * "
Under this statute the only duty that the City has is to determine if the petitions contain the signatures of 20% of the qualified voters. It is incumbent upon the City to *446either deny the referendum, because the petitions lacked the signatures of 20% of the qualified voters, or provide for the election on the basis that the requisite signatures were contained in the petitions.
In the City's answer to the petition for the alternative writ of mandamus they alleged that the petitions for referendum do not contain the signatures of 20% of the qualified voters in Albuquerque. However, on appeal to this court the argument by the City on this point is that, assuming without conceding that the petitions were timely filed, the writ should not have been issued until they first checked the sufficiency and validity of the petitions. This argument on appeal seems to be the true contention of the City, as shown by their statements in the trial court. However, since the City argued both of these related theories in the trial court, even though they failed to plead lack of time, we will consider both.
The City introduced evidence showing that there were approximately 108,619 registered voters in Albuquerque on January 18, 1965, and that there were approximately 125,700 persons living in Albuquerque who were not insane, were over 21 and, therefore, qualified to vote, even if not registered. Nichols objected to both figures as being incorrect and, in turn, introduced evidence to show that there were 80,000 registered.voters in Albuquerque on January 11, 1965. . . .....
It was stipulated that the petitions contained 24,550 signatures. Nichols introduced a witness who testified that he counted the signatures in the petitions and that he did not count names without addresses, names with lines drawn through them, illegible names, incomplete names and names with addresses outside the City, but that he did not make a determination of whether the signatures were those of registered voters.
On January 28, 1965, 100 names from the petitions were checked to see if they were registered or if the signers lived within the City limits. Several employees of the City had been working for about a week prior to January 28, 1965, checking the validity of the petitions, and testimony was given by Mr. Brito, who was checking the names, that it would probably take several months to check 24,000 names and that one person could check approximately 200 to 300 names a day. The trial court accepted the City's statement that the signature checking was proceeding with diligence. In addition, Nichols introduced evidence to show that approximately 15,000 votes were cast in the October 8, 1963, city election and approximately 19,000 votes were cast in the April 3, 1962, city election.
We now consider the City's contention that it was their duty to determine the sufficiency, validity and legality of the petitions. The City relies upon Kiddy v. Board of County Commissioners of Eddy *447County, 57 N.M. 145, 255 P.2d 678, to support this contention. We do not consider that Kiddy is authority for the proposition that the City has the duty to conduct the full scale investigation which is contemplated. Kiddy is clearly distinguishable from the case before us. In Kiddy the petition was improper on its face, in that it submitted two propositions as one question. This court held in Kiddy that the County Commissioners had the right to refuse to call an election upon the basis of a petition which was patently deficient upon its face. In the case before us no claim is made that the petitions are deficient upon their face. The only duty imposed upon the City, when presented with petitions sufficient on their face, was the ministerial act of calling the election. Kiddy recognizes that mandamus is proper in such circumstances.
As we read the pleadings, the only question raised by the City is that there are insufficient valid signatures on the petitions. If the City does what it proposes to do under their contention, that it is their duty to determine the sufficiency, validity and legality of the petitions, it would enable the City to make a judicial determination which, under the city charter and the statutes, it has no jurisdiction to make. Our statutes and the city charter are completely silent as to what duties and obligations the city officials have in a situation such as we have before us.
We believe that the problem before us is answered in People ex rel. Wright v. Kelly, 294 Mich. 503, 293 N.W. 865. In Kelly the contention was made that the secretary of state should conduct an investigation and reject all names where there was similarity in handwriting or nonexistent streets, street numbers, wards or precincts. The question there was whether the secretary of state could make an independent investigation and go behind the face of the petition to test the validity of the signatures. The court stated that this depended upon whether the secretary of state was given quasi-judicial or ministerial powers. The court held that the duties of the secretary of state were ministerial only, and that he could not conduct an independent investigation to determine the genuineness of the signatures, and that it was for the legislature and not the court to establish the machinery by which the-genuineness of the signatures could be determined.
In Kerley v. Wetherell, 61 Idaho 31, 96 P.2d 503, the court held that, in the absence of authority in the statute, the city clerk was not required or permitted to inquire as. to the qualifications of signers, or pass upon the genuineness of statements of electors that they had read and understood the ordinance which they were petitioning to referendum. See also, State v. Perrault, 34 N.M. 438, 283 P. 902.
We, therefore, hold that there is no authority for the City to make the determina*448 tion which they propose, i. e., to determine the sufficiency, validity and legality of the petitions. The trial court having found that the petitions contained names equal to 20% of the "qualified voters" and having ordered the election, nothing remains to be done by the City except to comply. .
The order appealed from is affirmed and remanded to the district court with direction that it proceed in a manner consistent herewith.
CARMODY, C. J., and MOISE, J., concur.

redpajama_set_name: RedPajamaCommonCrawl


ASX-listed medical device makers ResMed (ASX:RMD) and HeartWare (ASX:HIN) on Friday both reported strong gains in revenue for the quarter ending in June.
ResMed - which develops medical products to help diagnose, treat and manage respiratory disorders – increased its revenue for the quarter 17% to US$341.9 million ($325.8 million). For the year ending in June, revenue grew 14% to US$1.2 billion.
Profit grew to US$58.5 million for the quarter, and US$227 million for the year – up 10% and 19% respectively.
But SG&A expenses grew 22% to US$102.3 million, or 29.9% of revenue, partly as a result of the appreciation of the Australian dollar. R&D expenses also grew 35% to US$26 million.
ResMed on Friday also revealed it had acquired Germany's Grundler GmbH, a medical humidification product developer, but said the transaction is not expected to have a material impact on its financial results.
Also on Friday, heart pump developer HeartWare posted a 109% increase in June quarter revenue to US$20.4 million.
International markets accounted for 69% of June-quarter revenues, and sales in the US more than tripled to US$6.3 million.
But the company reported a wider net loss of US$10.1 million for the quarter, from a US$10 million loss a year ago.
For the six months ending in June it was a similar story, with revenue growing to US$38.4 million from US$20.5 million a year earlier, but the net loss increasing to US$19.5 million from US$14.5 million.
HIN shares fell 2.94% in Friday's trading to $1.650, while RMD dipped 1.47% to $2.680.


A Play from the Children's Series. Conrad is usually just a bully. One day he crosses the wrong person, and his day goes from bad to much worse. After learning a valuable lesson, Conrad still needs his new friend (?), Russell, to save him from angry townspeople!
Russell lives on his family's farm with his friends Winnie (the horse), Arthur (the pig) and Lilah (the chicken). Every day when he returns home from school he tells his friends about his encounters with Conrad, the school bully. Lilah gives vent to the fact that, although there is no excuse for bad behavior, there is always a reason why someone decides to behave so badly and often it is a reaction to experiences they have had in the past.
One day, Conrad decides to go out into the woods to try to capture a troublesome fox and he falls into a big hole and lands in a deep, dark cave. Inside the cave, Conrad meets the Cave Goddess who warns him that he is now in her world where she demands respect. However, he continues to exercise his bad behavior and the Cave Goddess finally turns Conrad into a Troll. The spell she casts includes the rule that he is not permitted to tell anyone who he is or he will be condemned to live the rest of his life under this spell. The only way that the spell can be broken is if he finally learns how to show kindness and build friendships.
During the search for Conrad, the town discovers the "Troll" living in the caves and everyone is instructed to avoid the caves at all cost. Russell, on the other hand, is convinced that the Troll knows where Conrad is and, remembering Lilah's words, he finally decides that it is just the "right thing to do" to find Conrad and bring him home. He finally abandons all fear and goes into the cave to confront the Troll and, ultimately, Winnie, Arthur and Lilah decide to go after him to lend support.
While arguing with the Troll, the Cave Goddess appears and haughtily tells Russell that she knows exactly where Conrad is. Russell takes a stand and tells the Cave Goddess that Conrad is his friend and she must turn him over immediately.
The moment the "Troll" hears Russell declare himself to be his friend, he is moved to defend him against the Cave Goddess and he stands between Russell and the Cave Goddess and insists that she not harm Russell or the others because they are all his friends.
Upon hearing the "Troll" show the kindness toward Russell and declare his friendship, the Cave Goddess reveals her gentle side and releases Conrad from the spell and returns him to his former self.
This play is intended to help young audiences examine the problem of bullying and look at its causes, reasons for happening, and the fact that it is an undesirable path to chose.
RUSSELL: (Between 10 and 12 years of age) A sweet and thoughtful farm boy.
CONRAD: (Between 10 and 12 years of age) An arrogant bully.
CAVE GODDESS: A beautiful young woman dressed glamorously in black dress and headdress, with touches of gold and silver sparkles.
This play can be done with simple sets or, if the budget allows, the theater can make the sets much more involved.
Costumes are minimal and the Cast can be played by a combination of children and adults, or they can be all children, depending on your theater's objectives.
The Authors are available for consultation with regard to any difficulties in performing due to venue problems, or if there is any need for script adjustment in order for your group to be able to be able to perform the work. Simply call us Toll Free at (215) 345-5550, and we will be glad to help wherever we can.


The Altofts and Normanton Brass Band was founded in the 1880's by a small group of mine workers at the local , privately owned, colliery Pope and Pearson where it used the First Aid Room for it's band practice sessions.
In 1890 the band was formally registered with the Friendly Society and changed it's name to "The West Riding and Silkstone Band". It was not long before the band became well known throughout the district and it's membership continued to increase.
Sponsorship was secured in 1936, the then Sir H. Middlebrook and Viscount Halifax each donating the grand sum of £1.00 per year towards band funds, which in those days was much needed and appreciated.
Due to an amalgamation of the local privately owned collieries the band then continued as "The Altofts and Whitwood Collieries Band" and became part of the coal industry's Social Welfare Organisation (CISWO).
In 1953 the band sought financial assistance from CISWO towards the cost of new instruments and, on the 1st May that year, Messer R.R.Kitchens of Leeds supplied instruments to the sum of £1488.15.3d which arrived on the 20th of June 1954. Many of these instruments are still used to this day for tuition purposes.
The band has been known by several names in it's history but after an arrangement with the Lee Brigg WMC came to an end the words "Lee Brigg" were dropped from it's name and the band is now Known as "The Altofts and Normanton Brass Band".
In 1998 the band was granted the princely sum of £45,453 by the National Lottery for new instruments. Supplementary funds were also raised and new uniforms purchased.
Over the most recent years the band have performed for several charitable causes (including Age Concern, Cancer Research UK and, more locally, The Alice Bacon Trust) raising over £3000, to date, with more charity events organised for the coming year. This is the band's contribution back to the community.
We are a social, non-contesting band who meet on Wednesday and Sunday evenings in the St.Mary Magdalene church hall, Altofts.
If you would like to join us or learn how to play please do come along!
YOU ARE NEVER TOO OLD TO LEARN!!


Join the alien abduction support group alongside the cast of People of Earth.
Our team worked to cleverly promote Season 1 of this comedy series using VR and 360 storytelling. Ahead of the series premiere, we introduced the show to fans via YouTube 360 video "Alien Abduction Support Group," giving potential viewers a unique way to step inside one of the show's typical support group sessions and meet the characters. The script was improv-heavy, so working with the show's regular crew, Supersphere advised on blocking, lighting, and camera placement to ensure the best result. We were able to leverage content from the same shoot to create a second 360° video, "How To Catch a Reptilian," which was released on YouTube 360 toward the end of Season 1.


Britain is made up of over 6,000 islands and surprisingly 267 of these are inhabited. Acclaimed film actress Alison Steadman OBE has always been fascinated with idyllic island life. In this series she'll celebrate the wild and remote beauty that's right under our noses and meet the people who call these hidden jewels their home.
In our first episode Alison travels to the windswept and rugged Scottish Inner Hebrides, where she explores the little known and sparsely populated islands of Gigha, Jura, Colonsay and Oronsay. In episode two Alison ventures to the Channel Islands where she winds her way from the southern island of Jersey up to Alderney in the north via Sark. In the final episode she's off to the tropical paradise of the Isles of Scilly, an archipelago off the Cornish coast that has some of the most spectacular un-spoilt beaches in the whole of Europe. She's here to explore tiny "Off Islands" of Tresco, Bryher, St Martins and St Agnes.


Housing minister Dominic Raab has announced that £45 million will go towards key community projects to help 'kick-start' the building of 'thousands' of new homes across England.
A total of 79 projects will receive a share of the money to support the creation of up to 7,280 homes on council-owned land.
The funding comes for the Land Release Fund, and can be used by councils to combat barriers that "would otherwise make land unusable for development". The government hopes the fund will support councils' ambition to unlock enough of their own land for at least 16,000 homes by 2020.
The projects include a range of necessary works such as the removal of asbestos, bat alleviation and the relocation of a pelican crossing.
Raab said: "We are investing £45 million to build roads and provide utilities, so councils can release the land to get up to 7,280 new homes built.
"It's part of our strategy to build the homes Britain needs and carry local communities with us.
The Land Release Fund is being administered through a partnership with the Local Government Association (LGA) and the Cabinet Office's One Public Estate (OPE) programme.
Poulton-Le-Fylde, Lancashire – £1.7 million to build new roads, roundabouts, and utility services, which will unlock up to 330 homes that could potentially be built with Japanese modular housing techniques.
Worcester – £750,000 to demolish a leisure centre and undertake asbestos decontamination works near its city centre, helping to unlock up to 50 homes.
Paignton, Devon – £1.9 million to build a new 350-metre sewer, drainage upgrades and two new roads, which will help unlock up to 200 homes.
Brighton, East Sussex – £335,000 to divert a public sewer and make electricity substation and highways improvements. Up to 30 homes could be delivered as a result.
Félicie Krikler, director at Assael Architecture, said: "It is very positive to see 79 projects being allocated funds to facilitate the build-out of sustainable and well-designed new homes. Council-owned land, not in use and needing remediation offers a great opportunity for this and means that we have a new canvas on which to create new homes."


It strikes me as the same concept as drinking a glass of wine or two while pregnant. Most doctors will tell you it's safe. But you'll find people that will tell you that glass of beer? It will surely give your baby Fetal Alcohol Syndrome. And then they'll yell at you for eating deli meats and hey! You! Baby killer using the artificial sweetener in your decaf coffee! WHAT ARE YOU DOING? I'll bet that isn't even decaf! Is that ANOTHER Diet Coke you're drinking? You know it has caffeine in it, don't you?
Is it safe to dye or bleach your hair while pregnant? Will you? It's what I'm babbling about today.
*Also! Exciting photos of my biggest hair donts!


ECHO Village is a unique housing development, predominantly for low income residents, serving the homeless, first time jail offenders, vets, and anyone who needs to break out of the cycle of poverty. Designed for 26 small, affordable homes, shared common grounds embracing the concept of community living. Residents share their talents with each other in a way that enriches everyone.


Notes: words by Malvina Reynolds, music by Pete Seeger; copyright 1962 Brio Music, renewed 1990. a.k.a. "I Want to Go to Andorra!" Pete Seeger's recording of this song was issued on a CD in 2003 by the Andorran government. Also on the CD is a 1996 speech by the Andorran Foreign Minister given on the occasion of his signing the nuclear non-proliferation treaty at the U. S. State Department in Washington, D.C.
To shoot on their Fourth of July.
They throw the rascals out.


text:
Snowy, messy AM commute Thursday in NY, NJ before temps plummet
Soul coach Ada Rojas on manifesting your vision for 2022
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Barbie honors Ida B. Wells, great granddaughter talks legacy
Nets' star Irving steadfast on vaccine refusal despite Durant injury
Saint Margaret Cortona Church reopens to community for first time since Sandy
by: AA, Joe Mauceri
LITTLE FERRY, NEW JERSEY (PIX11) – It's been almost a year since super storm Sandy flooded the town of Little Ferry, New Jersey and Saint Margaret of Cortona Church.
But after more than $1 million in repairs, the church finally reopened to the community Sunday.
"We've been through so much with the water from Sandy and Irene and I think it's just fantastic that God has given us this day," Rose Policastro said.
With the sun shining bright on parishioners, a procession led the congregation from the gym, where services have been held since December, to the new church.
Once inside, Bishop John Flesey blessed the building and congregation with holy water.
Pastor Kevin Carter compared the service to a rebirth for the community.
"It's ironic how water for us, in spite of what it did for us, is still more of a symbol of life," he said.
Life that echoed through the church as congregants filled the brand new pews and sang hymns to the heavens inside the church for the first time in months.
"I kind of look at it as the phoenix rising from the ashes, starting again anew," said Ed Berta.
"What makes the rebuilding here at St. Margaret's even more amazing is the fact that they were able to do so without any government funding. You see right now churches aren't able to apply for FEMA grants because of the separation of church and state, even though those organizations are usually the first to respond to a community after a disaster."
"All too often it's the churches, it's the schools that become the centers for emergency response. Where we are right now in Little Ferry outside of St. Margaret of Cortona, we're standing in front of a building that was the first response center during the initial hours of hurricane Sandy," said Jim Goodness, communications director of the Archdiocese of Newark.
But new legislation could make it possible for churches to apply for FEMA funding. A bill sponsored by New Jersey Representative Chris Smith passed the House overwhelmingly back in February. But a similar bill has stalled in the Senate. Opponents of the bill say eligible facilities must be open to the general public.
In a statement, a Spokesperson for the group Americans United told us:
"A fundamental rule of American life is that congregants, not the taxpayers, pay for the construction and repair of houses of worship. We must not let a storm sweep away the wall of separation between church and state."
But Goodness said that wall is washed away when churches step in to help with emergency response. And even if churches aren't given the funding they request from FEMA, they should at least be given the chance to apply.
"All we're asking is that we be given the opportunity, like every other non-profit or other civic organization, when there's a devastation to apply for grants and prove we need the money to restore ourselves because we are essential to the operation of the community," he said.
Though St. Margaret and many other churches were able to recover after Sandy, without some funding help Goodness says they might not be able to provide the same support for the community or rebuild in the future.
by Mark Sundstrom / Jan 20, 2022
It started as a narcotics officer was attempting to serve an arrest warrant in the vicinity of Rockne Street and Elwood Avenue, in the New Springville area, according to sources. That's when the alleged gunman opened fire through a door, striking the officer.
by JOE REEDY, Associated Press / Jan 20, 2022
NBC will not be sending its announcers and most hosts to the Beijing Olympics due to continued concerns about rising COVID-19 cases worldwide and China's strict policy about those who test positive.
It will be the second straight Games for which the broadcast teams will work mostly out of NBC Sports headquarters in Stamford, Connecticut, rather than the host city.
Snowy, messy AM commute Thursday before temps plummet
NYC alternate side parking suspended Thursday, Jan. 20; parking meters in effect


A lot has happened in the last 12 months so we've put together a roundup of topics that made the news in our blog.
Imperva tracks DDoS activity closely throughout the year. And our quarterly Threat Landscape Reports in the first half of the year (first quarter and second quarter) give us valuable information about how these attacks continue to evolve.
Early in the year, we reported how distributed denial of service attacks were growing shorter, more complex and persistent. This is a result of botnet-for-hire services that let users with little or no tech background to launch short, low-volume attacks. This is significant because it allows non-professional offenders to leverage DDoS to disrupt businesses and individuals.
Overall, 80 percent of all DDoS attacks lasted less than one hour and, for the first time, we saw 90 percent of network layer attacks lasting less than 30 minutes, compared to 78.2 percent in Q4 2016.
Nearly 74 percent of targets suffer repeat assaults, with 19 percent being attacked 10 times or more and 35 percent being hit six or more times. This trend is a substantial increase from the year before.
By the end of the second quarter of 2017, we witnessed a decrease in the number of network layer assaults. We also saw some relief in application layer attacks, which had increased earlier in the year. However the number of repeat attacks went up.
And finally in August we saw the emergence of a new attack tactic, which we've named "Pulse Wave DDoS" because of the pattern it generates – a rapid succession of attack bursts that distribute a botnet's attack output. This allows a single offensive strike to go after multiple targets.
Major security breaches on Equifax and Uber made headlines this year, but they only represent a portion of the total of security breaches. Here are a few we covered in the past months.
In February, a new Mirai botnet variant attack was directed at one of our clients, a U.S. college (full details here). It ran for 54 straight hours and flooded the school's website with over 2.8 billion requests.
Mirai (which means "the future" in Japanese) was first discovered in 2016 and quickly became one of the most virulent DDoS malware programs known. Ever since its source code went public last year, we've seen Mirai continue to expand and develop.
In March, we got a behind-the-scenes look at a major spam campaign falsely representing the pharmaceutical industry (more details here). Spam represents an estimated $431 billon market. Its scale – especially in the counterfeit drug trade – continues to grow.
The spam botnet we intercepted was built to circumvent security countermeasures and consisted of 80,000 compromised devices. After decoding the script, we discovered the attack was built specifically to bypass spam filters – the type that identified unwanted messages based on sender identity and links to known malicious domains. The exploit worked because it paired two compromised domains working together to generate spam and reroute visitors.
In late 2016 and into early 2017, vulnerabilities in Magento, a popular e-commerce platform, were detected during a routine security audit (further details here). These vulnerable entry points could have potentially led to remote code execution and exposed the system and its database of sensitive customer information.
Ransomware isn't new. It's been targeting desktop and laptop computers for years and then mobile phones and servers. Recently we encountered Ronggolawe, a new web server ransomware (see details here).
In August, Ronggolawe was uploaded to GitHub. Once the attacker got the malicious code on the server it had the opportunity to be used to either encrypt or decrypt the files in the server.
GitHub deployed a web application firewall and successfully blocked malicious file uploads and remote code execution attacks.
In May, while performing a simulated cyberattack on the GitLab system (more details here), we discovered a vulnerability in the network that left users exposed to session hijacking attacks.
Session hijacking involves the interception of session tokens that identify individual users logged into a website. An attacker can use a stolen token to access a user's account and do irreparable damage.
GitLab immediately implemented two important measures. It replaced private tokens with RSS tokens for fetching RSS feed. This helped avoid exposed session IDs. And it also expanded personal access tokens that offered role-based access controls. These provided the same functionality as private tokens but with better security. In addition, GitLab started gradually phasing out private tokens altogether.
In July Apache Struts became vulnerable to a remote code execution attack (details here). Based on notes given to us by the client, it was possible to perform an RCE attack with a malicious field value when using a Struts 1 plugin. This plugin included a Showcase app that enabled the vulnerability.
And finally, in October we noticed several of our customers being bombarded with "send-to-a-friend" spam attacks (more information here). These form-filler bots attach themselves to the social sharing module found on commercial websites.
Our security team noticed the high rate of traffic and the considerable number of targets and investigated. We eventually confirmed that the assault was carried out via a botnet that let attackers spread their unwanted messaging via the popular social sharing app.
The spam included snippets of text from various Star Wars novels. Were the spammers fans of the long-running sci-fi franchise? We'll never know. Most likely, they were riding the wave of the franchise's popularity to add uniqueness to their emails to trick filtering mechanisms. We successfully shut down the spam scam and did our part in defeating the dark side of the Force.
Bitcoin and related crypto currencies, one of the most targeted industries has dominated the news recently. In the third quarter, we saw that 3.6 percent of total network layer DDoS attacks targeted bitcoin exchanges and related sites on our service. As bitcoin price spikes, we see how threat actors have the relatively small and young industry in their sights making it into the top-10 attacked industry list.
High packet rate network layer attacks grow more common. These assaults where the packet-forwarding rate is 50+ Mpps continue to grow, accounting for five percent of the total number of network layer attacks.
Network layer attacks are extremely persistent. In Q3 2017, half of network layer targets were attacked at least twice, while nearly a third were hit more than 10 times.
And to wrap up an eventful year, Gartner published its 2017 Magic Quadrant for Web Application Firewalls (WAF) and named Imperva a WAF leader again for the fourth consecutive year. Most recently the Forrester Wave ranked Imperva as a leader for the DDoS mitigation current offering and strategy categories. We couldn't be more thrilled!