2009-06-09 Assigned to APPLE INC. reassignment APPLE INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: PA SEMI, INC.
In one embodiment, a cache comprises a data memory comprising a plurality of data entries, each data entry having capacity to store a cache block of data, and a cache control unit coupled to the data memory. The cache control unit is configured to dynamically allocate a given data entry in the data memory to store a cache block being cached or to store data that is not being cache but is being staged for retransmission on an interface to which the cache is coupled.
This invention is related to the field of caches.
Caches are included in systems to reduce the latency of read/write operations from data consumers such as processors and other devices in computer systems (where a data consumer reads data from the main memory in the system, and sometimes writes data to memory as well). Typically, a cache has a relatively small capacity compared to the main memory, and high speed memory is used to build the cache. Data recently accessed by the data consumer(s) is typically stored in the cache, in units of cache blocks. That is, cache storage is typically allocated and deallocated in cache-block-sized units. The cache blocks are address aligned to natural cache block boundaries in the memory address space.
In addition to caches, buffering is typically provided in the system, between the data consumer(s) and the cache and/or between the cache and the memory system. Buffers are used to temporarily stage data for transfer. Such buffers are often costly in both area and latency.
In one embodiment, a cache comprises a data memory comprising a plurality of data entries, each data entry having capacity to store a cache block of data, and a cache control unit coupled to the data memory. The cache control unit is configured to dynamically allocate a given data entry in the data memory to store a cache block being cached or to store data that is not being cached but is being staged for retransmission on an interface to which the cache is coupled.
In an embodiment, a method comprises receiving data in a cache, the data being staged for retransmission on an interface to which the cache is coupled; and dynamically allocating a given data entry in a data memory of the cache to store the staged data, the given data entry having a capacity to store a cache block being cached and also useable to cache the cache block.
FIG. 2 is a block diagram of one embodiment of an IOC shown in FIG. 1.
FIG. 3 is a table illustrating allocation of data entries in one embodiment of the IOC.
FIG. 4 is a block diagram of a second embodiment of the IOC.
FIG. 5 is an example using an embodiment of FIG. 4.
FIG. 6 is a flow diagram illustrating various operations of one embodiment of the IOC.
Turning now to FIG. 1, a block diagram of one embodiment of a system 10 is shown. In the illustrated embodiment, the system 10 includes one or more processors such as processors 18A-18B, one or more memory controllers such as memory controllers 20A-20B, an I/O bridge (IOB) 22, an I/O memory (IOM) 24, an I/O cache (IOC) 26, a level 2 (L2) cache 28, an interconnect 30, a DMA controller 14, a peripheral interface controller 32, one or more media access control circuits (MACs) such as MACs 34A-34B, and a physical interface layer (PHY) 36. The processors 18A-18B, memory controllers 20A-20B, IOB 22, IOC 26, and L2 cache 28 are coupled to the interconnect 30. The IOB 22 is further coupled to the IOC 26 and the IOM 24. The IOC 26 is also further coupled to the IOM 24. The DMA controller 14 is also coupled to the IOB 22 and the IOM 24. The MACs 34A-34B are coupled to the DMA controller 14 and to the physical interface layer 36. The peripheral interface controller 32 is also coupled to the T/O bridge 22 and the IOM 24 (and thus indirectly coupled to the DMA controller 14) and to the physical interface layer 36. In some embodiments, the components of the system 10 may be integrated onto a single integrated circuit as a system on a chip. In other embodiments, the system 10 may be implemented as two or more integrated circuits.
The IOC 26 may be a cache for I/O-generated transactions, e.g. from the peripheral interface controller 32 and/or from the DMA controller 14, on behalf of the MACs 34A-34B. The DMA controller 14 may also generate transactions to perform memory to memory DMA copy operations, in one embodiment. Additionally, the IOC 26 may allocate data entries in its data memory to stage data received from the interconnect 30 for retransmission to I/O and/or to stage data received from I/O to be retransmitted on the interconnect 30. More particularly, the IOC 26 may dynamically allocate data entries in the data memory to store a cache block provided in a fill (due to a cache miss) or to store staged data. Data may be viewed as "staged" if it is not being cached for future (and possibly repeated) access, but rather is in transit and is being held only until the data can be transmitted onto the target interface. In contrast, cached data generally remains cached until replaced by more recently accessed data (eviction), forced flush for coherency purposes, or explicitly flushed under, e.g., program control.
By using IOC 26 storage for staging data, separate buffering may be avoided. Data may be directly transferred between the data memory of the IOC 26 and the interconnect 30. The number of staging buffers available may also be relatively larger (e.g. some significant percentage of the IOC 26, for example), and may dynamically vary based on the traffic actually experienced in the system 10.
More specifically, in the illustrated embodiment, the IOC 26 may serve to stage data at the boundary between coherent transactions (on the interconnect 30) and non-coherent I/O transactions. The staged data may be flowing in either direction (from the interconnect 30 to I/O or from I/O to the interconnect 30) and may correspond to a transaction sourced either on the interconnect 30 or in an I/O device.
In some embodiments, the IOC 26 may stage data from the interconnect 30 to the I/O components (the peripheral interface controller 32 and the DMA controller 14, in this embodiment). Generally, the IOC 26 may stage data to be transferred from one interface to another interface. In this embodiment, the IOM 24 may be used as a buffer for data being transferred between the IOC 26 and the peripheral interface 32 or the DMA controller 14. Thus, the data path between the interconnect 30 and the DMA controller 14/peripheral interface controller 32 may be through the IOC 26 and the IOM 24. The control path (including read/write requests, addresses in the host address space associated with the requests, etc.) may be between the IOB 22 (and the IOC tags) and the DMA controller 14/peripheral interface controller 32. The IOM 24 may not be included in other embodiments, and the IOM 24 buffering may be completely absorbed into the IOC 26. That is, in such embodiments, the data path may be from the interconnect 30 to the IOC 26 to the DMA controller 14/peripheral interface controller 32.
The processors 18A-18B comprise circuitry to execute instructions defined in an instruction set architecture implemented by the processors 18A-18B. Any instruction set architecture may be implemented in various embodiments. For example, the PowerPC™ instruction set architecture may be implemented. Other exemplary instruction set architectures may include the ARM™ instruction set, the MIPS™ instruction set, the SPARC™ instruction set, the x86 instruction set (also referred to as IA-32), the IA-64 instruction set, etc.
The memory controllers 20A-20B comprise circuitry configured to interface to memory. For example, the memory controllers 20A-20B may be configured to interface to dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), double data rate (DDR) SDRAM, DDR2 SDRAM, Rambus DRAM (RDRAM), etc. The memory controllers 20A-20B may receive read and write transactions from the interconnect 30 for the memory to which they are coupled, and may perform the read/write operations to the memory. The read and write transactions may include read and write transactions initiated by the IOB 22 on behalf of the DMA controller 14 and/or the peripheral interface controller 32. Additionally, the read and write transactions may include transactions generated by the processors 18A-18B and/or the L2 cache 28.
The L2 cache 28 may comprise a cache memory configured to cache copies of data corresponding to various memory locations in the memories to which the memory controllers 20A-20B are coupled, for low latency access by the processors 18A-18B and/or other agents on the interconnect 30. The L2 cache 28 may comprise any capacity and configuration (e.g. direct mapped, set associative, etc.).
The IOB 22 comprises circuitry configured to communicate transactions on the interconnect 30 on behalf of the DMA controller 14 and the peripheral interface controller 32. The interconnect 30 may support cache coherency, and the IOB 22 may participate in the coherency and ensure coherency of transactions initiated by the IOB 22. In the illustrated embodiment, the IOB 22 employs the IOC 26 to cache recent transactions initiated by the IOB 22. The IOC 26 may have any capacity and configuration, in various embodiments, and may be coherent. The IOC 26 may be used, e.g., to cache blocks of data which are only partially updated due to reads/writes generated by the DMA controller 14 and the peripheral interface controller 32. Using the IOC 26, read-modify-write sequences may be avoided on the interconnect 30, in some cases. Additionally, transactions on the interconnect 30 may be avoided for a cache hit in the IOC 26 for a read/write generated by the DMA controller 14 or the peripheral interface controller 32 if the IOC 26 has sufficient ownership of the cache block to complete the read/write.
The interconnect 30 may comprise any communication medium for communicating among the processors 18A-18B, the memory controllers 20A-20B, the L2 cache 28, and the IOB 22. For example, the interconnect 30 may be a bus with coherency support. The interconnect 30 may alternatively be a point-to-point interconnect between the above agents, a packet-based interconnect, or any other interconnect.
The DMA controller 14 is configured to perform DMA transfers between the interface circuits (e.g. the peripheral interface controller 32 and MACs 34A-34B) and the memory address space. Particularly, the DMA transfers may be between memory locations to which the address space is mapped (in memory attached to the memory controllers 20A-20B, for example) and the interface circuits. Additionally, the DMA controller 14 may, in some embodiments, be configured to perform DMA transfers between sets of memory locations within the address space. That is, both the source and destination of such a DMA transfer may be memory locations. The DMA controller 14 may be configured to perform one or more operations (or "functions") on the DMA data as the DMA data is being transferred, in some embodiments. In one embodiment, some of the operations that the DMA controller 14 performs are operations on packet data (e.g. encryption/decryption, cyclical redundancy check (CRC) generation or checking, checksum generation or checking, etc.). The operations may also include an exclusive OR (XOR) operation, which may be used for redundant array of inexpensive disks (RAID) processing, for example.
The MACs 34A-34B may comprise circuitry implementing the media access controller functionality defined for network interfaces. For example, one or more of the MACs 34A-34B may implement the Gigabit Ethernet standard. One or more of the MACs 34A-34B may implement the 10 Gigabit Ethernet Attachment Unit Interface (XAUI) standard. Other embodiments may implement other Ethernet standards, such as the 10 Megabit or 100 Megabit standards, or any other network standard. In one implementation, there are 6 MACs, 4 of which are Gigabit Ethernet MACs and 2 of which are XAUI MACs. Other embodiments may have more or fewer MACs, and any mix of MAC types.
The peripheral interface controller 32 comprises circuitry configured to control a peripheral interface. In one embodiment, the peripheral interface controller 32 may control a peripheral component interconnect (PCI) Express interface. Other embodiments may implement other peripheral interfaces (e.g. PCI, PCI-X, universal serial bus (USB), etc.) in addition to or instead of the PCI Express interface.
The PHY 36 may generally comprise the circuitry configured to physically communicate on the external interfaces to the system 10 under the control of the interface circuits 16. In one particular embodiment, the PHY 36 may comprise a set of serializer/deserializer (SERDES) circuits that may be configured for use as PCI Express lanes or as Ethernet connections. The PHY 36 may include the circuitry that performs 8 b/10 b encoding/decoding for transmission through the SERDES and synchronization first-in, first-out (FIFO) buffers, and also the circuitry that logically configures the SERDES links for use as PCI Express or Ethernet communication links. In one implementation, the PHY may comprise 24 SERDES that can be configured as PCI Express lanes or Ethernet connections. Any desired number of SERDES may be configured as PCI Express and any desired number may be configured as Ethernet connections.
It is noted that, in various embodiments, the system 10 may include one or any number of any of the elements shown in FIG. 1 (e.g. processors, memory controllers, caches, I/O bridges, DMA controllers, and/or interface circuits, etc.).
Turning now to FIG. 2, a block diagram of one embodiment of the IOC 26 is shown in more detail. The IOC 26, in the embodiment of FIG. 2, includes a cache tag memory 40, a cache data memory 42, and a cache control unit 44. The cache control unit 44 includes a free list 46. The cache tag memory 40 is coupled to receive addresses for transactions on the interconnect 30 and to receive addresses for transactions from the IOB 22 (and received by the IOB 22 from the DMA controller 14 and/or the peripheral interface controller 32). The cache data memory 42 is coupled to receive data or provide data for the transactions from the interconnect 30 and the IOM 24. The cache control unit 44 is coupled to the tag memory 40 and the data memory 42, and to receive various control information related to the transactions received in the IOC 26.
The data memory 42 may comprise a set of data entries, each having capacity to store a cache block of data. The data memory 42 may comprise a RAM, for example, indexed by entry number. The cache tag memory 40 may comprise a set of tag entries, each configured to store an address tag and other state related to its corresponding data entry. The cache tag memory 40 may also comprise a RAM. Alternatively, the cache tag memory 40 may comprise a content addressable memory (CAM) for snooping purposes, or a RAM/CAM combination.
The cache control unit 44 may dynamically allocate a data entry in the data memory 42 to store data for a transaction received by the IOC 26. The transaction may be an I/O write to memory, for example, received from the IOB 22/IOM 24. The transaction may also be a read completion (with data) provided from the IOB/IOM 24 in response to a read previously received from the interconnect 30 and targetting I/O. The transaction may be a write received from the interconnect 30 that targets I/O. Additionally, the transaction may be a read completion for a read from an I/O device to memory.
The transaction may be considered either cacheable or non-cacheable, but a data entry may be provided in the data memory 42 in either case. If the transaction is non-cacheable (either because of the type of transaction, software-controlled restrictions such as translation attributes, or due to IOC 26 caching policies), the allocated entry is used as a buffer. If the transaction is cacheable and a cache miss, the allocated entry is used as a cache entry. If the transaction is cacheable and a cache hit, an entry is not allocated and the hitting entry may be updated (or data may be provided from the hitting entry). Thus, at any given point in time, a given data entry in the data memory 42 may be serving as a cache entry or as a staging buffer entry. That is, data entries are not statically assigned to buffer or cache use, in this embodiment.
In the illustrated embodiment, the cache control unit 44 implements a free list 46 to track which data entries are currently free and which are currently allocated. The free list 46 may comprise a free list value for each entry, which may indicate allocated or free. For example, the free list value may be a bit indicating allocated in one state (set or clear) and free in the other state. In such an embodiment, the free list may be a bit vector having a specified bit position for each data entry in the data memory 42. The free list 46 may comprise a register or other storage storing the free list value for each data entry.
The cache tag 40 stores tags for the cache blocks cached in the IOC 26, along with other cache state. For example, since the IOC 26 is maintained coherent on the interconnect 30, the cache state may include the various coherence states implemented in the coherence scheme on the interconnect 30. In one embodiment, a modified, exclusive, shared, invalid (MESI) or modified, owned, exclusive, shared, invalid (MOESI) scheme may be implemented. Other embodiments may implement any other scheme, or subsets of any scheme, as desired.
Staged data in the data memory 42 may not yet be coherent with the interconnect 30, or may not be coherent at all (e.g. data moving toward I/O). Accordingly, in this embodiment, the tag entries that correspond to data entries storing staged data may be marked invalid, even though the free list indicates that the data entry is allocated. Accordingly, the tag memory 40 may be snooped for coherence purposes, and no snoop hit will be detected for entries that are storing staged data. In general, each tag entry may include validity indication, comprising one or more bits per entry. For example, the validity indication may be a valid bit, indicating valid or invalid with set and clear states. Alternatively, the validity indication may be the cache state, with the invalid state indicating invalid and any other state (shared, exclusive, etc.) indicating valid. Any validity indication may be used. For the remainder of this disclosure, the cache state will be used as an example of a validity indication.
The combination of the cache state in the corresponding tag entry and the free list state for a data entry may indicate the current state of the data entry, in this embodiment. For example, the table in FIG. 3 illustrates the combinations of values and the corresponding current state of the data entry, for one embodiment. If the free list value for the data entry indicates free, then the data entry is not currently in use and is available to be allocated. The cache state is a don't care if the free list value indicates free, in this embodiment. If the free list value for the data entry is allocated and the cache state in the corresponding tag entry is invalid, the data entry is in use as a staging buffer. If the free list value for the data entry is allocated and the cache state in the corresponding tag entry is valid, then the data entry is in use as a cache entry.
The IOC 26 may have any configuration. Particularly, in one embodiment, the IOC 26 may be fully associative (in which any entry of the cache may be used to cache any address). Such a structure may be used, e.g., for relatively small capacities. For example, 128 entries may be implemented in a full associative configuration, in one embodiment. Both cache blocks and staging buffer entries may be freely allocated across the fully associative entries. For larger capacities of the IOC, timing and power consumption considerations may make the fully associative configuration less feasible. In such embodiments, a direct mapped or set associative configuration may be implemented.
In typical direct mapped and set associative caches, there is a preconfigured, one-to-one correspondence between tag entries and data entries. In a direct mapped configuration, each address maps to one possible entry (tag and data) in the cache, at which the corresponding cache block would be stored. If that entry was allocated to store staged data, then that entry could not be used to cache data until the staged data has been transmitted. Similarly, in a set associative configuration, each address maps to two or more possible entries (dependent on the associativity of the cache). However it is possible that all entries in a set could be allocated to staging buffer use. Performance may be impacted negatively in such cases, e.g. if the data that cannot be cached is frequently accessed.
FIG. 4 is block diagram of another embodiment of the IOC 26, including the cache tag memory 40, the cache data memory 42, and the cache control unit 44 (including the free list 46) as shown in the embodiment of FIG. 2 and coupled as shown in FIG. 2. Additionally, a tag/data entry table 48 is shown, coupled in parallel with the cache tag memory 40 to receive addresses of transactions and coupled to the cache control unit 44.
In the embodiment of FIG. 4, the tag/data entry table 48 may be used to map a given tag entry (and thus the address tag stored therein) to a cache data entry. Accordingly, the tag/data entry table 48 may provide the link between a tag entry and a data entry, rather then a fixed mapping. The table 48 may be updated by the cache control unit 44. The cache tag memory 40 may be designed as normal, having the configuration of the IOC 26 (e.g. direct mapped or set associative). The cache data memory 42 may have a different configuration (e.g. a RAM indexed by entry number). When a tag entry is allocated to a cache block to be stored in the IOC 26, the cache control unit 44 may allocate a data entry using the free list 46. The cache control unit 44 may update the tag/data entry table 48 to link the tag entry and the allocated data entry. When a data entry is allocated for staging buffer use, the tag/data entry table 48 may not be updated, and there may not be a tag entry for the corresponding data entry. Some cache entries may be unavailable for use, if all data entries are in use as staging buffers at the time a cache allocation is attempted. However, the flexible allocation of data entries may reduce the likelihood that a cacheable transaction is blocked from caching or causes other cache data to be evicted so that the newly received data can be cached.
In one embodiment, the tag/data entry table 48 is congruent with the cache tag memory 40 (that is, it has the same configuration in terms of rows and columns of entries). The table entry corresponding to a given tag entry may store a pointer to the data entry in the data memory 42 that is assigned to store the cache block that is tagged by the given tag entry. Thus, data entries may be freely allocated to cache blocks or staging buffers, as desired. The pointer may have any form, depending on the construction of the cache data memory 42. For example, the pointer may be an entry number, an entry number and way if the data memory is set associative, etc.
FIG. 5 is an example illustrating the use of the tag/data entry table 48. In the example, the tag memory 40 (and thus the IOC 26) is 4 way set associative and the cache data memory 42 is a RAM indexed by entry number. Two sets of the cache tag memory 40 are shown, as are two corresponding rows of the tag/data entry table 48. In the example, there are three cache blocks represented by tags (C1, C2, and C3 in FIG. 5). For each entry in the tag memory 40, a corresponding entry in the tag/data entry table 48 entry has a pointer to an entry in the data memory 42. Specifically, cache block C1 has a corresponding pointer P1, cache block C2 has a corresponding pointer P2, and cache block C3 has a corresponding pointer P3. As shown by the arrows in FIG. 5, each pointer may point to any entry in the cache data memory 42 (storing cache block CD1, cache block CD2, and cache block CD3, respectively, in FIG. 5).
Additionally, a data entry is shown storing staged data (BD1) in FIG. 5. The staged data occupies a data entry 50 in the data memory 42. Accordingly, the data entry 50 may be unavailable for allocation to store a cache block, until the staged data is transmitted. There is no pointer in the tag/data entry table 48 to the data entry 50, but the free list value for the entry shows allocated. In the example, the free list value is a bit, which is clear to indicate allocated and set to indicate available. The free list 46 is illustrated as a bit vector to the right of the data memory 42.
Accordingly, the cache control unit 44 may dynamically allocate any data entry for staging buffer or cache use, and may be permitted to cache data for any given index (and way) in the data memory 42 as well.
While the tag/data entry table 48 is shown separately in FIGS. 4 and 5, other embodiments may implement the table in the cache tag memory 42 (e.g. each tag entry may include the pointer to the allocated data entry). In some embodiments, portions of the IOC 26 may be integrated into the IOB 22. For example, the tag memory and cache controller may be integrated. In such embodiments, having the tag/data entry table 48 near the cache data memory 42 may be desirable, and thus a separate table may be implemented.
It is noted that the tag memory 42 has been described as storing an address tag. Any portion of the address may form the address tag, including all of the address. For example, in fully associative embodiments, all of the address may be stored (or all of the address except for the least significant bits that define an offset in a cache block). In direct-mapped or set associative embodiments, the address tag may exclude the portion of the address used as an index (and may also exclude the offset bits).
It is noted that, while the IOC 26 is described above as having entries that may be allocated as staging buffers or cache storage, other caches may implement similar functionality. For example, caches in the processors 18A-18B may implement such functionality. In such a cache, the source of transactions may be the processor core's load/store functionality, instead of various I/O devices (through the IOB/IOM, in the illustrated embodiment). Furthermore, the L2 cache 28 may implement such functionality.
Turning now to FIG. 6, a flow diagram is shown illustrating various operations of the IOC 26 for one embodiment. The IOC 26, and more particularly the cache control unit 44, may comprise circuitry implementing the operation shown in FIG. 6. While the blocks are shown in a particular order for ease of understanding, other orders may be used. Blocks may be performed in parallel in combinatorial logic in the IOC 26/cache control unit 44. Blocks, combinations of blocks, and/or the flow diagram as a whole may represent multiple clock cycles of operation.
The IOC 26 may receive a transaction that includes data (e.g. from the interconnect 30 or from an I/O device—block 60). If the transaction is not cacheable (decision block 62, "no" leg), the allocated entry is being used as a staging buffer and thus the tag may be set to invalid (block 72). The IOC 26 may allocate an entry from the free list (block 66), updating the free list to indicate that the entry has been allocated. Additionally, the IOC 26 may write the transaction data to the allocated entry (block 64). If the transaction is cacheable (decision block 62, "yes" leg) and if a data entry has already been allocated for the transaction (decision block 68, "yes" leg), the IOC 26 may update the tag state in the entry based on the coherence scheme implemented on the interconnect 30 (block 69) and may write the data to the allocated entry (block 64). The tag state may depend on various responses to the transaction, such as snoop responses, responses to probes, etc. A block may already have been allocated for the data if the transaction is cacheable and hits in the cache, or if the data is a fill for a previous cache miss. Additionally, in some embodiments, an entry may already have been allocated if a previous transaction having data within the boundaries of the same cache block has been provided, and merging of the transactions is permissible. For example, write transactions are mergeable in some systems.
If the transaction is cacheable (decision block 62, "yes" leg) and an entry has not already been allocated (decision block 68, "no" leg), the IOC 26 may set the tag state of a tag entry based on the coherence scheme implemented on the interconnect 30 (block 70) and may allocate an available entry from the free list (block 66). The IOC 26 may update the free list to indicate that the entry has been allocated. As mentioned previously, data may be cacheable or uncacheable according to transaction type, software constraint, or policy of the IOC 26. In some embodiments, the decision of whether or not to cache a given block may be deferred until the data entry is ready to be freed. For IS example, a write operation that writes less than a cache block, and is merged in the IOC 26 into a cache block of data read from memory, may be retained in the cache to permit additional writes to occur. An I/O write of a complete data block, on the other hand, may be written to memory and deallocated from the cache.
If the IOC 26 detects that staged data is ready to be retransmitted to its target (decision block 74, "yes" leg), the IOC 26 may read the staged data from the data entry and transmit the data (block 76). The IOC 26 may return the data entry to the free list (block 78). That is, the IOC 26 may update the free list 46 to indicate that the data entry is available. The target for the data may be on the interconnect 30, or may be an I/O device communicating through the IOB 22/IOM 24, depending on the direction that the data is traveling.
If the IOC 26 detects that a cache block is to be evicted (decision block 80, "yes" leg), the IOC 26 may set the tag state to invalid (block 82). If the evicted cache block is modified, the tag state may be set to invalid once the evict-writeback transaction has been address-ordered on the interconnect 30. Thus, the data entry storing the evicted data may be converted to a staging buffer. If the evicted cache block is modified, the IOC 26 may read the data from the entry when the data is ready to be transmitted on the interconnect 30 and may transmit the data (block 76). The data entry is also returned to the free list (block 78).
The IOC 26 may also snoop coherent transactions from the interconnect 30. Since data entries currently in use as staging buffers either have an invalid corresponding tag entry (or no tag entry at all, in the case of the embodiment of FIG. 4), no snoop hit will be detected on such entries. If a snoop hit is detected that causes the tag to be invalidated (decision block 84, "yes" leg), the IOC 26 may set the tag state to invalid (block 82). If the data is to be provided by the IOC 26 in response to the snoop, the IOC 26 may read the data from the entry and transmit it on the interconnect 30 (block 76). In some cases, the data is not provided (e.g. an invalidate transaction, used when the source of the invalidate is going to overwrite the cache block). The IOC 26 may return the entry to the free list (block 78). In some cases, the return to the free list may be delayed (e.g. if the data still needs to be forwarded, such as a read completion to an I/O device). If a snoop hit is detected that does not cause the tag to be invalidated (decision block 85, "yes" leg), the IOC 26 may update the tag state in accordance with the coherence scheme implemented by the interconnect 30 and may supply the data in response to the snoop, if necessary (block 86).
Not shown in FIG. 6 is the cacheable read cache hit case. If a read transaction from an I/O device hits in the IOC 26, the IOC 26 provides data from the hitting entry.
a cache control unit coupled to the data memory, wherein the cache control unit is configured to dynamically allocate a given data entry in the data memory to store a cache block being cached or to store data that is being staged for retransmission on an interface to which the cache is coupled.
2. The cache as recited in claim 1 further comprising a tag memory coupled to the cache control unit, wherein the tag memory comprises a plurality of tag entries configured to store address tags corresponding to data in the data memory, wherein a given address tag entry corresponding to the given data entry is marked invalid if the given data entry is storing staged data.
3. The cache as recited in claim 2 wherein the interface is a coherent interconnect, and wherein the tag memory is snooped to maintain coherency, and wherein a snoop hit is not detected on staged data since the tag is marked invalid.
4. The cache as recited in claim 1 wherein the cache control unit comprises a free list, and wherein the cache control unit is configured to use the free list to track which data entries in the data memory are currently allocated and which are currently free, and wherein the cache control unit is configured to update the free list to indicate that the given data entry is currently allocated responsive to allocating the given data entry.
5. The cache as recited in claim 4 further comprising a tag memory coupled to the cache control unit, wherein the tag memory comprises a plurality of tag entries configured to store address tags corresponding to data in the data memory and validity indications, and wherein a combination of the free list value for the given data entry and the validity indication in the tag memory for the given data entry indicate a current state of the given data entry.
6. The cache as recited in claim 5 wherein, if the free list value indicates that the given data entry is free, the given data entry is available for allocation.
7. The cache as recited in claim 5 wherein, if the free list value indicates that the given data entry is allocated and the validity indication indicates invalid, the given data entry is allocated to store staged data.
8. The cache as recited in claim 5 wherein, if the free list value indicates that the given data entry is allocated and the validity indication indicates valid, the given data entry is allocated to store a cache block.
9. The cache as recited in claim 5 wherein the validity indication comprises a cache state including at least an invalid state and a shared state.
10. The cache as recited in claim 5 wherein the cache control unit is configured to update the free list to indicate that the given data entry is currently free if the given data entry is storing staged data and the staged data has been retransmitted.
11. The cache as recited in claim 5 wherein, if the given data entry is storing cache data and the cache data is evicted, the cache control unit is configured to set the validity indication in the tag memory to invalid to convert the given data entry from a cache entry to a staging buffer.
12. The cache as recited in claim 11 wherein the cache control unit is configured to update the free list to indicate the given data entry is currently free responsive to transferring the evicted data.
13. The cache as recited in claim 5 further comprising a table that maps the tag entries in the tag memory to the data entries in the data memory, wherein the cache control unit is configured to create the mapping responsive to allocating a data entry for cache block storage.
14. The cache as recited in claim 13 wherein the table is congruent to the tag memory.
15. The cache as recited in claim 1 wherein the cache is coupled to a second interface, and wherein the cache is configured to receive the staged data for retransmission from the second interface.
16. The cache as recited in claim 15 wherein the cache is configured to receive data from Is the interface for retransmission on a second interface, and wherein the cache is configured to allocate a data entry to store the data.
dynamically allocating a given data entry in a data memory of the cache to store the staged data, the given data entry having a capacity to store a cache block being cached and also useable to cache the cache block.
18. The method as recited in claim 17 further comprising tracking which of the data entries in the data memory are currently allocated to either cache blocks or staged data and which entries are free.
19. The method as recited in claim 18 further comprising maintaining cache tags for the cache blocks.
20. The method as recited in claim 19 wherein a combination of cache state in the cache tags and state in the free list indicates whether the given data entry is storing staged data or a cache block.


Practice good sleep habits for the easiest, most effective way to better sleep!
Good sleep habits are essential for our health! I used to think that the pillars of optimal health were threefold: nutrition, exercise and stress management. Now I believe in a fourth pillar. Sleep. Sleep – enough of it, and especially enough good sleep (deep, restorative REM sleep) – restores our body clock. It restores our energy levels. It even helps keep us combat chronic disease. I now think of sleep as another tool in my arsenal to help stay healthy. Current guidelines (https://sleepfoundation.org/press-release/national-sleep-foundation-recommends-new-sleep-times) recommend adults sleep 7-9 hours every night. Many of us don't meet these recommended guidelines, often because we don't have good sleep habits in place.
Getting a good night's sleep can help. But getting a good night's sleep often requires practicing good sleep habits!
Foods can help, or make sleep worse. To avoid: caffeine after mid-afternoon since it is a stimulant. And alcohol near bedtime because although it initially acts as a sedative, it is a known sleep-disrupter. To try: a calming cup of warm organic milk (grassed if possible!). The amino acid tryptophan, found in milk, causes sleepiness. In fact, tryptophan converts to serotonin, which is then converted to melatonin. Melatonin regulates our sleep-wake cycles. Other melatonin-rich foods: try a cup of cherries before bed. Bananas and oranges are also good sources.
This post first appeared on Prescribe Nutrition's blog; it has been slightly modified here.


text:
Community, Faith
Wednesday, April 11th, 2012 By Catherine Cluett Pactol
Leaving a Legacy of Faith
Well-loved priest to move from Molokai.
By Catherine Cluett
While most Catholic priests are known for their spotless black cassocks and distinctive clerical collar, Molokai's Father Clyde Guerreiro is often found in work-worn denim overalls, a construction tool in hand.
Father Clyde Guerreiro, standing at the current site of the new St. Damien Church before it was constructed. Photo by Catherine Cluett
Described by parishioners and community members as self-deprecating, down-to-earth, quick to laugh, a handyman and a visionary, Guerriero is fulfilling his childhood dream of priesthood. As a member of the Sacred Hearts order, he has been serving on Molokai for five years. But at the end of June, Guerreiro will be leaving the island, having been asked to re-build a Catholic community in Wahiawa, Oahu, and later, Tonga.
"He's a builder, both in construction and in lives and communities," said Sacred Hearts provincial superior Father Johnathan Hurrell, who made the decision to transfer Guerreiro.
Building the St. Damien Church is what Guerreiro is best known for on Molokai. The multi-million dollar structure had been in the planning stages for the parish since 1995, but after St. Sophia church burned in 2010, Guerreiro worked with parishioners to make the new church a reality in time for the Christmas Eve service in 2011.
Guerreiro spearheaded fundraising efforts, helped plan the church's construction, and assisted hands-on as the building took shape.
The priest's background in construction came from his father.
"We were very close," said Guerreiro, who learned the trade working side by side in his dad's business. Yet despite the working relationship he had with his father, Guerreiro described his childhood growing up in Pearl City, Oahu, as "divisive."
"My dad broke the dinner table when I announced I wanted to enter seminary," said Guerreiro. "He hated the church." The young Guerreiro, encouraged by his mother, began seminary school at age 13.
"I'm what they called a 'lifer,'" he said of his long-term commitment to the church. "I've always wanted to be a priest… When I was young, I wanted to be three things: a truck driver, a pilot and a priest. I did all three."
But his religious calling took precedence, and Guerreiro rose to the top of his chosen vocation, traveling around the world as a provincial superior (and Hurrell's mentor), a position he likened to a CEO of the Sacred Hearts order.
But he described the leadership role as "painful" and left it to return to the type of work he said he prefers – working, teaching and building faith communities. While the Sacred Hearts order usually assigns priests to parishes, Guerreiro said he requested to serve on Molokai, because he perceived it at the time to be economically depressed.
"You wanna say going in, 'don't get close to people' but that never happens. I've gotten close to people… it's hard," he said.
"From the time I was a kid – I'm almost 80 years old – we've had priests come and go," said parishioner Fred Bicoy. "I felt sad… when I heard he was going to go – that's the[closeness] we have."
Father Clyde during the dedication Mass of the new St. Damien Church last year. Photo by Catherine Cluett
Molokai Work
Construction of the new church wasn't the only reason he came to Molokai, Guerreiro said.
One of his goals was to establish a community of Sacred Hearts brothers and sisters on Molokai. Three sisters now live on the island and serve those in need.
"As my brother in [the Sacred Hearts] community… he always looks after us," said Sacred Hearts Sister Jessie Kai. "He loves to tease," she added, laughing. "Those are the things I'll remember."
Among other legacies, Guerreiro will leave are the adult Faith Formations educational study group as well as the strong youth ministry program on Molokai. Guerreiro said he has also forged good relationships with other local ministers.
Forging relationships is one of the things Guerreiro did best, and many say they will miss his presence, laughter and leadership on Molokai.
"When he first mentioned [leaving]… my heart went down to my toes. I don't want to let him go," said Kai.
"He doesn't reside in isolation," said Rose Brito, St. Damien Parish secretary and long-time parishioner. "It's nice having someone who we can communicate with easily – he can make light of…things."
Guerreiro's ability to relate to his congregation is also what sticks out for Bicoy.
"I like his homilies because…even though [the scripture] was 2000 years ago, [he makes it so] we can relate to the word of God," said Bicoy.
For Guerreiro, his most memorable moments include celebrating the canonizations of St. Damien "with bishops up the yin-yang," and the groundbreaking of the new church.
"It was really a funeral, and from death came new life," he said of the ceremony, which included honoring relics from the burned ruins of St. Sophia.
But he said his favorite memories may be of "the dumb things," like the kids playing phone pranks on him.
"He's brought a wonderful enthusiasm to all aspects of parish life," said parishioner Maria Sullivan. "I will personally miss him."
One of Guerreiro's top priorities before he leaves is to finish construction of the new church, including a ramp between the church and the office building. He said the project has been put up for bid, but if the bids are too expensive, "me and the guys will do it ourselves."
Guerreiro is leaving before the normal six-year term is up because a recent merger of Sacred Hearts Hawaii provinces has created a larger pool of priests to serve each area. Hurrell said he chose Guerreiro to lead the order in reviving Our Lady of Sorrows parish in Wahiawa, which has been inactive for over 40 years. But once the new parish is back on its feet after one year, Guerreiro is scheduled for an even bigger challenge: starting a Sacred Hearts community in Tonga.
Sacred Hearts was invited by the Bishop of Tonga, who is looking for presence of another order, Guerreiro said. He will conduct continuing education for young priests, and start a new parish for English speaking foreign-born residents.
And, Guerreiro sighed, build a new church.
"He is a rare person who is open to cultures and world views, and appreciates people of different… backgrounds," said Hurrell.
While Molokai parishioners say they will miss Guerreiro, they are also hopeful for the future. Coming to serve the parish in July is Father William Petrie of Massachusetts, according to Hurrell. The priest has worked with Hansen's disease patients in India for 25 years, where he worked closely with Mother Teresa of Calcutta.
Petrie spent six months on Molokai in 2000, during which pastoral council member Leoda Shizuma said she got to know him.
"He is truly a wonderful person," she said. "He breathes St. Damien, which I believe is good for our souls here."
Kalaupapa will also be getting a new priest. Sacred Hearts Father Patrick Killilea, a native of Ireland, will begin serving this summer, according to Hurrell. He will replace Father Ambrose Sapa, who is being transferred to Oahu.
Guerriero called those taking his place "eminently qualified."
"I've made lasting friends and have family here," said Guerriero. "It's not like I'll never be back."
Posted in Community, Faith	 Add your comment
« Molokai Student Winners in Poster Contest
John Keawe Slack Key Clip »

redpajama_set_name: RedPajamaCommonCrawl


Polishing Synthetic Leather synthetic leather polishing pad specialized for glass polishing.
Polishing synthetic leather supplier in China! WINIW supply high quality polishing synthetic leather , synthetic polishing pad, specialized for the polishing of glass, jewelry, cellphone and LCD panel, etc.
WINIW Polishing Synthetic Leather are widely used for the polishing/grinding/buffing/lapping of sapphire, diode transistor(DTL), electronics, optical prism, piezoelectric glass, watch/clock crystal, crystal glass flat, etc.
WINIW supply various types and full range options Polishing Synthetic Leather, mainly 3 types: rough polishing, fine polishing and precise polishing.


Description Ideal for university graduates, entry level position assisting senior staff.
Typical tasks; Designer [70% Estimated].Website Development [20% Estimated]. Admin [10% Estimated] General Admin and Clerical, Website Logo Design Updates, Copywriting.
Job Description: Ideal for graduates from India, entry level position assisting senior staff.
Typical days of operation; Mon-Fri New Delhi Time 6:30am to 2:30pm (overtime to 4pm or later paid additional). Sat-Sun work negotiable. All work from home.
This is a clients and new clients website, DO NOT contact us. If you have any questions regarding the application, find the most appropriate application and fill it out as best you can. All applications will be considered. ONLY shortlisted applicants will be contacted.
Other Salary Details: Opportunity for pay rise if you do well.
Vridia LLP is a consulting agency that specialises in website development.
Do NOT email or call.


text:
var module_values = [];
var reset_check = false;

$(".module_list").find(':checked').each(function () {
    module_values.push($(this).val());
});

$(".clear_all").on("click", function (e) {
    e.preventDefault();
    clearAllSelectins();
});

$(".clear_all_modules").on("click", function (e) {
    e.preventDefault();
    clearAllModulesSelectins();
});

$(".reset").on("click", function (e) {
    e.preventDefault();
    $('input:checkbox').removeAttr('checked');
    $("tr").removeClass("highlight");
    for (var i in module_values) {
        $("input:checkbox[value=" + module_values[i] + "]").prop('checked', true);
    }
    reset_check = false;
});

$(".battery_list li span").on("click", function (e) {
    e.preventDefault();
    if (this.className.indexOf("highlight") > -1) {
        $("tr").removeClass("highlight");
        var classes = $(this).attr('class').split(' ');

        for (var i = 0; i < classes.length; i++) {
            $("." + classes[i]).closest("tr").addClass("highlight");
        }
    } else {
        //$('input:checkbox').removeAttr('checked');
        $("." + $(this).attr('class')).prop('checked', true);
        $("tr").removeClass("highlight");
        var classes = $(this).attr('class').split(' ');

        for (var i = 0; i < classes.length; i++) {
            $("." + classes[i]).closest("tr").addClass("highlight");
        }
    }
});

$(".battery_list input").on("click", function (e) {
    $(".module_list tr input").prop('checked', false);

    if (reset_check == false) {
        for (var i in module_values) {
            $("input:checkbox[value=" + module_values[i] + "]").prop('checked', true);
        }
    }

    $(".module_list  ." + $(this).attr('class')).prop('checked', true);
    $(".module_list tr").removeClass("highlight");

    var classes = $(this).attr('class').split(' ');

    for (var i = 0; i < classes.length; i++) {
        $(".module_list ." + classes[i]).closest("tr").addClass("highlight");
    }
});

var selectedProgramId = $("#selectedProgramId").val();
$li.hide().filter(".program_" + selectedProgramId).show();
if ((selectedProgramId == "") || (typeof selectedProgramId == "undefined" )) {
    $li.show();
}

// Filter Batteries that assigned to a specific program - JH
function clearAllSelectins() {
    $('input:checkbox').removeAttr('checked');
    $('input:radio').removeAttr('checked');
    $("tr").removeClass("highlight");
    reset_check = true;
}

function clearAllModulesSelectins() {
    $('input:checkbox').removeAttr('checked');
    $("tr").removeClass("highlight");
    reset_check = true;
}

var $li = $('.battery_list').find('li');
$("#selectedProgramId").on("change", function (e) {
    var selectedProgramId = $("#selectedProgramId").val();
    $li.hide().filter(".program_" + selectedProgramId).show();
    //clearAllSelectins(); // Clear All Module Selections

    if ((selectedProgramId == "") || (typeof selectedProgramId == "undefined" )) {
        $li.show();
    }
});
//})

redpajama_set_name: RedPajamaGithub


text:
Justia Patents With Particular Phosphor Or Electrode MaterialUS Patent Application for Light emission apparatus and method of fabricating the same Patent Application (Application #20020190637)
Light emission apparatus and method of fabricating the same
Mar 28, 2002 - Sumitomo Electric Industries, Ltd.
A light emission apparatus includes: an electrode; a LED mounted on the electrode with an indium layer posed therebetween, the LED having a substrate formed of an n-type ZnSe single crystal, and an epitaxial light emission structure formed of a compound crystal relating ZnSe serving as a matrix, the epitaxial light emission structure being provided on the substrate and emitting light when an electric current is introduced thereinto; and resin encapsulating the LED, the resin having a glass transition temperature of lower than 80 degrees centigrade or being soft to be still elastic in a vicinity of the LED at room temperature.
Latest Sumitomo Electric Industries, Ltd. Patents:
Differential amplifier circuit having stable gain
Fuel battery
Optical fiber amplifier
Titanium carbonitride powder and method for manufacturing titanium carbonitride powder
Insulated-gate transistor
[0001] 1. Field of the Invention
[0002] The present invention relates generally to novel semiconductor light emitting devices provided in the form of a single semiconductor chip and capable of emitting light of white color, a neutral color between red and blue, such as magenta, pink and the like, and the like and particularly to structures for reducing stress exerted to the same.
[0003] 2. Description of the Background Art
[0004] As a material for a high bright light emitting diode (LED) a device including a light emitting layer of AlGaAs, GaAsP and the like for red color has been put to practical use and an intensity of no less than several candela (Cd) has been implemented by an inexpensive LED. Other than LEDs for red, GaP for green and yellow-green, GaInN for blue and green, AlGaInP for Mars yellow and yellow have all been put to practical use as inexpensive LEDs.
[0005] These LEDs, however, all use a single semiconductor material for their light emitting layers and in principle they can only provide monochromatic light emission. Thus, while typical LED structures are capable of emitting light of a primary color, a color between red and green, and a color between green and blue, such as red, Mars yellow, yellow, yellow-green, green, blue-green, blue, blue-violet and violet, they are incapable of emitting light of a neutral color between red and blue and a neutral color between red, green and blue.
[0006] For illumination, decoration and some other similar applications for displaying, a source of light of a color between red and blue (e.g., magenta, pink), a color between red, blue and green (i.e., white), or the like is demanded, rather than a source of monochromatic light as described above. As has been described above, typical LEDs can only achieve a source of monochromatic light, and thus for their source of light a fluorescent lump, an incandescent lump or the like is used and it has thus suffered short lifetime, large sizes and low luminosity.
[0007] In contrast, the present inventors have succeeded in obtaining white light, pink light, magenta light and the like from a single LED using a ZnSe-based homoepitaxial layer formed on a ZnSe substrate, as has been described in Japanese Patent Laying-Open Nos. 2000-82845 and 2000-150960.
[0008] A ZnSe substrate which is doped with iodine, aluminum, chlorine, bromine, gallium, indium or the like can provide conductance of n-type, and when it is illuminated with light of shorter than 510 nm ZnSe can provide a so-called self-activated (SA) luminescence, a broad light emission having a center of an emission wavelength in a range of 550 nm to 650 nm. This light emission appears to be yellow, Mars yellow, or the like.
[0009] The central wavelength and the half-width of emission spectrum of SA luminescence can be adjusted by the species, amount or the like of the dopant introduced. Furthermore, a light emission structure of ZnSe used as a matrix can be formed on a ZnSe substrate through homoepitaxy. In this light emission structure, ZnSe or ZnCdSe or ZnSeTe can be used for an active layer to form a high bright LED emitting light at a wavelength from 460 nm to 510 nm for blue color or blue-green color.
[0010] FIG. 1 shows a concept of the present LED 5. In the figure an epitaxial light emission structure provides blue or blue-green light emission, of which that emitted toward the substrate is absorbed by a ZnSe substrate 1 and excites optically SA light emission and thus provides yellow, Mars yellow or red light. The former light emission and the latter light emission can be combined together to obtain emission of light of white, pink, magenta or other similar neutral colors.
[0011] The present LED 5 employs a group II-VI compound semiconductor, or ZnSe, as a main material. It should be noted, however, that this ZnSe crystallographically has a significantly smaller strength than GaP, GaAs and other similar group III-V compound semiconductor that are used for popular LEDs.
[0012] As such, if in a mounting process at each step an LED chip has stress introduced therein the ZnSe substrate crystal, epitaxial light emission structure 2 and the like are partially damaged, crack or the like and the device is thus significantly impaired disadvantageously.
[0013] FIG. 2 shows an example of a light emission apparatus having the LED 5 described above. As shown in FIG. 2, on a resin base 3 having a patterned interconnection (or electrode) 4 LED 5 is mounted with an indium layer 8 attached therebetween. LED 5 is connected to patterned interconnection 4 by a gold wire 7 and encapsulated with transparent resin 6.
[0014] The fabrication of the above inexpensive LED 5 essentially requires transparent resin 6. However, in the step of encapsulating the chip with transparent resin 6 the resin cures and contracts and thus introduces stress which significantly contributes to degradation of the device.
[0015] Furthermore, the present LED 5, as described in Japanese Patent Laying-Open No. 2001-28459, uses indium layer 8 serving as a soldering material also as a material for an ohmic electrode.
[0016] If the melting point of indium layer 8 and the softening point of transparent resin 6 are close, then, after a completed LED lamp for example reflowed or soldered to be mounted, indium layer (electrode) 8 would be affected and the value in driving voltage of the LED lamp would vary disadvantageously.
[0017] These issues are common to ZnSe-based LEDs for white color and pink, magenta and other similar neutral colors.
[0018] The present invention has been made to overcome the above issues. An object of the present invention lies, in a light emission apparatus mounted with a ZnSe-based LED chip fixed on an electrode by means of an indium layer, in reducing degradation of a device that is attributed to stress introduced when resin encapsulating the LED chip cures and contracts, and also in preventing the indium layer from being degraded and thus change a value in driving voltage of the LED lamp.
[0019] In accordance with the present invention a light emission apparatus in one aspect includes: an electrode; a light emitting device mounted on the electrode with an indium layer posed therebetween, the light emitting device having a substrate formed of an n-type ZnSe single crystal, and an epitaxial light emission structure formed of a compound crystal relating ZnSe serving as a matrix thereof, the epitaxial light emission structure being provided on the substrate and emitting light when an electric current is introduced thereinto; and resin encapsulating the light emitting device, the resin having a glass transition temperature of lower than 80 degrees centigrade.
[0020] The resin includes epoxy resin having a glass transition temperature of higher than 30 degrees centigrade and lower than 80 degrees centigrade and being transparent or having a light diffusing agent mixed therein.
[0021] In accordance with the present invention a light emission apparatus in another aspect includes: an electrode; a light emitting device mounted on the electrode with an indium layer posed therebetween, the light emitting device having a substrate formed of an n-type ZnSe single crystal, and an epitaxial light emission structure formed of a compound crystal relating ZnSe serving as a matrix thereof, the epitaxial light emission structure being provided on the substrate and emitting light when an electric current is introduced thereinto; and resin encapsulating the light emitting device. The resin includes a first resin transparent or having a light diffusing agent mixed therein, and covering the light emitting device, and a second resin transparent or having a light diffusing agent mixed therein, and covering the first resin, the first resin having an elasticity corresponding to an elongation of no less than 40% at room temperature, the second resin being harder than the first resin.
[0022] The first resin includes silicone resin and the second resin includes epoxy resin. Furthermore the present apparatus may be a so-called surface-mounted type including a base formed of insulator, wherein the electrode includes a patterned electrode formed on the base.
[0023] The present apparatus may include a reflector provided on the base to surround the light emitting device for reflecting fluorescence received from the substrate, wherein the resin is introduced into a region surrounded by the reflector.
[0024] In accordance with the present invention a method of fabricating a light emission apparatus, in one aspect, includes the steps of: mounting a light emitting device on an electrode with an indium layer posed therebetween, the light emitting device having a substrate formed of an n-type ZnSe single crystal, and an epitaxial light emission structure formed of a compound crystal relating ZnSe serving as a matrix thereof, the epitaxial light emission structure being provided on the substrate and emitting light when an electric current is introduced thereinto; and dropping epoxy resin on the light emitting device and then curing the epoxy resin to encapsulate the light emitting device, the epoxy resin having a glass transition temperature of no more than 80 degrees centigrade.
[0025] In accordance with the present invention a method of fabricating a light emission apparatus, in another aspect, includes the steps of: mounting a light emitting device on an electrode with an indium layer posed therebetween, the light emitting device having a substrate formed of an n-type ZnSe single crystal, and an epitaxial light emission structure formed of a compound crystal relating ZnSe serving as a matrix thereof, the epitaxial light emission structure being provided on the substrate and emitting light when an electric current is introduced thereinto; covering the light emitting device with silicone resin; and transfer-molding epoxy resin to cover the silicone resin therewith.
[0026] The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
[0027] In the drawings:
[0028] FIG. 1 is a cross section of a multi-color LED allowing a substrate to emit light;
[0029] FIG. 2 is a cross section of a light emission apparatus having a multi-color LED allowing a substrate to emit light;
[0030] FIG. 3 shows an LED chip having cracks attributed to stress introduced when resin encapsulating it contracts;
[0031] FIG. 4 shows an indium layer internally having voids after reflowing;
[0032] FIG. 5 is a cross section of an ZnSe substrate and an epitaxial light emission structure of an LED of the present invention in a first embodiment;
[0033] FIG. 6 is a side view of the light emission apparatus of the first embodiment;
[0034] FIG. 7 is a side view of the light emission apparatus of the first embodiment in a variation;
[0035] FIG. 8 is a cross section of the light emission apparatus of the present invention in a second embodiment;
[0036] FIG. 9 is a cross section of the light emission apparatus of the second embodiment in a variation; and
[0037] FIG. 10 is a cross section of the light emission apparatus of the present invention in a third embodiment.
[0038] The present invention is applied to a bare chip of a multi-color LED allowing a ZnSe-based substrate to emit light, as shown in FIG. 2, placed on a resin base 3 having a patterned interconnection (an electrode) 4, with an indium layer 8 posed therebetween, and furthermore encapsulated with transparent resin 6.
[0039] Generally in packaging a LED it is encapsulated with resin by casting, injection (or transfer-molding), potting or other similar various techniques, although the transparent resin used is overwhelmingly epoxy resin, since epoxy resin is highly transparent, significantly strong, easy to handle, highly weather-resistant, and inexpensive.
[0040] However, if ZnSe-based LED (chip) 5, to which the present invention is applied, is encapsulated with a typical, thermosetting epoxy resin, such as resin having as high a glass transition temperature (Tg) as 120 degrees centigrade or more, then when the resin thermosetts and thus contracts it would introduce stress which is in turn exerted to the chip directly and, as shown in FIG. 3, in LED 5 the epitaxial light emission structure would crack 9. This contributes to rapidly reduced lifetime of the device.
[0041] This is a disadvantage unique to a crystallographically weak ZnSe-based LED 5 that would not be encountered by a typical LED using GaP or the like. Accordingly a first issue of the present invention to be addressed is to decrease stress of resin 6 to maintain in a lamp (a light emitting apparatus) a lifetime that a bare chip of ZnSe-based LED 5 inherently has.
[0042] Furthermore, in the LED 5, as has been described previously, indium serving as a soldering material is also used as a material for an ohmic electrode to reduce cost. In a typical process for mounting an LED this soldering material is a thermosetting, epoxy-based silver paste. As such, for the present LED, a totally different process is adopted.
[0043] Since the soldering indium has a significantly low melting point of approximately 155 degrees centigrade, it softens at a temperature close to Tg of no less than 120 degrees centigrade of the aforementioned, typical transparent resin.
[0044] In general to mount an LED lamp the lamp is required to undergo a reflowing process, a soldering process or other similar high-temperature processes. For the present LED at such a high temperature (e.g., 230 degrees centigrade), however, transparent encapsulating resin 6 would soften and the soldering indium would also start to melt.
[0045] Thus when it is exposed to the high temperature and furthermore in cooling it from the high temperature when the transparent resin and the soldering indium are solidifying, the LED chip therein can disadvantageously move, which does not occur when the soldering material is typical silver paste.
[0046] In particular, in cooling if the indium is still soft while the resin starts to solidify then stress is exerted to move the LED chip upwards and as a result the LED chip tends to float up from the indium electrode. Thus, as shown in FIG. 4, indium layer 8 internally has a void 10 or the like and a large series resistance component would be introduced. This has also disadvantageously increased a value in driving voltage of the LED lamp. A second issue to be addressed by the present invention is resolve this problem unique to indium solder.
[0047] In accordance with the present invention the present LED 5 is encapsulated with transparent resin 6 either having a glass transition temperature, corresponding to the softening point of the resin, which is sufficiently low, more specifically 80 degrees centigrade or less (preferably 30 to 80 degrees centigrade) or being soft to have elasticity even at room temperature (for example having an elongation exceeding 40%) to address the above two issues simultaneously.
[0048] Note that to allow resin 6 for example of epoxy resin to have a glass transition temperature of 80 degrees centigrade or less, a curing agent adjusted in ratio can be used to reduce crosslink density in the resin at curing or allows the resin to have a principal chain structure to be significantly macromolecular.
[0049] For the first issue of the decrease of stress affected to LED 5, the reduction of curing and contraction of resin 6 is effective. A well known technique to achieve this is use as resin 6 a thermoplastic resin having a low glass transition temperature in particular. For example, the present inventors, as disclosed in Japanese Patent Laying-Open No. 2000-101149, use low-Tg epoxy resin as means reducing stress influenced to a package of LED 5.
[0050] This technique, however, is intended to decrease stress between the package and resin 6. Furthermore, in general techniques, low-Tg resin is often used in order to prevent disconnection of wire or the like.
[0051] In the present invention this technique is applied in order to decrease a significantly small stress introduced between LED 5 and transparent resin 6 that has a level negligible for typical LED devices and it has been found that using transparent thermoplastic resin having a glass transition temperature of 80 degrees centigrade or less, epoxy resin in particular, can prevent the light emission apparatus from having an extremely reduced lifetime.
[0052] It has been found that a similar effect can be obtained by using soft resin which is elastic after it has cured, such as silicone resin (for example having an elongation of 200%) or epoxy acrylate resin (for example having an elongation of 50%), as resin 6 to prevent the light emission apparatus from having reduced lifetime.
[0053] In general, these soft resins have high moisture permeability and can thus result in device failure. Accordingly as a protection layer a hard transparent resin is further used to seal around the soft resin and this also has been found to allow a lamp structure free from reduction in life.
[0054] It has also been found from an experiment that the second issue of preventing series resistance in indium layer 8 that is introduced during a reflowing or other similar high-temperature processes can be prevented by changing a property of transparent resin 6.
[0055] As has been described previously, it had been known that the introduction of the series resistance is attributed to the fact that in a reflowing or other similar processes when temperature is reduced a chip receives a force floating it up. The force allowing the chip to float up is attributed to the fact that in exposure to high temperature the indium melts or is softened, while the resin starts to solidify.
[0056] It was considered that this can be prevented by encapsulating LED 5 with a resin which does not cure before indium sufficiently solidifies, i.e., a resin having a low glass transition temperature or a soft resin which still has elasticity at room temperature.
[0057] Accordingly an experiment was conducted and epoxy resin, silicone resin and the like having a Tg of 80 degrees centigrade or less and elastic epoxy acrylate resin were used to encapsulate LED 5, and it was found that indium layer 8 can be prevented from having increased resistance.
[0058] These encapsulating techniques are identical to that which has resolved the first issue and the above two issues can thus be addressed simultaneously.
[0059] While in the above experiment the LED is encapsulated with resin mainly by means of potting to observe whether stress to the package is reduced, it may alternatively be encapsulated for example by means of casting to obtain a similar effect.
[0060] Transfer-molding is not suitable for directly encapsulating the present ZnSe-based LED 5, since the Tg, type and the like of the resin used can hardly be changed. However, there is not a problem in using transfer-molding to seal LED 5 encapsulated with silicone or any other similar soft resin (junction coat resin) previously.
[0061] Thus the present technique allows use of an inexpensive process using transparent resin to encapsulate ordinary LED 5. Furthermore, resin 6 is not required to be transparent and it may have a light scattering medium mixed therein. Furthermore, the present technique does not impose any limitation on the geometry of the package.
[0062] Thus, with the above-described technique, an inexpensive technique using resin for encapsulating that is similar to a conventional technique can be used to fabricate a source of light of white color, and magenta, pink and any other similar neutral colors which are sufficiently reliable and have a variety of color tones.
[0063] Hereinafter reference will be made to FIGS. 5-10 to describe the present invention in embodiments.
[0064] First Embodiment
[0065] As shown in FIG. 5, on an iodine-doped, n-type ZnSe substrate 1 an epitaxial light emission structure 2 for blue color having a peaked emission wavelength of 485 nm is grown by homoepitaxy with an MBE method.
[0066] Epitaxial light emission structure 2 is composed of a p-type contact layer 15 having a superlattice structure of a stack of layers of ZnTe and ZnSe doped to be p-type, a p-type clad layer 14 formed of a layer of Zn0.85Mg0.15S0.10Se0.90 doped to be p-type, a single quantum well active layer 13 formed of a structure of a stack of a ZnSe layer and a Zn0.88Cd0.12Se layer, an n-type clad layer 12 formed of a Zn0.85Mg0.15S0.10Se0.90 layer doped to be n type, and an n-type ZnSe buffer layer 11.
[0067] On p-type contact layer 15 of the present epitaxial wafer, there is formed a patterned, p-type electrode formed of Ti/Au in a lattice, and there is further formed a full-surface covered Au electrode in a thin film of no more than 20 nm in thickness, and on ZnSe substrate 1 at a back surface thereof an n-type electrode formed of In is provided. After the electrode is formed, the epitaxial wafer is cut to be a chip (of type 1) sized to be 400 &mgr;m×400 &mgr;m and having a thickness of 200 &mgr;m. This chip is an LED chip of a type allowing white light to be emitted.
[0068] Furthermore, exactly the same procedure is used to form epitaxial light emission structure 2 on an Al-doped ZnSe substrate 1 for blue color having a peaked emission wavelength of 475 nm and cut the resultant product in the form of a chip (type 2). This chip is an LED chip of a type allowing pink light and magenta light to be emitted.
[0069] These chips were mounted on a stem of To-18 type having electrodes 16 and 17 and they were potted and thus encapsulated with resin in seven different manners.
[0070] Devices A (type 1) and A′ (type 2) were encapsulated with a typical transparent epoxy resin having Tg=120 degrees centigrade, devices B (type 1) and B′ (type 2) were encapsulated with transparent epoxy resin having Tg=80 degrees centigrade, devices C (type 1) and C′ (type 2) were encapsulated with transparent epoxy resin having Tg=60 degrees centigrade, devices D (type 1) and D′ (type 2) were encapsulated with transparent epoxy resin having Tg=40 degrees centigrade, devices E (type 1) and E′ (type 2) were encapsulated with silicone resin (gelled) having an elongation of 250%, devices F (type 1) and F′ (type 2) were encapsulated with epoxy acrylate resin having an elongation of 50%, and devices G (type 1) and G′ (type 2) are as shown in FIG. 7, having LED 5 immediately surrounded by and thus encapsulated with elastic silicone resin (junction coat resin) 18 and further encapsulated therearound with typical transparent resin (epoxy resin) 6 having Tg=120 degrees centigrade. Furthermore for reference were also prepared devices H (type 1) and H′ (type 2), which were products mounted without resin encapsulating them.
[0071] All of the devices encapsulated with resin initially had their operating voltages (Vf) measured. Thereafter, they were annealed at 250 degrees centigrade for ten seconds and thus thermally treated to correspond to a reflowing process and their operating voltages were furthermore examined to see how they vary. Subsequently, a reliability test was conducted. More specifically, the devices were operated at 60 degrees centigrade (to accelerate degradation) to observe how the differences in packaging affect the lifetimes of the devices.
[0072] Each device have an initial operating voltage when it is operated with 5 mA, a final operating voltage when it is operated with 5 mA after annealing process, and a half-life in luminance during the device is operated at 60 degrees centigrade with 5 mA, as shown in Table 1. 1 TABLE 1 Names of Samples A B C D E F G H Initial Vf for 2.45 2.44 2.46 2.45 2.43 2.47 2.45 2.45 5 mA (V) Vf after 2.62 2.49 2.45 2.46 2.45 2.45 2.46 2.45 annealing for 5 mA (V) Half-life in 0.4 690 900 970 1,250 1,100 920 1,000 luminance (h) Names of Samples A′ B′ C′ D′ E′ F′ G′ H′ Initial Vf 2.47 2.48 2.45 2.43 2.48 2.45 2.49 2.45 for 5 mA (V) Vf after 2.72 2.47 2.43 2.46 2.43 2.42 2.46 2.45 annealing for 5 mA (V) Half-life in 0.4 210 390 410 330 270 320 300 luminance (h)
[0073] It can be understood from Table 1 that after annealed at 250 degrees centigrade, only devices A and A′ are significantly increased in Vf, whereas the other devices hardly vary in Vf. That is, it has been found that using epoxy resin having Tg of lower than 80 degrees centigrade or resin still soft at room temperature to encapsulate LED 5 can prevent LED 5 from floating up due to annealing and can thus prevent Vf from increasing disadvantageously.
[0074] Furthermore, as compared to devices H and H′ in the form of a bare chip, only devices A and A′ are extremely reduced in lifetime, as can be seen from Table 1, while the other devices hardly have a problem. The lifetimes of devices B and B′, although somewhat reduced, are believed to be tolerable. From this result it has been found that using epoxy resin having Tg of lower than 80 degrees centigrade or resin still soft at room temperature to encapsulate LED 5 can also eliminate disadvantageously reduced lifetime in luminance.
[0075] Generally, it can be said throughout the experiment that there is not a difference at all between a chip for white color and that for pink, magenta or other similar color and that a ZnSe-based, multi-color light emitting chip that is encapsulated with epoxy resin having Tg of lower than 80 degrees centigrade can characteristically prevent Vf from disadvantageously increasing during a reflowing process and a lifetime in luminance from disadvantageously decreasing as the chip is encapsulated.
[0076] Furthermore in a similar experiment a device was encapsulated with transparent resin 6 having fine particles of 20% by weight of silica mixed therein as a light diffusing agent and exactly the same result was obtained.
[0077] Second Embodiment
[0078] There was prepared a chip similar to that of type 1 used in the first embodiment. The chip was mounted in a package having a reflector 19 that has a geometry as shown in FIG. 8 and the chip was potted and thus encapsulated with resin in five different manners.
[0079] A device I was encapsulated with a typical transparent epoxy resin having Tg=120 degrees centigrade, a device J was encapsulated with transparent epoxy resin having Tg=80 degrees centigrade, a device K was encapsulated with transparent epoxy resin having Tg=60 degrees centigrade, a device L was encapsulated with transparent epoxy resin having Tg=40 degrees centigrade, and a device M was as shown in FIG. 9, having LED 5 previously surrounded by and thus encapsulated with elastic silicone resin (junction coat resin) 18 of 150% in elongation and further encapsulated therearound with typical transparent resin (epoxy resin) 6 having Tg=120 degrees centigrade. Furthermore for reference was also prepared a device N, which is a product mounted without resin encapsulating it.
[0080] All of the devices encapsulated with resin initially had their respective Vfs measured and they then underwent a typical reflowing process (with a maximum temperature of 250 degrees centigrade for ten seconds) four times and then examined for any change in Vf. Subsequently, a reliability test was conducted. More specifically, they were operated at 60 degrees centigrade to accelerate degradation to see how the differences in packaging affect the lifetimes of the devices.
[0081] Each device has an initial operating voltage when it is operated with 5 mA, a final operating voltage when it is operated with 5 mA after the reflowing process, and a half-life in luminance during the device is operated at 60 degrees centigrade with 5 mA, as shown in Table 2. 2 TABLE 2 Names of Samples I J K L M N Initial Vf for 2.45 2.45 2.43 2.45 2.47 2.47 5 mA(V) Vf after reflowing for 5 2.66 2.46 2.44 2.46 2.45 2.47 mA (V) Half-life in luminance 2 690 1,050 920 840 800 h
[0082] It can be understood from Table 2 that by reflowing at 250 degrees centigrade, only device I is significantly increased in Vf, whereas the other devices hardly vary in Vf. That is, also in a package of a reflector type, as well as in the first embodiment, using epoxy resin having a Tg of lower than 80 degrees centigrade or resin still soft at room temperature to encapsulate seal LED 5 can prevent LED 5 from floating up due to a high-temperature reflowing process and can prevent Vf from increasing disadvantageously.
[0083] Furthermore, as compared to device N in the form of a bare chip, only device I is extremely reduced in lifetime, as can be seen from Table 2, while the other devices hardly have a problem. The lifetime of device J, although somewhat reduced, is tolerable.
[0084] From this result it has been found that using epoxy resin having Tg of lower than 80 degrees centigrade or resin still soft at room temperature to seal LED 5 can also eliminate disadvantageously reduced lifetime in luminance.
[0085] Third Embodiment
[0086] There was prepared a chip similar to that of type 1 used in the first embodiment. The chip was mounted on a flat package shaped as shown in FIG. 2 and it was transfer-molded and casted and thus encapsulated with resin in four different manners.
[0087] A device O is transfer-molded and thus encapsulated with resin with a typical transparent epoxy resin having Tg=130 degrees centigrade. A device P is encapsulated as shown in FIG. 10, having LED 5 previously encapsulated with elastic silicone resin (junction coat resin) 18 of 120% in elongation and furthermore transfer-molded and thus encapsulated therearound with typical transparent resin (epoxy resin) 6 having Tg=130 degrees centigrade. A device Q is casted and thus encapsulated with typical transparent epoxy resin having Tg=120 degrees centigrade. A device R is casted and thus encapsulated with transparent epoxy resin having Tg=50 degrees centigrade. Furthermore for reference there was also prepared a device S mounted without resin encapsulating.
[0088] They were transfer-molded using a resin molding die having a temperature of approximately 140 degrees centigrade, which is sufficiently lower than the melting point of indium. Furthermore in casting them a plastic case was used for molding resin and a rubber-based material was inserted at an interface of the case and the substrate to prevent the resin from leaking when it cures.
[0090] Each device has an initial operating voltage when it is operated with 5 mA, a final operating voltage when it is operated with 5 mA after the reflowing process, and a half-life in luminance during the device is operated at 60 degrees centigrade with 5 mA, as shown in Table 3. 3 TABLE 3 Names of Samples O P Q R S Initial Vf for 2.43 2.45 2.43 2.44 2.48 5 mA(V) Vf after reflowing for 5 2.74 2.44 2.64 2.46 2.46 mA (V) Half-life in luminance 310 710 8 790 800 (h)
[0091] It can be understood from Table 3 that by reflowing at 250 degrees centigrade, only devices O and Q are significantly increased in Vf, whereas the other devices hardly vary in Vf. That is, also in the flat package, as well as in the first embodiment, using epoxy resin having a Tg of lower than 80 degrees centigrade or resin still soft at room temperature to seal LED 5 can prevent LED 5 from floating up due to a high-temperature reflowing process and can prevent Vf from increasing disadvantageously.
[0092] Furthermore, as compared to device S in the form of a bare chip, device Q had an extremely reduced lifetime and device O had a lifetime reduced to no more than half, as can be read from the result. The other devices do not have a problem.
[0093] From this result it has also been found that using epoxy resin having Tg of lower than 80 degrees centigrade or resin still soft at room temperature to seal a vicinity of LED 5 can eliminate disadvantageously reduced lifetime in luminance.
[0094] As has been described above, in accordance with the present invention a resin having a glass transition temperature of lower than 80 degrees centigrade or soft resin still having elasticity after it has cured can be used to cover a light emitting device to prevent the device from degrading due to stress introduced when the resin encapsulating the device cures and contracts and also to prevent an indium layer from degrading and thus changing a value of driving voltage of the light emission apparatus. Furthermore, the device can be encapsulated with the resin, as described above, by a simple and inexpensive process.
[0095] Thus, a light emission apparatus emitting light of white color and magenta, pink and other similar neutral colors highly reliably in a variety of color tones, can be fabricated at low cost and can be expected to be significantly demanded in such applications as displaying in mobile gear, liquid crystal display's backlights, decoration and the like in particular.
[0096] Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.
1. A light emission apparatus comprising:
an electrode;
a light emitting device mounted on said electrode with an indium layer posed therebetween, said light emitting device having a substrate formed of an n-type ZnSe single crystal, and an epitaxial light emission structure formed of a compound crystal relating ZnSe serving as a matrix thereof, said epitaxial light emission structure being provided on said substrate and emitting light when an electric current is introduced thereinto; and
resin encapsulating said light emitting device, said resin having a glass transition temperature of lower than 80 degrees centigrade.
2. The apparatus of claim 1, wherein said resin includes epoxy resin having a glass transition temperature of higher than 30 degrees centigrade and lower than 80 degrees centigrade and being transparent or having a light diffusing agent mixed therein.
3. The apparatus of claim 1, further comprising a base formed of insulator, wherein said electrode includes a patterned electrode formed on said base.
4. The apparatus of claim 3, further comprising a reflector provided on said base to surround said light emitting device for reflecting fluorescence received from said substrate, wherein said resin is introduced into a region surrounded by said reflector.
resin encapsulating said light emitting device, said resin including a first resin transparent or having a light diffusing agent mixed therein, and covering said light emitting device, and a second resin transparent or having a light diffusing agent mixed therein, and covering said first resin, said first resin having an elasticity corresponding to an elongation of no less than 40% at room temperature, said second resin being grater in hardness than said first resin.
6. The apparatus of claim 5, wherein said first resin includes silicone resin and said second resin includes epoxy resin.
9. A method of fabricating a light emission apparatus, comprising the steps of:
mounting a light emitting device on an electrode with an indium layer posed therebetween, said light emitting device having a substrate formed of an n-type ZnSe single crystal, and an epitaxial light emission structure formed of a compound crystal relating ZnSe serving as a matrix thereof, said epitaxial light emission structure being provided on said substrate and emitting light when an electric current is introduced thereinto; and
dropping epoxy resin on said light emitting device and then curing said epoxy resin to encapsulate said light emitting device with said epoxy resin, said epoxy resin having a glass transition temperature of lower than 80 degrees centigrade.
10. A method of fabricating a light emission apparatus, comprising the steps of:
mounting a light emitting device on an electrode with an indium layer posed therebetween, said light emitting device having a substrate formed of an n-type ZnSe single crystal, and an epitaxial light emission structure formed of a compound crystal relating ZnSe serving as a matrix thereof, said epitaxial light emission structure being provided on said substrate and emitting light when an electric current is introduced thereinto;
covering said light emitting device with silicone resin; and
transfer-molding epoxy resin to cover said silicone resin therewith.
Patent Grant number: 6741029
Applicant: Sumitomo Electric Industries, Ltd. (Osaka)
Inventors: Hideki Matsubara (Osaka), Toshihiko Takebe (Itami-shi), Hiroki Ishinaga (Kyoto-shi), Mamoru Maegawa (Kyoto-shi)
Application Number: 10112323
Current U.S. Class: With Particular Phosphor Or Electrode Material (313/503)
International Classification: H01J001/62; H01J063/04;