text:
\section{INTRODUCTION}
Analog-to-digital converters (ADCs) bridge real-world analog signals and digital processors on which signals can be processed efficiently. Typically, ADCs measure instantaneous uniform samples of analog signals to represent them digitally. A key parameter in such conversion is the sampling rate. Power consumption and cost of an ADC increase with the increase in the sampling rate. Hence, keeping the sampling rate as low as possible is desirable. Theoretically, the sampling rate has to be greater than the Nyquist rate for perfect reconstruction of bandlimited signals. Apart from the sampling rate, there are several other aspects of an ADC which play a key role in faithful sampling and reconstruction, especially when the sampling frameworks are implemented in hardware.

The dynamic range of an ADC plays a crucial role in sampling an analog signal. Generally, ADC's dynamic range should be larger than the signal's; otherwise, the signal gets clipped. A few approaches exist to recover the true samples from clipped ones for bandlimited signals \cite{marks_clipping2, marks_clipping1}. These approaches rely on the correlation among the samples when they are measured at a very high rate compared to the Nyquist rate. The requirement of a high sampling rate is a drawback of these approaches.

Several preprocessing approaches to avoid clipping exist, such as automatic gain control (AGC) \cite{perez2011automatic,mercy1981review}, companding \cite{landau_compander,landau_distorted_bl}, and modulo folding \cite{uls_tsp,uls_romonov,bhandari2021unlimited,eyar_moduloicassp, azar2022robust}. Among these, modulo folding is the most recent approach that need not be differentiable like companding and does not suffer from stability issues of the feedback amplifiers used in AGCs. In the modulo framework, the signal is folded to lie within the ADC's dynamic range, and then the folded signal is sampled using a conventional ADC. Theoretical guarantees for recovering bandlimited signals from folded samples are presented in \cite{uls_tsp}. The results state that a bandlimited signal can be uniquely recovered from its folded samples provided that they are sampled above the Nyquist rate \cite{uls_tsp}.

Several algorithms for \emph{unfolding} or recovering the true samples of a bandlimited signal from a modulo or folded samples are presented in \cite{uls_tsp,uls_romonov, eyar_moduloicassp}. These unfolding algorithms can be compared in terms of sampling rate, amount of unfolding they can handle, and noise robustness. The algorithm proposed in \cite{uls_tsp} requires almost 17 times higher sampling rate than the Nyquist rate. The approaches in \cite{uls_romonov} and \cite{eyar_moduloicassp,azar2022robust} operate at relatively lower sampling rates but require the knowledge of ADC's dynamic range. In contrast, the method proposed in \cite{eyar_moduloicassp,azar2022robust} requires a lower sampling rate, even in the presence of noise, compared to the algorithms presented in \cite{uls_tsp,uls_romonov}. Modulo sampling is also extended to different problems and signal models such as periodic bandlimited signals \cite{bhandari2021unlimited}, finite-rate-of-innovation (FRI) signals \cite{uls_fri}, sparse vector recovery \cite{uls_sparsevec}, direction of arrival estimation \cite{uls_doa}, computed tomography \cite{uls_radon}, and graph signals \cite{uls_graph}.

Beyond theoretical works, there also exist a few related hardware prototypes. High-dynamic-range ADCs, also known as \emph{self-reset} ADCs, are discussed in the context of imaging \cite{sradc_park, sradc_sasagwa, sradc_yuan, krishna2019unlimited}. These hardware architectures measure additional information, such as the amount of folding for each sample or the sign of the folding together with the folded samples. The additional information might enable simpler recovery at the expense of complex circuitry. Importantly, additional bits are required during the quantization process to store or transmit the side information.

Krishna et al. presented a hardware prototype that encodes the side information by using two bits \cite{krishna2019unlimited}. The architecture is designed to record the sign of the slope of the signal at each sample that lies outside the ADC's dynamic range. In a conventional ADC, a sample and hold (S/H) circuit is used to hold the sampled value for a prescribed period of time, during which quantization is performed on the sample. A folding circuit is used after S/H  to realize the modulo sampling \cite{krishna2019unlimited}. In this architecture, the S/H circuit has to hold the sampled value for folding and quantization, resulting in a larger holding time than a conventional ADC. A large holding time results in slower ADCs, which may not be helpful in applications with high-frequency signals. The resulting hardware circuit is able to fold signals up to 300 Hz, where the signal's amplitude should be less than three times the ADC's dynamic range.

Modulo hardware prototypes where the modulo part is implemented prior to the sampler are presented in \cite{bhandari2021unlimited,Bhandari:2022:J,mod_hyst}.
In these works, the authors are focused on different signal models, hardware limitations, and algorithms rather than providing details of the hardware circuitry. It was shown that the modulo hardware is able to fold low-frequency ($<300$ Hz) signals that are tenfold larger than the ADC's dynamic range. However, it is not clear how the hardware performs for high-frequency signals, and many details of the circuitry are omitted.

In practical applications, the frequency range of the signals can vary from a few kHz to several MHz. For example, the finite-rate-of-innovation (FRI) model is widely used to represent signals in time-of-flight applications such as ultrasound, sonar, and radar \cite{vetterli,eldar_sos}. These FRI signals have frequencies much higher than 300 Hz, and hence current hardware prototypes can be used, especially when the signal's bandwidth ranges up to a few kHz. Hence it is desirable to design and develop a modulo sampler that can operate at high frequencies while folding signals faithfully.

In this paper, we present a modulo hardware prototype that can be used for modulo sampling of signals up to 10 kHz. We show that by using our algorithm \cite{eyar_moduloicassp}, it is able to reconstruct bandlimited and FRI signals faithfully.
In the following, we present the contributions and the features of the proposed hardware system.
\begin{itemize}
    \item We design our hardware components to be able to fold signals up to 10kHz. Existing hardware shows results for signals below 300 Hz.

    \item The hardware prototype is designed to perform folding prior to the sampler, unlike the hardware in \cite{krishna2019unlimited}, which operates in the hold part of the sampler.  Thus, the suggested system can utilize faster ADCs with shorter hold times.

    \item In the proposed hardware prototype, modulo folding is realized through a feedback mechanism. At the time instants when the input signal goes beyond the ADC's dynamic range, a trigger signal is generated by using comparators. The trigger then activates a direct voltage generator that adds to the input signal to bring it within the dynamic range. This mechanism imposes a delay between the trigger time and the folding instance. We address this key issue of the hardware, which is not considered in previous works.
    By using the signal's smoothness and the feedback loop's time delay,
    we propose a hardware solution to avoid clipping that occurs due to the delay issue.

    \item The designed hardware prototype can operate at a maximum voltage of 11.75 v. The limitation is largely due to the use of a 15v subtractor or adder in the feedback loop, which enables a fast slew rate in the transitions of $\pm 2\lambda$. At high frequencies, these components can not be used at voltage above 15 v. In addition, we used an ADC with a dynamic range $[-1.25, 1.25]$. Hence, the hardware can fold signals which are eight times larger than the dynamic range of the signal.

    \item For demonstration, we consider sampling and reconstruction of bandlimited and FRI signals. For FRI signals, we use a lowpass sampling kernel prior to modulo folding. The filter removes unwanted information in the signal and allows sub-Nyquist sampling. Using our algorithm presented in \cite{eyar_moduloicassp,azar2022robust}, we show reconstruction of bandlimited signals from their folded samples measured through the hardware. We show that the combination of the proposed hardware and low-rate algorithm is able to reconstruct the signals by using a low-dynamic range ADC. In particular, for FRI signals, we show that the FRI parameters can be estimated with sub-Nyquist samples by utilizing the fact that our algorithm operates at the lowest possible rate.

\end{itemize}

The paper is organized as follows. In the next section, we discuss the signal model considered and the sampling and reconstruction framework in the presence of modulo hardware. In Section III, we present the hardware system by explaining its working principle and discussing the components of the system. In Section IV, we show the hardware's signal folding and reconstruction abilities.

\section{Signal Model and System Description}
\begin{figure*}
	\centering
	\includegraphics[width=4 in]{Figs/BL_US}
	\caption{A schematic of modulo-sampling and reconstruction of bandlimited signals.}
	\label{fig:bl_framework}
\end{figure*}
In this section, we consider modulo sampling for signals whose amplitudes lie beyond the bandwidth of the ADC's dynamic range. The class of signals that can be folded by modulo hardware can be very large; however, the recovery is limited by existing unfolding algorithms. For example, most unfolding algorithms are designed for bandlimited signals. Given this, we consider bandlimited signals as input to the modulo hardware and corresponding unfolding algorithms. We use a lowpass sampling kernel for FRI signals to make them bandlimited and, at the same time, reduce the sampling rate following the sub-Nyquist framework \cite{eldar_sos, mulleti_kernal}.

Consider a $\omega_c$-bandlimited signal $y(t)$ such that its Fourier transform $Y(\omega)$ vanishes outside the frequency interval $[-\omega_c, \omega_c]$. The signal can be perfectly reconstructed from its uniform samples measured at the Nyquist rate $\omega_{Nyq} = 2\omega_c$ rad/sec. provided that the ADC's dynamic range is above the signal's dynamic range. Specifically, if the dynamic range of the ADC is $[-\lambda, \lambda]$ for some $\lambda >0$ then it is assumed that $|y(t)|\leq \lambda$ for perfect reconstruction. If $|y(t)|>\lambda$, then the signal and its samples will be clipped, and perfect reconstruction is not guaranteed. In the latter scenario where $|y(t)|>\lambda$, one can either increase the dynamic range of the ADC or use prepossessing to avoid clipping. We consider the later solution where the modulo operation $\mathcal{M}_{\lambda}(\cdot)$ is applied to the signal $y(t)$ to restrict its dynamic range to $[-\lambda, \lambda]$. The output of the modulo operator in response to input $y(t)$ is given as
\begin{equation}
 y_\lambda(t) =	\mathcal{M}_{\lambda}(y(t)) = (y(t)+\lambda)\,\, \text{mod}\,\, 2\lambda -\lambda.
	\label{eq:mod_opp}
\end{equation}
The folded signal $y_\lambda(t)$ is then sampled to get discrete measurements $y_\lambda(nT_s)$. Due to modulo folding, $y_\lambda(t)$ is no longer bandlimited. To recover $y(t)$ while sampling slightly above the Nyquist rate of the input, one first applies an unfolding algorithm to recover $y(nT_s)$ from $y_\lambda(nT_s)$ \cite{eyar_moduloicassp,azar2022robust,mulleti2022modulo}. Then $y(t)$ is reconstructed from $y(nT_s)$ by assuming that the sampling is performed above the Nyquist rate.

A schematic of modulo sampling and reconstruction framework is shown in Fig.~\ref{fig:bl_framework}. It consists of a modulo-ADC followed by unfolding and reconstruction blocks. The modulo-ADC is comprised of a modulo-folding block followed by a conventional uniform sampler. The unfolding operation is implemented in the digital domain, and it should operate at the lowest possible sampling rate. To this end, we use the $B^2R^2$ algorithm for unfolding \cite{eyar_moduloicassp,azar2022robust}, which samples efficiently compared to other algorithms for bandlimited signals. Low-rate sampling and low-dynamic range requirements significantly reduce the power consumption and cost of the ADC.

Our objective is to demonstrate a robust hardware prototype of modulo ADC as discussed next.

\begin{figure}
	\centering
	\includegraphics[width= 3 in]{Figs/folding}
	\caption{Folding principle.}
	\label{Fig:folding}
\end{figure}
\section{Modulo Hardware Prototype}
In this section, we discuss the prototype of our modulo hardware. The modulo block's working principle and design will be discussed first, followed by its hardware implementation.
\subsection{Working Principle of Modulo Block}
The principle of computing $y_\lambda(t)$ from $y(t)$ is shown by the block diagram in Fig.~\ref{Fig:folding}. The system comprises an adder $S$, a direct-voltage generator (DVG), and two comparators, Comp-1 and Comp-2. To understand the working flow, let us first assume that for some time instant $t_1$, we have that $|y(t)|<\lambda$ for all $t<t_1$. Hence $y_\lambda(t) = y(t)$ and $z(t) = 0$ for all $t<t_1$. At $t=t_1$, let $|y(t)|$ cross $\lambda$. If $y(t_1)>\lambda$, then Comp-1 triggers a positive value. Else if, $y(t_1)<\lambda$, Comp-2 triggers a negative value. The DVG is designed such that for each positive input value, its output signal level increases by $-2\lambda$, whereas, for a negative input value, it decreases its output voltage by $2\lambda$. Hence, in the current example, DVG generates a signal $z(t) = \text{sgn}(y_\lambda(t_1)) 2\lambda u(t-t_1)$ where $u(t)$ is the unit-step function. In this way, by adding or subtracting (using $S$) constant DC signals from $y(t)$ whenever it crosses the dynamic range $[-\lambda, \lambda]$, the amplitude levels of $y_\lambda(t)$ are kept within the ADC's dynamic range.

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3 in]{Figs/dc_vg}
	\caption{Discrete Voltage Generator (DVG).}
	\label{Fig:dcvg}
\end{figure}

\begin{figure*}[!t]
	\centering
	\includegraphics[width=0.86\textwidth ]{Figs/UDR_Board_Labeled3.PNG}
	\caption{Modulo hardware board.}
	\label{Fig:hw_board}
\end{figure*}

While the parts such as comparators Comp-1 and Comp-2, and adder $S$ can be realized by using off-the-shelf components, DVG is a more involved system due to its feedback nature and requires careful design. Specifically, the feedback loop should follow changes in the input signal in the desired frequency and amplitude ranges. A detailed architecture of DVG is shown in Fig.~\ref{Fig:dcvg}. Its task is to generate a constant voltage signal whose amplitude is a constant multiple of $2\lambda$. Importantly, its output voltage $z(t)$ should increase (or decrease) by $2\lambda$ v for every negative (or positive trigger) at its input. To realize this task in the hardware, we use an up/down counter, a digital-to-analog converter (DAC), a multiplexer (MUX), and a multiplier $M$.

In the hardware design, we set $\lambda = 1.25$ v.
We start with the DAC, which can generate piecewise constant voltage output $s(t)$ in response to its digital input. Let the resolution, or step size of the DAC, be $\alpha$ v. Then, when the input bits of DAC go from one state to the next, the DAC output increases by $\alpha$ v. On the other hand, when the bits change from the present state to the previous state, output voltage $s(t)$ reduces by $\alpha$ v. Hence, the ADC works in a fashion expected by DVG with the following exceptions: (1) Input to the DAC is bits and one needs to map positive/negative trigger from comparators to these bits; (2) Output of the DAC takes only positive values and are multiple of $\alpha$. A scaling is required to make them multiple of $\pm 2\lambda$. To address the first issue, we employ a UP/DOWN counter whose inputs are the trigger voltages from the capacitors Comp-1 and Comp-2, and the output is bits. For every positive trigger at the input counter, output bits change to the next state, whereas for a negative trigger, they go back to the previous state. By connecting these bits to the input of the DAC, the output of the DAC is controlled by triggers.

To address the scaling issue, we use a MUX and a voltage multiplier $M$. The MUX and the multiplier are designed, together with a set of amplifiers, such that $s(t)$ is scaled to $z(t)$. A sign bit at the output of the counter, which is a function of the trigger's sign, is used as input to the MUX, which in turn controls the sign of the multiplier's output or $z(t)$'s sign.

To explain the sequences of events in DVG, let us consider our previous scenario where $|y(t)| <\lambda$ for some $t<t_1$ and at $t_1$, $|y(t)|$ crosses $\lambda$. For $t<t_1$, we have $y(t) = y_\lambda(t)$, $s(t) = 0$, $z(t) = 0$, and all the output bits of the counter are set to be zero. If $y(t_1)> \lambda$, Comp-1 triggers a positive voltage, and the counter's output bits state changes. Specifically, the least significant bit changes to one, and in response, the DAC's output voltage changes to $\alpha$ v. Meanwhile, after the positive trigger, the MUX outputs a voltage $-2\lambda/\alpha$ which is multiplied to $s(t)$ and outputs $z(t)$ as $-2\lambda u(t-t_1)$ as desired.

Next, we discuss the hardware board that realizes the folding operation discussed in this section.

\begin{table}[h!]
\centering
\caption{List of Hardware Components}
\label{table:hardware_components}
\begin{tabular}{||c c c||}
 \hline
 Component & Model Number & Make \\
 && \\ \hline
 Comparator & LM339 & Texas Instruments \\
 && \\
 UP/DOWN Counter & TEENSY4.1 & PJRC \\
 && \\

 Analog MUX & ADG1608 & Analog Devices \\
 && \\
 Analog Multiplier & AD835 & Analog Devices \\
 && \\
 Adder & LT1364 & Analog Devices \\
  && \\ [1ex]
\hline
\end{tabular}
\end{table}

\begin{table}[h!]
		\caption{Up/down counter operation.}
	\centering
	\begin{tabular}{||c c c c c c c||}
		\hline
		c & b & a & sgn & Counter values & $s(t)$ & $z(t)$  \\ [0.5ex]
		\hline\hline
		0 & 0 & 0 & 0~(1) & 0~(0) & 0 & 0  \\
		0 & 0 & 1 & 0~(1) & 1~(-1) & 1 & $2\lambda$ ($-2\lambda$)\\
		0 & 1 & 0 & 0~(1) & 2~(-2) & 2 & $4\lambda$ ($-4\lambda$)\\
		0 & 1 & 1 & 0~(1) & 3~(-3) & 3 & $6\lambda$ ($-6\lambda$)\\
		1 & 0 & 0 & 0~(1) & 4~(-3) & 4 & $8\lambda$ ($-8\lambda$)\\

		\hline
	\end{tabular}
	\label{table:counter}
\end{table}

\begin{figure}[!t]
	\centering
      \begin{tabular}{c}

	\subfigure[] {\includegraphics[width= 3.2 in]{Figs/Fig6_1KHz_10Vpp_4Folding_New_Clr.png}}\label{fig:2fold}\\
 \subfigure[] {\includegraphics[width= 3.2 in]{Figs/UDR_4_folds_2KHz.png}}\label{fig:4fold}

 \end{tabular}
 \caption{Screenshots of an oscilloscope capturing input signals (yellow), its folded outputs (green), and the DVG signals (blue): (a) 1kHz sinusoid with maximum amplitude $4\lambda$ and (a) 2kHz sinusoid with maximum amplitude $8\lambda$.}
	\label{Fig:Analysis_of_folding_ability}
\end{figure}

\begin{figure}[!h]
	\centering
	\begin{tabular}{c}
		\subfigure[] {\includegraphics[width=3.2in]{Figs/Fig7_1Folding_6Vpp_1KHz_New_Clr.png}\label{fig:1k_1}} \\
		\subfigure[] {\includegraphics[width=3.2in]{Figs/Fig7_1Folding_6Vpp_10KHz_New_Clr.png}\label{fig:10k_1}} \\
		\subfigure[] {\includegraphics[width=3.2in]{Figs/Fig7_1Folding_6Vpp_20KHz_New_Clr.png}\label{fig:20k_1}}
	\end{tabular}
	\caption{Analysis of frequency response of the modulo hardware (a)-(c) denote the real-time capture of an oscilloscope capturing the 1kHz, 10kHz, 20kHz, respectively, the sinusoidal input signal (yellow), its folded output (green), the DVG signal (blue).}
	\label{Fig:frequency_response}
\end{figure}

\subsection{Modulo Hardware Board}
Our modulo hardware board is presented in Fig.~\ref{Fig:hw_board}, along with the roles of the major building components. Table~\ref{table:hardware_components} contains a detailed listing of the hardware's components. The board is designed for $\lambda = 1.25$ v. While selecting components for the MUX, multiplier, and amplifiers involved, we observe that these components operate in their linear regions if the operating voltages are less than 12 v. This implies that $|z(t)|\leq 12$ v which limits the maximum value of input signal to $|y(t)| < 9\lambda = 11.75$ v. This is because if $y(t)$ crosses $9\lambda$ then $z(t)$ should be $-10\lambda = 12.5$ v to ensure that $y_\lambda = y(t) + z(t) \in [-\lambda, \lambda]$. Hence, the current design of the hardware can fold and sample signals eight times larger than ADC's dynamic range. This implies that the DVG output should take values from the set $\{0, \pm 2\lambda, \pm 4\lambda, \pm 6\lambda, \pm 8\lambda \}$. This requires the DAC to have five uniform voltage levels at its output (it produces only positive voltages), and a  3-bit DAC and hence a 3-bit counter are used as shown in Fig.~\ref{Fig:dcvg}. Instead of using an off-the-shelf DAC, we build a customized DAC for the hardware. By noting the DAC's output is a linear combination of its three input bits, we used adders LT1364 to realize the DAC. In Table~\ref{table:counter}, we list the values of bits and the counter (denoted as counter values). The three bits (a,b, and c) of the counter are used as input to the DAC, which converts the bits to an analog DC voltage. Here the resolution of the DAC is $\alpha = 1$ v.

We further analyze the working of the modulo hardware by considering a sinusoidal signal $y(t) = A\, \sin(2\pi f_0 t)$ where $A$ is amplitude, and $f_0$ is the frequency (in Hz). In this experiment, we set $\lambda = 1.25$. First, we analyze the folding ability of the hardware for different amplitude levels. Figure~\ref{Fig:Analysis_of_folding_ability}(a) and (b) depict screenshots of an oscilloscope capturing input $y(t)$ (in yellow), folded output $y_\lambda(t)$ (in green), and the DVG output $z(t)$ (in blue), for two signals with $f_0 = 1$ kHz, $A = 4\lambda$ and $f_0 = 2$ kHz, $A = 8\lambda$, respectively. We observed that the signals are folded back to lie within the dynamic range of the ADC as expected without clipping.

Next, we discuss the frequency response of the modulo ADC. As in any analog system, the modulo folder's response also depends on the input signal's frequency or bandwidth. In particular, beyond a particular frequency range, components of the hardware and the overall feedback loop may not respond quickly to fast changes in the input signal, as demonstrated in Fig.~\ref{Fig:frequency_response}. We observed that for 1kHz and 10 kHz, the hardware folds the signal accurately. However, for $f_0 = 20$ kHz, folding instants are not symmetric for positive and negative folds.

In the next section, we discuss several challenges of the modulo hardware and our proposed solutions.

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3.2 in]{Figs/mod_td}
	\caption{Effect of the time delay of the feedback loop on the modulo operation.}
	\label{Fig:mod_td}
\end{figure}

\subsection{Artifacts During Folding}
Errors or other artifacts that arise during folding operations in hardware result from various reasons. One of the major issues that arise in a modulo ADC is the time delay in the feedback loop (See Fig.~\ref{Fig:folding}). To elaborate, consider a scenario where $y(t)<\lambda$ for $t<t_1$ and it crosses $\lambda$ at time $t_1$. To fold the output voltage to the dynamic range of the ADC, $z(t) = 2\lambda u(t-t_1)$ needs to be subtracted from $y(t)$. However, there is a finite delay between the trigger time $t_1$ to generating $z(t)$. If the time delay is $T_d$, then $z(t) = 2\lambda u(t-t_1-T_d)$ is subtracted, which causes distortion. To illustrate this effect, in Fig.~\ref{Fig:mod_td}, we considered a sinusoidal signal (in blue) and its folded versions with and without delay. We observe that in the absence of any time delay ($T_d=0$) the signal folds perfectly (shown in red) to stay within the dynamic range. However, for a non-zero value of $T_d$, foldings do not take place at the folding instants, and the output of the modulo operator (shown in black) still remains outside the dynamic range $[-\lambda, \lambda]$, which results in a clipped modulo operator output. The proposed hardware solution addresses this issue and avoids the undesired clipping as shown in Figs.~\ref{Fig:Analysis_of_folding_ability} and \ref{Fig:frequency_response}.

Our solution uses the fact that with a finite time delay, the amount of overshoot of a smooth signal can be bounded. To elaborate, assume that the signal that undergoes the modulo operation is Lipschitz continuous. Specifically, a signal $y(t)$ is Lipschitz continuous if there exists a positive real number $\mathrm{L}_y$ such that for any $T>0$ we have
\begin{align}
    |y(t) -y(t+T)|\leq \mathrm{L}_y\, T.
    \label{eq:lipschitz}
\end{align}
With the Lipschitz smoothness condition, we note that the amplitude of $y(t)$ can not change more than $\mathrm{L}_y\, T_d$ between any folding instant and time of its effect to take place. Hence, if we choose the dynamic range of the ADC to be $[-(\lambda+\Delta \lambda), (\lambda+\Delta \lambda)]$ where $\Delta \lambda = \mathrm{L}_y\, T_d$ then the signal will not clip. We show this extended dynamic region in the example in Fig.~\ref{Fig:mod_td}. Alternatively, instead of increasing the ADC's dynamic range, one can keep it to be $[-\lambda, \lambda]$ and reduce the threshold values for comparators. In this case, Comp-1 will trigger when the input crosses $\lambda-\Delta \lambda$, and Comp-2 will trigger when the input goes beyond $-\lambda+\Delta \lambda$. In this way, the time delay issue is addressed by the modulo circuit without altering ADC's dynamic range. In our hardware, we choose the former solution. Specifically, we used an oscilloscope to measure and display samples. The dynamic range of the oscilloscope's ADC was sufficiently higher than $[-\lambda, \lambda]$ to sample signals of interest without clipping signals due to the delay in the feedback loop.

In order to apply the solution, the signal must be Lipschitz continuous. In our design, the modulo operation input signal is always a bandlimited signal satisfying the Lipschitz smoothness condition \cite{bl_bound}. For a bandlimited signal $y(t)$, its Lipschitz constant $\mathrm{L}_y$ is directly proportional to its bandwidth $\omega_c$ \cite{bl_bound}. Hence, for a given value $\Delta \lambda$ and $T_d$ (both depend on the modulo circuit), $\mathrm{L}_y = \Delta \lambda/T_d$ is fixed and this restricts the maximum frequency of the input signal that can be faithfully folded. In the current design, we choose to implement the counter management using a TEENSY microcontroller, resulting in a $1 \mu$s time delay. Then for a sinusoidal signal $y(t) = A \sin(2\pi f_0 t)$, the Lipschitz constant is given as $L_y = 2\pi A f_0$. For $A = 8\lambda$, $\Delta \lambda = 0.5 \lambda$, and $T_d = 1 \mu$s, we note that the maximum operating frequency is 10 kHz which is in line with the experimental results discussed in Fig. \ref{Fig:frequency_response}.

\section{Results}
In this section, we demonstrate the modulo hardware's signal reconstruction capability. We focus on the folding and reconstruction of bandlimited and FRI signals. In the hardware, the folded measurements are generally  contaminated by different noises, including quantization noise. Since the performance of an unfolding algorithm depends on the noise levels, we first discuss a few simulated results to assess the performance of the $B^2R^2$ algorithm used for unfolding. Then we demonstrate the results from the hardware.

\begin{figure}[!t]
	\centering
	\includegraphics[width= 2.5 in]{Figs/quantization.png}
	\caption{Comparison of HOD, CPF, and $B^2R^2$ algorithms after the quantization process in terms of MSE when recovering a bandlimited signal from modulo samples with $\lambda = 1.25$ and OF = 3,6. For a given number of bits, $B^2R^2$ has the lowest MSE.}
	\label{Fig:quantization}
\end{figure}

\begin{figure}[!t]
	\centering
	\includegraphics[width= 2.5 in]{Figs/Gaussian.png}
	\caption{Comparison of HOD, CPF and $B^2R^2$ algorithms (with unbounded noise) in terms of MSE when recovering a bandlimited signal from modulo samples with  $\lambda$ = 1.25 and OF = 3,6. For a given SNR and OF, $B^2R^2$ has the lowest MSE.}
	\label{Fig:unbounded}
\end{figure}
\subsection{Simulated Results}
In this section, we compare our $B^2R^2$ algorithm with the \emph{higher-order differences} (HOD) approach \cite{unlimited_sampling17, uls_tsp} and \emph{Chebyshev polynomial filter}-based (CPF) method \cite{uls_romonov}. Although a comparison of these methods is analyzed in \cite{eyar_moduloicassp}, the settings are different here. Importantly, quantization noise is not considered in our previous work.

We consider the noisy measurements as
\begin{align}
            \tilde{y}_{\lambda}(n T_s) = {y}_{\lambda}(n T_s) + v(n T_s),
        \label{eq: noisy_samples}
        \end{align}
where $v(n T_s)$ is the noise term. In the simulations, $\lambda$ is set to be $1.25$ as in the hardware. We normalize the bandlimited signals to have a maximum amplitude of $10$. The SNR is calculated as $\text{SNR} = 20 \log\left(\frac{||y_{\lambda}(n T_s)||}{||v(n T_s)||}\right)$. Reconstruction accuracies of different methods are compared in terms of the normalized mean-squared errors (MSEs) as $ \frac{\sum |y(nT_s) - \hat{y}(n Ts)|^2}{\sum |y(nT_s)|^2}$, where $\hat{y}(n T_s)$ is an estimate of $y(n T_s)$. For different noise settings and over-sampling factors (OFs), we considered 100 independent noise realizations and calculated the average MSE for them. We first consider quantization noise and then present results for unbounded noise.
\begin{figure}[!t]
    \centering
    \includegraphics[width=0.3\textwidth]{Figs/SignalGenerator.png}
    \caption{Bandlimited signal generator.}
    \label{fig:UDRSignalGen}
\end{figure}

 In the first simulation, the unfolding algorithms are applied to quantized folded samples. The MSE in the estimation of bandlimited signals for a different number of bits and OFs is shown in Fig. ~\ref{Fig:quantization}. We observe that for a given $\text{OF}$, $B^2R^2$ algorithm results in the lowest MSE for less than 5 bits. For more than five bits, all the algorithms, except HOD with OF = 3, perform equally well. The results show that low-resolution quantizers can be used with the $B^2R^2$ algorithm for unfolding, which saves both power and memory requirements.

Next, for unbounded noise, we assume that the noise samples $v(nT_s)$ are independent and identically distributed Gaussian random variables with zero means. The variance of $v(nT_s)$ is set to achieve the desired SNR. We compare the methods for different values of SNR and OFs with $\lambda = 1.25$. Fig.~\ref{Fig:unbounded} shows the MSE of the different algorithms for OF $= 3$ and $6$. We note that our algorithm results in the lowest error for a given OF and SNR.

Given the advantages of the $B^2R^2$ algorithm over the other approaches, we present the hardware results in the next section by using this method.

\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[]{\includegraphics[width=3.2in]{Figs/BL1_scope_11_Clr.png}\label{fig:BL1_scope}} \\
		\subfigure[]{\includegraphics[width=3.2in]{Figs/BL2_scope_13_Clr.png}\label{fig:BL2_scope}}
	\end{tabular}
	\caption{Screenshots of the oscilloscope capturing the bandlimited input signals (yellow) and its folded output signals (green).}
	\label{fig:BL_scopeex1}
\end{figure}
\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[]{\includegraphics[width=3.2in]{Figs/BL1_rec.png}\label{fig:BL1}} \\
		\subfigure[]{\includegraphics[width=3.2in]{Figs/BL2_rec.png}\label{fig:BL2}}
	\end{tabular}
	\caption{Hardware results for bandlimited signals. The $B^2R^2$ algorithm is used to unfold $y_\lambda(t)$ (measured at the output of hardware), and the unfolded signal $\hat{y}(t)$ is plotted with bandlimited signal $y(t)$.}
	\label{fig:BL_ex1}
\end{figure}

\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[Screenshot of the oscilloscope capturing filtered FRI signal (yellow), its folded output (green), and the DVG signal (blue).] {\includegraphics[width=3.2in]{Figs/FRI1_1_Clr.png}\label{fig:FRI1_1k}} \\
		\subfigure[Filtered FRI signal with its folded and unfolded versions.]{\includegraphics[width=3.2in]{Figs/Ex1_lpf.pdf}\label{fig:FRI_LPF1}}\\
		\subfigure[FRI signal reconstruction.] {\includegraphics[width=3.2in]{Figs/Ex1_fri.pdf}\label{fig:FRI1_REC}} \\

	\end{tabular}
	\caption{Reconstruction of FRI signal ($L=2$) via the modulo hardware.}
	\label{Fig:FRI1}
\end{figure}

\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[Screenshot of the oscilloscope capturing filtered FRI signal (yellow), its folded output (green), and the DVG signal (blue).] {\includegraphics[width=3.2in]{Figs/FRI2_1_Clr.png}\label{fig:FRI2_1k}} \\
		\subfigure[Filtered FRI signal with its folded and unfolded versions.]{\includegraphics[width=3.2in]{Figs/Ex2_lpf.pdf}\label{fig:FRI_LPF2}}\\
		\subfigure[FRI signal reconstruction.] {\includegraphics[width=3.2in]{Figs/Ex2_fri.pdf}\label{fig:FRI2_REC}} \\
	\end{tabular}
	\caption{Reconstruction of FRI signal ($L=3$) via the modulo hardware.}
	\label{Fig:FRI2}
\end{figure}

\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[Screenshot of the oscilloscope capturing filtered FRI signal (yellow), its folded output (green), and the DVG signal (blue).] {\includegraphics[width=3.2in]{Figs/FRI3_1_Clr.png}\label{fig:FRI3_1k}} \\
		\subfigure[Filtered FRI signal with its folded and unfolded versions.]{\includegraphics[width=3.2in]{Figs/Ex3_lpf.pdf}\label{fig:FRI_LPF3}}\\
		\subfigure[FRI signal reconstruction.] {\includegraphics[width=3.2in]{Figs/Ex3_fri.pdf}\label{fig:FRI3_REC}} \\

	\end{tabular}
	\caption{Reconstruction of FRI signal ($L=5$) via the modulo hardware.}
	\label{Fig:FRI3}
\end{figure}

\subsection{Hardware Results for Bandlimited Signals}
In this section, we first present results for bandlimited signals. For generating bandlimited or lowpass signals, we used an Arduino microcontroller (See Fig.~\ref{fig:UDRSignalGen}) which converts the digital signal to an analog signal via a DAC. The digital signals were generated using MATLAB software. Two examples of 1khz bandlimited signal are presented in Fig. \ref{fig:BL1_scope} and Fig. \ref{fig:BL2_scope}. The modulo hardware folds the signals to stay within the dynamic range, as shown in Fig.~\ref{fig:BL_scopeex1}. The signals are sampled with an oversampling factor of five ($\text{OF}=5$), and the $B^2R^2$ algorithm is applied for unfolding. The unfolded or reconstructed signals are shown in Fig.~\ref{fig:BL_ex1}. We observe that the reconstruction is close to the true signals except for an amplitude scaling factor, which is the result of scaling within the hardware.

\subsection{Hardware Results for FRI Signals}
Before presenting the results for FRI signals, we briefly discuss the FRI signal model and its sampling and reconstruction mechanism for ease of discussion.
Consider an FRI signal consisting of a stream of $L$ pulses:
\begin{align}
	f(t) = \sum_{\ell=1}^L a_\ell h(t-t_\ell),
	\label{eq:fri1}
\end{align}
where the pulse $h(t)$ a real-valued known pulse. We assume that $\{a_\ell\}_{\ell = 1}^L$ are real-valued and $\{t_\ell\}_{\ell = 1}^L \subset (0, T_0] \subset \mathbb{R}$ for a known $T_0$.

The FRI signal model in \eqref{eq:fri1} is encountered in several scientific applications such as radar imaging \cite{bar_radar, bajwa_radar, sunil}, ultrasound imaging \cite{eldar_sos,eldar_beamforming,mulleti_icip}, light detection and ranging (LIDAR) \cite{castorena_lidar}, time-domain optical coherence tomography (TDOCT) \cite{blu_oct}, and other time-of-flight imaging systems. In these applications,  $h(t)$ is the transmitted pulse and $\{a_\ell \,h(t-t_\ell)\}_{\ell=1}^{L}$ constitute the reflections from $L$ point targets. The amplitudes $\{a_\ell\}_{\ell = 1}^L$ depend on the sizes of the targets and the delays $\{t_\ell\}_{\ell = 1}^L$ are proportional to the distances of the targets from the transmitter. Here $T_0$ denotes the maximum time delay of the targets. The signal $f(t)$ is specified by $\{a_\ell, t_\ell\}_{\ell=1}^L$ and can be reconstructed from its sub-Nyquist measurements acquired using an appropriate sampling kernel \cite{vetterli,eldar_sos,fri_strang, mulleti_kernal}. Given their widespread application, here we consider sampling and reconstruction of FRI signals by using our hardware prototype.

FRI signals can be perfectly reconstructed by applying high-resolution spectral estimation methods, such as the annihilating filter (AF) or Prony's method and its variants
\cite{prony, plonka, schmidt_music, barabell_rmusic, bdrao_rmusic,sarkar_mp,paulraj_esprit} to the Fourier measurements
\begin{align}
	S(k\omega_0) = \frac{F(k\omega_0)}{H(k\omega_0)} =  \sum_{\ell = 1}^L a_\ell \, e^{-\mathrm{j}k\omega_0 t_\ell}, \, k \in \{-K, \cdots, K\},
	\label{eq:Skomega}
\end{align}
where we assume that $H(k \omega_0) \neq 0$. Here $K \geq L$ and $\omega_0 = \frac{2\pi}{T_0}$ \cite{eldar_2015sampling}. The Fourier measurements $\{S(k\omega_0)\}_{k =-K}^K$ can be determined from the samples $(f*g)(nT_s)$ where $g(t)$ is an ideal lowpass filter with bandwidth $[-K\omega_0, K \omega_0]$ and $T_s = \frac{2\pi}{(2K+1)\omega_0}$. In practice, the duration of the pulse $h(t)$ is very short, and hence $f(t)$ has a wide bandwidth. This results in a large sampling rate (or Nyquist rate) if $f(t)$ is sampled directly. However, the filtered signal $y(t) = (f*g)(t)$ is bandlimited to $[-K\omega_0, K \omega_0]$, which is much smaller than that of $h(t)$ and the sampling rate is much lower than the Nyquist rate.

As in the bandlimited signal model, a modulo operation can be applied to the filtered signal $y(t)$ to avoid clipping. Then $y_\lambda(t)$ is sampled. Then to determine the Fourier samples $\{S(k\omega_0)\}_{k =-K}^K$, unfolding is first applied. Since the filtered signal is bandlimited, we use the proposed hardware for modulo folding and can apply the $B^2R^2$ algorithm from unfolding.

In our setup, to generate the FRI signals, we consider $h(t)$ to be a short pulse of bandwidth 30kHz (Nyquist rate = 60kHz). We consider three examples with $L=2, 3,$ and 5. The amplitudes and time delays are generated randomly. The maximum time delay is $T_0 = 0.1$ sec. Once generated, the FRI signal is lowpass filtered with a cutoff frequency of 1kHz. MATLAB is used to generate the samples of filtered FRI signals and then an Arduino microcontroller is used to generate the analog counterpart of them. The signal is then folded using the hardware, and the folded signals are sampled. The sampling rate is 10kHz which is five times higher than the sampling rate of the lowpass signal. Still, the rate is six times lower than the Nyquist rate, and hence the system operates at a sub-Nyquist rate.

We first applied the $B^2R^2$ algorithm to unfold the signal and then used ESPRIT \cite{paulraj_esprit} to estimate the time delays and amplitudes of the FRI signals.
In Fig.~\ref{Fig:FRI1}, Fig.~\ref{Fig:FRI2} and  Fig.~\ref{Fig:FRI3} we show sampling and reconstruction of FRI signals with $L=2,3,5$ respectively.
The FRI signals followed by a lowpass filter are presented in Fig.~\ref{fig:FRI1_1k}, Fig.~\ref{fig:FRI2_1k}, and  Fig.~\ref{fig:FRI3_1k}.
The reconstruction of the lowpass signals displayed in Fig.~\ref{fig:FRI_LPF1}, Fig.~\ref{fig:FRI_LPF2} and  Fig.~\ref{fig:FRI_LPF3}, where $y(t)$ described the LPF output, $y_\lambda(t)$ is the folded signal (output of the modulo hardware), and the unfolded signals are given by $\hat{y}(t)$. Fig.~\ref{fig:FRI1_REC}, Fig.~\ref{fig:FRI2_REC} and Fig.~\ref{fig:FRI3_REC} show location and amplitude of the true signal $f(t)$ and estimated FRI signal $\hat{f}(t)$.
The maximum error in the estimation of time delay is $-15$ dB which shows that the system can be used in applications like radar and ultrasound imaging.

\section{Conclusions}
 We presented a hardware prototype for the modulo folding system and showed that for different bandlimited and FRI signals, the hardware is able to fold the signal faithfully. In particular, we were able to sample signals with 8 times the dynamic range of the ADC roughly. We also  addressed the time delay issue of the modulo system and presented a hardware solution. The overall system operates five times below the Nyquist rate, which enables one to use low-rate, low-dynamic range, power-efficient ADCs.

\bibliographystyle{IEEEtaes}

\section{INTRODUCTION}
Sampling plays a key role in efficiently processing real-world analog signals on digital signal processors. Analog to digital converters (ADCs) are used to implement sampling in the hardware. A key parameter of an ADC is its sampling rate. ADCs with high sampling rates are power-consuming and expensive, making them unsuitable for portable devices such as hand-held ultrasound devices. Hence, it is desirable to reduce the sampling rate. Signals with finite rate of innovation (FRI) have few degrees of freedom which aids in sub-Nyquist sampling \cite{eldar_2015sampling}. That is, signal is sampled at a rate much lower than the Nyquist rate \cite{shannon, nyquist} and hence low power ADCs could be used. FRI model is ubiquitous in several time of flight applications \cite{bajwa_radar, bar_radar,filho201seismic,rip,carter_sonar,eldar_sos,eldar_beamforming, sunil} where the signal of interest is represented as a linear combination of delayed copies of a known pulse. Thus, the desired information lies in the amplitudes and time delays of the pulse, which amounts to a few degrees of freedom.

Most existing works in the context of FRI sampling focus on reducing the ADC's sampling rate by using the signal structure \cite{vetterli, eldar_sos, fri_strang, blu_moms, mulleti_kernal} and ignores other aspects of the ADC.
The dynamic range of an ADC plays a crucial role in sampling an analog signal. ADC's dynamic range should generally be larger than the signal's; otherwise, the signal gets clipped. A few approaches exist to recover the true samples from clipped ones for bandlimited signals \cite{marks_clipping2, marks_clipping1}. These approaches rely on the correlation among the samples when they are measured at a very high rate compared to the Nyquist rate. The requirement of a high sampling rate is a drawback of these approaches. In addition, theoretical guarantees are missing, and it is unclear how many clipped samples can be recovered.

There are several preprocessing approaches such as automatic gain control (AGC) \cite{perez2011automatic,mercy1981review}, companding \cite{landau_compander,landau_distorted_bl}, and modulo folding \cite{uls_tsp,uls_romonov,uls_sparse,bhandari2021unlimited,eyar_moduloicassp}, that can be used prior to sampling to avoid clipping. Among these, modulo folding is most recent approach that need not be differentiable like companding and does not suffer from stability issues of the feedback amplifiers used in AGC. In the modulo framework, the signal is folded to lie within ADC's dynamic range and then the folded signal is sampled by using a conventional ADC. Theoretical guarantees for recovering bandlimited signals from folded samples are presented in \cite{uls_tsp,uls_identifiability}. The results states that the bandlimited signals can be uniquely recovered from folded samples provided that they are sampled above the Nyquist rate.

Several algorithms for \emph{unfolding} or recovering the true samples of bandlimited signals from modulo or folded samples are presented in \cite{uls_tsp,uls_romonov, eyar_moduloicassp}. These unfolding algorithms can be compared in terms of sampling rate, amount of unfolding they can handle, and noise robustness. It is shown that the method proposed in \cite{eyar_moduloicassp} has lowest reconstruction error for a given sampling rate, noise level, and signal's amplitude level compared to the algorithms presented in \cite{uls_tsp,uls_romonov}. The algorithm proposed in \cite{uls_tsp} requires almost 17-times higher sampling rate than the Nyquist rate but it is independent of the dynamic range of the ADC. Whereas, the approaches in \cite{uls_romonov, eyar_moduloicassp} requires the knowledge of ADC's dynamic range. Modulo sampling is also extended to different problems and signal models such as periodic bandlimited signals \cite{bhandari2021unlimited}, wavelets \cite{uls_wavelet}, mixture of sinusoids \cite{uls_sinmix}, finite-rate-of-innovation signals \cite{uls_fri}, multi-dimensional signals \cite{uls_md}, sparse vector recovery \cite{uls_gamp, uls_sparsevec}, direction of arrival estimation problem \cite{uls_doa}, computed tomography \cite{uls_radon}, and graph signals \cite{uls_graph}.

While theoretical guarantees and algorithms of any new sampling approach are always well researched but the question of whether they work in practice is difficult to answer. For modulo sampling, there exists a few hardware prototypes. For example, high-dynamic-range ADCs, also known as \emph{self-reset} ADCs, are discussed in the context of imaging \cite{sradc_park, sradc_sasagwa, sradc_yuan, krishna2019unlimited}. These hardware architectures measure additional information such as the amount of folding for each sample, or, the sign of the folding together with the folded samples. The additional information might enable simpler recovery but at the expense of complex circuitry. Importantly, additional bits are required during the quantization process to store or transmit the side information.

Krishna et al. presented a hardware prototype which encode the side-information by using two bits \cite{krishna2019unlimited}. The architecture is designed to record sign of the slope of the signal at each sampling instant when the sample lies outside ADC's dynamic range. In a conventional ADC, a sample and hold (S/H) circuit is used to hold the sampled value for a prescribed period of time during which quantization is performed on the sample. To realize the modulo sampling, a folding circuit is used after S/H \cite{krishna2019unlimited}. Hence, the S/H circuit has to hold the sampled value for folding and quantization, which results in a larger folding time compared to a conventional ADC. A large holding time results in slower ADC and hence it may not be useful for wideband application.

The Modulo hardware prototypes where the modulo part is implemented prior to sampler are presented in \cite{bhandari2021unlimited,Bhandari:2022:J,mod_hyst}. Since the modulo circuit is not part of the hold time, the ADC could be faster than the hardware realization in \cite{krishna2019unlimited}.  In \cite{mod_hyst}, the authors discussed a few implementation issues of modulo hardware such as hysteresis and folding transients, and proposed algorithmic solutions to mitigate them. Both these issues can also be addressed by careful calibration and by using high precision components. In \cite{Bhandari:2022:J}, Bhandari showed reconstruction of FRI signals by using a modulo hardware. In \cite{bhandari2021unlimited,Bhandari:2022:J,mod_hyst}, rather than providing details of the hardware circuitry the authors are focused on different signal models, hardware-limitations, and algorithms. They showed that the modulo hardware is able to fold low frequency signals which are 10-12 times larger than the ADC's dynamic range.

In this paper, we present a modulo hardware prototype which can be used in low-power time-of-flight applications, and show that by using our algorithm \cite{eyar_moduloicassp} it is able to faithfully reconstruct FRI signals.
In the following, we present our contributions and the salient features of our hardware system.
\begin{itemize}
    \item As an initial step, we design our hardware components in such a way that they can fold the signals upto 5KHz.

    Note that none of the existing hardwares handles such frequency input signals.
    \item Our hardware prototype is designed to operate prior to the sampler unlike the hardware in  \cite{krishna2019unlimited} which operates in the hold part of the sampler. Hence, the proposed system can use faster ADCs with smaller hold time.
    \item Modulo folding is realized through a feedback mechanism. The time instants at which the input signal goes beyond the ADC's dynamic range, a trigger signal is generated by using a set of comparators. The trigger then activates a direct-current (DC) generator that adds to the input signal to bring it to stay within the dynamic range. This feedback mechanism introduces a finite time delay between the trigger and addition operation. The delay has an undesirable effect and it causes a part of the input signal to stay beyond the dynamic range.
    We address this key issue of the hardware which was not considered in the previous works.
    By using smoothness of the signal and time delay of the feedback loop, we show that by changing the thresholds of comparators the delay issue can be mitigated. Specifically, by using tunable threshold voltages at the comparators, time delay issues can be resolved for signals with different bandwidths.
    \item To show an application of the hardware, we consider sampling and reconstruction of FRI signals. We use a lowpass filter (LPF) prior to modulo system as a sampling kernel. The filter removes unwanted information in the signal and allows sub-Nyquist sampling. The filtered signal is folded by the designed hardware and then sampled. For estimating the FRI parameters, the samples are first unfolded by using our algorithm presented in \cite{eyar_moduloicassp} and then the parameters are estimated by using annihilating filter approach. By using the fact that our algorithm operates at lowest possible rate, we show that FRI parameters can be estimated sub-Nyquist samples. In particular, we show that the system operates at five times the rate of innovation which is much lower than the Nyquist rate of the signal.
\end{itemize}

The paper is organized as follows. In the next section, we discuss the FRI signal model and its sampling and reconstruction framework in the presence of modulo hardware. In Section III, we present the actual hardware system by explaining its working principle and discussing the components of the system. In Section IV, we show the signal folding and reconstruction abilities of the hardware, and then the conclusion is followed.

\section{Signal Model and System Description}
In this section, we first introduce the FRI signal model and then discuss its sampling and reconstruction framework with modulo ADC.
\subsection{FRI Signal Model}
Consider an FRI signal consisting of stream of $L$ pulses:
\begin{align}
	f(t) = \sum_{\ell=1}^L a_\ell h(t-t_\ell),
	\label{eq:fri1}
\end{align}
where the pulse $h(t)$ a real-valued known pulse. We assume that $\{a_\ell\}_{\ell = 1}^L$ are real-valued and $\{t\}_{\ell = 1}^L \subset (0, T_0] \subset \mathbb{R}$ for a known $T_0$.

The FRI signal model in \eqref{eq:fri1} is encountered in several scientific applications such as radar imaging \cite{bar_radar, bajwa_radar, sunil}, ultrasound imaging \cite{eldar_sos,eldar_beamforming,mulleti_icip}, light detection and ranging (LIDAR) \cite{castorena_lidar}, time-domain optical-coherence tomography (TDOCT) \cite{blu_oct}, and other time-of-flight imaging systems. In these applications,  $h(t)$ is the transmitted pulse and $\{a_\ell \,h(t-t_\ell)\}_{\ell=1}^{L}$ constitute the reflections from $L$ point targets. The amplitudes $\{a_\ell\}_{\ell = 1}^L$ depend on the sizes of the targets and the delays $\{t\}_{\ell = 1}^L$ are proportional to the distances of the targets from the transmitter. Here $T_0$ denotes maximum time delay of the targets. The signal $f(t)$ is specified by $\{a_\ell, t_\ell\}_{\ell=1}^L$ and can be reconstructed from its sub-Nyquist measurements acquired using an appropriate sampling kernel \cite{vetterli,eldar_sos,fri_strang, mulleti_kernal}. The reconstruction is generally carried out in frequency domain as discussed next.

\subsection{Fourier-Domain Reconstruction}
Consider uniform samples of continuous-time Fourier transform of $f(t)$ given as
\begin{align}
	F(k \omega_0) = \int f(t) e^{-\mathrm{j} k\omega_0 t} \mathrm{d}t = H(k \omega_0) \sum_{\ell = 1}^L a_\ell \, e^{-\mathrm{j} k\omega_0 t_\ell},
	\label{eq:F}
\end{align}
for $k \in \mathcal{K}$. Here $H(\omega)$ is the Fourier transform of $h(t)$ and $\mathcal{K}$ is an integer set. In \eqref{eq:F}, $\omega_0>0$ denotes sampling interval in the frequency domain. Next, consider the following samples
\begin{align}
	S(k\omega_0) = \frac{F(k\omega_0)}{H(k\omega_0)} =  \sum_{\ell = 1}^L a_\ell \, e^{-\mathrm{j}k\omega_0 t_\ell},
	\label{eq:Skomega}
\end{align}
where we assume that $H(k \omega_0) \neq 0$ for $k \in \mathcal{K}$. In practice, the pulse $h(t)$ has small time support and hence, large bandwidth. Hence, for a finite set $\mathcal{K}$ it is possible to choose a set of frequencies $\{k \omega_0\}_{ k \in \mathcal{K}}$ such that $H(k \omega_0) \neq 0$. It can be shown that $2L$ consecutive samples of $S(k\omega_0)$ are sufficient to uniquely identify $\{a_\ell, t_\ell\}_{\ell=1}^L$ if $\omega_0 = \frac{2\pi}{T_0}$ \cite{eldar_2015sampling}. {\color{blue}{}In practice, high-resolution spectral estimation methods, such as the annihilating filter (AF) or Prony's method and its variants \cite{prony, plonka}, multiple signal classification \cite{schmidt_music, barabell_rmusic, bdrao_rmusic}, matrix-pencil method \cite{sarkar_mp}, estimation of signal parameter via rotational invariance technique (ESPRIT) \cite{paulraj_esprit}, etc., have been deployed for FRI parameter estimation. }

Since $h(t)$ is known, $H(k\omega_0), k \in \mathcal{K}$ can be calculated in advance. Hence, to compute $S(k\omega_0), k \in \mathcal{K}$ and then to estimate the FRI parameters, $F(k\omega_0), k \in \mathcal{K}$ has to be determined. Next, we discuss a lowpass filter (LPF) based sampling framework to determine these Fourier samples.

\subsection{LPF-Based Sub-Nyquist Sampling}
\label{sec:lpf}
In this section, we discuss a LPF-based sampling mechanism for FRI signals. Let $g(t)$ denotes an ideal lowpass filter with cutoff frequency $\omega_c$ rad/sec. In the frequency-domain we have that $G(\omega) = 1$ for $\omega \in [-\omega_c, \omega_c]$ and zero for the rest of the frequencies. Let $y(t)$ denotes response of the LPF to the input $f(t)$, that is, $y(t) = (f*g)(t)$, where $*$ denotes linear convolution operation. Consider an ADC with dynamic range $[-\lambda, \lambda]$ and sampling rate $\omega_s = \frac{2\pi}{T_s}$ rad/sec. By assuming that  $\|y(t)\|_{\infty}\leq \lambda$, uniform samples at the output of ADC are given as $y(nT_s), n \in \mathbb{Z}$. Then uniform measurements of discrete-time Fourier transform (DTFT) of the samples are given as
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) = \sum_{n \in \mathbb{Z}}y(nT_s)\,e^{\mathrm{j} k\omega_0 n T_s}, \quad k \in \mathcal{K}.
	\label{eq:y_dtft}
\end{align}
By using relationship between DTFT of samples $y(nT_s)$ and CTFT of $y(t)$ we have
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) &= \frac{1}{T_s}\sum_{m \in \mathbb{Z}} Y(k\omega_0 + m \omega_s), \nonumber \\
	&= \frac{1}{T_s}\sum_{m \in \mathbb{Z}} F(k\omega_0 + m \omega_s) \,G(k\omega_0 + m \omega_s),
		\label{eq:y_dtft2}
\end{align}
where we used the fact that $Y(\omega) = F(\omega)\,G(\omega)$. Next, consider the following conditions on the sampling rate and cutoff frequency of the filter
\begin{align}
	\omega_s \geq 2\omega_c, \quad \text{and} \quad \omega_c \geq K \omega_0,
	\label{eq:sampling_rate}
\end{align}
where $K \geq L$. Then by choosing $\mathcal{K} = \{-K, \cdots, K\}$, \eqref{eq:y_dtft2} can be written as
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) = F(k\omega_0), \quad k \in \mathcal{K},
	\label{eq:y_dtft3}
\end{align}
where we used the fact that $G(k\omega_0) = 1$ in these settings. The relationship \eqref{eq:y_dtft3} shows that the desired Fourier samples of $f(t)$ are determined from the samples of LPF by assuming that the conditions in \eqref{eq:y_dtft2} are satisfied. Hence, FRI parameters can be determined from the samples of the lowpass filter. A LPF-based sampling for FRI signal was used in \cite{vetterli,uls_sparse} but with a periodic FRI signal model. With perodization, a finite number of time samples are sufficient to determine the desired Fourier measurements, whereas, countable infinite measurements are required in aperiodic settings consider here.

The bandwidth of the pulse $h(t)$ and hence that of the FRI signal $f(t)$ could be very large. But the sampling rate $\omega_s$ is independent of the pulse and could be much smaller than its bandwidth which shows the FRI signal could be reconstructed from sub-Nyquist samples.

The sub-Nyquist sampling framework discussed assumes that $\|y(t)\|_{\infty}\leq \lambda$, in other words, the framework assumes that the dynamic range of the ADC is greater than that of the signal to be sampled. However, this condition may not be always true. Specifically, the amplitude range of the filtered signal $y(t)$ could be larger than ADC's dynamic range. In such a scenario, a direct sampling would lead to clipping of samples which is undesirable. To avoid clipping, a modulo operator is employed prior to sampling as discussed next.

\begin{figure*}
	\centering
	\includegraphics[width=6.5 in]{Figs/FRI_US}
	\caption{A schematic of modulo-sampling and reconstruction of FRI signals.}
	\label{fig:fri_framework}
\end{figure*}

\subsection{Modulo-Folding}
To avoid clipping, a modulo folding operator $\mathcal{M}_\lambda(\cdot)$ is used after LPF and before the ADC. The operator folds $y(t)$ to stay within ADC's dynamic range $[-\lambda, \lambda]$. The output of the modulo operator in response to input $y(t)$ is given as
\begin{equation}
 y_\lambda(t) =	\mathcal{M}_{\lambda}(y(t)) = (y(t)+\lambda)\,\, \text{mod}\,\, 2\lambda -\lambda.
	\label{eq:mod_opp}
\end{equation}
The folded signal is then sampled by the ADC to have measurements $y_\lambda(nT_s)$. Since modulo folding is a nonlinear operation, one can not directly apply DTFT on the samples to compute Fourier measurements of the FRI signal for its reconstruction. Hence, the true or unfolded samples $y(nT_s)$ are estimated from the folded ones $y_\lambda(nT_s)$ by applying an unfolding algorithm. There exist several unfolding methods for bandlimited signals \cite{uls_tsp, uls_romonov,eyar_moduloicassp}.
The sampling rate for unfolding varies for different algorithms and generally, is larger than the minimum sampling rate required for FRI signal recovery (cf. \eqref{eq:sampling_rate}).
Hence, the overall system operates on a higher sampling rate than that without a modulo case. However, if the overall sampling rate is much lower than the bandwidth of the FRI signal then the system operates at a sub-Nyquist rate. We show that this is indeed true when we apply our unfolding algorithm proposed in \cite{eyar_moduloicassp}.

An end-to-end modulo sampling framework for FRI signal sampling and reconstruction is shown in Fig.~\ref{fig:fri_framework}. The sampler or ADC together with the modulo block is termed as modulo-ADC.
Modulo-ADCs are able to sample signals beyond their dynamic range without clipping and hence they are termed as high-dynamic range ADCs. Alternatively, an ADC with a  much lower dynamic range can be used to sample signals with larger amplitudes. Sub-Nyquist sampling and low-dynamic range requirements significantly reduce the power consumption and cost of the ADC.

The modulo folding block is key component of the high-dynamic range ADC and we discuss its hardware implementation in the next section.

\begin{figure}
	\centering
	\includegraphics[width= 3 in]{Figs/folding}
	\caption{Folding principle}
	\label{Fig:folding}
\end{figure}
\section{Modulo Hardware Prototype}
In this section, we discuss our modulo hardware prototype. First, we explain the working principle of the modulo block and explain how its design and then discuss the hardware realization.
\subsection{Working Principle of Modulo Block}
Principle of computing $y_\lambda(t)$ from $y(t)$ is shown by block-diagram in Fig.~\ref{Fig:folding}. The system comprises of an adder $S$, a direct-current voltage generator (DC-VG), and two comparators $C_1$ and $C_2$. To understand the working let us first assume that for some time instant $t_1$, we have that $|y(t)|<\lambda$ for $t<t_1$. Hence $y_\lambda(t) = y(t)$ and $z(t) = 0$ for $t<t_1$. At $t=t_1$, let $|y(t)|$ crosses $\lambda$. If $y(t_1)>\lambda$, then the comparator $C_1$ triggers a positive value or else, $C_2$ triggers a negative value. The DC-VG is designed such that for every positive value input it reduces its output signal level by $-2\lambda$, whereas, for negative value it increases its output voltage by $2\lambda$. Hence, in the current example, DC-VG generates signal $z(t) = \text{sgn}(y_\lambda(t_1)) 2\lambda u(t-t_1)$ where $u(t)$ is unit-step function.
In this way by adding or subtracting (by using $S$) constant DC signals from $y(t)$ whenever it crosses dynamic range $[-\lambda, \lambda]$, the amplitude levels of $y_\lambda(t)$ are kept within ADC's dynamic range.

\begin{figure}[!h]
	\centering
	\begin{tabular}{c}
		\subfigure[]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Fig3_2Folding_6Vpp_3Vbias_1KHz_Up.png}\label{fig:Up_Folding}} \\
		\subfigure[]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Fig3_2Folding_6Vpp_3Vbias_1KHz_Down.png}\label{fig:Down_Folding}} \\
	\end{tabular}
	\caption{DC-VG folding mechanism.}
	\label{Fig:DC-VG_folding_mechanism}
\end{figure}

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3 in]{Figs/dc_vg}
	\caption{DC-VG}
	\label{Fig:dcvg}
\end{figure}

\begin{figure*}[!t]
	\centering
	\includegraphics[width=0.96\textwidth ]{IEEE_TAES_v1/Figs/UDR_Board_Labeled3.PNG}
	\caption{Modulo hardware board.}
	\label{Fig:hw_board}
\end{figure*}

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3.2 in]{IEEE_TAES_v1/Figs/Fig6_1KHz_10Vpp_4Folding_New.png}
	\caption{Analysis of folding ability of the modulo hardware.}
	\label{Fig:Analysis_of_folding_ability}
\end{figure}

\begin{figure}[!h]
	\centering
	\begin{tabular}{c}
		\subfigure[]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Fig7_1Folding_6Vpp_1KHz_New.png}\label{fig:1k_1}} \\
		\subfigure[]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Fig7_1Folding_6Vpp_10KHz_New.png}\label{fig:10k_1}} \\
		\subfigure[]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Fig7_1Folding_6Vpp_20KHz_New.png}\label{fig:20k_1}}
	\end{tabular}
	\caption{Analysis of frequency response of the modulo hardware.}
	\label{Fig:frequency_response}
\end{figure}

\begin{table}[h!]
		\caption{Folding Operation.}
	\centering
	\begin{tabular}{||c c c c c ||}
		\hline
		c & b & a & sgn & Counter values \\ [0.5ex]
		\hline\hline
		0 & 0 & 0 & 0~(1) & 0~(0) \\
		0 & 0 & 1 & 0~(1) & 1~(-1) \\
		0 & 1 & 0 & 0~(1) & 2~(-2) \\
		0 & 1 & 1 & 0~(1) & 3~(-3) \\
		1 & 0 & 0 & 0~(1) & 4~(-4) \\
		1 & 0 & 1 & 0~(1) & 5~(-5)\\
		1 & 1 & 0 & 0~(1) & 6~(-6)\\
		1 & 1 & 1 & 0~(1) & 7~(-7)\\
		\hline
	\end{tabular}
	\label{table:counter}
\end{table}

While the parts such as comparators $C_1$, $C_2$, and adder $S$ can be realized by using off-the-shelf components, DC-VG is a more involved system and required careful design. A detailed architecture of DC-VG is shown in Fig.~\ref{Fig:dcvg}. It consists of an up/down counter, a digital-to-analog converter (DAC), a multiplexer (MUX), and a multiplier $M$.  The role of the counter (together with DAC) is to generate a variable, but controlled DC voltage whenever there is a trigger at its input. The voltage values are set to be multiple of $2\lambda$ by using the MUX and multiplier $M$.
To elaborate the working principle, we first discuss the role of the counter and then the rest of the components.

In this particular system, we use a three-bit synchronous up/down counter. The bits from lower significant bit to higher significant bit are denoted as a, b, and c. The counter has an additional sign bit shown as sgn. With these bits, the counter can count from -7 to 7. For every positive trigger at the input the output counts up and with a negative trigger it counts down. In Table~\ref{table:counter}, we display the values of bits and the counter (denoted as counter values). The three bits (a,b, and c) of the counter are used as input to the DAC which converts the bits to analog DC voltages. Let the resolution or step size of the DAC is $\alpha$ then the output of DAC is $\alpha$ times the counter-value. To be more specific, consider the scenario where the output of counter and DAC are zero. Then for a positive (negative) trigger, the output of DAC increases (decreases) by $\alpha$. Specifically, the output of DAC, $s(t)$, is a piecewise constant signal with values that are multiples of $\alpha$. However, for folding to work, the change in the voltage should be in multiples of $2\lambda$. To ascertain that we use a MUX which outputs either $2\lambda$ or $-2\lambda$ depending on whether its input is 1 or 0. Then by multiplying the output of DAC with the output of MUX we generate $z(t)$.

{\color{blue}{The DC-VG operation can be seen in Fig  \ref{Fig:DC-VG_folding_mechanism} at the screenshots of an oscilloscope capturing input $y(t)$ (in yellow), its folded output $y_\lambda(t)$ (in green), $z(t)$ (in blue) and C1/C2 comparators respectively which triggers the +2$\lambda$ operation (in red).
In order to better illustrate the DC-VG counter up and down operation we capture Fig \ref{fig:Up_Folding} and Fig \ref{fig:Down_Folding} respectively.
Fig \ref{fig:Up_Folding} demonstrates the folding operation time sequence from the C1 comparator trigger operation (in red), following with a ramp of 2$\lambda$ of $z(t)$ (in blue) which result in increase of $y_\lambda(t)$ (in green) by 2$\lambda$ and keeping it at the +-2$\lambda$ ADC range.

Fig \ref{fig:Down_Folding} demonstrates the folding operation time sequence from the C2 comparator trigger operation (in red), following with a ramp of -2$\lambda$ of $z(t)$ (in blue) which result in increase of $y_\lambda(t)$ (in green) by -2$\lambda$ and keeping it at the +-2$\lambda$ ADC range.

}}

Next, we discuss the hardware board that realizes the folding operation discussed in this section.

\begin{table}[h!]
\centering
\caption{List of Hardware Components}
\label{table:hardware_components}
\begin{tabular}{||c c c||}
 \hline
 Component & Model Number & Make \\
 && \\ \hline
 Comparator & LM339 & Texas Instruments \\
 && \\
 UP/DOWN Counter & TEENSY4.1 & PJRC \\
 && \\
 DAC 3bits & LT1364 & Analog Devices \\
 && \\
 Analog MUX & ADG1608 & Analog Devices \\
 && \\
 Analog Multiplier & AD835 & Analog Devices \\
 && \\
 Adder & LT1364 & Analog Devices \\
  && \\ [1ex]
\hline
\end{tabular}
\end{table}
\subsection{Modulo Hardware Board}
Our modulo hardware board is shown in Fig.~\ref{Fig:hw_board} with main role of the various building components are marked. The details of the components of the hardware are listed in Table~\ref{table:hardware_components}. The board is designed for $\lambda \leq 1.25$ volts. The board can accommodate an input signal with a dynamic range between $[-4\lambda, 4\lambda]$ which implies that an ADC with our modulo hardware can sample four-times larger signals compared to its dynamic range without saturation and clipping.

We demonstrate the working of the modulo hardware by considering a sinusoidal signal $y(t) = A\, \sin(2\pi f_0 t)$ where $A$ is amplitude and $f_0$ is frequency (in Hz). In this experiment, we set $\lambda = 1.25$ and $-4\lambda <A <+4\lambda$. With these settings, we expect the signal to fold 4 tims in a quarter cycle of a sinusoid. Figs.~\ref{Fig:Analysis_of_folding_ability} screenshot of an oscilloscope capturing input $y(t)$ (in yellow) and its folded output $y_\lambda(t)$ (in green) in addition the DC-VG output signal $z(t)$ (in blue), for $f_0 = 1$ KHz. We observed that the signals are folded back to lie within the dynamic range of the ADC as expected without clipping. Next we will discuss the different frequencies in order to study the frequency response of the modulo folder. As in any analog system, the response of the modulo folder too depends on the frequency or bandwidth of the input signal. Beyond a particular frequency, the foldings may not be accurate as observed in Fig.~\ref{Fig:frequency_response}. We observed that for signals of 1 kHz and 10kHz the hardware is able to fold the signal accurately. However, for $f_0 = 20$ kHz, folding instants are not symmetric for positive and negative folds. In one of our future works, we are planning to design a hardware that overcome this limitation by using faster hardware logical components to implement the folding counter instead of using the current up/down counter. The current implementation demonstrates a prof of concept of implementing the modulo concept in the analog domain at near real life environment and pave the way for a high frequency applications which supports high dynamic range operation.

In the next section, we discuss a couple of inaccuracies of the modulo hardware and our proposed solution to overcome those.

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3.2 in]{Figs/mod_td}
	\caption{Effect of time delay of the feedback loop on the modulo operation.}
	\label{Fig:mod_td}
\end{figure}

\subsection{Artifacts During Folding}
Errors or other artifacts that arise during folding operation in hardware could be due to various reasons. For example, in Figs.~\ref{Fig:Analysis_of_folding_ability} and \ref{Fig:frequency_response}, we observe that the amplitude of the folded signals could go beyond the dynamic range momentarily around the folding instants. This is due to the settling time of the DC-VG when voltage values change. Specifically, after switching, the voltage at the output of DC-VG overshoots and undershoots before the oscillations settle down to the expected value. This can be overcome by using a faster adder whose response time should be at least a magnitude higher than the sample rate.

Another major issue that arises in a folding ADC is a time delay in the feedback loop (See Fig.~\ref{Fig:folding}). To elaborate, consider a scenario where $y(t)<\lambda$ for $t<t_1$ and it crosses $\lambda$ at time $t_1$ as discussed earlier. To fold the output voltage to the dynamic range of the ADC, $z(t) = -2\lambda u(t-t_1)$ needs to be added to $y(t)$. However, there is a finite delay between the trigger time $t_1$ to generating $z(t)$. If the time delay is $T_d$, then $z(t) = -2\lambda u(t-t_1-T_d)$ is added which causes distortion. To illustrate this effect in Fig.~\ref{Fig:mod_td} by considering a sinusoidal signal (in blue) and its folded versions with and without delay. We observe that in the absence of any time delay ($T_d=0$) the signal folds perfectly (shown in red) to stay within the dynamic range. However, for a non-zero value of $T_d$, foldings do not take place at the folding instants and the output of the modulo operator (shown in black) still remains outside the dynamic range $[-\lambda, \lambda]$. We propose a hardware solution to address this issue.

Our solution uses the fact that with a finite time delay, the amount of overshoot of a smooth signal can be bounded. To elaborate, let us assume that the signal that undergoes modulo operation is Lipschitz continuous. Specifically, a signal $y(t)$ is Lipschitz continuous if there exists a positive real number $\mathrm{L}_y$ such that for any $T>0$ we have
\begin{align}
    |y(t) -y(t+T)|\leq \mathrm{L}_y\, T.
    \label{eq:lipschitz}
\end{align}
With the Lipschitz smoothness condition, we note that the amplitude of $y(t)$ can not change more than $\mathrm{L}_y\, T_d$ between any folding instant and time of its effect to take place. Hence, if we choose dynamic range of the ADC to be $[-(\lambda+\Delta \lambda), (\lambda+\Delta \lambda)]$ where $\Delta \lambda = \mathrm{L}_y\, T_d$ then the signal will not clip. We show this extended dynamic region in the illustrative example in Fig.~\ref{Fig:mod_td}. Alternatively, instead of increasing ADC's dynamic range, one can keep it to be $[-\lambda, \lambda]$ and reduce the threshold values for comparators. In this case, $C_1$ will trigger when the input crosses $\lambda-\Delta \lambda$ and $C_2$ will trigger when input goes beyond $-\lambda+\Delta \lambda$. In this way, the time delay issue is addressed by the modulo circuit without altering ADC's dynamic range.

To implement the mentioned solution, the signal should be Lipschitz continuous. In our setup, the input to modulo operation is a lowpass or bandlimited signal which always satisfies the Lipschitz smoothness condition \cite{bl_bound}. For a bandlimited signal $y(t)$ its Lipschitz constant $\mathrm{L}_y$ is directly proportional to its bandwidth $\omega_c$ which is the same as the cutoff frequency of the LPF.
Hence, for a given value $\Delta \lambda$ and $T_d$ (both depend on the modulo circuit), $\mathrm{L}_y = \Delta \lambda/T_d$ is fixed and this restricts the maximum frequency of the input signal that can be faithfully folded. In the current design, we chose to implement the counter management by a TEENSY micro-controller which results in a time delay of $1 \mu$s which enable the hardware to support a wide range of frequencies with no need to modify the hardware components. In order to support higher frequencies, alternative design strategies with a faster response time and lower delay should be used.

\section{Results}
In this section, we show the signal reconstruction ability of the modulo hardware described in the previous section. From Fig.~\ref{fig:fri_framework}, we understood that the signal reconstruction ability is a function of LPF $g(t)$, modulo circuit $\mathcal{M}_\lambda(\cdot)$, ADC or sampler, unfolding algorithm, and parameter estimation method. Any error in the estimation of FRI parameters is a result of flaws and limitations of the hardware realizations and limitations of the algorithms in the presence of measurement noise. For example, ideally $g(t)$ should have infinite impulse response, however, only a truncated version could be realizable in hardware. The truncation will result in errors while determining the Fourier samples of the FRI signal (See Section~III.\ref{sec:lpf}). Similarly, quantization plays a role when a finite resolution quantizer is used after the sampler. In addition, all the hardware components contribute to different types of noise. We model all these noises and inaccuracies as additive noise at the output of the sampler. Specifically, the noisy measurements are given as
 \begin{align}
            \tilde{y}_{\lambda}(n T_s) = {y}_{\lambda}(n T_s) + v(n T_s),
        \label{eq: noisy_samples}
        \end{align}
where $v(n T_s)$ is the noise term. Both unfolding and parameter estimation algorithms should be robust to different noise models. The robustness of parameter estimation methods in the presence of noise is well studied (See \cite{mulleti_kernal, stoica, eldar_sos}). In \cite{eyar_moduloicassp}, we presented comparisons of unfolding algorithms for bandlimited signals. We showed that our beyond-bandwidth residual recovery ($B^2R^2$) approach results in lower error during unfolding compared to the \emph{higher-order differences} (HOD) approach \cite{unlimited_sampling17, uls_tsp} and \emph{Chebyshev polynomial filter}-based (CPF) method \cite{uls_romonov}. Importantly, for a given sampling rate, $\lambda$, and signal to noise ratio (SNR), $B^2R^2$ method results in the lowest error for both bounded and unbounded noise models.

Before presenting hardware results, we compare the performances of the $B^2R^2$ method with HOD and CPF approaches for quantization noise and unbounded noise. We would like to point out that quantization noise was not considered in \cite{eyar_moduloicassp}. Although, the algorithms were compared for unbounded noise but the simulation settings were different than those in our hardware. Hence, for a better understanding, we compared our algorithm for unbounded noise and quantizaition  noise with the current hardware settings. In the next section, we present these simulation results and then present hardware results.

\begin{figure}[!t]
	\centering
	\includegraphics[width= 2.5 in]{IEEE_TAES_v1/Figs/quantization.png}
	\caption{Comparison of HOD, CPF and $B^2R^2$ algorithms after the quantization process in terms of MSE when recovering a bandlimited signal from modulo samples with $\lambda = 1.25$ and OF = 3,6. For a given number of bits, $B^2R^2$ has the lowest MSE.}
	\label{Fig:quantization}
\end{figure}

\begin{figure}[!t]
	\centering
	\includegraphics[width= 2.5 in]{IEEE_TAES_v1/Figs/Gaussian.png}
	\caption{Comparison of HOD, CPF and $B^2R^2$ algorithms (with unbounded noise) in terms of MSE when recovering a bandlimited signal from modulo samples with  $\lambda$ = 1.25 and OF = 3,6. For a given SNR and OF, $B^2R^2$ has lowest MSE.}
	\label{Fig:unbounded}
\end{figure}
\subsection{Simulated Results}
In this section, we compare our $B^2R^2$ algorithm with the \emph{higher-order differences} (HOD) approach \cite{unlimited_sampling17, uls_tsp} and \emph{Chebyshev polynomial filter}-based (CPF) method \cite{uls_romonov}. We consider the noise measurements as in \eqref{eq: noisy_samples} for a simulation data. In the simulations, $\lambda$ is set to be $1.25$ as in the hardware. We normalize the bandlimited signals to have maximum amplitude of $10$. The SNR is calculated as $\text{SNR} = 20 \log\left(\frac{||y_{\lambda}(n T_s)||}{||v(n T_s)||}\right)$. The reconstruction accuracy of different methods is compared in terms of normalized mean-squared error (MSE) as $ \frac{\sum |y(nT_s) - \hat{y}(n Ts)|^2}{\sum |y(nT_s)|^2}$, where $\hat{y}(n T_s)$ estimate of $y(n T_s)$. For different noise settings and over-sampling factors (OFs), we considered 100 independent noise realizations and calculated the average MSE for them. We first consider quantization noise and then present results for unbounded noise.

\begin{figure}[!t]
    \centering
    \includegraphics[width=0.3\textwidth]{IEEE_TAES_v1/Figs/Signal Generator.png}
    \caption{Bandlimited signal generator.}
    \label{fig:UDRSignalGen}
\end{figure}

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3 in]{IEEE_TAES_v1/Figs/Up_2mS.png}
	\caption{Bandlimited folded signal.}
	\label{Fig:Bandlimited_folded_signal}
\end{figure}

 First, we consider an uniform quantizer after the sampling. The unfolding algorithms are applied on the quantized samples. The MSE in the estimation of bandlimited signals for a different number of bits and OFs is shown in Fig. ~\ref{Fig:quantization}. We observe that for a given $\text{OF}$, $B^2R^2$ algorithm results in the lowest MSE for less than 5 bits. For more than 5 bits all the algorithms, except HOD with OF = 3, perform equally well. The results show that low-resolution quantizers can be used with $B^2R^2$ algorithm for unrolling which saves both power and memory requirements.

Next, for unbounded noise, we assume that the noise measurements $v(nT_s)$ are independent and identically distributed Gaussian random variables with zero mean. The variance is set to achieve a desired SNR. We compare the methods for different values of SNR and OFs with $\lambda = 1.25$. Fig.~\ref{Fig:unbounded} shows MSE of the different algorithms for OF $= 3$ and $6$. We note that our algorithm results in lowest error for a given OF and SNR.

Given the advantages of $B^2R^2$ algorithm over the other approaches, we present the hardware results in the next section by using this method.

\begin{figure*}[!t]
	\centering
	\begin{tabular}{cc}
		\subfigure[]{\includegraphics[width=2.5in]{IEEE_TAES_v1/Figs/BL1_rec.png}\label{fig:BL1}} &
		\subfigure[]{\includegraphics[width=2.5in]{IEEE_TAES_v1/Figs/BL2_rec.png}\label{fig:BL2}}
	\end{tabular}
	\caption{Hardware results for bandlimited signals. The $B^2R^2$ algorithm is used to unfold $y_\lambda(t)$ (measured at the output of hardware) and the unfolded signal $\hat{y}(t)$ is plotted with bandlimited signal $y(t)$.}
	\label{fig:BL_ex1}
\end{figure*}

\begin{figure*}[!t]
	\centering
	\begin{tabular}{ccc}
		\subfigure[]{\includegraphics[width=2.2in]{IEEE_TAES_v1/Figs/Ex1_lpf.pdf}\label{fig:FRI11}} &
		\subfigure[]{\includegraphics[width=2.1in]{IEEE_TAES_v1/Figs/Ex2_lpf.pdf}\label{fig:FRI12}}&
		\subfigure[]{\includegraphics[width=2.1in]{IEEE_TAES_v1/Figs/Ex3_lpf.pdf}\label{fig:FRI13}}\\
		\subfigure[]{\includegraphics[width=2.1in]{IEEE_TAES_v1/Figs/Ex1_fri.pdf}\label{fig:FRI21}} &
		\subfigure[]{\includegraphics[width=2.1in]{IEEE_TAES_v1/Figs/Ex2_fri.pdf}\label{fig:FRI22}}&
		\subfigure[]{\includegraphics[width=2.1in]{IEEE_TAES_v1/Figs/Ex3_fri.pdf}\label{fig:FRI23}}
	\end{tabular}
	\caption{Hardware results for FRI signals: Top row shows three examples of lowpass filtered FRI signals $y(t)$, modulo outputs $y_\lambda(t)$, and unfolded signals $\hat{y}(t)$; bottom row shows true FRI signal $f(t)$ and its estimate $\hat{f}(t)$.}
	\label{fig:FRI_ex}
\end{figure*}

\subsection{Hardware Results}
In this section, we present results from the hardware.
Since bandlimited signals are input to the hardware , we first present results for them and then show results for FRI signals. If the hardware and unfolding algorithm is able to recover the bandlimited signals with high accuracy than it will leads to better reconstruction of the FRI signals. In all these experiments we set $\lambda = 1.25$ V and the cutoff frequency of the lowpass filter is 1 kHz. We observe that for frequencies less than or equal to 10 kHz, our hardware is able to reliably fold the signal. The Nyquist rate of the signal is 2 kHz. But for unfolding we need to oversample the signal. In all these experiments, we used $B^2R^2$ algorithm with OF = 5 which results in sampling rate of 10 kHz. Further, $y(t)$ and $y_\lambda(t)$ are measured from the hardware through an oscilloscope for processing by the algorithms as described in Fig. \ref{Fig:Bandlimited_folded_signal}.

We first consider the bandlimited signals. For generating bandlimited or lowpass signals we used a Arduino micro-controller (See Fig.~\ref{fig:UDRSignalGen}) which convert the digital signal to an analog signal via a DAC. The digital signals were generated using MATLAB software. In Fig.~\ref{fig:BL_ex1}, we show folding and reconstruction of two bandlimited signals. These signals have maximum amplitude of 5 V. We observe the signals are restricted to $[-\lambda, \lambda]$ by the modulo hardware and the algorithm was able to recover the true signal from the folded samples. The reconstructed signal has slightly larger amplitude compared to the true signal which is result of scaling within the hardware.

Next, we consider reconstruction of FRI signals from modulo samples. To generate the FRI signals, we consider $h(t)$ to be a sort pulse of bandwidth 30 kHz (Nyquist rate = 60 kHz). We consider three examples with $L=2, 3,$ and 5. The amplitudes and time delays are generated randomly. The maximum time delay is $T_0 = 0.1$ sec. Once generated, the FRI signal is lowpass filtered with a cutoff frequency of 1 kHz. Up to filtering operation, MATLAB is used and then Arduino micro-controller is used to generate the analog version of the filtered FRI signals. The signal is then folded using the hardware and folded signals are sampled. The sampling rate is 10 kHz which is five times higher than the sampling rate of the lowpass signal. Still the rate is six times lower than the Nyquist rate and hence the system operates at sub-Nyquist rate. The setup satisfies the conditions in \eqref{eq:sampling_rate} for $L=2, 3,$ and 5.

We first apply $B^2R^2$ algorithm to unfold the signal and then used ESPRIT \cite{paulraj_esprit} to estimate the time delays and amplitudes of the FRI signals. We show FRI signal sampling and reconstruction in Fig.~\ref{fig:FRI_ex} where the top row shows LPF output $y(t)$, folded signal (output of the modulo hardware) $y_\lambda(t)$, and unfolded signals $\hat{y}(t)$. The bottom row shows location and amplitude of the true signal $f(t)$ and estimated FRI signal $\hat{f}(t)$. The maximum error in the estimation of time delay $-15$ dB which shows that the system can be used in applications like radar and ultrasound imaging.

\section{Conclusions}
We considered the problem of recovering FRI signals from low-pass filtered, modulo samples. We presented a hardware prototype for the modulo folding system and show that for different bandlimited and FRI signals, the hardware is able to faithfully fold the signal. We also  address the time delay issue of the modulo system and presented a hardware solution for the same. The overall system operates at six times below the Nyquist rate which enables one to use low rate, low-dynamic range, power efficient ADCs.

\bibliographystyle{IEEEtaes}

\section{INTRODUCTION}
Sampling plays a key role in efficiently processing real-world analog signals on digital signal processors. Analog to digital converters (ADCs) are used to implement sampling in the hardware. A key parameter of an ADC is its sampling rate. ADCs with high sampling rates are power-consuming and expensive, making them unsuitable for portable devices such as hand-held ultrasound devices. Hence, it is desirable to reduce the sampling rate. Signals with finite rate of innovation (FRI) have few degrees of freedom which aids in sub-Nyquist sampling \cite{eldar_2015sampling}. That is, signal is sampled at a rate much lower than the Nyquist rate \cite{shannon, nyquist} and hence low power ADCs could be used. FRI model is ubiquitous in several time of flight applications \cite{bajwa_radar, bar_radar,filho201seismic,rip,carter_sonar,eldar_sos,eldar_beamforming, sunil} where the signal of interest is represented as a linear combination of delayed copies of a known pulse. Thus, the desired information lies in the amplitudes and time delays of the pulse, which amounts to a few degrees of freedom.

Most existing works in the context of FRI sampling focus on reducing the ADC's sampling rate by using the signal structure \cite{vetterli, eldar_sos, fri_strang, blu_moms, mulleti_kernal} and ignores other aspects of the ADC.
The dynamic range of an ADC plays a crucial role in sampling an analog signal. ADC's dynamic range should generally be larger than the signal's; otherwise, the signal gets clipped. A few approaches exist to recover the true samples from clipped ones for bandlimited signals \cite{marks_clipping2, marks_clipping1}. These approaches rely on the correlation among the samples when they are measured at a very high rate compared to the Nyquist rate. The requirement of a high sampling rate is a drawback of these approaches. In addition, theoretical guarantees are missing, and it is unclear how many clipped samples can be recovered.

There are several preprocessing approaches such as automatic gain control (AGC) \cite{perez2011automatic,mercy1981review}, companding \cite{landau_compander,landau_distorted_bl}, and modulo folding \cite{uls_tsp,uls_romonov,uls_sparse,bhandari2021unlimited,eyar_moduloicassp}, that can be used prior to sampling to avoid clipping. Among these, modulo folding is most recent approach that need not be differentiable like companding and does not suffer from stability issues of the feedback amplifiers used in AGC. In the modulo framework, the signal is folded to lie within ADC's dynamic range and then the folded signal is sampled by using a conventional ADC. Theoretical guarantees for recovering bandlimited signals from folded samples are presented in \cite{uls_tsp,uls_identifiability}. The results states that the bandlimited signals can be uniquely recovered from folded samples provided that they are sampled above the Nyquist rate.

Several algorithms for \emph{unfolding} or recovering the true samples of bandlimited signals from modulo or folded samples are presented in \cite{uls_tsp,uls_romonov, eyar_moduloicassp}. These unfolding algorithms can be compared in terms of sampling rate, amount of unfolding they can handle, and noise robustness. It is shown that the method proposed in \cite{eyar_moduloicassp} has lowest reconstruction error for a given sampling rate, noise level, and signal's amplitude level compared to the algorithms presented in \cite{uls_tsp,uls_romonov}. The algorithm proposed in \cite{uls_tsp} requires almost 17-times higher sampling rate than the Nyquist rate but it is independent of the dynamic range of the ADC. Whereas, the approaches in \cite{uls_romonov, eyar_moduloicassp} requires the knowledge of ADC's dynamic range. Modulo sampling is also extended to different problems and signal models such as periodic bandlimited signals \cite{bhandari2021unlimited}, wavelets \cite{uls_wavelet}, mixture of sinusoids \cite{uls_sinmix}, finite-rate-of-innovation signals \cite{uls_fri}, multi-dimensional signals \cite{uls_md}, sparse vector recovery \cite{uls_gamp, uls_sparsevec}, direction of arrival estimation problem \cite{uls_doa}, computed tomography \cite{uls_radon}, and graph signals \cite{uls_graph}.

While theoretical guarantees and algorithms of any new sampling approach are always well researched but the question of whether they work in practice is difficult to answer. For modulo sampling, there exists a few hardware prototypes. For example, high-dynamic-range ADCs, also known as \emph{self-reset} ADCs, are discussed in the context of imaging \cite{sradc_park, sradc_sasagwa, sradc_yuan, krishna2019unlimited}. These hardware architectures measure additional information such as the amount of folding for each sample, or, the sign of the folding together with the folded samples. The additional information might enable simpler recovery but at the expense of complex circuitry. Importantly, additional bits are required during the quantization process to store or transmit the side information.

Krishna et al. presented a hardware prototype which encode the side-information by using two bits \cite{krishna2019unlimited}. The architecture is designed to record sign of the slope of the signal at each sampling instant when the sample lies outside ADC's dynamic range. In a conventional ADC, a sample and hold (S/H) circuit is used to hold the sampled value for a prescribed period of time during which quantization is performed on the sample. To realize the modulo sampling, a folding circuit is used after S/H \cite{krishna2019unlimited}. Hence, the S/H circuit has to hold the sampled value for folding and quantization, which results in a larger folding time compared to a conventional ADC. A large holding time results in slower ADC and hence it may not be useful for wideband application.

The Modulo hardware prototypes where the modulo part is implemented prior to sampler are presented in \cite{bhandari2021unlimited,Bhandari:2022:J,mod_hyst}. Since the modulo circuit is not part of the hold time, the ADC could be faster than the hardware realization in \cite{krishna2019unlimited}.  In \cite{mod_hyst}, the authors discussed a few implementation issues of modulo hardware such as hysteresis and folding transients, and proposed algorithmic solutions to mitigate them. Both these issues can also be addressed by careful calibration and by using high precision components. In \cite{Bhandari:2022:J}, Bhandari showed reconstruction of FRI signals by using a modulo hardware. In \cite{bhandari2021unlimited,Bhandari:2022:J,mod_hyst}, rather than providing details of the hardware circuitry the authors are focused on different signal models, hardware-limitations, and algorithms. They showed that the modulo hardware is able to fold low frequency signals which are 10-12 times larger than the ADC's dynamic range.

In this paper, we present a modulo hardware prototype which can be used in low-power time-of-flight applications, and show that by using our algorithm \cite{eyar_moduloicassp} it is able to faithfully reconstruct FRI signals.
In the following, we present our contributions and the salient features of our hardware system.
\begin{itemize}
    \item As an initial step, we design our hardware components in such a way that they can fold the signals upto 10KHz.

    Note that none of the existing hardwares handles such frequency input signals.
    \item Our hardware prototype is designed to operate prior to the sampler unlike the hardware in  \cite{krishna2019unlimited} which operates in the hold part of the sampler. Hence, the proposed system can use faster ADCs with smaller hold time.
    \item Modulo folding is realized through a feedback mechanism. The time instants at which the input signal goes beyond the ADC's dynamic range, a trigger signal is generated by using a set of comparators. The trigger then activates a direct-current (DC) generator that adds to the input signal to bring it to stay within the dynamic range. This feedback mechanism introduces a finite time delay between the trigger and addition operation. The delay has an undesirable effect and it causes a part of the input signal to stay beyond the dynamic range.
    We address this key issue of the hardware which was not considered in the previous works.
    By using smoothness of the signal and time delay of the feedback loop, we show that by changing the thresholds of comparators the delay issue can be mitigated. Specifically, by using tunable threshold voltages at the comparators, time delay issues can be resolved for signals with different bandwidths.
    \item To show an application of the hardware, we consider sampling and reconstruction of FRI signals. We use a lowpass filter (LPF) prior to modulo system as a sampling kernel. The filter removes unwanted information in the signal and allows sub-Nyquist sampling. The filtered signal is folded by the designed hardware and then sampled. For estimating the FRI parameters, the samples are first unfolded by using our algorithm presented in \cite{eyar_moduloicassp} and then the parameters are estimated by using annihilating filter approach. By using the fact that our algorithm operates at lowest possible rate, we show that FRI parameters can be estimated sub-Nyquist samples. In particular, we show that the system operates at five times the rate of innovation which is much lower than the Nyquist rate of the signal.
\end{itemize}

The paper is organized as follows. In the next section, we discuss the FRI signal model and its sampling and reconstruction framework in the presence of modulo hardware. In Section III, we present the actual hardware system by explaining its working principle and discussing the components of the system. In Section IV, we show the signal folding and reconstruction abilities of the hardware, and then the conclusion is followed.

\section{Signal Model and System Description}
In this section, we first introduce the FRI signal model and then discuss its sampling and reconstruction framework with modulo ADC.
\subsection{FRI Signal Model}
Consider an FRI signal consisting of stream of $L$ pulses:
\begin{align}
	f(t) = \sum_{\ell=1}^L a_\ell h(t-t_\ell),
	\label{eq:fri1}
\end{align}
where the pulse $h(t)$ a real-valued known pulse. We assume that $\{a_\ell\}_{\ell = 1}^L$ are real-valued and $\{t\}_{\ell = 1}^L \subset (0, T_0] \subset \mathbb{R}$ for a known $T_0$.

The FRI signal model in \eqref{eq:fri1} is encountered in several scientific applications such as radar imaging \cite{bar_radar, bajwa_radar, sunil}, ultrasound imaging \cite{eldar_sos,eldar_beamforming,mulleti_icip}, light detection and ranging (LIDAR) \cite{castorena_lidar}, time-domain optical-coherence tomography (TDOCT) \cite{blu_oct}, and other time-of-flight imaging systems. In these applications,  $h(t)$ is the transmitted pulse and $\{a_\ell \,h(t-t_\ell)\}_{\ell=1}^{L}$ constitute the reflections from $L$ point targets. The amplitudes $\{a_\ell\}_{\ell = 1}^L$ depend on the sizes of the targets and the delays $\{t\}_{\ell = 1}^L$ are proportional to the distances of the targets from the transmitter. Here $T_0$ denotes maximum time delay of the targets. The signal $f(t)$ is specified by $\{a_\ell, t_\ell\}_{\ell=1}^L$ and can be reconstructed from its sub-Nyquist measurements acquired using an appropriate sampling kernel \cite{vetterli,eldar_sos,fri_strang, mulleti_kernal}. The reconstruction is generally carried out in frequency domain as discussed next.

\subsection{Fourier-Domain Reconstruction}
Consider uniform samples of continuous-time Fourier transform of $f(t)$ given as
\begin{align}
	F(k \omega_0) = \int f(t) e^{-\mathrm{j} k\omega_0 t} \mathrm{d}t = H(k \omega_0) \sum_{\ell = 1}^L a_\ell \, e^{-\mathrm{j} k\omega_0 t_\ell},
	\label{eq:F}
\end{align}
for $k \in \mathcal{K}$. Here $H(\omega)$ is the Fourier transform of $h(t)$ and $\mathcal{K}$ is an integer set. In \eqref{eq:F}, $\omega_0>0$ denotes sampling interval in the frequency domain. Next, consider the following samples
\begin{align}
	S(k\omega_0) = \frac{F(k\omega_0)}{H(k\omega_0)} =  \sum_{\ell = 1}^L a_\ell \, e^{-\mathrm{j}k\omega_0 t_\ell},
	\label{eq:Skomega}
\end{align}
where we assume that $H(k \omega_0) \neq 0$ for $k \in \mathcal{K}$. In practice, the pulse $h(t)$ has small time support and hence, large bandwidth. Hence, for a finite set $\mathcal{K}$ it is possible to choose a set of frequencies $\{k \omega_0\}_{ k \in \mathcal{K}}$ such that $H(k \omega_0) \neq 0$. It can be shown that $2L$ consecutive samples of $S(k\omega_0)$ are sufficient to uniquely identify $\{a_\ell, t_\ell\}_{\ell=1}^L$ if $\omega_0 = \frac{2\pi}{T_0}$ \cite{eldar_2015sampling}.
In practice, high-resolution spectral estimation methods, such as the annihilating filter (AF) or Prony's method and its variants \cite{prony, plonka}, multiple signal classification \cite{schmidt_music, barabell_rmusic, bdrao_rmusic}, matrix-pencil method \cite{sarkar_mp}, estimation of signal parameter via rotational invariance technique (ESPRIT) \cite{paulraj_esprit}, etc., have been deployed for FRI parameter estimation.

Since $h(t)$ is known, $H(k\omega_0), k \in \mathcal{K}$ can be calculated in advance. Hence, to compute $S(k\omega_0), k \in \mathcal{K}$ and then to estimate the FRI parameters, $F(k\omega_0), k \in \mathcal{K}$ has to be determined. Next, we discuss a lowpass filter (LPF) based sampling framework to determine these Fourier samples.

\subsection{LPF-Based Sub-Nyquist Sampling}
\label{sec:lpf}
In this section, we discuss a LPF-based sampling mechanism for FRI signals. Let $g(t)$ denotes an ideal lowpass filter with cutoff frequency $\omega_c$ rad/sec. In the frequency-domain we have that $G(\omega) = 1$ for $\omega \in [-\omega_c, \omega_c]$ and zero for the rest of the frequencies. Let $y(t)$ denotes response of the LPF to the input $f(t)$, that is, $y(t) = (f*g)(t)$, where $*$ denotes linear convolution operation. Consider an ADC with dynamic range $[-\lambda, \lambda]$ and sampling rate $\omega_s = \frac{2\pi}{T_s}$ rad/sec. By assuming that  $\|y(t)\|_{\infty}\leq \lambda$, uniform samples at the output of ADC are given as $y(nT_s), n \in \mathbb{Z}$. Then uniform measurements of discrete-time Fourier transform (DTFT) of the samples are given as
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) = \sum_{n \in \mathbb{Z}}y(nT_s)\,e^{\mathrm{j} k\omega_0 n T_s}, \quad k \in \mathcal{K}.
	\label{eq:y_dtft}
\end{align}
By using relationship between DTFT of samples $y(nT_s)$ and CTFT of $y(t)$ we have
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) &= \frac{1}{T_s}\sum_{m \in \mathbb{Z}} Y(k\omega_0 + m \omega_s), \nonumber \\
	&= \frac{1}{T_s}\sum_{m \in \mathbb{Z}} F(k\omega_0 + m \omega_s) \,G(k\omega_0 + m \omega_s),
		\label{eq:y_dtft2}
\end{align}
where we used the fact that $Y(\omega) = F(\omega)\,G(\omega)$. Next, consider the following conditions on the sampling rate and cutoff frequency of the filter
\begin{align}
	\omega_s \geq 2\omega_c, \quad \text{and} \quad \omega_c \geq K \omega_0,
	\label{eq:sampling_rate}
\end{align}
where $K \geq L$. Then by choosing $\mathcal{K} = \{-K, \cdots, K\}$, \eqref{eq:y_dtft2} can be written as
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) = F(k\omega_0), \quad k \in \mathcal{K},
	\label{eq:y_dtft3}
\end{align}
where we used the fact that $G(k\omega_0) = 1$ in these settings. The relationship \eqref{eq:y_dtft3} shows that the desired Fourier samples of $f(t)$ are determined from the samples of LPF by assuming that the conditions in \eqref{eq:y_dtft2} are satisfied. Hence, FRI parameters can be determined from the samples of the lowpass filter. A LPF-based sampling for FRI signal was used in \cite{vetterli,uls_sparse} but with a periodic FRI signal model. With perodization, a finite number of time samples are sufficient to determine the desired Fourier measurements, whereas, countable infinite measurements are required in aperiodic settings consider here.

The bandwidth of the pulse $h(t)$ and hence that of the FRI signal $f(t)$ could be very large. But the sampling rate $\omega_s$ is independent of the pulse and could be much smaller than its bandwidth which shows the FRI signal could be reconstructed from sub-Nyquist samples.

The sub-Nyquist sampling framework discussed assumes that $\|y(t)\|_{\infty}\leq \lambda$, in other words, the framework assumes that the dynamic range of the ADC is greater than that of the signal to be sampled. However, this condition may not be always true. Specifically, the amplitude range of the filtered signal $y(t)$ could be larger than ADC's dynamic range. In such a scenario, a direct sampling would lead to clipping of samples which is undesirable. To avoid clipping, a modulo operator is employed prior to sampling as discussed next.

\begin{figure*}
	\centering
	\includegraphics[width=6.5 in]{Figs/FRI_US}
	\caption{A schematic of modulo-sampling and reconstruction of FRI signals.}
	\label{fig:fri_framework}
\end{figure*}

\subsection{Modulo-Folding}
To avoid clipping, a modulo folding operator $\mathcal{M}_\lambda(\cdot)$ is used after LPF and before the ADC. The operator folds $y(t)$ to stay within ADC's dynamic range $[-\lambda, \lambda]$. The output of the modulo operator in response to input $y(t)$ is given as
\begin{equation}
 y_\lambda(t) =	\mathcal{M}_{\lambda}(y(t)) = (y(t)+\lambda)\,\, \text{mod}\,\, 2\lambda -\lambda.
	\label{eq:mod_opp}
\end{equation}
The modulo signal can be express as a linear combination of the true signal and a residual signal:
        \begin{align}
            y_\lambda(t) = y(t) - z(t),
            \label{eq:resiudual}
        \end{align}
where values of the residual signal $z(t)$ are integer multiples of $2\lambda$.
The folded signal is then sampled by the ADC to have measurements $y_\lambda(nT_s)$. Since modulo folding is a nonlinear operation, one can not directly apply DTFT on the samples to compute Fourier measurements of the FRI signal for its reconstruction. Hence, the true or unfolded samples $y(nT_s)$ are estimated from the folded ones $y_\lambda(nT_s)$ by applying an unfolding algorithm. There exist several unfolding methods for bandlimited signals \cite{uls_tsp, uls_romonov,eyar_moduloicassp}.
The sampling rate for unfolding varies for different algorithms and generally, is larger than the minimum sampling rate required for FRI signal recovery (cf. \eqref{eq:sampling_rate}).
Hence, the overall system operates on a higher sampling rate than that without a modulo case. However, if the overall sampling rate is much lower than the bandwidth of the FRI signal then the system operates at a sub-Nyquist rate. We show that this is indeed true when we apply our unfolding algorithm proposed in \cite{eyar_moduloicassp}.

An end-to-end modulo sampling framework for FRI signal sampling and reconstruction is shown in Fig.~\ref{fig:fri_framework}. The sampler or ADC together with the modulo block is termed as modulo-ADC.
Modulo-ADCs are able to sample signals beyond their dynamic range without clipping and hence they are termed as high-dynamic range ADCs. Alternatively, an ADC with a  much lower dynamic range can be used to sample signals with larger amplitudes. Sub-Nyquist sampling and low-dynamic range requirements significantly reduce the power consumption and cost of the ADC.

The modulo folding block is key component of the high-dynamic range ADC and we discuss its hardware implementation in the next section.

\begin{figure}
	\centering
	\includegraphics[width= 3 in]{Figs/folding}
	\caption{Folding principle}
	\label{Fig:folding}
\end{figure}
\section{Modulo Hardware Prototype}
In this section, we discuss our modulo hardware prototype. First, we will explain the working principle of the modulo block and describe its design and then discuss hardware realization.
\subsection{Working Principle of Modulo Block}
The principle of computing $y_\lambda(t)$ from $y(t)$ is shown by the block diagram in Fig.~\ref{Fig:folding}. The system comprises of an adder $S$, a direct-current voltage generator (DC-VG), and two comparators $C_1$ and $C_2$. To understand the working flow, let us first assume that for some time instant $t_1$, we have that $|y(t)|<\lambda$ for $t<t_1$. Hence $y_\lambda(t) = y(t)$ and $z(t) = 0$ for $t<t_1$. At $t=t_1$, let $|y(t)|$ crosses $\lambda$. If $y(t_1)>\lambda$, then the comparator $C_1$ triggers a positive value or else, $C_2$ triggers a negative value. The DC-VG is designed such that for every positive value input, it reduces its output signal level by $-2\lambda$, whereas, for negative value, it increases its output voltage by $2\lambda$. Hence, in the current example, DC-VG generates signal $z(t) = \text{sgn}(y_\lambda(t_1)) 2\lambda u(t-t_1)$ where $u(t)$ is unit-step function. In this way, by adding or subtracting (using $S$) constant DC signals from $y(t)$ whenever it crosses dynamic range $[-\lambda, \lambda]$, the amplitude levels of $y_\lambda(t)$ are kept within ADC's dynamic range.

\begin{figure}[!h]
	\centering
	\begin{tabular}{c}
		\subfigure[Live screen shot of an oscilloscope capturing the input signal (yellow), its folded output (green), the DC-VG signal (blue) and C1 comparator (red).
		] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Fig3_2Folding_6Vpp_3Vbias_1KHz_Up_Clr.png}\label{fig:Up_Folding}} \\
		\subfigure[Live screen shot of an oscilloscope capturing the input signal (yellow), its folded output (green), the DC-VG signal (blue) and C2 comparator (red).
		] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Fig3_2Folding_6Vpp_3Vbias_1KHz_Down_Clr.png}\label{fig:Down_Folding}} \\
	\end{tabular}
	\caption{DC-VG folding mechanism.}
	\label{Fig:DC-VG_folding_mechanism}
\end{figure}

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3 in]{Figs/dc_vg}
	\caption{DC-VG}
	\label{Fig:dcvg}
\end{figure}

\begin{figure*}[!t]
	\centering
	\includegraphics[width=0.86\textwidth ]{IEEE_TAES_v1/Figs/UDR_Board_Labeled3.PNG}
	\caption{Modulo hardware board.}
	\label{Fig:hw_board}
\end{figure*}

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3.2 in]{IEEE_TAES_v1/Figs/Fig6_1KHz_10Vpp_4Folding_New_Clr.png}
	\caption{
	Live screen shot of an oscilloscope capturing the 1kHz sinusoid input signal (yellow), its folded output (green) and the DC-VG signal (blue).}
	\label{Fig:Analysis_of_folding_ability}
\end{figure}

\begin{figure}[!h]
	\centering
	\begin{tabular}{c}
		\subfigure[Live screen shot of an oscilloscope capturing the 1kHz sinusoid input signal (yellow), its folded output (green) and the DC-VG signal (blue).] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Fig7_1Folding_6Vpp_1KHz_New_Clr.png}\label{fig:1k_1}} \\
		\subfigure[Live screen shot of an oscilloscope capturing the 10kHz sinusoid input signal (yellow), its folded output (green) and the DC-VG signal (blue).] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Fig7_1Folding_6Vpp_10KHz_New_Clr.png}\label{fig:10k_1}} \\
		\subfigure[Live screen shot of an oscilloscope capturing the 20kHz sinusoid input signal (yellow), its folded output (green) and the DC-VG signal (blue).] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Fig7_1Folding_6Vpp_20KHz_New_Clr.png}\label{fig:20k_1}}
	\end{tabular}
	\caption{Analysis of frequency response of the modulo hardware.}
	\label{Fig:frequency_response}
\end{figure}

\begin{table}[h!]
		\caption{Folding Operation.}
	\centering
	\begin{tabular}{||c c c c c ||}
		\hline
		c & b & a & sgn & Counter values \\ [0.5ex]
		\hline\hline
		0 & 0 & 0 & 0~(1) & 0~(0) \\
		0 & 0 & 1 & 0~(1) & 1~(-1) \\
		0 & 1 & 0 & 0~(1) & 2~(-2) \\
		0 & 1 & 1 & 0~(1) & 3~(-3) \\
		1 & 0 & 0 & 0~(1) & 4~(-4) \\
		1 & 0 & 1 & 0~(1) & 5~(-5)\\
		1 & 1 & 0 & 0~(1) & 6~(-6)\\
		1 & 1 & 1 & 0~(1) & 7~(-7)\\
		\hline
	\end{tabular}
	\label{table:counter}
\end{table}

While the parts such as comparators $C_1$, $C_2$, and adder $S$ can be realized by using off-the-shelf components, DC-VG is a more involved system and required careful design. A detailed architecture of DC-VG is shown in Fig.~\ref{Fig:dcvg}. It consists of an up/down counter, a digital-to-analog converter (DAC), a multiplexer (MUX), and a multiplier $M$.  The role of the counter (together with DAC) is to generate a variable, but controlled DC voltage whenever there is a trigger at its input. The voltage values are set to be multiple of $2\lambda$ by using the MUX and multiplier $M$.
To elaborate the working principle, we first discuss the role of the counter and then the rest of the components.

In this particular system, we use a three-bit synchronous up/down counter. The bits from lower significant bit to higher significant bit are denoted as a, b, and c. The counter has an additional sign bit shown as sgn. With these bits, the counter can count from -7 to 7. For every positive trigger at the input the output counts up and with a negative trigger it counts down. In Table~\ref{table:counter}, we display the values of bits and the counter (denoted as counter values). The three bits (a,b, and c) of the counter are used as input to the DAC which converts the bits to analog DC voltages. Let the resolution or step size of the DAC is $\alpha$ then the output of DAC is $\alpha$ times the counter-value. To be more specific, consider the scenario where the output of counter and DAC are zero. Then for a positive (negative) trigger, the output of DAC increases (decreases) by $\alpha$. Specifically, the output of DAC, $s(t)$, is a piecewise constant signal with values that are multiples of $\alpha$. However, for folding to work, the change in the voltage should be in multiples of $2\lambda$. To ascertain that we use a MUX which outputs either $2\lambda$ or $-2\lambda$ depending on whether its input is 1 or 0. Then by multiplying the output of DAC with the output of MUX we generate $z(t)$.

The DC-VG operation can be seen in Fig  \ref{Fig:DC-VG_folding_mechanism} at the screenshots of an oscilloscope capturing input $y(t)$ (in yellow), its folded output $y_\lambda(t)$ (in green), $z(t)$ (in blue) and C1/C2 comparators respectively which triggers the +2$\lambda$ operation (in red).
In order to better illustrate the DC-VG counter up and down operation we capture Fig \ref{fig:Up_Folding} and Fig \ref{fig:Down_Folding} respectively.
Fig \ref{fig:Up_Folding} demonstrates the folding operation time sequence from the C1 comparator trigger operation (in red), following with a ramp of 2$\lambda$ of $z(t)$ (in blue) which result in increase of $y_\lambda(t)$ (in green) by 2$\lambda$ and keeping it at the +-2$\lambda$ ADC range.

Fig \ref{fig:Down_Folding} demonstrates the folding operation time sequence from the C2 comparator trigger operation (in red), following with a ramp of -2$\lambda$ of $z(t)$ (in blue) which result in increase of $y_\lambda(t)$ (in green) by -2$\lambda$ and keeping it at the +-$\lambda$ ADC range.

Next, we discuss the hardware board that realizes the folding operation discussed in this section.

\begin{table}[h!]
\centering
\caption{List of Hardware Components}
\label{table:hardware_components}
\begin{tabular}{||c c c||}
 \hline
 Component & Model Number & Make \\
 && \\ \hline
 Comparator & LM339 & Texas Instruments \\
 && \\
 UP/DOWN Counter & TEENSY4.1 & PJRC \\
 && \\
 DAC 3bits & LT1364 & Analog Devices \\
 && \\
 Analog MUX & ADG1608 & Analog Devices \\
 && \\
 Analog Multiplier & AD835 & Analog Devices \\
 && \\
 Adder & LT1364 & Analog Devices \\
  && \\ [1ex]
\hline
\end{tabular}
\end{table}
\subsection{Modulo Hardware Board}
Our modulo hardware board is shown in Fig.~\ref{Fig:hw_board} with main role of the various building components are marked. The details of the components of the hardware are listed in Table~\ref{table:hardware_components}. The board is designed for $\lambda \leq 1.25$ volts. The board can accommodate an input signal with a dynamic range between $[-4\lambda, 4\lambda]$ which implies that an ADC with our modulo hardware can sample four-times larger signals compared to its dynamic range without saturation and clipping.

We demonstrate the working of the modulo hardware by considering a sinusoidal signal $y(t) = A\, \sin(2\pi f_0 t)$ where $A$ is amplitude and $f_0$ is frequency (in Hz). In this experiment, we set $\lambda = 1.25$ and $-4\lambda <A <+4\lambda$. With these settings, we expect the signal to fold 4 times in a quarter cycle of a sinusoid. Figs.~\ref{Fig:Analysis_of_folding_ability} screenshot of an oscilloscope capturing input $y(t)$ (in yellow) and its folded output $y_\lambda(t)$ (in green) in addition the DC-VG output signal $z(t)$ (in blue), for $f_0 = 1$ KHz. We observed that the signals are folded back to lie within the dynamic range of the ADC as expected without clipping. Next we will discuss the different frequencies in order to study the frequency response of the modulo folder. As in any analog system, the response of the modulo folder too depends on the frequency or bandwidth of the input signal. Beyond a particular frequency, the folding may not be accurate as observed in Fig.~\ref{Fig:frequency_response}. We observed that for signals of 1 kHz and 10kHz the hardware is able to fold the signal accurately. However, for $f_0 = 20$ kHz, folding instants are not symmetric for positive and negative folds. In one of our future works, we are planning to design a hardware that overcome this limitation by using faster hardware logical components to implement the folding counter instead of using the current up/down counter. The current implementation demonstrates a prof of concept of implementing the modulo concept in the analog domain at near real life environment and pave the way for a high frequency applications which supports high dynamic range operation.

In the next section, we discuss a couple of inaccuracies of the modulo hardware and our proposed solutions to overcome those.

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3.2 in]{Figs/mod_td}
	\caption{Effect of time delay of the feedback loop on the modulo operation.}
	\label{Fig:mod_td}
\end{figure}

\subsection{Artifacts During Folding}
Errors or other artifacts that arise during folding operation in hardware could be due to various reasons. For example, in Figs.~\ref{Fig:Analysis_of_folding_ability} and \ref{Fig:frequency_response}, we observe that the amplitude of the folded signals could go beyond the dynamic range momentarily around the folding instants. This is due to the settling time of the DC-VG when voltage values change. Specifically, after switching, the voltage at the output of DC-VG overshoots and undershoots before the oscillations settle down to the expected value. This can be overcome by using a faster adder $S$ whose response time should be at least a magnitude higher than the sample rate.

Another major issue that arises in a folding ADC is a time delay in the feedback loop (See Fig.~\ref{Fig:folding}). To elaborate, consider a scenario where $y(t)<\lambda$ for $t<t_1$ and it crosses $\lambda$ at time $t_1$ as discussed earlier. To fold the output voltage to the dynamic range of the ADC, $z(t) = -2\lambda u(t-t_1)$ needs to be added to $y(t)$. However, there is a finite delay between the trigger time $t_1$ to generating $z(t)$. If the time delay is $T_d$, then $z(t) = -2\lambda u(t-t_1-T_d)$ is added which causes distortion. To illustrate this effect in Fig.~\ref{Fig:mod_td} by considering a sinusoidal signal (in blue) and its folded versions with and without delay. We observe that in the absence of any time delay ($T_d=0$) the signal folds perfectly (shown in red) to stay within the dynamic range. However, for a non-zero value of $T_d$, foldings do not take place at the folding instants and the output of the modulo operator (shown in black) still remains outside the dynamic range $[-\lambda, \lambda]$. We propose a hardware solution to address this issue.

Our solution uses the fact that with a finite time delay, the amount of overshoot of a smooth signal can be bounded. To elaborate, let us assume that the signal that undergoes modulo operation is Lipschitz continuous. Specifically, a signal $y(t)$ is Lipschitz continuous if there exists a positive real number $\mathrm{L}_y$ such that for any $T>0$ we have
\begin{align}
    |y(t) -y(t+T)|\leq \mathrm{L}_y\, T.
    \label{eq:lipschitz}
\end{align}
With the Lipschitz smoothness condition, we note that the amplitude of $y(t)$ can not change more than $\mathrm{L}_y\, T_d$ between any folding instant and time of its effect to take place. Hence, if we choose dynamic range of the ADC to be $[-(\lambda+\Delta \lambda), (\lambda+\Delta \lambda)]$ where $\Delta \lambda = \mathrm{L}_y\, T_d$ then the signal will not clip. We show this extended dynamic region in the illustrative example in Fig.~\ref{Fig:mod_td}. Alternatively, instead of increasing ADC's dynamic range, one can keep it to be $[-\lambda, \lambda]$ and reduce the threshold values for comparators. In this case, $C_1$ will trigger when the input crosses $\lambda-\Delta \lambda$ and $C_2$ will trigger when input goes beyond $-\lambda+\Delta \lambda$. In this way, the time delay issue is addressed by the modulo circuit without altering ADC's dynamic range.

To implement the mentioned solution, the signal should be Lipschitz continuous. In our setup, the input to modulo operation is a lowpass or bandlimited signal which always satisfies the Lipschitz smoothness condition \cite{bl_bound}. For a bandlimited signal $y(t)$ its Lipschitz constant $\mathrm{L}_y$ is directly proportional to its bandwidth $\omega_c$ which is the same as the cutoff frequency of the LPF.
Hence, for a given value $\Delta \lambda$ and $T_d$ (both depend on the modulo circuit), $\mathrm{L}_y = \Delta \lambda/T_d$ is fixed and this restricts the maximum frequency of the input signal that can be faithfully folded. In the current design, we chose to implement the counter management by a TEENSY micro-controller which results in a time delay of $1 \mu$s which enable the hardware to support a wide range of frequencies with no need to modify the hardware components. In order to support higher frequencies, alternative design strategies with a faster response time and lower delay should be used.

\section{Results}
In this section, we show the signal reconstruction ability of the modulo hardware described in the previous section. From Fig.~\ref{fig:fri_framework}, we understood that the signal reconstruction ability is a function of LPF $g(t)$, modulo circuit $\mathcal{M}_\lambda(\cdot)$, ADC or sampler, unfolding algorithm, and parameter estimation method. Any error in the estimation of FRI parameters is a result of flaws and limitations of the hardware realizations and limitations of the algorithms in the presence of measurement noise. For example, ideally $g(t)$ should have infinite impulse response, however, only a truncated version could be realizable in hardware. The truncation will result in errors while determining the Fourier samples of the FRI signal (See Section~III.\ref{sec:lpf}). Similarly, quantization plays a role when a finite resolution quantizer is used after the sampler. In addition, all the hardware components contribute to different types of noise. We model all these noises and inaccuracies as additive noise at the output of the sampler. Specifically, the noisy measurements are given as
 \begin{align}
            \tilde{y}_{\lambda}(n T_s) = {y}_{\lambda}(n T_s) + v(n T_s),
        \label{eq: noisy_samples}
        \end{align}
where $v(n T_s)$ is the noise term. Both unfolding and parameter estimation algorithms should be robust to different noise models. The robustness of parameter estimation methods in the presence of noise is well studied (See \cite{mulleti_kernal, stoica, eldar_sos}). In \cite{eyar_moduloicassp}, we presented comparisons of unfolding algorithms for bandlimited signals. We showed that our beyond-bandwidth residual recovery ($B^2R^2$) approach results in lower error during unfolding compared to the \emph{higher-order differences} (HOD) approach \cite{unlimited_sampling17, uls_tsp} and \emph{Chebyshev polynomial filter}-based (CPF) method \cite{uls_romonov}. Importantly, for a given sampling rate, $\lambda$, and signal to noise ratio (SNR), $B^2R^2$ method results in the lowest error for both bounded and unbounded noise models.

Before presenting hardware results, we compare the performances of the $B^2R^2$ method with HOD and CPF approaches for quantization noise and unbounded noise. We would like to point out that quantization noise was not considered in \cite{eyar_moduloicassp}. Although, the algorithms were compared for unbounded noise but the simulation settings were different than those in our hardware. Hence, for a better understanding, we compared our algorithm for unbounded noise and quantizaition  noise with the current hardware settings. In the next section, we present these simulation results and then present hardware results.

\begin{figure}[!t]
	\centering
	\includegraphics[width= 2.5 in]{IEEE_TAES_v1/Figs/quantization.png}
	\caption{Comparison of HOD, CPF and $B^2R^2$ algorithms after the quantization process in terms of MSE when recovering a bandlimited signal from modulo samples with $\lambda = 1.25$ and OF = 3,6. For a given number of bits, $B^2R^2$ has the lowest MSE.}
	\label{Fig:quantization}
\end{figure}

\begin{figure}[!t]
	\centering
	\includegraphics[width= 2.5 in]{IEEE_TAES_v1/Figs/Gaussian.png}
	\caption{Comparison of HOD, CPF and $B^2R^2$ algorithms (with unbounded noise) in terms of MSE when recovering a bandlimited signal from modulo samples with  $\lambda$ = 1.25 and OF = 3,6. For a given SNR and OF, $B^2R^2$ has lowest MSE.}
	\label{Fig:unbounded}
\end{figure}
\subsection{Simulated Results}
In this section, we compare our $B^2R^2$ algorithm with the \emph{higher-order differences} (HOD) approach \cite{unlimited_sampling17, uls_tsp} and \emph{Chebyshev polynomial filter}-based (CPF) method \cite{uls_romonov}. We consider the noise measurements as in \eqref{eq: noisy_samples} for a simulation data. In the simulations, $\lambda$ is set to be $1.25$ as in the hardware. We normalize the bandlimited signals to have maximum amplitude of $10$. The SNR is calculated as $\text{SNR} = 20 \log\left(\frac{||y_{\lambda}(n T_s)||}{||v(n T_s)||}\right)$. The reconstruction accuracy of different methods is compared in terms of normalized mean-squared error (MSE) as $ \frac{\sum |y(nT_s) - \hat{y}(n Ts)|^2}{\sum |y(nT_s)|^2}$, where $\hat{y}(n T_s)$ estimate of $y(n T_s)$. For different noise settings and over-sampling factors (OFs), we considered 100 independent noise realizations and calculated the average MSE for them. We first consider quantization noise and then present results for unbounded noise.

\begin{figure}[!t]
    \centering
    \includegraphics[width=0.3\textwidth]{IEEE_TAES_v1/Figs/Signal Generator.png}
    \caption{Bandlimited signal generator.}
    \label{fig:UDRSignalGen}
\end{figure}

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3.2 in]{IEEE_TAES_v1/Figs/Up_2mS_Clr.png}
	\caption{Bandlimited folded signal.}
	\label{Fig:Bandlimited_folded_signal}
\end{figure}

 First, we consider an uniform quantizer after the sampling. The unfolding algorithms are applied on the quantized samples. The MSE in the estimation of bandlimited signals for a different number of bits and OFs is shown in Fig. ~\ref{Fig:quantization}. We observe that for a given $\text{OF}$, $B^2R^2$ algorithm results in the lowest MSE for less than 5 bits. For more than 5 bits all the algorithms, except HOD with OF = 3, perform equally well. The results show that low-resolution quantizers can be used with $B^2R^2$ algorithm for unrolling which saves both power and memory requirements.

Next, for unbounded noise, we assume that the noise measurements $v(nT_s)$ are independent and identically distributed Gaussian random variables with zero mean. The variance is set to achieve a desired SNR. We compare the methods for different values of SNR and OFs with $\lambda = 1.25$. Fig.~\ref{Fig:unbounded} shows MSE of the different algorithms for OF $= 3$ and $6$. We note that our algorithm results in lowest error for a given OF and SNR.

Given the advantages of $B^2R^2$ algorithm over the other approaches, we present the hardware results in the next section by using this method.

\begin{figure*}[!t]
	\centering
	\begin{tabular}{cc}
		\subfigure[]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/BL1_scope_11_Clr.png}\label{fig:BL1_scope}} &
		\subfigure[]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/BL2_scope_13_Clr.png}\label{fig:BL2_scope}}
	\end{tabular}
	\caption{Live screen shot of an oscilloscope capturing the input bandlimited signals (yellow) and its folded output signals (green).}
	\label{fig:BL_scopeex1}

\end{figure*}
\begin{figure*}[!t]
	\centering
	\begin{tabular}{cc}
		\subfigure[]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/BL1_rec.png}\label{fig:BL1}} &
		\subfigure[]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/BL2_rec.png}\label{fig:BL2}}
	\end{tabular}
	\caption{Hardware results for bandlimited signals. The $B^2R^2$ algorithm is used to unfold $y_\lambda(t)$ (measured at the output of hardware) and the unfolded signal $\hat{y}(t)$ is plotted with bandlimited signal $y(t)$.}
	\label{fig:BL_ex1}
\end{figure*}

\begin{figure*}[!t]
	\centering
	\begin{tabular}{ccc}
		\subfigure[]{\includegraphics[width=2.2in]{IEEE_TAES_v1/Figs/Ex1_lpf.pdf}\label{fig:FRI11}} &
		\subfigure[]{\includegraphics[width=2.1in]{IEEE_TAES_v1/Figs/Ex2_lpf.pdf}\label{fig:FRI12}}&
		\subfigure[]{\includegraphics[width=2.1in]{IEEE_TAES_v1/Figs/Ex3_lpf.pdf}\label{fig:FRI13}}\\
		\subfigure[]{\includegraphics[width=2.1in]{IEEE_TAES_v1/Figs/Ex1_fri.pdf}\label{fig:FRI21}} &
		\subfigure[]{\includegraphics[width=2.1in]{IEEE_TAES_v1/Figs/Ex2_fri.pdf}\label{fig:FRI22}}&
		\subfigure[]{\includegraphics[width=2.1in]{IEEE_TAES_v1/Figs/Ex3_fri.pdf}\label{fig:FRI23}}
	\end{tabular}
	\caption{Hardware results for FRI signals: Top row shows three examples of lowpass filtered FRI signals $y(t)$, modulo outputs $y_\lambda(t)$, and unfolded signals $\hat{y}(t)$; bottom row shows true FRI signal $f(t)$ and its estimate $\hat{f}(t)$.}
	\label{fig:FRI_ex}
\end{figure*}

\subsection{Hardware Results}
In this section, we present results from the hardware.
Since bandlimited signals are input to the hardware , we first present results for them and then show results for FRI signals. If the hardware and unfolding algorithm is able to recover the bandlimited signals with high accuracy than it will leads to better reconstruction of the FRI signals. In all these experiments we set $\lambda = 1.25$ V and the cutoff frequency of the lowpass filter is 1 kHz. We observe that for frequencies less than or equal to 10 kHz, our hardware is able to reliably fold the signal. The Nyquist rate of the signal is 2 kHz. But for unfolding we need to oversample the signal. In all these experiments, we used $B^2R^2$ algorithm with OF = 5 which results in sampling rate of 10 kHz. Further, $y(t)$ and $y_\lambda(t)$ are measured from the hardware through an oscilloscope for processing by the algorithms as described in Fig. \ref{Fig:Bandlimited_folded_signal}.

We first consider the bandlimited signals. For generating bandlimited or lowpass signals we used a Arduino micro-controller (See Fig.~\ref{fig:UDRSignalGen}) which convert the digital signal to an analog signal via a DAC. The digital signals were generated using MATLAB software as can be seen in Fig. \ref{fig:BL_scopeex1} while Fig. \ref{fig:BL1_scope} is a 1khz bandlimitted signal with xxx time instances and Fig. \ref{fig:BL2_scope} is a 1khz bandlimitted signal with xxx time instances respectively. In Fig.~\ref{fig:BL_ex1}, we show folding and reconstruction of the two bandlimited signals as described in Fig. \ref{fig:BL_scopeex1}. These signals have maximum amplitude of 5 V. We observe the signals are restricted to $[-\lambda, \lambda]$ by the modulo hardware and the algorithm was able to recover the true signal from the folded samples. The reconstructed signal has slightly larger amplitude compared to the true signal which is result of scaling within the hardware.

Next, we consider reconstruction of FRI signals from modulo samples. To generate the FRI signals, we consider $h(t)$ to be a sort pulse of bandwidth 30 kHz (Nyquist rate = 60 kHz). We consider three examples with $L=2, 3,$ and 5. The amplitudes and time delays are generated randomly. The maximum time delay is $T_0 = 0.1$ sec. Once generated, the FRI signal is lowpass filtered with a cutoff frequency of 1 kHz. Up to filtering operation, MATLAB is used and then Arduino micro-controller is used to generate the analog version of the filtered FRI signals. The signal is then folded using the hardware and folded signals are sampled. The sampling rate is 10 kHz which is five times higher than the sampling rate of the lowpass signal. Still the rate is six times lower than the Nyquist rate and hence the system operates at sub-Nyquist rate. The setup satisfies the conditions in \eqref{eq:sampling_rate} for $L=2, 3,$ and 5.

We first apply $B^2R^2$ algorithm to unfold the signal and then used ESPRIT \cite{paulraj_esprit} to estimate the time delays and amplitudes of the FRI signals. We show FRI signal sampling and reconstruction in Fig.~\ref{fig:FRI_ex} where the top row shows LPF output $y(t)$, folded signal (output of the modulo hardware) $y_\lambda(t)$, and unfolded signals $\hat{y}(t)$. The bottom row shows location and amplitude of the true signal $f(t)$ and estimated FRI signal $\hat{f}(t)$. The maximum error in the estimation of time delay $-15$ dB which shows that the system can be used in applications like radar and ultrasound imaging.

\section{Conclusions}
We considered the problem of recovering FRI signals from low-pass filtered, modulo samples. We presented a hardware prototype for the modulo folding system and show that for different bandlimited and FRI signals, the hardware is able to faithfully fold the signal. We also  address the time delay issue of the modulo system and presented a hardware solution for the same. The overall system operates at six times below the Nyquist rate which enables one to use low rate, low-dynamic range, power efficient ADCs.

\bibliographystyle{IEEEtaes}

\section{INTRODUCTION}
Sampling plays a key role in efficiently processing real-world analog signals on digital signal processors. Analog to digital converters (ADCs) are used to implement sampling in the hardware. A key parameter of an ADC is its sampling rate. ADCs with high sampling rates are power-consuming and expensive, making them unsuitable for portable devices such as hand-held ultrasound devices. Hence, it is desirable to reduce the sampling rate.
FRI model is ubiquitous in several time of flight applications \cite{bajwa_radar, bar_radar,filho201seismic,rip,carter_sonar,eldar_sos,eldar_beamforming, sunil} where the signal of interest is represented as a linear combination of delayed copies of a known pulse. Thus, the desired information lies in the amplitudes and time delays of the pulse.
Signals with finite rate of innovation (FRI) have few degrees of freedom which aids in sub-Nyquist sampling \cite{eldar_2015sampling}. That is, signal is sampled at a rate much lower than the Nyquist rate \cite{shannon, nyquist} and hence low power ADCs could be used.

Most existing works in the context of FRI sampling focus on reducing the ADC's sampling rate by using the signal structure \cite{vetterli, eldar_sos, fri_strang, blu_moms, mulleti_kernal} and ignores other aspects of the ADC. These aspects may plays a key role in faithful sampling and reconstruction, especially when the sampling frameworks are implemented in hardware. We focus on one such aspect which arises during the hardware realization of sampling mechanism.  Specifically, we address the dynamic range issue of ADCs.
The dynamic range of an ADC plays a crucial role in sampling an analog signal. ADC's dynamic range should generally be larger than the signal's; otherwise, the signal gets clipped. A few approaches exist to recover the true samples from clipped ones for bandlimited signals \cite{marks_clipping2, marks_clipping1}. These approaches rely on the correlation among the samples when they are measured at a very high rate compared to the Nyquist rate. The requirement of a high sampling rate is a drawback of these approaches. In addition, theoretical guarantees are missing, and it is unclear how many clipped samples can be recovered.

There are several preprocessing approaches such as automatic gain control (AGC) \cite{perez2011automatic,mercy1981review}, companding \cite{landau_compander,landau_distorted_bl}, and modulo folding \cite{uls_tsp,uls_romonov,uls_sparse,bhandari2021unlimited,eyar_moduloicassp}, that can be used prior to sampling to avoid clipping. Among these, modulo folding is most recent approach that need not be differentiable like companding and does not suffer from stability issues of the feedback amplifiers used in AGC. In the modulo framework, the signal is folded to lie within ADC's dynamic range and then the folded signal is sampled by using a conventional ADC. Theoretical guarantees for recovering bandlimited signals from folded samples are presented in \cite{uls_tsp,uls_identifiability}. The results state that bandlimited signal can be uniquely recovered from its folded samples provided that they are sampled above the Nyquist rate \cite{uls_tsp,uls_identifiability}.

Several algorithms for \emph{unfolding} or recovering the true samples of bandlimited signal from a modulo or folded samples are presented in \cite{uls_tsp,uls_romonov, eyar_moduloicassp}. These unfolding algorithms can be compared in terms of sampling rate, amount of unfolding they can handle, and noise robustness. It is shown that the method proposed in \cite{eyar_moduloicassp} required a lower sampling rate even in the presence of noise compared to the algorithms presented in \cite{uls_tsp,uls_romonov}.
In particular, the algorithm proposed in \cite{uls_tsp} requires almost 17-times higher sampling rate than the Nyquist rate, whereas, the reconstruction methods in \cite{uls_romonov, eyar_moduloicassp} require sampling rate slightly above the Nyquist rate.
Moreover, the method in \cite{uls_tsp} independent of the dynamic range of the ADC. Whereas, the approaches in \cite{uls_romonov, eyar_moduloicassp} requires the knowledge of ADC's dynamic range. Modulo sampling is also extended to different problems and signal models such as periodic bandlimited signals \cite{bhandari2021unlimited}, wavelets \cite{uls_wavelet}, mixture of sinusoids \cite{uls_sinmix}, finite-rate-of-innovation signals \cite{uls_fri}, multi-dimensional signals \cite{uls_md}, sparse vector recovery \cite{uls_gamp, uls_sparsevec}, direction of arrival estimation problem \cite{uls_doa}, computed tomography \cite{uls_radon}, and graph signals \cite{uls_graph}.

While theoretical guarantees and algorithms of any new sampling approach are always well researched but the question of whether they work in practice is difficult to answer. For modulo sampling, there exists a few hardware prototypes. For example, high-dynamic-range ADCs, also known as \emph{self-reset} ADCs, are discussed in the context of imaging \cite{sradc_park, sradc_sasagwa, sradc_yuan, krishna2019unlimited}. These hardware architectures measure additional information such as the amount of folding for each sample, or, the sign of the folding together with the folded samples. The additional information might enable simpler recovery but at the expense of complex circuitry. Importantly, additional bits are required during the quantization process to store or transmit the side information.

Krishna et al. presented a hardware prototype which encode the side-information by using two bits \cite{krishna2019unlimited}. The architecture is designed to record sign of the slope of the signal at each sample that lies outside the ADC's dynamic range. In a conventional ADC, a sample and hold (S/H) circuit is used to hold the sampled value for a prescribed period of time during which quantization is performed on the sample. To realize the modulo sampling, a folding circuit is used after S/H \cite{krishna2019unlimited}. Hence, the S/H circuit has to hold the sampled value for folding and quantization, which results in a larger holding time compared to a conventional ADC. A large holding time results in slower ADC and hence it may not be useful for wideband applications.

The modulo hardware prototypes where the modulo part is implemented prior to sampler are presented in \cite{bhandari2021unlimited,Bhandari:2022:J,mod_hyst}. Since the modulo circuit is not a part of the hold time, the ADC could be faster than the hardware realization in \cite{krishna2019unlimited}.  In \cite{mod_hyst}, the authors discussed a few implementation issues of modulo hardware such as hysteresis and folding transients. Further, they proposed algorithmic solutions to mitigate them. Both these issues can also be addressed by careful calibration and by using high precision components \cite{mod_hyst}. In \cite{Bhandari:2022:J}, Bhandari showed reconstruction of FRI signals by using a modulo hardware. In \cite{bhandari2021unlimited,Bhandari:2022:J,mod_hyst}, rather than providing details of the hardware circuitry the authors are focused on different signal models, hardware-limitations, and algorithms. They showed that the modulo hardware is able to fold low frequency signals that are 10-12 times larger than the ADC's dynamic range.

In this paper, we present a modulo hardware prototype which can be used in low-power time-of-flight applications, and show that by using our algorithm \cite{eyar_moduloicassp} it is able to faithfully reconstruct FRI signals.
In the following, we present the contributions and the salient features of the proposed hardware system.
\begin{itemize}
    \item As an initial step, we design our hardware components to be able to fold signals up to 10kHz. Note that no existing hardware is capable of handling such frequency input signals.

    \item The hardware prototype is designed to perform folding operation prior to the sampler unlike the hardware in \cite{krishna2019unlimited} which operates in the hold part of the sampler.  Thus, the suggested system can utilize faster ADCs with shorter hold time.
    \item Modulo folding is realized through a feedback mechanism. The time instants at which the input signal goes beyond the ADC's dynamic range, a trigger signal is generated by using comparators. The trigger then activates a direct-current (DC) generator that adds to the input signal to bring it to stay within the dynamic range. This mechanism imposes a delay between the instance delay (when the signal amplitude exceeds the dynamic range) and the folding instance.
    We address this key issue of the hardware which is not considered in the previous works.
    By using the smoothness of the signal and time delay of the feedback loop, we demonstrate that the clipping occurred due to delay issue can be mitigated. alternately we demonstrate that by using tunable threshold voltages at the comparators, the time delay issues can be resolved for signals with different bandwidths.
    \item To demonstrate an application of the hardware capabilities, we consider sampling and reconstruction of FRI signals. We use a lowpass filter (LPF) prior to modulo system as a sampling kernel. The filter removes unwanted information in the signal and allows sub-Nyquist sampling. The filtered signal is folded by the designed hardware and then sampled. For estimating the FRI parameters, the samples are first unfolded by using our algorithm presented in \cite{eyar_moduloicassp} and then the parameters are estimated by using the annihilating filter approach. We show that FRI parameters can be estimated with sub-Nyquist samples by utilizing the fact that our algorithm operates at the lowest possible rate. In particular, we demonstrate that the system functions at five times the rate of innovation, which is significantly lower than the signal's Nyquist rate.
    \item Since the output of the LPF is a bandlimited signal, the proposed framework is also useful for modulo-sampling bandlimited signals as shown in the results.

\end{itemize}

The paper is organized as follows. In the next section, we discuss the FRI signal model and its sampling and reconstruction framework in the presence of modulo hardware. In Section III, we present the actual hardware system by explaining its working principle and discussing the components of the system. In Section IV, we show the signal folding and reconstruction abilities of the hardware, and then the conclusion is followed.

\section{Signal Model and System Description}
In this section, we first introduce the FRI signal model and then discuss its sampling and reconstruction framework with modulo ADC.
\subsection{FRI Signal Model}
Consider an FRI signal consisting of stream of $L$ pulses:
\begin{align}
	f(t) = \sum_{\ell=1}^L a_\ell h(t-t_\ell),
	\label{eq:fri1}
\end{align}
where the pulse $h(t)$ a real-valued known pulse. We assume that $\{a_\ell\}_{\ell = 1}^L$ are real-valued and $\{t_\ell\}_{\ell = 1}^L \subset (0, T_0] \subset \mathbb{R}$ for a known $T_0$.

The FRI signal model in \eqref{eq:fri1} is encountered in several scientific applications such as radar imaging \cite{bar_radar, bajwa_radar, sunil}, ultrasound imaging \cite{eldar_sos,eldar_beamforming,mulleti_icip}, light detection and ranging (LIDAR) \cite{castorena_lidar}, time-domain optical-coherence tomography (TDOCT) \cite{blu_oct}, and other time-of-flight imaging systems. In these applications,  $h(t)$ is the transmitted pulse and $\{a_\ell \,h(t-t_\ell)\}_{\ell=1}^{L}$ constitute the reflections from $L$ point targets. The amplitudes $\{a_\ell\}_{\ell = 1}^L$ depend on the sizes of the targets and the delays $\{t_\ell\}_{\ell = 1}^L$ are proportional to the distances of the targets from the transmitter. Here $T_0$ denotes maximum time delay of the targets. The signal $f(t)$ is specified by $\{a_\ell, t_\ell\}_{\ell=1}^L$ and can be reconstructed from its sub-Nyquist measurements acquired using an appropriate sampling kernel \cite{vetterli,eldar_sos,fri_strang, mulleti_kernal}. The reconstruction is generally carried out in frequency domain as discussed next.

\subsection{Fourier-Domain Reconstruction}
Consider uniform samples of continuous-time Fourier transform of $f(t)$ given as
\begin{align}
	F(k \omega_0) = \int f(t) e^{-\mathrm{j} k\omega_0 t} \mathrm{d}t = H(k \omega_0) \sum_{\ell = 1}^L a_\ell \, e^{-\mathrm{j} k\omega_0 t_\ell},
	\label{eq:F}
\end{align}
for $k \in \mathcal{K}$. Here $H(\omega)$ is the Fourier transform of $h(t)$ and $\mathcal{K}$ is an integer set. In \eqref{eq:F}, $\omega_0>0$ denotes sampling interval in the frequency domain. Next, consider the following samples
\begin{align}
	S(k\omega_0) = \frac{F(k\omega_0)}{H(k\omega_0)} =  \sum_{\ell = 1}^L a_\ell \, e^{-\mathrm{j}k\omega_0 t_\ell},
	\label{eq:Skomega}
\end{align}
where we assume that $H(k \omega_0) \neq 0$ for $k \in \mathcal{K}$. In practice, the pulse $h(t)$ has small time support and hence, large bandwidth. Hence, for a finite set $\mathcal{K}$ it is possible to choose a set of frequencies $\{k \omega_0\}_{ k \in \mathcal{K}}$ such that $H(k \omega_0) \neq 0$. It can be shown that $2L$ consecutive samples of $S(k\omega_0)$ are sufficient to uniquely identify $\{a_\ell, t_\ell\}_{\ell=1}^L$ if $\omega_0 = \frac{2\pi}{T_0}$ \cite{eldar_2015sampling}.
In practice, high-resolution spectral estimation methods, such as the annihilating filter (AF) or Prony's method and its variants
\cite{prony, plonka, schmidt_music, barabell_rmusic, bdrao_rmusic,sarkar_mp,paulraj_esprit}, have been deployed for FRI parameter estimation.

Since $h(t)$ is known, $H(k\omega_0), k \in \mathcal{K}$ can be calculated in advance. Hence, to compute $S(k\omega_0), k \in \mathcal{K}$ and then to estimate the FRI parameters, $F(k\omega_0), k \in \mathcal{K}$ has to be determined. Next, we discuss a lowpass filter (LPF) based sampling framework to determine these Fourier samples.

\subsection{LPF-Based Sub-Nyquist Sampling}
\label{sec:lpf}
In this section, we discuss an LPF-based sampling mechanism for FRI signals. Let $g(t)$ denotes an ideal lowpass filter with cutoff frequency $\omega_c$ rad/sec. In the frequency-domain we have that $G(\omega) = 1$ for $\omega \in [-\omega_c, \omega_c]$ and zero for the rest of the frequencies. Let $y(t)$ denotes response of the LPF to the input $f(t)$, that is, $y(t) = (f*g)(t)$, where $*$ denotes linear convolution operation. Consider an ADC with dynamic range $[-\lambda, \lambda]$ and sampling rate $\omega_s = \frac{2\pi}{T_s}$ rad/sec. By assuming that  $\|y(t)\|_{\infty}\leq \lambda$, uniform samples at the output of ADC are given as $y(nT_s), n \in \mathbb{Z}$. Then uniform measurements of discrete-time Fourier transform (DTFT) of the samples are given as
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) = \sum_{n \in \mathbb{Z}}y(nT_s)\,e^{\mathrm{j} k\omega_0 n T_s}, \quad k \in \mathcal{K}.
	\label{eq:y_dtft}
\end{align}
By using the relationship between DTFT of samples $y(nT_s)$ and CTFT of $y(t)$ we have
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) &= \frac{1}{T_s}\sum_{m \in \mathbb{Z}} Y(k\omega_0 + m \omega_s), \nonumber \\
	&= \frac{1}{T_s}\sum_{m \in \mathbb{Z}} F(k\omega_0 + m \omega_s) \,G(k\omega_0 + m \omega_s),
		\label{eq:y_dtft2}
\end{align}
where we used the fact that $Y(\omega) = F(\omega)\,G(\omega)$. Next, consider the following conditions on the sampling rate and cutoff frequency of the filter
\begin{align}
	\omega_s \geq 2\omega_c, \quad \text{and} \quad \omega_c \geq K \omega_0,
	\label{eq:sampling_rate}
\end{align}
where $K \geq L$. Then by choosing $\mathcal{K} = \{-K, \cdots, K\}$, equation \eqref{eq:y_dtft2} can be written as
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) = F(k\omega_0), \quad k \in \mathcal{K},
	\label{eq:y_dtft3}
\end{align}
where we used the fact that $G(k\omega_0) = 1$ in this settings. The relationship \eqref{eq:y_dtft3} shows that the desired Fourier samples of $f(t)$ are determined from the samples of LPF output by assuming that the conditions in \eqref{eq:sampling_rate} are satisfied. Hence, FRI parameters can be determined from the samples of the lowpass filter. An LPF-based sampling for FRI signal was used in \cite{vetterli,uls_sparse} but with a periodic FRI signal model. With perodization, a finite number of time samples are sufficient to determine the desired Fourier measurements, whereas, countable infinite measurements are required in aperiodic setting consider here.

The bandwidth of the pulse $h(t)$ and hence that of the FRI signal $f(t)$ could be very large. But the sampling rate $\omega_s$ is independent of the pulse and could be much smaller than its bandwidth which shows the FRI signal could be reconstructed from sub-Nyquist samples.

The sub-Nyquist sampling framework discussed assumes that $\|y(t)\|_{\infty}\leq \lambda$, in other words, the framework assumes that the dynamic range of the ADC is greater than that of the signal to be sampled. However, this condition may not be always true. Specifically, the amplitude range of the filtered signal $y(t)$ could be larger than ADC's dynamic range. In such a scenario, a direct sampling would lead to clipping of samples which is undesirable. To avoid clipping, a modulo operator is employed prior to sampling as discussed next.

\begin{figure*}
	\centering
	\includegraphics[width=6.5 in]{Figs/FRI_US}
	\caption{A schematic of modulo-sampling and reconstruction of FRI signals.}
	\label{fig:fri_framework}
\end{figure*}

\subsection{Modulo-Folding}
To avoid clipping, a modulo folding operator $\mathcal{M}_\lambda(\cdot)$ is used after LPF and before the ADC. The operator folds $y(t)$ to stay within ADC's dynamic range $[-\lambda, \lambda]$. The output of the modulo operator in response to input $y(t)$ is given as
\begin{equation}
 y_\lambda(t) =	\mathcal{M}_{\lambda}(y(t)) = (y(t)+\lambda)\,\, \text{mod}\,\, 2\lambda -\lambda.
	\label{eq:mod_opp}
\end{equation}

In general, the modulo signal can be expressed as a linear combination of the true signal and a residual signal:
        \begin{align}
            y_\lambda(t) = y(t) - z(t),
            \label{eq:resiudual}
        \end{align}
where values of the residual signal $z(t)$ are integer multiples of $2\lambda$.
The folded signal is then sampled by the ADC to have measurements $y_\lambda(nT_s)$. Since modulo folding is a nonlinear operation, one can not directly apply DTFT on the samples to compute Fourier measurements of the FRI signal for its reconstruction. Hence, the true or unfolded samples $y(nT_s)$ are estimated from the folded ones $y_\lambda(nT_s)$ by applying an unfolding algorithm. There exist several unfolding methods for bandlimited signals \cite{uls_tsp, uls_romonov,eyar_moduloicassp}.
The sampling rate for unfolding varies for different algorithms and generally, is larger than the minimum sampling rate required for FRI signal recovery (cf. \eqref{eq:sampling_rate}).
Hence, the overall system operates on a higher sampling rate than that without a modulo case. However, if the overall sampling rate is much lower than the bandwidth of the FRI signal then the system operates at a sub-Nyquist rate. We show that this is indeed true when we apply our unfolding algorithm proposed in \cite{eyar_moduloicassp}.

An end-to-end modulo sampling framework for FRI signal sampling and reconstruction is shown in Fig.~\ref{fig:fri_framework}. The sampler or ADC together with the modulo block is termed as modulo-ADC.
Modulo-ADCs are able to sample signals beyond their dynamic range without clipping and hence they are termed as high-dynamic range ADCs. Alternatively, an ADC with a  much lower dynamic range can be used to sample signals with larger amplitudes. Sub-Nyquist sampling and low-dynamic range requirements significantly reduce the power consumption and cost of the ADC.

The modulo folding block is a key component of the high-dynamic range ADC and we discuss its hardware implementation in the next section.

\begin{figure}
	\centering
	\includegraphics[width= 3 in]{Figs/folding}
	\caption{Folding principle}
	\label{Fig:folding}
\end{figure}
\section{Modulo Hardware Prototype}
In this section, we discuss the prototype of our modulo hardware. The modulo block's working principle and design will be discussed first, followed by its hardware implementation.
\subsection{Working Principle of Modulo Block}
The principle of computing $y_\lambda(t)$ from $y(t)$ is shown by the block diagram in Fig.~\ref{Fig:folding}. The system comprises of an adder $S$, a direct-current voltage generator (DC-VG), and two comparators $C_1$ and $C_2$. To understand the working flow, let us first assume that for some time instant $t_1$, we have that $|y(t)|<\lambda$ for all $t<t_1$. Hence $y_\lambda(t) = y(t)$ and $z(t) = 0$ for all $t<t_1$. At $t=t_1$, let $|y(t)|$ crosses $\lambda$. If $y(t_1)>\lambda$, then the comparator $C_1$ triggers a positive value If $y(t_1)<\lambda$, $C_2$ triggers a negative value. The DC-VG is designed such that for each positive input value, it increases its output signal level by $-2\lambda$, whereas, for negative input value, it decreases its output voltage by $2\lambda$ (as in \ref{eq:resiudual}). Hence, in the current example, DC-VG generates signal $z(t) = \text{sgn}(y_\lambda(t_1)) 2\lambda u(t-t_1)$ where $u(t)$ is unit-step function. In this way, by adding or subtracting (using $S$) constant DC signals from $y(t)$ whenever it crosses the dynamic range $[-\lambda, \lambda]$, the amplitude levels of $y_\lambda(t)$ are kept within ADC's dynamic range.

\begin{figure}[!h]
	\centering
	\begin{tabular}{c}
		\subfigure[] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Fig3_2Folding_6Vpp_3Vbias_1KHz_Up_Clr.png}\label{fig:Up_Folding}} \\
		\subfigure[] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Fig3_2Folding_6Vpp_3Vbias_1KHz_Down_Clr.png}\label{fig:Down_Folding}} \\
	\end{tabular}
	\caption{DC-VG based folding operation. (a)-(b) denote the real-time capture of an oscilloscope displaying the input signal (yellow), its folded output (green), the DC-VG signal (blue), and the C1 and C2 comparator (red) respectively.}
	\label{Fig:DC-VG_folding_mechanism}
\end{figure}

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3 in]{Figs/dc_vg}
	\caption{DC-VG}
	\label{Fig:dcvg}
\end{figure}

\begin{figure*}[!t]
	\centering
	\includegraphics[width=0.86\textwidth ]{IEEE_TAES_v1/Figs/UDR_Board_Labeled3.PNG}
	\caption{Modulo hardware board.}
	\label{Fig:hw_board}
\end{figure*}

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3.2 in]{IEEE_TAES_v1/Figs/Fig6_1KHz_10Vpp_4Folding_New_Clr.png}
	\caption{
	Live screen shot of an oscilloscope capturing the 1kHz sinusoid input signal (yellow), its folded output (green) and the DC-VG signal (blue).}
	\label{Fig:Analysis_of_folding_ability}
\end{figure}

\begin{figure}[!h]
	\centering
	\begin{tabular}{c}
		\subfigure[] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Fig7_1Folding_6Vpp_1KHz_New_Clr.png}\label{fig:1k_1}} \\
		\subfigure[] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Fig7_1Folding_6Vpp_10KHz_New_Clr.png}\label{fig:10k_1}} \\
		\subfigure[] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Fig7_1Folding_6Vpp_20KHz_New_Clr.png}\label{fig:20k_1}}
	\end{tabular}
	\caption{Analysis of frequency response of the modulo hardware (a)-(c) denote the real-time capture of an oscilloscope capturing the 1kHz, 10kHz, 20kHz, respectively, sinusoidal input signal (yellow), its folded output (green), the DC-VG signal (blue).}
	\label{Fig:frequency_response}
\end{figure}

\begin{table}[h!]
		\caption{Up/down counter operation.}
	\centering
	\begin{tabular}{||c c c c c ||}
		\hline
		c & b & a & sgn & Counter values \\ [0.5ex]
		\hline\hline
		0 & 0 & 0 & 0~(1) & 0~(0) \\
		0 & 0 & 1 & 0~(1) & 1~(-1) \\
		0 & 1 & 0 & 0~(1) & 2~(-2) \\
		0 & 1 & 1 & 0~(1) & 3~(-3) \\
		1 & 0 & 0 & 0~(1) & 4~(-4) \\
		1 & 0 & 1 & 0~(1) & 5~(-5)\\
		1 & 1 & 0 & 0~(1) & 6~(-6)\\
		1 & 1 & 1 & 0~(1) & 7~(-7)\\
		\hline
	\end{tabular}
	\label{table:counter}
\end{table}

While the parts such as comparators $C_1$, $C_2$, and adder $S$ can be realized by using off-the-shelf components, DC-VG is a more involved system and required careful design. A detailed architecture of DC-VG is shown in Fig.~\ref{Fig:dcvg}. It consists of an up/down counter, a digital-to-analog converter (DAC), a multiplexer (MUX), and a multiplier $M$.  The function of the counter, along with the DAC, is to produce a piece-wise constant DC voltage whenever a trigger is present at its input. By employing the MUX and multiplier $M$, the voltage values are configured to be multiples of $2\lambda$.
To explain the working principle, we will first discuss the function of the counter, followed by the other components.

In this particular system, we use a three-bit synchronous up/down counter. The bits from lower significant bit to higher significant bit are denoted as a, b, and c, respectively. The counter has an additional sign bit shown as sgn. With these bits, the counter can count from -7 to 7. For each positive input trigger, the output counts up, and for each negative input trigger, it counts down. In Table~\ref{table:counter}, we list the values of bits and the counter (denoted as counter values). The three bits (a,b, and c) of the counter are used as input to the DAC which converts the bits to an analog DC voltages. Let the resolution or step size of the DAC is $\alpha$ then the output of DAC is $\alpha$ times the counter-value. To be more specific, consider the scenario where the output of counter and DAC are zero. DAC's output then increases (decreases) by $\alpha$ in response to a positive (negative) trigger. DAC's output signal, $s(t),$ is a piecewise constant signal whose values are multiples of $\alpha$. For folding to function, however, the voltage change must be in multiples of $2\lambda$. Further, we employ a MUX whose output is $2\lambda$ or $-2\lambda$ depending on whether its input (sgn bit) is 1 or 0. Then, $z(t)$ is generated by multiplying the output of DAC by the output of MUX.

Fig. \ref{fig:Up_Folding} (Fig. \ref{fig:Down_Folding}) demonstrates the DC-VG based folding operation time sequence beginning with the C1 (C2) comparator trigger operation, in red, followed by $z(t)$, in blue, which results in a 2$\lambda$ increase (decrease) of $y_\lambda(t)$, in green, and keeping it within the $\pm\lambda$ ADC range.

Next, we discuss the hardware board that realizes the folding operation discussed in this section.

\begin{table}[h!]
\centering
\caption{List of Hardware Components}
\label{table:hardware_components}
\begin{tabular}{||c c c||}
 \hline
 Component & Model Number & Make \\
 && \\ \hline
 Comparator & LM339 & Texas Instruments \\
 && \\
 UP/DOWN Counter & TEENSY4.1 & PJRC \\
 && \\
 DAC 3bits & LT1364 & Analog Devices \\
 && \\
 Analog MUX & ADG1608 & Analog Devices \\
 && \\
 Analog Multiplier & AD835 & Analog Devices \\
 && \\
 Adder & LT1364 & Analog Devices \\
  && \\ [1ex]
\hline
\end{tabular}
\end{table}
\subsection{Modulo Hardware Board}
Our modulo hardware board is presented in Fig.~\ref{Fig:hw_board}, along with the roles of the major building components. Table~\ref{table:hardware_components} contains a detailed listing of the hardware's components. The board is designed for $\lambda\leq1.25$ volts or less. The board can accommodate an input signal with a dynamic range between $[-8\lambda, 8\lambda]$, which means that an ADC equipped with our modulo hardware can sample signals four times bigger than its dynamic range without saturation and clipping.

We demonstrate the working of the modulo hardware by considering a sinusoidal signal $y(t) = A\, \sin(2\pi f_0 t)$ where $A$ is amplitude and $f_0$ is frequency (in Hz). In this experiment, we set $\lambda = 1.25$ and $-4\lambda <A <+4\lambda$. With this setting, we expect the signal to fold 4 times in a half sinusoidal cycle. Fig.~\ref{Fig:Analysis_of_folding_ability} depicts screenshot of an oscilloscope capturing input $y(t)$ (in yellow) and its folded output $y_\lambda(t)$ (in green) in addition the DC-VG output signal $z(t)$ (in blue), for $f_0 = 1$kHz. We observed that the signals are folded back to lie within the dynamic range of the ADC as expected without clipping. Next we discuss the the frequency response of the modulo ADC. As in any analog system, the response of the modulo folder too depends on the frequency or bandwidth of the input signal. Beyond a particular frequency, the folding may not be accurate as demonstrated in Fig.~\ref{Fig:frequency_response}. We observed that for signals of 1kHz and 10kHz the hardware is able to fold the signal accurately. However, for $f_0 = 20$kHz, folding instants are not symmetric for positive and negative folds. In one of our future works, we are planning to design a hardware that overcomes this limitation by using a faster hardware logical components to implement the folding counter instead of using the current up/down counter. The current implementation demonstrates a proof of concept of implementing the modulo concept in the analog domain at near real life environment and paves the way for a high frequency applications which supports high dynamic range operation.

In the next section, we discuss a couple of inaccuracies of the modulo hardware and our proposed solutions to overcome those.

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3.2 in]{Figs/mod_td}
	\caption{Effect of time delay of the feedback loop on the modulo operation.}
	\label{Fig:mod_td}
\end{figure}

\subsection{Artifacts During Folding}
Errors or other artifacts that arise during folding operation in hardware could be due to various reasons. One of the major issues that arises in a modulo ADC is the time delay in the feedback loop (See Fig.~\ref{Fig:folding}). To elaborate, consider a scenario where $y(t)<\lambda$ for $t<t_1$ and it crosses $\lambda$ at time $t_1$ as discussed earlier. To fold the output voltage to the dynamic range of the ADC, $z(t) = 2\lambda u(t-t_1)$ needs to be subtracted from $y(t)$. However, there is a finite delay between the trigger time $t_1$ to generating $z(t)$. If the time delay is $T_d$, then $z(t) = 2\lambda u(t-t_1-T_d)$ is subtracted, which causes distortion. To illustrate this effect, in Fig.~\ref{Fig:mod_td}, we considered a sinusoidal signal (in blue) and its folded versions with and without delay. We observe that in the absence of any time delay ($T_d=0$) the signal folds perfectly (shown in red) to stay within the dynamic range. However, for a non-zero value of $T_d$, foldings do not take place at the folding instants and the output of the modulo operator (shown in black) still remains outside the dynamic range $[-\lambda, \lambda]$, which results in a clipped modulo operator output. However, the proposed hardware solution addresses this issue and avoids the undesired clipping as shown in Figs.~\ref{Fig:Analysis_of_folding_ability} and \ref{Fig:frequency_response}.

Our solution uses the fact that with a finite time delay, the amount of overshoot of a smooth signal can be bounded. To elaborate, let us assume that the signal that undergoes modulo operation is Lipschitz continuous. Specifically, a signal $y(t)$ is Lipschitz continuous if there exists a positive real number $\mathrm{L}_y$ such that for any $T>0$ we have
\begin{align}
    |y(t) -y(t+T)|\leq \mathrm{L}_y\, T.
    \label{eq:lipschitz}
\end{align}
With the Lipschitz smoothness condition, we note that the amplitude of $y(t)$ can not change more than $\mathrm{L}_y\, T_d$ between any folding instant and time of its effect to take place. Hence, if we choose dynamic range of the ADC to be $[-(\lambda+\Delta \lambda), (\lambda+\Delta \lambda)]$ where $\Delta \lambda = \mathrm{L}_y\, T_d$ then the signal will not clip. We show this extended dynamic region in the illustrative example in Fig.~\ref{Fig:mod_td}. Alternatively, instead of increasing ADC's dynamic range, one can keep it to be $[-\lambda, \lambda]$ and reduce the threshold values for comparators. In this case, $C_1$ will trigger when the input crosses $\lambda-\Delta \lambda$ and $C_2$ will trigger when input goes beyond $-\lambda+\Delta \lambda$. In this way, the time delay issue is addressed by the modulo circuit without altering ADC's dynamic range.

In order to apply the solution, the signal must be Lipschitz continuous. In our design, the modulo operation input signal is always a lowpass or bandlimited signal satisfying the Lipschitz smoothness condition \cite{bl_bound}. For a bandlimited signal $y(t)$ its Lipschitz constant $\mathrm{L}_y$ is directly proportional to its bandwidth $\omega_c$ which is the same as the cutoff frequency of the LPF.
Hence, for a given value $\Delta \lambda$ and $T_d$ (both depend on the modulo circuit), $\mathrm{L}_y = \Delta \lambda/T_d$ is fixed and this restricts the maximum frequency of the input signal that can be faithfully folded. In the current design, we choose to implement the counter management using a TEENSY micro-controller, resulting in a $1 \mu$s time delay. This enables the hardware to accommodate a wide range of frequencies without requiring any modifications to the hardware components.

Another issue one can observe after DC-VG switching is that the voltage at the output of DC-VG either overshoots or undershoots (refer to Fig.~\ref{Fig:Analysis_of_folding_ability}) before the oscillations settle down to the expected value. This issue may be resolved by using a faster adder $S$ whose response time should be at least a magnitude higher than the sample rate. In one of our future works, we are planning to design a hardware that overcomes this limitation.

\section{Results}
In this section, we demonstrate the modulo hardware described in the previous section's signal reconstruction capability. From Fig.~\ref{fig:fri_framework}, we found that the signal reconstruction capability is a function of LPF $g(t)$, modulo circuit $\mathcal{M}_\lambda(\cdot)$, ADC or sampler, unfolding algorithm, and parameter estimation method. Any error in the estimation of FRI parameters is a result of flaws and limitations of the hardware realizations and limitations of the algorithms in the presence of measurement noise. For example, ideally $g(t)$ should have infinite impulse response, however, only a truncated version could be realizable in hardware. The truncation will result in errors while determining the Fourier samples of the FRI signal (See Section~III.\ref{sec:lpf}). Similarly, quantization plays a role when a finite resolution quantizer is used after the sampler. In addition, all the hardware components contribute to different types of noise. We model all these noises and inaccuracies as additive noise at the output of the sampler. Specifically, the noisy measurements are given as
 \begin{align}
            \tilde{y}_{\lambda}(n T_s) = {y}_{\lambda}(n T_s) + v(n T_s),
        \label{eq: noisy_samples}
        \end{align}
where $v(n T_s)$ is the noise term. Both unfolding and parameter estimation algorithms should be robust to different noise models. The robustness of parameter estimation methods in the presence of noise is well studied (See \cite{mulleti_kernal, stoica, eldar_sos}). In \cite{eyar_moduloicassp}, we presented comparisons of unfolding algorithms for bandlimited signals. We showed that our beyond-bandwidth residual recovery ($B^2R^2$) approach results in lower error during unfolding compared to the \emph{higher-order differences} (HOD) approach \cite{unlimited_sampling17, uls_tsp} and \emph{Chebyshev polynomial filter}-based (CPF) method \cite{uls_romonov}. Importantly, for a given sampling rate, $\lambda$, and signal to noise ratio (SNR), $B^2R^2$ method results in the lowest error for both bounded and unbounded noise models.

Before presenting hardware results, we compare the performances of the $B^2R^2$ method with HOD and CPF approaches for quantization noise and unbounded noise. We would like to point out that quantization noise was not considered in \cite{eyar_moduloicassp}. Although, the algorithms were compared for unbounded noise but the simulation settings were different than those in our hardware. Hence, for a better understanding, we compared our algorithm for unbounded noise and quantizaition  noise with the current hardware settings. In the next section, we present these simulation results and then present hardware results.

\begin{figure}[!t]
	\centering
	\includegraphics[width= 2.5 in]{IEEE_TAES_v1/Figs/quantization.png}
	\caption{Comparison of HOD, CPF and $B^2R^2$ algorithms after the quantization process in terms of MSE when recovering a bandlimited signal from modulo samples with $\lambda = 1.25$ and OF = 3,6. For a given number of bits, $B^2R^2$ has the lowest MSE.}
	\label{Fig:quantization}
\end{figure}

\begin{figure}[!t]
	\centering
	\includegraphics[width= 2.5 in]{IEEE_TAES_v1/Figs/Gaussian.png}
	\caption{Comparison of HOD, CPF and $B^2R^2$ algorithms (with unbounded noise) in terms of MSE when recovering a bandlimited signal from modulo samples with  $\lambda$ = 1.25 and OF = 3,6. For a given SNR and OF, $B^2R^2$ has lowest MSE.}
	\label{Fig:unbounded}
\end{figure}
\subsection{Simulated Results}
In this section, we compare our $B^2R^2$ algorithm with the \emph{higher-order differences} (HOD) approach \cite{unlimited_sampling17, uls_tsp} and \emph{Chebyshev polynomial filter}-based (CPF) method \cite{uls_romonov}. We consider the noise measurements as in \eqref{eq: noisy_samples} for a simulation data. In the simulations, $\lambda$ is set to be $1.25$ as in the hardware. We normalize the bandlimited signals to have maximum amplitude of $10$. The SNR is calculated as $\text{SNR} = 20 \log\left(\frac{||y_{\lambda}(n T_s)||}{||v(n T_s)||}\right)$. The reconstruction accuracy of different methods is compared in terms of normalized mean-squared error (MSE) as $ \frac{\sum |y(nT_s) - \hat{y}(n Ts)|^2}{\sum |y(nT_s)|^2}$, where $\hat{y}(n T_s)$ estimate of $y(n T_s)$. For different noise settings and over-sampling factors (OFs), we considered 100 independent noise realizations and calculated the average MSE for them. We first consider quantization noise and then present results for unbounded noise.

\begin{figure}[!t]
    \centering
    \includegraphics[width=0.3\textwidth]{IEEE_TAES_v1/Figs/Signal Generator.png}
    \caption{Bandlimited signal generator.}
    \label{fig:UDRSignalGen}
\end{figure}

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3.2 in]{IEEE_TAES_v1/Figs/Up_2mS_Clr.png}
	\caption{Bandlimited folded signal.}
	\label{Fig:Bandlimited_folded_signal}
\end{figure}

 First, we consider an uniform quantizer after the sampling. The unfolding algorithms are applied on the quantized samples. The MSE in the estimation of bandlimited signals for a different number of bits and OFs is shown in Fig. ~\ref{Fig:quantization}. We observe that for a given $\text{OF}$, $B^2R^2$ algorithm results in the lowest MSE for less than 5 bits. For more than 5 bits all the algorithms, except HOD with OF = 3, perform equally well. The results show that low-resolution quantizers can be used with $B^2R^2$ algorithm for unrolling which saves both power and memory requirements.

Next, for unbounded noise, we assume that the noise measurements $v(nT_s)$ are independent and identically distributed Gaussian random variables with zero mean. The variance is set to achieve a desired SNR. We compare the methods for different values of SNR and OFs with $\lambda = 1.25$. Fig.~\ref{Fig:unbounded} shows MSE of the different algorithms for OF $= 3$ and $6$. We note that our algorithm results in lowest error for a given OF and SNR.

Given the advantages of $B^2R^2$ algorithm over the other approaches, we present the hardware results in the next section by using this method.

\begin{figure*}[!t]
	\centering
	\begin{tabular}{cc}
		\subfigure[]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/BL1_scope_11_Clr.png}\label{fig:BL1_scope}} &
		\subfigure[]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/BL2_scope_13_Clr.png}\label{fig:BL2_scope}}
	\end{tabular}
	\caption{Live screen shot of an oscilloscope capturing the input bandlimited signals (yellow) and its folded output signals (green).}
	\label{fig:BL_scopeex1}

\end{figure*}
\begin{figure*}[!t]
	\centering
	\begin{tabular}{cc}
		\subfigure[]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/BL1_rec.png}\label{fig:BL1}} &
		\subfigure[]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/BL2_rec.png}\label{fig:BL2}}
	\end{tabular}
	\caption{Hardware results for bandlimited signals. The $B^2R^2$ algorithm is used to unfold $y_\lambda(t)$ (measured at the output of hardware) and the unfolded signal $\hat{y}(t)$ is plotted with bandlimited signal $y(t)$.}
	\label{fig:BL_ex1}
\end{figure*}

\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[FRI1 live screen shot of an oscilloscope capturing the 1kHz sinusoid input signal (yellow), its folded output (green) and the DC-VG signal (blue).] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/FRI1_1_Clr.png}\label{fig:FRI1_1k}} \\
		\subfigure[]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Ex1_lpf.pdf}\label{fig:FRI_LPF1}}\\
		\subfigure[FRI1 Reconstruction.] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Ex1_fri.pdf}\label{fig:FRI1_REC}} \\

	\end{tabular}
	\caption{Reconstruction of FRI3 signal via the modulo hardware .}
	\label{Fig:FRI1}
\end{figure}

\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[FRI2 live screen shot of an oscilloscope capturing the 1kHz sinusoid input signal (yellow), its folded output (green) and the DC-VG signal (blue).] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/FRI2_1_Clr.png}\label{fig:FRI2_1k}} \\
		\subfigure[]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Ex2_lpf.pdf}\label{fig:FRI_LPF2}}\\
		\subfigure[FRI2 Reconstruction.] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Ex2_fri.pdf}\label{fig:FRI2_REC}} \\
	\end{tabular}
	\caption{Reconstruction of FRI2 signal via the modulo hardware .}
	\label{Fig:FRI2}
\end{figure}

\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[FRI3 live screen shot of an oscilloscope capturing the 1kHz sinusoid input signal (yellow), its folded output (green) and the DC-VG signal (blue).] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/FRI3_1_Clr.png}\label{fig:FRI3_1k}} \\
		\subfigure[]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Ex3_lpf.pdf}\label{fig:FRI_LPF3}}\\
		\subfigure[FRI3 Reconstruction.] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Ex3_fri.pdf}\label{fig:FRI3_REC}} \\

	\end{tabular}
	\caption{Reconstruction of FRI5 signal via the modulo hardware .}
	\label{Fig:FRI3}
\end{figure}

\subsection{Hardware Results}
In this section, we present results from the hardware.
Since bandlimited signals are input to the hardware , we first present results for them and then show results for FRI signals. If the hardware and unfolding algorithm is able to recover the bandlimited signals with high accuracy than it will leads to better reconstruction of the FRI signals. In all these experiments we set $\lambda = 1.25$ V and the cutoff frequency of the lowpass filter is 1kHz. We observe that for frequencies less than or equal to 10kHz, our hardware is able to reliably fold the signal. The Nyquist rate of the signal is 2kHz. But for unfolding we need to oversample the signal. In all these experiments, we used $B^2R^2$ algorithm with OF = 5 which results in sampling rate of 10kHz. Further, $y(t)$ (yellow) and $y_\lambda(t)$ (green) are measured from the hardware through an oscilloscope for processing by the algorithms as described in Fig. \ref{Fig:Bandlimited_folded_signal}.

We first consider the bandlimited signals. For generating bandlimited or lowpass signals we used a Arduino micro-controller (See Fig.~\ref{fig:UDRSignalGen}) which convert the digital signal to an analog signal via a DAC. The digital signals were generated using MATLAB software. Two examples of 1khz bandlimited signal are presented in Fig. \ref{fig:BL1_scope} and Fig. \ref{fig:BL2_scope}. In Fig.~\ref{fig:BL_ex1}, we show folding and reconstruction, using the $B^2R^2$ algorithm, of the two bandlimited signals that displayed in Fig. \ref{fig:BL_scopeex1}. These signals have maximum amplitude of 5V. We observe the signals are restricted to $[-\lambda, \lambda]$ by the modulo hardware and the algorithm was able to recover the true signal from the folded samples. The reconstructed signal has slightly larger amplitude compared to the true signal which is result of scaling within the hardware.

Next, we consider reconstruction of FRI signals from modulo samples. To generate the FRI signals, we consider $h(t)$ to be a short pulse of bandwidth 30kHz (Nyquist rate = 60kHz). We consider three examples with $L=2, 3,$ and 5. The amplitudes and time delays are generated randomly. The maximum time delay is $T_0 = 0.1$ sec. Once generated, the FRI signal is lowpass filtered with a cutoff frequency of 1kHz. Up to filtering operation, MATLAB is used and then Arduino micro-controller is used to generate the analog version of the filtered FRI signals. The signal is then folded using the hardware and the folded signals are sampled. The sampling rate is 10kHz which is five times higher than the sampling rate of the lowpass signal. Still the rate is six times lower than the Nyquist rate and hence the system operates at sub-Nyquist rate. The setup satisfies the conditions in \eqref{eq:sampling_rate} for $L=2, 3,$ and 5.

We first apply $B^2R^2$ algorithm to unfold the signal and then used ESPRIT \cite{paulraj_esprit} to estimate the time delays and amplitudes of the FRI signals.
In Fig.~\ref{Fig:FRI1}, Fig.~\ref{Fig:FRI2} and  Fig.~\ref{Fig:FRI3} we show sampling and reconstruction of FRI signals with $L=2,3,5$ respectively.
The FRI signals followed by a lowpass filter are presented in Fig.~\ref{fig:FRI1_1k}, Fig.~\ref{fig:FRI2_1k} and  Fig.~\ref{fig:FRI3_1k}.
The reconstruction of the lowpass signals displayed in Fig.~\ref{fig:FRI_LPF1}, Fig.~\ref{fig:FRI_LPF2} and  Fig.~\ref{fig:FRI_LPF3}, where $y(t)$ described the LPF output , $y_\lambda(t)$ is the folded signal (output of the modulo hardware), and the unfolded signals are given by $\hat{y}(t)$. Fig.~\ref{fig:FRI1_REC}, Fig.~\ref{fig:FRI2_REC} and Fig.~\ref{fig:FRI3_REC} show location and amplitude of the true signal $f(t)$ and estimated FRI signal $\hat{f}(t)$.
The maximum error in the estimation of time delay is $-15$ dB which shows that the system can be used in applications like radar and ultrasound imaging.

\section{Conclusions}
We considered the problem of recovering FRI signals from low-pass filtered, modulo samples. We presented a hardware prototype for the modulo folding system and show that for different bandlimited and FRI signals, the hardware is able to faithfully fold the signal. We also  address the time delay issue of the modulo system and presented a hardware solution for the same. The overall system operates at six times below the Nyquist rate which enables one to use low rate, low-dynamic range, power efficient ADCs.

\bibliographystyle{IEEEtaes}

\section{INTRODUCTION}
Sampling plays a key role in efficiently processing real-world analog signals on digital signal processors. Analog to digital converters (ADCs) are used to implement sampling in the hardware. A key parameter of the ADC is its sampling rate. ADCs with high sampling rates are power consuming and expensive which make them unsuitable for portable devices such as hand-held ultrasound device. Hence, it is desirable to reduce the sampling rate. Following the Shannon-Nyquist sampling theorem \cite{shannon, nyquist}, it is well known that the sampling rate of bandlimited signals are dictated by their highest frequency. Hence, in wideband signal applications one can not sample below the Nquist rate by considering the bandlimited signal model.

Finite-rate-of-innovation (FRI) model is another signal model which is ubiquitous in several time of flight applications \cite{bajwa_radar, bar_radar,filho201seismic,rip,carter_sonar,eldar_sos,eldar_beamforming, sunil}. In these applications, the signal of interest consists of a linear combination of delayed copies of a known pulse. Thus, the desired information lies in the amplitudes and time delays of the pulse which amounts to few degrees of freedom and aids sub-Nyquist sampling \cite{eldar_2015sampling}. Most prior works in the context of FRI sampling are focused on reducing the sampling rate of the ADC by using the signal structure and consequently reducing the power consumption and cost of the ADCs \cite{vetterli, eldar_sos, fri_strang, blu_moms, mulleti_kernal}.

Dynamic range of an ADC too plays a crucial role in sampling an analog signal. In general, ADC's dynamic range should be larger than that of the signal's, otherwise the signal is clipped. There exist a few approaches to recover the true samples from clipped ones for bandlimited signals \cite{marks_clipping2, marks_clipping1}. These approaches relies on correlation among the samples when they are measured at very high-rate compared to the Nyquist rate. Requirement of high-sampling rate is a drawback of these approaches. In addition, theoretical guarantees are missing and it is not clear on how many clipped samples can be recovered.

There are three popular analog preprocssing approaches, namely automatic gain control (AGC) \cite{perez2011automatic,mercy1981review}, companding \cite{landau_compander,landau_distorted_bl}, and modulo folding \cite{uls_tsp,uls_romonov,uls_sparse,bhandari2021unlimited,eyar_moduloicassp}, that can be used prior to sampling to avoid clipping. In AGC, a chain of amplifiers is used with a feedback loop such that a suitable output level is maintained at the output \cite{perez2011automatic,mercy1981review}. An AGC system uses a closed loop feedback mechanism to maintain a constant signal level at its output for a varying input signal levels \cite{perez2011automatic,mercy1981review}. The closed loop feedback consists of a chain of amplifiers and maintaining its stability is a challenging task. Companding is an alternative approach to limit the dynamic range of the input signals. In this approach, smaller amplitudes of the signals have larger gain compared to the larger ones. Beurling presented theoretical guarantees and proved that knowledge of the companded signal over the input signal's bandwidth is sufficient to uniquely identify the signal provided \cite{landau_compander}. Landau et al. \cite{landau_distorted_bl} proposed an iterative algorithm to recover a bandlimited signal from its companded signal. The algorithm converges if the compander is differentiable over the dynamic range of the input signal which limits its practical application.

The third approach is to use modulo folding prior to sampling which fold the input signal to lie within the dynamic range of the ADC \cite{uls_tsp,uls_romonov,uls_sparse,bhandari2021unlimited,eyar_moduloicassp}. The folded signal is then sampled by using a conventional ADC. Theoretical guarantees for recovering bandlimited signals from folded samples are presented in \cite{uls_tsp,uls_identifiability}. The results states that the bandlimited signals can be uniquely recovered from folded samples provided that they are sampled above the Nyquist rate. Several algorithms for \emph{unfolding} or recovering the true samples of bandlimited signals from modulo or folded samples are presented in \cite{uls_tsp,uls_romonov, eyar_moduloicassp}. These unfolding algorithms can be compared in terms of sampling rate, amount of unfolding they can accommodate, and noise robustness. It is shown that the method proposed in \cite{eyar_moduloicassp} has lowest reconstruction error for a given sampling rate, noise level, and signal's amplitude level compared to the algorithms presented in \cite{uls_tsp,uls_romonov}. The algorithm proposed in \cite{uls_tsp} requires almost 17-times higher sapling rate than the Nyquist rate but it is independent of the dynamic range of the ADC. Whereas, the approaches in \cite{uls_romonov, eyar_moduloicassp} requires the knowledge of ADC's dynamic range. Modulo sampling is also extended to different problems and signal models such as periodic bandlimited signals \cite{bhandari2021unlimited}, wavelets \cite{uls_wavelet}, mixture of sinusoids \cite{uls_sinmix}, finite-rate-of-innovation signals \cite{uls_fri}, multi-dimensional signals \cite{uls_md}, sparse vector recovery \cite{uls_gamp, uls_sparsevec}, direction of arrival estimation problem \cite{uls_doa}, computed tomography \cite{uls_radon}, and graph signals \cite{uls_graph}.

While theoretical guarantees and algorithms of any new sampling approach are always well researched but the question on whether they work in practice is always difficult to answer. For modulo sampling, there exists a few hardware prototypes. For example, high-dynamic-range ADCs, also known as \emph{self-reset} ADCs, are discussed in the context of imaging \cite{sradc_park, sradc_sasagwa, sradc_yuan, krishna2019unlimited}. These hardware architectures measures additional information such as the amount of folding for each sample, or, the sign of the folding together with the folded samples. The additional information might enable simpler recovery but at the expense of complex circuitry. Importantly, additional bits are required during the quantization process to store or transmit the side information.

Krishna et al. presented a hardware prototype which encode the side-information by using two bits \cite{krishna2019unlimited}. The architecture is designed to record sign of the slope of the signal at each sampling instant when the sample lies outside ADC's dynamic range. In a conventional ADC, a sample and hold (S/H) circuit is used to hold the sampled value for a prescribed period of time during which quantization is performed on the sample. To realize the modulo sampling, a folding circuit is used after S/H \cite{krishna2019unlimited}. Hence, the S/H circuit has to hold the sampled value for folding and quantization, which results in a larger folding time compared to a conventional ADC. A large holding time results in slower ADC and hence it may not be useful for wideband application.

The proposed modulo-ADC is able to sample signals beyond its dynamic range while keeping the power dissipation and area requirements lower compared to a conventional ADC \cite{krishna2019unlimited}. A major drawback of this modulo-ADC's architecture is that the modulo operation is performed between the sample and hold (S/H), and quantization blocks of the ADC. Specifically, modulo operation is performed on the hold values of S/H circuit and then the folded sample is quantized. Hence, compared to a conventional ADC, the hold time is relatively high which makes the architecture slower.

\newpage
In introduction, we discuss the following:

1st-paragraph: Standard sampling and sub-Nyquist; importance of low sampling rates; FRI signal model and application to radar\\

2nd-paragraph: Introduce the dynamic range issue and discuss the existing approaches to address it: AGC, commanding, and modulo. Why modulo is important.\\

3rd paragraph: Discuss about modulo method, recovery algorithms and their issues with high-sampling rates and instability in noise. Discuss about our proposed algorithm (Eyar's ICASSP-22 paper)\\

4th paragraph: Can we implement these in HW? Discuss about hardware prototypes and applications. Shortcomings: No practical applications, low operating frequencies, more?\\

5th paragraph: In this paper, we present a HW prototype combined with recently proposed algorithm to address these issues.\\

 6th Paragraph: The paper is organized as follows; Notations \\

\section{Signal Model and System Description}
In this section, we first introduce FRI signal model and then discuss its sampling and reconstruction framework with modulo ADC.
\subsection{FRI Signal Model}
Consider an FRI signal consisting of stream of $L$ pulses:
\begin{align}
	f(t) = \sum_{\ell=1}^L a_\ell h(t-t_\ell),
	\label{eq:fri1}
\end{align}
where the pulse $h(t)$ a real-valued known pulse. We assume that $a_\ell$s are real-valued and $t_\ell \in (0, T_d] \subset \mathbb{R}$ for a known $T_d$.

The FRI signal model in \eqref{eq:fri1} is encountered in several scientific applications such as radar imaging \cite{bar_radar, bajwa_radar, sunil}, ultrasound imaging \cite{eldar_sos,eldar_beamforming,mulleti_icip}, light detection and ranging (LIDAR) \cite{castorena_lidar}, time-domain optical-coherence tomography (TDOCT) \cite{blu_oct}, and other time-of-flight imaging systems. In these applications,  $h(t)$ is the transmitted pulse and $\{a_\ell \,h(t-t_\ell)\}_{\ell=1}^{L}$ constitute the reflections from $L$ point targets. The amplitudes $a_\ell$s depend on the sizes of the targets and the delays $t_\ell$s are proportional to the distances of the targets from the transmitter. Here $T_d$ denotes maximum time delay of the targets. The signal $f(t)$ is specified by $\{a_\ell, t_\ell\}_{\ell=1}^L$ and can be reconstructed from its sub-Nyquist measurements acquired using an appropriate sampling kernel \cite{vetterli,eldar_sos,fri_strang, mulleti_kernal}. The reconstruction is generally carried out in frequency domain as discussed next.

\subsection{Fourier-Domain Reconstruction}
Consider uniform samples of continuous-time Fourier transform of $f(t)$ given as
\begin{align}
	F(k \omega_0) = \int f(t) e^{-\mathrm{j} k\omega_0 t} \mathrm{d}t = H(k \omega_0) \sum_{\ell = 1}^L a_\ell \, e^{-\mathrm{j} k\omega_0 t_\ell},
	\label{eq:F}
\end{align}
for $k \in \mathcal{K}$ where $H(\omega)$ is the Fourier transform of $h(t)$ and $\mathcal{K}$ is a set integers. In \eqref{eq:F}, $\omega_0>0$ denotes sampling interval in the frequency domain. Next, consider the following samples
\begin{align}
	S(k\omega_0) = \frac{F(k\omega_0)}{H(k\omega_0)} =  \sum_{\ell = 1}^L a_\ell \, e^{-\mathrm{j}k\omega_0 t_\ell},
	\label{eq:Skomega}
\end{align}
where we assume that $H(k \omega_0) \neq 0$ for $k \in \mathcal{K}$. In practice, the pulse $h(t)$ has small time support and hence, large bandwidth. Hence, for a finite set $\mathcal{K}$ it is possible to choose a set of frequencies $\{k \omega_0\}_{ k \in \mathcal{K}}$ such that $H(k \omega_0) \neq 0$ for $k \in \mathcal{K}$. It can be shown that $2L$ consecutive samples of $S(k\omega_0)$ are sufficient to uniquely identify $\{a_\ell, t_\ell\}_{\ell=1}^L$ if $\omega_0 = \frac{2\pi}{T_d}$ \cite{eldar_2015sampling}. In practice, high-resolution spectral estimation methods, such as the annihilating filter (AF) or Prony's method and its variants \cite{prony, plonka}, multiple signal classification \cite{schmidt_music, barabell_rmusic, bdrao_rmusic}, matrix-pencil method \cite{sarkar_mp}, estimation of signal parameter via rotational invariance technique (ESPRIT) \cite{paulraj_esprit}, etc. have been deployed for FRI parameter estimation.

Since $h(t)$ is known, $H(k\omega_0), k \in \mathcal{K}$ can be calculated in advance. Hence, to compute $S(k\omega_0), k \in \mathcal{K}$ and then estimate FRI parameters, $F(k\omega_0), k \in \mathcal{K}$ has to be determined. Next, we discuss a lowpass filter (LPF) based sampling framework to determine these Fourier samples.

\subsection{LPF-Based Sub-Nyquist Sampling}
In this section, we discuss a LPF-based sampling mechanism for FRI signals. Let $g(t)$ denotes an ideal lowpass filter with cutoff frequency $\omega_c$ rad/sec. In the frequency-domain we have that $G(\omega) = 1$ for $\omega \in [-\omega_c, \omega_c]$ and zero for the rest of the frequencies. Let $y(t)$ denotes response of the LPF to the input $f(t)$, that is, $y(t) = (f*g)(t)$, where $*$ denotes linear convolution operation. Consider an ADC with dynamic range $[-\lambda, \lambda]$ and sampling rate $\omega_s = \frac{2\pi}{T_s}$ rad/sec. By assuming that  $\|y(t)\|_{\infty}\leq \lambda$, uniform samples at the output of ADC are given as $y(nT_s), n \in \mathbb{Z}$. Then uniform measurements of discrete-time Fourier transform (DTFT) of the samples are given as
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) = \sum_{n \in \mathbb{Z}}y(nT_s)\,e^{\mathrm{j} k\omega_0 n T_s}, \quad k \in \mathcal{K}.
	\label{eq:y_dtft}
\end{align}
By using relationship between DTFT of samples $y(nT_s)$ and CTFT of $y(t)$ we have
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) &= \frac{1}{T_s}\sum_{m \in \mathbb{Z}} Y(k\omega_0 + m \omega_s), \nonumber \\
	&= \frac{1}{T_s}\sum_{m \in \mathbb{Z}} F(k\omega_0 + m \omega_s) \,G(k\omega_0 + m \omega_s),
		\label{eq:y_dtft2}
\end{align}
where we used the fact that $Y(\omega) = F(\omega)\,G(\omega)$. Next, consider the following conditions on the sampling rate and cutoff frequency of the filter
\begin{align}
	\omega_s \geq 2\omega_c, \quad \text{and} \quad \omega_c \geq K \omega_0,
	\label{eq:sampling_rate}
\end{align}
where $K \geq L$. Then by choosing $\mathcal{K} = \{-K, \cdots, K\}$, \eqref{eq:y_dtft2} can be written as
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) = F(k\omega_0), \quad k \in \mathcal{K},
	\label{eq:y_dtft3}
\end{align}
where we used the fact that $G(k\omega_0) = 1$ in these settings. The relationship \eqref{eq:y_dtft3} shows that the desired Fourier samples of $f(t)$ are determined from the samples of LPF by assuming that the conditions in \eqref{eq:y_dtft2} are satisfied. Hence, FRI parameters can be determined from the samples of the lowpass filter.

The bandwidth of the pulse $h(t)$ and hence that of the FRI signal $f(t)$ could be very large. But the sampling rate $\omega_s$ is independent of the pulse and could be much smaller than its bandwidth which shows the FRI signal could be reconstructed from sub-Nyquist samples.

The sub-Nyquist sampling framework discussed assumes that $\|y(t)\|_{\infty}\leq \lambda$, in other words, the framework assumes that the dynamic range of the ADC is greater than that of the signal to be sampled. However, this condition may not be always true. Specifically, the amplitude range of the filtered signal $y(t)$ could be larger than ADC's dynamic range. In such scenario, a direct sampling would lead to clipping of samples which is undesirable. To avoid clipping, a modulo operator is employed prior to sampling as discussed next.

\begin{figure*}
	\centering
	\includegraphics[width=6.5 in]{Figs/FRI_US}
	\caption{A schematic of modulo-sampling and reconstruction of FRI signals.}
	\label{fig:fri_framework}
\end{figure*}

\subsection{Modulo-Folding}
To avoid clipping, a modulo folding operator $\mathcal{M}_\lambda(\cdot)$ is used after LPF and before the ADC. The operator folds $y(t)$ to stay within ADC's dynamic range $[-\lambda, \lambda]$. The output of the modulo operator in response to input $y(t)$ is given as\begin{equation}
 y_\lambda(t) =	\mathcal{M}_{\lambda}(y(t)) = (y(t)+\lambda)\,\, \text{mod}\,\, 2\lambda -\lambda.
	\label{eq:mod_opp}
\end{equation}
The folded signal is then sampled by the ADC to have measurements $y_\lambda(nT_s)$. Since modulo folding is a nonlinear operation, one can not directly apply DTFT on the samples to compute Fourier measurements of the FRI signal for its reconstruction. Hence, the true or unfolded samples $y(nT_s)$ are estimated from the folded ones $y_\lambda(nT_s)$ by applying an unfolding algorithm. There exist several unfolding methods for badnlimited signals such as $y(t)$ \cite{uls_tsp, uls_romonov,eyar_moduloicassp}. The sampling rates for unfolding varies for different algorithms and generally, is larger than the minimum sampling rate required for FRI signal recovery (cf. \eqref{eq:sampling_rate}). Hence, the overall system operates on a higher sampling rate than that in without modulo case. However, if the overall sampling rate is much lower than the bandwidth of the FRI signal then the system operates at sub-Nyquist rate. We show that this is indeed true when we apply our unfolding algorithm proposed in \cite{eyar_moduloicassp}.

An end-to-end modulo sampling framework for FRI signal sampling and reconstruction is shown in Fig.~\ref{fig:fri_framework}. The sampler or ADC together with the modulo block is termed as modulo-ADC. Modulo-ADC's are able to sample signals beyond their dynamic range without clipping and hence they are termed as high-dynamic range ADCs. Alternatively, an ADC with much lower dynamic range can be used to sample signals with larger amplitudes. Sub-Nyquist sampling and low-dynamic range requirements significantly reduces the power consumption and cost of the ADC.

The modulo folding block is key component of the high-dynamic range ADC and we discuss it hardware implementation in the next section.

\begin{figure}
	\centering
	\includegraphics[width= 3 in]{Figs/folding}
	\caption{Folding principle}
	\label{Fig:folding}
\end{figure}
\section{Modulo Hardware Prototype}
In this section, we discuss our modulo hardware prototype. First, we explain the working principle of the modulo block and explain how its design and then discuss the hardware realization.
\subsection{Working Principle of Modulo Block}
Principle of computing $y_\lambda(t)$ from $y(t)$ is shown by block-diagram in Fig.~\ref{Fig:folding}. The system comprises of an adder $S$, a direct-current voltage generator (DC-VG), and two comparators $C_1$ and $C_2$. To understand the working let us first assume that for some time instant $t_1$, we have that $|y(t)|<\lambda$ for $t<t_1$. Hence $y_\lambda(t) = y(t)$ and $z(t) = 0$ for $t<t_1$. At $t=t_1$, let $|f(t)|$ crosses $\lambda$. If $f(t_1)>0$, then the comparator $C_1$ triggers a positive spike or else, $C_2$ triggers a negative spike. The DC-VG is designed such that for every positive spike input it reduces its output signal level by $-2\lambda$, whereas, for negative spike it increases its output voltage by $2\lambda$. Hence, in the current example, DC-VG generates signal $z(t) = \text{sgn}(y_\lambda(t_1)) 2\lambda u(t-t_1)$ where $u(t)$ is unit-step function.
In this way by adding or subtracting (by using $S$) constant DC signals from $f(t)$ whenever it crosses dynamic range $[-\lambda, \lambda]$, the amplitude levels of $f_\lambda(t)$ are kept within ADC's dynamic range.

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3 in]{Figs/dc_vg}
	\caption{DC-VG}
	\label{Fig:dcvg}
\end{figure}

\begin{figure*}[!t]
	\centering
	\includegraphics[width=5 in]{Figs/UDR_Board_Labeled.PNG}
	\caption{DC-VG Modulo Hardware Board}
	\label{Fig:hw_board}
\end{figure*}
\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[]{\includegraphics[width=3in]{Figs/UDRPhase2pictures500Hz}\label{fig:500_2}} \\
		\subfigure[]{\includegraphics[width=3in]{Figs/UDRPhase2pictures2KHz}\label{fig:2k_2}}
	\end{tabular}
	\caption{Two Fold}
	\label{Fig:two_fold}
\end{figure}

\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[]{\includegraphics[width=3in]{Figs/500Hz}\label{fig:500_1}} \\
		\subfigure[]{\includegraphics[width=3in]{Figs/1KHz}\label{fig:1k_1}} \\
		\subfigure[]{\includegraphics[width=3in]{Figs/5KHz}\label{fig:5k_1}}
	\end{tabular}
	\caption{Frequency response}
	\label{Fig:frequency_response}
\end{figure}
\begin{table}[h!]
		\caption{Folding Operation.}
	\centering
	\begin{tabular}{||c c c c c ||}
		\hline
		c & b & a & sgn & Counter values \\ [0.5ex]
		\hline\hline
		0 & 0 & 0 & 0~(1) & 0~(0) \\
		0 & 0 & 1 & 0~(1) & 1~(1) \\
		0 & 1 & 0 & 0~(1) & 2~(2) \\
		0 & 1 & 1 & 0~(1) & 3~(3) \\
		1 & 0 & 0 & 0~(0) & 4~(4) \\
		0 & 0 & 1 & 0~(0) & 1~(-1) \\
		0 & 1 & 0 & 0~(0) & 2~(-2) \\
		0 & 1 & 1 & 0~(0) & 3~(-3) \\
		1 & 0 & 0 & 0~(0) & 4~(-4) \\
		\hline
	\end{tabular}
	\label{table:counter}
\end{table}

While the parts such as comparators $C_1$, $C_2$, and adder $S$ can be realized by using off-the-shelf components, DC-VG is more involved system and required careful design. A detailed architecture of DC-VG is shown in Fig.~\ref{Fig:dcvg}. It consists of an up/down counter, a digital-to-analog converter (DAC), a multiplexer (MUX), and a multiplier $M$.  The role of the counter (together with DAC) is to generate a variable, but controlled, DC voltage whenever there is a trigger at its input. The voltage values are set to be multiple of $2\lambda$ by using the MUX and multiplier $M$. To explain the working in details, we first discuss the counter and then the rest of the components.

In this particular system, we use a three-bit synchronous up/down converter. The bits from lower significant bit to higher significant bit are denoted as a, b, and c. The counter has an additional sign bit shown as sgn. With these bits, the counter can count from -7 to 7. For every positive trigger at the input, the output counts up and with negative trigger it counts down. In Table~\ref{table:counter}, we display the values of bits and the counter (denoted as counter values). The three bits (a,b,and c) of the counter is used as input to the DAC which convert the bits to analog DC voltages. Let the resolution or step size of the DAC is $\alpha$ then the output of DAC is counter-value times $\alpha$. To explain the working in more details, consider the scenario where the output of counter and DAC are zero. Then for a positive (negative) trigger, the output of DAC increases (decreases) by $\alpha$. Specifically, output of DAC, $s(t)$, is a piecewise constant signal with its values which are multiple of $\alpha$. However, for folding to work, the change in the voltage should be in multiple of $2\lambda$. To ascertain that we use a MUX which outputs either $2\lambda/\alpha$ or $-2\lambda/\alpha$ depending on whether its input is 1 or 0. Then by multiplying output of DAC with output of MUX we generate $z(t)$. Next, we discuss the hardware board the realize the folding operation discussed in this section.

\begin{table}[h!]
\centering
\caption{List of Hardware Components}
\label{table:hardware_components}
\begin{tabular}{||c c c||}
 \hline
 Component & Model Number & Make \\
 && \\ \hline
 Comparator & LM339 & Texas Instruments \\
 && \\
 UP/DOWN Counter & TEENSY4.1 & PJRC \\
 && \\
 DAC 3bits & LT1364 & Analog Devices \\
 && \\
 Analog MUX & ADG1608 & Analog Devices \\
 && \\
 Analog Multiplier & AD835 & Analog Devices \\
 && \\
 Subtractor & LT1364 & Analog Devices \\
  && \\ [1ex]
\hline
\end{tabular}
\end{table}
\subsection{Modulo Hardware Board}
Our modulo hardware board is shown in Fig.~\ref{Fig:hw_board} with different building components are labeled. The board is designed for $\lambda \leq 1.25$ volts. The board can accommodate an input signal with dynamic range between $[-4\lambda, 4\lambda]$ which implies that an ADC with our modulo hardware can sample four-times larger signals compared to its dynamic range without saturation and clipping. We demonstrate working of the modulo hardware by considering sinusoidal signal $y(t) = A\, \sin(2\pi f_0 t)$ where $A$ is amplitude and $f_0$ is frequency (in Hz). In this experiment, we set $\lambda = 1.25$ and $3\lambda <A <4\lambda$. With these settings, we expect the signal to fold twice in a quarter cycle of sinusoid. Figs.~\ref{Fig:two_fold}(a) and \ref{Fig:two_fold}(b) screenshots of an oscilloscope capturing input $y(t)$ (in yellow) and its folded output $y_\lambda(t)$ (in green) for $f_0 = 500$ Hz and $f_0 = 2$ kHz, respectively. We observed that the signals are folded back to lie within the dynamic range of the ADC as expected without clipping. The reason we choose two different frequencies is to study the frequency response of the modulo folder. As in any analog system, the response of modulo folder too depends on the frequency or bandwidth of the input signal. Beyond a particular frequency the foldings may not be accurate as observed in Fig.~\ref{Fig:frequency_response}. We observed that for signals of 500 Hz and 1kHz the hardware is able to fold the signal accurately. However, for $f_0 = 5$ kHz, folding instants are not symmetric for positive and negative folds. In the next section, we discuss a couple of inaccuracies of the modulo hardware and our proposed solution to overcome those.

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3.2 in]{Figs/mod_td}
	\caption{Time Delay}
	\label{Fig:mod_td}
\end{figure}

\subsection{Artifacts During Folding}
Errors or other artifacts arise during folding operation in a hardware could be due to various reasons. For examples, in Figs.~\ref{Fig:two_fold} and \ref{Fig:frequency_response}, we observe that the amplitude of the folded signals could go beyond the dynamic range momentarily around the folding instants. This is due to the settling time of the DC-VG when voltage values change. Specifically, after switching, the voltage at the output of DC-VG overshoots and undershoots before the oscillations settle down to expected value. {\color{red}How to overcome? <NG> this can be overcome by using faster substrator (M) which stabelize time should be at least a magnitude higher then the sample rate}

Another major issue that arises in a folding ADC is time-delay in the feedback loop (See Fig.~\ref{Fig:folding}). To elaborate, consider a scenario where $y(t)<\lambda$ for $t<t_1$ and it crosses $\lambda$ at time $t_1$ as discussed earlier. To fold the output voltage to the dynamic range of the ADC, $z(t) = -2\lambda u(t-t_1)$ needs to be added to $y(t)$. However, there is a finite delay between the trigger time $t_1$ to generating $z(t)$. If the time delay is $T_d$, then $z(t) = -2\lambda u(t-t_1-T_d)$ is added which causes distortion. {\color{red}In the current design we chose to implement the counter management by a TEENSY micro-controller which in total results with 1us delay this implementation provides us the flexability to support a wide range of frequencies with no need to modify the hardware components. In order to support higher frequencies we prepared the option to implement the counter by a discreet components which may result with a faster time response and lower the delay. }

\section{Results}
\subsection{Simulated results}
In this section, we present simulated results of several methods for recovering a bandlimited signal from the modulo samples.
Specifically, we compare the proposed algorithm with the \emph{higher-order differences} (HOD) approach \cite{unlimited_sampling17, uls_tsp} and \emph{Chebyshev polynomial filter}-based (CPF) method \cite{uls_romonov}.
We handle the noisy setting where we compare the proposed and existing approaches for reconstructing signals from modulo samples.
We exhibit the robustness to noise of the $B^2R^2$ algorithm for different noise level and the over-sampling factor.
We consider reconstruction problem from the next noisy samples
        \begin{align}
            \tilde{f}_{\lambda}(n T_s) = {f}_{\lambda}(n T_s) + v(n T_s) = \mathcal{M}_{\lambda}f(n T_s) + v(n T_s),
        \label{eq: noisy_samples}
        \end{align}
where $v(n T_s)$ specifies the noise.
In the experiments the modulo parameter $\lambda$ is fixed to $1.25$. We normalize the bandlimited signals to have maximum amplitude of $10$.
The SNR is calculated as $\text{SNR} = 20 \log\left(\frac{||f_{\lambda}(n T_s)||}{||v(n T_s)||}\right)$. The reconstruction accuracy of different methods is compared in terms of normalized mean-squared error (MSE) as $ \frac{\sum |f(nT_s) - \hat{f}(n Ts)|^2}{\sum |f(nT_s)|^2}$, where $\hat{f}(n T_s)$ signifies the estimate of $f(n T_s)$.
For each noise level and over-sampling factor, we examine 100 independent noise realizations and we calculate the average MSE for them.

\subsubsection{Quantization noise}
 In these experiments, we consider an uniform quantizer after the sampling. We compare the algorithms for different number of bits and OFs. Fig. ~\ref{Fig:quantization} shows MSEs of the different methods for OF $ = 3$ and $6$.

\subsubsection{Unbounded noise}
    For the unbounded noise we assume that the noise measurements $v(nT_s)$ are independent and identically distributed Gaussian random variables with zero mean. The variance is set to achieve a desired SNR. We compare the methods for different values of SNR and OFs. Fig.~\ref{Fig:unbounded} shows MSE of the different algorithms for OF $= 3$ and $6$.

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3 in]{IEEE_TAES_v1/Figs/quantization.png}
	\caption{Quantization noise}
	\label{Fig:quantization}
\end{figure}

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3 in]{IEEE_TAES_v1/Figs/Gaussian.png}
	\caption{Unbounded noise}
	\label{Fig:unbounded}
\end{figure}

\section{Hardware Simulation}
\begin{align}
x(t) = \frac{\sin(w_c t)}{w_c t}
\end{align}
Bandlimited signals
\begin{align}
y(t) = \sum_{m=-M}^M c_m x(t-mT_s).
\end{align}

From hardware:
$y_\lambda(nT_1)$, $T_1<<T_s$. Downsample

FRI signals
\begin{align}
f(t) = \sum_{\ell=1}^L a_\ell \delta(t-\tau_\ell).
\end{align}

\begin{align}
y(t) = \sum_{\ell=1}^L a_\ell x(t-\tau_\ell).
\end{align}

$0 < \tau_\ell \leq T_{\max}$\\

$T_{\max}= \frac{2L 2\pi}{\omega_c}$\\

From hardware:
$y_\lambda(nT_1)$, $T_1<<T_s$. Downsample

\section{Conclusions}

\section*{APPENDIX}

Appendixes, if needed, appear before the acknowledgment.

\section*{ACKNOWLEDGMENT}
The preferred spelling of the word ``acknowledgment'' in American English is without an ``e'' after the ``g.'' Use the singular heading even if you have many acknowledgments. Avoid expressions such as ``One of us (S.B.A.) would like to thank ... .'' Instead, write ``F. A. Author thanks ... .'' In most cases, sponsor and financial support acknowledgments are placed in the unnumbered footnote on the first page, not here.

\bibliographystyle{IEEEtaes}

\section{INTRODUCTION}
Sampling plays a key role in efficiently processing real-world analog signals on digital signal processors. Analog to digital converters (ADCs) are used to implement sampling in the hardware. A key parameter of the ADC is its sampling rate. ADCs with high sampling rates are power consuming and expensive which make them unsuitable for portable devices such as hand-held ultrasound device. Hence, it is desirable to reduce the sampling rate. Following the Shannon-Nyquist sampling theorem \cite{shannon, nyquist}, it is well known that the sampling rate of bandlimited signals are dictated by their highest frequency. Hence, in wideband signal applications one can not sample below the Nquist rate by considering the bandlimited signal model.

Finite-rate-of-innovation (FRI) model is another signal model which is ubiquitous in several time of flight applications \cite{bajwa_radar, bar_radar,filho201seismic,rip,carter_sonar,eldar_sos,eldar_beamforming, sunil}. In these applications, the signal of interest consists of a linear combination of delayed copies of a known pulse. Thus, the desired information lies in the amplitudes and time delays of the pulse which amounts to few degrees of freedom and aids sub-Nyquist sampling \cite{eldar_2015sampling}. Most prior works in the context of FRI sampling are focused on reducing the sampling rate of the ADC by using the signal structure and consequently reducing the power consumption and cost of the ADCs \cite{vetterli, eldar_sos, fri_strang, blu_moms, mulleti_kernal}.

Dynamic range of an ADC too plays a crucial role in sampling an analog signal. In general, ADC's dynamic range should be larger than that of the signal's, otherwise the signal is clipped. There exist a few approaches to recover the true samples from clipped ones for bandlimited signals \cite{marks_clipping2, marks_clipping1}. These approaches relies on correlation among the samples when they are measured at very high-rate compared to the Nyquist rate. Requirement of high-sampling rate is a drawback of these approaches. In addition, theoretical guarantees are missing and it is not clear on how many clipped samples can be recovered.

There are three popular analog preprocssing approaches, namely automatic gain control (AGC) \cite{perez2011automatic,mercy1981review}, companding \cite{landau_compander,landau_distorted_bl}, and modulo folding \cite{uls_tsp,uls_romonov,uls_sparse,bhandari2021unlimited,eyar_moduloicassp}, that can be used prior to sampling to avoid clipping. In AGC, a chain of amplifiers is used with a feedback loop such that a suitable output level is maintained at the output \cite{perez2011automatic,mercy1981review}. An AGC system uses a closed loop feedback mechanism to maintain a constant signal level at its output for a varying input signal levels \cite{perez2011automatic,mercy1981review}. The closed loop feedback consists of a chain of amplifiers and maintaining its stability is a challenging task. Companding is an alternative approach to limit the dynamic range of the input signals. In this approach, smaller amplitudes of the signals have larger gain compared to the larger ones. Beurling presented theoretical guarantees and proved that knowledge of the companded signal over the input signal's bandwidth is sufficient to uniquely identify the signal provided \cite{landau_compander}. Landau et al. \cite{landau_distorted_bl} proposed an iterative algorithm to recover a bandlimited signal from its companded signal. The algorithm converges if the compander is differentiable over the dynamic range of the input signal which limits its practical application.

The third approach is to use modulo folding prior to sampling which fold the input signal to lie within the dynamic range of the ADC \cite{uls_tsp,uls_romonov,uls_sparse,bhandari2021unlimited,eyar_moduloicassp}. The folded signal is then sampled by using a conventional ADC. Theoretical guarantees for recovering bandlimited signals from folded samples are presented in \cite{uls_tsp,uls_identifiability}. The results states that the bandlimited signals can be uniquely recovered from folded samples provided that they are sampled above the Nyquist rate. Several algorithms for \emph{unfolding} or recovering the true samples of bandlimited signals from modulo or folded samples are presented in \cite{uls_tsp,uls_romonov, eyar_moduloicassp}. These unfolding algorithms can be compared in terms of sampling rate, amount of unfolding they can accommodate, and noise robustness. It is shown that the method proposed in \cite{eyar_moduloicassp} has lowest reconstruction error for a given sampling rate, noise level, and signal's amplitude level compared to the algorithms presented in \cite{uls_tsp,uls_romonov}. The algorithm proposed in \cite{uls_tsp} requires almost 17-times higher sapling rate than the Nyquist rate but it is independent of the dynamic range of the ADC. Whereas, the approaches in \cite{uls_romonov, eyar_moduloicassp} requires the knowledge of ADC's dynamic range. Modulo sampling is also extended to different problems and signal models such as periodic bandlimited signals \cite{bhandari2021unlimited}, wavelets \cite{uls_wavelet}, mixture of sinusoids \cite{uls_sinmix}, finite-rate-of-innovation signals \cite{uls_fri}, multi-dimensional signals \cite{uls_md}, sparse vector recovery \cite{uls_gamp, uls_sparsevec}, direction of arrival estimation problem \cite{uls_doa}, computed tomography \cite{uls_radon}, and graph signals \cite{uls_graph}.

While theoretical guarantees and algorithms of any new sampling approach are always well researched but the question on whether they work in practice is always difficult to answer. For modulo sampling, there exists a few hardware prototypes. For example, high-dynamic-range ADCs, also known as \emph{self-reset} ADCs, are discussed in the context of imaging \cite{sradc_park, sradc_sasagwa, sradc_yuan, krishna2019unlimited}. These hardware architectures measures additional information such as the amount of folding for each sample, or, the sign of the folding together with the folded samples. The additional information might enable simpler recovery but at the expense of complex circuitry. Importantly, additional bits are required during the quantization process to store or transmit the side information.

Krishna et al. presented a hardware prototype which encode the side-information by using two bits \cite{krishna2019unlimited}. The architecture is designed to record sign of the slope of the signal at each sampling instant when the sample lies outside ADC's dynamic range. In a conventional ADC, a sample and hold (S/H) circuit is used to hold the sampled value for a prescribed period of time during which quantization is performed on the sample. To realize the modulo sampling, a folding circuit is used after S/H \cite{krishna2019unlimited}. Hence, the S/H circuit has to hold the sampled value for folding and quantization, which results in a larger folding time compared to a conventional ADC. A large holding time results in slower ADC and hence it may not be useful for wideband application.

The proposed modulo-ADC is able to sample signals beyond its dynamic range while keeping the power dissipation and area requirements lower compared to a conventional ADC \cite{krishna2019unlimited}. A major drawback of this modulo-ADC's architecture is that the modulo operation is performed between the sample and hold (S/H), and quantization blocks of the ADC. Specifically, modulo operation is performed on the hold values of S/H circuit and then the folded sample is quantized. Hence, compared to a conventional ADC, the hold time is relatively high which makes the architecture slower.

\newpage
In introduction, we discuss the following:

1st-paragraph: Standard sampling and sub-Nyquist; importance of low sampling rates; FRI signal model and application to radar\\

2nd-paragraph: Introduce the dynamic range issue and discuss the existing approaches to address it: AGC, commanding, and modulo. Why modulo is important.\\

3rd paragraph: Discuss about modulo method, recovery algorithms and their issues with high-sampling rates and instability in noise. Discuss about our proposed algorithm (Eyar's ICASSP-22 paper)\\

4th paragraph: Can we implement these in HW? Discuss about hardware prototypes and applications. Shortcomings: No practical applications, low operating frequencies, more?\\

5th paragraph: In this paper, we present a HW prototype combined with recently proposed algorithm to address these issues.\\

 6th Paragraph: The paper is organized as follows; Notations \\

\section{Signal Model and System Description}
In this section, we first introduce FRI signal model and then discuss its sampling and reconstruction framework with modulo ADC.
\subsection{FRI Signal Model}
Consider an FRI signal consisting of stream of $L$ pulses:
\begin{align}
	f(t) = \sum_{\ell=1}^L a_\ell h(t-t_\ell),
	\label{eq:fri1}
\end{align}
where the pulse $h(t)$ a real-valued known pulse. We assume that $a_\ell$s are real-valued and $t_\ell \in (0, T_d] \subset \mathbb{R}$ for a known $T_d$.

The FRI signal model in \eqref{eq:fri1} is encountered in several scientific applications such as radar imaging \cite{bar_radar, bajwa_radar, sunil}, ultrasound imaging \cite{eldar_sos,eldar_beamforming,mulleti_icip}, light detection and ranging (LIDAR) \cite{castorena_lidar}, time-domain optical-coherence tomography (TDOCT) \cite{blu_oct}, and other time-of-flight imaging systems. In these applications,  $h(t)$ is the transmitted pulse and $\{a_\ell \,h(t-t_\ell)\}_{\ell=1}^{L}$ constitute the reflections from $L$ point targets. The amplitudes $a_\ell$s depend on the sizes of the targets and the delays $t_\ell$s are proportional to the distances of the targets from the transmitter. Here $T_d$ denotes maximum time delay of the targets. The signal $f(t)$ is specified by $\{a_\ell, t_\ell\}_{\ell=1}^L$ and can be reconstructed from its sub-Nyquist measurements acquired using an appropriate sampling kernel \cite{vetterli,eldar_sos,fri_strang, mulleti_kernal}. The reconstruction is generally carried out in frequency domain as discussed next.

\subsection{Fourier-Domain Reconstruction}
Consider uniform samples of continuous-time Fourier transform of $f(t)$ given as
\begin{align}
	F(k \omega_0) = \int f(t) e^{-\mathrm{j} k\omega_0 t} \mathrm{d}t = H(k \omega_0) \sum_{\ell = 1}^L a_\ell \, e^{-\mathrm{j} k\omega_0 t_\ell},
	\label{eq:F}
\end{align}
for $k \in \mathcal{K}$ where $H(\omega)$ is the Fourier transform of $h(t)$ and $\mathcal{K}$ is a set integers. In \eqref{eq:F}, $\omega_0>0$ denotes sampling interval in the frequency domain. Next, consider the following samples
\begin{align}
	S(k\omega_0) = \frac{F(k\omega_0)}{H(k\omega_0)} =  \sum_{\ell = 1}^L a_\ell \, e^{-\mathrm{j}k\omega_0 t_\ell},
	\label{eq:Skomega}
\end{align}
where we assume that $H(k \omega_0) \neq 0$ for $k \in \mathcal{K}$. In practice, the pulse $h(t)$ has small time support and hence, large bandwidth. Hence, for a finite set $\mathcal{K}$ it is possible to choose a set of frequencies $\{k \omega_0\}_{ k \in \mathcal{K}}$ such that $H(k \omega_0) \neq 0$ for $k \in \mathcal{K}$. It can be shown that $2L$ consecutive samples of $S(k\omega_0)$ are sufficient to uniquely identify $\{a_\ell, t_\ell\}_{\ell=1}^L$ if $\omega_0 = \frac{2\pi}{T_d}$ \cite{eldar_2015sampling}. In practice, high-resolution spectral estimation methods, such as the annihilating filter (AF) or Prony's method and its variants \cite{prony, plonka}, multiple signal classification \cite{schmidt_music, barabell_rmusic, bdrao_rmusic}, matrix-pencil method \cite{sarkar_mp}, estimation of signal parameter via rotational invariance technique (ESPRIT) \cite{paulraj_esprit}, etc. have been deployed for FRI parameter estimation.

Since $h(t)$ is known, $H(k\omega_0), k \in \mathcal{K}$ can be calculated in advance. Hence, to compute $S(k\omega_0), k \in \mathcal{K}$ and then estimate FRI parameters, $F(k\omega_0), k \in \mathcal{K}$ has to be determined. Next, we discuss a lowpass filter (LPF) based sampling framework to determine these Fourier samples.

\subsection{LPF-Based Sub-Nyquist Sampling}
In this section, we discuss a LPF-based sampling mechanism for FRI signals. Let $g(t)$ denotes an ideal lowpass filter with cutoff frequency $\omega_c$ rad/sec. In the frequency-domain we have that $G(\omega) = 1$ for $\omega \in [-\omega_c, \omega_c]$ and zero for the rest of the frequencies. Let $y(t)$ denotes response of the LPF to the input $f(t)$, that is, $y(t) = (f*g)(t)$, where $*$ denotes linear convolution operation. Consider an ADC with dynamic range $[-\lambda, \lambda]$ and sampling rate $\omega_s = \frac{2\pi}{T_s}$ rad/sec. By assuming that  $\|y(t)\|_{\infty}\leq \lambda$, uniform samples at the output of ADC are given as $y(nT_s), n \in \mathbb{Z}$. Then uniform measurements of discrete-time Fourier transform (DTFT) of the samples are given as
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) = \sum_{n \in \mathbb{Z}}y(nT_s)\,e^{\mathrm{j} k\omega_0 n T_s}, \quad k \in \mathcal{K}.
	\label{eq:y_dtft}
\end{align}
By using relationship between DTFT of samples $y(nT_s)$ and CTFT of $y(t)$ we have
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) &= \frac{1}{T_s}\sum_{m \in \mathbb{Z}} Y(k\omega_0 + m \omega_s), \nonumber \\
	&= \frac{1}{T_s}\sum_{m \in \mathbb{Z}} F(k\omega_0 + m \omega_s) \,G(k\omega_0 + m \omega_s),
		\label{eq:y_dtft2}
\end{align}
where we used the fact that $Y(\omega) = F(\omega)\,G(\omega)$. Next, consider the following conditions on the sampling rate and cutoff frequency of the filter
\begin{align}
	\omega_s \geq 2\omega_c, \quad \text{and} \quad \omega_c \geq K \omega_0,
	\label{eq:sampling_rate}
\end{align}
where $K \geq L$. Then by choosing $\mathcal{K} = \{-K, \cdots, K\}$, \eqref{eq:y_dtft2} can be written as
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) = F(k\omega_0), \quad k \in \mathcal{K},
	\label{eq:y_dtft3}
\end{align}
where we used the fact that $G(k\omega_0) = 1$ in these settings. The relationship \eqref{eq:y_dtft3} shows that the desired Fourier samples of $f(t)$ are determined from the samples of LPF by assuming that the conditions in \eqref{eq:y_dtft2} are satisfied. Hence, FRI parameters can be determined from the samples of the lowpass filter.

The bandwidth of the pulse $h(t)$ and hence that of the FRI signal $f(t)$ could be very large. But the sampling rate $\omega_s$ is independent of the pulse and could be much smaller than its bandwidth which shows the FRI signal could be reconstructed from sub-Nyquist samples.

The sub-Nyquist sampling framework discussed assumes that $\|y(t)\|_{\infty}\leq \lambda$, in other words, the framework assumes that the dynamic range of the ADC is greater than that of the signal to be sampled. However, this condition may not be always true. Specifically, the amplitude range of the filtered signal $y(t)$ could be larger than ADC's dynamic range. In such scenario, a direct sampling would lead to clipping of samples which is undesirable. To avoid clipping, a modulo operator is employed prior to sampling as discussed next.

\begin{figure*}
	\centering
	\includegraphics[width=6.5 in]{Figs/FRI_US}
	\caption{A schematic of modulo-sampling and reconstruction of FRI signals.}
	\label{fig:fri_framework}
\end{figure*}

\subsection{Modulo-Folding}
To avoid clipping, a modulo folding operator $\mathcal{M}_\lambda(\cdot)$ is used after LPF and before the ADC. The operator folds $y(t)$ to stay within ADC's dynamic range $[-\lambda, \lambda]$. The output of the modulo operator in response to input $y(t)$ is given as\begin{equation}
 y_\lambda(t) =	\mathcal{M}_{\lambda}(y(t)) = (y(t)+\lambda)\,\, \text{mod}\,\, 2\lambda -\lambda.
	\label{eq:mod_opp}
\end{equation}
The folded signal is then sampled by the ADC to have measurements $y_\lambda(nT_s)$. Since modulo folding is a nonlinear operation, one can not directly apply DTFT on the samples to compute Fourier measurements of the FRI signal for its reconstruction. Hence, the true or unfolded samples $y(nT_s)$ are estimated from the folded ones $y_\lambda(nT_s)$ by applying an unfolding algorithm. There exist several unfolding methods for badnlimited signals such as $y(t)$ \cite{uls_tsp, uls_romonov,eyar_moduloicassp}. The sampling rates for unfolding varies for different algorithms and generally, is larger than the minimum sampling rate required for FRI signal recovery (cf. \eqref{eq:sampling_rate}). Hence, the overall system operates on a higher sampling rate than that in without modulo case. However, if the overall sampling rate is much lower than the bandwidth of the FRI signal then the system operates at sub-Nyquist rate. We show that this is indeed true when we apply our unfolding algorithm proposed in \cite{eyar_moduloicassp}.

An end-to-end modulo sampling framework for FRI signal sampling and reconstruction is shown in Fig.~\ref{fig:fri_framework}. The sampler or ADC together with the modulo block is termed as modulo-ADC. Modulo-ADC's are able to sample signals beyond their dynamic range without clipping and hence they are termed as high-dynamic range ADCs. Alternatively, an ADC with much lower dynamic range can be used to sample signals with larger amplitudes. Sub-Nyquist sampling and low-dynamic range requirements significantly reduces the power consumption and cost of the ADC.

The modulo folding block is key component of the high-dynamic range ADC and we discuss it hardware implementation in the next section.

\begin{figure}
	\centering
	\includegraphics[width= 3 in]{Figs/folding}
	\caption{Folding principle}
	\label{Fig:folding}
\end{figure}
\section{Modulo Hardware Prototype}
In this section, we discuss our modulo hardware prototype. First, we explain the working principle of the modulo block and explain how its design and then discuss the hardware realization.
\subsection{Working Principle of Modulo Block}
Principle of computing $y_\lambda(t)$ from $y(t)$ is shown by block-diagram in Fig.~\ref{Fig:folding}. The system comprises of an adder $S$, a direct-current voltage generator (DC-VG), and two comparators $C_1$ and $C_2$. To understand the working let us first assume that for some time instant $t_1$, we have that $|y(t)|<\lambda$ for $t<t_1$. Hence $y_\lambda(t) = y(t)$ and $z(t) = 0$ for $t<t_1$. At $t=t_1$, let $|f(t)|$ crosses $\lambda$. If $f(t_1)>0$, then the comparator $C_1$ triggers a positive spike or else, $C_2$ triggers a negative spike. The DC-VG is designed such that for every positive spike input it reduces its output signal level by $-2\lambda$, whereas, for negative spike it increases its output voltage by $2\lambda$. Hence, in the current example, DC-VG generates signal $z(t) = \text{sgn}(y_\lambda(t_1)) 2\lambda u(t-t_1)$ where $u(t)$ is unit-step function.
In this way by adding or subtracting (by using $S$) constant DC signals from $f(t)$ whenever it crosses dynamic range $[-\lambda, \lambda]$, the amplitude levels of $f_\lambda(t)$ are kept within ADC's dynamic range.

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3 in]{Figs/dc_vg}
	\caption{DC-VG}
	\label{Fig:dcvg}
\end{figure}

\begin{figure*}[!t]
	\centering
	\includegraphics[width=5 in]{Figs/UDR_Board_Labeled.PNG}
	\caption{DC-VG Modulo Hardware Board}
	\label{Fig:hw_board}
\end{figure*}
\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[]{\includegraphics[width=3in]{Figs/UDRPhase2pictures500Hz}\label{fig:500_2}} \\
		\subfigure[]{\includegraphics[width=3in]{Figs/UDRPhase2pictures2KHz}\label{fig:2k_2}}
	\end{tabular}
	\caption{Two Fold}
	\label{Fig:two_fold}
\end{figure}

\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[]{\includegraphics[width=3in]{Figs/500Hz}\label{fig:500_1}} \\
		\subfigure[]{\includegraphics[width=3in]{Figs/1KHz}\label{fig:1k_1}} \\
		\subfigure[]{\includegraphics[width=3in]{Figs/5KHz}\label{fig:5k_1}}
	\end{tabular}
	\caption{Frequency response}
	\label{Fig:frequency_response}
\end{figure}

\begin{table}[h!]
		\caption{Folding Operation.}
	\centering
	\begin{tabular}{||c c c c c ||}
		\hline
		c & b & a & sgn & Counter values \\ [0.5ex]
		\hline\hline
		0 & 0 & 0 & 0~(1) & 0~(0) \\
		0 & 0 & 1 & 0~(1) & 1~(1) \\
		0 & 1 & 0 & 0~(1) & 2~(2) \\
		0 & 1 & 1 & 0~(1) & 3~(3) \\
		1 & 0 & 0 & 0~(1) & 4~(4) \\
		0 & 0 & 1 & 1~(0) & 1~(-1) \\
		0 & 1 & 0 & 1~(0) & 2~(-2) \\
		0 & 1 & 1 & 1~(0) & 3~(-3) \\
		1 & 0 & 0 & 1~(0) & 4~(-4) \\
		\hline
	\end{tabular}
	\label{table:counter}
\end{table}

While the parts such as comparators $C_1$, $C_2$, and adder $S$ can be realized by using off-the-shelf components, DC-VG is more involved system and required careful design. A detailed architecture of DC-VG is shown in Fig.~\ref{Fig:dcvg}. It consists of an up/down counter, a digital-to-analog converter (DAC), a multiplexer (MUX), and a multiplier $M$.  The role of the counter (together with DAC) is to generate a variable, but controlled, DC voltage whenever there is a trigger at its input. The voltage values are set to be multiple of $2\lambda$ by using the MUX and multiplier $M$. To explain the working in details, we first discuss the counter and then the rest of the components.

In this particular system, we use a three-bit synchronous up/down converter. The bits from lower significant bit to higher significant bit are denoted as a, b, and c. The counter has an additional sign bit shown as sgn. With these bits, the counter can count from -7 to 7. For every positive trigger at the input, the output counts up and with negative trigger it counts down. In Table~\ref{table:counter}, we display the values of bits and the counter (denoted as counter values). The three bits (a,b,and c) of the counter is used as input to the DAC which convert the bits to analog DC voltages. Let the resolution or step size of the DAC is $\alpha$ then the output of DAC is counter-value times $\alpha$. To explain the working in more details, consider the scenario where the output of counter and DAC are zero. Then for a positive (negative) trigger, the output of DAC increases (decreases) by $\alpha$. Specifically, output of DAC, $s(t)$, is a piecewise constant signal with its values which are multiple of $\alpha$. However, for folding to work, the change in the voltage should be in multiple of $2\lambda$. To ascertain that we use a MUX which outputs either $2\lambda/\alpha$ or $-2\lambda/\alpha$ depending on whether its input is 1 or 0. Then by multiplying output of DAC with output of MUX we generate $z(t)$. Next, we discuss the hardware board the realize the folding operation discussed in this section.

\begin{table}[h!]
\centering
\caption{List of Hardware Components}
\label{table:hardware_components}
\begin{tabular}{||c c c||}
 \hline
 Component & Model Number & Make \\
 && \\ \hline
 Comparator & LM339 & Texas Instruments \\
 && \\
 UP/DOWN Counter & TEENSY4.1 & PJRC \\
 && \\
 DAC 3bits & LT1364 & Analog Devices \\
 && \\
 Analog MUX & ADG1608 & Analog Devices \\
 && \\
 Analog Multiplier & AD835 & Analog Devices \\
 && \\
 Subtractor & LT1364 & Analog Devices \\
  && \\ [1ex]
\hline
\end{tabular}
\end{table}
\subsection{Modulo Hardware Board}
Our modulo hardware board is shown in Fig.~\ref{Fig:hw_board} with different building components are labeled. The board is designed for $\lambda \leq 1.25$ volts. The board can accommodate an input signal with dynamic range between $[-4\lambda, 4\lambda]$ which implies that an ADC with our modulo hardware can sample four-times larger signals compared to its dynamic range without saturation and clipping. We demonstrate working of the modulo hardware by considering sinusoidal signal $y(t) = A\, \sin(2\pi f_0 t)$ where $A$ is amplitude and $f_0$ is frequency (in Hz). In this experiment, we set $\lambda = 1.25$ and $3\lambda <A <4\lambda$. With these settings, we expect the signal to fold twice in a quarter cycle of sinusoid. Figs.~\ref{Fig:two_fold}(a) and \ref{Fig:two_fold}(b) screenshots of an oscilloscope capturing input $y(t)$ (in yellow) and its folded output $y_\lambda(t)$ (in green) for $f_0 = 500$ Hz and $f_0 = 2$ kHz, respectively. We observed that the signals are folded back to lie within the dynamic range of the ADC as expected without clipping. The reason we choose two different frequencies is to study the frequency response of the modulo folder. As in any analog system, the response of modulo folder too depends on the frequency or bandwidth of the input signal. Beyond a particular frequency the foldings may not be accurate as observed in Fig.~\ref{Fig:frequency_response}. We observed that for signals of 500 Hz and 1kHz the hardware is able to fold the signal accurately. However, for $f_0 = 5$ kHz, folding instants are not symmetric for positive and negative folds. In the next section, we discuss a couple of inaccuracies of the modulo hardware and our proposed solution to overcome those.

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3.2 in]{Figs/mod_td}
	\caption{Time Delay}
	\label{Fig:mod_td}
\end{figure}

\subsection{Artifacts During Folding}
Errors or other artifacts arise during folding operation in a hardware could be due to various reasons. For examples, in Figs.~\ref{Fig:two_fold} and \ref{Fig:frequency_response}, we observe that the amplitude of the folded signals could go beyond the dynamic range momentarily around the folding instants. This is due to the settling time of the DC-VG when voltage values change. Specifically, after switching, the voltage at the output of DC-VG overshoots and undershoots before the oscillations settle down to expected value. This can be overcome by using faster substrator (M) which its response time should be at least a magnitude higher than the sample rate.

Another major issue that arises in a folding ADC is time-delay in the feedback loop (See Fig.~\ref{Fig:folding}). To elaborate, consider a scenario where $y(t)<\lambda$ for $t<t_1$ and it crosses $\lambda$ at time $t_1$ as discussed earlier. To fold the output voltage to the dynamic range of the ADC, $z(t) = -2\lambda u(t-t_1)$ needs to be added to $y(t)$. However, there is a finite delay between the trigger time $t_1$ to generating $z(t)$. If the time delay is $T_d$, then $z(t) = -2\lambda u(t-t_1-T_d)$ is added which causes distortion. In the current design we chose to implement the counter management by a TEENSY micro-controller which in total results with 1us delay this implementation provides us the flexibility to support a wide range of frequencies with no need to modify the hardware components. In order to support higher frequencies we prepared the option to implement the counter by a discreet components which may result with a faster time response and lower the delay.

\section{Results}
\subsection{Simulated results}
In this section, we present simulated results of several methods for recovering a bandlimited signal from the modulo samples.
Specifically, we compare the proposed algorithm with the \emph{higher-order differences} (HOD) approach \cite{unlimited_sampling17, uls_tsp} and \emph{Chebyshev polynomial filter}-based (CPF) method \cite{uls_romonov}.
We handle the noisy setting where we compare the proposed and existing approaches for reconstructing signals from modulo samples.
We exhibit the robustness to noise of the $B^2R^2$ algorithm for different noise level and the over-sampling factor.
We consider reconstruction problem from the next noisy samples
        \begin{align}
            \tilde{f}_{\lambda}(n T_s) = {f}_{\lambda}(n T_s) + v(n T_s) = \mathcal{M}_{\lambda}f(n T_s) + v(n T_s),
        \label{eq: noisy_samples}
        \end{align}
where $v(n T_s)$ specifies the noise.
In the experiments the modulo parameter $\lambda$ is fixed to $1.25$. We normalize the bandlimited signals to have maximum amplitude of $10$.
The SNR is calculated as $\text{SNR} = 20 \log\left(\frac{||f_{\lambda}(n T_s)||}{||v(n T_s)||}\right)$. The reconstruction accuracy of different methods is compared in terms of normalized mean-squared error (MSE) as $ \frac{\sum |f(nT_s) - \hat{f}(n Ts)|^2}{\sum |f(nT_s)|^2}$, where $\hat{f}(n T_s)$ signifies the estimate of $f(n T_s)$.
For each noise level and over-sampling factor, we examine 100 independent noise realizations and we calculate the average MSE for them.

\subsubsection{Quantization noise}
 In these experiments, we consider an uniform quantizer after the sampling. We compare the algorithms for different number of bits and OFs. Fig. ~\ref{Fig:quantization} shows MSEs of the different methods for OF $ = 3$ and $6$.

\subsubsection{Unbounded noise}
    For the unbounded noise we assume that the noise measurements $v(nT_s)$ are independent and identically distributed Gaussian random variables with zero mean. The variance is set to achieve a desired SNR. We compare the methods for different values of SNR and OFs. Fig.~\ref{Fig:unbounded} shows MSE of the different algorithms for OF $= 3$ and $6$.

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3 in]{IEEE_TAES_v1/Figs/quantization.png}
	\caption{Quantization noise}
	\label{Fig:quantization}
\end{figure}

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3 in]{IEEE_TAES_v1/Figs/Gaussian.png}
	\caption{Unbounded noise}
	\label{Fig:unbounded}
\end{figure}

\section{Hardware results}
In this section we will describe the modulo board results for two examples of a bandlimited signals and their output folded signal $y_\lambda(nT_s)$.

The first example as described in Fig[\ref{fig:Signal_num1}] is a bandlimited signal with bandwidth of 1Khz and a duration of 0.1sec.
Fig[\ref{fig:signal_num1_ZoomIn}] demonstrate the folding of the modulo circuit in more details. The reconstruction of the signal is described in the results section.

The second example as described in Fig[\ref{fig:Signal_num2}] is a bandlimited signal with bandwidth of 1Khz and a duration of 0.1sec. Fig[\ref{fig:signal_num2_ZoomIn}] demonstrate the folding of the modulo circuit in more details. The reconstruction of the signal is described in the results section.

\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[]{\includegraphics[width=3in]{IEEE_TAES_v1/Figs/Eyar_BL_signal_num1_for_UDR21.png}\label{fig:Signal_num1}} \\
		\subfigure[]{\includegraphics[width=3in]{IEEE_TAES_v1/Figs/Eyar_BL_signal_num1_for_UDR21_ZoomIn.png}\label{fig:signal_num1_ZoomIn}} \\
	\end{tabular}
	\caption{Example 1 - Bandlimited signal with bandwidth of 1Khz and a duration of 0.1sec}
	\label{fig:signal_num1_for_UDR21}
\end{figure}

\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[]{\includegraphics[width=3in]{IEEE_TAES_v1/Figs/Eyar_BL_signal_num2_for_UDR21.png}\label{fig:Signal_num2}} \\
		\subfigure[]{\includegraphics[width=3in]{IEEE_TAES_v1/Figs/Eyar_BL_signal_num2_for_UDR21_ZoomIn.png}\label{fig:signal_num2_ZoomIn}} \\
	\end{tabular}
	\caption{Example 2 - Bandlimited signal with bandwidth of 1Khz and a duration of 0.1sec}
	\label{fig:signal_num1_for_UDR21}
\end{figure}

\section{Hardware Simulation}
\begin{align}
x(t) = \frac{\sin(w_c t)}{w_c t}
\end{align}
Bandlimited signals
\begin{align}
y(t) = \sum_{m=-M}^M c_m x(t-mT_s).
\end{align}

From hardware:
$y_\lambda(nT_1)$, $T_1<<T_s$. Downsample

FRI signals
\begin{align}
f(t) = \sum_{\ell=1}^L a_\ell \delta(t-\tau_\ell).
\end{align}

\begin{align}
y(t) = \sum_{\ell=1}^L a_\ell x(t-\tau_\ell).
\end{align}

$0 < \tau_\ell \leq T_{\max}$\\

$T_{\max}= \frac{2L 2\pi}{\omega_c}$\\

From hardware:
$y_\lambda(nT_1)$, $T_1<<T_s$. Downsample

\section{Conclusions}

\section*{APPENDIX}

Appendixes, if needed, appear before the acknowledgment.

\section*{ACKNOWLEDGMENT}
The preferred spelling of the word ``acknowledgment'' in American English is without an ``e'' after the ``g.'' Use the singular heading even if you have many acknowledgments. Avoid expressions such as ``One of us (S.B.A.) would like to thank ... .'' Instead, write ``F. A. Author thanks ... .'' In most cases, sponsor and financial support acknowledgments are placed in the unnumbered footnote on the first page, not here.

\bibliographystyle{IEEEtaes}

\section{INTRODUCTION}
Sampling plays a key role in efficiently processing real-world analog signals on digital signal processors. Analog to digital converters (ADCs) are used to implement sampling in the hardware. A key parameter of an ADC is its sampling rate. ADCs with high sampling rates are power-consuming and expensive, making them unsuitable for portable devices such as hand-held ultrasound devices. Hence, it is desirable to reduce the sampling rate. Following the Shannon-Nyquist sampling, theorem \cite{shannon, nyquist}, it is well known that the sampling rate of bandlimited signals is dictated by their highest frequency. Hence, in wideband signal applications, one can not sample below the Nyquist rate by considering the bandlimited signal model.

Finite-rate-of-innovation (FRI) model is another signal model which is ubiquitous in several time of flight applications \cite{bajwa_radar, bar_radar,filho201seismic,rip,carter_sonar,eldar_sos,eldar_beamforming, sunil}. In these applications, the signal of interest consists of a linear combination of delayed copies of a known pulse. Thus, the desired information lies in the amplitudes and time delays of the pulse, which amounts to a few degrees of freedom and aids sub-Nyquist sampling \cite{eldar_2015sampling}. Most prior works in the context of FRI sampling focus on reducing the ADC's sampling rate by using the signal structure and consequently reducing the power consumption and cost of the ADCs \cite{vetterli, eldar_sos, fri_strang, blu_moms, mulleti_kernal}.

The dynamic range of an ADC to plays a crucial role in sampling an analog signal. ADC's dynamic range should generally be larger than the signal's; otherwise, the signal is clipped. A few approaches exist to recover the true samples from clipped ones for bandlimited signals \cite{marks_clipping2, marks_clipping1}. These approaches rely on the correlation among the samples when they are measured at a very high rate compared to the Nyquist rate. The requirement of a high sampling rate is a drawback of these approaches. In addition, theoretical guarantees are missing, and it is unclear how many clipped samples can be recovered.

There are three popular analog preprocessing approaches, namely automatic gain control (AGC) \cite{perez2011automatic,mercy1981review}, companding \cite{landau_compander,landau_distorted_bl}, and modulo folding \cite{uls_tsp,uls_romonov,uls_sparse,bhandari2021unlimited,eyar_moduloicassp}, that can be used prior to sampling to avoid clipping. In AGC, a chain of amplifiers is used with a feedback loop such that a suitable output level is maintained at the output \cite{perez2011automatic,mercy1981review}. An AGC system uses a closed-loop feedback mechanism to maintain a constant signal level at its output for varying input signal levels \cite{perez2011automatic,mercy1981review}. The closed-loop feedback consists of a chain of amplifiers and maintaining its stability is a challenging task. Companding is an alternative approach to limit the dynamic range of the input signals. In this approach, smaller amplitudes of the signals have a larger gain compared to the larger ones. Beurling presented theoretical guarantees and proved that knowledge of the companded signal over the input signal's bandwidth is sufficient to uniquely identify the signal provided \cite{landau_compander}. Landau et al. \cite{landau_distorted_bl} proposed an iterative algorithm to recover a bandlimited signal from its companded signal. The algorithm converges if the compander is differentiable over the dynamic range of the input signal which limits its practical application.

The third approach is to use modulo folding prior to sampling which fold the input signal to lie within the dynamic range of the ADC \cite{uls_tsp,uls_romonov,uls_sparse,bhandari2021unlimited,eyar_moduloicassp}. The folded signal is then sampled by using a conventional ADC. Theoretical guarantees for recovering bandlimited signals from folded samples are presented in \cite{uls_tsp,uls_identifiability}. The results states that the bandlimited signals can be uniquely recovered from folded samples provided that they are sampled above the Nyquist rate. Several algorithms for \emph{unfolding} or recovering the true samples of bandlimited signals from modulo or folded samples are presented in \cite{uls_tsp,uls_romonov, eyar_moduloicassp}. These unfolding algorithms can be compared in terms of sampling rate, amount of unfolding they can accommodate, and noise robustness. It is shown that the method proposed in \cite{eyar_moduloicassp} has lowest reconstruction error for a given sampling rate, noise level, and signal's amplitude level compared to the algorithms presented in \cite{uls_tsp,uls_romonov}. The algorithm proposed in \cite{uls_tsp} requires almost 17-times higher sapling rate than the Nyquist rate but it is independent of the dynamic range of the ADC. Whereas, the approaches in \cite{uls_romonov, eyar_moduloicassp} requires the knowledge of ADC's dynamic range. Modulo sampling is also extended to different problems and signal models such as periodic bandlimited signals \cite{bhandari2021unlimited}, wavelets \cite{uls_wavelet}, mixture of sinusoids \cite{uls_sinmix}, finite-rate-of-innovation signals \cite{uls_fri}, multi-dimensional signals \cite{uls_md}, sparse vector recovery \cite{uls_gamp, uls_sparsevec}, direction of arrival estimation problem \cite{uls_doa}, computed tomography \cite{uls_radon}, and graph signals \cite{uls_graph}.

While theoretical guarantees and algorithms of any new sampling approach are always well researched but the question of whether they work in practice is always difficult to answer. For modulo sampling, there exists a few hardware prototypes. For example, high-dynamic-range ADCs, also known as \emph{self-reset} ADCs, are discussed in the context of imaging \cite{sradc_park, sradc_sasagwa, sradc_yuan, krishna2019unlimited}. These hardware architectures measure additional information such as the amount of folding for each sample, or, the sign of the folding together with the folded samples. The additional information might enable simpler recovery but at the expense of complex circuitry. Importantly, additional bits are required during the quantization process to store or transmit the side information.

Krishna et al. presented a hardware prototype which encode the side-information by using two bits \cite{krishna2019unlimited}. The architecture is designed to record sign of the slope of the signal at each sampling instant when the sample lies outside ADC's dynamic range. In a conventional ADC, a sample and hold (S/H) circuit is used to hold the sampled value for a prescribed period of time during which quantization is performed on the sample. To realize the modulo sampling, a folding circuit is used after S/H \cite{krishna2019unlimited}. Hence, the S/H circuit has to hold the sampled value for folding and quantization, which results in a larger folding time compared to a conventional ADC. A large holding time results in slower ADC and hence it may not be useful for wideband application.

The proposed modulo-ADC is able to sample signals beyond its dynamic range while keeping the power dissipation and area requirements lower compared to a conventional ADC \cite{krishna2019unlimited}. A major drawback of this modulo-ADC's architecture is that the modulo operation is performed between the sample and hold (S/H), and quantization blocks of the ADC. Specifically, modulo operation is performed on the hold values of S/H circuit and then the folded sample is quantized. Hence, compared to a conventional ADC, the hold time is relatively high which makes the architecture slower. Modulo hardware prototypes where the modulo part is implemented prior to sampler are presented in \cite{bhandari2021unlimited,Bhandari:2022:J,mod_hyst}. Since the modulo circuit is not part of the hold time, the ADC could be faster than the hardware realization in \cite{krishna2019unlimited}.  In \cite{mod_hyst}, the authors discussed a few implementation issues of modulo hardware such as hysteresis and folding transients, and propose algorithmic solutions to mitigate them. Both these issues can also be addressed by careful calibration and by using high precision components. In \cite{Bhandari:2022:J}, Bhandari showed reconstruction of FRI signals by suing a modulo hardware. In \cite{bhandari2021unlimited,Bhandari:2022:J,mod_hyst}, details of the hardware circuitry is not discussed and hence we can not comment further on the implementation aspects. While focusing on different signal models, hardware aspects, and algorithms, the authors show that the modulo hardware is able to fold signals which are 10-12 times larger than the ADC's dynamic range. However, not much is discussed about the frequency response of the modulo circuit which too plays a crucial role in the application of these circuits.

In this paper, we present a modulo hardware prototype and show that by using our algorithm \cite{eyar_moduloicassp} it is able to faithfully reconstruct FRI signals.
In the following, we present our contributions and the salient features of our hardware system.
\begin{itemize}
    \item Our main focus during the design phase is to show that the modulo system can fold high frequency signals. To this end we choose our components such that the system can faithfully fold signals up to 1 kHz. Note that none of the existing hardware shows such high frequency response.
    \item Our hardware prototype is designed to operate prior to the sampler unlike the hardware in  \cite{krishna2019unlimited} which operates in the hold part of the sampler. Hence, it can use faster ADCs with smaller hold time.
    \item Modulo folding is realized through a feedback mechanism. The time instants at which the input signal goes beyond the ADC's dynamic range, a trigger signal is generated by using a set of comparators. The trigger then activates a direct-current (DC) generator that adds to the input signal to bring it to stay within the dynamic range. This feedback mechanism introduces a finite time delay between the trigger and addition which causes part of the input signal to stay beyond the dynamic range.
    We address this key issue of the hardware which was not considered in the previous works.
    By using the amount of smoothness of the signal and time delay of the feedback loop we show that by changing the thresholds of compactors the delay issue can be mitigated. Importantly, by using tunable threshold voltages at the comparators, time delay issues can be resolved for signals with different bandwidths.
    \item To show that application of the hardware, we consider sampling and reconstruction of FRI signals. We use a lowpass filter (LPF) kernel prior to modulo system and sampler. The filter removes unwanted information in the signal and allows sub-Nyquist sampling. The filtered signal is folded by the designed hardware and then sampled. For estimating the FRI parameters, the samples are first unfolded by using our algorithm presented in \cite{eyar_moduloicassp} and then the parameters are estimated by using annihilating filter approach. By using the fact that our algorithm operates at lowest possible rate, we show that FRI parameters can be estimated sub-Nyquist samples. In particular, we show that the system operates at five times the rate of innovation which is much lower than the Nyquist rate of the signal.
\end{itemize}
The hardware prototype can be used in low-power time-of-flight applications such as handheld ultrasound devices.

The paper is organized as follows. In the next section, we discuss the FRI signal model and its sampling and reconstruction framework in the presence of modulo hardware. In Section III, we present the actual hardware system by explaining its working principle and discussing the components of the system. In Section IV, we show the signal folding and reconstruction abilities of the hardware, and then the conclusion is followed.

\section{Signal Model and System Description}
In this section, we first introduce the FRI signal model and then discuss its sampling and reconstruction framework with modulo ADC.
\subsection{FRI Signal Model}
Consider an FRI signal consisting of stream of $L$ pulses:
\begin{align}
	f(t) = \sum_{\ell=1}^L a_\ell h(t-t_\ell),
	\label{eq:fri1}
\end{align}
where the pulse $h(t)$ a real-valued known pulse. We assume that $a_\ell$s are real-valued and $t_\ell \in (0, T_0] \subset \mathbb{R}$ for a known $T_0$.

The FRI signal model in \eqref{eq:fri1} is encountered in several scientific applications such as radar imaging \cite{bar_radar, bajwa_radar, sunil}, ultrasound imaging \cite{eldar_sos,eldar_beamforming,mulleti_icip}, light detection and ranging (LIDAR) \cite{castorena_lidar}, time-domain optical-coherence tomography (TDOCT) \cite{blu_oct}, and other time-of-flight imaging systems. In these applications,  $h(t)$ is the transmitted pulse and $\{a_\ell \,h(t-t_\ell)\}_{\ell=1}^{L}$ constitute the reflections from $L$ point targets. The amplitudes $a_\ell$s depend on the sizes of the targets and the delays $t_\ell$s are proportional to the distances of the targets from the transmitter. Here $T_0$ denotes maximum time delay of the targets. The signal $f(t)$ is specified by $\{a_\ell, t_\ell\}_{\ell=1}^L$ and can be reconstructed from its sub-Nyquist measurements acquired using an appropriate sampling kernel \cite{vetterli,eldar_sos,fri_strang, mulleti_kernal}. The reconstruction is generally carried out in frequency domain as discussed next.

\subsection{Fourier-Domain Reconstruction}
Consider uniform samples of continuous-time Fourier transform of $f(t)$ given as
\begin{align}
	F(k \omega_0) = \int f(t) e^{-\mathrm{j} k\omega_0 t} \mathrm{d}t = H(k \omega_0) \sum_{\ell = 1}^L a_\ell \, e^{-\mathrm{j} k\omega_0 t_\ell},
	\label{eq:F}
\end{align}
for $k \in \mathcal{K}$ where $H(\omega)$ is the Fourier transform of $h(t)$ and $\mathcal{K}$ is a set integers. In \eqref{eq:F}, $\omega_0>0$ denotes sampling interval in the frequency domain. Next, consider the following samples
\begin{align}
	S(k\omega_0) = \frac{F(k\omega_0)}{H(k\omega_0)} =  \sum_{\ell = 1}^L a_\ell \, e^{-\mathrm{j}k\omega_0 t_\ell},
	\label{eq:Skomega}
\end{align}
where we assume that $H(k \omega_0) \neq 0$ for $k \in \mathcal{K}$. In practice, the pulse $h(t)$ has small time support and hence, large bandwidth. Hence, for a finite set $\mathcal{K}$ it is possible to choose a set of frequencies $\{k \omega_0\}_{ k \in \mathcal{K}}$ such that $H(k \omega_0) \neq 0$ for $k \in \mathcal{K}$. It can be shown that $2L$ consecutive samples of $S(k\omega_0)$ are sufficient to uniquely identify $\{a_\ell, t_\ell\}_{\ell=1}^L$ if $\omega_0 = \frac{2\pi}{T_0}$ \cite{eldar_2015sampling}. In practice, high-resolution spectral estimation methods, such as the annihilating filter (AF) or Prony's method and its variants \cite{prony, plonka}, multiple signal classification \cite{schmidt_music, barabell_rmusic, bdrao_rmusic}, matrix-pencil method \cite{sarkar_mp}, estimation of signal parameter via rotational invariance technique (ESPRIT) \cite{paulraj_esprit}, etc. have been deployed for FRI parameter estimation.

Since $h(t)$ is known, $H(k\omega_0), k \in \mathcal{K}$ can be calculated in advance. Hence, to compute $S(k\omega_0), k \in \mathcal{K}$ and then estimate FRI parameters, $F(k\omega_0), k \in \mathcal{K}$ has to be determined. Next, we discuss a lowpass filter (LPF) based sampling framework to determine these Fourier samples.

\subsection{LPF-Based Sub-Nyquist Sampling}
\label{sec:lpf}
In this section, we discuss a LPF-based sampling mechanism for FRI signals. Let $g(t)$ denotes an ideal lowpass filter with cutoff frequency $\omega_c$ rad/sec. In the frequency-domain we have that $G(\omega) = 1$ for $\omega \in [-\omega_c, \omega_c]$ and zero for the rest of the frequencies. Let $y(t)$ denotes response of the LPF to the input $f(t)$, that is, $y(t) = (f*g)(t)$, where $*$ denotes linear convolution operation. Consider an ADC with dynamic range $[-\lambda, \lambda]$ and sampling rate $\omega_s = \frac{2\pi}{T_s}$ rad/sec. By assuming that  $\|y(t)\|_{\infty}\leq \lambda$, uniform samples at the output of ADC are given as $y(nT_s), n \in \mathbb{Z}$. Then uniform measurements of discrete-time Fourier transform (DTFT) of the samples are given as
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) = \sum_{n \in \mathbb{Z}}y(nT_s)\,e^{\mathrm{j} k\omega_0 n T_s}, \quad k \in \mathcal{K}.
	\label{eq:y_dtft}
\end{align}
By using relationship between DTFT of samples $y(nT_s)$ and CTFT of $y(t)$ we have
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) &= \frac{1}{T_s}\sum_{m \in \mathbb{Z}} Y(k\omega_0 + m \omega_s), \nonumber \\
	&= \frac{1}{T_s}\sum_{m \in \mathbb{Z}} F(k\omega_0 + m \omega_s) \,G(k\omega_0 + m \omega_s),
		\label{eq:y_dtft2}
\end{align}
where we used the fact that $Y(\omega) = F(\omega)\,G(\omega)$. Next, consider the following conditions on the sampling rate and cutoff frequency of the filter
\begin{align}
	\omega_s \geq 2\omega_c, \quad \text{and} \quad \omega_c \geq K \omega_0,
	\label{eq:sampling_rate}
\end{align}
where $K \geq L$. Then by choosing $\mathcal{K} = \{-K, \cdots, K\}$, \eqref{eq:y_dtft2} can be written as
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) = F(k\omega_0), \quad k \in \mathcal{K},
	\label{eq:y_dtft3}
\end{align}
where we used the fact that $G(k\omega_0) = 1$ in these settings. The relationship \eqref{eq:y_dtft3} shows that the desired Fourier samples of $f(t)$ are determined from the samples of LPF by assuming that the conditions in \eqref{eq:y_dtft2} are satisfied. Hence, FRI parameters can be determined from the samples of the lowpass filter.

The bandwidth of the pulse $h(t)$ and hence that of the FRI signal $f(t)$ could be very large. But the sampling rate $\omega_s$ is independent of the pulse and could be much smaller than its bandwidth which shows the FRI signal could be reconstructed from sub-Nyquist samples.

The sub-Nyquist sampling framework discussed assumes that $\|y(t)\|_{\infty}\leq \lambda$, in other words, the framework assumes that the dynamic range of the ADC is greater than that of the signal to be sampled. However, this condition may not be always true. Specifically, the amplitude range of the filtered signal $y(t)$ could be larger than ADC's dynamic range. In such a scenario, a direct sampling would lead to clipping of samples which is undesirable. To avoid clipping, a modulo operator is employed prior to sampling as discussed next.

\begin{figure*}
	\centering
	\includegraphics[width=6.5 in]{Figs/FRI_US}
	\caption{A schematic of modulo-sampling and reconstruction of FRI signals.}
	\label{fig:fri_framework}
\end{figure*}

\subsection{Modulo-Folding}
To avoid clipping, a modulo folding operator $\mathcal{M}_\lambda(\cdot)$ is used after LPF and before the ADC. The operator folds $y(t)$ to stay within ADC's dynamic range $[-\lambda, \lambda]$. The output of the modulo operator in response to input $y(t)$ is given as
\begin{equation}
 y_\lambda(t) =	\mathcal{M}_{\lambda}(y(t)) = (y(t)+\lambda)\,\, \text{mod}\,\, 2\lambda -\lambda.
	\label{eq:mod_opp}
\end{equation}
The folded signal is then sampled by the ADC to have measurements $y_\lambda(nT_s)$. Since modulo folding is a nonlinear operation, one can not directly apply DTFT on the samples to compute Fourier measurements of the FRI signal for its reconstruction. Hence, the true or unfolded samples $y(nT_s)$ are estimated from the folded ones $y_\lambda(nT_s)$ by applying an unfolding algorithm. There exist several unfolding methods for bandlimited signals such as $y(t)$ \cite{uls_tsp, uls_romonov,eyar_moduloicassp}.
The sampling rate for unfolding varies for different algorithms and generally, is larger than the minimum sampling rate required for FRI signal recovery (cf. \eqref{eq:sampling_rate}).
Hence, the overall system operates on a higher sampling rate than that without a modulo case. However, if the overall sampling rate is much lower than the bandwidth of the FRI signal then the system operates at a sub-Nyquist rate. We show that this is indeed true when we apply our unfolding algorithm proposed in \cite{eyar_moduloicassp}.

An end-to-end modulo sampling framework for FRI signal sampling and reconstruction is shown in Fig.~\ref{fig:fri_framework}. The sampler or ADC together with the modulo block is termed as modulo-ADC.
Modulo-ADCs are able to sample signals beyond their dynamic range without clipping and hence they are termed as high-dynamic range ADCs. Alternatively, an ADC with a  much lower dynamic range can be used to sample signals with larger amplitudes. Sub-Nyquist sampling and low-dynamic range requirements significantly reduce the power consumption and cost of the ADC.

The modulo folding block is key component of the high-dynamic range ADC and we discuss its hardware implementation in the next section.

\begin{figure}
	\centering
	\includegraphics[width= 3 in]{Figs/folding}
	\caption{Folding principle}
	\label{Fig:folding}
\end{figure}
\section{Modulo Hardware Prototype}
In this section, we discuss our modulo hardware prototype. First, we explain the working principle of the modulo block and explain how its design and then discuss the hardware realization.
\subsection{Working Principle of Modulo Block}
Principle of computing $y_\lambda(t)$ from $y(t)$ is shown by block-diagram in Fig.~\ref{Fig:folding}. The system comprises of an adder $S$, a direct-current voltage generator (DC-VG), and two comparators $C_1$ and $C_2$. To understand the working let us first assume that for some time instant $t_1$, we have that $|y(t)|<\lambda$ for $t<t_1$. Hence $y_\lambda(t) = y(t)$ and $z(t) = 0$ for $t<t_1$. At $t=t_1$, let $|f(t)|$ crosses $\lambda$. If $f(t_1)>0$, then the comparator $C_1$ triggers a positive value or else, $C_2$ triggers a negative value. The DC-VG is designed such that for every positive value input it reduces its output signal level by $-2\lambda$, whereas, for negative value it increases its output voltage by $2\lambda$. Hence, in the current example, DC-VG generates signal $z(t) = \text{sgn}(y_\lambda(t_1)) 2\lambda u(t-t_1)$ where $u(t)$ is unit-step function.
In this way by adding or subtracting (by using $S$) constant DC signals from $f(t)$ whenever it crosses dynamic range $[-\lambda, \lambda]$, the amplitude levels of $f_\lambda(t)$ are kept within ADC's dynamic range.

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3 in]{Figs/dc_vg}
	\caption{DC-VG}
	\label{Fig:dcvg}
\end{figure}

\begin{figure*}[!t]
	\centering
	\includegraphics[width=5 in]{IEEE_TAES_v1/Figs/UDR_Board_Labeled3.PNG}
	\caption{Modulo Hardware Board.}
	\label{Fig:hw_board}
\end{figure*}
\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[]{\includegraphics[width=2.5in]{Figs/UDRPhase2pictures500Hz}\label{fig:500_2}} \\
		\subfigure[]{\includegraphics[width=2.5in]{Figs/UDRPhase2pictures2KHz}\label{fig:2k_2}}
	\end{tabular}
	\caption{Analysis of folding ability of the modulo hardware.}
	\label{Fig:two_fold}
\end{figure}

\begin{figure}[!h]
	\centering
	\begin{tabular}{c}
		\subfigure[]{\includegraphics[width=2.5in]{Figs/500Hz}\label{fig:500_1}} \\
		\subfigure[]{\includegraphics[width=2.5in]{Figs/1KHz}\label{fig:1k_1}} \\
		\subfigure[]{\includegraphics[width=2.5in]{Figs/5KHz}\label{fig:5k_1}}
	\end{tabular}
	\caption{Analysis of frequency response of the modulo hardware.}
	\label{Fig:frequency_response}
\end{figure}

\begin{table}[h!]
		\caption{Folding Operation.}
	\centering
	\begin{tabular}{||c c c c c ||}
		\hline
		c & b & a & sgn & Counter values \\ [0.5ex]
		\hline\hline
		0 & 0 & 0 & 0~(1) & 0~(0) \\
		0 & 0 & 1 & 0~(1) & 1~(-1) \\
		0 & 1 & 0 & 0~(1) & 2~(-2) \\
		0 & 1 & 1 & 0~(1) & 3~(-3) \\
		1 & 0 & 0 & 0~(1) & 4~(-4) \\
		1 & 0 & 1 & 0~(1) & 5~(-5)\\
		1 & 1 & 0 & 0~(1) & 6~(-6)\\
		1 & 1 & 1 & 0~(1) & 7~(-7)\\
		\hline
	\end{tabular}
	\label{table:counter}
\end{table}
While the parts such as comparators $C_1$, $C_2$, and adder $S$ can be realized by using off-the-shelf components, DC-VG is a more involved system and required careful design. A detailed architecture of DC-VG is shown in Fig.~\ref{Fig:dcvg}. It consists of an up/down counter, a digital-to-analog converter (DAC), a multiplexer (MUX), and a multiplier $M$.  The role of the counter (together with DAC) is to generate a variable, but controlled, DC voltage whenever there is a trigger at its input. The voltage values are set to be multiple of $2\lambda$ by using the MUX and multiplier $M$.
To elaborate the working principle, we first discuss the role of the counter and then the rest of the components.

In this particular system, we use a three-bit synchronous up/down converter. The bits from lower significant bit to higher significant bit are denoted as a, b, and c. The counter has an additional sign bit shown as sgn. With these bits, the counter can count from -7 to 7. For every positive trigger at the input, the output counts up and with a negative trigger it counts down. In Table~\ref{table:counter}, we display the values of bits and the counter (denoted as counter values). The three bits (a,b, and c) of the counter are used as input to the DAC which converts the bits to analog DC voltages. Let the resolution or step size of the DAC is $\alpha$ then the output of DAC is $\alpha$ times the counter-value. To be more specific, consider the scenario where the output of counter and DAC are zero. Then for a positive (negative) trigger, the output of DAC increases (decreases) by $\alpha$. Specifically, the output of DAC, $s(t)$, is a piecewise constant signal with values that are multiples of $\alpha$. However, for folding to work, the change in the voltage should be in multiples of $2\lambda$. To ascertain that we use a MUX which outputs either $2\lambda$ or $-2\lambda$ depending on whether its input is 1 or 0. Then by multiplying the output of DAC with the output of MUX we generate $z(t)$. Next, we discuss the hardware board the realize the folding operation discussed in this section.

\begin{table}[h!]
\centering
\caption{List of Hardware Components}
\label{table:hardware_components}
\begin{tabular}{||c c c||}
 \hline
 Component & Model Number & Make \\
 && \\ \hline
 Comparator & LM339 & Texas Instruments \\
 && \\
 UP/DOWN Counter & TEENSY4.1 & PJRC \\
 && \\
 DAC 3bits & LT1364 & Analog Devices \\
 && \\
 Analog MUX & ADG1608 & Analog Devices \\
 && \\
 Analog Multiplier & AD835 & Analog Devices \\
 && \\
 Adder & LT1364 & Analog Devices \\
  && \\ [1ex]
\hline
\end{tabular}
\end{table}
\subsection{Modulo Hardware Board}
Our modulo hardware board is shown in Fig.~\ref{Fig:hw_board} with main role of the various building components are marked. The details of the components of the hardware are listed in Table~\ref{table:hardware_components}. The board is designed for $\lambda \leq 1.25$ volts. The board can accommodate an input signal with a dynamic range between $[-4\lambda, 4\lambda]$ which implies that an ADC with our modulo hardware can sample four-times larger signals compared to its dynamic range without saturation and clipping.

We demonstrate working of the modulo hardware by considering sinusoidal signal $y(t) = A\, \sin(2\pi f_0 t)$ where $A$ is amplitude and $f_0$ is frequency (in Hz). In this experiment, we set $\lambda = 1.25$ and $3\lambda <A <4\lambda$. With these settings, we expect the signal to fold twice in a quarter cycle of a sinusoid. Figs.~\ref{Fig:two_fold}(a) and \ref{Fig:two_fold}(b) screenshots of an oscilloscope capturing input $y(t)$ (in yellow) and its folded output $y_\lambda(t)$ (in green) for $f_0 = 500$ Hz and $f_0 = 2$ kHz, respectively. We observed that the signals are folded back to lie within the dynamic range of the ADC as expected without clipping. The reason we choose two different frequencies is to study the frequency response of the modulo folder. As in any analog system, the response of the modulo folder too depends on the frequency or bandwidth of the input signal. Beyond a particular frequency, the foldings may not be accurate as observed in Fig.~\ref{Fig:frequency_response}. We observed that for signals of 500 Hz and 1kHz the hardware is able to fold the signal accurately. However, for $f_0 = 5$ kHz, folding instants are not symmetric for positive and negative folds. In the next section, we discuss a couple of inaccuracies of the modulo hardware and our proposed solution to overcome those.

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3.2 in]{Figs/mod_td}
	\caption{Effect of time delay of the feedback loop on the modulo operation.}
	\label{Fig:mod_td}
\end{figure}

\subsection{Artifacts During Folding}
Errors or other artifacts that arise during folding operation in hardware could be due to various reasons. For example, in Figs.~\ref{Fig:two_fold} and \ref{Fig:frequency_response}, we observe that the amplitude of the folded signals could go beyond the dynamic range momentarily around the folding instants. This is due to the settling time of the DC-VG when voltage values change. Specifically, after switching, the voltage at the output of DC-VG overshoots and undershoots before the oscillations settle down to the expected value. This can be overcome by using a faster adder whose response time should be at least a magnitude higher than the sample rate.

Another major issue that arises in a folding ADC is a time delay in the feedback loop (See Fig.~\ref{Fig:folding}). To elaborate, consider a scenario where $y(t)<\lambda$ for $t<t_1$ and it crosses $\lambda$ at time $t_1$ as discussed earlier. To fold the output voltage to the dynamic range of the ADC, $z(t) = -2\lambda u(t-t_1)$ needs to be added to $y(t)$. However, there is a finite delay between the trigger time $t_1$ to generating $z(t)$. If the time delay is $T_d$, then $z(t) = -2\lambda u(t-t_1-T_d)$ is added which causes distortion. To illustrate this effect in Fig.~\ref{Fig:mod_td} by considering a sinusoidal signal (in blue) and its folded versions with and without delay. We observe that in the absence of any time delay ($T_d=0$) the signal folds perfectly (shown in red) to stay within the dynamic range. However, for a non-zero value of $T_d$, foldings do not take place at the folding instants and the output of the modulo operator (shown in black) still remains outside the dynamic range $[-\lambda, \lambda]$. We propose a hardware solution to address this issue.

Out solution uses the fact that with a finite time delay, the amount of overshoot of a smooth signal can be bounded. To elaborate, let us assume that the signal that undergoes modulo operation is Lipschitz continuous. Specifically, a signal $y(t)$ is Lipschitz continuous if there exists a positive real number $\mathrm{L}_y$ such that for any $T>0$ we have
\begin{align}
    |y(t) -y(t+T)|\leq \mathrm{L}_y\, T.
    \label{eq:lipschitz}
\end{align}
With the Lipschitz smoothness condition, we note that the amplitude of $y(t)$ can not change more than $\mathrm{L}_y\, T_d$ between any folding instant and time of its effect to take place. Hence, if we choose dynamic range of the ADC to be $[-(\lambda+\Delta \lambda), (\lambda+\Delta \lambda)]$ where $\Delta \lambda = \mathrm{L}_y\, T_d$ then the signal will not clip. We show this extended dynamic region in the illustrative example in Fig.~\ref{Fig:mod_td}. Alternatively, instead of increasing ADC's dynamic range, one can keep it to be $[-\lambda, \lambda]$ and reduce the threshold values for comparators. In this case, $C_1$ will trigger when the input crosses $\lambda-\Delta \lambda$ and $C_2$ will trigger when input goes beyond $-\lambda+\Delta \lambda$. In this way, the time delay issue is addressed by the modulo circuit without altering ADC's dynamic range.

To implement the mentioned solution, the signal should be Lipschitz continuous. In our setup, the input to modulo operation is a lowpass or bandlimited signal which always satisfies the Lipschitz smoothness condition \cite{bl_bound}. For a bandlimited signal $y(t)$ its Lipschitz constant $\mathrm{L}_y$ is directly proportional to its bandwidth $\omega_c$ which is the same as the cutoff frequency of the LPF.
Hence, for a given value $\Delta \lambda$ and $T_d$ (both depend on the modulo circuit), $\mathrm{L}_y = \Delta \lambda/T_d$ is fixed and this restricts the maximum frequency of the input signal that can be faithfully folded. In the current design, we chose to implement the counter management by a TEENSY micro-controller which results in a time delay of $1 \mu$s which enable the hardware to support a wide range of frequencies with no need to modify the hardware components. In order to support higher frequencies, alternative design strategies with a faster response time and lower delay should be used.

\section{Results}
In this section, we show the signal reconstruction ability of the modulo hardware described in the previous section. From Fig.~\ref{fig:fri_framework}, we understood that the signal reconstruction ability is a function of LPF $g(t)$, modulo circuit $\mathcal{M}_\lambda(\cdot)$, ADC or sampler, unfolding algorithm, and parameter estimation method. Any error in the estimation of FRI parameters is a result of flaws and limitations of the hardware realizations and limitations of the algorithms in the presence of measurement noise. For example, ideally $g(t)$ should have infinite impulse response, however, only a truncated version could be realizable in hardware. The truncation will result in errors while determining the Fourier samples of the FRI signal (See Section~III.\ref{sec:lpf}). Similarly, quantization plays a role when a finite resolution quantizer is used after the sampler. In addition, all the hardware components contribute to different types of noise. We model all these noises and inaccuracies as additive noise at the output of the sampler. Specifically, the noisy measurements are given as
 \begin{align}
            \tilde{y}_{\lambda}(n T_s) = {y}_{\lambda}(n T_s) + v(n T_s),
        \label{eq: noisy_samples}
        \end{align}
where $v(n T_s)$ is the noise term. Both unfolding and parameter estimation algorithms should be robust to different noise models. The robustness of parameter estimation methods in the presence of noise is well studied (See \cite{mulleti_kernal, stoica, eldar_sos}). In \cite{eyar_moduloicassp}, we presented comparisons of unfolding algorithms for bandlimited signals. We showed that our beyond-bandwidth residual recovery ($B^2R^2$) approach results in lower error during unfolding compared to the \emph{higher-order differences} (HOD) approach \cite{unlimited_sampling17, uls_tsp} and \emph{Chebyshev polynomial filter}-based (CPF) method \cite{uls_romonov}. Importantly, for a given sampling rate, $\lambda$, and signal to noise ratio (SNR), $B^2R^2$ method results in the lowest error for both bounded and unbounded noise models.

Before presenting hardware results, we compare the performances of the $B^2R^2$ method with HOD and CPF approaches for quantization noise and unbounded noise. We would like to point out that quantization noise was not considered in \cite{eyar_moduloicassp}. Although, the algorithms were compared for unbounded noise but the simulation settings were different than those in our hardware. Hence, for a better understanding, we compared our algorithm for unbounded noise and quantizaition  noise with the current hardware settings. In the next section, we present these simulation results and then present hardware results.

\begin{figure}[!t]
	\centering
	\includegraphics[width= 2.5 in]{IEEE_TAES_v1/Figs/quantization.png}
	\caption{Comparison of HOD, CPF and $B^2R^2$ algorithms after the quantization process in terms of MSE when recovering a bandlimited signal from modulo samples with $\lambda = 1.25$ and OF = 3,6. For a given number of bits, $B^2R^2$ has the lowest MSE.}
	\label{Fig:quantization}
\end{figure}

\begin{figure}[!t]
	\centering
	\includegraphics[width= 2.5 in]{IEEE_TAES_v1/Figs/Gaussian.png}
	\caption{Comparison of HOD, CPF and $B^2R^2$ algorithms (with unbounded noise) in terms of MSE when recovering a bandlimited signal from modulo samples with  $\lambda$ = 1.25 and OF = 3,6. For a given SNR and OF, $B^2R^2$ has lowest MSE.}
	\label{Fig:unbounded}
\end{figure}
\subsection{Simulated Results}
In this section, we compare our $B^2R^2$ algorithm with the \emph{higher-order differences} (HOD) approach \cite{unlimited_sampling17, uls_tsp} and \emph{Chebyshev polynomial filter}-based (CPF) method \cite{uls_romonov}. We consider the noise measurements as in \eqref{eq: noisy_samples} for a simulation data. In the simulations, $\lambda$ is set to be $1.25$ as in the hardware. We normalize the bandlimited signals to have maximum amplitude of $10$. The SNR is calculated as $\text{SNR} = 20 \log\left(\frac{||y_{\lambda}(n T_s)||}{||v(n T_s)||}\right)$. The reconstruction accuracy of different methods is compared in terms of normalized mean-squared error (MSE) as $ \frac{\sum |y(nT_s) - \hat{y}(n Ts)|^2}{\sum |y(nT_s)|^2}$, where $\hat{y}(n T_s)$ estimate of $y(n T_s)$. For different noise settings and over-sampling factors (OFs), we considered 100 independent noise realizations and calculated the average MSE for them. We first consider quantization noise and then present results for unbounded noise.

\begin{figure}[!t]
    \centering
    \includegraphics[width=0.3\textwidth]{IEEE_TAES_v1/Figs/Signal Generator.png}
    \caption{Bandlimited signal generator.}
    \label{fig:UDRSignalGen}
\end{figure}

 First, we consider an uniform quantizer after the sampling. The unfolding algorithms are applied on the quantized samples. The MSE in the estimation of bandlimited signals for a different number of bits and OFs is shown in Fig. ~\ref{Fig:quantization}. We observe that for a given $\text{OF}$, $B^2R^2$ algorithm results in the lowest MSE for less than 5 bits. For more than 5 bits all the algorithms, except HOD with OF = 3, perform equally well. The results show that low-resolution quantizers can be used with $B^2R^2$ algorithm for unrolling which saves both power and memory requirements.

Next, for unbounded noise, we assume that the noise measurements $v(nT_s)$ are independent and identically distributed Gaussian random variables with zero mean. The variance is set to achieve a desired SNR. We compare the methods for different values of SNR and OFs with $\lambda = 1.25$. Fig.~\ref{Fig:unbounded} shows MSE of the different algorithms for OF $= 3$ and $6$. We note that our algorithm results in lowest error for a given OF and SNR.

Given the advantages of $B^2R^2$ algorithm over the other approaches, we present the hardware results in the next section by using this method.

\begin{figure*}[!t]
	\centering
	\begin{tabular}{cc}
		\subfigure[]{\includegraphics[width=2.5in]{IEEE_TAES_v1/Figs/BL1_rec.png}\label{fig:BL1}} &
		\subfigure[]{\includegraphics[width=2.5in]{IEEE_TAES_v1/Figs/BL2_rec.png}\label{fig:BL2}}
	\end{tabular}
	\caption{Hardware results for bandlimited signals. The $B^2R^2$ algorithm is used to unfold $y_\lambda(t)$ (measured at the output of hardware) and the unfolded signal $\hat{y}(t)$ is plotted with bandlimited signal $y(t)$.}
	\label{fig:BL_ex1}
\end{figure*}

\begin{figure*}[!t]
	\centering
	\begin{tabular}{ccc}
		\subfigure[]{\includegraphics[width=2.2in]{IEEE_TAES_v1/Figs/Ex1_lpf.pdf}\label{fig:FRI11}} &
		\subfigure[]{\includegraphics[width=2.1in]{IEEE_TAES_v1/Figs/Ex2_lpf.pdf}\label{fig:FRI12}}&
		\subfigure[]{\includegraphics[width=2.1in]{IEEE_TAES_v1/Figs/Ex3_lpf.pdf}\label{fig:FRI13}}\\
		\subfigure[]{\includegraphics[width=2.1in]{IEEE_TAES_v1/Figs/Ex1_fri.pdf}\label{fig:FRI21}} &
		\subfigure[]{\includegraphics[width=2.1in]{IEEE_TAES_v1/Figs/Ex2_fri.pdf}\label{fig:FRI22}}&
		\subfigure[]{\includegraphics[width=2.1in]{IEEE_TAES_v1/Figs/Ex3_fri.pdf}\label{fig:FRI23}}
	\end{tabular}
	\caption{Hardware results for FRI signals: Top row shows three examples of lowpass filtered FRI signals $y(t)$, modulo outputs $y_\lambda(t)$, and unfolded signals $\hat{y}(t)$; bottom row shows true FRI signal $f(t)$ and its estimate $\hat{f}(t)$.}
	\label{fig:FRI_ex}
\end{figure*}

\subsection{Hardware Results}
In this section, we present results from the hardware.
Since bandlimited signals are input to the hardware , we fist present results for them and then show results for FRI signals. If the hardware and unfolding algorithm is able to recover the bandlimited signals with high accuracy than it will leads to better reconstruction of the FRI signals. In all these experiments we set $\lambda = 1.25$ V and the cutoff frequency of the lowpass filter is 1 kHz. We observe that for frequencies less than or equal to 1 kHz, out hardware is able to reliably fold the signal. The Nyquist rate of the signal is 2 kHz. But for unfolding we need to oversample the signal. In all these experiments, we used $B^2R^2$ algorithm with OF = 5 which results in sampling rate of 10 kHz. Further, $y(t)$ and $y_\lambda(t)$ are measured from the hardware through an oscilloscope for processing by the algorithms.

We first consider the bandlimited signals. For generating bandlimited or lowpass signals we used a Arduino micro-controller (See Fig.~\ref{fig:UDRSignalGen}) which convert the digital signal to an analog signal via a DAC. The digital signals were generated using MATLAB software. In Fig.~\ref{fig:BL_ex1}, we show folding and reconstruction of two bandlimited signals. These signals have maximum amplitude of 5 V. We observe the signals are restricted to $[-\lambda, \lambda]$ by the modulo hardware and the algorithm was able to recover the true signal from the folded samples. The reconstructed signal has slightly larger amplitude compared to the true signal which is result of scaling within the hardware.

Next, we consider reconstruction of FRI signals from modulo samples. To generate the FRI signals, we consider $h(t)$ to be a sort pulse of bandwidth 30 kHz (Nyquist rate = 60 kHz). We consider three examples with $L=2, 3,$ and 5. The amplitudes and time delays are generated randomly. The maximum time delay is $T_0 = 0.1$ sec. Once generated, the FRI signal is lowpass filtered with a cutoff frequency of 1 kHz. Up to filtering operation, MATLAB is used and then Arduino micro-controller is used to generate the analog version of the filtered FRI signals. The signal is then folded using the hardware and folded signals are sampled. The sampling rate is 10 kHz which is five times higher than the sampling rate of the lowpass signal. Still the rate is six times lower than the Nyquist rate and hence the system operates at sub-Nyquist rate. The setup satisfies the conditions in \eqref{eq:sampling_rate} for $L=2, 3,$ and 5.

We first apply $B^2R^2$ algorithm to unfold the signal and then used ESPRIT \cite{paulraj_esprit} to estimate the time delays and amplitudes of the FRI signals. We show FRI signal sampling and reconstruction in Fig.~\ref{fig:FRI_ex} where the top row shows LPF output $y(t)$, folded signal (output of the modulo hardware) $y_\lambda(t)$, and unfolded signals $\hat{y}(t)$. The bottom row shows location and amplitude of the true signal $f(t)$ and estimated FRI signal $\hat{f}(t)$. The maximum error in the estimation of time delay $-15$ dB which shows that the system can be used in applications like radar and ultrasound imaging.

\section{Conclusions}
We considered the problem of recovering FRI signals from low-pass filtered, modulo samples. We presented a hardware prototype for the modulo folding system and show that for different bandlimited and FRI signals, the hardware is able to faithfully fold the signal. We also  address the time delay issue of the modulo system and presented a hardware solution for the same. The overall system operates at six times below the Nyquist rate which enables one to use low rate, low-dynamic range, power efficient ADCs.

\bibliographystyle{IEEEtaes}

\section{INTRODUCTION}
Sampling plays a key role in efficiently processing real-world analog signals on digital signal processors. Analog to digital converters (ADCs) are used to implement sampling in the hardware. A key parameter of an ADC is its sampling rate. ADCs with high sampling rates are power-consuming and expensive, making them unsuitable for portable devices such as hand-held ultrasound devices. Hence, it is desirable to reduce the sampling rate. Signals with finite rate of innovation (FRI) have few degrees of freedom which aids in sub-Nyquist sampling \cite{eldar_2015sampling}. That is, signal is sampled at a rate much lower than the Nyquist rate \cite{shannon, nyquist} and hence low power ADCs could be used. FRI model is ubiquitous in several time of flight applications \cite{bajwa_radar, bar_radar,filho201seismic,rip,carter_sonar,eldar_sos,eldar_beamforming, sunil} where the signal of interest consists of a linear combination of delayed copies of a known pulse. Thus, the desired information lies in the amplitudes and time delays of the pulse, which amounts to a few degrees of freedom.

Most existing works in the context of FRI sampling focus on reducing the ADC's sampling rate by using the signal structure \cite{vetterli, eldar_sos, fri_strang, blu_moms, mulleti_kernal} and ignores other aspects of the ADC.
The dynamic range of an ADC to plays a crucial role in sampling an analog signal. ADC's dynamic range should generally be larger than the signal's; otherwise, the signal is clipped. A few approaches exist to recover the true samples from clipped ones for bandlimited signals \cite{marks_clipping2, marks_clipping1}. These approaches rely on the correlation among the samples when they are measured at a very high rate compared to the Nyquist rate. The requirement of a high sampling rate is a drawback of these approaches. In addition, theoretical guarantees are missing, and it is unclear how many clipped samples can be recovered.

There are several preprocessing approaches such as automatic gain control (AGC) \cite{perez2011automatic,mercy1981review}, companding \cite{landau_compander,landau_distorted_bl}, and modulo folding \cite{uls_tsp,uls_romonov,uls_sparse,bhandari2021unlimited,eyar_moduloicassp}, that can be used prior to sampling to avoid clipping. Among these, modulo folding is most recent approach that need not be differentiable like companding and does not suffer from stability issues of the feedback amplifiers used in AGC. In the modulo framework, the signal is folded to lie within ADC's dynamic range and then the folded signal is sampled by using a conventional ADC. Theoretical guarantees for recovering bandlimited signals from folded samples are presented in \cite{uls_tsp,uls_identifiability}. The results states that the bandlimited signals can be uniquely recovered from folded samples provided that they are sampled above the Nyquist rate.

Several algorithms for \emph{unfolding} or recovering the true samples of bandlimited signals from modulo or folded samples are presented in \cite{uls_tsp,uls_romonov, eyar_moduloicassp}. These unfolding algorithms can be compared in terms of sampling rate, amount of unfolding they can handle, and noise robustness. It is shown that the method proposed in \cite{eyar_moduloicassp} has lowest reconstruction error for a given sampling rate, noise level, and signal's amplitude level compared to the algorithms presented in \cite{uls_tsp,uls_romonov}. The algorithm proposed in \cite{uls_tsp} requires almost 17-times higher sapling rate than the Nyquist rate but it is independent of the dynamic range of the ADC. Whereas, the approaches in \cite{uls_romonov, eyar_moduloicassp} requires the knowledge of ADC's dynamic range. Modulo sampling is also extended to different problems and signal models such as periodic bandlimited signals \cite{bhandari2021unlimited}, wavelets \cite{uls_wavelet}, mixture of sinusoids \cite{uls_sinmix}, finite-rate-of-innovation signals \cite{uls_fri}, multi-dimensional signals \cite{uls_md}, sparse vector recovery \cite{uls_gamp, uls_sparsevec}, direction of arrival estimation problem \cite{uls_doa}, computed tomography \cite{uls_radon}, and graph signals \cite{uls_graph}.

While theoretical guarantees and algorithms of any new sampling approach are always well researched but the question of whether they work in practice is always difficult to answer. For modulo sampling, there exists a few hardware prototypes. For example, high-dynamic-range ADCs, also known as \emph{self-reset} ADCs, are discussed in the context of imaging \cite{sradc_park, sradc_sasagwa, sradc_yuan, krishna2019unlimited}. These hardware architectures measure additional information such as the amount of folding for each sample, or, the sign of the folding together with the folded samples. The additional information might enable simpler recovery but at the expense of complex circuitry. Importantly, additional bits are required during the quantization process to store or transmit the side information.

Krishna et al. presented a hardware prototype which encode the side-information by using two bits \cite{krishna2019unlimited}. The architecture is designed to record sign of the slope of the signal at each sampling instant when the sample lies outside ADC's dynamic range. In a conventional ADC, a sample and hold (S/H) circuit is used to hold the sampled value for a prescribed period of time during which quantization is performed on the sample. To realize the modulo sampling, a folding circuit is used after S/H \cite{krishna2019unlimited}. Hence, the S/H circuit has to hold the sampled value for folding and quantization, which results in a larger folding time compared to a conventional ADC. A large holding time results in slower ADC and hence it may not be useful for wideband application.

The proposed modulo-ADC is able to sample signals beyond its dynamic range while keeping the power dissipation and area requirements lower compared to a conventional ADC \cite{krishna2019unlimited}. A major drawback of this modulo-ADC's architecture is that the modulo operation is performed between the sample and hold (S/H), and quantization blocks of the ADC. Specifically, modulo operation is performed on the hold values of S/H circuit and then the folded sample is quantized. Hence, compared to a conventional ADC, the hold time is relatively high which makes the architecture slower. Modulo hardware prototypes where the modulo part is implemented prior to sampler are presented in \cite{bhandari2021unlimited,Bhandari:2022:J,mod_hyst}. Since the modulo circuit is not part of the hold time, the ADC could be faster than the hardware realization in \cite{krishna2019unlimited}.  In \cite{mod_hyst}, the authors discussed a few implementation issues of modulo hardware such as hysteresis and folding transients, and propose algorithmic solutions to mitigate them. Both these issues can also be addressed by careful calibration and by using high precision components. In \cite{Bhandari:2022:J}, Bhandari showed reconstruction of FRI signals by suing a modulo hardware. In \cite{bhandari2021unlimited,Bhandari:2022:J,mod_hyst}, rather than providing details of the hardware circuitry the authors are focused on different signal models, hardware-limitations, and algorithms. They show that the modulo hardware is able to fold signals which are 10-12 times larger than the ADC's dynamic range. However, not much is discussed about the frequency response of the modulo circuit which too plays a crucial role in the application of these circuits.

In this paper, we present a modulo hardware prototype and show that by using our algorithm \cite{eyar_moduloicassp} it is able to faithfully reconstruct FRI signals.
In the following, we present our contributions and the salient features of our hardware system.
\begin{itemize}
    \item Our main focus during the design phase is to show that the modulo system can fold high frequency signals. To this end we choose our components such that the system can faithfully fold signals up to 1 kHz. Note that none of the existing hardware shows such high frequency response.
    \item Our hardware prototype is designed to operate prior to the sampler unlike the hardware in  \cite{krishna2019unlimited} which operates in the hold part of the sampler. Hence, the proposed system can use faster ADCs with smaller hold time.
    \item Modulo folding is realized through a feedback mechanism. The time instants at which the input signal goes beyond the ADC's dynamic range, a trigger signal is generated by using a set of comparators. The trigger then activates a direct-current (DC) generator that adds to the input signal to bring it to stay within the dynamic range. This feedback mechanism introduces a finite time delay between the trigger and addition operation. The delay has an undesirable effect and it causes a part of the input signal to stay beyond the dynamic range.
    We address this key issue of the hardware which was not considered in the previous works.
    By using smoothness of the signal and time delay of the feedback loop we show that by changing the thresholds of compactors the delay issue can be mitigated. Specifically, by using tunable threshold voltages at the comparators, time delay issues can be resolved for signals with different bandwidths.
    \item To show an application of the hardware, we consider sampling and reconstruction of FRI signals. We use a lowpass filter (LPF) prior to modulo system as a sampling kernel. The filter removes unwanted information in the signal and allows sub-Nyquist sampling. The filtered signal is folded by the designed hardware and then sampled. For estimating the FRI parameters, the samples are first unfolded by using our algorithm presented in \cite{eyar_moduloicassp} and then the parameters are estimated by using annihilating filter approach. By using the fact that our algorithm operates at lowest possible rate, we show that FRI parameters can be estimated sub-Nyquist samples. In particular, we show that the system operates at five times the rate of innovation which is much lower than the Nyquist rate of the signal.
\end{itemize}
The hardware prototype can be used in low-power time-of-flight applications such as handheld ultrasound devices.

The paper is organized as follows. In the next section, we discuss the FRI signal model and its sampling and reconstruction framework in the presence of modulo hardware. In Section III, we present the actual hardware system by explaining its working principle and discussing the components of the system. In Section IV, we show the signal folding and reconstruction abilities of the hardware, and then the conclusion is followed.

\section{Signal Model and System Description}
In this section, we first introduce the FRI signal model and then discuss its sampling and reconstruction framework with modulo ADC.
\subsection{FRI Signal Model}
Consider an FRI signal consisting of stream of $L$ pulses:
\begin{align}
	f(t) = \sum_{\ell=1}^L a_\ell h(t-t_\ell),
	\label{eq:fri1}
\end{align}
where the pulse $h(t)$ a real-valued known pulse. We assume that $a_\ell$s are real-valued and $t_\ell \in (0, T_0] \subset \mathbb{R}$ for a known $T_0$.

The FRI signal model in \eqref{eq:fri1} is encountered in several scientific applications such as radar imaging \cite{bar_radar, bajwa_radar, sunil}, ultrasound imaging \cite{eldar_sos,eldar_beamforming,mulleti_icip}, light detection and ranging (LIDAR) \cite{castorena_lidar}, time-domain optical-coherence tomography (TDOCT) \cite{blu_oct}, and other time-of-flight imaging systems. In these applications,  $h(t)$ is the transmitted pulse and $\{a_\ell \,h(t-t_\ell)\}_{\ell=1}^{L}$ constitute the reflections from $L$ point targets. The amplitudes $a_\ell$s depend on the sizes of the targets and the delays $t_\ell$s are proportional to the distances of the targets from the transmitter. Here $T_0$ denotes maximum time delay of the targets. The signal $f(t)$ is specified by $\{a_\ell, t_\ell\}_{\ell=1}^L$ and can be reconstructed from its sub-Nyquist measurements acquired using an appropriate sampling kernel \cite{vetterli,eldar_sos,fri_strang, mulleti_kernal}. The reconstruction is generally carried out in frequency domain as discussed next.

\subsection{Fourier-Domain Reconstruction}
Consider uniform samples of continuous-time Fourier transform of $f(t)$ given as
\begin{align}
	F(k \omega_0) = \int f(t) e^{-\mathrm{j} k\omega_0 t} \mathrm{d}t = H(k \omega_0) \sum_{\ell = 1}^L a_\ell \, e^{-\mathrm{j} k\omega_0 t_\ell},
	\label{eq:F}
\end{align}
for $k \in \mathcal{K}$ where $H(\omega)$ is the Fourier transform of $h(t)$ and $\mathcal{K}$ is a set integers. In \eqref{eq:F}, $\omega_0>0$ denotes sampling interval in the frequency domain. Next, consider the following samples
\begin{align}
	S(k\omega_0) = \frac{F(k\omega_0)}{H(k\omega_0)} =  \sum_{\ell = 1}^L a_\ell \, e^{-\mathrm{j}k\omega_0 t_\ell},
	\label{eq:Skomega}
\end{align}
where we assume that $H(k \omega_0) \neq 0$ for $k \in \mathcal{K}$. In practice, the pulse $h(t)$ has small time support and hence, large bandwidth. Hence, for a finite set $\mathcal{K}$ it is possible to choose a set of frequencies $\{k \omega_0\}_{ k \in \mathcal{K}}$ such that $H(k \omega_0) \neq 0$ for $k \in \mathcal{K}$. It can be shown that $2L$ consecutive samples of $S(k\omega_0)$ are sufficient to uniquely identify $\{a_\ell, t_\ell\}_{\ell=1}^L$ if $\omega_0 = \frac{2\pi}{T_0}$ \cite{eldar_2015sampling}. In practice, high-resolution spectral estimation methods, such as the annihilating filter (AF) or Prony's method and its variants \cite{prony, plonka}, multiple signal classification \cite{schmidt_music, barabell_rmusic, bdrao_rmusic}, matrix-pencil method \cite{sarkar_mp}, estimation of signal parameter via rotational invariance technique (ESPRIT) \cite{paulraj_esprit}, etc. have been deployed for FRI parameter estimation.

Since $h(t)$ is known, $H(k\omega_0), k \in \mathcal{K}$ can be calculated in advance. Hence, to compute $S(k\omega_0), k \in \mathcal{K}$ and then estimate FRI parameters, $F(k\omega_0), k \in \mathcal{K}$ has to be determined. Next, we discuss a lowpass filter (LPF) based sampling framework to determine these Fourier samples.

\subsection{LPF-Based Sub-Nyquist Sampling}
\label{sec:lpf}
In this section, we discuss a LPF-based sampling mechanism for FRI signals. Let $g(t)$ denotes an ideal lowpass filter with cutoff frequency $\omega_c$ rad/sec. In the frequency-domain we have that $G(\omega) = 1$ for $\omega \in [-\omega_c, \omega_c]$ and zero for the rest of the frequencies. Let $y(t)$ denotes response of the LPF to the input $f(t)$, that is, $y(t) = (f*g)(t)$, where $*$ denotes linear convolution operation. Consider an ADC with dynamic range $[-\lambda, \lambda]$ and sampling rate $\omega_s = \frac{2\pi}{T_s}$ rad/sec. By assuming that  $\|y(t)\|_{\infty}\leq \lambda$, uniform samples at the output of ADC are given as $y(nT_s), n \in \mathbb{Z}$. Then uniform measurements of discrete-time Fourier transform (DTFT) of the samples are given as
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) = \sum_{n \in \mathbb{Z}}y(nT_s)\,e^{\mathrm{j} k\omega_0 n T_s}, \quad k \in \mathcal{K}.
	\label{eq:y_dtft}
\end{align}
By using relationship between DTFT of samples $y(nT_s)$ and CTFT of $y(t)$ we have
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) &= \frac{1}{T_s}\sum_{m \in \mathbb{Z}} Y(k\omega_0 + m \omega_s), \nonumber \\
	&= \frac{1}{T_s}\sum_{m \in \mathbb{Z}} F(k\omega_0 + m \omega_s) \,G(k\omega_0 + m \omega_s),
		\label{eq:y_dtft2}
\end{align}
where we used the fact that $Y(\omega) = F(\omega)\,G(\omega)$. Next, consider the following conditions on the sampling rate and cutoff frequency of the filter
\begin{align}
	\omega_s \geq 2\omega_c, \quad \text{and} \quad \omega_c \geq K \omega_0,
	\label{eq:sampling_rate}
\end{align}
where $K \geq L$. Then by choosing $\mathcal{K} = \{-K, \cdots, K\}$, \eqref{eq:y_dtft2} can be written as
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) = F(k\omega_0), \quad k \in \mathcal{K},
	\label{eq:y_dtft3}
\end{align}
where we used the fact that $G(k\omega_0) = 1$ in these settings. The relationship \eqref{eq:y_dtft3} shows that the desired Fourier samples of $f(t)$ are determined from the samples of LPF by assuming that the conditions in \eqref{eq:y_dtft2} are satisfied. Hence, FRI parameters can be determined from the samples of the lowpass filter.

The bandwidth of the pulse $h(t)$ and hence that of the FRI signal $f(t)$ could be very large. But the sampling rate $\omega_s$ is independent of the pulse and could be much smaller than its bandwidth which shows the FRI signal could be reconstructed from sub-Nyquist samples.

The sub-Nyquist sampling framework discussed assumes that $\|y(t)\|_{\infty}\leq \lambda$, in other words, the framework assumes that the dynamic range of the ADC is greater than that of the signal to be sampled. However, this condition may not be always true. Specifically, the amplitude range of the filtered signal $y(t)$ could be larger than ADC's dynamic range. In such a scenario, a direct sampling would lead to clipping of samples which is undesirable. To avoid clipping, a modulo operator is employed prior to sampling as discussed next.

\begin{figure*}
	\centering
	\includegraphics[width=6.5 in]{Figs/FRI_US}
	\caption{A schematic of modulo-sampling and reconstruction of FRI signals.}
	\label{fig:fri_framework}
\end{figure*}

\subsection{Modulo-Folding}
To avoid clipping, a modulo folding operator $\mathcal{M}_\lambda(\cdot)$ is used after LPF and before the ADC. The operator folds $y(t)$ to stay within ADC's dynamic range $[-\lambda, \lambda]$. The output of the modulo operator in response to input $y(t)$ is given as
\begin{equation}
 y_\lambda(t) =	\mathcal{M}_{\lambda}(y(t)) = (y(t)+\lambda)\,\, \text{mod}\,\, 2\lambda -\lambda.
	\label{eq:mod_opp}
\end{equation}
The folded signal is then sampled by the ADC to have measurements $y_\lambda(nT_s)$. Since modulo folding is a nonlinear operation, one can not directly apply DTFT on the samples to compute Fourier measurements of the FRI signal for its reconstruction. Hence, the true or unfolded samples $y(nT_s)$ are estimated from the folded ones $y_\lambda(nT_s)$ by applying an unfolding algorithm. There exist several unfolding methods for bandlimited signals such as $y(t)$ \cite{uls_tsp, uls_romonov,eyar_moduloicassp}.
The sampling rate for unfolding varies for different algorithms and generally, is larger than the minimum sampling rate required for FRI signal recovery (cf. \eqref{eq:sampling_rate}).
Hence, the overall system operates on a higher sampling rate than that without a modulo case. However, if the overall sampling rate is much lower than the bandwidth of the FRI signal then the system operates at a sub-Nyquist rate. We show that this is indeed true when we apply our unfolding algorithm proposed in \cite{eyar_moduloicassp}.

An end-to-end modulo sampling framework for FRI signal sampling and reconstruction is shown in Fig.~\ref{fig:fri_framework}. The sampler or ADC together with the modulo block is termed as modulo-ADC.
Modulo-ADCs are able to sample signals beyond their dynamic range without clipping and hence they are termed as high-dynamic range ADCs. Alternatively, an ADC with a  much lower dynamic range can be used to sample signals with larger amplitudes. Sub-Nyquist sampling and low-dynamic range requirements significantly reduce the power consumption and cost of the ADC.

The modulo folding block is key component of the high-dynamic range ADC and we discuss its hardware implementation in the next section.

\begin{figure}
	\centering
	\includegraphics[width= 3 in]{Figs/folding}
	\caption{Folding principle}
	\label{Fig:folding}
\end{figure}
\section{Modulo Hardware Prototype}
In this section, we discuss our modulo hardware prototype. First, we explain the working principle of the modulo block and explain how its design and then discuss the hardware realization.
\subsection{Working Principle of Modulo Block}
Principle of computing $y_\lambda(t)$ from $y(t)$ is shown by block-diagram in Fig.~\ref{Fig:folding}. The system comprises of an adder $S$, a direct-current voltage generator (DC-VG), and two comparators $C_1$ and $C_2$. To understand the working let us first assume that for some time instant $t_1$, we have that $|y(t)|<\lambda$ for $t<t_1$. Hence $y_\lambda(t) = y(t)$ and $z(t) = 0$ for $t<t_1$. At $t=t_1$, let $|f(t)|$ crosses $\lambda$. If $f(t_1)>0$, then the comparator $C_1$ triggers a positive value or else, $C_2$ triggers a negative value. The DC-VG is designed such that for every positive value input it reduces its output signal level by $-2\lambda$, whereas, for negative value it increases its output voltage by $2\lambda$. Hence, in the current example, DC-VG generates signal $z(t) = \text{sgn}(y_\lambda(t_1)) 2\lambda u(t-t_1)$ where $u(t)$ is unit-step function.
In this way by adding or subtracting (by using $S$) constant DC signals from $f(t)$ whenever it crosses dynamic range $[-\lambda, \lambda]$, the amplitude levels of $f_\lambda(t)$ are kept within ADC's dynamic range.

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3 in]{Figs/dc_vg}
	\caption{DC-VG}
	\label{Fig:dcvg}
\end{figure}

\begin{figure*}[!t]
	\centering
	\includegraphics[width=5 in]{IEEE_TAES_v1/Figs/UDR_Board_Labeled3.PNG}
	\caption{Modulo Hardware Board.}
	\label{Fig:hw_board}
\end{figure*}
\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[]{\includegraphics[width=2.5in]{Figs/UDRPhase2pictures500Hz}\label{fig:500_2}} \\
		\subfigure[]{\includegraphics[width=2.5in]{Figs/UDRPhase2pictures2KHz}\label{fig:2k_2}}
	\end{tabular}
	\caption{Analysis of folding ability of the modulo hardware.}
	\label{Fig:two_fold}
\end{figure}

\begin{figure}[!h]
	\centering
	\begin{tabular}{c}
		\subfigure[]{\includegraphics[width=2.5in]{Figs/500Hz}\label{fig:500_1}} \\
		\subfigure[]{\includegraphics[width=2.5in]{Figs/1KHz}\label{fig:1k_1}} \\
		\subfigure[]{\includegraphics[width=2.5in]{Figs/5KHz}\label{fig:5k_1}}
	\end{tabular}
	\caption{Analysis of frequency response of the modulo hardware.}
	\label{Fig:frequency_response}
\end{figure}

\begin{table}[h!]
		\caption{Folding Operation.}
	\centering
	\begin{tabular}{||c c c c c ||}
		\hline
		c & b & a & sgn & Counter values \\ [0.5ex]
		\hline\hline
		0 & 0 & 0 & 0~(1) & 0~(0) \\
		0 & 0 & 1 & 0~(1) & 1~(-1) \\
		0 & 1 & 0 & 0~(1) & 2~(-2) \\
		0 & 1 & 1 & 0~(1) & 3~(-3) \\
		1 & 0 & 0 & 0~(1) & 4~(-4) \\
		1 & 0 & 1 & 0~(1) & 5~(-5)\\
		1 & 1 & 0 & 0~(1) & 6~(-6)\\
		1 & 1 & 1 & 0~(1) & 7~(-7)\\
		\hline
	\end{tabular}
	\label{table:counter}
\end{table}
While the parts such as comparators $C_1$, $C_2$, and adder $S$ can be realized by using off-the-shelf components, DC-VG is a more involved system and required careful design. A detailed architecture of DC-VG is shown in Fig.~\ref{Fig:dcvg}. It consists of an up/down counter, a digital-to-analog converter (DAC), a multiplexer (MUX), and a multiplier $M$.  The role of the counter (together with DAC) is to generate a variable, but controlled, DC voltage whenever there is a trigger at its input. The voltage values are set to be multiple of $2\lambda$ by using the MUX and multiplier $M$.
To elaborate the working principle, we first discuss the role of the counter and then the rest of the components.

In this particular system, we use a three-bit synchronous up/down converter. The bits from lower significant bit to higher significant bit are denoted as a, b, and c. The counter has an additional sign bit shown as sgn. With these bits, the counter can count from -7 to 7. For every positive trigger at the input, the output counts up and with a negative trigger it counts down. In Table~\ref{table:counter}, we display the values of bits and the counter (denoted as counter values). The three bits (a,b, and c) of the counter are used as input to the DAC which converts the bits to analog DC voltages. Let the resolution or step size of the DAC is $\alpha$ then the output of DAC is $\alpha$ times the counter-value. To be more specific, consider the scenario where the output of counter and DAC are zero. Then for a positive (negative) trigger, the output of DAC increases (decreases) by $\alpha$. Specifically, the output of DAC, $s(t)$, is a piecewise constant signal with values that are multiples of $\alpha$. However, for folding to work, the change in the voltage should be in multiples of $2\lambda$. To ascertain that we use a MUX which outputs either $2\lambda$ or $-2\lambda$ depending on whether its input is 1 or 0. Then by multiplying the output of DAC with the output of MUX we generate $z(t)$. Next, we discuss the hardware board the realize the folding operation discussed in this section.

\begin{table}[h!]
\centering
\caption{List of Hardware Components}
\label{table:hardware_components}
\begin{tabular}{||c c c||}
 \hline
 Component & Model Number & Make \\
 && \\ \hline
 Comparator & LM339 & Texas Instruments \\
 && \\
 UP/DOWN Counter & TEENSY4.1 & PJRC \\
 && \\
 DAC 3bits & LT1364 & Analog Devices \\
 && \\
 Analog MUX & ADG1608 & Analog Devices \\
 && \\
 Analog Multiplier & AD835 & Analog Devices \\
 && \\
 Adder & LT1364 & Analog Devices \\
  && \\ [1ex]
\hline
\end{tabular}
\end{table}
\subsection{Modulo Hardware Board}
Our modulo hardware board is shown in Fig.~\ref{Fig:hw_board} with main role of the various building components are marked. The details of the components of the hardware are listed in Table~\ref{table:hardware_components}. The board is designed for $\lambda \leq 1.25$ volts. The board can accommodate an input signal with a dynamic range between $[-4\lambda, 4\lambda]$ which implies that an ADC with our modulo hardware can sample four-times larger signals compared to its dynamic range without saturation and clipping.

We demonstrate working of the modulo hardware by considering sinusoidal signal $y(t) = A\, \sin(2\pi f_0 t)$ where $A$ is amplitude and $f_0$ is frequency (in Hz). In this experiment, we set $\lambda = 1.25$ and $3\lambda <A <4\lambda$. With these settings, we expect the signal to fold twice in a quarter cycle of a sinusoid. Figs.~\ref{Fig:two_fold}(a) and \ref{Fig:two_fold}(b) screenshots of an oscilloscope capturing input $y(t)$ (in yellow) and its folded output $y_\lambda(t)$ (in green) for $f_0 = 500$ Hz and $f_0 = 2$ kHz, respectively. We observed that the signals are folded back to lie within the dynamic range of the ADC as expected without clipping. The reason we choose two different frequencies is to study the frequency response of the modulo folder. As in any analog system, the response of the modulo folder too depends on the frequency or bandwidth of the input signal. Beyond a particular frequency, the foldings may not be accurate as observed in Fig.~\ref{Fig:frequency_response}. We observed that for signals of 500 Hz and 1kHz the hardware is able to fold the signal accurately. However, for $f_0 = 5$ kHz, folding instants are not symmetric for positive and negative folds. In the next section, we discuss a couple of inaccuracies of the modulo hardware and our proposed solution to overcome those.

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3.2 in]{Figs/mod_td}
	\caption{Effect of time delay of the feedback loop on the modulo operation.}
	\label{Fig:mod_td}
\end{figure}

\subsection{Artifacts During Folding}
Errors or other artifacts that arise during folding operation in hardware could be due to various reasons. For example, in Figs.~\ref{Fig:two_fold} and \ref{Fig:frequency_response}, we observe that the amplitude of the folded signals could go beyond the dynamic range momentarily around the folding instants. This is due to the settling time of the DC-VG when voltage values change. Specifically, after switching, the voltage at the output of DC-VG overshoots and undershoots before the oscillations settle down to the expected value. This can be overcome by using a faster adder whose response time should be at least a magnitude higher than the sample rate.

Another major issue that arises in a folding ADC is a time delay in the feedback loop (See Fig.~\ref{Fig:folding}). To elaborate, consider a scenario where $y(t)<\lambda$ for $t<t_1$ and it crosses $\lambda$ at time $t_1$ as discussed earlier. To fold the output voltage to the dynamic range of the ADC, $z(t) = -2\lambda u(t-t_1)$ needs to be added to $y(t)$. However, there is a finite delay between the trigger time $t_1$ to generating $z(t)$. If the time delay is $T_d$, then $z(t) = -2\lambda u(t-t_1-T_d)$ is added which causes distortion. To illustrate this effect in Fig.~\ref{Fig:mod_td} by considering a sinusoidal signal (in blue) and its folded versions with and without delay. We observe that in the absence of any time delay ($T_d=0$) the signal folds perfectly (shown in red) to stay within the dynamic range. However, for a non-zero value of $T_d$, foldings do not take place at the folding instants and the output of the modulo operator (shown in black) still remains outside the dynamic range $[-\lambda, \lambda]$. We propose a hardware solution to address this issue.

Out solution uses the fact that with a finite time delay, the amount of overshoot of a smooth signal can be bounded. To elaborate, let us assume that the signal that undergoes modulo operation is Lipschitz continuous. Specifically, a signal $y(t)$ is Lipschitz continuous if there exists a positive real number $\mathrm{L}_y$ such that for any $T>0$ we have
\begin{align}
    |y(t) -y(t+T)|\leq \mathrm{L}_y\, T.
    \label{eq:lipschitz}
\end{align}
With the Lipschitz smoothness condition, we note that the amplitude of $y(t)$ can not change more than $\mathrm{L}_y\, T_d$ between any folding instant and time of its effect to take place. Hence, if we choose dynamic range of the ADC to be $[-(\lambda+\Delta \lambda), (\lambda+\Delta \lambda)]$ where $\Delta \lambda = \mathrm{L}_y\, T_d$ then the signal will not clip. We show this extended dynamic region in the illustrative example in Fig.~\ref{Fig:mod_td}. Alternatively, instead of increasing ADC's dynamic range, one can keep it to be $[-\lambda, \lambda]$ and reduce the threshold values for comparators. In this case, $C_1$ will trigger when the input crosses $\lambda-\Delta \lambda$ and $C_2$ will trigger when input goes beyond $-\lambda+\Delta \lambda$. In this way, the time delay issue is addressed by the modulo circuit without altering ADC's dynamic range.

To implement the mentioned solution, the signal should be Lipschitz continuous. In our setup, the input to modulo operation is a lowpass or bandlimited signal which always satisfies the Lipschitz smoothness condition \cite{bl_bound}. For a bandlimited signal $y(t)$ its Lipschitz constant $\mathrm{L}_y$ is directly proportional to its bandwidth $\omega_c$ which is the same as the cutoff frequency of the LPF.
Hence, for a given value $\Delta \lambda$ and $T_d$ (both depend on the modulo circuit), $\mathrm{L}_y = \Delta \lambda/T_d$ is fixed and this restricts the maximum frequency of the input signal that can be faithfully folded. In the current design, we chose to implement the counter management by a TEENSY micro-controller which results in a time delay of $1 \mu$s which enable the hardware to support a wide range of frequencies with no need to modify the hardware components. In order to support higher frequencies, alternative design strategies with a faster response time and lower delay should be used.

\section{Results}
In this section, we show the signal reconstruction ability of the modulo hardware described in the previous section. From Fig.~\ref{fig:fri_framework}, we understood that the signal reconstruction ability is a function of LPF $g(t)$, modulo circuit $\mathcal{M}_\lambda(\cdot)$, ADC or sampler, unfolding algorithm, and parameter estimation method. Any error in the estimation of FRI parameters is a result of flaws and limitations of the hardware realizations and limitations of the algorithms in the presence of measurement noise. For example, ideally $g(t)$ should have infinite impulse response, however, only a truncated version could be realizable in hardware. The truncation will result in errors while determining the Fourier samples of the FRI signal (See Section~III.\ref{sec:lpf}). Similarly, quantization plays a role when a finite resolution quantizer is used after the sampler. In addition, all the hardware components contribute to different types of noise. We model all these noises and inaccuracies as additive noise at the output of the sampler. Specifically, the noisy measurements are given as
 \begin{align}
            \tilde{y}_{\lambda}(n T_s) = {y}_{\lambda}(n T_s) + v(n T_s),
        \label{eq: noisy_samples}
        \end{align}
where $v(n T_s)$ is the noise term. Both unfolding and parameter estimation algorithms should be robust to different noise models. The robustness of parameter estimation methods in the presence of noise is well studied (See \cite{mulleti_kernal, stoica, eldar_sos}). In \cite{eyar_moduloicassp}, we presented comparisons of unfolding algorithms for bandlimited signals. We showed that our beyond-bandwidth residual recovery ($B^2R^2$) approach results in lower error during unfolding compared to the \emph{higher-order differences} (HOD) approach \cite{unlimited_sampling17, uls_tsp} and \emph{Chebyshev polynomial filter}-based (CPF) method \cite{uls_romonov}. Importantly, for a given sampling rate, $\lambda$, and signal to noise ratio (SNR), $B^2R^2$ method results in the lowest error for both bounded and unbounded noise models.

Before presenting hardware results, we compare the performances of the $B^2R^2$ method with HOD and CPF approaches for quantization noise and unbounded noise. We would like to point out that quantization noise was not considered in \cite{eyar_moduloicassp}. Although, the algorithms were compared for unbounded noise but the simulation settings were different than those in our hardware. Hence, for a better understanding, we compared our algorithm for unbounded noise and quantizaition  noise with the current hardware settings. In the next section, we present these simulation results and then present hardware results.

\begin{figure}[!t]
	\centering
	\includegraphics[width= 2.5 in]{IEEE_TAES_v1/Figs/quantization.png}
	\caption{Comparison of HOD, CPF and $B^2R^2$ algorithms after the quantization process in terms of MSE when recovering a bandlimited signal from modulo samples with $\lambda = 1.25$ and OF = 3,6. For a given number of bits, $B^2R^2$ has the lowest MSE.}
	\label{Fig:quantization}
\end{figure}

\begin{figure}[!t]
	\centering
	\includegraphics[width= 2.5 in]{IEEE_TAES_v1/Figs/Gaussian.png}
	\caption{Comparison of HOD, CPF and $B^2R^2$ algorithms (with unbounded noise) in terms of MSE when recovering a bandlimited signal from modulo samples with  $\lambda$ = 1.25 and OF = 3,6. For a given SNR and OF, $B^2R^2$ has lowest MSE.}
	\label{Fig:unbounded}
\end{figure}
\subsection{Simulated Results}
In this section, we compare our $B^2R^2$ algorithm with the \emph{higher-order differences} (HOD) approach \cite{unlimited_sampling17, uls_tsp} and \emph{Chebyshev polynomial filter}-based (CPF) method \cite{uls_romonov}. We consider the noise measurements as in \eqref{eq: noisy_samples} for a simulation data. In the simulations, $\lambda$ is set to be $1.25$ as in the hardware. We normalize the bandlimited signals to have maximum amplitude of $10$. The SNR is calculated as $\text{SNR} = 20 \log\left(\frac{||y_{\lambda}(n T_s)||}{||v(n T_s)||}\right)$. The reconstruction accuracy of different methods is compared in terms of normalized mean-squared error (MSE) as $ \frac{\sum |y(nT_s) - \hat{y}(n Ts)|^2}{\sum |y(nT_s)|^2}$, where $\hat{y}(n T_s)$ estimate of $y(n T_s)$. For different noise settings and over-sampling factors (OFs), we considered 100 independent noise realizations and calculated the average MSE for them. We first consider quantization noise and then present results for unbounded noise.

\begin{figure}[!t]
    \centering
    \includegraphics[width=0.3\textwidth]{IEEE_TAES_v1/Figs/Signal Generator.png}
    \caption{Bandlimited signal generator.}
    \label{fig:UDRSignalGen}
\end{figure}

 First, we consider an uniform quantizer after the sampling. The unfolding algorithms are applied on the quantized samples. The MSE in the estimation of bandlimited signals for a different number of bits and OFs is shown in Fig. ~\ref{Fig:quantization}. We observe that for a given $\text{OF}$, $B^2R^2$ algorithm results in the lowest MSE for less than 5 bits. For more than 5 bits all the algorithms, except HOD with OF = 3, perform equally well. The results show that low-resolution quantizers can be used with $B^2R^2$ algorithm for unrolling which saves both power and memory requirements.

Next, for unbounded noise, we assume that the noise measurements $v(nT_s)$ are independent and identically distributed Gaussian random variables with zero mean. The variance is set to achieve a desired SNR. We compare the methods for different values of SNR and OFs with $\lambda = 1.25$. Fig.~\ref{Fig:unbounded} shows MSE of the different algorithms for OF $= 3$ and $6$. We note that our algorithm results in lowest error for a given OF and SNR.

Given the advantages of $B^2R^2$ algorithm over the other approaches, we present the hardware results in the next section by using this method.

\begin{figure*}[!t]
	\centering
	\begin{tabular}{cc}
		\subfigure[]{\includegraphics[width=2.5in]{IEEE_TAES_v1/Figs/BL1_rec.png}\label{fig:BL1}} &
		\subfigure[]{\includegraphics[width=2.5in]{IEEE_TAES_v1/Figs/BL2_rec.png}\label{fig:BL2}}
	\end{tabular}
	\caption{Hardware results for bandlimited signals. The $B^2R^2$ algorithm is used to unfold $y_\lambda(t)$ (measured at the output of hardware) and the unfolded signal $\hat{y}(t)$ is plotted with bandlimited signal $y(t)$.}
	\label{fig:BL_ex1}
\end{figure*}

\begin{figure*}[!t]
	\centering
	\begin{tabular}{ccc}
		\subfigure[]{\includegraphics[width=2.2in]{IEEE_TAES_v1/Figs/Ex1_lpf.pdf}\label{fig:FRI11}} &
		\subfigure[]{\includegraphics[width=2.1in]{IEEE_TAES_v1/Figs/Ex2_lpf.pdf}\label{fig:FRI12}}&
		\subfigure[]{\includegraphics[width=2.1in]{IEEE_TAES_v1/Figs/Ex3_lpf.pdf}\label{fig:FRI13}}\\
		\subfigure[]{\includegraphics[width=2.1in]{IEEE_TAES_v1/Figs/Ex1_fri.pdf}\label{fig:FRI21}} &
		\subfigure[]{\includegraphics[width=2.1in]{IEEE_TAES_v1/Figs/Ex2_fri.pdf}\label{fig:FRI22}}&
		\subfigure[]{\includegraphics[width=2.1in]{IEEE_TAES_v1/Figs/Ex3_fri.pdf}\label{fig:FRI23}}
	\end{tabular}
	\caption{Hardware results for FRI signals: Top row shows three examples of lowpass filtered FRI signals $y(t)$, modulo outputs $y_\lambda(t)$, and unfolded signals $\hat{y}(t)$; bottom row shows true FRI signal $f(t)$ and its estimate $\hat{f}(t)$.}
	\label{fig:FRI_ex}
\end{figure*}

\subsection{Hardware Results}
In this section, we present results from the hardware.
Since bandlimited signals are input to the hardware , we fist present results for them and then show results for FRI signals. If the hardware and unfolding algorithm is able to recover the bandlimited signals with high accuracy than it will leads to better reconstruction of the FRI signals. In all these experiments we set $\lambda = 1.25$ V and the cutoff frequency of the lowpass filter is 1 kHz. We observe that for frequencies less than or equal to 1 kHz, out hardware is able to reliably fold the signal. The Nyquist rate of the signal is 2 kHz. But for unfolding we need to oversample the signal. In all these experiments, we used $B^2R^2$ algorithm with OF = 5 which results in sampling rate of 10 kHz. Further, $y(t)$ and $y_\lambda(t)$ are measured from the hardware through an oscilloscope for processing by the algorithms.

We first consider the bandlimited signals. For generating bandlimited or lowpass signals we used a Arduino micro-controller (See Fig.~\ref{fig:UDRSignalGen}) which convert the digital signal to an analog signal via a DAC. The digital signals were generated using MATLAB software. In Fig.~\ref{fig:BL_ex1}, we show folding and reconstruction of two bandlimited signals. These signals have maximum amplitude of 5 V. We observe the signals are restricted to $[-\lambda, \lambda]$ by the modulo hardware and the algorithm was able to recover the true signal from the folded samples. The reconstructed signal has slightly larger amplitude compared to the true signal which is result of scaling within the hardware.

Next, we consider reconstruction of FRI signals from modulo samples. To generate the FRI signals, we consider $h(t)$ to be a sort pulse of bandwidth 30 kHz (Nyquist rate = 60 kHz). We consider three examples with $L=2, 3,$ and 5. The amplitudes and time delays are generated randomly. The maximum time delay is $T_0 = 0.1$ sec. Once generated, the FRI signal is lowpass filtered with a cutoff frequency of 1 kHz. Up to filtering operation, MATLAB is used and then Arduino micro-controller is used to generate the analog version of the filtered FRI signals. The signal is then folded using the hardware and folded signals are sampled. The sampling rate is 10 kHz which is five times higher than the sampling rate of the lowpass signal. Still the rate is six times lower than the Nyquist rate and hence the system operates at sub-Nyquist rate. The setup satisfies the conditions in \eqref{eq:sampling_rate} for $L=2, 3,$ and 5.

We first apply $B^2R^2$ algorithm to unfold the signal and then used ESPRIT \cite{paulraj_esprit} to estimate the time delays and amplitudes of the FRI signals. We show FRI signal sampling and reconstruction in Fig.~\ref{fig:FRI_ex} where the top row shows LPF output $y(t)$, folded signal (output of the modulo hardware) $y_\lambda(t)$, and unfolded signals $\hat{y}(t)$. The bottom row shows location and amplitude of the true signal $f(t)$ and estimated FRI signal $\hat{f}(t)$. The maximum error in the estimation of time delay $-15$ dB which shows that the system can be used in applications like radar and ultrasound imaging.

\section{Conclusions}
We considered the problem of recovering FRI signals from low-pass filtered, modulo samples. We presented a hardware prototype for the modulo folding system and show that for different bandlimited and FRI signals, the hardware is able to faithfully fold the signal. We also  address the time delay issue of the modulo system and presented a hardware solution for the same. The overall system operates at six times below the Nyquist rate which enables one to use low rate, low-dynamic range, power efficient ADCs.

\bibliographystyle{IEEEtaes}

\section{INTRODUCTION}
Sampling plays a key role in efficiently processing real-world analog signals on digital signal processors. Analog to digital converters (ADCs) are used to implement sampling in the hardware. A key parameter of an ADC is its sampling rate. ADCs with high sampling rates are power-consuming and expensive, making them unsuitable for portable devices such as hand-held ultrasound devices. Hence, it is desirable to reduce the sampling rate. Signals with finite rate of innovation (FRI) have few degrees of freedom which aids in sub-Nyquist sampling \cite{eldar_2015sampling}. That is, signal is sampled at a rate much lower than the Nyquist rate \cite{shannon, nyquist} and hence low power ADCs could be used. FRI model is ubiquitous in several time of flight applications \cite{bajwa_radar, bar_radar,filho201seismic,rip,carter_sonar,eldar_sos,eldar_beamforming, sunil} where the signal of interest is represented as a linear combination of delayed copies of a known pulse. Thus, the desired information lies in the amplitudes and time delays of the pulse, which amounts to a few degrees of freedom.

Most existing works in the context of FRI sampling focus on reducing the ADC's sampling rate by using the signal structure \cite{vetterli, eldar_sos, fri_strang, blu_moms, mulleti_kernal} and ignores other aspects of the ADC.
The dynamic range of an ADC plays a crucial role in sampling an analog signal. ADC's dynamic range should generally be larger than the signal's; otherwise, the signal gets clipped. A few approaches exist to recover the true samples from clipped ones for bandlimited signals \cite{marks_clipping2, marks_clipping1}. These approaches rely on the correlation among the samples when they are measured at a very high rate compared to the Nyquist rate. The requirement of a high sampling rate is a drawback of these approaches. In addition, theoretical guarantees are missing, and it is unclear how many clipped samples can be recovered.

There are several preprocessing approaches such as automatic gain control (AGC) \cite{perez2011automatic,mercy1981review}, companding \cite{landau_compander,landau_distorted_bl}, and modulo folding \cite{uls_tsp,uls_romonov,uls_sparse,bhandari2021unlimited,eyar_moduloicassp}, that can be used prior to sampling to avoid clipping. Among these, modulo folding is most recent approach that need not be differentiable like companding and does not suffer from stability issues of the feedback amplifiers used in AGC. In the modulo framework, the signal is folded to lie within ADC's dynamic range and then the folded signal is sampled by using a conventional ADC. Theoretical guarantees for recovering bandlimited signals from folded samples are presented in \cite{uls_tsp,uls_identifiability}. The results states that the bandlimited signals can be uniquely recovered from folded samples provided that they are sampled above the Nyquist rate.

Several algorithms for \emph{unfolding} or recovering the true samples of bandlimited signals from modulo or folded samples are presented in \cite{uls_tsp,uls_romonov, eyar_moduloicassp}. These unfolding algorithms can be compared in terms of sampling rate, amount of unfolding they can handle, and noise robustness. It is shown that the method proposed in \cite{eyar_moduloicassp} has lowest reconstruction error for a given sampling rate, noise level, and signal's amplitude level compared to the algorithms presented in \cite{uls_tsp,uls_romonov}. The algorithm proposed in \cite{uls_tsp} requires almost 17-times higher sampling rate than the Nyquist rate but it is independent of the dynamic range of the ADC. Whereas, the approaches in \cite{uls_romonov, eyar_moduloicassp} requires the knowledge of ADC's dynamic range. Modulo sampling is also extended to different problems and signal models such as periodic bandlimited signals \cite{bhandari2021unlimited}, wavelets \cite{uls_wavelet}, mixture of sinusoids \cite{uls_sinmix}, finite-rate-of-innovation signals \cite{uls_fri}, multi-dimensional signals \cite{uls_md}, sparse vector recovery \cite{uls_gamp, uls_sparsevec}, direction of arrival estimation problem \cite{uls_doa}, computed tomography \cite{uls_radon}, and graph signals \cite{uls_graph}.

While theoretical guarantees and algorithms of any new sampling approach are always well researched but the question of whether they work in practice is difficult to answer. For modulo sampling, there exists a few hardware prototypes. For example, high-dynamic-range ADCs, also known as \emph{self-reset} ADCs, are discussed in the context of imaging \cite{sradc_park, sradc_sasagwa, sradc_yuan, krishna2019unlimited}. These hardware architectures measure additional information such as the amount of folding for each sample, or, the sign of the folding together with the folded samples. The additional information might enable simpler recovery but at the expense of complex circuitry. Importantly, additional bits are required during the quantization process to store or transmit the side information.

Krishna et al. presented a hardware prototype which encode the side-information by using two bits \cite{krishna2019unlimited}. The architecture is designed to record sign of the slope of the signal at each sampling instant when the sample lies outside ADC's dynamic range. In a conventional ADC, a sample and hold (S/H) circuit is used to hold the sampled value for a prescribed period of time during which quantization is performed on the sample. To realize the modulo sampling, a folding circuit is used after S/H \cite{krishna2019unlimited}. Hence, the S/H circuit has to hold the sampled value for folding and quantization, which results in a larger folding time compared to a conventional ADC. A large holding time results in slower ADC and hence it may not be useful for wideband application.

The Modulo hardware prototypes where the modulo part is implemented prior to sampler are presented in \cite{bhandari2021unlimited,Bhandari:2022:J,mod_hyst}. Since the modulo circuit is not part of the hold time, the ADC could be faster than the hardware realization in \cite{krishna2019unlimited}.  In \cite{mod_hyst}, the authors discussed a few implementation issues of modulo hardware such as hysteresis and folding transients, and proposed algorithmic solutions to mitigate them. Both these issues can also be addressed by careful calibration and by using high precision components. In \cite{Bhandari:2022:J}, Bhandari showed reconstruction of FRI signals by using a modulo hardware. In \cite{bhandari2021unlimited,Bhandari:2022:J,mod_hyst}, rather than providing details of the hardware circuitry the authors are focused on different signal models, hardware-limitations, and algorithms. They showed that the modulo hardware is able to fold low frequency signals which are 10-12 times larger than the ADC's dynamic range.

In this paper, we present a modulo hardware prototype which can be used in low-power time-of-flight applications, and show that by using our algorithm \cite{eyar_moduloicassp} it is able to faithfully reconstruct FRI signals.
In the following, we present our contributions and the salient features of our hardware system.
\begin{itemize}
    \item As an initial step, we design our hardware components in such a way that they can fold the signals upto 5KHz.

    Note that none of the existing hardwares handles such frequency input signals.
    \item Our hardware prototype is designed to operate prior to the sampler unlike the hardware in  \cite{krishna2019unlimited} which operates in the hold part of the sampler. Hence, the proposed system can use faster ADCs with smaller hold time.
    \item Modulo folding is realized through a feedback mechanism. The time instants at which the input signal goes beyond the ADC's dynamic range, a trigger signal is generated by using a set of comparators. The trigger then activates a direct-current (DC) generator that adds to the input signal to bring it to stay within the dynamic range. This feedback mechanism introduces a finite time delay between the trigger and addition operation. The delay has an undesirable effect and it causes a part of the input signal to stay beyond the dynamic range.
    We address this key issue of the hardware which was not considered in the previous works.
    By using smoothness of the signal and time delay of the feedback loop, we show that by changing the thresholds of comparators the delay issue can be mitigated. Specifically, by using tunable threshold voltages at the comparators, time delay issues can be resolved for signals with different bandwidths.
    \item To show an application of the hardware, we consider sampling and reconstruction of FRI signals. We use a lowpass filter (LPF) prior to modulo system as a sampling kernel. The filter removes unwanted information in the signal and allows sub-Nyquist sampling. The filtered signal is folded by the designed hardware and then sampled. For estimating the FRI parameters, the samples are first unfolded by using our algorithm presented in \cite{eyar_moduloicassp} and then the parameters are estimated by using annihilating filter approach. By using the fact that our algorithm operates at lowest possible rate, we show that FRI parameters can be estimated sub-Nyquist samples. In particular, we show that the system operates at five times the rate of innovation which is much lower than the Nyquist rate of the signal.
\end{itemize}

The paper is organized as follows. In the next section, we discuss the FRI signal model and its sampling and reconstruction framework in the presence of modulo hardware. In Section III, we present the actual hardware system by explaining its working principle and discussing the components of the system. In Section IV, we show the signal folding and reconstruction abilities of the hardware, and then the conclusion is followed.

\section{Signal Model and System Description}
In this section, we first introduce the FRI signal model and then discuss its sampling and reconstruction framework with modulo ADC.
\subsection{FRI Signal Model}
Consider an FRI signal consisting of stream of $L$ pulses:
\begin{align}
	f(t) = \sum_{\ell=1}^L a_\ell h(t-t_\ell),
	\label{eq:fri1}
\end{align}
where the pulse $h(t)$ a real-valued known pulse. We assume that $a_\ell$s are real-valued and $t_\ell \in (0, T_0] \subset \mathbb{R}$ for a known $T_0$.

The FRI signal model in \eqref{eq:fri1} is encountered in several scientific applications such as radar imaging \cite{bar_radar, bajwa_radar, sunil}, ultrasound imaging \cite{eldar_sos,eldar_beamforming,mulleti_icip}, light detection and ranging (LIDAR) \cite{castorena_lidar}, time-domain optical-coherence tomography (TDOCT) \cite{blu_oct}, and other time-of-flight imaging systems. In these applications,  $h(t)$ is the transmitted pulse and $\{a_\ell \,h(t-t_\ell)\}_{\ell=1}^{L}$ constitute the reflections from $L$ point targets. The amplitudes $a_\ell$s depend on the sizes of the targets and the delays $t_\ell$s are proportional to the distances of the targets from the transmitter. Here $T_0$ denotes maximum time delay of the targets. The signal $f(t)$ is specified by $\{a_\ell, t_\ell\}_{\ell=1}^L$ and can be reconstructed from its sub-Nyquist measurements acquired using an appropriate sampling kernel \cite{vetterli,eldar_sos,fri_strang, mulleti_kernal}. The reconstruction is generally carried out in frequency domain as discussed next.

\subsection{Fourier-Domain Reconstruction}
Consider uniform samples of continuous-time Fourier transform of $f(t)$ given as
\begin{align}
	F(k \omega_0) = \int f(t) e^{-\mathrm{j} k\omega_0 t} \mathrm{d}t = H(k \omega_0) \sum_{\ell = 1}^L a_\ell \, e^{-\mathrm{j} k\omega_0 t_\ell},
	\label{eq:F}
\end{align}
for $k \in \mathcal{K}$. Here $H(\omega)$ is the Fourier transform of $h(t)$ and $\mathcal{K}$ is an integer set. In \eqref{eq:F}, $\omega_0>0$ denotes sampling interval in the frequency domain. Next, consider the following samples
\begin{align}
	S(k\omega_0) = \frac{F(k\omega_0)}{H(k\omega_0)} =  \sum_{\ell = 1}^L a_\ell \, e^{-\mathrm{j}k\omega_0 t_\ell},
	\label{eq:Skomega}
\end{align}
where we assume that $H(k \omega_0) \neq 0$ for $k \in \mathcal{K}$. In practice, the pulse $h(t)$ has small time support and hence, large bandwidth. Hence, for a finite set $\mathcal{K}$ it is possible to choose a set of frequencies $\{k \omega_0\}_{ k \in \mathcal{K}}$ such that $H(k \omega_0) \neq 0$. It can be shown that $2L$ consecutive samples of $S(k\omega_0)$ are sufficient to uniquely identify $\{a_\ell, t_\ell\}_{\ell=1}^L$ if $\omega_0 = \frac{2\pi}{T_0}$ \cite{eldar_2015sampling}. {\color{blue}{}In practice, high-resolution spectral estimation methods, such as the annihilating filter (AF) or Prony's method and its variants \cite{prony, plonka}, multiple signal classification \cite{schmidt_music, barabell_rmusic, bdrao_rmusic}, matrix-pencil method \cite{sarkar_mp}, estimation of signal parameter via rotational invariance technique (ESPRIT) \cite{paulraj_esprit}, etc., have been deployed for FRI parameter estimation. }

Since $h(t)$ is known, $H(k\omega_0), k \in \mathcal{K}$ can be calculated in advance. Hence, to compute $S(k\omega_0), k \in \mathcal{K}$ and then to estimate the FRI parameters, $F(k\omega_0), k \in \mathcal{K}$ has to be determined. Next, we discuss a lowpass filter (LPF) based sampling framework to determine these Fourier samples.

\subsection{LPF-Based Sub-Nyquist Sampling}
\label{sec:lpf}
In this section, we discuss a LPF-based sampling mechanism for FRI signals. Let $g(t)$ denotes an ideal lowpass filter with cutoff frequency $\omega_c$ rad/sec. In the frequency-domain we have that $G(\omega) = 1$ for $\omega \in [-\omega_c, \omega_c]$ and zero for the rest of the frequencies. Let $y(t)$ denotes response of the LPF to the input $f(t)$, that is, $y(t) = (f*g)(t)$, where $*$ denotes linear convolution operation. Consider an ADC with dynamic range $[-\lambda, \lambda]$ and sampling rate $\omega_s = \frac{2\pi}{T_s}$ rad/sec. By assuming that  $\|y(t)\|_{\infty}\leq \lambda$, uniform samples at the output of ADC are given as $y(nT_s), n \in \mathbb{Z}$. Then uniform measurements of discrete-time Fourier transform (DTFT) of the samples are given as
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) = \sum_{n \in \mathbb{Z}}y(nT_s)\,e^{\mathrm{j} k\omega_0 n T_s}, \quad k \in \mathcal{K}.
	\label{eq:y_dtft}
\end{align}
By using relationship between DTFT of samples $y(nT_s)$ and CTFT of $y(t)$ we have
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) &= \frac{1}{T_s}\sum_{m \in \mathbb{Z}} Y(k\omega_0 + m \omega_s), \nonumber \\
	&= \frac{1}{T_s}\sum_{m \in \mathbb{Z}} F(k\omega_0 + m \omega_s) \,G(k\omega_0 + m \omega_s),
		\label{eq:y_dtft2}
\end{align}
where we used the fact that $Y(\omega) = F(\omega)\,G(\omega)$. Next, consider the following conditions on the sampling rate and cutoff frequency of the filter
\begin{align}
	\omega_s \geq 2\omega_c, \quad \text{and} \quad \omega_c \geq K \omega_0,
	\label{eq:sampling_rate}
\end{align}
where $K \geq L$. Then by choosing $\mathcal{K} = \{-K, \cdots, K\}$, \eqref{eq:y_dtft2} can be written as
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) = F(k\omega_0), \quad k \in \mathcal{K},
	\label{eq:y_dtft3}
\end{align}
where we used the fact that $G(k\omega_0) = 1$ in these settings. The relationship \eqref{eq:y_dtft3} shows that the desired Fourier samples of $f(t)$ are determined from the samples of LPF by assuming that the conditions in \eqref{eq:y_dtft2} are satisfied. Hence, FRI parameters can be determined from the samples of the lowpass filter. A LPF-based sampling for FRI signal was used in \cite{vetterli,uls_sparse} but with a periodic FRI signal model. With perodization, a finite number of time samples are sufficient to determine the desired Fourier measurements, whereas, countable infinite measurements are required in aperiodic settings consider here.

The bandwidth of the pulse $h(t)$ and hence that of the FRI signal $f(t)$ could be very large. But the sampling rate $\omega_s$ is independent of the pulse and could be much smaller than its bandwidth which shows the FRI signal could be reconstructed from sub-Nyquist samples.

The sub-Nyquist sampling framework discussed assumes that $\|y(t)\|_{\infty}\leq \lambda$, in other words, the framework assumes that the dynamic range of the ADC is greater than that of the signal to be sampled. However, this condition may not be always true. Specifically, the amplitude range of the filtered signal $y(t)$ could be larger than ADC's dynamic range. In such a scenario, a direct sampling would lead to clipping of samples which is undesirable. To avoid clipping, a modulo operator is employed prior to sampling as discussed next.

\begin{figure*}
	\centering
	\includegraphics[width=6.5 in]{Figs/FRI_US}
	\caption{A schematic of modulo-sampling and reconstruction of FRI signals.}
	\label{fig:fri_framework}
\end{figure*}

\subsection{Modulo-Folding}
To avoid clipping, a modulo folding operator $\mathcal{M}_\lambda(\cdot)$ is used after LPF and before the ADC. The operator folds $y(t)$ to stay within ADC's dynamic range $[-\lambda, \lambda]$. The output of the modulo operator in response to input $y(t)$ is given as
\begin{equation}
 y_\lambda(t) =	\mathcal{M}_{\lambda}(y(t)) = (y(t)+\lambda)\,\, \text{mod}\,\, 2\lambda -\lambda.
	\label{eq:mod_opp}
\end{equation}
The folded signal is then sampled by the ADC to have measurements $y_\lambda(nT_s)$. Since modulo folding is a nonlinear operation, one can not directly apply DTFT on the samples to compute Fourier measurements of the FRI signal for its reconstruction. Hence, the true or unfolded samples $y(nT_s)$ are estimated from the folded ones $y_\lambda(nT_s)$ by applying an unfolding algorithm. There exist several unfolding methods for bandlimited signals \cite{uls_tsp, uls_romonov,eyar_moduloicassp}.
The sampling rate for unfolding varies for different algorithms and generally, is larger than the minimum sampling rate required for FRI signal recovery (cf. \eqref{eq:sampling_rate}).
Hence, the overall system operates on a higher sampling rate than that without a modulo case. However, if the overall sampling rate is much lower than the bandwidth of the FRI signal then the system operates at a sub-Nyquist rate. We show that this is indeed true when we apply our unfolding algorithm proposed in \cite{eyar_moduloicassp}.

An end-to-end modulo sampling framework for FRI signal sampling and reconstruction is shown in Fig.~\ref{fig:fri_framework}. The sampler or ADC together with the modulo block is termed as modulo-ADC.
Modulo-ADCs are able to sample signals beyond their dynamic range without clipping and hence they are termed as high-dynamic range ADCs. Alternatively, an ADC with a  much lower dynamic range can be used to sample signals with larger amplitudes. Sub-Nyquist sampling and low-dynamic range requirements significantly reduce the power consumption and cost of the ADC.

The modulo folding block is key component of the high-dynamic range ADC and we discuss its hardware implementation in the next section.

\begin{figure}
	\centering
	\includegraphics[width= 3 in]{Figs/folding}
	\caption{Folding principle}
	\label{Fig:folding}
\end{figure}
\section{Modulo Hardware Prototype}
In this section, we discuss our modulo hardware prototype. First, we explain the working principle of the modulo block and explain how its design and then discuss the hardware realization.
\subsection{Working Principle of Modulo Block}
Principle of computing $y_\lambda(t)$ from $y(t)$ is shown by block-diagram in Fig.~\ref{Fig:folding}. The system comprises of an adder $S$, a direct-current voltage generator (DC-VG), and two comparators $C_1$ and $C_2$. To understand the working let us first assume that for some time instant $t_1$, we have that $|y(t)|<\lambda$ for $t<t_1$. Hence $y_\lambda(t) = y(t)$ and $z(t) = 0$ for $t<t_1$. At $t=t_1$, let $|y(t)|$ crosses $\lambda$. If $y(t_1)>0$, then the comparator $C_1$ triggers a positive value or else, $C_2$ triggers a negative value. The DC-VG is designed such that for every positive value input it reduces its output signal level by $-2\lambda$, whereas, for negative value it increases its output voltage by $2\lambda$. Hence, in the current example, DC-VG generates signal $z(t) = \text{sgn}(y_\lambda(t_1)) 2\lambda u(t-t_1)$ where $u(t)$ is unit-step function.
In this way by adding or subtracting (by using $S$) constant DC signals from $f(t)$ whenever it crosses dynamic range $[-\lambda, \lambda]$, the amplitude levels of $f_\lambda(t)$ are kept within ADC's dynamic range.

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3 in]{Figs/dc_vg}
	\caption{DC-VG}
	\label{Fig:dcvg}
\end{figure}

\begin{figure*}[!t]
	\centering
	\includegraphics[width=5 in]{IEEE_TAES_v1/Figs/UDR_Board_Labeled3.PNG}
	\caption{Modulo hardware board.}
	\label{Fig:hw_board}
\end{figure*}
\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[]{\includegraphics[width=2.5in]{Figs/UDRPhase2pictures500Hz}\label{fig:500_2}} \\
		\subfigure[]{\includegraphics[width=2.5in]{Figs/UDRPhase2pictures2KHz}\label{fig:2k_2}}
	\end{tabular}
	\caption{Analysis of folding ability of the modulo hardware.}
	\label{Fig:two_fold}
\end{figure}

\begin{figure}[!h]
	\centering
	\begin{tabular}{c}
		\subfigure[]{\includegraphics[width=2.5in]{Figs/500Hz}\label{fig:500_1}} \\
		\subfigure[]{\includegraphics[width=2.5in]{Figs/1KHz}\label{fig:1k_1}} \\
		\subfigure[]{\includegraphics[width=2.5in]{Figs/5KHz}\label{fig:5k_1}}
	\end{tabular}
	\caption{Analysis of frequency response of the modulo hardware.}
	\label{Fig:frequency_response}
\end{figure}

\begin{table}[h!]
		\caption{Folding Operation.}
	\centering
	\begin{tabular}{||c c c c c ||}
		\hline
		c & b & a & sgn & Counter values \\ [0.5ex]
		\hline\hline
		0 & 0 & 0 & 0~(1) & 0~(0) \\
		0 & 0 & 1 & 0~(1) & 1~(-1) \\
		0 & 1 & 0 & 0~(1) & 2~(-2) \\
		0 & 1 & 1 & 0~(1) & 3~(-3) \\
		1 & 0 & 0 & 0~(1) & 4~(-4) \\
		1 & 0 & 1 & 0~(1) & 5~(-5)\\
		1 & 1 & 0 & 0~(1) & 6~(-6)\\
		1 & 1 & 1 & 0~(1) & 7~(-7)\\
		\hline
	\end{tabular}
	\label{table:counter}
\end{table}
While the parts such as comparators $C_1$, $C_2$, and adder $S$ can be realized by using off-the-shelf components, DC-VG is a more involved system and required careful design. A detailed architecture of DC-VG is shown in Fig.~\ref{Fig:dcvg}. It consists of an up/down counter, a digital-to-analog converter (DAC), a multiplexer (MUX), and a multiplier $M$.  The role of the counter (together with DAC) is to generate a variable, but controlled DC voltage whenever there is a trigger at its input. The voltage values are set to be multiple of $2\lambda$ by using the MUX and multiplier $M$.
To elaborate the working principle, we first discuss the role of the counter and then the rest of the components.

In this particular system, we use a three-bit synchronous up/down counter. The bits from lower significant bit to higher significant bit are denoted as a, b, and c. The counter has an additional sign bit shown as sgn. With these bits, the counter can count from -7 to 7. For every positive trigger at the input the output counts up and with a negative trigger it counts down. In Table~\ref{table:counter}, we display the values of bits and the counter (denoted as counter values). The three bits (a,b, and c) of the counter are used as input to the DAC which converts the bits to analog DC voltages. Let the resolution or step size of the DAC is $\alpha$ then the output of DAC is $\alpha$ times the counter-value. To be more specific, consider the scenario where the output of counter and DAC are zero. Then for a positive (negative) trigger, the output of DAC increases (decreases) by $\alpha$. Specifically, the output of DAC, $s(t)$, is a piecewise constant signal with values that are multiples of $\alpha$. However, for folding to work, the change in the voltage should be in multiples of $2\lambda$. To ascertain that we use a MUX which outputs either $2\lambda$ or $-2\lambda$ depending on whether its input is 1 or 0. Then by multiplying the output of DAC with the output of MUX we generate $z(t)$. Next, we discuss the hardware board that realizes the folding operation discussed in this section.

\begin{table}[h!]
\centering
\caption{List of Hardware Components}
\label{table:hardware_components}
\begin{tabular}{||c c c||}
 \hline
 Component & Model Number & Make \\
 && \\ \hline
 Comparator & LM339 & Texas Instruments \\
 && \\
 UP/DOWN Counter & TEENSY4.1 & PJRC \\
 && \\
 DAC 3bits & LT1364 & Analog Devices \\
 && \\
 Analog MUX & ADG1608 & Analog Devices \\
 && \\
 Analog Multiplier & AD835 & Analog Devices \\
 && \\
 Adder & LT1364 & Analog Devices \\
  && \\ [1ex]
\hline
\end{tabular}
\end{table}
\subsection{Modulo Hardware Board}
Our modulo hardware board is shown in Fig.~\ref{Fig:hw_board} with main role of the various building components are marked. The details of the components of the hardware are listed in Table~\ref{table:hardware_components}. The board is designed for $\lambda \leq 1.25$ volts. The board can accommodate an input signal with a dynamic range between $[-4\lambda, 4\lambda]$ which implies that an ADC with our modulo hardware can sample four-times larger signals compared to its dynamic range without saturation and clipping.

We demonstrate the working of the modulo hardware by considering a sinusoidal signal $y(t) = A\, \sin(2\pi f_0 t)$ where $A$ is amplitude and $f_0$ is frequency (in Hz). In this experiment, we set $\lambda = 1.25$ and $3\lambda <A <4\lambda$. With these settings, we expect the signal to fold twice in a quarter cycle of a sinusoid. Figs.~\ref{Fig:two_fold}(a) and \ref{Fig:two_fold}(b) screenshots of an oscilloscope capturing input $y(t)$ (in yellow) and its folded output $y_\lambda(t)$ (in green) for $f_0 = 500$ Hz and $f_0 = 2$ kHz, respectively. We observed that the signals are folded back to lie within the dynamic range of the ADC as expected without clipping. The reason we choose two different frequencies is to study the frequency response of the modulo folder. As in any analog system, the response of the modulo folder too depends on the frequency or bandwidth of the input signal. Beyond a particular frequency, the foldings may not be accurate as observed in Fig.~\ref{Fig:frequency_response}. We observed that for signals of 500 Hz and 1kHz the hardware is able to fold the signal accurately. However, for $f_0 = 5$ kHz, folding instants are not symmetric for positive and negative folds. In one of our future works, we are planning to design a hardware that overcome this limitation by using hardware logical components to implement the folding counter instead of using the current up/down counter. Further, we aim to handle frequencies that are grater than 5kHz. In the next section, we discuss a couple of inaccuracies of the modulo hardware and our proposed solution to overcome those.

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3.2 in]{Figs/mod_td}
	\caption{Effect of time delay of the feedback loop on the modulo operation.}
	\label{Fig:mod_td}
\end{figure}

\subsection{Artifacts During Folding}
Errors or other artifacts that arise during folding operation in hardware could be due to various reasons. For example, in Figs.~\ref{Fig:two_fold} and \ref{Fig:frequency_response}, we observe that the amplitude of the folded signals could go beyond the dynamic range momentarily around the folding instants. This is due to the settling time of the DC-VG when voltage values change. Specifically, after switching, the voltage at the output of DC-VG overshoots and undershoots before the oscillations settle down to the expected value. This can be overcome by using a faster adder whose response time should be at least a magnitude higher than the sample rate.

Another major issue that arises in a folding ADC is a time delay in the feedback loop (See Fig.~\ref{Fig:folding}). To elaborate, consider a scenario where $y(t)<\lambda$ for $t<t_1$ and it crosses $\lambda$ at time $t_1$ as discussed earlier. To fold the output voltage to the dynamic range of the ADC, $z(t) = -2\lambda u(t-t_1)$ needs to be added to $y(t)$. However, there is a finite delay between the trigger time $t_1$ to generating $z(t)$. If the time delay is $T_d$, then $z(t) = -2\lambda u(t-t_1-T_d)$ is added which causes distortion. To illustrate this effect in Fig.~\ref{Fig:mod_td} by considering a sinusoidal signal (in blue) and its folded versions with and without delay. We observe that in the absence of any time delay ($T_d=0$) the signal folds perfectly (shown in red) to stay within the dynamic range. However, for a non-zero value of $T_d$, foldings do not take place at the folding instants and the output of the modulo operator (shown in black) still remains outside the dynamic range $[-\lambda, \lambda]$. We propose a hardware solution to address this issue.

Out solution uses the fact that with a finite time delay, the amount of overshoot of a smooth signal can be bounded. To elaborate, let us assume that the signal that undergoes modulo operation is Lipschitz continuous. Specifically, a signal $y(t)$ is Lipschitz continuous if there exists a positive real number $\mathrm{L}_y$ such that for any $T>0$ we have
\begin{align}
    |y(t) -y(t+T)|\leq \mathrm{L}_y\, T.
    \label{eq:lipschitz}
\end{align}
With the Lipschitz smoothness condition, we note that the amplitude of $y(t)$ can not change more than $\mathrm{L}_y\, T_d$ between any folding instant and time of its effect to take place. Hence, if we choose dynamic range of the ADC to be $[-(\lambda+\Delta \lambda), (\lambda+\Delta \lambda)]$ where $\Delta \lambda = \mathrm{L}_y\, T_d$ then the signal will not clip. We show this extended dynamic region in the illustrative example in Fig.~\ref{Fig:mod_td}. Alternatively, instead of increasing ADC's dynamic range, one can keep it to be $[-\lambda, \lambda]$ and reduce the threshold values for comparators. In this case, $C_1$ will trigger when the input crosses $\lambda-\Delta \lambda$ and $C_2$ will trigger when input goes beyond $-\lambda+\Delta \lambda$. In this way, the time delay issue is addressed by the modulo circuit without altering ADC's dynamic range.

To implement the mentioned solution, the signal should be Lipschitz continuous. In our setup, the input to modulo operation is a lowpass or bandlimited signal which always satisfies the Lipschitz smoothness condition \cite{bl_bound}. For a bandlimited signal $y(t)$ its Lipschitz constant $\mathrm{L}_y$ is directly proportional to its bandwidth $\omega_c$ which is the same as the cutoff frequency of the LPF.
Hence, for a given value $\Delta \lambda$ and $T_d$ (both depend on the modulo circuit), $\mathrm{L}_y = \Delta \lambda/T_d$ is fixed and this restricts the maximum frequency of the input signal that can be faithfully folded. In the current design, we chose to implement the counter management by a TEENSY micro-controller which results in a time delay of $1 \mu$s which enable the hardware to support a wide range of frequencies with no need to modify the hardware components. In order to support higher frequencies, alternative design strategies with a faster response time and lower delay should be used.

\section{Results}
In this section, we show the signal reconstruction ability of the modulo hardware described in the previous section. From Fig.~\ref{fig:fri_framework}, we understood that the signal reconstruction ability is a function of LPF $g(t)$, modulo circuit $\mathcal{M}_\lambda(\cdot)$, ADC or sampler, unfolding algorithm, and parameter estimation method. Any error in the estimation of FRI parameters is a result of flaws and limitations of the hardware realizations and limitations of the algorithms in the presence of measurement noise. For example, ideally $g(t)$ should have infinite impulse response, however, only a truncated version could be realizable in hardware. The truncation will result in errors while determining the Fourier samples of the FRI signal (See Section~III.\ref{sec:lpf}). Similarly, quantization plays a role when a finite resolution quantizer is used after the sampler. In addition, all the hardware components contribute to different types of noise. We model all these noises and inaccuracies as additive noise at the output of the sampler. Specifically, the noisy measurements are given as
 \begin{align}
            \tilde{y}_{\lambda}(n T_s) = {y}_{\lambda}(n T_s) + v(n T_s),
        \label{eq: noisy_samples}
        \end{align}
where $v(n T_s)$ is the noise term. Both unfolding and parameter estimation algorithms should be robust to different noise models. The robustness of parameter estimation methods in the presence of noise is well studied (See \cite{mulleti_kernal, stoica, eldar_sos}). In \cite{eyar_moduloicassp}, we presented comparisons of unfolding algorithms for bandlimited signals. We showed that our beyond-bandwidth residual recovery ($B^2R^2$) approach results in lower error during unfolding compared to the \emph{higher-order differences} (HOD) approach \cite{unlimited_sampling17, uls_tsp} and \emph{Chebyshev polynomial filter}-based (CPF) method \cite{uls_romonov}. Importantly, for a given sampling rate, $\lambda$, and signal to noise ratio (SNR), $B^2R^2$ method results in the lowest error for both bounded and unbounded noise models.

Before presenting hardware results, we compare the performances of the $B^2R^2$ method with HOD and CPF approaches for quantization noise and unbounded noise. We would like to point out that quantization noise was not considered in \cite{eyar_moduloicassp}. Although, the algorithms were compared for unbounded noise but the simulation settings were different than those in our hardware. Hence, for a better understanding, we compared our algorithm for unbounded noise and quantizaition  noise with the current hardware settings. In the next section, we present these simulation results and then present hardware results.

\begin{figure}[!t]
	\centering
	\includegraphics[width= 2.5 in]{IEEE_TAES_v1/Figs/quantization.png}
	\caption{Comparison of HOD, CPF and $B^2R^2$ algorithms after the quantization process in terms of MSE when recovering a bandlimited signal from modulo samples with $\lambda = 1.25$ and OF = 3,6. For a given number of bits, $B^2R^2$ has the lowest MSE.}
	\label{Fig:quantization}
\end{figure}

\begin{figure}[!t]
	\centering
	\includegraphics[width= 2.5 in]{IEEE_TAES_v1/Figs/Gaussian.png}
	\caption{Comparison of HOD, CPF and $B^2R^2$ algorithms (with unbounded noise) in terms of MSE when recovering a bandlimited signal from modulo samples with  $\lambda$ = 1.25 and OF = 3,6. For a given SNR and OF, $B^2R^2$ has lowest MSE.}
	\label{Fig:unbounded}
\end{figure}
\subsection{Simulated Results}
In this section, we compare our $B^2R^2$ algorithm with the \emph{higher-order differences} (HOD) approach \cite{unlimited_sampling17, uls_tsp} and \emph{Chebyshev polynomial filter}-based (CPF) method \cite{uls_romonov}. We consider the noise measurements as in \eqref{eq: noisy_samples} for a simulation data. In the simulations, $\lambda$ is set to be $1.25$ as in the hardware. We normalize the bandlimited signals to have maximum amplitude of $10$. The SNR is calculated as $\text{SNR} = 20 \log\left(\frac{||y_{\lambda}(n T_s)||}{||v(n T_s)||}\right)$. The reconstruction accuracy of different methods is compared in terms of normalized mean-squared error (MSE) as $ \frac{\sum |y(nT_s) - \hat{y}(n Ts)|^2}{\sum |y(nT_s)|^2}$, where $\hat{y}(n T_s)$ estimate of $y(n T_s)$. For different noise settings and over-sampling factors (OFs), we considered 100 independent noise realizations and calculated the average MSE for them. We first consider quantization noise and then present results for unbounded noise.

\begin{figure}[!t]
    \centering
    \includegraphics[width=0.3\textwidth]{IEEE_TAES_v1/Figs/Signal Generator.png}
    \caption{Bandlimited signal generator.}
    \label{fig:UDRSignalGen}
\end{figure}

 First, we consider an uniform quantizer after the sampling. The unfolding algorithms are applied on the quantized samples. The MSE in the estimation of bandlimited signals for a different number of bits and OFs is shown in Fig. ~\ref{Fig:quantization}. We observe that for a given $\text{OF}$, $B^2R^2$ algorithm results in the lowest MSE for less than 5 bits. For more than 5 bits all the algorithms, except HOD with OF = 3, perform equally well. The results show that low-resolution quantizers can be used with $B^2R^2$ algorithm for unrolling which saves both power and memory requirements.

Next, for unbounded noise, we assume that the noise measurements $v(nT_s)$ are independent and identically distributed Gaussian random variables with zero mean. The variance is set to achieve a desired SNR. We compare the methods for different values of SNR and OFs with $\lambda = 1.25$. Fig.~\ref{Fig:unbounded} shows MSE of the different algorithms for OF $= 3$ and $6$. We note that our algorithm results in lowest error for a given OF and SNR.

Given the advantages of $B^2R^2$ algorithm over the other approaches, we present the hardware results in the next section by using this method.

\begin{figure*}[!t]
	\centering
	\begin{tabular}{cc}
		\subfigure[]{\includegraphics[width=2.5in]{IEEE_TAES_v1/Figs/BL1_rec.png}\label{fig:BL1}} &
		\subfigure[]{\includegraphics[width=2.5in]{IEEE_TAES_v1/Figs/BL2_rec.png}\label{fig:BL2}}
	\end{tabular}
	\caption{Hardware results for bandlimited signals. The $B^2R^2$ algorithm is used to unfold $y_\lambda(t)$ (measured at the output of hardware) and the unfolded signal $\hat{y}(t)$ is plotted with bandlimited signal $y(t)$.}
	\label{fig:BL_ex1}
\end{figure*}

\begin{figure*}[!t]
	\centering
	\begin{tabular}{ccc}
		\subfigure[]{\includegraphics[width=2.2in]{IEEE_TAES_v1/Figs/Ex1_lpf.pdf}\label{fig:FRI11}} &
		\subfigure[]{\includegraphics[width=2.1in]{IEEE_TAES_v1/Figs/Ex2_lpf.pdf}\label{fig:FRI12}}&
		\subfigure[]{\includegraphics[width=2.1in]{IEEE_TAES_v1/Figs/Ex3_lpf.pdf}\label{fig:FRI13}}\\
		\subfigure[]{\includegraphics[width=2.1in]{IEEE_TAES_v1/Figs/Ex1_fri.pdf}\label{fig:FRI21}} &
		\subfigure[]{\includegraphics[width=2.1in]{IEEE_TAES_v1/Figs/Ex2_fri.pdf}\label{fig:FRI22}}&
		\subfigure[]{\includegraphics[width=2.1in]{IEEE_TAES_v1/Figs/Ex3_fri.pdf}\label{fig:FRI23}}
	\end{tabular}
	\caption{Hardware results for FRI signals: Top row shows three examples of lowpass filtered FRI signals $y(t)$, modulo outputs $y_\lambda(t)$, and unfolded signals $\hat{y}(t)$; bottom row shows true FRI signal $f(t)$ and its estimate $\hat{f}(t)$.}
	\label{fig:FRI_ex}
\end{figure*}

\subsection{Hardware Results}
In this section, we present results from the hardware.
Since bandlimited signals are input to the hardware , we fist present results for them and then show results for FRI signals. If the hardware and unfolding algorithm is able to recover the bandlimited signals with high accuracy than it will leads to better reconstruction of the FRI signals. In all these experiments we set $\lambda = 1.25$ V and the cutoff frequency of the lowpass filter is 1 kHz. We observe that for frequencies less than or equal to 1 kHz, out hardware is able to reliably fold the signal. The Nyquist rate of the signal is 2 kHz. But for unfolding we need to oversample the signal. In all these experiments, we used $B^2R^2$ algorithm with OF = 5 which results in sampling rate of 10 kHz. Further, $y(t)$ and $y_\lambda(t)$ are measured from the hardware through an oscilloscope for processing by the algorithms.

We first consider the bandlimited signals. For generating bandlimited or lowpass signals we used a Arduino micro-controller (See Fig.~\ref{fig:UDRSignalGen}) which convert the digital signal to an analog signal via a DAC. The digital signals were generated using MATLAB software. In Fig.~\ref{fig:BL_ex1}, we show folding and reconstruction of two bandlimited signals. These signals have maximum amplitude of 5 V. We observe the signals are restricted to $[-\lambda, \lambda]$ by the modulo hardware and the algorithm was able to recover the true signal from the folded samples. The reconstructed signal has slightly larger amplitude compared to the true signal which is result of scaling within the hardware.

Next, we consider reconstruction of FRI signals from modulo samples. To generate the FRI signals, we consider $h(t)$ to be a sort pulse of bandwidth 30 kHz (Nyquist rate = 60 kHz). We consider three examples with $L=2, 3,$ and 5. The amplitudes and time delays are generated randomly. The maximum time delay is $T_0 = 0.1$ sec. Once generated, the FRI signal is lowpass filtered with a cutoff frequency of 1 kHz. Up to filtering operation, MATLAB is used and then Arduino micro-controller is used to generate the analog version of the filtered FRI signals. The signal is then folded using the hardware and folded signals are sampled. The sampling rate is 10 kHz which is five times higher than the sampling rate of the lowpass signal. Still the rate is six times lower than the Nyquist rate and hence the system operates at sub-Nyquist rate. The setup satisfies the conditions in \eqref{eq:sampling_rate} for $L=2, 3,$ and 5.

We first apply $B^2R^2$ algorithm to unfold the signal and then used ESPRIT \cite{paulraj_esprit} to estimate the time delays and amplitudes of the FRI signals. We show FRI signal sampling and reconstruction in Fig.~\ref{fig:FRI_ex} where the top row shows LPF output $y(t)$, folded signal (output of the modulo hardware) $y_\lambda(t)$, and unfolded signals $\hat{y}(t)$. The bottom row shows location and amplitude of the true signal $f(t)$ and estimated FRI signal $\hat{f}(t)$. The maximum error in the estimation of time delay $-15$ dB which shows that the system can be used in applications like radar and ultrasound imaging.

\section{Conclusions}
We considered the problem of recovering FRI signals from low-pass filtered, modulo samples. We presented a hardware prototype for the modulo folding system and show that for different bandlimited and FRI signals, the hardware is able to faithfully fold the signal. We also  address the time delay issue of the modulo system and presented a hardware solution for the same. The overall system operates at six times below the Nyquist rate which enables one to use low rate, low-dynamic range, power efficient ADCs.

\bibliographystyle{IEEEtaes}

\section{INTRODUCTION}
Sampling plays a key role in efficiently processing real-world analog signals on digital signal processors. Analog to digital converters (ADCs) are used to implement sampling in the hardware. A key parameter of an ADC is its sampling rate. ADCs with high sampling rates are power-consuming and expensive, making them unsuitable for portable devices such as hand-held ultrasound devices. Hence, it is desirable to reduce the sampling rate. Signals with finite rate of innovation (FRI) have few degrees of freedom which aids in sub-Nyquist sampling \cite{eldar_2015sampling}. That is, signal is sampled at a rate much lower than the Nyquist rate \cite{shannon, nyquist} and hence low power ADCs could be used. FRI model is ubiquitous in several time of flight applications \cite{bajwa_radar, bar_radar,filho201seismic,rip,carter_sonar,eldar_sos,eldar_beamforming, sunil} where the signal of interest is represented as a linear combination of delayed copies of a known pulse. Thus, the desired information lies in the amplitudes and time delays of the pulse, which amounts to a few degrees of freedom.

Most existing works in the context of FRI sampling focus on reducing the ADC's sampling rate by using the signal structure \cite{vetterli, eldar_sos, fri_strang, blu_moms, mulleti_kernal} and ignores other aspects of the ADC.
The dynamic range of an ADC plays a crucial role in sampling an analog signal. ADC's dynamic range should generally be larger than the signal's; otherwise, the signal gets clipped. A few approaches exist to recover the true samples from clipped ones for bandlimited signals \cite{marks_clipping2, marks_clipping1}. These approaches rely on the correlation among the samples when they are measured at a very high rate compared to the Nyquist rate. The requirement of a high sampling rate is a drawback of these approaches. In addition, theoretical guarantees are missing, and it is unclear how many clipped samples can be recovered.

There are several preprocessing approaches such as automatic gain control (AGC) \cite{perez2011automatic,mercy1981review}, companding \cite{landau_compander,landau_distorted_bl}, and modulo folding \cite{uls_tsp,uls_romonov,uls_sparse,bhandari2021unlimited,eyar_moduloicassp}, that can be used prior to sampling to avoid clipping. Among these, modulo folding is most recent approach that need not be differentiable like companding and does not suffer from stability issues of the feedback amplifiers used in AGC. In the modulo framework, the signal is folded to lie within ADC's dynamic range and then the folded signal is sampled by using a conventional ADC. Theoretical guarantees for recovering bandlimited signals from folded samples are presented in \cite{uls_tsp,uls_identifiability}. The results states that the bandlimited signals can be uniquely recovered from folded samples provided that they are sampled above the Nyquist rate.

Several algorithms for \emph{unfolding} or recovering the true samples of bandlimited signals from modulo or folded samples are presented in \cite{uls_tsp,uls_romonov, eyar_moduloicassp}. These unfolding algorithms can be compared in terms of sampling rate, amount of unfolding they can handle, and noise robustness. It is shown that the method proposed in \cite{eyar_moduloicassp} has lowest reconstruction error for a given sampling rate, noise level, and signal's amplitude level compared to the algorithms presented in \cite{uls_tsp,uls_romonov}. The algorithm proposed in \cite{uls_tsp} requires almost 17-times higher sampling rate than the Nyquist rate but it is independent of the dynamic range of the ADC. Whereas, the approaches in \cite{uls_romonov, eyar_moduloicassp} requires the knowledge of ADC's dynamic range. Modulo sampling is also extended to different problems and signal models such as periodic bandlimited signals \cite{bhandari2021unlimited}, wavelets \cite{uls_wavelet}, mixture of sinusoids \cite{uls_sinmix}, finite-rate-of-innovation signals \cite{uls_fri}, multi-dimensional signals \cite{uls_md}, sparse vector recovery \cite{uls_gamp, uls_sparsevec}, direction of arrival estimation problem \cite{uls_doa}, computed tomography \cite{uls_radon}, and graph signals \cite{uls_graph}.

While theoretical guarantees and algorithms of any new sampling approach are always well researched but the question of whether they work in practice is difficult to answer. For modulo sampling, there exists a few hardware prototypes. For example, high-dynamic-range ADCs, also known as \emph{self-reset} ADCs, are discussed in the context of imaging \cite{sradc_park, sradc_sasagwa, sradc_yuan, krishna2019unlimited}. These hardware architectures measure additional information such as the amount of folding for each sample, or, the sign of the folding together with the folded samples. The additional information might enable simpler recovery but at the expense of complex circuitry. Importantly, additional bits are required during the quantization process to store or transmit the side information.

Krishna et al. presented a hardware prototype which encode the side-information by using two bits \cite{krishna2019unlimited}. The architecture is designed to record sign of the slope of the signal at each sampling instant when the sample lies outside ADC's dynamic range. In a conventional ADC, a sample and hold (S/H) circuit is used to hold the sampled value for a prescribed period of time during which quantization is performed on the sample. To realize the modulo sampling, a folding circuit is used after S/H \cite{krishna2019unlimited}. Hence, the S/H circuit has to hold the sampled value for folding and quantization, which results in a larger folding time compared to a conventional ADC. A large holding time results in slower ADC and hence it may not be useful for wideband application.

The Modulo hardware prototypes where the modulo part is implemented prior to sampler are presented in \cite{bhandari2021unlimited,Bhandari:2022:J,mod_hyst}. Since the modulo circuit is not part of the hold time, the ADC could be faster than the hardware realization in \cite{krishna2019unlimited}.  In \cite{mod_hyst}, the authors discussed a few implementation issues of modulo hardware such as hysteresis and folding transients, and proposed algorithmic solutions to mitigate them. Both these issues can also be addressed by careful calibration and by using high precision components. In \cite{Bhandari:2022:J}, Bhandari showed reconstruction of FRI signals by using a modulo hardware. In \cite{bhandari2021unlimited,Bhandari:2022:J,mod_hyst}, rather than providing details of the hardware circuitry the authors are focused on different signal models, hardware-limitations, and algorithms. They showed that the modulo hardware is able to fold low frequency signals which are 10-12 times larger than the ADC's dynamic range.

In this paper, we present a modulo hardware prototype which can be used in low-power time-of-flight applications, and show that by using our algorithm \cite{eyar_moduloicassp} it is able to faithfully reconstruct FRI signals.
In the following, we present our contributions and the salient features of our hardware system.
\begin{itemize}
    \item As an initial step, we design our hardware components in such a way that they can fold the signals upto 5KHz.

    Note that none of the existing hardwares handles such frequency input signals.
    \item Our hardware prototype is designed to operate prior to the sampler unlike the hardware in  \cite{krishna2019unlimited} which operates in the hold part of the sampler. Hence, the proposed system can use faster ADCs with smaller hold time.
    \item Modulo folding is realized through a feedback mechanism. The time instants at which the input signal goes beyond the ADC's dynamic range, a trigger signal is generated by using a set of comparators. The trigger then activates a direct-current (DC) generator that adds to the input signal to bring it to stay within the dynamic range. This feedback mechanism introduces a finite time delay between the trigger and addition operation. The delay has an undesirable effect and it causes a part of the input signal to stay beyond the dynamic range.
    We address this key issue of the hardware which was not considered in the previous works.
    By using smoothness of the signal and time delay of the feedback loop, we show that by changing the thresholds of comparators the delay issue can be mitigated. Specifically, by using tunable threshold voltages at the comparators, time delay issues can be resolved for signals with different bandwidths.
    \item To show an application of the hardware, we consider sampling and reconstruction of FRI signals. We use a lowpass filter (LPF) prior to modulo system as a sampling kernel. The filter removes unwanted information in the signal and allows sub-Nyquist sampling. The filtered signal is folded by the designed hardware and then sampled. For estimating the FRI parameters, the samples are first unfolded by using our algorithm presented in \cite{eyar_moduloicassp} and then the parameters are estimated by using annihilating filter approach. By using the fact that our algorithm operates at lowest possible rate, we show that FRI parameters can be estimated sub-Nyquist samples. In particular, we show that the system operates at five times the rate of innovation which is much lower than the Nyquist rate of the signal.
\end{itemize}

The paper is organized as follows. In the next section, we discuss the FRI signal model and its sampling and reconstruction framework in the presence of modulo hardware. In Section III, we present the actual hardware system by explaining its working principle and discussing the components of the system. In Section IV, we show the signal folding and reconstruction abilities of the hardware, and then the conclusion is followed.

\section{Signal Model and System Description}
In this section, we first introduce the FRI signal model and then discuss its sampling and reconstruction framework with modulo ADC.
\subsection{FRI Signal Model}
Consider an FRI signal consisting of stream of $L$ pulses:
\begin{align}
	f(t) = \sum_{\ell=1}^L a_\ell h(t-t_\ell),
	\label{eq:fri1}
\end{align}
where the pulse $h(t)$ a real-valued known pulse. We assume that $\{a_\ell\}_{\ell = 1}^L$ are real-valued and $\{t\}_{\ell = 1}^L \subset (0, T_0] \subset \mathbb{R}$ for a known $T_0$.

The FRI signal model in \eqref{eq:fri1} is encountered in several scientific applications such as radar imaging \cite{bar_radar, bajwa_radar, sunil}, ultrasound imaging \cite{eldar_sos,eldar_beamforming,mulleti_icip}, light detection and ranging (LIDAR) \cite{castorena_lidar}, time-domain optical-coherence tomography (TDOCT) \cite{blu_oct}, and other time-of-flight imaging systems. In these applications,  $h(t)$ is the transmitted pulse and $\{a_\ell \,h(t-t_\ell)\}_{\ell=1}^{L}$ constitute the reflections from $L$ point targets. The amplitudes $\{a_\ell\}_{\ell = 1}^L$ depend on the sizes of the targets and the delays $\{t\}_{\ell = 1}^L$ are proportional to the distances of the targets from the transmitter. Here $T_0$ denotes maximum time delay of the targets. The signal $f(t)$ is specified by $\{a_\ell, t_\ell\}_{\ell=1}^L$ and can be reconstructed from its sub-Nyquist measurements acquired using an appropriate sampling kernel \cite{vetterli,eldar_sos,fri_strang, mulleti_kernal}. The reconstruction is generally carried out in frequency domain as discussed next.

\subsection{Fourier-Domain Reconstruction}
Consider uniform samples of continuous-time Fourier transform of $f(t)$ given as
\begin{align}
	F(k \omega_0) = \int f(t) e^{-\mathrm{j} k\omega_0 t} \mathrm{d}t = H(k \omega_0) \sum_{\ell = 1}^L a_\ell \, e^{-\mathrm{j} k\omega_0 t_\ell},
	\label{eq:F}
\end{align}
for $k \in \mathcal{K}$. Here $H(\omega)$ is the Fourier transform of $h(t)$ and $\mathcal{K}$ is an integer set. In \eqref{eq:F}, $\omega_0>0$ denotes sampling interval in the frequency domain. Next, consider the following samples
\begin{align}
	S(k\omega_0) = \frac{F(k\omega_0)}{H(k\omega_0)} =  \sum_{\ell = 1}^L a_\ell \, e^{-\mathrm{j}k\omega_0 t_\ell},
	\label{eq:Skomega}
\end{align}
where we assume that $H(k \omega_0) \neq 0$ for $k \in \mathcal{K}$. In practice, the pulse $h(t)$ has small time support and hence, large bandwidth. Hence, for a finite set $\mathcal{K}$ it is possible to choose a set of frequencies $\{k \omega_0\}_{ k \in \mathcal{K}}$ such that $H(k \omega_0) \neq 0$. It can be shown that $2L$ consecutive samples of $S(k\omega_0)$ are sufficient to uniquely identify $\{a_\ell, t_\ell\}_{\ell=1}^L$ if $\omega_0 = \frac{2\pi}{T_0}$ \cite{eldar_2015sampling}. {\color{blue}{}In practice, high-resolution spectral estimation methods, such as the annihilating filter (AF) or Prony's method and its variants \cite{prony, plonka}, multiple signal classification \cite{schmidt_music, barabell_rmusic, bdrao_rmusic}, matrix-pencil method \cite{sarkar_mp}, estimation of signal parameter via rotational invariance technique (ESPRIT) \cite{paulraj_esprit}, etc., have been deployed for FRI parameter estimation. }

Since $h(t)$ is known, $H(k\omega_0), k \in \mathcal{K}$ can be calculated in advance. Hence, to compute $S(k\omega_0), k \in \mathcal{K}$ and then to estimate the FRI parameters, $F(k\omega_0), k \in \mathcal{K}$ has to be determined. Next, we discuss a lowpass filter (LPF) based sampling framework to determine these Fourier samples.

\subsection{LPF-Based Sub-Nyquist Sampling}
\label{sec:lpf}
In this section, we discuss a LPF-based sampling mechanism for FRI signals. Let $g(t)$ denotes an ideal lowpass filter with cutoff frequency $\omega_c$ rad/sec. In the frequency-domain we have that $G(\omega) = 1$ for $\omega \in [-\omega_c, \omega_c]$ and zero for the rest of the frequencies. Let $y(t)$ denotes response of the LPF to the input $f(t)$, that is, $y(t) = (f*g)(t)$, where $*$ denotes linear convolution operation. Consider an ADC with dynamic range $[-\lambda, \lambda]$ and sampling rate $\omega_s = \frac{2\pi}{T_s}$ rad/sec. By assuming that  $\|y(t)\|_{\infty}\leq \lambda$, uniform samples at the output of ADC are given as $y(nT_s), n \in \mathbb{Z}$. Then uniform measurements of discrete-time Fourier transform (DTFT) of the samples are given as
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) = \sum_{n \in \mathbb{Z}}y(nT_s)\,e^{\mathrm{j} k\omega_0 n T_s}, \quad k \in \mathcal{K}.
	\label{eq:y_dtft}
\end{align}
By using relationship between DTFT of samples $y(nT_s)$ and CTFT of $y(t)$ we have
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) &= \frac{1}{T_s}\sum_{m \in \mathbb{Z}} Y(k\omega_0 + m \omega_s), \nonumber \\
	&= \frac{1}{T_s}\sum_{m \in \mathbb{Z}} F(k\omega_0 + m \omega_s) \,G(k\omega_0 + m \omega_s),
		\label{eq:y_dtft2}
\end{align}
where we used the fact that $Y(\omega) = F(\omega)\,G(\omega)$. Next, consider the following conditions on the sampling rate and cutoff frequency of the filter
\begin{align}
	\omega_s \geq 2\omega_c, \quad \text{and} \quad \omega_c \geq K \omega_0,
	\label{eq:sampling_rate}
\end{align}
where $K \geq L$. Then by choosing $\mathcal{K} = \{-K, \cdots, K\}$, \eqref{eq:y_dtft2} can be written as
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) = F(k\omega_0), \quad k \in \mathcal{K},
	\label{eq:y_dtft3}
\end{align}
where we used the fact that $G(k\omega_0) = 1$ in these settings. The relationship \eqref{eq:y_dtft3} shows that the desired Fourier samples of $f(t)$ are determined from the samples of LPF by assuming that the conditions in \eqref{eq:y_dtft2} are satisfied. Hence, FRI parameters can be determined from the samples of the lowpass filter. A LPF-based sampling for FRI signal was used in \cite{vetterli,uls_sparse} but with a periodic FRI signal model. With perodization, a finite number of time samples are sufficient to determine the desired Fourier measurements, whereas, countable infinite measurements are required in aperiodic settings consider here.

The bandwidth of the pulse $h(t)$ and hence that of the FRI signal $f(t)$ could be very large. But the sampling rate $\omega_s$ is independent of the pulse and could be much smaller than its bandwidth which shows the FRI signal could be reconstructed from sub-Nyquist samples.

The sub-Nyquist sampling framework discussed assumes that $\|y(t)\|_{\infty}\leq \lambda$, in other words, the framework assumes that the dynamic range of the ADC is greater than that of the signal to be sampled. However, this condition may not be always true. Specifically, the amplitude range of the filtered signal $y(t)$ could be larger than ADC's dynamic range. In such a scenario, a direct sampling would lead to clipping of samples which is undesirable. To avoid clipping, a modulo operator is employed prior to sampling as discussed next.

\begin{figure*}
	\centering
	\includegraphics[width=6.5 in]{Figs/FRI_US}
	\caption{A schematic of modulo-sampling and reconstruction of FRI signals.}
	\label{fig:fri_framework}
\end{figure*}

\subsection{Modulo-Folding}
To avoid clipping, a modulo folding operator $\mathcal{M}_\lambda(\cdot)$ is used after LPF and before the ADC. The operator folds $y(t)$ to stay within ADC's dynamic range $[-\lambda, \lambda]$. The output of the modulo operator in response to input $y(t)$ is given as
\begin{equation}
 y_\lambda(t) =	\mathcal{M}_{\lambda}(y(t)) = (y(t)+\lambda)\,\, \text{mod}\,\, 2\lambda -\lambda.
	\label{eq:mod_opp}
\end{equation}
The folded signal is then sampled by the ADC to have measurements $y_\lambda(nT_s)$. Since modulo folding is a nonlinear operation, one can not directly apply DTFT on the samples to compute Fourier measurements of the FRI signal for its reconstruction. Hence, the true or unfolded samples $y(nT_s)$ are estimated from the folded ones $y_\lambda(nT_s)$ by applying an unfolding algorithm. There exist several unfolding methods for bandlimited signals \cite{uls_tsp, uls_romonov,eyar_moduloicassp}.
The sampling rate for unfolding varies for different algorithms and generally, is larger than the minimum sampling rate required for FRI signal recovery (cf. \eqref{eq:sampling_rate}).
Hence, the overall system operates on a higher sampling rate than that without a modulo case. However, if the overall sampling rate is much lower than the bandwidth of the FRI signal then the system operates at a sub-Nyquist rate. We show that this is indeed true when we apply our unfolding algorithm proposed in \cite{eyar_moduloicassp}.

An end-to-end modulo sampling framework for FRI signal sampling and reconstruction is shown in Fig.~\ref{fig:fri_framework}. The sampler or ADC together with the modulo block is termed as modulo-ADC.
Modulo-ADCs are able to sample signals beyond their dynamic range without clipping and hence they are termed as high-dynamic range ADCs. Alternatively, an ADC with a  much lower dynamic range can be used to sample signals with larger amplitudes. Sub-Nyquist sampling and low-dynamic range requirements significantly reduce the power consumption and cost of the ADC.

The modulo folding block is key component of the high-dynamic range ADC and we discuss its hardware implementation in the next section.

\begin{figure}
	\centering
	\includegraphics[width= 3 in]{Figs/folding}
	\caption{Folding principle}
	\label{Fig:folding}
\end{figure}
\section{Modulo Hardware Prototype}
In this section, we discuss our modulo hardware prototype. First, we explain the working principle of the modulo block and explain how its design and then discuss the hardware realization.
\subsection{Working Principle of Modulo Block}
Principle of computing $y_\lambda(t)$ from $y(t)$ is shown by block-diagram in Fig.~\ref{Fig:folding}. The system comprises of an adder $S$, a direct-current voltage generator (DC-VG), and two comparators $C_1$ and $C_2$. To understand the working let us first assume that for some time instant $t_1$, we have that $|y(t)|<\lambda$ for $t<t_1$. Hence $y_\lambda(t) = y(t)$ and $z(t) = 0$ for $t<t_1$. At $t=t_1$, let $|y(t)|$ crosses $\lambda$. If $y(t_1)>\lambda$, then the comparator $C_1$ triggers a positive value or else, $C_2$ triggers a negative value. The DC-VG is designed such that for every positive value input it reduces its output signal level by $-2\lambda$, whereas, for negative value it increases its output voltage by $2\lambda$. Hence, in the current example, DC-VG generates signal $z(t) = \text{sgn}(y_\lambda(t_1)) 2\lambda u(t-t_1)$ where $u(t)$ is unit-step function.
In this way by adding or subtracting (by using $S$) constant DC signals from $y(t)$ whenever it crosses dynamic range $[-\lambda, \lambda]$, the amplitude levels of $y_\lambda(t)$ are kept within ADC's dynamic range.

\begin{figure}[!h]
	\centering
	\begin{tabular}{c}
		\subfigure[]{\includegraphics[width=2.5in]{IEEE_TAES_v1/Figs/Up_2mS.png}\label{fig:Up_2mS}} \\
		\subfigure[]{\includegraphics[width=2.5in]{IEEE_TAES_v1/Figs/Up_2uS.png}\label{fig:Up_2uS}} \\
		\subfigure[]{\includegraphics[width=2.5in]{IEEE_TAES_v1/Figs/Down_2uS.png}\label{fig:Down_2uS}}
	\end{tabular}
	\caption{Analysis of frequency response of the folding mechanism.}
	\label{Fig:frequency_response}
\end{figure}

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3 in]{Figs/dc_vg}
	\caption{DC-VG}
	\label{Fig:dcvg}
\end{figure}

\begin{figure*}[!t]
	\centering
	\includegraphics[width=5 in]{IEEE_TAES_v1/Figs/UDR_Board_Labeled3.PNG}
	\caption{Modulo hardware board.}
	\label{Fig:hw_board}
\end{figure*}
\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[]{\includegraphics[width=2.5in]{Figs/UDRPhase2pictures500Hz}\label{fig:500_2}} \\
		\subfigure[]{\includegraphics[width=2.5in]{Figs/UDRPhase2pictures2KHz}\label{fig:2k_2}}
	\end{tabular}
	\caption{Analysis of folding ability of the modulo hardware.}
	\label{Fig:two_fold}
\end{figure}

\begin{figure}[!h]
	\centering
	\begin{tabular}{c}
		\subfigure[]{\includegraphics[width=2.5in]{Figs/500Hz}\label{fig:500_1}} \\
		\subfigure[]{\includegraphics[width=2.5in]{Figs/1KHz}\label{fig:1k_1}} \\
		\subfigure[]{\includegraphics[width=2.5in]{Figs/5KHz}\label{fig:5k_1}}
	\end{tabular}
	\caption{Analysis of frequency response of the modulo hardware.}
	\label{Fig:frequency_response}
\end{figure}

\begin{table}[h!]
		\caption{Folding Operation.}
	\centering
	\begin{tabular}{||c c c c c ||}
		\hline
		c & b & a & sgn & Counter values \\ [0.5ex]
		\hline\hline
		0 & 0 & 0 & 0~(1) & 0~(0) \\
		0 & 0 & 1 & 0~(1) & 1~(-1) \\
		0 & 1 & 0 & 0~(1) & 2~(-2) \\
		0 & 1 & 1 & 0~(1) & 3~(-3) \\
		1 & 0 & 0 & 0~(1) & 4~(-4) \\
		1 & 0 & 1 & 0~(1) & 5~(-5)\\
		1 & 1 & 0 & 0~(1) & 6~(-6)\\
		1 & 1 & 1 & 0~(1) & 7~(-7)\\
		\hline
	\end{tabular}
	\label{table:counter}
\end{table}
While the parts such as comparators $C_1$, $C_2$, and adder $S$ can be realized by using off-the-shelf components, DC-VG is a more involved system and required careful design. A detailed architecture of DC-VG is shown in Fig.~\ref{Fig:dcvg}. It consists of an up/down counter, a digital-to-analog converter (DAC), a multiplexer (MUX), and a multiplier $M$.  The role of the counter (together with DAC) is to generate a variable, but controlled DC voltage whenever there is a trigger at its input. The voltage values are set to be multiple of $2\lambda$ by using the MUX and multiplier $M$.
To elaborate the working principle, we first discuss the role of the counter and then the rest of the components.

In this particular system, we use a three-bit synchronous up/down counter. The bits from lower significant bit to higher significant bit are denoted as a, b, and c. The counter has an additional sign bit shown as sgn. With these bits, the counter can count from -7 to 7. For every positive trigger at the input the output counts up and with a negative trigger it counts down. In Table~\ref{table:counter}, we display the values of bits and the counter (denoted as counter values). The three bits (a,b, and c) of the counter are used as input to the DAC which converts the bits to analog DC voltages. Let the resolution or step size of the DAC is $\alpha$ then the output of DAC is $\alpha$ times the counter-value. To be more specific, consider the scenario where the output of counter and DAC are zero. Then for a positive (negative) trigger, the output of DAC increases (decreases) by $\alpha$. Specifically, the output of DAC, $s(t)$, is a piecewise constant signal with values that are multiples of $\alpha$. However, for folding to work, the change in the voltage should be in multiples of $2\lambda$. To ascertain that we use a MUX which outputs either $2\lambda$ or $-2\lambda$ depending on whether its input is 1 or 0. Then by multiplying the output of DAC with the output of MUX we generate $z(t)$. Next, we discuss the hardware board that realizes the folding operation discussed in this section.

\begin{table}[h!]
\centering
\caption{List of Hardware Components}
\label{table:hardware_components}
\begin{tabular}{||c c c||}
 \hline
 Component & Model Number & Make \\
 && \\ \hline
 Comparator & LM339 & Texas Instruments \\
 && \\
 UP/DOWN Counter & TEENSY4.1 & PJRC \\
 && \\
 DAC 3bits & LT1364 & Analog Devices \\
 && \\
 Analog MUX & ADG1608 & Analog Devices \\
 && \\
 Analog Multiplier & AD835 & Analog Devices \\
 && \\
 Adder & LT1364 & Analog Devices \\
  && \\ [1ex]
\hline
\end{tabular}
\end{table}
\subsection{Modulo Hardware Board}
Our modulo hardware board is shown in Fig.~\ref{Fig:hw_board} with main role of the various building components are marked. The details of the components of the hardware are listed in Table~\ref{table:hardware_components}. The board is designed for $\lambda \leq 1.25$ volts. The board can accommodate an input signal with a dynamic range between $[-4\lambda, 4\lambda]$ which implies that an ADC with our modulo hardware can sample four-times larger signals compared to its dynamic range without saturation and clipping.

We demonstrate the working of the modulo hardware by considering a sinusoidal signal $y(t) = A\, \sin(2\pi f_0 t)$ where $A$ is amplitude and $f_0$ is frequency (in Hz). In this experiment, we set $\lambda = 1.25$ and $3\lambda <A <4\lambda$. With these settings, we expect the signal to fold twice in a quarter cycle of a sinusoid. Figs.~\ref{Fig:two_fold}(a) and \ref{Fig:two_fold}(b) screenshots of an oscilloscope capturing input $y(t)$ (in yellow) and its folded output $y_\lambda(t)$ (in green) for $f_0 = 500$ Hz and $f_0 = 2$ kHz, respectively. We observed that the signals are folded back to lie within the dynamic range of the ADC as expected without clipping. The reason we choose two different frequencies is to study the frequency response of the modulo folder. As in any analog system, the response of the modulo folder too depends on the frequency or bandwidth of the input signal. Beyond a particular frequency, the foldings may not be accurate as observed in Fig.~\ref{Fig:frequency_response}. We observed that for signals of 500 Hz and 1kHz the hardware is able to fold the signal accurately. However, for $f_0 = 5$ kHz, folding instants are not symmetric for positive and negative folds. In one of our future works, we are planning to design a hardware that overcome this limitation by using hardware logical components to implement the folding counter instead of using the current up/down counter. Further, we aim to handle frequencies that are grater than 5kHz. In the next section, we discuss a couple of inaccuracies of the modulo hardware and our proposed solution to overcome those.

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3.2 in]{Figs/mod_td}
	\caption{Effect of time delay of the feedback loop on the modulo operation.}
	\label{Fig:mod_td}
\end{figure}

\subsection{Artifacts During Folding}
Errors or other artifacts that arise during folding operation in hardware could be due to various reasons. For example, in Figs.~\ref{Fig:two_fold} and \ref{Fig:frequency_response}, we observe that the amplitude of the folded signals could go beyond the dynamic range momentarily around the folding instants. This is due to the settling time of the DC-VG when voltage values change. Specifically, after switching, the voltage at the output of DC-VG overshoots and undershoots before the oscillations settle down to the expected value. This can be overcome by using a faster adder whose response time should be at least a magnitude higher than the sample rate.

Another major issue that arises in a folding ADC is a time delay in the feedback loop (See Fig.~\ref{Fig:folding}). To elaborate, consider a scenario where $y(t)<\lambda$ for $t<t_1$ and it crosses $\lambda$ at time $t_1$ as discussed earlier. To fold the output voltage to the dynamic range of the ADC, $z(t) = -2\lambda u(t-t_1)$ needs to be added to $y(t)$. However, there is a finite delay between the trigger time $t_1$ to generating $z(t)$. If the time delay is $T_d$, then $z(t) = -2\lambda u(t-t_1-T_d)$ is added which causes distortion. To illustrate this effect in Fig.~\ref{Fig:mod_td} by considering a sinusoidal signal (in blue) and its folded versions with and without delay. We observe that in the absence of any time delay ($T_d=0$) the signal folds perfectly (shown in red) to stay within the dynamic range. However, for a non-zero value of $T_d$, foldings do not take place at the folding instants and the output of the modulo operator (shown in black) still remains outside the dynamic range $[-\lambda, \lambda]$. We propose a hardware solution to address this issue.

Out solution uses the fact that with a finite time delay, the amount of overshoot of a smooth signal can be bounded. To elaborate, let us assume that the signal that undergoes modulo operation is Lipschitz continuous. Specifically, a signal $y(t)$ is Lipschitz continuous if there exists a positive real number $\mathrm{L}_y$ such that for any $T>0$ we have
\begin{align}
    |y(t) -y(t+T)|\leq \mathrm{L}_y\, T.
    \label{eq:lipschitz}
\end{align}
With the Lipschitz smoothness condition, we note that the amplitude of $y(t)$ can not change more than $\mathrm{L}_y\, T_d$ between any folding instant and time of its effect to take place. Hence, if we choose dynamic range of the ADC to be $[-(\lambda+\Delta \lambda), (\lambda+\Delta \lambda)]$ where $\Delta \lambda = \mathrm{L}_y\, T_d$ then the signal will not clip. We show this extended dynamic region in the illustrative example in Fig.~\ref{Fig:mod_td}. Alternatively, instead of increasing ADC's dynamic range, one can keep it to be $[-\lambda, \lambda]$ and reduce the threshold values for comparators. In this case, $C_1$ will trigger when the input crosses $\lambda-\Delta \lambda$ and $C_2$ will trigger when input goes beyond $-\lambda+\Delta \lambda$. In this way, the time delay issue is addressed by the modulo circuit without altering ADC's dynamic range.

To implement the mentioned solution, the signal should be Lipschitz continuous. In our setup, the input to modulo operation is a lowpass or bandlimited signal which always satisfies the Lipschitz smoothness condition \cite{bl_bound}. For a bandlimited signal $y(t)$ its Lipschitz constant $\mathrm{L}_y$ is directly proportional to its bandwidth $\omega_c$ which is the same as the cutoff frequency of the LPF.
Hence, for a given value $\Delta \lambda$ and $T_d$ (both depend on the modulo circuit), $\mathrm{L}_y = \Delta \lambda/T_d$ is fixed and this restricts the maximum frequency of the input signal that can be faithfully folded. In the current design, we chose to implement the counter management by a TEENSY micro-controller which results in a time delay of $1 \mu$s which enable the hardware to support a wide range of frequencies with no need to modify the hardware components. In order to support higher frequencies, alternative design strategies with a faster response time and lower delay should be used.

\section{Results}
In this section, we show the signal reconstruction ability of the modulo hardware described in the previous section. From Fig.~\ref{fig:fri_framework}, we understood that the signal reconstruction ability is a function of LPF $g(t)$, modulo circuit $\mathcal{M}_\lambda(\cdot)$, ADC or sampler, unfolding algorithm, and parameter estimation method. Any error in the estimation of FRI parameters is a result of flaws and limitations of the hardware realizations and limitations of the algorithms in the presence of measurement noise. For example, ideally $g(t)$ should have infinite impulse response, however, only a truncated version could be realizable in hardware. The truncation will result in errors while determining the Fourier samples of the FRI signal (See Section~III.\ref{sec:lpf}). Similarly, quantization plays a role when a finite resolution quantizer is used after the sampler. In addition, all the hardware components contribute to different types of noise. We model all these noises and inaccuracies as additive noise at the output of the sampler. Specifically, the noisy measurements are given as
 \begin{align}
            \tilde{y}_{\lambda}(n T_s) = {y}_{\lambda}(n T_s) + v(n T_s),
        \label{eq: noisy_samples}
        \end{align}
where $v(n T_s)$ is the noise term. Both unfolding and parameter estimation algorithms should be robust to different noise models. The robustness of parameter estimation methods in the presence of noise is well studied (See \cite{mulleti_kernal, stoica, eldar_sos}). In \cite{eyar_moduloicassp}, we presented comparisons of unfolding algorithms for bandlimited signals. We showed that our beyond-bandwidth residual recovery ($B^2R^2$) approach results in lower error during unfolding compared to the \emph{higher-order differences} (HOD) approach \cite{unlimited_sampling17, uls_tsp} and \emph{Chebyshev polynomial filter}-based (CPF) method \cite{uls_romonov}. Importantly, for a given sampling rate, $\lambda$, and signal to noise ratio (SNR), $B^2R^2$ method results in the lowest error for both bounded and unbounded noise models.

Before presenting hardware results, we compare the performances of the $B^2R^2$ method with HOD and CPF approaches for quantization noise and unbounded noise. We would like to point out that quantization noise was not considered in \cite{eyar_moduloicassp}. Although, the algorithms were compared for unbounded noise but the simulation settings were different than those in our hardware. Hence, for a better understanding, we compared our algorithm for unbounded noise and quantizaition  noise with the current hardware settings. In the next section, we present these simulation results and then present hardware results.

\begin{figure}[!t]
	\centering
	\includegraphics[width= 2.5 in]{IEEE_TAES_v1/Figs/quantization.png}
	\caption{Comparison of HOD, CPF and $B^2R^2$ algorithms after the quantization process in terms of MSE when recovering a bandlimited signal from modulo samples with $\lambda = 1.25$ and OF = 3,6. For a given number of bits, $B^2R^2$ has the lowest MSE.}
	\label{Fig:quantization}
\end{figure}

\begin{figure}[!t]
	\centering
	\includegraphics[width= 2.5 in]{IEEE_TAES_v1/Figs/Gaussian.png}
	\caption{Comparison of HOD, CPF and $B^2R^2$ algorithms (with unbounded noise) in terms of MSE when recovering a bandlimited signal from modulo samples with  $\lambda$ = 1.25 and OF = 3,6. For a given SNR and OF, $B^2R^2$ has lowest MSE.}
	\label{Fig:unbounded}
\end{figure}
\subsection{Simulated Results}
In this section, we compare our $B^2R^2$ algorithm with the \emph{higher-order differences} (HOD) approach \cite{unlimited_sampling17, uls_tsp} and \emph{Chebyshev polynomial filter}-based (CPF) method \cite{uls_romonov}. We consider the noise measurements as in \eqref{eq: noisy_samples} for a simulation data. In the simulations, $\lambda$ is set to be $1.25$ as in the hardware. We normalize the bandlimited signals to have maximum amplitude of $10$. The SNR is calculated as $\text{SNR} = 20 \log\left(\frac{||y_{\lambda}(n T_s)||}{||v(n T_s)||}\right)$. The reconstruction accuracy of different methods is compared in terms of normalized mean-squared error (MSE) as $ \frac{\sum |y(nT_s) - \hat{y}(n Ts)|^2}{\sum |y(nT_s)|^2}$, where $\hat{y}(n T_s)$ estimate of $y(n T_s)$. For different noise settings and over-sampling factors (OFs), we considered 100 independent noise realizations and calculated the average MSE for them. We first consider quantization noise and then present results for unbounded noise.

\begin{figure}[!t]
    \centering
    \includegraphics[width=0.3\textwidth]{IEEE_TAES_v1/Figs/Signal Generator.png}
    \caption{Bandlimited signal generator.}
    \label{fig:UDRSignalGen}
\end{figure}

 First, we consider an uniform quantizer after the sampling. The unfolding algorithms are applied on the quantized samples. The MSE in the estimation of bandlimited signals for a different number of bits and OFs is shown in Fig. ~\ref{Fig:quantization}. We observe that for a given $\text{OF}$, $B^2R^2$ algorithm results in the lowest MSE for less than 5 bits. For more than 5 bits all the algorithms, except HOD with OF = 3, perform equally well. The results show that low-resolution quantizers can be used with $B^2R^2$ algorithm for unrolling which saves both power and memory requirements.

Next, for unbounded noise, we assume that the noise measurements $v(nT_s)$ are independent and identically distributed Gaussian random variables with zero mean. The variance is set to achieve a desired SNR. We compare the methods for different values of SNR and OFs with $\lambda = 1.25$. Fig.~\ref{Fig:unbounded} shows MSE of the different algorithms for OF $= 3$ and $6$. We note that our algorithm results in lowest error for a given OF and SNR.

Given the advantages of $B^2R^2$ algorithm over the other approaches, we present the hardware results in the next section by using this method.

\begin{figure*}[!t]
	\centering
	\begin{tabular}{cc}
		\subfigure[]{\includegraphics[width=2.5in]{IEEE_TAES_v1/Figs/BL1_rec.png}\label{fig:BL1}} &
		\subfigure[]{\includegraphics[width=2.5in]{IEEE_TAES_v1/Figs/BL2_rec.png}\label{fig:BL2}}
	\end{tabular}
	\caption{Hardware results for bandlimited signals. The $B^2R^2$ algorithm is used to unfold $y_\lambda(t)$ (measured at the output of hardware) and the unfolded signal $\hat{y}(t)$ is plotted with bandlimited signal $y(t)$.}
	\label{fig:BL_ex1}
\end{figure*}

\begin{figure*}[!t]
	\centering
	\begin{tabular}{ccc}
		\subfigure[]{\includegraphics[width=2.2in]{IEEE_TAES_v1/Figs/Ex1_lpf.pdf}\label{fig:FRI11}} &
		\subfigure[]{\includegraphics[width=2.1in]{IEEE_TAES_v1/Figs/Ex2_lpf.pdf}\label{fig:FRI12}}&
		\subfigure[]{\includegraphics[width=2.1in]{IEEE_TAES_v1/Figs/Ex3_lpf.pdf}\label{fig:FRI13}}\\
		\subfigure[]{\includegraphics[width=2.1in]{IEEE_TAES_v1/Figs/Ex1_fri.pdf}\label{fig:FRI21}} &
		\subfigure[]{\includegraphics[width=2.1in]{IEEE_TAES_v1/Figs/Ex2_fri.pdf}\label{fig:FRI22}}&
		\subfigure[]{\includegraphics[width=2.1in]{IEEE_TAES_v1/Figs/Ex3_fri.pdf}\label{fig:FRI23}}
	\end{tabular}
	\caption{Hardware results for FRI signals: Top row shows three examples of lowpass filtered FRI signals $y(t)$, modulo outputs $y_\lambda(t)$, and unfolded signals $\hat{y}(t)$; bottom row shows true FRI signal $f(t)$ and its estimate $\hat{f}(t)$.}
	\label{fig:FRI_ex}
\end{figure*}

\subsection{Hardware Results}
In this section, we present results from the hardware.
Since bandlimited signals are input to the hardware , we fist present results for them and then show results for FRI signals. If the hardware and unfolding algorithm is able to recover the bandlimited signals with high accuracy than it will leads to better reconstruction of the FRI signals. In all these experiments we set $\lambda = 1.25$ V and the cutoff frequency of the lowpass filter is 1 kHz. We observe that for frequencies less than or equal to 1 kHz, out hardware is able to reliably fold the signal. The Nyquist rate of the signal is 2 kHz. But for unfolding we need to oversample the signal. In all these experiments, we used $B^2R^2$ algorithm with OF = 5 which results in sampling rate of 10 kHz. Further, $y(t)$ and $y_\lambda(t)$ are measured from the hardware through an oscilloscope for processing by the algorithms.

We first consider the bandlimited signals. For generating bandlimited or lowpass signals we used a Arduino micro-controller (See Fig.~\ref{fig:UDRSignalGen}) which convert the digital signal to an analog signal via a DAC. The digital signals were generated using MATLAB software. In Fig.~\ref{fig:BL_ex1}, we show folding and reconstruction of two bandlimited signals. These signals have maximum amplitude of 5 V. We observe the signals are restricted to $[-\lambda, \lambda]$ by the modulo hardware and the algorithm was able to recover the true signal from the folded samples. The reconstructed signal has slightly larger amplitude compared to the true signal which is result of scaling within the hardware.

Next, we consider reconstruction of FRI signals from modulo samples. To generate the FRI signals, we consider $h(t)$ to be a sort pulse of bandwidth 30 kHz (Nyquist rate = 60 kHz). We consider three examples with $L=2, 3,$ and 5. The amplitudes and time delays are generated randomly. The maximum time delay is $T_0 = 0.1$ sec. Once generated, the FRI signal is lowpass filtered with a cutoff frequency of 1 kHz. Up to filtering operation, MATLAB is used and then Arduino micro-controller is used to generate the analog version of the filtered FRI signals. The signal is then folded using the hardware and folded signals are sampled. The sampling rate is 10 kHz which is five times higher than the sampling rate of the lowpass signal. Still the rate is six times lower than the Nyquist rate and hence the system operates at sub-Nyquist rate. The setup satisfies the conditions in \eqref{eq:sampling_rate} for $L=2, 3,$ and 5.

We first apply $B^2R^2$ algorithm to unfold the signal and then used ESPRIT \cite{paulraj_esprit} to estimate the time delays and amplitudes of the FRI signals. We show FRI signal sampling and reconstruction in Fig.~\ref{fig:FRI_ex} where the top row shows LPF output $y(t)$, folded signal (output of the modulo hardware) $y_\lambda(t)$, and unfolded signals $\hat{y}(t)$. The bottom row shows location and amplitude of the true signal $f(t)$ and estimated FRI signal $\hat{f}(t)$. The maximum error in the estimation of time delay $-15$ dB which shows that the system can be used in applications like radar and ultrasound imaging.

\section{Conclusions}
We considered the problem of recovering FRI signals from low-pass filtered, modulo samples. We presented a hardware prototype for the modulo folding system and show that for different bandlimited and FRI signals, the hardware is able to faithfully fold the signal. We also  address the time delay issue of the modulo system and presented a hardware solution for the same. The overall system operates at six times below the Nyquist rate which enables one to use low rate, low-dynamic range, power efficient ADCs.

\bibliographystyle{IEEEtaes}

\section{INTRODUCTION}
Sampling plays a key role in efficiently processing real-world analog signals on digital signal processors. Analog to digital converters (ADCs) are used to implement sampling in the hardware. A key parameter of an ADC is its sampling rate. ADCs with high sampling rates are power-consuming and expensive, making them unsuitable for portable devices such as hand-held ultrasound devices. Hence, it is desirable to reduce the sampling rate.
FRI model is ubiquitous in several time of flight applications \cite{bajwa_radar, bar_radar,filho201seismic,rip,carter_sonar,eldar_sos,eldar_beamforming, sunil} where the signal of interest is represented as a linear combination of delayed copies of a known pulse. Thus, the desired information lies in the amplitudes and time delays of the pulse.
Signals with finite rate of innovation (FRI) have few degrees of freedom which aids in sub-Nyquist sampling \cite{eldar_2015sampling}. That is, signal is sampled at a rate much lower than the Nyquist rate \cite{shannon, nyquist} and hence low power ADCs could be used.

Most existing works in the context of FRI sampling focus on reducing the ADC's sampling rate by using the signal structure \cite{vetterli, eldar_sos, fri_strang, blu_moms, mulleti_kernal} and ignores other aspects of the ADC. These aspects may plays a key role in faithful sampling and reconstruction, especially when the sampling frameworks are implemented in hardware. We focus on one such aspect which arises during the hardware realization of sampling mechanism.  Specifically, we address the dynamic range issue of ADCs.
The dynamic range of an ADC plays a crucial role in sampling an analog signal. ADC's dynamic range should generally be larger than the signal's; otherwise, the signal gets clipped. A few approaches exist to recover the true samples from clipped ones for bandlimited signals \cite{marks_clipping2, marks_clipping1}. These approaches rely on the correlation among the samples when they are measured at a very high rate compared to the Nyquist rate. The requirement of a high sampling rate is a drawback of these approaches. In addition, theoretical guarantees are missing, and it is unclear how many clipped samples can be recovered.

There are several preprocessing approaches such as automatic gain control (AGC) \cite{perez2011automatic,mercy1981review}, companding \cite{landau_compander,landau_distorted_bl}, and modulo folding \cite{uls_tsp,uls_romonov,uls_sparse,bhandari2021unlimited,eyar_moduloicassp}, that can be used prior to sampling to avoid clipping. Among these, modulo folding is most recent approach that need not be differentiable like companding and does not suffer from stability issues of the feedback amplifiers used in AGC. In the modulo framework, the signal is folded to lie within ADC's dynamic range and then the folded signal is sampled by using a conventional ADC. Theoretical guarantees for recovering bandlimited signals from folded samples are presented in \cite{uls_tsp,uls_identifiability}. The results state that bandlimited signal can be uniquely recovered from its folded samples provided that they are sampled above the Nyquist rate \cite{uls_tsp,uls_identifiability}.

Several algorithms for \emph{unfolding} or recovering the true samples of bandlimited signal from a modulo or folded samples are presented in \cite{uls_tsp,uls_romonov, eyar_moduloicassp}. These unfolding algorithms can be compared in terms of sampling rate, amount of unfolding they can handle, and noise robustness. It is shown that the method proposed in \cite{eyar_moduloicassp} required a lower sampling rate even in the presence of noise compared to the algorithms presented in \cite{uls_tsp,uls_romonov}.
In particular, the algorithm proposed in \cite{uls_tsp} requires almost 17-times higher sampling rate than the Nyquist rate, whereas, the reconstruction methods in \cite{uls_romonov, eyar_moduloicassp} require sampling rate slightly above the Nyquist rate.
Moreover, the method in \cite{uls_tsp} independent of the dynamic range of the ADC. Whereas, the approaches in \cite{uls_romonov} and \cite{eyar_moduloicassp} require the knowledge of ADC's dynamic range. Modulo sampling is also extended to different problems and signal models such as periodic bandlimited signals \cite{bhandari2021unlimited}, wavelets \cite{uls_wavelet}, mixture of sinusoids \cite{uls_sinmix}, finite-rate-of-innovation signals \cite{uls_fri}, multi-dimensional signals \cite{uls_md}, sparse vector recovery \cite{uls_gamp, uls_sparsevec}, direction of arrival estimation problem \cite{uls_doa}, computed tomography \cite{uls_radon}, and graph signals \cite{uls_graph}.

While theoretical guarantees and algorithms of any new sampling approach are always well researched but the question of whether they work in practice is difficult to answer. For modulo sampling, there exists a few hardware prototypes. For example, high-dynamic-range ADCs, also known as \emph{self-reset} ADCs, are discussed in the context of imaging \cite{sradc_park, sradc_sasagwa, sradc_yuan, krishna2019unlimited}. These hardware architectures measure additional information such as the amount of folding for each sample, or, the sign of the folding together with the folded samples. The additional information might enable simpler recovery but at the expense of complex circuitry. Importantly, additional bits are required during the quantization process to store or transmit the side information.

Krishna et al. presented a hardware prototype which encode the side-information by using two bits \cite{krishna2019unlimited}. The architecture is designed to record sign of the slope of the signal at each sample that lies outside the ADC's dynamic range. In a conventional ADC, a sample and hold (S/H) circuit is used to hold the sampled value for a prescribed period of time during which quantization is performed on the sample. To realize the modulo sampling, a folding circuit is used after S/H \cite{krishna2019unlimited}. Hence, the S/H circuit has to hold the sampled value for folding and quantization, which results in a larger holding time compared to a conventional ADC. A large holding time results in slower ADC and hence it may not be useful for wideband applications.

The modulo hardware prototypes where the modulo part is implemented prior to sampler are presented in \cite{bhandari2021unlimited,Bhandari:2022:J,mod_hyst}. Since the modulo circuit is not a part of the hold time, the ADC could be faster than the hardware realization in \cite{krishna2019unlimited}.  In \cite{mod_hyst}, the authors discussed a few implementation issues of modulo hardware such as hysteresis and folding transients. Further, they proposed algorithmic solutions to mitigate them. Both these issues can also be addressed by careful calibration and by using high precision components \cite{mod_hyst}. In \cite{Bhandari:2022:J}, Bhandari showed reconstruction of FRI signals by using a modulo hardware. In \cite{bhandari2021unlimited,Bhandari:2022:J,mod_hyst}, rather than providing details of the hardware circuitry the authors are focused on different signal models, hardware-limitations, and algorithms. They showed that the modulo hardware is able to fold low frequency signals that are 10-12 times larger than the ADC's dynamic range.

In this paper, we present a modulo hardware prototype which can be used in low-power time-of-flight applications, and show that by using our algorithm \cite{eyar_moduloicassp} it is able to faithfully reconstruct FRI signals.
In the following, we present the contributions and the salient features of the proposed hardware system.
\begin{itemize}
    \item As an initial step, we design our hardware components to be able to fold signals up to 10kHz. Note that no existing hardware is capable of handling such frequency input signals.

    \item The hardware prototype is designed to perform folding operation prior to the sampler unlike the hardware in \cite{krishna2019unlimited} which operates in the hold part of the sampler.  Thus, the suggested system can utilize faster ADCs with shorter hold time.
    \item Modulo folding is realized through a feedback mechanism. The time instants at which the input signal goes beyond the ADC's dynamic range, a trigger signal is generated by using comparators. The trigger then activates a direct-current (DC) generator that adds to the input signal to bring it to stay within the dynamic range. This mechanism imposes a delay between the instance delay (when the signal amplitude exceeds the dynamic range) and the folding instance.
    We address this key issue of the hardware which is not considered in the previous works.
    By using the smoothness of the signal and time delay of the feedback loop, we demonstrate that the clipping occurred due to delay issue can be mitigated. alternately we demonstrate that by using tunable threshold voltages at the comparators, the time delay issues can be resolved for signals with different bandwidths.
    \item To demonstrate an application of the hardware capabilities, we consider sampling and reconstruction of FRI signals. We use a lowpass filter (LPF) prior to modulo system as a sampling kernel. The filter removes unwanted information in the signal and allows sub-Nyquist sampling. The filtered signal is folded by the designed hardware and then sampled. For estimating the FRI parameters, the samples are first unfolded by using our algorithm presented in \cite{eyar_moduloicassp} and then the parameters are estimated by using the annihilating filter approach. We show that FRI parameters can be estimated with sub-Nyquist samples by utilizing the fact that our algorithm operates at the lowest possible rate. In particular, we demonstrate that the system functions at five times the rate of innovation, which is significantly lower than the signal's Nyquist rate.
    \item Since the output of the LPF is a bandlimited signal, the proposed framework is also useful for modulo-sampling bandlimited signals as shown in the results.

\end{itemize}

The paper is organized as follows. In the next section, we discuss the FRI signal model and its sampling and reconstruction framework in the presence of modulo hardware. In Section III, we present the actual hardware system by explaining its working principle and discussing the components of the system. In Section IV, we show the signal folding and reconstruction abilities of the hardware, and then the conclusion is followed.

\section{Signal Model and System Description}
In this section, we first introduce the FRI signal model and then discuss its sampling and reconstruction framework with modulo ADC.
\subsection{FRI Signal Model}
Consider an FRI signal consisting of stream of $L$ pulses:
\begin{align}
	f(t) = \sum_{\ell=1}^L a_\ell h(t-t_\ell),
	\label{eq:fri1}
\end{align}
where the pulse $h(t)$ a real-valued known pulse. We assume that $\{a_\ell\}_{\ell = 1}^L$ are real-valued and $\{t_\ell\}_{\ell = 1}^L \subset (0, T_0] \subset \mathbb{R}$ for a known $T_0$.

The FRI signal model in \eqref{eq:fri1} is encountered in several scientific applications such as radar imaging \cite{bar_radar, bajwa_radar, sunil}, ultrasound imaging \cite{eldar_sos,eldar_beamforming,mulleti_icip}, light detection and ranging (LIDAR) \cite{castorena_lidar}, time-domain optical-coherence tomography (TDOCT) \cite{blu_oct}, and other time-of-flight imaging systems. In these applications,  $h(t)$ is the transmitted pulse and $\{a_\ell \,h(t-t_\ell)\}_{\ell=1}^{L}$ constitute the reflections from $L$ point targets. The amplitudes $\{a_\ell\}_{\ell = 1}^L$ depend on the sizes of the targets and the delays $\{t_\ell\}_{\ell = 1}^L$ are proportional to the distances of the targets from the transmitter. Here $T_0$ denotes maximum time delay of the targets. The signal $f(t)$ is specified by $\{a_\ell, t_\ell\}_{\ell=1}^L$ and can be reconstructed from its sub-Nyquist measurements acquired using an appropriate sampling kernel \cite{vetterli,eldar_sos,fri_strang, mulleti_kernal}. The reconstruction is generally carried out in frequency domain as discussed next.

\subsection{Fourier-Domain Reconstruction}
Consider uniform samples of continuous-time Fourier transform of $f(t)$ given as
\begin{align}
	F(k \omega_0) = \int f(t) e^{-\mathrm{j} k\omega_0 t} \mathrm{d}t = H(k \omega_0) \sum_{\ell = 1}^L a_\ell \, e^{-\mathrm{j} k\omega_0 t_\ell},
	\label{eq:F}
\end{align}
for $k \in \mathcal{K}$. Here $H(\omega)$ is the Fourier transform of $h(t)$ and $\mathcal{K}$ is an integer set. In \eqref{eq:F}, $\omega_0>0$ denotes sampling interval in the frequency domain. Next, consider the following samples
\begin{align}
	S(k\omega_0) = \frac{F(k\omega_0)}{H(k\omega_0)} =  \sum_{\ell = 1}^L a_\ell \, e^{-\mathrm{j}k\omega_0 t_\ell},
	\label{eq:Skomega}
\end{align}
where we assume that $H(k \omega_0) \neq 0$ for $k \in \mathcal{K}$. In practice, the pulse $h(t)$ has small time support and hence, large bandwidth. Hence, for a finite set $\mathcal{K}$ it is possible to choose a set of frequencies $\{k \omega_0\}_{ k \in \mathcal{K}}$ such that $H(k \omega_0) \neq 0$. It can be shown that $2L$ consecutive samples of $S(k\omega_0)$ are sufficient to uniquely identify $\{a_\ell, t_\ell\}_{\ell=1}^L$ if $\omega_0 = \frac{2\pi}{T_0}$ \cite{eldar_2015sampling}.
In practice, high-resolution spectral estimation methods, such as the annihilating filter (AF) or Prony's method and its variants
\cite{prony, plonka, schmidt_music, barabell_rmusic, bdrao_rmusic,sarkar_mp,paulraj_esprit}, have been deployed for FRI parameter estimation.

Since $h(t)$ is known, $H(k\omega_0), k \in \mathcal{K}$ can be calculated in advance. Hence, to compute $S(k\omega_0), k \in \mathcal{K}$ and then to estimate the FRI parameters, $F(k\omega_0), k \in \mathcal{K}$ has to be determined. Next, we discuss a lowpass filter (LPF) based sampling framework to determine these Fourier samples.

\subsection{LPF-Based Sub-Nyquist Sampling}
\label{sec:lpf}
In this section, we discuss an LPF-based sampling mechanism for FRI signals. Let $g(t)$ denotes an ideal lowpass filter with cutoff frequency $\omega_c$ rad/sec. In the frequency-domain we have that $G(\omega) = 1$ for $\omega \in [-\omega_c, \omega_c]$ and zero for the rest of the frequencies. Let $y(t)$ denotes response of the LPF to the input $f(t)$, that is, $y(t) = (f*g)(t)$, where $*$ denotes linear convolution operation. Consider an ADC with dynamic range $[-\lambda, \lambda]$ and sampling rate $\omega_s = \frac{2\pi}{T_s}$ rad/sec. By assuming that  $\|y(t)\|_{\infty}\leq \lambda$, uniform samples at the output of ADC are given as $y(nT_s), n \in \mathbb{Z}$. Then uniform measurements of discrete-time Fourier transform (DTFT) of the samples are given as
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) = \sum_{n \in \mathbb{Z}}y(nT_s)\,e^{\mathrm{j} k\omega_0 n T_s}, \quad k \in \mathcal{K}.
	\label{eq:y_dtft}
\end{align}
By using the relationship between DTFT of samples $y(nT_s)$ and CTFT of $y(t)$ we have
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) &= \frac{1}{T_s}\sum_{m \in \mathbb{Z}} Y(k\omega_0 + m \omega_s), \nonumber \\
	&= \frac{1}{T_s}\sum_{m \in \mathbb{Z}} F(k\omega_0 + m \omega_s) \,G(k\omega_0 + m \omega_s),
		\label{eq:y_dtft2}
\end{align}
where we used the fact that $Y(\omega) = F(\omega)\,G(\omega)$. Next, consider the following conditions on the sampling rate and cutoff frequency of the filter
\begin{align}
	\omega_s \geq 2\omega_c, \quad \text{and} \quad \omega_c \geq K \omega_0,
	\label{eq:sampling_rate}
\end{align}
where $K \geq L$. Then by choosing $\mathcal{K} = \{-K, \cdots, K\}$, equation \eqref{eq:y_dtft2} can be written as
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) = F(k\omega_0), \quad k \in \mathcal{K},
	\label{eq:y_dtft3}
\end{align}
where we used the fact that $G(k\omega_0) = 1$ in this settings. The relationship \eqref{eq:y_dtft3} shows that the desired Fourier samples of $f(t)$ are determined from the samples of LPF output by assuming that the conditions in \eqref{eq:sampling_rate} are satisfied. Hence, FRI parameters can be determined from the samples of the lowpass filter. An LPF-based sampling for FRI signal was used in \cite{vetterli,uls_sparse} but with a periodic FRI signal model. With perodization, a finite number of time samples are sufficient to determine the desired Fourier measurements, whereas, countable infinite measurements are required in aperiodic setting consider here.

The bandwidth of the pulse $h(t)$ and hence that of the FRI signal $f(t)$ could be very large. But the sampling rate $\omega_s$ is independent of the pulse and could be much smaller than its bandwidth which shows the FRI signal could be reconstructed from sub-Nyquist samples.

The sub-Nyquist sampling framework discussed assumes that $\|y(t)\|_{\infty}\leq \lambda$, in other words, the framework assumes that the dynamic range of the ADC is greater than that of the signal to be sampled. However, this condition may not be always true. Specifically, the amplitude range of the filtered signal $y(t)$ could be larger than ADC's dynamic range. In such a scenario, a direct sampling would lead to clipping of samples which is undesirable. To avoid clipping, a modulo operator is employed prior to sampling as discussed next.

\begin{figure*}
	\centering
	\includegraphics[width=6.5 in]{Figs/FRI_US}
	\caption{A schematic of modulo-sampling and reconstruction of FRI signals.}
	\label{fig:fri_framework}
\end{figure*}

\subsection{Modulo-Folding}
To avoid clipping, a modulo folding operator $\mathcal{M}_\lambda(\cdot)$ is used after LPF and before the ADC. The operator folds $y(t)$ to stay within ADC's dynamic range $[-\lambda, \lambda]$. The output of the modulo operator in response to input $y(t)$ is given as
\begin{equation}
 y_\lambda(t) =	\mathcal{M}_{\lambda}(y(t)) = (y(t)+\lambda)\,\, \text{mod}\,\, 2\lambda -\lambda.
	\label{eq:mod_opp}
\end{equation}

In general, the modulo signal can be expressed as a linear combination of the true signal and a residual signal:
        \begin{align}
            y_\lambda(t) = y(t) - z(t),
            \label{eq:resiudual}
        \end{align}
where values of the residual signal $z(t)$ are integer multiples of $2\lambda$.
The folded signal is then sampled by the ADC to have measurements $y_\lambda(nT_s)$. Since modulo folding is a nonlinear operation, one can not directly apply DTFT on the samples to compute Fourier measurements of the FRI signal for its reconstruction. Hence, the true or unfolded samples $y(nT_s)$ are estimated from the folded ones $y_\lambda(nT_s)$ by applying an unfolding algorithm. There exist several unfolding methods for bandlimited signals \cite{uls_tsp, uls_romonov,eyar_moduloicassp}.
The sampling rate for unfolding varies for different algorithms and generally, is larger than the minimum sampling rate required for FRI signal recovery (cf. \eqref{eq:sampling_rate}).
Hence, the overall system operates on a higher sampling rate than that without a modulo case. However, if the overall sampling rate is much lower than the bandwidth of the FRI signal then the system operates at a sub-Nyquist rate. We show that this is indeed true when we apply our unfolding algorithm proposed in \cite{eyar_moduloicassp}.

An end-to-end modulo sampling framework for FRI signal sampling and reconstruction is shown in Fig.~\ref{fig:fri_framework}. The sampler or ADC together with the modulo block is termed as modulo-ADC.
Modulo-ADCs are able to sample signals beyond their dynamic range without clipping and hence they are termed as high-dynamic range ADCs. Alternatively, an ADC with a  much lower dynamic range can be used to sample signals with larger amplitudes. Sub-Nyquist sampling and low-dynamic range requirements significantly reduce the power consumption and cost of the ADC.

The modulo folding block is a key component of the high-dynamic range ADC and we discuss its hardware implementation in the next section.

\begin{figure}
	\centering
	\includegraphics[width= 3 in]{Figs/folding}
	\caption{Folding principle}
	\label{Fig:folding}
\end{figure}
\section{Modulo Hardware Prototype}
In this section, we discuss the prototype of our modulo hardware. The modulo block's working principle and design will be discussed first, followed by its hardware implementation.
\subsection{Working Principle of Modulo Block}
The principle of computing $y_\lambda(t)$ from $y(t)$ is shown by the block diagram in Fig.~\ref{Fig:folding}. The system comprises of an adder $S$, a direct-current voltage generator (DC-VG), and two comparators $C_1$ and $C_2$. To understand the working flow, let us first assume that for some time instant $t_1$, we have that $|y(t)|<\lambda$ for all $t<t_1$. Hence $y_\lambda(t) = y(t)$ and $z(t) = 0$ for all $t<t_1$. At $t=t_1$, let $|y(t)|$ crosses $\lambda$. If $y(t_1)>\lambda$, then the comparator $C_1$ triggers a positive value If $y(t_1)<\lambda$, $C_2$ triggers a negative value. The DC-VG is designed such that for each positive input value, it increases its output signal level by $-2\lambda$, whereas, for negative input value, it decreases its output voltage by $2\lambda$ (as in \ref{eq:resiudual}). Hence, in the current example, DC-VG generates signal $z(t) = \text{sgn}(y_\lambda(t_1)) 2\lambda u(t-t_1)$ where $u(t)$ is unit-step function. In this way, by adding or subtracting (using $S$) constant DC signals from $y(t)$ whenever it crosses the dynamic range $[-\lambda, \lambda]$, the amplitude levels of $y_\lambda(t)$ are kept within ADC's dynamic range.

\begin{figure}[!h]
	\centering
	\begin{tabular}{c}
		\subfigure[] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Fig3_2Folding_6Vpp_3Vbias_1KHz_Up_Clr.png}\label{fig:Up_Folding}} \\
		\subfigure[] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Fig3_2Folding_6Vpp_3Vbias_1KHz_Down_Clr.png}\label{fig:Down_Folding}} \\
	\end{tabular}
	\caption{DC-VG based folding operation. (a)-(b) denote the real-time capture of an oscilloscope displaying the input signal (yellow), its folded output (green), the DC-VG signal (blue), and the C1 and C2 comparator (red) respectively.}
	\label{Fig:DC-VG_folding_mechanism}
\end{figure}

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3 in]{Figs/dc_vg}
	\caption{DC-VG}
	\label{Fig:dcvg}
\end{figure}

\begin{figure*}[!t]
	\centering
	\includegraphics[width=0.86\textwidth ]{IEEE_TAES_v1/Figs/UDR_Board_Labeled3.PNG}
	\caption{Modulo hardware board.}
	\label{Fig:hw_board}
\end{figure*}

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3.2 in]{IEEE_TAES_v1/Figs/Fig6_1KHz_10Vpp_4Folding_New_Clr.png}
	\caption{
	Live screen shot of an oscilloscope capturing the 1kHz sinusoid input signal (yellow), its folded output (green) and the DC-VG signal (blue).}
	\label{Fig:Analysis_of_folding_ability}
\end{figure}

\begin{figure}[!h]
	\centering
	\begin{tabular}{c}
		\subfigure[] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Fig7_1Folding_6Vpp_1KHz_New_Clr.png}\label{fig:1k_1}} \\
		\subfigure[] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Fig7_1Folding_6Vpp_10KHz_New_Clr.png}\label{fig:10k_1}} \\
		\subfigure[] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Fig7_1Folding_6Vpp_20KHz_New_Clr.png}\label{fig:20k_1}}
	\end{tabular}
	\caption{Analysis of frequency response of the modulo hardware (a)-(c) denote the real-time capture of an oscilloscope capturing the 1kHz, 10kHz, 20kHz, respectively, sinusoidal input signal (yellow), its folded output (green), the DC-VG signal (blue).}
	\label{Fig:frequency_response}
\end{figure}

\begin{table}[h!]
		\caption{Up/down counter operation.}
	\centering
	\begin{tabular}{||c c c c c ||}
		\hline
		c & b & a & sgn & Counter values \\ [0.5ex]
		\hline\hline
		0 & 0 & 0 & 0~(1) & 0~(0) \\
		0 & 0 & 1 & 0~(1) & 1~(-1) \\
		0 & 1 & 0 & 0~(1) & 2~(-2) \\
		0 & 1 & 1 & 0~(1) & 3~(-3) \\
		1 & 0 & 0 & 0~(1) & 4~(-4) \\
		1 & 0 & 1 & 0~(1) & 5~(-5)\\
		1 & 1 & 0 & 0~(1) & 6~(-6)\\
		1 & 1 & 1 & 0~(1) & 7~(-7)\\
		\hline
	\end{tabular}
	\label{table:counter}
\end{table}

While the parts such as comparators $C_1$, $C_2$, and adder $S$ can be realized by using off-the-shelf components, DC-VG is a more involved system and required careful design. A detailed architecture of DC-VG is shown in Fig.~\ref{Fig:dcvg}. It consists of an up/down counter, a digital-to-analog converter (DAC), a multiplexer (MUX), and a multiplier $M$.  The function of the counter, along with the DAC, is to produce a piece-wise constant DC voltage whenever a trigger is present at its input. By employing the MUX and multiplier $M$, the voltage values are configured to be multiples of $2\lambda$.
To explain the working principle, we will first discuss the function of the counter, followed by the other components.

In this particular system, we use a three-bit synchronous up/down counter. The bits from lower significant bit to higher significant bit are denoted as a, b, and c, respectively. The counter has an additional sign bit shown as sgn. With these bits, the counter can count from -7 to 7. For each positive input trigger, the output counts up, and for each negative input trigger, it counts down. In Table~\ref{table:counter}, we list the values of bits and the counter (denoted as counter values). The three bits (a,b, and c) of the counter are used as input to the DAC which converts the bits to an analog DC voltages. Let the resolution or step size of the DAC is $\alpha$ then the output of DAC is $\alpha$ times the counter-value. To be more specific, consider the scenario where the output of counter and DAC are zero. DAC's output then increases (decreases) by $\alpha$ in response to a positive (negative) trigger. DAC's output signal, $s(t),$ is a piecewise constant signal whose values are multiples of $\alpha$. For folding to function, however, the voltage change must be in multiples of $2\lambda$. Further, we employ a MUX whose output is $2\lambda$ or $-2\lambda$ depending on whether its input (sgn bit) is 1 or 0. Then, $z(t)$ is generated by multiplying the output of DAC by the output of MUX.

Fig. \ref{fig:Up_Folding} (Fig. \ref{fig:Down_Folding}) demonstrates the DC-VG based folding operation time sequence beginning with the C1 (C2) comparator trigger operation, in red, followed by $z(t)$, in blue, which results in a 2$\lambda$ increase (decrease) of $y_\lambda(t)$, in green, and keeping it within the $\pm\lambda$ ADC range.

Next, we discuss the hardware board that realizes the folding operation discussed in this section.

\begin{table}[h!]
\centering
\caption{List of Hardware Components}
\label{table:hardware_components}
\begin{tabular}{||c c c||}
 \hline
 Component & Model Number & Make \\
 && \\ \hline
 Comparator & LM339 & Texas Instruments \\
 && \\
 UP/DOWN Counter & TEENSY4.1 & PJRC \\
 && \\
 DAC 3bits & LT1364 & Analog Devices \\
 && \\
 Analog MUX & ADG1608 & Analog Devices \\
 && \\
 Analog Multiplier & AD835 & Analog Devices \\
 && \\
 Adder & LT1364 & Analog Devices \\
  && \\ [1ex]
\hline
\end{tabular}
\end{table}
\subsection{Modulo Hardware Board}
Our modulo hardware board is presented in Fig.~\ref{Fig:hw_board}, along with the roles of the major building components. Table~\ref{table:hardware_components} contains a detailed listing of the hardware's components. The board is designed for $\lambda\leq1.25$ volts or less. The board can accommodate an input signal with a dynamic range between $[-8\lambda, 8\lambda]$, which means that an ADC equipped with our modulo hardware can sample signals four times bigger than its dynamic range without saturation and clipping.

We demonstrate the working of the modulo hardware by considering a sinusoidal signal $y(t) = A\, \sin(2\pi f_0 t)$ where $A$ is amplitude and $f_0$ is frequency (in Hz). In this experiment, we set $\lambda = 1.25$ and $-4\lambda <A <+4\lambda$. With this setting, we expect the signal to fold 4 times in a half sinusoidal cycle. Fig.~\ref{Fig:Analysis_of_folding_ability} depicts screenshot of an oscilloscope capturing input $y(t)$ (in yellow) and its folded output $y_\lambda(t)$ (in green) in addition the DC-VG output signal $z(t)$ (in blue), for $f_0 = 1$kHz. We observed that the signals are folded back to lie within the dynamic range of the ADC as expected without clipping. Next we discuss the the frequency response of the modulo ADC. As in any analog system, the response of the modulo folder too depends on the frequency or bandwidth of the input signal. Beyond a particular frequency, the folding may not be accurate as demonstrated in Fig.~\ref{Fig:frequency_response}. We observed that for signals of 1kHz and 10kHz the hardware is able to fold the signal accurately. However, for $f_0 = 20$kHz, folding instants are not symmetric for positive and negative folds. In one of our future works, we are planning to design a hardware that overcomes this limitation by using a faster hardware logical components to implement the folding counter instead of using the current up/down counter. The current implementation demonstrates a proof of concept of implementing the modulo concept in the analog domain at near real life environment and paves the way for a high frequency applications which supports high dynamic range operation.

In the next section, we discuss a couple of inaccuracies of the modulo hardware and our proposed solutions to overcome those.

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3.2 in]{Figs/mod_td}
	\caption{Effect of time delay of the feedback loop on the modulo operation.}
	\label{Fig:mod_td}
\end{figure}

\subsection{Artifacts During Folding}
Errors or other artifacts that arise during folding operation in hardware could be due to various reasons. One of the major issues that arises in a modulo ADC is the time delay in the feedback loop (See Fig.~\ref{Fig:folding}). To elaborate, consider a scenario where $y(t)<\lambda$ for $t<t_1$ and it crosses $\lambda$ at time $t_1$ as discussed earlier. To fold the output voltage to the dynamic range of the ADC, $z(t) = 2\lambda u(t-t_1)$ needs to be subtracted from $y(t)$. However, there is a finite delay between the trigger time $t_1$ to generating $z(t)$. If the time delay is $T_d$, then $z(t) = 2\lambda u(t-t_1-T_d)$ is subtracted, which causes distortion. To illustrate this effect, in Fig.~\ref{Fig:mod_td}, we considered a sinusoidal signal (in blue) and its folded versions with and without delay. We observe that in the absence of any time delay ($T_d=0$) the signal folds perfectly (shown in red) to stay within the dynamic range. However, for a non-zero value of $T_d$, foldings do not take place at the folding instants and the output of the modulo operator (shown in black) still remains outside the dynamic range $[-\lambda, \lambda]$, which results in a clipped modulo operator output. However, the proposed hardware solution addresses this issue and avoids the undesired clipping as shown in Figs.~\ref{Fig:Analysis_of_folding_ability} and \ref{Fig:frequency_response}.

Our solution uses the fact that with a finite time delay, the amount of overshoot of a smooth signal can be bounded. To elaborate, let us assume that the signal that undergoes modulo operation is Lipschitz continuous. Specifically, a signal $y(t)$ is Lipschitz continuous if there exists a positive real number $\mathrm{L}_y$ such that for any $T>0$ we have
\begin{align}
    |y(t) -y(t+T)|\leq \mathrm{L}_y\, T.
    \label{eq:lipschitz}
\end{align}
With the Lipschitz smoothness condition, we note that the amplitude of $y(t)$ can not change more than $\mathrm{L}_y\, T_d$ between any folding instant and time of its effect to take place. Hence, if we choose dynamic range of the ADC to be $[-(\lambda+\Delta \lambda), (\lambda+\Delta \lambda)]$ where $\Delta \lambda = \mathrm{L}_y\, T_d$ then the signal will not clip. We show this extended dynamic region in the illustrative example in Fig.~\ref{Fig:mod_td}. Alternatively, instead of increasing ADC's dynamic range, one can keep it to be $[-\lambda, \lambda]$ and reduce the threshold values for comparators. In this case, $C_1$ will trigger when the input crosses $\lambda-\Delta \lambda$ and $C_2$ will trigger when input goes beyond $-\lambda+\Delta \lambda$. In this way, the time delay issue is addressed by the modulo circuit without altering ADC's dynamic range.

In order to apply the solution, the signal must be Lipschitz continuous. In our design, the modulo operation input signal is always a lowpass or bandlimited signal satisfying the Lipschitz smoothness condition \cite{bl_bound}. For a bandlimited signal $y(t)$ its Lipschitz constant $\mathrm{L}_y$ is directly proportional to its bandwidth $\omega_c$ which is the same as the cutoff frequency of the LPF.
Hence, for a given value $\Delta \lambda$ and $T_d$ (both depend on the modulo circuit), $\mathrm{L}_y = \Delta \lambda/T_d$ is fixed and this restricts the maximum frequency of the input signal that can be faithfully folded. In the current design, we choose to implement the counter management using a TEENSY micro-controller, resulting in a $1 \mu$s time delay. This enables the hardware to accommodate a wide range of frequencies without requiring any modifications to the hardware components.

Another issue one can observe after DC-VG switching is that the voltage at the output of DC-VG either overshoots or undershoots (refer to Fig.~\ref{Fig:Analysis_of_folding_ability}) before the oscillations settle down to the expected value. This issue may be resolved by using a faster adder $S$ whose response time should be at least a magnitude higher than the sample rate. In one of our future works, we are planning to design a hardware that overcomes this limitation.

\section{Results}
In this section, we demonstrate the modulo hardware described in the previous section's signal reconstruction capability. From Fig.~\ref{fig:fri_framework}, we found that the signal reconstruction capability is a function of LPF $g(t)$, modulo circuit $\mathcal{M}_\lambda(\cdot)$, ADC or sampler, unfolding algorithm, and parameter estimation method. Any error in the estimation of FRI parameters is a result of flaws and limitations of the hardware realizations and limitations of the algorithms in the presence of measurement noise. For example, ideally $g(t)$ should have infinite impulse response, however, only a truncated version could be realizable in hardware. The truncation will result in errors while determining the Fourier samples of the FRI signal (See Section~III.\ref{sec:lpf}). Similarly, quantization plays a role when a finite resolution quantizer is used after the sampler. In addition, all the hardware components contribute to different types of noise. We model all these noises and inaccuracies as additive noise at the output of the sampler. Specifically, the noisy measurements are given as
 \begin{align}
            \tilde{y}_{\lambda}(n T_s) = {y}_{\lambda}(n T_s) + v(n T_s),
        \label{eq: noisy_samples}
        \end{align}
where $v(n T_s)$ is the noise term. Both unfolding and parameter estimation algorithms should be robust to different noise models. The robustness of parameter estimation methods in the presence of noise is well studied (See \cite{mulleti_kernal, stoica, eldar_sos}). In \cite{eyar_moduloicassp}, we presented comparisons of unfolding algorithms for bandlimited signals. We showed that our beyond-bandwidth residual recovery ($B^2R^2$) approach results in lower error during unfolding compared to the \emph{higher-order differences} (HOD) approach \cite{unlimited_sampling17, uls_tsp} and \emph{Chebyshev polynomial filter}-based (CPF) method \cite{uls_romonov}. Importantly, for a given sampling rate, $\lambda$, and signal to noise ratio (SNR), $B^2R^2$ method results in the lowest error for both bounded and unbounded noise models.

Before presenting hardware results, we compare the performances of the $B^2R^2$ method with HOD and CPF approaches for quantization noise and unbounded noise. We would like to point out that quantization noise was not considered in \cite{eyar_moduloicassp}. Although, the algorithms were compared for unbounded noise but the simulation settings were different than those in our hardware. Hence, for a better understanding, we compared our algorithm for unbounded noise and quantizaition  noise with the current hardware settings. In the next section, we present these simulation results and then present hardware results.

\begin{figure}[!t]
	\centering
	\includegraphics[width= 2.5 in]{IEEE_TAES_v1/Figs/quantization.png}
	\caption{Comparison of HOD, CPF and $B^2R^2$ algorithms after the quantization process in terms of MSE when recovering a bandlimited signal from modulo samples with $\lambda = 1.25$ and OF = 3,6. For a given number of bits, $B^2R^2$ has the lowest MSE.}
	\label{Fig:quantization}
\end{figure}

\begin{figure}[!t]
	\centering
	\includegraphics[width= 2.5 in]{IEEE_TAES_v1/Figs/Gaussian.png}
	\caption{Comparison of HOD, CPF and $B^2R^2$ algorithms (with unbounded noise) in terms of MSE when recovering a bandlimited signal from modulo samples with  $\lambda$ = 1.25 and OF = 3,6. For a given SNR and OF, $B^2R^2$ has lowest MSE.}
	\label{Fig:unbounded}
\end{figure}
\subsection{Simulated Results}
In this section, we compare our $B^2R^2$ algorithm with the \emph{higher-order differences} (HOD) approach \cite{unlimited_sampling17, uls_tsp} and \emph{Chebyshev polynomial filter}-based (CPF) method \cite{uls_romonov}. We consider the noise measurements as in \eqref{eq: noisy_samples} for a simulation data. In the simulations, $\lambda$ is set to be $1.25$ as in the hardware. We normalize the bandlimited signals to have maximum amplitude of $10$. The SNR is calculated as $\text{SNR} = 20 \log\left(\frac{||y_{\lambda}(n T_s)||}{||v(n T_s)||}\right)$. The reconstruction accuracy of different methods is compared in terms of normalized mean-squared error (MSE) as $ \frac{\sum |y(nT_s) - \hat{y}(n Ts)|^2}{\sum |y(nT_s)|^2}$, where $\hat{y}(n T_s)$ estimate of $y(n T_s)$. For different noise settings and over-sampling factors (OFs), we considered 100 independent noise realizations and calculated the average MSE for them. We first consider quantization noise and then present results for unbounded noise.

\begin{figure}[!t]
    \centering
    \includegraphics[width=0.3\textwidth]{IEEE_TAES_v1/Figs/Signal Generator.png}
    \caption{Bandlimited signal generator.}
    \label{fig:UDRSignalGen}
\end{figure}

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3.2 in]{IEEE_TAES_v1/Figs/Up_2mS_Clr.png}
	\caption{Bandlimited folded signal.}
	\label{Fig:Bandlimited_folded_signal}
\end{figure}

 First, we consider an uniform quantizer after the sampling. The unfolding algorithms are applied on the quantized samples. The MSE in the estimation of bandlimited signals for a different number of bits and OFs is shown in Fig. ~\ref{Fig:quantization}. We observe that for a given $\text{OF}$, $B^2R^2$ algorithm results in the lowest MSE for less than 5 bits. For more than 5 bits all the algorithms, except HOD with OF = 3, perform equally well. The results show that low-resolution quantizers can be used with $B^2R^2$ algorithm for unrolling which saves both power and memory requirements.

Next, for unbounded noise, we assume that the noise measurements $v(nT_s)$ are independent and identically distributed Gaussian random variables with zero mean. The variance is set to achieve a desired SNR. We compare the methods for different values of SNR and OFs with $\lambda = 1.25$. Fig.~\ref{Fig:unbounded} shows MSE of the different algorithms for OF $= 3$ and $6$. We note that our algorithm results in lowest error for a given OF and SNR.

Given the advantages of $B^2R^2$ algorithm over the other approaches, we present the hardware results in the next section by using this method.

\begin{figure*}[!t]
	\centering
	\begin{tabular}{cc}
		\subfigure[]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/BL1_scope_11_Clr.png}\label{fig:BL1_scope}} &
		\subfigure[]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/BL2_scope_13_Clr.png}\label{fig:BL2_scope}}
	\end{tabular}
	\caption{Live screen shot of an oscilloscope capturing the input bandlimited signals (yellow) and its folded output signals (green).}
	\label{fig:BL_scopeex1}

\end{figure*}
\begin{figure*}[!t]
	\centering
	\begin{tabular}{cc}
		\subfigure[]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/BL1_rec.png}\label{fig:BL1}} &
		\subfigure[]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/BL2_rec.png}\label{fig:BL2}}
	\end{tabular}
	\caption{Hardware results for bandlimited signals. The $B^2R^2$ algorithm is used to unfold $y_\lambda(t)$ (measured at the output of hardware) and the unfolded signal $\hat{y}(t)$ is plotted with bandlimited signal $y(t)$.}
	\label{fig:BL_ex1}
\end{figure*}

\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[FRI1 live screen shot of an oscilloscope capturing the 1kHz sinusoid input signal (yellow), its folded output (green) and the DC-VG signal (blue).] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/FRI1_1_Clr.png}\label{fig:FRI1_1k}} \\
		\subfigure[]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Ex1_lpf.pdf}\label{fig:FRI_LPF1}}\\
		\subfigure[FRI1 Reconstruction.] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Ex1_fri.pdf}\label{fig:FRI1_REC}} \\

	\end{tabular}
	\caption{Reconstruction of FRI3 signal via the modulo hardware .}
	\label{Fig:FRI1}
\end{figure}

\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[FRI2 live screen shot of an oscilloscope capturing the 1kHz sinusoid input signal (yellow), its folded output (green) and the DC-VG signal (blue).] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/FRI2_1_Clr.png}\label{fig:FRI2_1k}} \\
		\subfigure[]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Ex2_lpf.pdf}\label{fig:FRI_LPF2}}\\
		\subfigure[FRI2 Reconstruction.] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Ex2_fri.pdf}\label{fig:FRI2_REC}} \\
	\end{tabular}
	\caption{Reconstruction of FRI2 signal via the modulo hardware .}
	\label{Fig:FRI2}
\end{figure}

\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[FRI3 live screen shot of an oscilloscope capturing the 1kHz sinusoid input signal (yellow), its folded output (green) and the DC-VG signal (blue).] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/FRI3_1_Clr.png}\label{fig:FRI3_1k}} \\
		\subfigure[]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Ex3_lpf.pdf}\label{fig:FRI_LPF3}}\\
		\subfigure[FRI3 Reconstruction.] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Ex3_fri.pdf}\label{fig:FRI3_REC}} \\

	\end{tabular}
	\caption{Reconstruction of FRI5 signal via the modulo hardware .}
	\label{Fig:FRI3}
\end{figure}

\subsection{Hardware Results}
In this section, we present results from the hardware.
Since bandlimited signals are input to the hardware , we first present results for them and then show results for FRI signals. If the hardware and unfolding algorithm is able to recover the bandlimited signals with high accuracy than it will leads to better reconstruction of the FRI signals. In all these experiments we set $\lambda = 1.25$ V and the cutoff frequency of the lowpass filter is 1kHz. We observe that for frequencies less than or equal to 10kHz, our hardware is able to reliably fold the signal. The Nyquist rate of the signal is 2kHz. But for unfolding we need to oversample the signal. In all these experiments, we used $B^2R^2$ algorithm with OF = 5 which results in sampling rate of 10kHz. Further, $y(t)$ (yellow) and $y_\lambda(t)$ (green) are measured from the hardware through an oscilloscope for processing by the algorithms as described in Fig. \ref{Fig:Bandlimited_folded_signal}.

We first consider the bandlimited signals. For generating bandlimited or lowpass signals we used a Arduino micro-controller (See Fig.~\ref{fig:UDRSignalGen}) which convert the digital signal to an analog signal via a DAC. The digital signals were generated using MATLAB software. Two examples of 1khz bandlimited signal are presented in Fig. \ref{fig:BL1_scope} and Fig. \ref{fig:BL2_scope}. In Fig.~\ref{fig:BL_ex1}, we show folding and reconstruction, using the $B^2R^2$ algorithm, of the two bandlimited signals that displayed in Fig. \ref{fig:BL_scopeex1}. These signals have maximum amplitude of 5V. We observe the signals are restricted to $[-\lambda, \lambda]$ by the modulo hardware and the algorithm was able to recover the true signal from the folded samples. The reconstructed signal has slightly larger amplitude compared to the true signal which is result of scaling within the hardware.

Next, we consider reconstruction of FRI signals from modulo samples. To generate the FRI signals, we consider $h(t)$ to be a short pulse of bandwidth 30kHz (Nyquist rate = 60kHz). We consider three examples with $L=2, 3,$ and 5. The amplitudes and time delays are generated randomly. The maximum time delay is $T_0 = 0.1$ sec. Once generated, the FRI signal is lowpass filtered with a cutoff frequency of 1kHz. Up to filtering operation, MATLAB is used and then Arduino micro-controller is used to generate the analog version of the filtered FRI signals. The signal is then folded using the hardware and the folded signals are sampled. The sampling rate is 10kHz which is five times higher than the sampling rate of the lowpass signal. Still the rate is six times lower than the Nyquist rate and hence the system operates at sub-Nyquist rate. The setup satisfies the conditions in \eqref{eq:sampling_rate} for $L=2, 3,$ and 5.

We first apply $B^2R^2$ algorithm to unfold the signal and then used ESPRIT \cite{paulraj_esprit} to estimate the time delays and amplitudes of the FRI signals.
In Fig.~\ref{Fig:FRI1}, Fig.~\ref{Fig:FRI2} and  Fig.~\ref{Fig:FRI3} we show sampling and reconstruction of FRI signals with $L=2,3,5$ respectively.
The FRI signals followed by a lowpass filter are presented in Fig.~\ref{fig:FRI1_1k}, Fig.~\ref{fig:FRI2_1k} and  Fig.~\ref{fig:FRI3_1k}.
The reconstruction of the lowpass signals displayed in Fig.~\ref{fig:FRI_LPF1}, Fig.~\ref{fig:FRI_LPF2} and  Fig.~\ref{fig:FRI_LPF3}, where $y(t)$ described the LPF output , $y_\lambda(t)$ is the folded signal (output of the modulo hardware), and the unfolded signals are given by $\hat{y}(t)$. Fig.~\ref{fig:FRI1_REC}, Fig.~\ref{fig:FRI2_REC} and Fig.~\ref{fig:FRI3_REC} show location and amplitude of the true signal $f(t)$ and estimated FRI signal $\hat{f}(t)$.
The maximum error in the estimation of time delay is $-15$ dB which shows that the system can be used in applications like radar and ultrasound imaging.

\section{Conclusions}
We considered the problem of recovering FRI signals from low-pass filtered, modulo samples. We presented a hardware prototype for the modulo folding system and show that for different bandlimited and FRI signals, the hardware is able to faithfully fold the signal. We also  address the time delay issue of the modulo system and presented a hardware solution for the same. The overall system operates at six times below the Nyquist rate which enables one to use low rate, low-dynamic range, power efficient ADCs.

\bibliographystyle{IEEEtaes}

\section{INTRODUCTION}
Analog-to-digital converters (ADCs) act as a bridge between real-world analog signals and digital processors on which signals can be processed efficiently. Typically, ADCs measure instantaneous uniform samples of analog signals to represent them digitally. A key parameter in such conversion is the sampling rate. Power consumption and cost of an ADC increase with the increase in the sampling rate. Hence, keeping the sampling rate as low as possible is desirable. Theoretically, the sampling rate has to be greater than the Nyquist rate for perfect reconstruction of bandlimited signals. However, in practice, the acquisition may not be ideal, and sampling has to be performed above the Nyquist rate. Apart from the sampling rate, there could be several other aspects of an ADC which play a key role in faithful sampling and reconstruction, especially when the sampling frameworks are implemented in hardware.

The dynamic range of an ADC is one such key aspect and it plays a crucial role in sampling an analog signal. Generally, ADC's dynamic range should be larger than the signal's; otherwise, the signal gets clipped. A few approaches exist to recover the true samples from clipped ones for bandlimited signals \cite{marks_clipping2, marks_clipping1}. These approaches rely on the correlation among the samples when they are measured at a very high rate compared to the Nyquist rate. The requirement of a high sampling rate is a drawback of these approaches.

There are several preprocessing approaches such as automatic gain control (AGC) \cite{perez2011automatic,mercy1981review}, companding \cite{landau_compander,landau_distorted_bl}, and modulo folding \cite{uls_tsp,uls_romonov,uls_sparse,bhandari2021unlimited,eyar_moduloicassp}, that can be used prior to sampling to avoid clipping. Among these, modulo folding is the most recent approach that need not be differentiable like companding and does not suffer from stability issues of the feedback amplifiers used in AGC. In the modulo framework, the signal is folded to lie within ADC's dynamic range, and then the folded signal is sampled by using a conventional ADC. Theoretical guarantees for recovering bandlimited signals from folded samples are presented in \cite{uls_tsp,uls_identifiability}. The results state that bandlimited signal can be uniquely recovered from its folded samples provided that they are sampled above the Nyquist rate \cite{uls_tsp,uls_identifiability}.

Several algorithms for \emph{unfolding} or recovering the true samples of bandlimited signal from a modulo or folded samples are presented in \cite{uls_tsp,uls_romonov, eyar_moduloicassp}. These unfolding algorithms can be compared in terms of sampling rate, amount of unfolding they can handle, and noise robustness. The algorithm proposed in \cite{uls_tsp} requires almost 17 times higher sampling rate than the Nyquist rate, but it is independent of the dynamic range of the ADC. Whereas the approaches in \cite{uls_romonov} and \cite{eyar_moduloicassp} operate at relatively lower sampling rates but require the knowledge of ADC's dynamic range. It is shown that the method proposed in \cite{eyar_moduloicassp} required a lower sampling rate, even in the presence of noise, compared to the algorithms presented in \cite{uls_tsp,uls_romonov}. Modulo sampling is also extended to different problems and signal models such as periodic bandlimited signals \cite{bhandari2021unlimited}, wavelets \cite{uls_wavelet}, a mixture of sinusoids \cite{uls_sinmix}, finite-rate-of-innovation (FRI) signals \cite{uls_fri}, multi-dimensional signals \cite{uls_md}, sparse vector recovery \cite{uls_gamp, uls_sparsevec}, the direction of arrival estimation problem \cite{uls_doa}, computed tomography \cite{uls_radon}, and graph signals \cite{uls_graph}.

While theoretical guarantees and algorithms of any new sampling approach are always well-researched but the question of whether they work in practice is difficult to answer. For modulo sampling, there exists a few hardware prototypes. For example, high-dynamic-range ADCs, also known as \emph{self-reset} ADCs, are discussed in the context of imaging \cite{sradc_park, sradc_sasagwa, sradc_yuan, krishna2019unlimited}. These hardware architectures measure additional information, such as the amount of folding for each sample or, the sign of the folding together with the folded samples. The additional information might enable simpler recovery but at the expense of complex circuitry. Importantly, additional bits are required during the quantization process to store or transmit the side information.

Krishna et al. presented a hardware prototype that encodes the side information by using two bits \cite{krishna2019unlimited}. The architecture is designed to record sign of the slope of the signal at each sample that lies outside the ADC's dynamic range. In a conventional ADC, a sample and hold (S/H) circuit is used to hold the sampled value for a prescribed period of time during which quantization is performed on the sample. To realize the modulo sampling, a folding circuit is used after S/H \cite{krishna2019unlimited}. In this architecture, the S/H circuit has to hold the sampled value for folding and quantization, which results in a larger holding time compared to a conventional ADC. A large holding time results in slower ADCs, and hence it may not be useful in wideband applications.

The modulo hardware prototypes where the modulo part is implemented prior to the sampler are presented in \cite{bhandari2021unlimited,Bhandari:2022:J,mod_hyst}. Since the modulo circuit is not a part of the hold time, the ADC could be faster than the hardware realization in \cite{krishna2019unlimited}.  In \cite{mod_hyst}, the authors discussed a few implementation issues of modulo hardware such as hysteresis and folding transients. Further, they proposed algorithmic solutions to mitigate them. Both these issues can also be addressed by careful calibration and by using high-precision components \cite{mod_hyst}. In all these works \cite{bhandari2021unlimited,Bhandari:2022:J,mod_hyst}, the authors are focused on different signal models, hardware limitations, and algorithms rather than providing details of the hardware circuitry. It was shown that the modulo hardware is able to fold low-frequency signals that are 10-12 times larger than the ADC's dynamic range.

In this paper, we present a modulo hardware prototype that can be used in low-power time-of-flight applications and show that by using our algorithm \cite{eyar_moduloicassp} it is able to faithfully reconstruct FRI signals.
In the following, we present the contributions and the salient features of the proposed hardware system.
\begin{itemize}
    \item As an initial step, we design our hardware components to be able to fold signals up to 10kHz. Note that no existing hardware is capable of handling such wideband signals.

    \item The hardware prototype is designed to perform folding operation prior to the sampler unlike the hardware in \cite{krishna2019unlimited} which operates in the hold part of the sampler.  Thus, the suggested system can utilize faster ADCs with shorter hold times.
    \item In the proposed hardware prototype, modulo folding is realized through a feedback mechanism. At the time instants when the input signal goes beyond the ADC's dynamic range, a trigger signal is generated by using comparators. The trigger then activates a direct-current (DC) generator that adds to the input signal to bring it to stay within the dynamic range. This mechanism imposes a delay between the instance delay (when the signal amplitude exceeds the dynamic range) and the folding instance.
    We address this key issue of the hardware which is not considered in the previous works.
    By using the smoothness of the signal and the time delay of the feedback loop, we demonstrate that the clipping that occurred due to a delay issue can be mitigated. Alternately we demonstrate that by using tunable threshold voltages at the comparators, the time delay issues can be resolved for signals with different bandwidths.
    \item By using our algorithm presented in \cite{eyar_moduloicassp}, we show the reconstruction of bandlimited signals from their folded samples measured through the hardware. We use a bandlimited signal generator which is realized using an Arduino microcontroller. We show that the combination of the proposed hardware and low-rate algorithm is able to reconstruct the signals by using a low-dynamic range ADC.

    \item To demonstrate an application of the hardware capabilities, we consider sampling and reconstruction of finite-rate-of-innovation (FRI) signals \cite{vetterli, eldar_sos, eldar_2015sampling}. We use a lowpass filter (LPF) prior to the modulo system as a sampling kernel. The filter removes unwanted information in the signal and allows sub-Nyquist sampling. The filtered signal is folded by the designed hardware and then sampled. For estimating the FRI parameters, the samples are first unfolded by using our algorithm presented in \cite{eyar_moduloicassp}, and then the parameters are estimated by using the annihilating filter approach. We show that FRI parameters can be estimated with sub-Nyquist samples by utilizing the fact that our algorithm operates at the lowest possible rate. In particular, we demonstrate that the system functions at five times the rate of innovation, which is significantly lower than the signal's Nyquist rate.

\end{itemize}

The paper is organized as follows. In the next section, we discuss the signal model considered and, the sampling and reconstruction framework in the presence of modulo hardware. In Section III, we present the actual hardware system by explaining its working principle and discussing the components of the system. In Section IV, we show the signal folding and reconstruction abilities of the hardware, and then the conclusion is followed.

\section{Signal Model and System Description}
In this section, we consider modulo sampling and reconstruction of bandlimited signals. We first define the problem and discuss the modulo-sampling framework.

\subsection{Problem Description}
Consider a $\omega_c$-bandlimited signal $y(t)$ such that its Fourier transform $Y(\omega)$ vanishes outside the frequency interval $[-\omega_c, \omega_c]$. The signal can be perfectly reconstructed from its uniform samples measured at the Nyquist rate $\omega_{Nyq} = 2\omega_c$ rad/sec. provided that the dynamic range of the ADC is above the dynamic range of the signal. Specifically, if the dynamic range of the ADC is $[-\lambda, \lambda]$ for some $\lambda >0$ then $|y(t)|\leq \lambda$ for perfect reconstruction. If $|y(t)|>\lambda$ then the signal and its samples will be clipped and perfect reconstruction is not guaranteed at the Nyquist rate. In the later scenario where $|y(t)|>\lambda$, one can either increase the dynamic range of the ADC or use a prepossessing to avoid clipping. We consider the later solution where the modulo operation $\mathcal{M}_{\lambda}(\cdot)$ is applied to the signal $y(t)$ to restrict its dynamic range to $[-\lambda, \lambda]$. The output of the modulo operator in response to input $y(t)$ is given as
\begin{equation}
 y_\lambda(t) =	\mathcal{M}_{\lambda}(y(t)) = (y(t)+\lambda)\,\, \text{mod}\,\, 2\lambda -\lambda.
	\label{eq:mod_opp}
\end{equation}
Then the folded signal $y_\lambda(t)$ is sampled to get discrete measurements $y_\lambda(nT_s)$. Due to modulo folding, $y_\lambda(t)$ is no longer bandlimited and hence Shannon-Nyquist sampling framework can not be applied for reconstruction. To this end, one first applies an unfolding algorithm to recover $y(nT_s)$ from $y_\lambda(nT_s)$. Then $y(t)$ is reconstructed from $y(nT_s)$ by assuming that the sampling is performed above the Nyquist rate. Unfolding algorithms too are functions of the sampling rate and, in practice, the sampling rate should be higher than the Nyquist rate to perfectly recover $y(nT_s)$ from $y_\lambda(nT_s)$.

In short, the modulo-sampling framework consists of an analog prepossessing block that does the folding operation and a digital unfolding algorithm. While one can verify the performance of the algorithms on simulated samples, a natural question is whether they work well with samples measured from a modulo sampler. A few related questions are whether a modulo sampler can be built and applied for any practical applications. What are the practical challenges and how to address them?

Our objective is to demonstrate a hardware prototype of modulo ADC and answer the above questions.
\begin{figure*}
	\centering
	\includegraphics[width=4 in]{Figs/BL_US}
	\caption{A schematic of modulo-sampling and reconstruction of bandlimited signals.}
	\label{fig:bl_framework}
\end{figure*}

\subsection{System Description }
A schematic of modulo sampling and reconstruction framework is shown in Fig.~\ref{fig:bl_framework}. It consists of a modulo-ADC followed by unfolding and reconstruction blocks. The modulo-ADC is comprised of a modulo-folding block followed by a conventional uniform sampler. The folding operator $\mathcal{M}_\lambda(\cdot)$ is realized in the analog domain and should be designed to mimic modulo folding as closely as possible for desired frequencies of operation. Modulo-ADCs are able to sample signals beyond their dynamic range without clipping and hence they are termed high-dynamic range ADCs. Alternatively, an ADC with a  much lower dynamic range can be used to sample signals with larger amplitudes.

The unfolding operation is implemented in the digital domain and it should operate at the lowest possible sampling rate. To this end, we use the $B^2R^2$-algorithm for unfolding which is sampling efficiently compared to other algorithms for bandlimited signals. Low-rate sampling and low-dynamic range requirements significantly reduce the power consumption and cost of the ADC.

The modulo folding block is a key component of the high-dynamic range ADC and we discuss its hardware implementation in the next section.

\begin{figure}
	\centering
	\includegraphics[width= 3 in]{Figs/folding}
	\caption{Folding principle}
	\label{Fig:folding}
\end{figure}
\section{Modulo Hardware Prototype}
In this section, we discuss the prototype of our modulo hardware. The modulo block's working principle and design will be discussed first, followed by its hardware implementation.
\subsection{Working Principle of Modulo Block}
The principle of computing $y_\lambda(t)$ from $y(t)$ is shown by the block diagram in Fig.~\ref{Fig:folding}. The system comprises an adder $S$, a direct-current voltage generator (DC-VG), and two comparators $C_1$ and $C_2$. To understand the working flow, let us first assume that for some time instant $t_1$, we have that $|y(t)|<\lambda$ for all $t<t_1$. Hence $y_\lambda(t) = y(t)$ and $z(t) = 0$ for all $t<t_1$. At $t=t_1$, let $|y(t)|$ crosses $\lambda$. If $y(t_1)>\lambda$, then the comparator $C_1$ triggers a positive value If $y(t_1)<\lambda$, $C_2$ triggers a negative value. The DC-VG is designed such that for each positive input value, it increases its output signal level by $-2\lambda$, whereas, for a negative input value, it decreases its output voltage by $2\lambda$. Hence, in the current example, DC-VG generates signal $z(t) = \text{sgn}(y_\lambda(t_1)) 2\lambda u(t-t_1)$ where $u(t)$ is unit-step function. In this way, by adding or subtracting (using $S$) constant DC signals from $y(t)$ whenever it crosses the dynamic range $[-\lambda, \lambda]$, the amplitude levels of $y_\lambda(t)$ are kept within ADC's dynamic range.

\begin{figure}[!h]
	\centering
	\begin{tabular}{c}
		\subfigure[] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Fig3_2Folding_6Vpp_3Vbias_1KHz_Up_Clr.png}\label{fig:Up_Folding}} \\
		\subfigure[] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Fig3_2Folding_6Vpp_3Vbias_1KHz_Down_Clr.png}\label{fig:Down_Folding}} \\
	\end{tabular}
	\caption{DC-VG based folding operation. (a)-(b) denote the real-time capture of an oscilloscope displaying the input signal (yellow), its folded output (green), the DC-VG signal (blue), and the C1 and C2 comparator (red) respectively.}
	\label{Fig:DC-VG_folding_mechanism}
\end{figure}

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3 in]{Figs/dc_vg}
	\caption{DC-VG}
	\label{Fig:dcvg}
\end{figure}

\begin{figure*}[!t]
	\centering
	\includegraphics[width=0.86\textwidth ]{IEEE_TAES_v1/Figs/UDR_Board_Labeled3.PNG}
	\caption{Modulo hardware board.}
	\label{Fig:hw_board}
\end{figure*}

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3.2 in]{IEEE_TAES_v1/Figs/Fig6_1KHz_10Vpp_4Folding_New_Clr.png}
	\caption{
	Live screenshot of an oscilloscope capturing the 1kHz sinusoid input signal (yellow), its folded output (green), and the DC-VG signal (blue).}
	\label{Fig:Analysis_of_folding_ability}
\end{figure}

\begin{figure}[!h]
	\centering
	\begin{tabular}{c}
		\subfigure[] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Fig7_1Folding_6Vpp_1KHz_New_Clr.png}\label{fig:1k_1}} \\
		\subfigure[] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Fig7_1Folding_6Vpp_10KHz_New_Clr.png}\label{fig:10k_1}} \\
		\subfigure[] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Fig7_1Folding_6Vpp_20KHz_New_Clr.png}\label{fig:20k_1}}
	\end{tabular}
	\caption{Analysis of frequency response of the modulo hardware (a)-(c) denote the real-time capture of an oscilloscope capturing the 1kHz, 10kHz, 20kHz, respectively, the sinusoidal input signal (yellow), its folded output (green), the DC-VG signal (blue).}
	\label{Fig:frequency_response}
\end{figure}

\begin{table}[h!]
		\caption{Up/down counter operation.}
	\centering
	\begin{tabular}{||c c c c c ||}
		\hline
		c & b & a & sgn & Counter values \\ [0.5ex]
		\hline\hline
		0 & 0 & 0 & 0~(1) & 0~(0) \\
		0 & 0 & 1 & 0~(1) & 1~(-1) \\
		0 & 1 & 0 & 0~(1) & 2~(-2) \\
		0 & 1 & 1 & 0~(1) & 3~(-3) \\
		1 & 0 & 0 & 0~(1) & 4~(-4) \\
		1 & 0 & 1 & 0~(1) & 5~(-5)\\
		1 & 1 & 0 & 0~(1) & 6~(-6)\\
		1 & 1 & 1 & 0~(1) & 7~(-7)\\
		\hline
	\end{tabular}
	\label{table:counter}
\end{table}

While the parts such as comparators $C_1$, $C_2$, and adder $S$ can be realized by using off-the-shelf components, DC-VG is a more involved system and required careful design. A detailed architecture of DC-VG is shown in Fig.~\ref{Fig:dcvg}. It consists of an up/down counter, a digital-to-analog converter (DAC), a multiplexer (MUX), and a multiplier $M$.  The function of the counter, along with the DAC, is to produce a piece-wise constant DC voltage whenever a trigger is present at its input. By employing the MUX and multiplier $M$, the voltage values are configured to be multiples of $2\lambda$.
To explain the working principle, we will first discuss the function of the counter, followed by the other components.

In this particular system, we use a three-bit synchronous up/down counter. The bits from lower significant bit to higher significant bit are denoted as a, b, and c, respectively. The counter has an additional sign bit shown as sgn. With these bits, the counter can count from -7 to 7. For each positive input trigger, the output counts up, and for each negative input trigger, it counts down. In Table~\ref{table:counter}, we list the values of bits and the counter (denoted as counter values). The three bits (a,b, and c) of the counter are used as input to the DAC which converts the bits to an analog DC voltage. Let the resolution or step size of the DAC is $\alpha$ then the output of DAC is $\alpha$ times the counter-value. To be more specific, consider the scenario where the output of the counter and DAC are zero. DAC's output then increases (decreases) by $\alpha$ in response to a positive (negative) trigger. DAC's output signal, $s(t),$ is a piecewise constant signal whose values are multiples of $\alpha$. For folding to function, however, the voltage change must be in multiples of $2\lambda$. Further, we employ a MUX whose output is $2\lambda$ or $-2\lambda$ depending on whether its input (sign bit) is 1 or 0. Then, $z(t)$ is generated by multiplying the output of DAC by the output of MUX.

Fig. \ref{fig:Up_Folding} (Fig. \ref{fig:Down_Folding}) demonstrates the DC-VG based folding operation time sequence beginning with the C1 (C2) comparator trigger operation, in red, followed by $z(t)$, in blue, which results in a 2$\lambda$ increase (decrease) of $y_\lambda(t)$, in green, and keeping it within the $\pm\lambda$ ADC range.

Next, we discuss the hardware board that realizes the folding operation discussed in this section.

\begin{table}[h!]
\centering
\caption{List of Hardware Components}
\label{table:hardware_components}
\begin{tabular}{||c c c||}
 \hline
 Component & Model Number & Make \\
 && \\ \hline
 Comparator & LM339 & Texas Instruments \\
 && \\
 UP/DOWN Counter & TEENSY4.1 & PJRC \\
 && \\
 DAC 3bits & LT1364 & Analog Devices \\
 && \\
 Analog MUX & ADG1608 & Analog Devices \\
 && \\
 Analog Multiplier & AD835 & Analog Devices \\
 && \\
 Adder & LT1364 & Analog Devices \\
  && \\ [1ex]
\hline
\end{tabular}
\end{table}
\subsection{Modulo Hardware Board}
Our modulo hardware board is presented in Fig.~\ref{Fig:hw_board}, along with the roles of the major building components. Table~\ref{table:hardware_components} contains a detailed listing of the hardware's components. The board is designed for $\lambda\leq1.25$ volts or less. The board can accommodate an input signal with a dynamic range between $[-8\lambda, 8\lambda]$, which means that an ADC equipped with our modulo hardware can sample signals four times bigger than its dynamic range without saturation and clipping.

We demonstrate the working of the modulo hardware by considering a sinusoidal signal $y(t) = A\, \sin(2\pi f_0 t)$ where $A$ is amplitude and $f_0$ is the frequency (in Hz). In this experiment, we set $\lambda = 1.25$ and $-4\lambda <A <+4\lambda$. With this setting, we expect the signal to fold 4 times in a half sinusoidal cycle. Fig.~\ref{Fig:Analysis_of_folding_ability} depicts a screenshot of an oscilloscope capturing input $y(t)$ (in yellow) and its folded output $y_\lambda(t)$ (in green) in addition to the DC-VG output signal $z(t)$ (in blue), for $f_0 = 1$kHz. We observed that the signals are folded back to lie within the dynamic range of the ADC as expected without clipping. Next, we discuss the frequency response of the modulo ADC. As in any analog system, the response of the modulo folder too depends on the frequency or bandwidth of the input signal. Beyond a particular frequency, the folding may not be accurate as demonstrated in Fig.~\ref{Fig:frequency_response}. We observed that for signals of 1kHz and 10kHz the hardware is able to fold the signal accurately. However, for $f_0 = 20$kHz, folding instants are not symmetric for positive and negative folds. In one of our future works, we are planning to design hardware that overcomes this limitation by using faster hardware logical components to implement the folding counter instead of using the current up/down counter. The current implementation demonstrates a proof of concept of implementing the modulo concept in the analog domain in a near real-life environment and paves the way for high-frequency applications which support high dynamic range operation.

In the next section, we discuss a couple of inaccuracies of the modulo hardware and our proposed solutions to overcome those.

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3.2 in]{Figs/mod_td}
	\caption{Effect of time delay of the feedback loop on the modulo operation.}
	\label{Fig:mod_td}
\end{figure}

\subsection{Artifacts During Folding}
Errors or other artifacts that arise during folding operations in hardware could be due to various reasons. One of the major issues that arise in a modulo ADC is the time delay in the feedback loop (See Fig.~\ref{Fig:folding}). To elaborate, consider a scenario where $y(t)<\lambda$ for $t<t_1$ and it crosses $\lambda$ at time $t_1$ as discussed earlier. To fold the output voltage to the dynamic range of the ADC, $z(t) = 2\lambda u(t-t_1)$ needs to be subtracted from $y(t)$. However, there is a finite delay between the trigger time $t_1$ to generating $z(t)$. If the time delay is $T_d$, then $z(t) = 2\lambda u(t-t_1-T_d)$ is subtracted, which causes distortion. To illustrate this effect, in Fig.~\ref{Fig:mod_td}, we considered a sinusoidal signal (in blue) and its folded versions with and without delay. We observe that in the absence of any time delay ($T_d=0$) the signal folds perfectly (shown in red) to stay within the dynamic range. However, for a non-zero value of $T_d$, foldings do not take place at the folding instants, and the output of the modulo operator (shown in black) still remains outside the dynamic range $[-\lambda, \lambda]$, which results in a clipped modulo operator output. However, the proposed hardware solution addresses this issue and avoids the undesired clipping as shown in Figs.~\ref{Fig:Analysis_of_folding_ability} and \ref{Fig:frequency_response}.

Our solution uses the fact that with a finite time delay, the amount of overshoot of a smooth signal can be bounded. To elaborate, let us assume that the signal that undergoes modulo operation is Lipschitz continuous. Specifically, a signal $y(t)$ is Lipschitz continuous if there exists a positive real number $\mathrm{L}_y$ such that for any $T>0$ we have
\begin{align}
    |y(t) -y(t+T)|\leq \mathrm{L}_y\, T.
    \label{eq:lipschitz}
\end{align}
With the Lipschitz smoothness condition, we note that the amplitude of $y(t)$ can not change more than $\mathrm{L}_y\, T_d$ between any folding instant and time of its effect to take place. Hence, if we choose dynamic range of the ADC to be $[-(\lambda+\Delta \lambda), (\lambda+\Delta \lambda)]$ where $\Delta \lambda = \mathrm{L}_y\, T_d$ then the signal will not clip. We show this extended dynamic region in the illustrative example in Fig.~\ref{Fig:mod_td}. Alternatively, instead of increasing ADC's dynamic range, one can keep it to be $[-\lambda, \lambda]$ and reduce the threshold values for comparators. In this case, $C_1$ will trigger when the input crosses $\lambda-\Delta \lambda$ and $C_2$ will trigger when the input goes beyond $-\lambda+\Delta \lambda$. In this way, the time delay issue is addressed by the modulo circuit without altering ADC's dynamic range.

In order to apply the solution, the signal must be Lipschitz continuous. In our design, the modulo operation input signal is always a lowpass or bandlimited signal satisfying the Lipschitz smoothness condition \cite{bl_bound}. For a bandlimited signal $y(t)$ its Lipschitz constant $\mathrm{L}_y$ is directly proportional to its bandwidth $\omega_c$ which is the same as the cutoff frequency of the LPF.
Hence, for a given value $\Delta \lambda$ and $T_d$ (both depend on the modulo circuit), $\mathrm{L}_y = \Delta \lambda/T_d$ is fixed and this restricts the maximum frequency of the input signal that can be faithfully folded. In the current design, we choose to implement the counter management using a TEENSY microcontroller, resulting in a $1 \mu$s time delay. This enables the hardware to accommodate a wide range of frequencies without requiring any modifications to the hardware components.

Another issue one can observe after DC-VG switching is that the voltage at the output of DC-VG either overshoots or undershoots (refer to Fig.~\ref{Fig:Analysis_of_folding_ability}) before the oscillations settle down to the expected value. This issue may be resolved by using a faster adder $S$ whose response time should be at least a magnitude higher than the sample rate. In one of our future works, we are planning to design hardware that overcomes this limitation.

\section{Results}
In this section, we demonstrate the modulo hardware described in the previous section's signal reconstruction capability.
In the hardware settings consider here, the samples are contaminated by the measurement noise. In addition, quantization plays a role when a finite-resolution quantizer is used after the sampler. We model all these noises and inaccuracies as additive noise at the output of the sampler. Specifically, the noisy measurements are given as
 \begin{align}
            \tilde{y}_{\lambda}(n T_s) = {y}_{\lambda}(n T_s) + v(n T_s),
        \label{eq: noisy_samples}
        \end{align}
where $v(n T_s)$ is the noise term. Both unfolding and parameter estimation algorithms should be robust to different noise models. The robustness of parameter estimation methods in the presence of noise is well studied (See \cite{mulleti_kernal, stoica, eldar_sos}). In \cite{eyar_moduloicassp}, we presented comparisons of unfolding algorithms for bandlimited signals. We showed that our beyond-bandwidth residual recovery ($B^2R^2$) approach results in a lower error during unfolding compared to the \emph{higher-order differences} (HOD) approach \cite{unlimited_sampling17, uls_tsp} and \emph{Chebyshev polynomial filter}-based (CPF) method \cite{uls_romonov}. Importantly, for a given sampling rate, $\lambda$, and signal-to-noise ratio (SNR), the $B^2R^2$ method results in the lowest error for both bounded and unbounded noise models.

Before presenting hardware results, we compare the performances of the $B^2R^2$ method with HOD and CPF approaches for quantization noise and unbounded noise. We would like to point out that quantization noise was not considered in \cite{eyar_moduloicassp}. Although, the algorithms were compared for unbounded noise the simulation settings were different than those in our hardware. Hence, for a better understanding, we compared our algorithm for unbounded noise and quantization  noise with the current hardware settings. In the next section, we present these simulation results and then present hardware results.

\begin{figure}[!t]
	\centering
	\includegraphics[width= 2.5 in]{IEEE_TAES_v1/Figs/quantization.png}
	\caption{Comparison of HOD, CPF, and $B^2R^2$ algorithms after the quantization process in terms of MSE when recovering a bandlimited signal from modulo samples with $\lambda = 1.25$ and OF = 3,6. For a given number of bits, $B^2R^2$ has the lowest MSE.}
	\label{Fig:quantization}
\end{figure}

\begin{figure}[!t]
	\centering
	\includegraphics[width= 2.5 in]{IEEE_TAES_v1/Figs/Gaussian.png}
	\caption{Comparison of HOD, CPF and $B^2R^2$ algorithms (with unbounded noise) in terms of MSE when recovering a bandlimited signal from modulo samples with  $\lambda$ = 1.25 and OF = 3,6. For a given SNR and OF, $B^2R^2$ has the lowest MSE.}
	\label{Fig:unbounded}
\end{figure}
\subsection{Simulated Results}
In this section, we compare our $B^2R^2$ algorithm with the \emph{higher-order differences} (HOD) approach \cite{unlimited_sampling17, uls_tsp} and \emph{Chebyshev polynomial filter}-based (CPF) method \cite{uls_romonov}. We consider the noise measurements as in \eqref{eq: noisy_samples} for simulation data. In the simulations, $\lambda$ is set to be $1.25$ as in the hardware. We normalize the bandlimited signals to have a maximum amplitude of $10$. The SNR is calculated as $\text{SNR} = 20 \log\left(\frac{||y_{\lambda}(n T_s)||}{||v(n T_s)||}\right)$. The reconstruction accuracy of different methods is compared in terms of the normalized mean-squared error (MSE) as $ \frac{\sum |y(nT_s) - \hat{y}(n Ts)|^2}{\sum |y(nT_s)|^2}$, where $\hat{y}(n T_s)$ estimate of $y(n T_s)$. For different noise settings and over-sampling factors (OFs), we considered 100 independent noise realizations and calculated the average MSE for them. We first consider quantization noise and then present results for unbounded noise.

\begin{figure}[!t]
    \centering
    \includegraphics[width=0.3\textwidth]{IEEE_TAES_v1/Figs/Signal Generator.png}
    \caption{Bandlimited signal generator.}
    \label{fig:UDRSignalGen}
\end{figure}

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3.2 in]{IEEE_TAES_v1/Figs/Up_2mS_Clr.png}
	\caption{Bandlimited folded signal.}
	\label{Fig:Bandlimited_folded_signal}
\end{figure}

 First, we consider a uniform quantizer after the sampling. The unfolding algorithms are applied on the quantized samples. The MSE in the estimation of bandlimited signals for a different number of bits and OFs is shown in Fig. ~\ref{Fig:quantization}. We observe that for a given $\text{OF}$, $B^2R^2$ algorithm results in the lowest MSE for less than 5 bits. For more than 5 bits all the algorithms, except HOD with OF = 3, perform equally well. The results show that low-resolution quantizers can be used with the $B^2R^2$ algorithm for unrolling which saves both power and memory requirements.

Next, for unbounded noise, we assume that the noise measurements $v(nT_s)$ are independent and identically distributed Gaussian random variables with zero mean. The variance is set to achieve the desired SNR. We compare the methods for different values of SNR and OFs with $\lambda = 1.25$. Fig.~\ref{Fig:unbounded} shows the MSE of the different algorithms for OF $= 3$ and $6$. We note that our algorithm results in the lowest error for a given OF and SNR.

Given the advantages of the $B^2R^2$ algorithm over the other approaches, we present the hardware results in the next section by using this method.

\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/BL1_scope_11_Clr.png}\label{fig:BL1_scope}} \\
		\subfigure[]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/BL2_scope_13_Clr.png}\label{fig:BL2_scope}}
	\end{tabular}
	\caption{Live screen shot of an oscilloscope capturing the input bandlimited signals (yellow) and its folded output signals (green).}
	\label{fig:BL_scopeex1}
\end{figure}
\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/BL1_rec.png}\label{fig:BL1}} \\
		\subfigure[]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/BL2_rec.png}\label{fig:BL2}}
	\end{tabular}
	\caption{Hardware results for bandlimited signals. The $B^2R^2$ algorithm is used to unfold $y_\lambda(t)$ (measured at the output of hardware), and the unfolded signal $\hat{y}(t)$ is plotted with bandlimited signal $y(t)$.}
	\label{fig:BL_ex1}
\end{figure}

\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[Screen shot of the oscilloscope capturing filtered FRI signal (yellow), its folded output (green), and the DC-VG signal (blue).] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/FRI1_1_Clr.png}\label{fig:FRI1_1k}} \\
		\subfigure[Filtered FRI signal with its folded and unfolded versions.]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Ex1_lpf.pdf}\label{fig:FRI_LPF1}}\\
		\subfigure[FRI signal reconstruction.] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Ex1_fri.pdf}\label{fig:FRI1_REC}} \\

	\end{tabular}
	\caption{Reconstruction of FRI signal ($L=2$) via the modulo hardware .}
	\label{Fig:FRI1}
\end{figure}

\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[Screen shot of the oscilloscope capturing filtered FRI signal (yellow), its folded output (green), and the DC-VG signal (blue).] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/FRI2_1_Clr.png}\label{fig:FRI2_1k}} \\
		\subfigure[Filtered FRI signal with its folded and unfolded versions.]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Ex2_lpf.pdf}\label{fig:FRI_LPF2}}\\
		\subfigure[FRI signal reconstruction.] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Ex2_fri.pdf}\label{fig:FRI2_REC}} \\
	\end{tabular}
	\caption{Reconstruction of FRI signal ($L=3$) via the modulo hardware .}
	\label{Fig:FRI2}
\end{figure}

\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[Screen shot of the oscilloscope capturing filtered FRI signal (yellow), its folded output (green), and the DC-VG signal (blue).] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/FRI3_1_Clr.png}\label{fig:FRI3_1k}} \\
		\subfigure[Filtered FRI signal with its folded and unfolded versions.]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Ex3_lpf.pdf}\label{fig:FRI_LPF3}}\\
		\subfigure[FRI signal reconstruction.] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Ex3_fri.pdf}\label{fig:FRI3_REC}} \\

	\end{tabular}
	\caption{Reconstruction of FRI signal ($L=5$) via the modulo hardware.}
	\label{Fig:FRI3}
\end{figure}

\subsection{Hardware Results}
In this section, we present results from the hardware.
Since bandlimited signals are input to the hardware, we first present results for them and then show results for FRI signals. If the hardware and unfolding algorithm are able to recover the bandlimited signals with high accuracy then it will lead to a better reconstruction of the FRI signals. In all these experiments we set $\lambda = 1.25$ V and the cutoff frequency of the lowpass filter is 1kHz. We observe that for frequencies less than or equal to 10kHz, our hardware is able to reliably fold the signal. The Nyquist rate of the signal is 2kHz. But for unfolding, we need to oversample the signal. In all these experiments, we used the $B^2R^2$ algorithm with OF = 5 which results in a sampling rate of 10kHz. Further, $y(t)$ (yellow) and $y_\lambda(t)$ (green) are measured from the hardware through an oscilloscope for processing by the algorithms as described in Fig. \ref{Fig:Bandlimited_folded_signal}.

We first consider the bandlimited signals. For generating bandlimited or lowpass signals we used an Arduino microcontroller (See Fig.~\ref{fig:UDRSignalGen}) which converts the digital signal to an analog signal via a DAC. The digital signals were generated using MATLAB software. Two examples of 1khz bandlimited signal are presented in Fig. \ref{fig:BL1_scope} and Fig. \ref{fig:BL2_scope}. In Fig.~\ref{fig:BL_ex1}, we show folding and reconstruction, using the $B^2R^2$ algorithm, of the two bandlimited signals that are displayed in Fig. \ref{fig:BL_scopeex1}. These signals have a maximum amplitude of 5V. We observe the signals are restricted to $[-\lambda, \lambda]$ by the modulo hardware, and the algorithm was able to recover the true signal from the folded samples. The reconstructed signal has a slightly larger amplitude compared to the true signal which is the result of scaling within the hardware.

\subsection{Application to FRI Signals}
Consider an FRI signal consisting of a stream of $L$ pulses:
\begin{align}
	f(t) = \sum_{\ell=1}^L a_\ell h(t-t_\ell),
	\label{eq:fri1}
\end{align}
where the pulse $h(t)$ a real-valued known pulse. We assume that $\{a_\ell\}_{\ell = 1}^L$ are real-valued and $\{t_\ell\}_{\ell = 1}^L \subset (0, T_0] \subset \mathbb{R}$ for a known $T_0$.

The FRI signal model in \eqref{eq:fri1} is encountered in several scientific applications such as radar imaging \cite{bar_radar, bajwa_radar, sunil}, ultrasound imaging \cite{eldar_sos,eldar_beamforming,mulleti_icip}, light detection and ranging (LIDAR) \cite{castorena_lidar}, time-domain optical coherence tomography (TDOCT) \cite{blu_oct}, and other time-of-flight imaging systems. In these applications,  $h(t)$ is the transmitted pulse and $\{a_\ell \,h(t-t_\ell)\}_{\ell=1}^{L}$ constitute the reflections from $L$ point targets. The amplitudes $\{a_\ell\}_{\ell = 1}^L$ depend on the sizes of the targets and the delays $\{t_\ell\}_{\ell = 1}^L$ are proportional to the distances of the targets from the transmitter. Here $T_0$ denotes the maximum time delay of the targets. The signal $f(t)$ is specified by $\{a_\ell, t_\ell\}_{\ell=1}^L$ and can be reconstructed from its sub-Nyquist measurements acquired using an appropriate sampling kernel \cite{vetterli,eldar_sos,fri_strang, mulleti_kernal}. Given their widespread application, here we consider sampling and reconstruction of FRI signals by using our hardware prototype.

FRI signals can be perfectly reconstructed by applying high-resolution spectral estimation methods, such as the annihilating filter (AF) or Prony's method and its variants
\cite{prony, plonka, schmidt_music, barabell_rmusic, bdrao_rmusic,sarkar_mp,paulraj_esprit} to the Fourier measurements
\begin{align}
	S(k\omega_0) = \frac{F(k\omega_0)}{H(k\omega_0)} =  \sum_{\ell = 1}^L a_\ell \, e^{-\mathrm{j}k\omega_0 t_\ell}, \, k \in \{-K, \cdots, K\},
	\label{eq:Skomega}
\end{align}
where we assume that $H(k \omega_0) \neq 0$. Here $K \geq L$ and $\omega_0 = \frac{2\pi}{T_0}$ \cite{eldar_2015sampling}. The Fourier measurements $\{S(k\omega_0)\}_{k =-K}^K$ can be determined from the samples $(f*g)(nT_s)$ where $g(t)$ is an ideal lowpass filter with bandwidth $[-K\omega_0, K \omega_0]$ and $T_s = \frac{2\pi}{(2K+1)\omega_0}$. In practice, the duration of the pulse $h(t)$ is very short, and hence $f(t)$ has a wide bandwidth. This results in a large sampling rate (or Nyquist rate) if $f(t)$ is sampled directly. However, the filtered signal $y(t) = (f*g)(t)$ is bandlimited to $[-K\omega_0, K \omega_0]$ which is much smaller than that of $h(t)$ and the sampling rate is much lower than the Nyquist rate.

As in the bandlimited signal model, a modulo operation can be applied to the filtered signal $y(t)$ to avoid clipping. Then $y_\lambda(t)$ is sampled. Then to determine the Fourier samples $\{S(k\omega_0)\}_{k =-K}^K$, unfolding is first applied. Since the filtered signal is bandlimited, we use the proposed hardware for modulo folding and can apply the $B^2R^2$ algorithm from unfolding.

In our setup, to generate the FRI signals, we consider $h(t)$ to be a short pulse of bandwidth 30kHz (Nyquist rate = 60kHz). We consider three examples with $L=2, 3,$ and 5. The amplitudes and time delays are generated randomly. The maximum time delay is $T_0 = 0.1$ sec. Once generated, the FRI signal is lowpass filtered with a cutoff frequency of 1kHz. Up to the filtering operation, MATLAB is used and then an Arduino micro-controller is used to generate the analog version of the filtered FRI signals. The signal is then folded using the hardware and the folded signals are sampled. The sampling rate is 10kHz which is five times higher than the sampling rate of the lowpass signal. Still, the rate is six times lower than the Nyquist rate and hence the system operates at a sub-Nyquist rate.

We first apply the $B^2R^2$ algorithm to unfold the signal and then used ESPRIT \cite{paulraj_esprit} to estimate the time delays and amplitudes of the FRI signals.
In Fig.~\ref{Fig:FRI1}, Fig.~\ref{Fig:FRI2} and  Fig.~\ref{Fig:FRI3} we show sampling and reconstruction of FRI signals with $L=2,3,5$ respectively.
The FRI signals followed by a lowpass filter are presented in Fig.~\ref{fig:FRI1_1k}, Fig.~\ref{fig:FRI2_1k}, and  Fig.~\ref{fig:FRI3_1k}.
The reconstruction of the lowpass signals displayed in Fig.~\ref{fig:FRI_LPF1}, Fig.~\ref{fig:FRI_LPF2} and  Fig.~\ref{fig:FRI_LPF3}, where $y(t)$ described the LPF output, $y_\lambda(t)$ is the folded signal (output of the modulo hardware), and the unfolded signals are given by $\hat{y}(t)$. Fig.~\ref{fig:FRI1_REC}, Fig.~\ref{fig:FRI2_REC} and Fig.~\ref{fig:FRI3_REC} show location and amplitude of the true signal $f(t)$ and estimated FRI signal $\hat{f}(t)$.
The maximum error in the estimation of time delay is $-15$ dB which shows that the system can be used in applications like radar and ultrasound imaging.

\section{Conclusions}
 We presented a hardware prototype for the modulo folding system and show that for different bandlimited and FRI signals, the hardware is able to faithfully fold the signal. We also  address the time delay issue of the modulo system and presented a hardware solution for the same. The overall system operates at five times below the Nyquist rate which enables one to use low-rate, low-dynamic range, power-efficient ADCs.

\bibliographystyle{IEEEtaes}

\section{INTRODUCTION}
Analog-to-digital converters (ADCs) act as a bridge between real-world analog signals and digital processors on which signals can be processed efficiently. Typically, ADCs measure instantaneous uniform samples of analog signals to represent them digitally. A key parameter in such conversion is the sampling rate. Power consumption and cost of an ADC increase with the increase in the sampling rate. Hence, keeping the sampling rate as low as possible is desirable. Theoretically, the sampling rate has to be greater than the Nyquist rate for perfect reconstruction of bandlimited signals. Apart from the sampling rate, there are several other aspects of an ADC which play a key role in faithful sampling and reconstruction, especially when the sampling frameworks are implemented in hardware.

The dynamic range of an ADC plays a crucial role in sampling an analog signal. Generally, ADC's dynamic range should be larger than the signal's; otherwise, the signal gets clipped. A few approaches exist to recover the true samples from clipped ones for bandlimited signals \cite{marks_clipping2, marks_clipping1}. These approaches rely on the correlation among the samples when they are measured at a very high rate compared to the Nyquist rate. The requirement of a high sampling rate is a drawback of these approaches.

Several preprocessing approaches to avoid clipping exist, such as automatic gain control (AGC) \cite{perez2011automatic,mercy1981review}, companding \cite{landau_compander,landau_distorted_bl}, and modulo folding \cite{uls_tsp,uls_romonov,uls_sparse,bhandari2021unlimited,eyar_moduloicassp}. Among these, modulo folding is the most recent approach that need not be differentiable like companding and does not suffer from stability issues of the feedback amplifiers used in AGCs. In the modulo framework, the signal is folded to lie within the ADC's dynamic range, and then the folded signal is sampled using a conventional ADC. Theoretical guarantees for recovering bandlimited signals from folded samples are presented in \cite{uls_tsp,uls_identifiability}. The results state that a bandlimited signal can be uniquely recovered from its folded samples provided that they are sampled above the Nyquist rate \cite{uls_tsp,uls_identifiability}.

Several algorithms for \emph{unfolding} or recovering the true samples of a bandlimited signal from a modulo or folded samples are presented in \cite{uls_tsp,uls_romonov, eyar_moduloicassp}. These unfolding algorithms can be compared in terms of sampling rate, amount of unfolding they can handle, and noise robustness. The algorithm proposed in \cite{uls_tsp} requires almost 17 times higher sampling rate than the Nyquist rate. The approaches in \cite{uls_romonov} and \cite{eyar_moduloicassp} operate at relatively lower sampling rates but require the knowledge of ADC's dynamic range where the method proposed in \cite{eyar_moduloicassp} requira a lower sampling rate, even in the presence of noise, compared to the algorithms presented in \cite{uls_tsp,uls_romonov}. Modulo sampling is also extended to different problems and signal models such as periodic bandlimited signals \cite{bhandari2021unlimited}, wavelets \cite{uls_wavelet}, a mixture of sinusoids \cite{uls_sinmix}, finite-rate-of-innovation (FRI) signals \cite{uls_fri}, multi-dimensional signals \cite{uls_md}, sparse vector recovery \cite{uls_gamp, uls_sparsevec}, direction of arrival estimation \cite{uls_doa}, computed tomography \cite{uls_radon}, and graph signals \cite{uls_graph}.

Beyond theoretical works, there also exist a few related hardware prototypes. High-dynamic-range ADCs, also known as \emph{self-reset} ADCs, are discussed in the context of imaging \cite{sradc_park, sradc_sasagwa, sradc_yuan, krishna2019unlimited}. These hardware architectures measure additional information, such as the amount of folding for each sample or the sign of the folding together with the folded samples. The additional information might enable simpler recovery at the expense of complex circuitry. Importantly, additional bits are required during the quantization process to store or transmit the side information.

Krishna et al. presented a hardware prototype that encodes the side information by using two bits \cite{krishna2019unlimited}. The architecture is designed to record the sign of the slope of the signal at each sample that lies outside the ADC's dynamic range. In a conventional ADC, a sample and hold (S/H) circuit is used to hold the sampled value for a prescribed period of time, during which quantization is performed on the sample. A folding circuit is used after S/H  to realize the modulo sampling \cite{krishna2019unlimited}. In this architecture, the S/H circuit has to hold the sampled value for folding and quantization, resulting in a larger holding time than a conventional ADC. A large holding time results in slower ADCs, which may not be helpful in wideband applications. {\color{red} Write bandwidth of the hardware prototypes. And say that they are not useful for applications such as where bandwidth is large. Ultrasound example?}

Modulo hardware prototypes where the modulo part is implemented prior to the sampler are presented in \cite{bhandari2021unlimited,Bhandari:2022:J,mod_hyst}. Since the modulo circuit is not a part of the hold time, the ADC could be faster than the hardware realization in \cite{krishna2019unlimited}.  In \cite{mod_hyst}, the authors discussed a few implementation issues of modulo hardware such as hysteresis and folding transients. Further, they proposed algorithmic solutions to mitigate them. Both these issues can also be addressed by careful calibration and by using high-precision components \cite{mod_hyst}. In all these works \cite{bhandari2021unlimited,Bhandari:2022:J,mod_hyst}, the authors are focused on different signal models, hardware limitations, and algorithms rather than providing details of the hardware circuitry. It was shown that the modulo hardware is able to fold low-frequency signals that are 10-12 times larger than the ADC's dynamic range.

In this paper, we present a modulo hardware prototype that can be used in low-power time-of-flight applications and show that by using our algorithm \cite{eyar_moduloicassp}, it is able to reconstruct FRI signals faithfully.
In the following, we present the contributions and the features of the proposed hardware system.
\begin{itemize}
    \item We design our hardware components to be able to fold signals up to 10kHz. Note that no existing hardware is capable of handling such high-frequency signals.

    \item The hardware prototype is designed to perform folding operation prior to the sampler, unlike the hardware in \cite{krishna2019unlimited}, which operates in the hold part of the sampler.  Thus, the suggested system can utilize faster ADCs with shorter hold times.
    \item In the proposed hardware prototype, modulo folding is realized through a feedback mechanism. At the time instants when the input signal goes beyond the ADC's dynamic range, a trigger signal is generated by using comparators. The trigger then activates a direct-current (DC) generator that adds to the input signal to bring it within the dynamic range. This mechanism imposes a delay between the instance delay (when the signal amplitude exceeds the dynamic range) and the folding instance.
    We address this key issue of the hardware which is not considered in previous works.
    By using the signal's smoothness and the feedback loop's time delay,
    we propose a hardware solution to avoid clipping that occurred due to the delay issue. Specifically, we demonstrate that tunable threshold voltages at the comparators can resolve the time delay issues for signals with different bandwidths.

    \item To demonstrate the performance of the hardware, we consider sampling and reconstruction of bandlimited and FRI signals. For FRI signals, we use a lowpass sampling kernel prior to modulo folding. The filter removes unwanted information in the signal and allows sub-Nyquist sampling. Hence, inputs to modulo sampling are always bandlimited signals, even for FRI signal sampling. Using our algorithm presented in \cite{eyar_moduloicassp}, we show the reconstruction of bandlimited signals from their folded samples measured through the hardware. We show that the combination of the proposed hardware and low-rate algorithm is able to reconstruct the signals by using a low-dynamic range ADC. In particular, for FRI signals, we show that the FRI parameters can be estimated with sub-Nyquist samples by utilizing the fact that our algorithm operates at the lowest possible rate. Specifically, we demonstrate that the system functions at five times the rate of innovation, which is significantly lower than the signal's Nyquist rate.

\end{itemize}

The paper is organized as follows. In the next section, we discuss the signal model considered and the sampling and reconstruction framework in the presence of modulo hardware. In Section III, we present the actual hardware system by explaining its working principle and discussing the components of the system. In Section IV, we show the hardware's signal folding and reconstruction abilities.

\section{Signal Model and System Description}
In this section, we consider modulo sampling for signals that lie beyond the bandwidth of ADC's dynamic range. This paper considers only bandlimited signals as input to the modulo hardware and corresponding unfolding algorithms. Though, one can use other classes of signals as input to the proposed hardware, such as signals in shift-invariant spaces, and then use a corresponding unfolding algorithm.

Consider a $\omega_c$-bandlimited signal $y(t)$ such that its Fourier transform $Y(\omega)$ vanishes outside the frequency interval $[-\omega_c, \omega_c]$. The signal can be perfectly reconstructed from its uniform samples measured at the Nyquist rate $\omega_{Nyq} = 2\omega_c$ rad/sec. provided that the dynamic range of the ADC is above the dynamic range of the signal. Specifically, if the dynamic range of the ADC is $[-\lambda, \lambda]$ for some $\lambda >0$ then it is assumed that $|y(t)|\leq \lambda$ for perfect reconstruction. If $|y(t)|>\lambda$, then the signal and its samples will be clipped, and perfect reconstruction is not guaranteed at the Nyquist rate. In the latter scenario where $|y(t)|>\lambda$, one can either increase the dynamic range of the ADC or use a prepossessing to avoid clipping. We consider the later solution where the modulo operation $\mathcal{M}_{\lambda}(\cdot)$ is applied to the signal $y(t)$ to restrict its dynamic range to $[-\lambda, \lambda]$. The output of the modulo operator in response to input $y(t)$ is given as
\begin{equation}
 y_\lambda(t) =	\mathcal{M}_{\lambda}(y(t)) = (y(t)+\lambda)\,\, \text{mod}\,\, 2\lambda -\lambda.
	\label{eq:mod_opp}
\end{equation}
The folded signal $y_\lambda(t)$ is then sampled to get discrete measurements $y_\lambda(nT_s)$. Due to modulo folding, $y_\lambda(t)$ is no longer bandlimited. To recover $y(t)$ while sampling slightly above the Nyquist rate of the input, one first applies an unfolding algorithm to recover $y(nT_s)$ from $y_\lambda(nT_s)$ \cite{eyar_moduloicassp,azar2022robust,mulleti2022modulo}. Then $y(t)$ is reconstructed from $y(nT_s)$ by assuming that the sampling is performed above the Nyquist rate. Unfolding algorithms are functions of the sampling rate, and, in practice, the sampling rate should be higher than the Nyquist rate to perfectly recover $y(nT_s)$ from $y_\lambda(nT_s)$.

In short, the modulo-sampling framework consists of an analog-prepossessing block that performs the folding operation and a digital unfolding algorithm. While one can verify the performance of the algorithms on simulated samples, a natural question is whether they work well with samples measured from a modulo sampler. A few related questions are whether a modulo sampler can be built and applied for any practical applications. What are the practical challenges and how to address them?

Our objective is to demonstrate a hardware prototype of modulo ADC and answer the above questions.
\begin{figure*}
	\centering
	\includegraphics[width=4 in]{Figs/BL_US}
	\caption{A schematic of modulo-sampling and reconstruction of bandlimited signals.}
	\label{fig:bl_framework}
\end{figure*}

\subsection{System Description }
A schematic of modulo sampling and reconstruction framework is shown in Fig.~\ref{fig:bl_framework}. It consists of a modulo-ADC followed by unfolding and reconstruction blocks. The modulo-ADC is comprised of a modulo-folding block followed by a conventional uniform sampler. The folding operator $\mathcal{M}_\lambda(\cdot)$ is realized in the analog domain and should be designed to mimic modulo folding as closely as possible for desired frequencies of operation. Modulo-ADCs are able to sample signals beyond their dynamic range without clipping and hence they are termed high-dynamic range ADCs. Alternatively, an ADC with a  much lower dynamic range can be used to sample signals with larger amplitudes.

The unfolding operation is implemented in the digital domain and it should operate at the lowest possible sampling rate. To this end, we use the $B^2R^2$-algorithm for unfolding which is sampling efficiently compared to other algorithms for bandlimited signals. Low-rate sampling and low-dynamic range requirements significantly reduce the power consumption and cost of the ADC.

The modulo folding block is a key component of the high-dynamic range ADC and we discuss its hardware implementation in the next section.

\begin{figure}
	\centering
	\includegraphics[width= 3 in]{Figs/folding}
	\caption{Folding principle}
	\label{Fig:folding}
\end{figure}
\section{Modulo Hardware Prototype}
In this section, we discuss the prototype of our modulo hardware. The modulo block's working principle and design will be discussed first, followed by its hardware implementation.
\subsection{Working Principle of Modulo Block}
The principle of computing $y_\lambda(t)$ from $y(t)$ is shown by the block diagram in Fig.~\ref{Fig:folding}. The system comprises an adder $S$, a direct-current voltage generator (DC-VG), and two comparators $C_1$ and $C_2$. To understand the working flow, let us first assume that for some time instant $t_1$, we have that $|y(t)|<\lambda$ for all $t<t_1$. Hence $y_\lambda(t) = y(t)$ and $z(t) = 0$ for all $t<t_1$. At $t=t_1$, let $|y(t)|$ crosses $\lambda$. If $y(t_1)>\lambda$, then the comparator $C_1$ triggers a positive value If $y(t_1)<\lambda$, $C_2$ triggers a negative value. The DC-VG is designed such that for each positive input value, it increases its output signal level by $-2\lambda$, whereas, for a negative input value, it decreases its output voltage by $2\lambda$. Hence, in the current example, DC-VG generates signal $z(t) = \text{sgn}(y_\lambda(t_1)) 2\lambda u(t-t_1)$ where $u(t)$ is unit-step function. In this way, by adding or subtracting (using $S$) constant DC signals from $y(t)$ whenever it crosses the dynamic range $[-\lambda, \lambda]$, the amplitude levels of $y_\lambda(t)$ are kept within ADC's dynamic range.

\begin{figure}[!h]
	\centering
	\begin{tabular}{c}
		\subfigure[] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Fig3_2Folding_6Vpp_3Vbias_1KHz_Up_Clr.png}\label{fig:Up_Folding}} \\
		\subfigure[] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Fig3_2Folding_6Vpp_3Vbias_1KHz_Down_Clr.png}\label{fig:Down_Folding}} \\
	\end{tabular}
	\caption{DC-VG based folding operation. (a)-(b) denote the real-time capture of an oscilloscope displaying the input signal (yellow), its folded output (green), the DC-VG signal (blue), and the C1 and C2 comparator (red) respectively.}
	\label{Fig:DC-VG_folding_mechanism}
\end{figure}

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3 in]{Figs/dc_vg}
	\caption{DC-VG}
	\label{Fig:dcvg}
\end{figure}

\begin{figure*}[!t]
	\centering
	\includegraphics[width=0.86\textwidth ]{IEEE_TAES_v1/Figs/UDR_Board_Labeled3.PNG}
	\caption{Modulo hardware board.}
	\label{Fig:hw_board}
\end{figure*}

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3.2 in]{IEEE_TAES_v1/Figs/Fig6_1KHz_10Vpp_4Folding_New_Clr.png}
	\caption{
	Live screenshot of an oscilloscope capturing the 1kHz sinusoid input signal (yellow), its folded output (green), and the DC-VG signal (blue).}
	\label{Fig:Analysis_of_folding_ability}
\end{figure}

\begin{figure}[!h]
	\centering
	\begin{tabular}{c}
		\subfigure[] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Fig7_1Folding_6Vpp_1KHz_New_Clr.png}\label{fig:1k_1}} \\
		\subfigure[] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Fig7_1Folding_6Vpp_10KHz_New_Clr.png}\label{fig:10k_1}} \\
		\subfigure[] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Fig7_1Folding_6Vpp_20KHz_New_Clr.png}\label{fig:20k_1}}
	\end{tabular}
	\caption{Analysis of frequency response of the modulo hardware (a)-(c) denote the real-time capture of an oscilloscope capturing the 1kHz, 10kHz, 20kHz, respectively, the sinusoidal input signal (yellow), its folded output (green), the DC-VG signal (blue).}
	\label{Fig:frequency_response}
\end{figure}

\begin{table}[h!]
		\caption{Up/down counter operation.}
	\centering
	\begin{tabular}{||c c c c c ||}
		\hline
		c & b & a & sgn & Counter values \\ [0.5ex]
		\hline\hline
		0 & 0 & 0 & 0~(1) & 0~(0) \\
		0 & 0 & 1 & 0~(1) & 1~(-1) \\
		0 & 1 & 0 & 0~(1) & 2~(-2) \\
		0 & 1 & 1 & 0~(1) & 3~(-3) \\
		1 & 0 & 0 & 0~(1) & 4~(-4) \\
		1 & 0 & 1 & 0~(1) & 5~(-5)\\
		1 & 1 & 0 & 0~(1) & 6~(-6)\\
		1 & 1 & 1 & 0~(1) & 7~(-7)\\
		\hline
	\end{tabular}
	\label{table:counter}
\end{table}

While the parts such as comparators $C_1$, $C_2$, and adder $S$ can be realized by using off-the-shelf components, DC-VG is a more involved system and required careful design. A detailed architecture of DC-VG is shown in Fig.~\ref{Fig:dcvg}. It consists of an up/down counter, a digital-to-analog converter (DAC), a multiplexer (MUX), and a multiplier $M$.  The function of the counter, along with the DAC, is to produce a piece-wise constant DC voltage whenever a trigger is present at its input. By employing the MUX and multiplier $M$, the voltage values are configured to be multiples of $2\lambda$.
To explain the working principle, we will first discuss the function of the counter, followed by the other components.

In this particular system, we use a three-bit synchronous up/down counter. The bits from lower significant bit to higher significant bit are denoted as a, b, and c, respectively. The counter has an additional sign bit shown as sgn. With these bits, the counter can count from -7 to 7. For each positive input trigger, the output counts up, and for each negative input trigger, it counts down. In Table~\ref{table:counter}, we list the values of bits and the counter (denoted as counter values). The three bits (a,b, and c) of the counter are used as input to the DAC which converts the bits to an analog DC voltage. Let the resolution or step size of the DAC is $\alpha$ then the output of DAC is $\alpha$ times the counter-value. To be more specific, consider the scenario where the output of the counter and DAC are zero. DAC's output then increases (decreases) by $\alpha$ in response to a positive (negative) trigger. DAC's output signal, $s(t),$ is a piecewise constant signal whose values are multiples of $\alpha$. For folding to function, however, the voltage change must be in multiples of $2\lambda$. Further, we employ a MUX whose output is $2\lambda$ or $-2\lambda$ depending on whether its input (sign bit) is 1 or 0. Then, $z(t)$ is generated by multiplying the output of DAC by the output of MUX.

Fig. \ref{fig:Up_Folding} (Fig. \ref{fig:Down_Folding}) demonstrates the DC-VG based folding operation time sequence beginning with the C1 (C2) comparator trigger operation, in red, followed by $z(t)$, in blue, which results in a 2$\lambda$ increase (decrease) of $y_\lambda(t)$, in green, and keeping it within the $\pm\lambda$ ADC range.

Next, we discuss the hardware board that realizes the folding operation discussed in this section.

\begin{table}[h!]
\centering
\caption{List of Hardware Components}
\label{table:hardware_components}
\begin{tabular}{||c c c||}
 \hline
 Component & Model Number & Make \\
 && \\ \hline
 Comparator & LM339 & Texas Instruments \\
 && \\
 UP/DOWN Counter & TEENSY4.1 & PJRC \\
 && \\
 DAC 3bits & LT1364 & Analog Devices \\
 && \\
 Analog MUX & ADG1608 & Analog Devices \\
 && \\
 Analog Multiplier & AD835 & Analog Devices \\
 && \\
 Adder & LT1364 & Analog Devices \\
  && \\ [1ex]
\hline
\end{tabular}
\end{table}
\subsection{Modulo Hardware Board}
Our modulo hardware board is presented in Fig.~\ref{Fig:hw_board}, along with the roles of the major building components. Table~\ref{table:hardware_components} contains a detailed listing of the hardware's components. The board is designed for $\lambda\leq1.25$ volts or less. The board can accommodate an input signal with a dynamic range between $[-8\lambda, 8\lambda]$, which means that an ADC equipped with our modulo hardware can sample signals four times bigger than its dynamic range without saturation and clipping.

We demonstrate the working of the modulo hardware by considering a sinusoidal signal $y(t) = A\, \sin(2\pi f_0 t)$ where $A$ is amplitude and $f_0$ is the frequency (in Hz). In this experiment, we set $\lambda = 1.25$ and $-4\lambda <A <+4\lambda$. With this setting, we expect the signal to fold 4 times in a half sinusoidal cycle. Fig.~\ref{Fig:Analysis_of_folding_ability} depicts a screenshot of an oscilloscope capturing input $y(t)$ (in yellow) and its folded output $y_\lambda(t)$ (in green) in addition to the DC-VG output signal $z(t)$ (in blue), for $f_0 = 1$kHz. We observed that the signals are folded back to lie within the dynamic range of the ADC as expected without clipping. Next, we discuss the frequency response of the modulo ADC. As in any analog system, the response of the modulo folder too depends on the frequency or bandwidth of the input signal. Beyond a particular frequency, the folding may not be accurate as demonstrated in Fig.~\ref{Fig:frequency_response}. We observed that for signals of 1kHz and 10kHz the hardware is able to fold the signal accurately. However, for $f_0 = 20$kHz, folding instants are not symmetric for positive and negative folds. In one of our future works, we are planning to design hardware that overcomes this limitation by using faster hardware logical components to implement the folding counter instead of using the current up/down counter. The current implementation demonstrates a proof of concept of implementing the modulo concept in the analog domain in a near real-life environment and paves the way for high-frequency applications which support high dynamic range operation.

In the next section, we discuss a couple of inaccuracies of the modulo hardware and our proposed solutions to overcome those.

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3.2 in]{Figs/mod_td}
	\caption{Effect of time delay of the feedback loop on the modulo operation.}
	\label{Fig:mod_td}
\end{figure}

\subsection{Artifacts During Folding}
Errors or other artifacts that arise during folding operations in hardware could be due to various reasons. One of the major issues that arise in a modulo ADC is the time delay in the feedback loop (See Fig.~\ref{Fig:folding}). To elaborate, consider a scenario where $y(t)<\lambda$ for $t<t_1$ and it crosses $\lambda$ at time $t_1$ as discussed earlier. To fold the output voltage to the dynamic range of the ADC, $z(t) = 2\lambda u(t-t_1)$ needs to be subtracted from $y(t)$. However, there is a finite delay between the trigger time $t_1$ to generating $z(t)$. If the time delay is $T_d$, then $z(t) = 2\lambda u(t-t_1-T_d)$ is subtracted, which causes distortion. To illustrate this effect, in Fig.~\ref{Fig:mod_td}, we considered a sinusoidal signal (in blue) and its folded versions with and without delay. We observe that in the absence of any time delay ($T_d=0$) the signal folds perfectly (shown in red) to stay within the dynamic range. However, for a non-zero value of $T_d$, foldings do not take place at the folding instants, and the output of the modulo operator (shown in black) still remains outside the dynamic range $[-\lambda, \lambda]$, which results in a clipped modulo operator output. However, the proposed hardware solution addresses this issue and avoids the undesired clipping as shown in Figs.~\ref{Fig:Analysis_of_folding_ability} and \ref{Fig:frequency_response}.

Our solution uses the fact that with a finite time delay, the amount of overshoot of a smooth signal can be bounded. To elaborate, let us assume that the signal that undergoes modulo operation is Lipschitz continuous. Specifically, a signal $y(t)$ is Lipschitz continuous if there exists a positive real number $\mathrm{L}_y$ such that for any $T>0$ we have
\begin{align}
    |y(t) -y(t+T)|\leq \mathrm{L}_y\, T.
    \label{eq:lipschitz}
\end{align}
With the Lipschitz smoothness condition, we note that the amplitude of $y(t)$ can not change more than $\mathrm{L}_y\, T_d$ between any folding instant and time of its effect to take place. Hence, if we choose dynamic range of the ADC to be $[-(\lambda+\Delta \lambda), (\lambda+\Delta \lambda)]$ where $\Delta \lambda = \mathrm{L}_y\, T_d$ then the signal will not clip. We show this extended dynamic region in the illustrative example in Fig.~\ref{Fig:mod_td}. Alternatively, instead of increasing ADC's dynamic range, one can keep it to be $[-\lambda, \lambda]$ and reduce the threshold values for comparators. In this case, $C_1$ will trigger when the input crosses $\lambda-\Delta \lambda$ and $C_2$ will trigger when the input goes beyond $-\lambda+\Delta \lambda$. In this way, the time delay issue is addressed by the modulo circuit without altering ADC's dynamic range.

In order to apply the solution, the signal must be Lipschitz continuous. In our design, the modulo operation input signal is always a lowpass or bandlimited signal satisfying the Lipschitz smoothness condition \cite{bl_bound}. For a bandlimited signal $y(t)$ its Lipschitz constant $\mathrm{L}_y$ is directly proportional to its bandwidth $\omega_c$ which is the same as the cutoff frequency of the LPF.
Hence, for a given value $\Delta \lambda$ and $T_d$ (both depend on the modulo circuit), $\mathrm{L}_y = \Delta \lambda/T_d$ is fixed and this restricts the maximum frequency of the input signal that can be faithfully folded. In the current design, we choose to implement the counter management using a TEENSY microcontroller, resulting in a $1 \mu$s time delay. This enables the hardware to accommodate a wide range of frequencies without requiring any modifications to the hardware components.

Another issue one can observe after DC-VG switching is that the voltage at the output of DC-VG either overshoots or undershoots (refer to Fig.~\ref{Fig:Analysis_of_folding_ability}) before the oscillations settle down to the expected value. This issue may be resolved by using a faster adder $S$ whose response time should be at least a magnitude higher than the sample rate. In one of our future works, we are planning to design hardware that overcomes this limitation.

\section{Results}
In this section, we demonstrate the modulo hardware described in the previous section's signal reconstruction capability.
In the hardware settings consider here, the samples are contaminated by the measurement noise. In addition, quantization plays a role when a finite-resolution quantizer is used after the sampler. We model all these noises and inaccuracies as additive noise at the output of the sampler. Specifically, the noisy measurements are given as
 \begin{align}
            \tilde{y}_{\lambda}(n T_s) = {y}_{\lambda}(n T_s) + v(n T_s),
        \label{eq: noisy_samples}
        \end{align}
where $v(n T_s)$ is the noise term. Both unfolding and parameter estimation algorithms should be robust to different noise models. The robustness of parameter estimation methods in the presence of noise is well studied (See \cite{mulleti_kernal, stoica, eldar_sos}). In \cite{eyar_moduloicassp}, we presented comparisons of unfolding algorithms for bandlimited signals. We showed that our beyond-bandwidth residual recovery ($B^2R^2$) approach results in a lower error during unfolding compared to the \emph{higher-order differences} (HOD) approach \cite{unlimited_sampling17, uls_tsp} and \emph{Chebyshev polynomial filter}-based (CPF) method \cite{uls_romonov}. Importantly, for a given sampling rate, $\lambda$, and signal-to-noise ratio (SNR), the $B^2R^2$ method results in the lowest error for both bounded and unbounded noise models.

Before presenting hardware results, we compare the performances of the $B^2R^2$ method with HOD and CPF approaches for quantization noise and unbounded noise. We would like to point out that quantization noise was not considered in \cite{eyar_moduloicassp}. Although, the algorithms were compared for unbounded noise the simulation settings were different than those in our hardware. Hence, for a better understanding, we compared our algorithm for unbounded noise and quantization  noise with the current hardware settings. In the next section, we present these simulation results and then present hardware results.

\begin{figure}[!t]
	\centering
	\includegraphics[width= 2.5 in]{IEEE_TAES_v1/Figs/quantization.png}
	\caption{Comparison of HOD, CPF, and $B^2R^2$ algorithms after the quantization process in terms of MSE when recovering a bandlimited signal from modulo samples with $\lambda = 1.25$ and OF = 3,6. For a given number of bits, $B^2R^2$ has the lowest MSE.}
	\label{Fig:quantization}
\end{figure}

\begin{figure}[!t]
	\centering
	\includegraphics[width= 2.5 in]{IEEE_TAES_v1/Figs/Gaussian.png}
	\caption{Comparison of HOD, CPF and $B^2R^2$ algorithms (with unbounded noise) in terms of MSE when recovering a bandlimited signal from modulo samples with  $\lambda$ = 1.25 and OF = 3,6. For a given SNR and OF, $B^2R^2$ has the lowest MSE.}
	\label{Fig:unbounded}
\end{figure}
\subsection{Simulated Results}
In this section, we compare our $B^2R^2$ algorithm with the \emph{higher-order differences} (HOD) approach \cite{unlimited_sampling17, uls_tsp} and \emph{Chebyshev polynomial filter}-based (CPF) method \cite{uls_romonov}. We consider the noise measurements as in \eqref{eq: noisy_samples} for simulation data. In the simulations, $\lambda$ is set to be $1.25$ as in the hardware. We normalize the bandlimited signals to have a maximum amplitude of $10$. The SNR is calculated as $\text{SNR} = 20 \log\left(\frac{||y_{\lambda}(n T_s)||}{||v(n T_s)||}\right)$. The reconstruction accuracy of different methods is compared in terms of the normalized mean-squared error (MSE) as $ \frac{\sum |y(nT_s) - \hat{y}(n Ts)|^2}{\sum |y(nT_s)|^2}$, where $\hat{y}(n T_s)$ estimate of $y(n T_s)$. For different noise settings and over-sampling factors (OFs), we considered 100 independent noise realizations and calculated the average MSE for them. We first consider quantization noise and then present results for unbounded noise.

\begin{figure}[!t]
    \centering
    \includegraphics[width=0.3\textwidth]{IEEE_TAES_v1/Figs/Signal Generator.png}
    \caption{Bandlimited signal generator.}
    \label{fig:UDRSignalGen}
\end{figure}

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3.2 in]{IEEE_TAES_v1/Figs/Up_2mS_Clr.png}
	\caption{Bandlimited folded signal.}
	\label{Fig:Bandlimited_folded_signal}
\end{figure}

 First, we consider a uniform quantizer after the sampling. The unfolding algorithms are applied on the quantized samples. The MSE in the estimation of bandlimited signals for a different number of bits and OFs is shown in Fig. ~\ref{Fig:quantization}. We observe that for a given $\text{OF}$, $B^2R^2$ algorithm results in the lowest MSE for less than 5 bits. For more than 5 bits all the algorithms, except HOD with OF = 3, perform equally well. The results show that low-resolution quantizers can be used with the $B^2R^2$ algorithm for unrolling which saves both power and memory requirements.

Next, for unbounded noise, we assume that the noise measurements $v(nT_s)$ are independent and identically distributed Gaussian random variables with zero mean. The variance is set to achieve the desired SNR. We compare the methods for different values of SNR and OFs with $\lambda = 1.25$. Fig.~\ref{Fig:unbounded} shows the MSE of the different algorithms for OF $= 3$ and $6$. We note that our algorithm results in the lowest error for a given OF and SNR.

Given the advantages of the $B^2R^2$ algorithm over the other approaches, we present the hardware results in the next section by using this method.

\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/BL1_scope_11_Clr.png}\label{fig:BL1_scope}} \\
		\subfigure[]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/BL2_scope_13_Clr.png}\label{fig:BL2_scope}}
	\end{tabular}
	\caption{Live screen shot of an oscilloscope capturing the input bandlimited signals (yellow) and its folded output signals (green).}
	\label{fig:BL_scopeex1}
\end{figure}
\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/BL1_rec.png}\label{fig:BL1}} \\
		\subfigure[]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/BL2_rec.png}\label{fig:BL2}}
	\end{tabular}
	\caption{Hardware results for bandlimited signals. The $B^2R^2$ algorithm is used to unfold $y_\lambda(t)$ (measured at the output of hardware), and the unfolded signal $\hat{y}(t)$ is plotted with bandlimited signal $y(t)$.}
	\label{fig:BL_ex1}
\end{figure}

\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[Screen shot of the oscilloscope capturing filtered FRI signal (yellow), its folded output (green), and the DC-VG signal (blue).] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/FRI1_1_Clr.png}\label{fig:FRI1_1k}} \\
		\subfigure[Filtered FRI signal with its folded and unfolded versions.]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Ex1_lpf.pdf}\label{fig:FRI_LPF1}}\\
		\subfigure[FRI signal reconstruction.] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Ex1_fri.pdf}\label{fig:FRI1_REC}} \\

	\end{tabular}
	\caption{Reconstruction of FRI signal ($L=2$) via the modulo hardware .}
	\label{Fig:FRI1}
\end{figure}

\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[Screen shot of the oscilloscope capturing filtered FRI signal (yellow), its folded output (green), and the DC-VG signal (blue).] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/FRI2_1_Clr.png}\label{fig:FRI2_1k}} \\
		\subfigure[Filtered FRI signal with its folded and unfolded versions.]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Ex2_lpf.pdf}\label{fig:FRI_LPF2}}\\
		\subfigure[FRI signal reconstruction.] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Ex2_fri.pdf}\label{fig:FRI2_REC}} \\
	\end{tabular}
	\caption{Reconstruction of FRI signal ($L=3$) via the modulo hardware .}
	\label{Fig:FRI2}
\end{figure}

\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[Screen shot of the oscilloscope capturing filtered FRI signal (yellow), its folded output (green), and the DC-VG signal (blue).] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/FRI3_1_Clr.png}\label{fig:FRI3_1k}} \\
		\subfigure[Filtered FRI signal with its folded and unfolded versions.]{\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Ex3_lpf.pdf}\label{fig:FRI_LPF3}}\\
		\subfigure[FRI signal reconstruction.] {\includegraphics[width=3.2in]{IEEE_TAES_v1/Figs/Ex3_fri.pdf}\label{fig:FRI3_REC}} \\

	\end{tabular}
	\caption{Reconstruction of FRI signal ($L=5$) via the modulo hardware.}
	\label{Fig:FRI3}
\end{figure}

\subsection{Hardware Results}
In this section, we present results from the hardware.
Since bandlimited signals are input to the hardware, we first present results for them and then show results for FRI signals. If the hardware and unfolding algorithm are able to recover the bandlimited signals with high accuracy then it will lead to a better reconstruction of the FRI signals. In all these experiments we set $\lambda = 1.25$ V and the cutoff frequency of the lowpass filter is 1kHz. We observe that for frequencies less than or equal to 10kHz, our hardware is able to reliably fold the signal. The Nyquist rate of the signal is 2kHz. But for unfolding, we need to oversample the signal. In all these experiments, we used the $B^2R^2$ algorithm with OF = 5 which results in a sampling rate of 10kHz. Further, $y(t)$ (yellow) and $y_\lambda(t)$ (green) are measured from the hardware through an oscilloscope for processing by the algorithms as described in Fig. \ref{Fig:Bandlimited_folded_signal}.

We first consider the bandlimited signals. For generating bandlimited or lowpass signals we used an Arduino microcontroller (See Fig.~\ref{fig:UDRSignalGen}) which converts the digital signal to an analog signal via a DAC. The digital signals were generated using MATLAB software. Two examples of 1khz bandlimited signal are presented in Fig. \ref{fig:BL1_scope} and Fig. \ref{fig:BL2_scope}. In Fig.~\ref{fig:BL_ex1}, we show folding and reconstruction, using the $B^2R^2$ algorithm, of the two bandlimited signals that are displayed in Fig. \ref{fig:BL_scopeex1}. These signals have a maximum amplitude of 5V. We observe the signals are restricted to $[-\lambda, \lambda]$ by the modulo hardware, and the algorithm was able to recover the true signal from the folded samples. The reconstructed signal has a slightly larger amplitude compared to the true signal which is the result of scaling within the hardware.

\subsection{Application to FRI Signals}
Consider an FRI signal consisting of a stream of $L$ pulses:
\begin{align}
	f(t) = \sum_{\ell=1}^L a_\ell h(t-t_\ell),
	\label{eq:fri1}
\end{align}
where the pulse $h(t)$ a real-valued known pulse. We assume that $\{a_\ell\}_{\ell = 1}^L$ are real-valued and $\{t_\ell\}_{\ell = 1}^L \subset (0, T_0] \subset \mathbb{R}$ for a known $T_0$.

The FRI signal model in \eqref{eq:fri1} is encountered in several scientific applications such as radar imaging \cite{bar_radar, bajwa_radar, sunil}, ultrasound imaging \cite{eldar_sos,eldar_beamforming,mulleti_icip}, light detection and ranging (LIDAR) \cite{castorena_lidar}, time-domain optical coherence tomography (TDOCT) \cite{blu_oct}, and other time-of-flight imaging systems. In these applications,  $h(t)$ is the transmitted pulse and $\{a_\ell \,h(t-t_\ell)\}_{\ell=1}^{L}$ constitute the reflections from $L$ point targets. The amplitudes $\{a_\ell\}_{\ell = 1}^L$ depend on the sizes of the targets and the delays $\{t_\ell\}_{\ell = 1}^L$ are proportional to the distances of the targets from the transmitter. Here $T_0$ denotes the maximum time delay of the targets. The signal $f(t)$ is specified by $\{a_\ell, t_\ell\}_{\ell=1}^L$ and can be reconstructed from its sub-Nyquist measurements acquired using an appropriate sampling kernel \cite{vetterli,eldar_sos,fri_strang, mulleti_kernal}. Given their widespread application, here we consider sampling and reconstruction of FRI signals by using our hardware prototype.

FRI signals can be perfectly reconstructed by applying high-resolution spectral estimation methods, such as the annihilating filter (AF) or Prony's method and its variants
\cite{prony, plonka, schmidt_music, barabell_rmusic, bdrao_rmusic,sarkar_mp,paulraj_esprit} to the Fourier measurements
\begin{align}
	S(k\omega_0) = \frac{F(k\omega_0)}{H(k\omega_0)} =  \sum_{\ell = 1}^L a_\ell \, e^{-\mathrm{j}k\omega_0 t_\ell}, \, k \in \{-K, \cdots, K\},
	\label{eq:Skomega}
\end{align}
where we assume that $H(k \omega_0) \neq 0$. Here $K \geq L$ and $\omega_0 = \frac{2\pi}{T_0}$ \cite{eldar_2015sampling}. The Fourier measurements $\{S(k\omega_0)\}_{k =-K}^K$ can be determined from the samples $(f*g)(nT_s)$ where $g(t)$ is an ideal lowpass filter with bandwidth $[-K\omega_0, K \omega_0]$ and $T_s = \frac{2\pi}{(2K+1)\omega_0}$. In practice, the duration of the pulse $h(t)$ is very short, and hence $f(t)$ has a wide bandwidth. This results in a large sampling rate (or Nyquist rate) if $f(t)$ is sampled directly. However, the filtered signal $y(t) = (f*g)(t)$ is bandlimited to $[-K\omega_0, K \omega_0]$ which is much smaller than that of $h(t)$ and the sampling rate is much lower than the Nyquist rate.

As in the bandlimited signal model, a modulo operation can be applied to the filtered signal $y(t)$ to avoid clipping. Then $y_\lambda(t)$ is sampled. Then to determine the Fourier samples $\{S(k\omega_0)\}_{k =-K}^K$, unfolding is first applied. Since the filtered signal is bandlimited, we use the proposed hardware for modulo folding and can apply the $B^2R^2$ algorithm from unfolding.

In our setup, to generate the FRI signals, we consider $h(t)$ to be a short pulse of bandwidth 30kHz (Nyquist rate = 60kHz). We consider three examples with $L=2, 3,$ and 5. The amplitudes and time delays are generated randomly. The maximum time delay is $T_0 = 0.1$ sec. Once generated, the FRI signal is lowpass filtered with a cutoff frequency of 1kHz. Up to the filtering operation, MATLAB is used and then an Arduino micro-controller is used to generate the analog version of the filtered FRI signals. The signal is then folded using the hardware and the folded signals are sampled. The sampling rate is 10kHz which is five times higher than the sampling rate of the lowpass signal. Still, the rate is six times lower than the Nyquist rate and hence the system operates at a sub-Nyquist rate.

We first apply the $B^2R^2$ algorithm to unfold the signal and then used ESPRIT \cite{paulraj_esprit} to estimate the time delays and amplitudes of the FRI signals.
In Fig.~\ref{Fig:FRI1}, Fig.~\ref{Fig:FRI2} and  Fig.~\ref{Fig:FRI3} we show sampling and reconstruction of FRI signals with $L=2,3,5$ respectively.
The FRI signals followed by a lowpass filter are presented in Fig.~\ref{fig:FRI1_1k}, Fig.~\ref{fig:FRI2_1k}, and  Fig.~\ref{fig:FRI3_1k}.
The reconstruction of the lowpass signals displayed in Fig.~\ref{fig:FRI_LPF1}, Fig.~\ref{fig:FRI_LPF2} and  Fig.~\ref{fig:FRI_LPF3}, where $y(t)$ described the LPF output, $y_\lambda(t)$ is the folded signal (output of the modulo hardware), and the unfolded signals are given by $\hat{y}(t)$. Fig.~\ref{fig:FRI1_REC}, Fig.~\ref{fig:FRI2_REC} and Fig.~\ref{fig:FRI3_REC} show location and amplitude of the true signal $f(t)$ and estimated FRI signal $\hat{f}(t)$.
The maximum error in the estimation of time delay is $-15$ dB which shows that the system can be used in applications like radar and ultrasound imaging.

\section{Conclusions}
 We presented a hardware prototype for the modulo folding system and show that for different bandlimited and FRI signals, the hardware is able to faithfully fold the signal. We also  address the time delay issue of the modulo system and presented a hardware solution for the same. The overall system operates at five times below the Nyquist rate which enables one to use low-rate, low-dynamic range, power-efficient ADCs.

\bibliographystyle{IEEEtaes}

\section{INTRODUCTION}
Sampling plays a key role in efficiently processing real-world analog signals on digital signal processors. Analog to digital converters (ADCs) are used to implement sampling in the hardware. A key parameter of the ADC is its sampling rate. ADCs with high sampling rates are power consuming and expensive which make them unsuitable for portable devices such as hand-held ultrasound device. Hence, it is desirable to reduce the sampling rate. Following the Shannon-Nyquist sampling theorem \cite{shannon, nyquist}, it is well known that the sampling rate of bandlimited signals are dictated by their highest frequency. Hence, in wideband signal applications one can not sample below the Nquist rate by considering the bandlimited signal model.

Finite-rate-of-innovation (FRI) model is another signal model which is ubiquitous in several time of flight applications \cite{bajwa_radar, bar_radar,filho201seismic,rip,carter_sonar,eldar_sos,eldar_beamforming}. In these applications, the signal of interest consists of a linear combination of delayed copies of a known pulse. Thus, the desired information lies in the amplitudes and time delays of the pulse which amounts to few degrees of freedom and aids sub-Nyquist sampling \cite{eldar_2015sampling}. Most prior works in the context of FRI sampling are focused on reducing the sampling rate of the ADC by using the signal structure and consequently reducing the power consumption and cost of the ADCs \cite{vetterli, eldar_sos, fri_strang, blu_moms, mulleti_kernal}.

Dynamic range of an ADC too plays a crucial role in sampling an analog signal. In general, ADC's dynamic range should be larger than that of the signal's, otherwise the signal is clipped. There exist a few approaches to recover the true samples from clipped ones for bandlimited signals \cite{marks_clipping2, marks_clipping1}. These approaches relies on correlation among the samples when they are measured at very high-rate compared to the Nyquist rate. Requirement of high-sampling rate is a drawback of these approaches. In addition, theoretical guarantees are missing and it is not clear on how many clipped samples can be recovered.

There are three popular analog preprocssing approaches, namely automatic gain control (AGC) \cite{perez2011automatic,mercy1981review}, companding \cite{landau_compander,landau_distorted_bl}, and modulo folding \cite{uls_tsp,uls_romonov,uls_sparse,bhandari2021unlimited,eyar_moduloicassp}, that can be used prior to sampling to avoid clipping. In AGC, a chain of amplifiers is used with a feedback loop such that a suitable output level is maintained at the output \cite{perez2011automatic,mercy1981review}. An AGC system uses a closed loop feedback mechanism to maintain a constant signal level at its output for a varying input signal levels \cite{perez2011automatic,mercy1981review}. The closed loop feedback consists of a chain of amplifiers and maintaining its stability is a challenging task. Companding is an alternative approach to limit the dynamic range of the input signals. In this approach, smaller amplitudes of the signals have larger gain compared to the larger ones. Beurling presented theoretical guarantees and proved that knowledge of the companded signal over the input signal's bandwidth is sufficient to uniquely identify the signal provided \cite{landau_compander}. Landau et al. \cite{landau_distorted_bl} proposed an iterative algorithm to recover a bandlimited signal from its companded signal. The algorithm converges if the compander is differentiable over the dynamic range of the input signal which limits its practical application.

The third approach is to use modulo folding prior to sampling which fold the input signal to lie within the dynamic range of the ADC \cite{uls_tsp,uls_romonov,uls_sparse,bhandari2021unlimited,eyar_moduloicassp}. The folded signal is then sampled by using a conventional ADC. Theoretical guarantees for recovering bandlimited signals from folded samples are presented in \cite{uls_tsp,uls_identifiability}. The results states that the bandlimited signals can be uniquely recovered from folded samples provided that they are sampled above the Nyquist rate. Several algorithms for \emph{unfolding} or recovering the true samples of bandlimited signals from modulo or folded samples are presented in \cite{uls_tsp,uls_romonov, eyar_moduloicassp}. These unfolding algorithms can be compared in terms of sampling rate, amount of unfolding they can accommodate, and noise robustness. It is shown that the method proposed in \cite{eyar_moduloicassp} has lowest reconstruction error for a given sampling rate, noise level, and signal's amplitude level compared to the algorithms presented in \cite{uls_tsp,uls_romonov}. The algorithm proposed in \cite{uls_tsp} requires almost 17-times higher sapling rate than the Nyquist rate but it is independent of the dynamic range of the ADC. Whereas, the approaches in \cite{uls_romonov, eyar_moduloicassp} requires the knowledge of ADC's dynamic range. Modulo sampling is also extended to different problems and signal models such as periodic bandlimited signals \cite{bhandari2021unlimited}, wavelets \cite{uls_wavelet}, mixture of sinusoids \cite{uls_sinmix}, finite-rate-of-innovation signals \cite{uls_fri}, multi-dimensional signals \cite{uls_md}, sparse vector recovery \cite{uls_gamp, uls_sparsevec}, direction of arrival estimation problem \cite{uls_doa}, computed tomography \cite{uls_radon}, and graph signals \cite{uls_graph}.

While theoretical guarantees and algorithms of any new sampling approach are always well researched but the question on whether they work in practice is always difficult to answer. For modulo sampling, there exists a few hardware prototypes. For example, high-dynamic-range ADCs, also known as \emph{self-reset} ADCs, are discussed in the context of imaging \cite{sradc_park, sradc_sasagwa, sradc_yuan, krishna2019unlimited}. These hardware architectures measures additional information such as the amount of folding for each sample, or, the sign of the folding together with the folded samples. The additional information might enable simpler recovery but at the expense of complex circuitry. Importantly, additional bits are required during the quantization process to store or transmit the side information.

Krishna et al. presented a hardware prototype which encode the side-information by using two bits \cite{krishna2019unlimited}. The architecture is designed to record sign of the slope of the signal at each sampling instant when the sample lies outside ADC's dynamic range. In a conventional ADC, a sample and hold (S/H) circuit is used to hold the sampled value for a prescribed period of time during which quantization is performed on the sample. To realize the modulo sampling, a folding circuit is used after S/H \cite{krishna2019unlimited}. Hence, the S/H circuit has to hold the sampled value for folding and quantization, which results in a larger folding time compared to a conventional ADC. A large holding time results in slower ADC and hence it may not be useful for wideband application.

The proposed modulo-ADC is able to sample signals beyond its dynamic range while keeping the power dissipation and area requirements lower compared to a conventional ADC \cite{krishna2019unlimited}. A major drawback of this modulo-ADC's architecture is that the modulo operation is performed between the sample and hold (S/H), and quantization blocks of the ADC. Specifically, modulo operation is performed on the hold values of S/H circuit and then the folded sample is quantized. Hence, compared to a conventional ADC, the hold time is relatively high which makes the architecture slower.

\newpage
In introduction, we discuss the following:

1st-paragraph: Standard sampling and sub-Nyquist; importance of low sampling rates; FRI signal model and application to radar\\

2nd-paragraph: Introduce the dynamic range issue and discuss the existing approaches to address it: AGC, commanding, and modulo. Why modulo is important.\\

3rd paragraph: Discuss about modulo method, recovery algorithms and their issues with high-sampling rates and instability in noise. Discuss about our proposed algorithm (Eyar's ICASSP-22 paper)\\

4th paragraph: Can we implement these in HW? Discuss about hardware prototypes and applications. Shortcomings: No practical applications, low operating frequencies, more?\\

5th paragraph: In this paper, we present a HW prototype combined with recently proposed algorithm to address these issues.\\

 6th Paragraph: The paper is organized as follows; Notations \\

\section{Signal Model and System Description}
In this section, we first introduce FRI signal model and then discuss its sampling and reconstruction framework with modulo ADC.
\subsection{FRI Signal Model}
Consider an FRI signal consisting of stream of $L$ pulses:
\begin{align}
	f(t) = \sum_{\ell=1}^L a_\ell h(t-t_\ell),
	\label{eq:fri1}
\end{align}
where the pulse $h(t)$ a real-valued known pulse. We assume that $a_\ell$s are real-valued and $t_\ell \in (0, T_d] \subset \mathbb{R}$ for a known $T_d$.

The FRI signal model in \eqref{eq:fri1} is encountered in several scientific applications such as radar imaging \cite{bar_radar, bajwa_radar, sunil}, ultrasound imaging \cite{eldar_sos,eldar_beamforming,mulleti_icip}, light detection and ranging (LIDAR) \cite{castorena_lidar}, time-domain optical-coherence tomography (TDOCT) \cite{blu_oct}, and other time-of-flight imaging systems. In these applications,  $h(t)$ is the transmitted pulse and $\{a_\ell \,h(t-t_\ell)\}_{\ell=1}^{L}$ constitute the reflections from $L$ point targets. The amplitudes $a_\ell$s depend on the sizes of the targets and the delays $t_\ell$s are proportional to the distances of the targets from the transmitter. Here $T_d$ denotes maximum time delay of the targets. The signal $f(t)$ is specified by $\{a_\ell, t_\ell\}_{\ell=1}^L$ and can be reconstructed from its sub-Nyquist measurements acquired using an appropriate sampling kernel \cite{vetterli,eldar_sos,fri_strang, mulleti_kernal}. The reconstruction is generally carried out in frequency domain as discussed next.

\subsection{Fourier-Domain Reconstruction}
Consider uniform samples of continuous-time Fourier transform of $f(t)$ given as
\begin{align}
	F(k \omega_0) = \int f(t) e^{-\mathrm{j} k\omega_0 t} \mathrm{d}t = H(k \omega_0) \sum_{\ell = 1}^L a_\ell \, e^{-\mathrm{j} k\omega_0 t_\ell},
	\label{eq:F}
\end{align}
for $k \in \mathcal{K}$ where $H(\omega)$ is the Fourier transform of $h(t)$ and $\mathcal{K}$ is a set integers. In \eqref{eq:F}, $\omega_0>0$ denotes sampling interval in the frequency domain. Next, consider the following samples
\begin{align}
	S(k\omega_0) = \frac{F(k\omega_0)}{H(k\omega_0)} =  \sum_{\ell = 1}^L a_\ell \, e^{-\mathrm{j}k\omega_0 t_\ell},
	\label{eq:Skomega}
\end{align}
where we assume that $H(k \omega_0) \neq 0$ for $k \in \mathcal{K}$. In practice, the pulse $h(t)$ has small time support and hence, large bandwidth. Hence, for a finite set $\mathcal{K}$ it is possible to choose a set of frequencies $\{k \omega_0\}_{ k \in \mathcal{K}}$ such that $H(k \omega_0) \neq 0$ for $k \in \mathcal{K}$. It can be shown that $2L$ consecutive samples of $S(k\omega_0)$ are sufficient to uniquely identify $\{a_\ell, t_\ell\}_{\ell=1}^L$ if $\omega_0 = \frac{2\pi}{T_d}$ \cite{eldar_2015sampling}. In practice, high-resolution spectral estimation methods, such as the annihilating filter (AF) or Prony's method and its variants \cite{prony, plonka}, multiple signal classification \cite{schmidt_music, barabell_rmusic, bdrao_rmusic}, matrix-pencil method \cite{sarkar_mp}, estimation of signal parameter via rotational invariance technique (ESPRIT) \cite{paulraj_esprit}, etc. have been deployed for FRI parameter estimation.

Since $h(t)$ is known, $H(k\omega_0), k \in \mathcal{K}$ can be calculated in advance. Hence, to compute $S(k\omega_0), k \in \mathcal{K}$ and then estimate FRI parameters, $F(k\omega_0), k \in \mathcal{K}$ has to be determined. Next, we discuss a lowpass filter (LPF) based sampling framework to determine these Fourier samples.

\subsection{LPF-Based Sub-Nyquist Sampling}
In this section, we discuss a LPF-based sampling mechanism for FRI signals. Let $g(t)$ denotes an ideal lowpass filter with cutoff frequency $\omega_c$ rad/sec. In the frequency-domain we have that $G(\omega) = 1$ for $\omega \in [-\omega_c, \omega_c]$ and zero for the rest of the frequencies. Let $y(t)$ denotes response of the LPF to the input $f(t)$, that is, $y(t) = (f*g)(t)$, where $*$ denotes linear convolution operation. Consider an ADC with dynamic range $[-\lambda, \lambda]$ and sampling rate $\omega_s = \frac{2\pi}{T_s}$ rad/sec. By assuming that  $\|y(t)\|_{\infty}\leq \lambda$, uniform samples at the output of ADC are given as $y(nT_s), n \in \mathbb{Z}$. Then uniform measurements of discrete-time Fourier transform (DTFT) of the samples are given as
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) = \sum_{n \in \mathbb{Z}}y(nT_s)\,e^{\mathrm{j} k\omega_0 n T_s}, \quad k \in \mathcal{K}.
	\label{eq:y_dtft}
\end{align}
By using relationship between DTFT of samples $y(nT_s)$ and CTFT of $y(t)$ we have
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) &= \frac{1}{T_s}\sum_{m \in \mathbb{Z}} Y(k\omega_0 + m \omega_s), \nonumber \\
	&= \frac{1}{T_s}\sum_{m \in \mathbb{Z}} F(k\omega_0 + m \omega_s) \,G(k\omega_0 + m \omega_s),
		\label{eq:y_dtft2}
\end{align}
where we used the fact that $Y(\omega) = F(\omega)\,G(\omega)$. Next, consider the following conditions on the sampling rate and cutoff frequency of the filter
\begin{align}
	\omega_s \geq 2\omega_c, \quad \text{and} \quad \omega_c \geq K \omega_0,
	\label{eq:sampling_rate}
\end{align}
where $K \geq L$. Then by choosing $\mathcal{K} = \{-K, \cdots, K\}$, \eqref{eq:y_dtft2} can be written as
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) = F(k\omega_0), \quad k \in \mathcal{K},
	\label{eq:y_dtft3}
\end{align}
where we used the fact that $G(k\omega_0) = 1$ in these settings. The relationship \eqref{eq:y_dtft3} shows that the desired Fourier samples of $f(t)$ are determined from the samples of LPF by assuming that the conditions in \eqref{eq:y_dtft2} are satisfied. Hence, FRI parameters can be determined from the samples of the lowpass filter.

The bandwidth of the pulse $h(t)$ and hence that of the FRI signal $f(t)$ could be very large. But the sampling rate $\omega_s$ is independent of the pulse and could be much smaller than its bandwidth which shows the FRI signal could be reconstructed from sub-Nyquist samples.

The sub-Nyquist sampling framework discussed assumes that $\|y(t)\|_{\infty}\leq \lambda$, in other words, the framework assumes that the dynamic range of the ADC is greater than that of the signal to be sampled. However, this condition may not be always true. Specifically, the amplitude range of the filtered signal $y(t)$ could be larger than ADC's dynamic range. In such scenario, a direct sampling would lead to clipping of samples which is undesirable. To avoid clipping, a modulo operator is employed prior to sampling as discussed next.

\begin{figure*}
	\centering
	\includegraphics[width=6.5 in]{Figs/FRI_US}
	\caption{A schematic of modulo-sampling and reconstruction of FRI signals.}
	\label{fig:fri_framework}
\end{figure*}

\subsection{Modulo-Folding}
To avoid clipping, a modulo folding operator $\mathcal{M}_\lambda(\cdot)$ is used after LPF and before the ADC. The operator folds $y(t)$ to stay within ADC's dynamic range $[-\lambda, \lambda]$. The output of the modulo operator in response to input $y(t)$ is given as\begin{equation}
 y_\lambda(t) =	\mathcal{M}_{\lambda}(y(t)) = (y(t)+\lambda)\,\, \text{mod}\,\, 2\lambda -\lambda.
	\label{eq:mod_opp}
\end{equation}
The folded signal is then sampled by the ADC to have measurements $y_\lambda(nT_s)$. Since modulo folding is a nonlinear operation, one can not directly apply DTFT on the samples to compute Fourier measurements of the FRI signal for its reconstruction. Hence, the true or unfolded samples $y(nT_s)$ are estimated from the folded ones $y_\lambda(nT_s)$ by applying an unfolding algorithm. There exist several unfolding methods for badnlimited signals such as $y(t)$ \cite{uls_tsp, uls_romonov,eyar_moduloicassp}. The sampling rates for unfolding varies for different algorithms and generally, is larger than the minimum sampling rate required for FRI signal recovery (cf. \eqref{eq:sampling_rate}). Hence, the overall system operates on a higher sampling rate than that in without modulo case. However, if the overall sampling rate is much lower than the bandwidth of the FRI signal then the system operates at sub-Nyquist rate. We show that this is indeed true when we apply our unfolding algorithm proposed in \cite{eyar_moduloicassp}.

An end-to-end modulo sampling framework for FRI signal sampling and reconstruction is shown in Fig.~\ref{fig:fri_framework}. The sampler or ADC together with the modulo block is termed as modulo-ADC. Modulo-ADC's are able to sample signals beyond their dynamic range without clipping and hence they are termed as high-dynamic range ADCs. Alternatively, an ADC with much lower dynamic range can be used to sample signals with larger amplitudes. Sub-Nyquist sampling and low-dynamic range requirements significantly reduces the power consumption and cost of the ADC.

The modulo folding block is key component of the high-dynamic range ADC and we discuss it hardware implementation in the next section.

\begin{figure}
	\centering
	\includegraphics[width= 3 in]{Figs/folding}
	\caption{Folding principle}
	\label{Fig:folding}
\end{figure}
\section{Modulo Hardware Prototype}
In this section, we discuss our modulo hardware prototype. First, we explain the working principle of the modulo block and explain how its design and then discuss the hardware realization.
\subsection{Working Principle of Modulo Block}
Principle of computing $y_\lambda(t)$ from $y(t)$ is shown by block-diagram in Fig.~\ref{Fig:folding}. The system comprises of an adder, a direct-current voltage generator (DC-VG), and two comparators $C_1$ and $C_2$. To understand the working let us first assume that for some time instant $t_1$, we have that $|y(t)|<\lambda$ for $t<t_1$. Hence $y_\lambda(t) = y(t)$ and $z(t) = 0$ for $t<t_1$. At $t=t_1$, let $|f(t)|$ crosses $\lambda$. If $f(t_1)>0$, then the comparator $C_1$ triggers a positive spike or else, $C_2$ triggers a negative spike. The DC-VG is designed such that for every positive spike input it reduces its output signal level by $-2\lambda$, whereas, for negative spike it increases its output voltage by $2\lambda$. Hence, in the current example, DC-VG generates signal $z(t) = \text{sgn}(y_\lambda(t_1)) 2\lambda u(t-t_1)$ where $u(t)$ is unit-step function.
In this way by adding or subtracting constant DC signals from $f(t)$ whenever it crosses dynamic range $[-\lambda, \lambda]$, the amplitude levels of $f_\lambda(t)$ are kept within ADC's dynamic range.

\begin{figure*}
	\centering
	\includegraphics[width= 5.5 in]{Figs/mod_hw.jpg}
	\caption{Hardware Board}
	\label{Fig:hw_board}
\end{figure*}

\begin{figure}
    \centering
    \includegraphics[width=0.48\textwidth]{IEEE_TAES_v1/Figs/UDR block_diag v3.png}
    \caption{UDR block diagram.}
    \label{fig:UDRscheme}
\end{figure}

\begin{figure}
    \centering
    \includegraphics[width=0.48\textwidth]{IEEE_TAES_v1/Figs/UDR VER3 Comparator Vref.png}
    \caption{UDR Comparator.}
    \label{fig:UDRComparator}
\end{figure}

\begin{figure}
    \centering
    \includegraphics[width=0.48\textwidth]{IEEE_TAES_v1/Figs/UDR VER3 Analog Multiplier.png}
    \caption{UDR Analog Multiplier.}
    \label{fig:UDRAnalog Multiplier}
\end{figure}

\begin{figure}
    \centering
    \includegraphics[width=0.48\textwidth]{IEEE_TAES_v1/Figs/UDR VER3 Analog MUX.png}
    \caption{UDR Analog MUX.}
    \label{fig:UDRAnalogMUX}
\end{figure}

\begin{figure}
    \centering
    \includegraphics[width=0.48\textwidth]{IEEE_TAES_v1/Figs/UDR VER3 Buffer Vmod Out.png}
    \caption{UDR Buffer Vmod Out.}
    \label{fig:UDRBufferVmodOut}
\end{figure}

\begin{figure}
    \centering
    \includegraphics[width=0.48\textwidth]{IEEE_TAES_v1/Figs/UDR VER3 Comparator Vref.png}
    \caption{UDR Comparator Vref.}
    \label{fig:UDRComparatorVref}
\end{figure}

\begin{figure}
    \centering
    \includegraphics[width=0.48\textwidth]{IEEE_TAES_v1/Figs/UDR VER3 DAC 3 Bits.png}
    \caption{UDR DAC 3 Bits.}
    \label{fig:UDRDAC3Bits}
\end{figure}

\begin{figure}
    \centering
    \includegraphics[width=0.48\textwidth]{IEEE_TAES_v1/Figs/UDR VER3 Subtractor .png}
    \caption{UDR Subtractor.}
    \label{fig:UDRSubtractor}
\end{figure}

\begin{figure}
    \centering
    \includegraphics[width=0.48\textwidth]{IEEE_TAES_v1/Figs/UDR VER3 up down counter block.png}
    \caption{UDR up down counter.}
    \label{fig:UDRupdowncounter}
\end{figure}

\section{The Proposed HW prototype}
Give a detailed description of the HW starting from a block diagram. What makes it wideband? Details of each component?\\
Add details of GUI\\
Show sinewave plots at different frequencies

{\color{blue}
\section{Hardware Prototype Specifications}
\label{sec:hw}
We have implemented a hardware  system based on our proposed method.}

\begin{table}[h!]
\centering
\begin{tabular}{||c c c||}
 \hline
 Device & Reference & Manufacturer \\ [0.5ex]
 \hline\hline
 Signal Generator & & \\
 Signal Generator & & Arduino\\
 && \\
 Comparator & & \\
 Comparator & & Mini-Circuits \\
 && \\
 Subtractor & & \\
 Subtractor & & Mini-Circuits \\
 && \\
 UP/DOWN Counter & & \\
 UP/DOWN Counter & & Mini-Circuits \\
 && \\
 DAC 3bits & & \\
 DAC 3bits & & Mini-Circuits \\
 && \\
 Analog Multiplier & & \\
 Analog Multiplier & & Mini-Circuits \\
 && \\ [1ex]
 \hline
\end{tabular}
\caption{Device list.}
\label{table:1}
\end{table}

{\color{blue}\subsection{Signal generator}}

{\color{blue}\subsection{Comparator}}
{\color{blue}\subsection{Subtractor}}
{\color{blue}\subsection{UP/DOWN Counter}}
{\color{blue}\subsection{DAC 3bits}}
{\color{blue}\subsection{Analog Multiplier}}

{\color{blue}\subsection{UDR performance}}
Show sinewave plots at different frequencies
\begin{figure}
    \centering
    \includegraphics[width=0.48\textwidth]{IEEE_TAES_v1/Figs/1KHz.png}
    \caption{UDR 1KHz.}
    \label{fig:UDR1KHz}
\end{figure}

\newpage
~\newpage
\section{Results}
\subsection{Simulated results}
In this section, we present simulated results of several methods for recovering a bandlimited signal from the modulo samples.
Specifically, we compare the proposed algorithm with the \emph{higher-order differences} (HOD) approach \cite{unlimited_sampling17, uls_tsp} and \emph{Chebyshev polynomial filter}-based (CPF) method \cite{uls_romonov}.
We handle the noisy setting where we compare the proposed and existing approaches for reconstructing signals from modulo samples.
We exhibit the robustness to noise of the $B^2R^2$ algorithm for different noise level and the over-sampling factor.
We consider reconstruction problem from the next noisy samples
        \begin{align}
            \tilde{f}_{\lambda}(n T_s) = {f}_{\lambda}(n T_s) + v(n T_s) = \mathcal{M}_{\lambda}f(n T_s) + v(n T_s),
        \label{eq: noisy_samples}
        \end{align}
where $v(n T_s)$ specifies the noise.
In the experiments the modulo parameter $\lambda$ is fixed to $1.25$. We normalize the bandlimited signals to have maximum amplitude of $10$.
The SNR is calculated as $\text{SNR} = 20 \log\left(\frac{||f_{\lambda}(n T_s)||}{||v(n T_s)||}\right)$. The reconstruction accuracy of different methods is compared in terms of normalized mean-squared error (MSE) as $ \frac{\sum |f(nT_s) - \hat{f}(n Ts)|^2}{\sum |f(nT_s)|^2}$, where $\hat{f}(n T_s)$ signifies the estimate of $f(n T_s)$.
For each noise level and over-sampling factor, we examine 100 independent noise realizations and we calculate the average MSE for them.

\subsubsection{Quantization noise}
 In these experiments, we consider an uniform quantizer after the sampling. We compare the algorithms for different number of bits and OFs. Fig. ~\ref{Fig:quantization} shows MSEs of the different methods for OF $ = 3$ and $6$.

\subsubsection{Unbounded noise}
    For the unbounded noise we assume that the noise measurements $v(nT_s)$ are independent and identically distributed Gaussian random variables with zero mean. The variance is set to achieve a desired SNR. We compare the methods for different values of SNR and OFs. Fig.~\ref{Fig:unbounded} shows MSE of the different algorithms for OF $= 3$ and $6$.

\begin{figure*}
	\centering
	\includegraphics[width= 3 in]{IEEE_TAES_v1/Figs/quantization.png}
	\caption{Quantization noise}
	\label{Fig:quantization}
\end{figure*}

\begin{figure*}
	\centering
	\includegraphics[width= 3 in]{IEEE_TAES_v1/Figs/Gaussian.png}
	\caption{Unbounded noise}
	\label{Fig:unbounded}
\end{figure*}

\subsection{Hardware Results}
{\color{blue}{
Hardware results and data to be generated:
\begin{enumerate}
    \item Sinusoidal frequencies and their modulo responses with different frequencies. We should capture the response on a CRO and please also take a video. Goal: To show the frequency response. \\
    Five frequencies, $f_1. f_2, f_3, f_4, f_5$. For frequencies less than $f_3$, everything should work well. From $f_3$ on wards the distortion should appear. Amplitude of the signal or sinusoidal is denoted by $A$ and dynamic range is $\lambda$. We need to fix $\frac{A}{\lambda} = 2$ (one fold).
    \item Sinusoidal frequencies and their modulo responses with different amplitudes. Goal: how much folding can be achieved.\\
    Fix the frequency to $f_1$. Show the response for different values of $\frac{A}{\lambda}$
    \item We need design an experiment to show the delay in the feedback loop for different frequencies. Goal: To show that for small frequencies the delays do not have any effect.
    \item We to generate output of a lowpass filter with cutoff frequency $f_c$ Hz, send it to the modulo, sample at higher rates. Give the samples to Eyar for reconstruction. We need to generate a set of such examples. May be 6. Then we can show a few of them. Note: Capture both the lowpass signal and modulo response for a better comparison. Goal: to show recovery of bandlimited signals.
    \item We should generate two pulses with different time-delays. The bandwidth of each pulse should be 12-15 times the cutoff of lowpass filter. Then lowpass filter, modulo it, and measure the samples. We need to capture each of the pulses. Goal: To recover FRI signals.

\end{enumerate}
}}

\section{Conclusions}

\newpage~\newpage

\section*{APPENDIX}

Appendixes, if needed, appear before the acknowledgment.

\section*{ACKNOWLEDGMENT}
The preferred spelling of the word ``acknowledgment'' in American English is without an ``e'' after the ``g.'' Use the singular heading even if you have many acknowledgments. Avoid expressions such as ``One of us (S.B.A.) would like to thank ... .'' Instead, write ``F. A. Author thanks ... .'' In most cases, sponsor and financial support acknowledgments are placed in the unnumbered footnote on the first page, not here.

\bibliographystyle{IEEEtaes}

\section{INTRODUCTION}
Sampling plays a key role in efficiently processing real-world analog signals on digital signal processors. Analog to digital converters (ADCs) are used to implement sampling in the hardware. A key parameter of the ADC is its sampling rate. ADCs with high sampling rates are power consuming and expensive which make them unsuitable for portable devices such as hand-held ultrasound device. Hence, it is desirable to reduce the sampling rate. Following the Shannon-Nyquist sampling theorem \cite{shannon, nyquist}, it is well known that the sampling rate of bandlimited signals are dictated by their highest frequency. Hence, in wideband signal applications one can not sample below the Nquist rate by considering the bandlimited signal model.

Finite-rate-of-innovation (FRI) model is another signal model which is ubiquitous in several time of flight applications \cite{bajwa_radar, bar_radar,filho201seismic,rip,carter_sonar,eldar_sos,eldar_beamforming}. In these applications, the signal of interest consists of a linear combination of delayed copies of a known pulse. Thus, the desired information lies in the amplitudes and time delays of the pulse which amounts to few degrees of freedom and aids sub-Nyquist sampling \cite{eldar_2015sampling}. Most prior works in the context of FRI sampling are focused on reducing the sampling rate of the ADC by using the signal structure and consequently reducing the power consumption and cost of the ADCs \cite{vetterli, eldar_sos, fri_strang, blu_moms, mulleti_kernal}.

Dynamic range of an ADC too plays a crucial role in sampling an analog signal. In general, ADC's dynamic range should be larger than that of the signal's, otherwise the signal is clipped. There exist a few approaches to recover the true samples from clipped ones for bandlimited signals \cite{marks_clipping2, marks_clipping1}. These approaches relies on correlation among the samples when they are measured at very high-rate compared to the Nyquist rate. Requirement of high-sampling rate is a drawback of these approaches. In addition, theoretical guarantees are missing and it is not clear on how many clipped samples can be recovered.

There are three popular analog preprocssing approaches, namely automatic gain control (AGC) \cite{perez2011automatic,mercy1981review}, companding \cite{landau_compander,landau_distorted_bl}, and modulo folding \cite{uls_tsp,uls_romonov,uls_sparse,bhandari2021unlimited,eyar_moduloicassp}, that can be used prior to sampling to avoid clipping. In AGC, a chain of amplifiers is used with a feedback loop such that a suitable output level is maintained at the output \cite{perez2011automatic,mercy1981review}. An AGC system uses a closed loop feedback mechanism to maintain a constant signal level at its output for a varying input signal levels \cite{perez2011automatic,mercy1981review}. The closed loop feedback consists of a chain of amplifiers and maintaining its stability is a challenging task. Companding is an alternative approach to limit the dynamic range of the input signals. In this approach, smaller amplitudes of the signals have larger gain compared to the larger ones. Beurling presented theoretical guarantees and proved that knowledge of the companded signal over the input signal's bandwidth is sufficient to uniquely identify the signal provided \cite{landau_compander}. Landau et al. \cite{landau_distorted_bl} proposed an iterative algorithm to recover a bandlimited signal from its companded signal. The algorithm converges if the compander is differentiable over the dynamic range of the input signal which limits its practical application.

The third approach is to use modulo folding prior to sampling which fold the input signal to lie within the dynamic range of the ADC \cite{uls_tsp,uls_romonov,uls_sparse,bhandari2021unlimited,eyar_moduloicassp}. The folded signal is then sampled by using a conventional ADC. Theoretical guarantees for recovering bandlimited signals from folded samples are presented in \cite{uls_tsp,uls_identifiability}. The results states that the bandlimited signals can be uniquely recovered from folded samples provided that they are sampled above the Nyquist rate. Several algorithms for \emph{unfolding} or recovering the true samples of bandlimited signals from modulo or folded samples are presented in \cite{uls_tsp,uls_romonov, eyar_moduloicassp}. These unfolding algorithms can be compared in terms of sampling rate, amount of unfolding they can accommodate, and noise robustness. It is shown that the method proposed in \cite{eyar_moduloicassp} has lowest reconstruction error for a given sampling rate, noise level, and signal's amplitude level compared to the algorithms presented in \cite{uls_tsp,uls_romonov}. The algorithm proposed in \cite{uls_tsp} requires almost 17-times higher sapling rate than the Nyquist rate but it is independent of the dynamic range of the ADC. Whereas, the approaches in \cite{uls_romonov, eyar_moduloicassp} requires the knowledge of ADC's dynamic range. Modulo sampling is also extended to different problems and signal models such as periodic bandlimited signals \cite{bhandari2021unlimited}, wavelets \cite{uls_wavelet}, mixture of sinusoids \cite{uls_sinmix}, finite-rate-of-innovation signals \cite{uls_fri}, multi-dimensional signals \cite{uls_md}, sparse vector recovery \cite{uls_gamp, uls_sparsevec}, direction of arrival estimation problem \cite{uls_doa}, computed tomography \cite{uls_radon}, and graph signals \cite{uls_graph}.

While theoretical guarantees and algorithms of any new sampling approach are always well researched but the question on whether they work in practice is always difficult to answer. For modulo sampling, there exists a few hardware prototypes. For example, high-dynamic-range ADCs, also known as \emph{self-reset} ADCs, are discussed in the context of imaging \cite{sradc_park, sradc_sasagwa, sradc_yuan, krishna2019unlimited}. These hardware architectures measures additional information such as the amount of folding for each sample, or, the sign of the folding together with the folded samples. The additional information might enable simpler recovery but at the expense of complex circuitry. Importantly, additional bits are required during the quantization process to store or transmit the side information.

Krishna et al. presented a hardware prototype which encode the side-information by using two bits \cite{krishna2019unlimited}. The architecture is designed to record sign of the slope of the signal at each sampling instant when the sample lies outside ADC's dynamic range. In a conventional ADC, a sample and hold (S/H) circuit is used to hold the sampled value for a prescribed period of time during which quantization is performed on the sample. To realize the modulo sampling, a folding circuit is used after S/H \cite{krishna2019unlimited}. Hence, the S/H circuit has to hold the sampled value for folding and quantization, which results in a larger folding time compared to a conventional ADC. A large holding time results in slower ADC and hence it may not be useful for wideband application.

The proposed modulo-ADC is able to sample signals beyond its dynamic range while keeping the power dissipation and area requirements lower compared to a conventional ADC \cite{krishna2019unlimited}. A major drawback of this modulo-ADC's architecture is that the modulo operation is performed between the sample and hold (S/H), and quantization blocks of the ADC. Specifically, modulo operation is performed on the hold values of S/H circuit and then the folded sample is quantized. Hence, compared to a conventional ADC, the hold time is relatively high which makes the architecture slower.

\newpage
In introduction, we discuss the following:

1st-paragraph: Standard sampling and sub-Nyquist; importance of low sampling rates; FRI signal model and application to radar\\

2nd-paragraph: Introduce the dynamic range issue and discuss the existing approaches to address it: AGC, commanding, and modulo. Why modulo is important.\\

3rd paragraph: Discuss about modulo method, recovery algorithms and their issues with high-sampling rates and instability in noise. Discuss about our proposed algorithm (Eyar's ICASSP-22 paper)\\

4th paragraph: Can we implement these in HW? Discuss about hardware prototypes and applications. Shortcomings: No practical applications, low operating frequencies, more?\\

5th paragraph: In this paper, we present a HW prototype combined with recently proposed algorithm to address these issues.\\

 6th Paragraph: The paper is organized as follows; Notations \\

\section{Signal Model and System Description}
In this section, we first introduce FRI signal model and then discuss its sampling and reconstruction framework with modulo ADC.
\subsection{FRI Signal Model}
Consider an FRI signal consisting of stream of $L$ pulses:
\begin{align}
	f(t) = \sum_{\ell=1}^L a_\ell h(t-t_\ell),
	\label{eq:fri1}
\end{align}
where the pulse $h(t)$ a real-valued known pulse. We assume that $a_\ell$s are real-valued and $t_\ell \in (0, T_d] \subset \mathbb{R}$ for a known $T_d$.

The FRI signal model in \eqref{eq:fri1} is encountered in several scientific applications such as radar imaging \cite{bar_radar, bajwa_radar, sunil}, ultrasound imaging \cite{eldar_sos,eldar_beamforming,mulleti_icip}, light detection and ranging (LIDAR) \cite{castorena_lidar}, time-domain optical-coherence tomography (TDOCT) \cite{blu_oct}, and other time-of-flight imaging systems. In these applications,  $h(t)$ is the transmitted pulse and $\{a_\ell \,h(t-t_\ell)\}_{\ell=1}^{L}$ constitute the reflections from $L$ point targets. The amplitudes $a_\ell$s depend on the sizes of the targets and the delays $t_\ell$s are proportional to the distances of the targets from the transmitter. Here $T_d$ denotes maximum time delay of the targets. The signal $f(t)$ is specified by $\{a_\ell, t_\ell\}_{\ell=1}^L$ and can be reconstructed from its sub-Nyquist measurements acquired using an appropriate sampling kernel \cite{vetterli,eldar_sos,fri_strang, mulleti_kernal}. The reconstruction is generally carried out in frequency domain as discussed next.

\subsection{Fourier-Domain Reconstruction}
Consider uniform samples of continuous-time Fourier transform of $f(t)$ given as
\begin{align}
	F(k \omega_0) = \int f(t) e^{-\mathrm{j} k\omega_0 t} \mathrm{d}t = H(k \omega_0) \sum_{\ell = 1}^L a_\ell \, e^{-\mathrm{j} k\omega_0 t_\ell},
	\label{eq:F}
\end{align}
for $k \in \mathcal{K}$ where $H(\omega)$ is the Fourier transform of $h(t)$ and $\mathcal{K}$ is a set integers. In \eqref{eq:F}, $\omega_0>0$ denotes sampling interval in the frequency domain. Next, consider the following samples
\begin{align}
	S(k\omega_0) = \frac{F(k\omega_0)}{H(k\omega_0)} =  \sum_{\ell = 1}^L a_\ell \, e^{-\mathrm{j}k\omega_0 t_\ell},
	\label{eq:Skomega}
\end{align}
where we assume that $H(k \omega_0) \neq 0$ for $k \in \mathcal{K}$. In practice, the pulse $h(t)$ has small time support and hence, large bandwidth. Hence, for a finite set $\mathcal{K}$ it is possible to choose a set of frequencies $\{k \omega_0\}_{ k \in \mathcal{K}}$ such that $H(k \omega_0) \neq 0$ for $k \in \mathcal{K}$. It can be shown that $2L$ consecutive samples of $S(k\omega_0)$ are sufficient to uniquely identify $\{a_\ell, t_\ell\}_{\ell=1}^L$ if $\omega_0 = \frac{2\pi}{T_d}$ \cite{eldar_2015sampling}. In practice, high-resolution spectral estimation methods, such as the annihilating filter (AF) or Prony's method and its variants \cite{prony, plonka}, multiple signal classification \cite{schmidt_music, barabell_rmusic, bdrao_rmusic}, matrix-pencil method \cite{sarkar_mp}, estimation of signal parameter via rotational invariance technique (ESPRIT) \cite{paulraj_esprit}, etc. have been deployed for FRI parameter estimation.

Since $h(t)$ is known, $H(k\omega_0), k \in \mathcal{K}$ can be calculated in advance. Hence, to compute $S(k\omega_0), k \in \mathcal{K}$ and then estimate FRI parameters, $F(k\omega_0), k \in \mathcal{K}$ has to be determined. Next, we discuss a lowpass filter (LPF) based sampling framework to determine these Fourier samples.

\subsection{LPF-Based Sub-Nyquist Sampling}
In this section, we discuss a LPF-based sampling mechanism for FRI signals. Let $g(t)$ denotes an ideal lowpass filter with cutoff frequency $\omega_c$ rad/sec. In the frequency-domain we have that $G(\omega) = 1$ for $\omega \in [-\omega_c, \omega_c]$ and zero for the rest of the frequencies. Let $y(t)$ denotes response of the LPF to the input $f(t)$, that is, $y(t) = (f*g)(t)$, where $*$ denotes linear convolution operation. Consider an ADC with dynamic range $[-\lambda, \lambda]$ and sampling rate $\omega_s = \frac{2\pi}{T_s}$ rad/sec. By assuming that  $\|y(t)\|_{\infty}\leq \lambda$, uniform samples at the output of ADC are given as $y(nT_s), n \in \mathbb{Z}$. Then uniform measurements of discrete-time Fourier transform (DTFT) of the samples are given as
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) = \sum_{n \in \mathbb{Z}}y(nT_s)\,e^{\mathrm{j} k\omega_0 n T_s}, \quad k \in \mathcal{K}.
	\label{eq:y_dtft}
\end{align}
By using relationship between DTFT of samples $y(nT_s)$ and CTFT of $y(t)$ we have
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) &= \frac{1}{T_s}\sum_{m \in \mathbb{Z}} Y(k\omega_0 + m \omega_s), \nonumber \\
	&= \frac{1}{T_s}\sum_{m \in \mathbb{Z}} F(k\omega_0 + m \omega_s) \,G(k\omega_0 + m \omega_s),
		\label{eq:y_dtft2}
\end{align}
where we used the fact that $Y(\omega) = F(\omega)\,G(\omega)$. Next, consider the following conditions on the sampling rate and cutoff frequency of the filter
\begin{align}
	\omega_s \geq 2\omega_c, \quad \text{and} \quad \omega_c \geq K \omega_0,
	\label{eq:sampling_rate}
\end{align}
where $K \geq L$. Then by choosing $\mathcal{K} = \{-K, \cdots, K\}$, \eqref{eq:y_dtft2} can be written as
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) = F(k\omega_0), \quad k \in \mathcal{K},
	\label{eq:y_dtft3}
\end{align}
where we used the fact that $G(k\omega_0) = 1$ in these settings. The relationship \eqref{eq:y_dtft3} shows that the desired Fourier samples of $f(t)$ are determined from the samples of LPF by assuming that the conditions in \eqref{eq:y_dtft2} are satisfied. Hence, FRI parameters can be determined from the samples of the lowpass filter.

The bandwidth of the pulse $h(t)$ and hence that of the FRI signal $f(t)$ could be very large. But the sampling rate $\omega_s$ is independent of the pulse and could be much smaller than its bandwidth which shows the FRI signal could be reconstructed from sub-Nyquist samples.

The sub-Nyquist sampling framework discussed assumes that $\|y(t)\|_{\infty}\leq \lambda$, in other words, the framework assumes that the dynamic range of the ADC is greater than that of the signal to be sampled. However, this condition may not be always true. Specifically, the amplitude range of the filtered signal $y(t)$ could be larger than ADC's dynamic range. In such scenario, a direct sampling would lead to clipping of samples which is undesirable. To avoid clipping, a modulo operator is employed prior to sampling as discussed next.

\begin{figure*}
	\centering
	\includegraphics[width=6.5 in]{Figs/FRI_US}
	\caption{A schematic of modulo-sampling and reconstruction of FRI signals.}
	\label{fig:fri_framework}
\end{figure*}

\subsection{Modulo-Folding}
To avoid clipping, a modulo folding operator $\mathcal{M}_\lambda(\cdot)$ is used after LPF and before the ADC. The operator folds $y(t)$ to stay within ADC's dynamic range $[-\lambda, \lambda]$. The output of the modulo operator in response to input $y(t)$ is given as\begin{equation}
 y_\lambda(t) =	\mathcal{M}_{\lambda}(y(t)) = (y(t)+\lambda)\,\, \text{mod}\,\, 2\lambda -\lambda.
	\label{eq:mod_opp}
\end{equation}
The folded signal is then sampled by the ADC to have measurements $y_\lambda(nT_s)$. Since modulo folding is a nonlinear operation, one can not directly apply DTFT on the samples to compute Fourier measurements of the FRI signal for its reconstruction. Hence, the true or unfolded samples $y(nT_s)$ are estimated from the folded ones $y_\lambda(nT_s)$ by applying an unfolding algorithm. There exist several unfolding methods for badnlimited signals such as $y(t)$ \cite{uls_tsp, uls_romonov,eyar_moduloicassp}. The sampling rates for unfolding varies for different algorithms and generally, is larger than the minimum sampling rate required for FRI signal recovery (cf. \eqref{eq:sampling_rate}). Hence, the overall system operates on a higher sampling rate than that in without modulo case. However, if the overall sampling rate is much lower than the bandwidth of the FRI signal then the system operates at sub-Nyquist rate. We show that this is indeed true when we apply our unfolding algorithm proposed in \cite{eyar_moduloicassp}.

An end-to-end modulo sampling framework for FRI signal sampling and reconstruction is shown in Fig.~\ref{fig:fri_framework}. The sampler or ADC together with the modulo block is termed as modulo-ADC. Modulo-ADC's are able to sample signals beyond their dynamic range without clipping and hence they are termed as high-dynamic range ADCs. Alternatively, an ADC with much lower dynamic range can be used to sample signals with larger amplitudes. Sub-Nyquist sampling and low-dynamic range requirements significantly reduces the power consumption and cost of the ADC.

The modulo folding block is key component of the high-dynamic range ADC and we discuss it hardware implementation in the next section.

\begin{figure}
	\centering
	\includegraphics[width= 3 in]{Figs/folding}
	\caption{Folding principle}
	\label{Fig:folding}
\end{figure}
\section{Modulo Hardware Prototype}
In this section, we discuss our modulo hardware prototype. First, we explain the working principle of the modulo block and explain how its design and then discuss the hardware realization.
\subsection{Working Principle of Modulo Block}
Principle of computing $y_\lambda(t)$ from $y(t)$ is shown by block-diagram in Fig.~\ref{Fig:folding}. The system comprises of an adder, a direct-current voltage generator (DC-VG), and two comparators $C_1$ and $C_2$. To understand the working let us first assume that for some time instant $t_1$, we have that $|y(t)|<\lambda$ for $t<t_1$. Hence $y_\lambda(t) = y(t)$ and $z(t) = 0$ for $t<t_1$. At $t=t_1$, let $|f(t)|$ crosses $\lambda$. If $f(t_1)>0$, then the comparator $C_1$ triggers a positive spike or else, $C_2$ triggers a negative spike. The DC-VG is designed such that for every positive spike input it reduces its output signal level by $-2\lambda$, whereas, for negative spike it increases its output voltage by $2\lambda$. Hence, in the current example, DC-VG generates signal $z(t) = \text{sgn}(y_\lambda(t_1)) 2\lambda u(t-t_1)$ where $u(t)$ is unit-step function.
In this way by adding or subtracting constant DC signals from $f(t)$ whenever it crosses dynamic range $[-\lambda, \lambda]$, the amplitude levels of $f_\lambda(t)$ are kept within ADC's dynamic range.

\begin{figure}
	\centering
    \includegraphics[width=0.48\textwidth]{Figs/mod_hw.jpg}
	\caption{Hardware Board}
	\label{Fig:hw_board}
\end{figure}

\begin{figure}
    \centering
    \includegraphics[width=0.48\textwidth]{IEEE_TAES_v1/Figs/UDR block_diag v3.png}
    \caption{UDR block diagram.}
    \label{fig:UDRscheme}
\end{figure}

\begin{table}[h!]
\centering
\begin{tabular}{||c c c||}
 \hline
 Device & Reference & Manufacturer \\ [0.5ex]
 \hline\hline
 Signal Generator & & \\
 Signal Generator & & Arduino\\
 DAC & msp4725 & Microchip \\
 && \\
 Comparator & & \\
 Comparator & TLV3201 & Texas Instruments \\
 && \\
 UP/DOWN Counter & & \\
 UP/DOWN Counter & & Arduino \\
 && \\
 DAC 3bits & & \\
 DAC 3bits & LT1364 & Analog Devices \\
 && \\
 Analog MUX & & \\
 Analog MUX & ADG1608 & Analog Devices \\
 && \\
 Analog Multiplier & & \\
 Analog Multiplier & AD835 & Analog Devices \\
 && \\
 subtractor & & \\
 Subtractor & LT1364 & Analog Devices \\
  && \\ [1ex]
\hline
\end{tabular}
\caption{Device list.}
\label{table:1}
\end{table}

{\color{red}
\section{Hardware Prototype Specifications}
\label{sec:hw}
We have implemented a hardware  system based on our proposed method. A Unlimited Dynamic Range ADC hardware prototype of the suggested design is demonstrated in Figure \ref{fig:UDRscheme} with the components as appears in Table [\ref{table:1}].
It can be seen from the Figure \ref{fig:UDRscheme}, that the hardware contains a signal generator, a comperator, up/down counter, a digital to analog converter, an analog multiplier and a subtractor blocks.

\begin{figure}
    \centering
    \includegraphics[width=0.48\textwidth]{IEEE_TAES_v1/Figs/Signal Generator.png}
    \caption{UDR Signal Generator.}
    \label{fig:UDRSignalGen}
\end{figure}

\subsection{Signal generator}
The Signal Generator block is responsible of generating a band limited signal as described in Figure [\ref{fig:UDR1KHz}]. In order to implement the signal we generated the desired signal digitally in Matlab and transfer it to the Arduino micro-controller which convert the digital signal to an analog signal via a DAC, the signal is then used as the input to the UDR board  as can be seen in Figure [\ref{fig:UDRSignalGen}].

\begin{figure}
    \centering
    \includegraphics[width=0.48\textwidth]{IEEE_TAES_v1/Figs/UDR VER3 Comparator Vref.png}
    \caption{UDR Comparator.}
    \label{fig:UDRComparator}
\end{figure}

\subsection{Comparator}
In the comperator block as described in Figure [\ref{fig:UDRComparator}] the signal (Sia) is being split into two comparators (a) and (b) and being compared to a predefined level crossing value of +$\lambda$ or –$\lambda$ respectively, this enables the circuit to extract the needed folding direction. The implementation of -+$\lambda$ values are set with adjustable regulator (c) and (d) and a voltage dividers which in our implementation is set to $\lambda$=1.25[V]. In case a level crossing was detected either above +$\lambda$ or below -$\lambda$ then the output of either comparator (a) (SiaP) or comparator (b) (SiaN) is set to a logical '1', which in turn serves as an input to the UP/DOWN Counter.

\begin{figure}
    \centering
    \includegraphics[width=0.48\textwidth]{IEEE_TAES_v1/Figs/UDR VER3 up down counter block.png}
    \caption{UDR up down counter.}
    \label{fig:UDRupdowncounter}
\end{figure}

\subsection{UP/DOWN Counter}
In the UP/DOWN Counter block as described in Figure [\ref{fig:UDRupdowncounter}] the SiaP and SiaN are used as a trigger to a micro controller which upon raising edge of either one of them, will update a counter which reflects the number of 2$\lambda$ which need to be added or substract from the input signal Sia. The output of the  UP/DOWN Counter block is implemented as 5 lines A,B,C for the counter absolute value and D & E for the sign of the counter according to table[ \ref{table:2}] the values of the first 3 lines are transferred into the 3bits DAC block and the additional sign (+-) lines are transferred into the multiplier block.

\begin{figure}
    \centering
    \includegraphics[width=0.48\textwidth]{IEEE_TAES_v1/Figs/UDR VER3 DAC 3 Bits.png}
    \caption{UDR DAC 3 Bits.}
    \label{fig:UDRDAC3Bits}
\end{figure}

\subsection{DAC 3bits}
The 3bits Digital to Analog Converter (DAC), as described in Figure [\ref{fig:UDRDAC3Bits}], is responsible of converting the output of the micro-controller taking as an input the 5 lines from the micro-controller and converts them to 3 analog signals chip-selects (CS) for the Analog MUX block.

\begin{figure}
    \centering
    \includegraphics[width=0.48\textwidth]{IEEE_TAES_v1/Figs/UDR VER3 Analog MUX.png}
    \caption{UDR Analog MUX.}
    \label{fig:UDRAnalogMUX}
\end{figure}

\subsection{Analog MUX}
The Analog MUX block, as described in Figure [\ref{fig:UDRAnalogMUX}], is responsible of converting the output of the 3 bits DAC to a positive DC voltage per Table [\ref{table:2}] in 4 steps of +2Vref (2.5V) each. the output DC will be used as an input to the analog multiplier block.

\begin{figure}
    \centering
    \includegraphics[width=0.48\textwidth]{IEEE_TAES_v1/Figs/UDR VER3 Analog Multiplier.png}
    \caption{UDR Analog Multiplier.}
    \label{fig:UDRAnalogMultiplier}
\end{figure}

\begin{table}[h!]
\centering
\begin{tabular}{||c c c c c c c||}
 \hline
 A & B & C & (+) & (-) & Counter & Substractor \\ [0.5ex]
 \hline\hline
 0 & 0 & 0 & 1 & 0 & 1 & 0V\\
 0 & 0 & 1 & 1 & 0 & 1 & 2.5V\\
 0 & 1 & 0 & 1 & 0 & 2 & 5V\\
 0 & 1 & 1 & 1 & 0 & 3 & 7.5V\\
 1 & 0 & 0 & 1 & 0 & 4 & 10v\\
 0 & 0 & 1 & 0 & 1 & -1 & -2.5V\\
 0 & 1 & 0 & 0 & 1 & -2 & -5V\\
 0 & 1 & 1 & 0 & 1 & -3 & -7.5V\\
 1 & 0 & 0 & 0 & 1 & -4 & -10v\\
\hline
\end{tabular}
\caption{Folding Operation.}
\label{table:2}
\end{table}

\subsection{Analog Multiplier}
The Analog multiplier block, as described in Figure [\ref{fig:UDRAnalogMultiplier}], is receiving the 2 signs signals from the UP/DOWN Counter block and the output of the analog mux block and performs a multiplication operation which multiply the Analog mux DC output by the sign of the UP/DOWN Counter block $W$=$X$x$Y$, the DC output will be used as the input for the substractor block per Table [\ref{table:2}.

\begin{figure}
    \centering
    \includegraphics[width=0.48\textwidth]{IEEE_TAES_v1/Figs/UDR VER3 Subtractor .png}
    \caption{UDR Subtractor.}
    \label{fig:UDRSubtractor}
\end{figure}

\subsection{Subtractor}
The substractor block, as described in Figure [\ref{fig:UDRSubtractor}], is receiving the outout of the multiplier block and substracting it from the input signal which in turn is feeding back to the comperator block in Figure [\ref{fig:UDRComparator}]. The modulo feedback loop ensures that the input signal for the comperator will always be between -+$\lambda$.
As long as the input signal is in the range of voltage levels between +Vref and -Vref, then Vmod Out = Sia, in that case comparator +-Vref output will be UP=0 and Down=0, thus the up/down counter output will be CBA=000, so DAC 3bits output will be Y= 0 these will result that the Analog multiplier output will be X*Y=0 too, which have no effect on the subtractor that calculate Sia-X*Y=Vmod , thus Sia=Vmod Out.
In case the input signal Sia level is crossing +Vref it will be detected by the comparator +-Vref then its output will be UP = 1 and Down =0, and since Sia is positive then the comparator +-signs output is SiaP=1 SiaN=0, the output of the UP/DOWN Counter will be CBA=001, thus Y=1, and since SiaP=1 the output of Analog MUX is X=+2Vref, so the output of Analog Multiplier is X*Y=+2Vref, which will effect the Subtractor result to be Sia-2Vref, so the Vmod will step down 2Vref from its current value.
In case the input signal Sia level is crossing -Vref it will be detected by the comparator +-Vref then its output will be UP = 0 and Down =1, and since Sia is negative then the comparator +-signs output is SiaP=0 SiaN=1, the output of the UP/DOWN Counter will be CBA=001, thus Y=1, and since SiaN=1 the output of Analog MUX is X=-2Vref, so the output of Analog Multiplier is X*Y=-2Vref, thus the Subtractor result will be Sia=Sia-(-2Vref), so the Vmod will step up 2Vref from its current value.

\begin{figure}
    \centering
    \includegraphics[width=0.48\textwidth]{IEEE_TAES_v1/Figs/UDR VER3 Buffer Vmod Out.png}
    \caption{UDR Buffer Vmod Out.}
    \label{fig:UDRBufferVmodOut}
\end{figure}

\subsection{ADC Output Buffer}
The ADC Output Buffer block, as described in Figure [\ref{fig:UDRBufferVmodOut}], is used to transfer the signal to an off the shelf ADC which in out case we used an oscilloscope in order to sample the folded signal and to convert it from Analog to digital. This signal is transfer to the matlab for a reconstruction procedure.

\section{UDR Circuit Challenges}
The main challenges in the UDR hardware implementation are
The Substractor block implementation and the counter management mechanism. In this paragraph we will explore the challenges and our way to overcome them.

\subsection{Substractor block in practice}

\subsection{counter management mechanism in practice}

}

{\color{blue}\subsection{UDR performance}}
Show sinewave plots at different frequencies

\begin{figure}
    \centering
    \includegraphics[width=0.48\textwidth]{IEEE_TAES_v1/Figs/1KHz.png}
    \caption{UDR 1KHz.}
    \label{fig:UDR1KHz}
\end{figure}

\newpage
~\newpage
\section{Results}
\subsection{Simulated results}
In this section, we present simulated results of several methods for recovering a bandlimited signal from the modulo samples.
Specifically, we compare the proposed algorithm with the \emph{higher-order differences} (HOD) approach \cite{unlimited_sampling17, uls_tsp} and \emph{Chebyshev polynomial filter}-based (CPF) method \cite{uls_romonov}.
We handle the noisy setting where we compare the proposed and existing approaches for reconstructing signals from modulo samples.
We exhibit the robustness to noise of the $B^2R^2$ algorithm for different noise level and the over-sampling factor.
We consider reconstruction problem from the next noisy samples
        \begin{align}
            \tilde{f}_{\lambda}(n T_s) = {f}_{\lambda}(n T_s) + v(n T_s) = \mathcal{M}_{\lambda}f(n T_s) + v(n T_s),
        \label{eq: noisy_samples}
        \end{align}
where $v(n T_s)$ specifies the noise.
In the experiments the modulo parameter $\lambda$ is fixed to $1.25$. We normalize the bandlimited signals to have maximum amplitude of $10$.
The SNR is calculated as $\text{SNR} = 20 \log\left(\frac{||f_{\lambda}(n T_s)||}{||v(n T_s)||}\right)$. The reconstruction accuracy of different methods is compared in terms of normalized mean-squared error (MSE) as $ \frac{\sum |f(nT_s) - \hat{f}(n Ts)|^2}{\sum |f(nT_s)|^2}$, where $\hat{f}(n T_s)$ signifies the estimate of $f(n T_s)$.
For each noise level and over-sampling factor, we examine 100 independent noise realizations and we calculate the average MSE for them.

\subsubsection{Quantization noise}
 In these experiments, we consider an uniform quantizer after the sampling. We compare the algorithms for different number of bits and OFs. Fig. ~\ref{Fig:quantization} shows MSEs of the different methods for OF $ = 3$ and $6$.

\subsubsection{Unbounded noise}
    For the unbounded noise we assume that the noise measurements $v(nT_s)$ are independent and identically distributed Gaussian random variables with zero mean. The variance is set to achieve a desired SNR. We compare the methods for different values of SNR and OFs. Fig.~\ref{Fig:unbounded} shows MSE of the different algorithms for OF $= 3$ and $6$.

\begin{figure*}
	\centering
	\includegraphics[width= 3 in]{IEEE_TAES_v1/Figs/quantization.png}
	\caption{Quantization noise}
	\label{Fig:quantization}
\end{figure*}

\begin{figure*}
	\centering
	\includegraphics[width= 3 in]{IEEE_TAES_v1/Figs/Gaussian.png}
	\caption{Unbounded noise}
	\label{Fig:unbounded}
\end{figure*}

\subsection{Hardware Results}
{\color{blue}{
Hardware results and data to be generated:
\begin{enumerate}
    \item Sinusoidal frequencies and their modulo responses with different frequencies. We should capture the response on a CRO and please also take a video. Goal: To show the frequency response. \\
    Five frequencies, $f_1. f_2, f_3, f_4, f_5$. For frequencies less than $f_3$, everything should work well. From $f_3$ on wards the distortion should appear. Amplitude of the signal or sinusoidal is denoted by $A$ and dynamic range is $\lambda$. We need to fix $\frac{A}{\lambda} = 2$ (one fold).
    \item Sinusoidal frequencies and their modulo responses with different amplitudes. Goal: how much folding can be achieved.\\
    Fix the frequency to $f_1$. Show the response for different values of $\frac{A}{\lambda}$
    \item We need design an experiment to show the delay in the feedback loop for different frequencies. Goal: To show that for small frequencies the delays do not have any effect.
    \item We to generate output of a lowpass filter with cutoff frequency $f_c$ Hz, send it to the modulo, sample at higher rates. Give the samples to Eyar for reconstruction. We need to generate a set of such examples. May be 6. Then we can show a few of them. Note: Capture both the lowpass signal and modulo response for a better comparison. Goal: to show recovery of bandlimited signals.
    \item We should generate two pulses with different time-delays. The bandwidth of each pulse should be 12-15 times the cutoff of lowpass filter. Then lowpass filter, modulo it, and measure the samples. We need to capture each of the pulses. Goal: To recover FRI signals.

\end{enumerate}
}}

\section{Conclusions}

\newpage~\newpage

\section*{APPENDIX}

Appendixes, if needed, appear before the acknowledgment.

\section*{ACKNOWLEDGMENT}
The preferred spelling of the word ``acknowledgment'' in American English is without an ``e'' after the ``g.'' Use the singular heading even if you have many acknowledgments. Avoid expressions such as ``One of us (S.B.A.) would like to thank ... .'' Instead, write ``F. A. Author thanks ... .'' In most cases, sponsor and financial support acknowledgments are placed in the unnumbered footnote on the first page, not here.

\bibliographystyle{IEEEtaes}

\section{INTRODUCTION}
Sampling plays a key role in efficiently processing real-world analog signals on digital signal processors. Analog to digital converters (ADCs) are used to implement sampling in the hardware. A key parameter of the ADC is its sampling rate. ADCs with high sampling rates are power consuming and expensive which make them unsuitable for portable devices such as hand-held ultrasound device. Hence, it is desirable to reduce the sampling rate. Following the Shannon-Nyquist sampling theorem \cite{shannon, nyquist}, it is well known that the sampling rate of bandlimited signals are dictated by their highest frequency. Hence, in wideband signal applications one can not sample below the Nquist rate by considering the bandlimited signal model.

Finite-rate-of-innovation (FRI) model is another signal model which is ubiquitous in several time of flight applications \cite{bajwa_radar, bar_radar,filho201seismic,rip,carter_sonar,eldar_sos,eldar_beamforming}. In these applications, the signal of interest consists of a linear combination of delayed copies of a known pulse. Thus, the desired information lies in the amplitudes and time delays of the pulse which amounts to few degrees of freedom and aids sub-Nyquist sampling \cite{eldar_2015sampling}. Most prior works in the context of FRI sampling are focused on reducing the sampling rate of the ADC by using the signal structure and consequently reducing the power consumption and cost of the ADCs \cite{vetterli, eldar_sos, fri_strang, blu_moms, mulleti_kernal}.

Dynamic range of an ADC too plays a crucial role in sampling an analog signal. In general, ADC's dynamic range should be larger than that of the signal's, otherwise the signal is clipped. There exist a few approaches to recover the true samples from clipped ones for bandlimited signals \cite{marks_clipping2, marks_clipping1}. These approaches relies on correlation among the samples when they are measured at very high-rate compared to the Nyquist rate. Requirement of high-sampling rate is a drawback of these approaches. In addition, theoretical guarantees are missing and it is not clear on how many clipped samples can be recovered.

There are three popular analog preprocssing approaches, namely automatic gain control (AGC) \cite{perez2011automatic,mercy1981review}, companding \cite{landau_compander,landau_distorted_bl}, and modulo folding \cite{uls_tsp,uls_romonov,uls_sparse,bhandari2021unlimited,eyar_moduloicassp}, that can be used prior to sampling to avoid clipping. In AGC, a chain of amplifiers is used with a feedback loop such that a suitable output level is maintained at the output \cite{perez2011automatic,mercy1981review}. An AGC system uses a closed loop feedback mechanism to maintain a constant signal level at its output for a varying input signal levels \cite{perez2011automatic,mercy1981review}. The closed loop feedback consists of a chain of amplifiers and maintaining its stability is a challenging task. Companding is an alternative approach to limit the dynamic range of the input signals. In this approach, smaller amplitudes of the signals have larger gain compared to the larger ones. Beurling presented theoretical guarantees and proved that knowledge of the companded signal over the input signal's bandwidth is sufficient to uniquely identify the signal provided \cite{landau_compander}. Landau et al. \cite{landau_distorted_bl} proposed an iterative algorithm to recover a bandlimited signal from its companded signal. The algorithm converges if the compander is differentiable over the dynamic range of the input signal which limits its practical application.

The third approach is to use modulo folding prior to sampling which fold the input signal to lie within the dynamic range of the ADC \cite{uls_tsp,uls_romonov,uls_sparse,bhandari2021unlimited,eyar_moduloicassp}. The folded signal is then sampled by using a conventional ADC. Theoretical guarantees for recovering bandlimited signals from folded samples are presented in \cite{uls_tsp,uls_identifiability}. The results states that the bandlimited signals can be uniquely recovered from folded samples provided that they are sampled above the Nyquist rate. Several algorithms for \emph{unfolding} or recovering the true samples of bandlimited signals from modulo or folded samples are presented in \cite{uls_tsp,uls_romonov, eyar_moduloicassp}. These unfolding algorithms can be compared in terms of sampling rate, amount of unfolding they can accommodate, and noise robustness. It is shown that the method proposed in \cite{eyar_moduloicassp} has lowest reconstruction error for a given sampling rate, noise level, and signal's amplitude level compared to the algorithms presented in \cite{uls_tsp,uls_romonov}. The algorithm proposed in \cite{uls_tsp} requires almost 17-times higher sapling rate than the Nyquist rate but it is independent of the dynamic range of the ADC. Whereas, the approaches in \cite{uls_romonov, eyar_moduloicassp} requires the knowledge of ADC's dynamic range. Modulo sampling is also extended to different problems and signal models such as periodic bandlimited signals \cite{bhandari2021unlimited}, wavelets \cite{uls_wavelet}, mixture of sinusoids \cite{uls_sinmix}, finite-rate-of-innovation signals \cite{uls_fri}, multi-dimensional signals \cite{uls_md}, sparse vector recovery \cite{uls_gamp, uls_sparsevec}, direction of arrival estimation problem \cite{uls_doa}, computed tomography \cite{uls_radon}, and graph signals \cite{uls_graph}.

While theoretical guarantees and algorithms of any new sampling approach are always well researched but the question on whether they work in practice is always difficult to answer. For modulo sampling, there exists a few hardware prototypes. For example, high-dynamic-range ADCs, also known as \emph{self-reset} ADCs, are discussed in the context of imaging \cite{sradc_park, sradc_sasagwa, sradc_yuan, krishna2019unlimited}. These hardware architectures measures additional information such as the amount of folding for each sample, or, the sign of the folding together with the folded samples. The additional information might enable simpler recovery but at the expense of complex circuitry. Importantly, additional bits are required during the quantization process to store or transmit the side information.

Krishna et al. presented a hardware prototype which encode the side-information by using two bits \cite{krishna2019unlimited}. The architecture is designed to record sign of the slope of the signal at each sampling instant when the sample lies outside ADC's dynamic range. In a conventional ADC, a sample and hold (S/H) circuit is used to hold the sampled value for a prescribed period of time during which quantization is performed on the sample. To realize the modulo sampling, a folding circuit is used after S/H \cite{krishna2019unlimited}. Hence, the S/H circuit has to hold the sampled value for folding and quantization, which results in a larger folding time compared to a conventional ADC. A large holding time results in slower ADC and hence it may not be useful for wideband application.

The proposed modulo-ADC is able to sample signals beyond its dynamic range while keeping the power dissipation and area requirements lower compared to a conventional ADC \cite{krishna2019unlimited}. A major drawback of this modulo-ADC's architecture is that the modulo operation is performed between the sample and hold (S/H), and quantization blocks of the ADC. Specifically, modulo operation is performed on the hold values of S/H circuit and then the folded sample is quantized. Hence, compared to a conventional ADC, the hold time is relatively high which makes the architecture slower.

\newpage
In introduction, we discuss the following:

1st-paragraph: Standard sampling and sub-Nyquist; importance of low sampling rates; FRI signal model and application to radar\\

2nd-paragraph: Introduce the dynamic range issue and discuss the existing approaches to address it: AGC, commanding, and modulo. Why modulo is important.\\

3rd paragraph: Discuss about modulo method, recovery algorithms and their issues with high-sampling rates and instability in noise. Discuss about our proposed algorithm (Eyar's ICASSP-22 paper)\\

4th paragraph: Can we implement these in HW? Discuss about hardware prototypes and applications. Shortcomings: No practical applications, low operating frequencies, more?\\

5th paragraph: In this paper, we present a HW prototype combined with recently proposed algorithm to address these issues.\\

 6th Paragraph: The paper is organized as follows; Notations \\

\section{Signal Model and System Description}
In this section, we first introduce FRI signal model and then discuss its sampling and reconstruction framework with modulo ADC.
\subsection{FRI Signal Model}
Consider an FRI signal consisting of stream of $L$ pulses:
\begin{align}
	f(t) = \sum_{\ell=1}^L a_\ell h(t-t_\ell),
	\label{eq:fri1}
\end{align}
where the pulse $h(t)$ a real-valued known pulse. We assume that $a_\ell$s are real-valued and $t_\ell \in (0, T_d] \subset \mathbb{R}$ for a known $T_d$.

The FRI signal model in \eqref{eq:fri1} is encountered in several scientific applications such as radar imaging \cite{bar_radar, bajwa_radar, sunil}, ultrasound imaging \cite{eldar_sos,eldar_beamforming,mulleti_icip}, light detection and ranging (LIDAR) \cite{castorena_lidar}, time-domain optical-coherence tomography (TDOCT) \cite{blu_oct}, and other time-of-flight imaging systems. In these applications,  $h(t)$ is the transmitted pulse and $\{a_\ell \,h(t-t_\ell)\}_{\ell=1}^{L}$ constitute the reflections from $L$ point targets. The amplitudes $a_\ell$s depend on the sizes of the targets and the delays $t_\ell$s are proportional to the distances of the targets from the transmitter. Here $T_d$ denotes maximum time delay of the targets. The signal $f(t)$ is specified by $\{a_\ell, t_\ell\}_{\ell=1}^L$ and can be reconstructed from its sub-Nyquist measurements acquired using an appropriate sampling kernel \cite{vetterli,eldar_sos,fri_strang, mulleti_kernal}. The reconstruction is generally carried out in frequency domain as discussed next.

\subsection{Fourier-Domain Reconstruction}
Consider uniform samples of continuous-time Fourier transform of $f(t)$ given as
\begin{align}
	F(k \omega_0) = \int f(t) e^{-\mathrm{j} k\omega_0 t} \mathrm{d}t = H(k \omega_0) \sum_{\ell = 1}^L a_\ell \, e^{-\mathrm{j} k\omega_0 t_\ell},
	\label{eq:F}
\end{align}
for $k \in \mathcal{K}$ where $H(\omega)$ is the Fourier transform of $h(t)$ and $\mathcal{K}$ is a set integers. In \eqref{eq:F}, $\omega_0>0$ denotes sampling interval in the frequency domain. Next, consider the following samples
\begin{align}
	S(k\omega_0) = \frac{F(k\omega_0)}{H(k\omega_0)} =  \sum_{\ell = 1}^L a_\ell \, e^{-\mathrm{j}k\omega_0 t_\ell},
	\label{eq:Skomega}
\end{align}
where we assume that $H(k \omega_0) \neq 0$ for $k \in \mathcal{K}$. In practice, the pulse $h(t)$ has small time support and hence, large bandwidth. Hence, for a finite set $\mathcal{K}$ it is possible to choose a set of frequencies $\{k \omega_0\}_{ k \in \mathcal{K}}$ such that $H(k \omega_0) \neq 0$ for $k \in \mathcal{K}$. It can be shown that $2L$ consecutive samples of $S(k\omega_0)$ are sufficient to uniquely identify $\{a_\ell, t_\ell\}_{\ell=1}^L$ if $\omega_0 = \frac{2\pi}{T_d}$ \cite{eldar_2015sampling}. In practice, high-resolution spectral estimation methods, such as the annihilating filter (AF) or Prony's method and its variants \cite{prony, plonka}, multiple signal classification \cite{schmidt_music, barabell_rmusic, bdrao_rmusic}, matrix-pencil method \cite{sarkar_mp}, estimation of signal parameter via rotational invariance technique (ESPRIT) \cite{paulraj_esprit}, etc. have been deployed for FRI parameter estimation.

Since $h(t)$ is known, $H(k\omega_0), k \in \mathcal{K}$ can be calculated in advance. Hence, to compute $S(k\omega_0), k \in \mathcal{K}$ and then estimate FRI parameters, $F(k\omega_0), k \in \mathcal{K}$ has to be determined. Next, we discuss a lowpass filter (LPF) based sampling framework to determine these Fourier samples.

\subsection{LPF-Based Sub-Nyquist Sampling}
In this section, we discuss a LPF-based sampling mechanism for FRI signals. Let $g(t)$ denotes an ideal lowpass filter with cutoff frequency $\omega_c$ rad/sec. In the frequency-domain we have that $G(\omega) = 1$ for $\omega \in [-\omega_c, \omega_c]$ and zero for the rest of the frequencies. Let $y(t)$ denotes response of the LPF to the input $f(t)$, that is, $y(t) = (f*g)(t)$, where $*$ denotes linear convolution operation. Consider an ADC with dynamic range $[-\lambda, \lambda]$ and sampling rate $\omega_s = \frac{2\pi}{T_s}$ rad/sec. By assuming that  $\|y(t)\|_{\infty}\leq \lambda$, uniform samples at the output of ADC are given as $y(nT_s), n \in \mathbb{Z}$. Then uniform measurements of discrete-time Fourier transform (DTFT) of the samples are given as
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) = \sum_{n \in \mathbb{Z}}y(nT_s)\,e^{\mathrm{j} k\omega_0 n T_s}, \quad k \in \mathcal{K}.
	\label{eq:y_dtft}
\end{align}
By using relationship between DTFT of samples $y(nT_s)$ and CTFT of $y(t)$ we have
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) &= \frac{1}{T_s}\sum_{m \in \mathbb{Z}} Y(k\omega_0 + m \omega_s), \nonumber \\
	&= \frac{1}{T_s}\sum_{m \in \mathbb{Z}} F(k\omega_0 + m \omega_s) \,G(k\omega_0 + m \omega_s),
		\label{eq:y_dtft2}
\end{align}
where we used the fact that $Y(\omega) = F(\omega)\,G(\omega)$. Next, consider the following conditions on the sampling rate and cutoff frequency of the filter
\begin{align}
	\omega_s \geq 2\omega_c, \quad \text{and} \quad \omega_c \geq K \omega_0,
	\label{eq:sampling_rate}
\end{align}
where $K \geq L$. Then by choosing $\mathcal{K} = \{-K, \cdots, K\}$, \eqref{eq:y_dtft2} can be written as
\begin{align}
	Y(e^{\mathrm{j} k\omega_0 T_s}) = F(k\omega_0), \quad k \in \mathcal{K},
	\label{eq:y_dtft3}
\end{align}
where we used the fact that $G(k\omega_0) = 1$ in these settings. The relationship \eqref{eq:y_dtft3} shows that the desired Fourier samples of $f(t)$ are determined from the samples of LPF by assuming that the conditions in \eqref{eq:y_dtft2} are satisfied. Hence, FRI parameters can be determined from the samples of the lowpass filter.

The bandwidth of the pulse $h(t)$ and hence that of the FRI signal $f(t)$ could be very large. But the sampling rate $\omega_s$ is independent of the pulse and could be much smaller than its bandwidth which shows the FRI signal could be reconstructed from sub-Nyquist samples.

The sub-Nyquist sampling framework discussed assumes that $\|y(t)\|_{\infty}\leq \lambda$, in other words, the framework assumes that the dynamic range of the ADC is greater than that of the signal to be sampled. However, this condition may not be always true. Specifically, the amplitude range of the filtered signal $y(t)$ could be larger than ADC's dynamic range. In such scenario, a direct sampling would lead to clipping of samples which is undesirable. To avoid clipping, a modulo operator is employed prior to sampling as discussed next.

\begin{figure*}
	\centering
	\includegraphics[width=6.5 in]{Figs/FRI_US}
	\caption{A schematic of modulo-sampling and reconstruction of FRI signals.}
	\label{fig:fri_framework}
\end{figure*}

\subsection{Modulo-Folding}
To avoid clipping, a modulo folding operator $\mathcal{M}_\lambda(\cdot)$ is used after LPF and before the ADC. The operator folds $y(t)$ to stay within ADC's dynamic range $[-\lambda, \lambda]$. The output of the modulo operator in response to input $y(t)$ is given as\begin{equation}
 y_\lambda(t) =	\mathcal{M}_{\lambda}(y(t)) = (y(t)+\lambda)\,\, \text{mod}\,\, 2\lambda -\lambda.
	\label{eq:mod_opp}
\end{equation}
The folded signal is then sampled by the ADC to have measurements $y_\lambda(nT_s)$. Since modulo folding is a nonlinear operation, one can not directly apply DTFT on the samples to compute Fourier measurements of the FRI signal for its reconstruction. Hence, the true or unfolded samples $y(nT_s)$ are estimated from the folded ones $y_\lambda(nT_s)$ by applying an unfolding algorithm. There exist several unfolding methods for badnlimited signals such as $y(t)$ \cite{uls_tsp, uls_romonov,eyar_moduloicassp}. The sampling rates for unfolding varies for different algorithms and generally, is larger than the minimum sampling rate required for FRI signal recovery (cf. \eqref{eq:sampling_rate}). Hence, the overall system operates on a higher sampling rate than that in without modulo case. However, if the overall sampling rate is much lower than the bandwidth of the FRI signal then the system operates at sub-Nyquist rate. We show that this is indeed true when we apply our unfolding algorithm proposed in \cite{eyar_moduloicassp}.

An end-to-end modulo sampling framework for FRI signal sampling and reconstruction is shown in Fig.~\ref{fig:fri_framework}. The sampler or ADC together with the modulo block is termed as modulo-ADC. Modulo-ADC's are able to sample signals beyond their dynamic range without clipping and hence they are termed as high-dynamic range ADCs. Alternatively, an ADC with much lower dynamic range can be used to sample signals with larger amplitudes. Sub-Nyquist sampling and low-dynamic range requirements significantly reduces the power consumption and cost of the ADC.

The modulo folding block is key component of the high-dynamic range ADC and we discuss it hardware implementation in the next section.

\begin{figure}
	\centering
	\includegraphics[width= 3 in]{Figs/folding}
	\caption{Folding principle}
	\label{Fig:folding}
\end{figure}
\section{Modulo Hardware Prototype}
In this section, we discuss our modulo hardware prototype. First, we explain the working principle of the modulo block and explain how its design and then discuss the hardware realization.
\subsection{Working Principle of Modulo Block}
Principle of co
M

File outline
Editor mode.

	\caption{Modulo Hardware Board}

mputing $y_\lambda(t)$ from $y(t)$ is shown by block-diagram in Fig.~\ref{Fig:folding}. The system comprises of an adder, a direct-current voltage generator (DC-VG), and two comparators $C_1$ and $C_2$. To understand the working let us first assume that for some time instant $t_1$, we have that $|y(t)|<\lambda$ for $t<t_1$. Hence $y_\lambda(t) = y(t)$ and $z(t) = 0$ for $t<t_1$. At $t=t_1$, let $|f(t)|$ crosses $\lambda$. If $f(t_1)>0$, then the comparator $C_1$ triggers a positive spike or else, $C_2$ triggers a negative spike. The DC-VG is designed such that for every positive spike input it reduces its output signal level by $-2\lambda$, whereas, for negative spike it increases its output voltage by $2\lambda$. Hence, in the current example, DC-VG generates signal $z(t) = \text{sgn}(y_\lambda(t_1)) 2\lambda u(t-t_1)$ where $u(t)$ is unit-step function.
In this way by adding or subtracting constant DC signals from $f(t)$ whenever it crosses dynamic range $[-\lambda, \lambda]$, the amplitude levels of $f_\lambda(t)$ are kept within ADC's dynamic range.

\begin{figure}
	\centering
    \includegraphics[width=0.48\textwidth]{IEEE_TAES_v1/Figs/UDR_Board_Labeled.PNG}
	\caption{DC-VG Modulo Hardware Board}
	\label{Fig:hw_board}
\end{figure}

\begin{figure}
    \centering
    \includegraphics[width=0.48\textwidth]{IEEE_TAES_v1/Figs/UDR block_diag v3.png}
    \caption{UDR block diagram.}
    \label{fig:UDRscheme}
\end{figure}

\begin{table}[h!]
\centering
\begin{tabular}{||c c c||}
 \hline
 Device & Reference & Manufacturer \\ [0.5ex]
 \hline\hline
 Signal Generator & & \\
 Signal Generator & & Arduino\\
 DAC & msp4725 & Microchip \\
 && \\
 Comparator & & \\
 Comparator & LM339 & Texas Instruments \\
 && \\
 UP/DOWN Counter & & \\
 UP/DOWN Counter & & Arduino \\
 && \\
 DAC 3bits & & \\
 DAC 3bits & LT1364 & Analog Devices \\
 && \\
 Analog MUX & & \\
 Analog MUX & ADG1608 & Analog Devices \\
 && \\
 Analog Multiplier & & \\
 Analog Multiplier & AD835 & Analog Devices \\
 && \\
 Subtractor & & \\
 Subtractor & LT1364 & Analog Devices \\
  && \\ [1ex]
\hline
\end{tabular}
\caption{Device list.}
\label{table:1}
\end{table}

{\color{blue}\subsection{UDR performance}}
Show sinewave plots at different frequencies

\newpage
~\newpage
\section{Results}
\subsection{Simulated results}
In this section, we present simulated results of several methods for recovering a bandlimited signal from the modulo samples.
Specifically, we compare the proposed algorithm with the \emph{higher-order differences} (HOD) approach \cite{unlimited_sampling17, uls_tsp} and \emph{Chebyshev polynomial filter}-based (CPF) method \cite{uls_romonov}.
We handle the noisy setting where we compare the proposed and existing approaches for reconstructing signals from modulo samples.
We exhibit the robustness to noise of the $B^2R^2$ algorithm for different noise level and the over-sampling factor.
We consider reconstruction problem from the next noisy samples
        \begin{align}
            \tilde{f}_{\lambda}(n T_s) = {f}_{\lambda}(n T_s) + v(n T_s) = \mathcal{M}_{\lambda}f(n T_s) + v(n T_s),
        \label{eq: noisy_samples}
        \end{align}
where $v(n T_s)$ specifies the noise.
In the experiments the modulo parameter $\lambda$ is fixed to $1.25$. We normalize the bandlimited signals to have maximum amplitude of $10$.
The SNR is calculated as $\text{SNR} = 20 \log\left(\frac{||f_{\lambda}(n T_s)||}{||v(n T_s)||}\right)$. The reconstruction accuracy of different methods is compared in terms of normalized mean-squared error (MSE) as $ \frac{\sum |f(nT_s) - \hat{f}(n Ts)|^2}{\sum |f(nT_s)|^2}$, where $\hat{f}(n T_s)$ signifies the estimate of $f(n T_s)$.
For each noise level and over-sampling factor, we examine 100 independent noise realizations and we calculate the average MSE for them.

\subsubsection{Quantization noise}
 In these experiments, we consider an uniform quantizer after the sampling. We compare the algorithms for different number of bits and OFs. Fig. ~\ref{Fig:quantization} shows MSEs of the different methods for OF $ = 3$ and $6$.

\subsubsection{Unbounded noise}
    For the unbounded noise we assume that the noise measurements $v(nT_s)$ are independent and identically distributed Gaussian random variables with zero mean. The variance is set to achieve a desired SNR. We compare the methods for different values of SNR and OFs. Fig.~\ref{Fig:unbounded} shows MSE of the different algorithms for OF $= 3$ and $6$.

\begin{figure*}
	\centering
	\includegraphics[width= 3 in]{IEEE_TAES_v1/Figs/quantization.png}
	\caption{Quantization noise}
	\label{Fig:quantization}
\end{figure*}

\begin{figure*}
	\centering
	\includegraphics[width= 3 in]{IEEE_TAES_v1/Figs/Gaussian.png}
	\caption{Unbounded noise}
	\label{Fig:unbounded}
\end{figure*}

\subsection{Hardware Results}
{\color{blue}{
Hardware results and data to be generated:
\begin{enumerate}
    \item Sinusoidal frequencies and their modulo responses with different frequencies. We should capture the response on a CRO and please also take a video. Goal: To show the frequency response. \\
    Five frequencies, $f_1. f_2, f_3, f_4, f_5$. For frequencies less than $f_3$, everything should work well. From $f_3$ on wards the distortion should appear. Amplitude of the signal or sinusoidal is denoted by $A$ and dynamic range is $\lambda$. We need to fix $\frac{A}{\lambda} = 2$ (one fold).
    \item Sinusoidal frequencies and their modulo responses with different amplitudes. Goal: how much folding can be achieved.\\
    Fix the frequency to $f_1$. Show the response for different values of $\frac{A}{\lambda}$
    \item We need design an experiment to show the delay in the feedback loop for different frequencies. Goal: To show that for small frequencies the delays do not have any effect.
    \item We to generate output of a lowpass filter with cutoff frequency $f_c$ Hz, send it to the modulo, sample at higher rates. Give the samples to Eyar for reconstruction. We need to generate a set of such examples. May be 6. Then we can show a few of them. Note: Capture both the lowpass signal and modulo response for a better comparison. Goal: to show recovery of bandlimited signals.
    \item We should generate two pulses with different time-delays. The bandwidth of each pulse should be 12-15 times the cutoff of lowpass filter. Then lowpass filter, modulo it, and measure the samples. We need to capture each of the pulses. Goal: To recover FRI signals.

\end{enumerate}
}}

\section{Hardware Simulation}
\begin{align}
    x(t) = \frac{\sin(w_c t)}{w_c t}
\end{align}

\section{Conclusions}

\newpage~\newpage

\section*{APPENDIX}

Appendixes, if needed, appear before the acknowledgment.

\section*{ACKNOWLEDGMENT}
The preferred spelling of the word ``acknowledgment'' in American English is without an ``e'' after the ``g.'' Use the singular heading even if you have many acknowledgments. Avoid expressions such as ``One of us (S.B.A.) would like to thank ... .'' Instead, write ``F. A. Author thanks ... .'' In most cases, sponsor and financial support acknowledgments are placed in the unnumbered footnote on the first page, not here.

\bibliographystyle{IEEEtaes}

\section{INTRODUCTION}
Analog-to-digital converters (ADCs) bridge real-world analog signals and digital processors on which signals can be processed efficiently. Typically, ADCs measure instantaneous uniform samples of analog signals to represent them digitally. A key parameter in such conversion is the sampling rate. Power consumption and cost of an ADC increase with the increase in the sampling rate. Hence, keeping the sampling rate as low as possible is desirable. Theoretically, the sampling rate has to be greater than the Nyquist rate for perfect reconstruction of bandlimited signals. Apart from the sampling rate, there are several other aspects of an ADC which play a key role in faithful sampling and reconstruction, especially when the sampling frameworks are implemented in hardware.

The dynamic range of an ADC plays a crucial role in sampling an analog signal. Generally, ADC's dynamic range should be larger than the signal's; otherwise, the signal gets clipped. A few approaches exist to recover the true samples from clipped ones for bandlimited signals \cite{marks_clipping2, marks_clipping1}. These approaches rely on the correlation among the samples when they are measured at a very high rate compared to the Nyquist rate. The requirement of a high sampling rate is a drawback of these approaches.

Several preprocessing approaches to avoid clipping exist, such as automatic gain control (AGC) \cite{perez2011automatic,mercy1981review}, companding \cite{landau_compander,landau_distorted_bl}, and modulo folding \cite{uls_tsp,uls_romonov,bhandari2021unlimited,eyar_moduloicassp, azar2022robust}. Among these, modulo folding is the most recent approach that need not be differentiable like companding and does not suffer from stability issues of the feedback amplifiers used in AGCs. In the modulo framework, the signal is folded to lie within the ADC's dynamic range, and then the folded signal is sampled using a conventional ADC. Theoretical guarantees for recovering bandlimited signals from folded samples are presented in \cite{uls_tsp}. The results state that a bandlimited signal can be uniquely recovered from its folded samples provided that they are sampled above the Nyquist rate \cite{uls_tsp}.

Several algorithms for \emph{unfolding} or recovering the true samples of a bandlimited signal from a modulo or folded samples are presented in \cite{uls_tsp,uls_romonov, eyar_moduloicassp}. These unfolding algorithms can be compared in terms of sampling rate, amount of unfolding they can handle, and noise robustness. The algorithm proposed in \cite{uls_tsp} requires almost 17 times higher sampling rate than the Nyquist rate. The approaches in \cite{uls_romonov} and \cite{eyar_moduloicassp,azar2022robust} operate at relatively lower sampling rates but require the knowledge of ADC's dynamic range. In contrast, the method proposed in \cite{eyar_moduloicassp,azar2022robust} requires a lower sampling rate, even in the presence of noise, compared to the algorithms presented in \cite{uls_tsp,uls_romonov}. Modulo sampling is also extended to different problems and signal models such as periodic bandlimited signals \cite{bhandari2021unlimited}, finite-rate-of-innovation (FRI) signals \cite{uls_fri}, sparse vector recovery \cite{uls_sparsevec}, direction of arrival estimation \cite{uls_doa}, computed tomography \cite{uls_radon}, and graph signals \cite{uls_graph}.

Beyond theoretical works, there also exist a few related hardware prototypes. High-dynamic-range ADCs, also known as \emph{self-reset} ADCs, are discussed in the context of imaging \cite{sradc_park, sradc_sasagwa, sradc_yuan, krishna2019unlimited}. These hardware architectures measure additional information, such as the amount of folding for each sample or the sign of the folding together with the folded samples. The additional information might enable simpler recovery at the expense of complex circuitry. Importantly, additional bits are required during the quantization process to store or transmit the side information.

Krishna et al. presented a hardware prototype that encodes the side information by using two bits \cite{krishna2019unlimited}. The architecture is designed to record the sign of the slope of the signal at each sample that lies outside the ADC's dynamic range. In a conventional ADC, a sample and hold (S/H) circuit is used to hold the sampled value for a prescribed period of time, during which quantization is performed on the sample. A folding circuit is used after S/H  to realize the modulo sampling \cite{krishna2019unlimited}. In this architecture, the S/H circuit has to hold the sampled value for folding and quantization, resulting in a larger holding time than a conventional ADC. A large holding time results in slower ADCs, which may not be helpful in applications with high-frequency signals. The resulting hardware circuit is able to fold signals up to 300 Hz, where the signal's amplitude should be less than three times the ADC's dynamic range.

Modulo hardware prototypes where the modulo part is implemented prior to the sampler are presented in \cite{bhandari2021unlimited,Bhandari:2022:J,mod_hyst}.
In these works, the authors are focused on different signal models, hardware limitations, and algorithms rather than providing details of the hardware circuitry. It was shown that the modulo hardware is able to fold low-frequency ($<300$ Hz) signals that are tenfold larger than the ADC's dynamic range. However, it is not clear how the hardware performs for high-frequency signals, and many details of the circuitry are omitted.

In practical applications, the frequency range of the signals can vary from a few kHz to several MHz. For example, the finite-rate-of-innovation (FRI) model is widely used to represent signals in time-of-flight applications such as ultrasound, sonar, and radar \cite{vetterli,eldar_sos}. These FRI signals have frequencies much higher than 300 Hz, and hence current hardware prototypes can be used, especially when the signal's bandwidth ranges up to a few kHz. Hence it is desirable to design and develop a modulo sampler that can operate at high frequencies while folding signals faithfully.

In this paper, we present a modulo hardware prototype that can be used for modulo sampling of signals up to 10 kHz. We show that by using our algorithm \cite{eyar_moduloicassp}, it is able to reconstruct bandlimited and FRI signals faithfully.
In the following, we present the contributions and the features of the proposed hardware system.
\begin{itemize}
    \item We design our hardware components to be able to fold signals up to 10kHz. Existing hardware shows results for signals below 300 Hz.

    \item The hardware prototype is designed to perform folding prior to the sampler, unlike the hardware in \cite{krishna2019unlimited}, which operates in the hold part of the sampler.  Thus, the suggested system can utilize faster ADCs with shorter hold times.

    \item In the proposed hardware prototype, modulo folding is realized through a feedback mechanism. At the time instants when the input signal goes beyond the ADC's dynamic range, a trigger signal is generated by using comparators. The trigger then activates a direct voltage generator that adds to the input signal to bring it within the dynamic range. This mechanism imposes a delay between the trigger time and the folding instance. We address this key issue of the hardware, which is not considered in previous works.
    By using the signal's smoothness and the feedback loop's time delay,
    we propose a hardware solution to avoid clipping that occurs due to the delay issue.

    \item The designed hardware prototype can operate at a maximum voltage of 11.75 v. The limitation is largely due to the use of a 15v subtractor or adder in the feedback loop, which enables a fast slew rate in the transitions of $\pm 2\lambda$. At high frequencies, these components can not be used at voltage above 15 v. In addition, we used an ADC with a dynamic range $[-1.25, 1.25]$. Hence, the hardware can fold signals which are eight times larger than the dynamic range of the signal.

    \item For demonstration, we consider sampling and reconstruction of bandlimited and FRI signals. For FRI signals, we use a lowpass sampling kernel prior to modulo folding. The filter removes unwanted information in the signal and allows sub-Nyquist sampling. Using our algorithm presented in \cite{eyar_moduloicassp,azar2022robust}, we show reconstruction of bandlimited signals from their folded samples measured through the hardware. We show that the combination of the proposed hardware and low-rate algorithm is able to reconstruct the signals by using a low-dynamic range ADC. In particular, for FRI signals, we show that the FRI parameters can be estimated with sub-Nyquist samples by utilizing the fact that our algorithm operates at the lowest possible rate.

\end{itemize}

The paper is organized as follows. In the next section, we discuss the signal model considered and the sampling and reconstruction framework in the presence of modulo hardware. In Section III, we present the hardware system by explaining its working principle and discussing the components of the system. In Section IV, we show the hardware's signal folding and reconstruction abilities.

\section{Signal Model and System Description}
\begin{figure*}
	\centering
	\includegraphics[width=4 in]{Figs/BL_US}
	\caption{A schematic of modulo-sampling and reconstruction of bandlimited signals.}
	\label{fig:bl_framework}
\end{figure*}
In this section, we consider modulo sampling for signals whose amplitudes lie beyond the bandwidth of the ADC's dynamic range. The class of signals that can be folded by modulo hardware can be very large; however, the recovery is limited by existing unfolding algorithms. For example, most unfolding algorithms are designed for bandlimited signals. Given this, we consider bandlimited signals as input to the modulo hardware and corresponding unfolding algorithms. We use a lowpass sampling kernel for FRI signals to make them bandlimited and, at the same time, reduce the sampling rate following the sub-Nyquist framework \cite{eldar_sos, mulleti_kernal}.

Consider a $\omega_c$-bandlimited signal $y(t)$ such that its Fourier transform $Y(\omega)$ vanishes outside the frequency interval $[-\omega_c, \omega_c]$. The signal can be perfectly reconstructed from its uniform samples measured at the Nyquist rate $\omega_{Nyq} = 2\omega_c$ rad/sec. provided that the ADC's dynamic range is above the signal's dynamic range. Specifically, if the dynamic range of the ADC is $[-\lambda, \lambda]$ for some $\lambda >0$ then it is assumed that $|y(t)|\leq \lambda$ for perfect reconstruction. If $|y(t)|>\lambda$, then the signal and its samples will be clipped, and perfect reconstruction is not guaranteed. In the latter scenario where $|y(t)|>\lambda$, one can either increase the dynamic range of the ADC or use prepossessing to avoid clipping. We consider the later solution where the modulo operation $\mathcal{M}_{\lambda}(\cdot)$ is applied to the signal $y(t)$ to restrict its dynamic range to $[-\lambda, \lambda]$. The output of the modulo operator in response to input $y(t)$ is given as
\begin{equation}
 y_\lambda(t) =	\mathcal{M}_{\lambda}(y(t)) = (y(t)+\lambda)\,\, \text{mod}\,\, 2\lambda -\lambda.
	\label{eq:mod_opp}
\end{equation}
The folded signal $y_\lambda(t)$ is then sampled to get discrete measurements $y_\lambda(nT_s)$. Due to modulo folding, $y_\lambda(t)$ is no longer bandlimited. To recover $y(t)$ while sampling slightly above the Nyquist rate of the input, one first applies an unfolding algorithm to recover $y(nT_s)$ from $y_\lambda(nT_s)$ \cite{eyar_moduloicassp,azar2022robust,mulleti2022modulo}. Then $y(t)$ is reconstructed from $y(nT_s)$ by assuming that the sampling is performed above the Nyquist rate.

A schematic of modulo sampling and reconstruction framework is shown in Fig.~\ref{fig:bl_framework}. It consists of a modulo-ADC followed by unfolding and reconstruction blocks. The modulo-ADC is comprised of a modulo-folding block followed by a conventional uniform sampler. The unfolding operation is implemented in the digital domain, and it should operate at the lowest possible sampling rate. To this end, we use the $B^2R^2$ algorithm for unfolding \cite{eyar_moduloicassp,azar2022robust}, which samples efficiently compared to other algorithms for bandlimited signals. Low-rate sampling and low-dynamic range requirements significantly reduce the power consumption and cost of the ADC.

Our objective is to demonstrate a robust hardware prototype of modulo ADC as discussed next.

\begin{figure}
	\centering
	\includegraphics[width= 3 in]{Figs/folding}
	\caption{Folding principle.}
	\label{Fig:folding}
\end{figure}
\section{Modulo Hardware Prototype}
In this section, we discuss the prototype of our modulo hardware. The modulo block's working principle and design will be discussed first, followed by its hardware implementation.
\subsection{Working Principle of Modulo Block}
The principle of computing $y_\lambda(t)$ from $y(t)$ is shown by the block diagram in Fig.~\ref{Fig:folding}. The system comprises an adder $S$, a direct-voltage generator (DVG), and two comparators, Comp-1 and Comp-2. To understand the working flow, let us first assume that for some time instant $t_1$, we have that $|y(t)|<\lambda$ for all $t<t_1$. Hence $y_\lambda(t) = y(t)$ and $z(t) = 0$ for all $t<t_1$. At $t=t_1$, let $|y(t)|$ cross $\lambda$. If $y(t_1)>\lambda$, then Comp-1 triggers a positive value. Else if, $y(t_1)<\lambda$, Comp-2 triggers a negative value. The DVG is designed such that for each positive input value, its output signal level increases by $-2\lambda$, whereas, for a negative input value, it decreases its output voltage by $2\lambda$. Hence, in the current example, DVG generates a signal $z(t) = \text{sgn}(y_\lambda(t_1)) 2\lambda u(t-t_1)$ where $u(t)$ is the unit-step function. In this way, by adding or subtracting (using $S$) constant DC signals from $y(t)$ whenever it crosses the dynamic range $[-\lambda, \lambda]$, the amplitude levels of $y_\lambda(t)$ are kept within the ADC's dynamic range.

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3 in]{Figs/dc_vg}
	\caption{Discrete Voltage Generator (DVG).}
	\label{Fig:dcvg}
\end{figure}

\begin{figure*}[!t]
	\centering
	\includegraphics[width=0.86\textwidth ]{Figs/UDR_Board_Labeled3.PNG}
	\caption{Modulo hardware board.}
	\label{Fig:hw_board}
\end{figure*}

While the parts such as comparators Comp-1 and Comp-2, and adder $S$ can be realized by using off-the-shelf components, DVG is a more involved system due to its feedback nature and requires careful design. Specifically, the feedback loop should follow changes in the input signal in the desired frequency and amplitude ranges. A detailed architecture of DVG is shown in Fig.~\ref{Fig:dcvg}. Its task is to generate a constant voltage signal whose amplitude is a constant multiple of $2\lambda$. Importantly, its output voltage $z(t)$ should increase (or decrease) by $2\lambda$ v for every negative (or positive trigger) at its input. To realize this task in the hardware, we use an up/down counter, a digital-to-analog converter (DAC), a multiplexer (MUX), and a multiplier $M$.

In the hardware design, we set $\lambda = 1.25$ v.
We start with the DAC, which can generate piecewise constant voltage output $s(t)$ in response to its digital input. Let the resolution, or step size of the DAC, be $\alpha$ v. Then, when the input bits of DAC go from one state to the next, the DAC output increases by $\alpha$ v. On the other hand, when the bits change from the present state to the previous state, output voltage $s(t)$ reduces by $\alpha$ v. Hence, the ADC works in a fashion expected by DVG with the following exceptions: (1) Input to the DAC is bits and one needs to map positive/negative trigger from comparators to these bits; (2) Output of the DAC takes only positive values and are multiple of $\alpha$. A scaling is required to make them multiple of $\pm 2\lambda$. To address the first issue, we employ a UP/DOWN counter whose inputs are the trigger voltages from the capacitors Comp-1 and Comp-2, and the output is bits. For every positive trigger at the input counter, output bits change to the next state, whereas for a negative trigger, they go back to the previous state. By connecting these bits to the input of the DAC, the output of the DAC is controlled by triggers.

To address the scaling issue, we use a MUX and a voltage multiplier $M$. The MUX and the multiplier are designed, together with a set of amplifiers, such that $s(t)$ is scaled to $z(t)$. A sign bit at the output of the counter, which is a function of the trigger's sign, is used as input to the MUX, which in turn controls the sign of the multiplier's output or $z(t)$'s sign.

To explain the sequences of events in DVG, let us consider our previous scenario where $|y(t)| <\lambda$ for some $t<t_1$ and at $t_1$, $|y(t)|$ crosses $\lambda$. For $t<t_1$, we have $y(t) = y_\lambda(t)$, $s(t) = 0$, $z(t) = 0$, and all the output bits of the counter are set to be zero. If $y(t_1)> \lambda$, Comp-1 triggers a positive voltage, and the counter's output bits state changes. Specifically, the least significant bit changes to one, and in response, the DAC's output voltage changes to $\alpha$ v. Meanwhile, after the positive trigger, the MUX outputs a voltage $-2\lambda/\alpha$ which is multiplied to $s(t)$ and outputs $z(t)$ as $-2\lambda u(t-t_1)$ as desired.

Next, we discuss the hardware board that realizes the folding operation discussed in this section.

\begin{table}[h!]
\centering
\caption{List of Hardware Components}
\label{table:hardware_components}
\begin{tabular}{||c c c||}
 \hline
 Component & Model Number & Make \\
 && \\ \hline
 Comparator & LM339 & Texas Instruments \\
 && \\
 UP/DOWN Counter & TEENSY4.1 & PJRC \\
 && \\

 Analog MUX & ADG1608 & Analog Devices \\
 && \\
 Analog Multiplier & AD835 & Analog Devices \\
 && \\
 Adder & LT1364 & Analog Devices \\
  && \\ [1ex]
\hline
\end{tabular}
\end{table}

\begin{table}[h!]
		\caption{Up/down counter operation.}
	\centering
	\begin{tabular}{||c c c c c c c||}
		\hline
		c & b & a & sgn & Counter values & $s(t)$ & $z(t)$  \\ [0.5ex]
		\hline\hline
		0 & 0 & 0 & 0~(1) & 0~(0) & 0 & 0  \\
		0 & 0 & 1 & 0~(1) & 1~(-1) & 1 & $2\lambda$ ($-2\lambda$)\\
		0 & 1 & 0 & 0~(1) & 2~(-2) & 2 & $4\lambda$ ($-4\lambda$)\\
		0 & 1 & 1 & 0~(1) & 3~(-3) & 3 & $6\lambda$ ($-6\lambda$)\\
		1 & 0 & 0 & 0~(1) & 4~(-3) & 4 & $8\lambda$ ($-8\lambda$)\\

		\hline
	\end{tabular}
	\label{table:counter}
\end{table}

\begin{figure}[!t]
	\centering
      \begin{tabular}{c}

	\subfigure[] {\includegraphics[width= 3.2 in]{Figs/Fig6_1KHz_10Vpp_4Folding_New_Clr.png}}\label{fig:2fold}\\
 \subfigure[] {\includegraphics[width= 3.2 in]{Figs/UDR_4_folds_2KHz.png}}\label{fig:4fold}

 \end{tabular}
 \caption{Screenshots of an oscilloscope capturing input signals (yellow), its folded outputs (green), and the DVG signals (blue): (a) 1kHz sinusoid with maximum amplitude $4\lambda$ and (a) 2kHz sinusoid with maximum amplitude $8\lambda$.}
	\label{Fig:Analysis_of_folding_ability}
\end{figure}

\begin{figure}[!h]
	\centering
	\begin{tabular}{c}
		\subfigure[] {\includegraphics[width=3.2in]{Figs/Fig7_1Folding_6Vpp_1KHz_New_Clr.png}\label{fig:1k_1}} \\
		\subfigure[] {\includegraphics[width=3.2in]{Figs/Fig7_1Folding_6Vpp_10KHz_New_Clr.png}\label{fig:10k_1}} \\
		\subfigure[] {\includegraphics[width=3.2in]{Figs/Fig7_1Folding_6Vpp_20KHz_New_Clr.png}\label{fig:20k_1}}
	\end{tabular}
	\caption{Analysis of frequency response of the modulo hardware (a)-(c) denote the real-time capture of an oscilloscope capturing the 1kHz, 10kHz, 20kHz, respectively, the sinusoidal input signal (yellow), its folded output (green), the DVG signal (blue).}
	\label{Fig:frequency_response}
\end{figure}

\subsection{Modulo Hardware Board}
Our modulo hardware board is presented in Fig.~\ref{Fig:hw_board}, along with the roles of the major building components. Table~\ref{table:hardware_components} contains a detailed listing of the hardware's components. The board is designed for $\lambda = 1.25$ v. While selecting components for the MUX, multiplier, and amplifiers involved, we observe that these components operate in their linear regions if the operating voltages are less than 12 v. This implies that $|z(t)|\leq 12$ v which limits the maximum value of input signal to $|y(t)| < 9\lambda = 11.75$ v. This is because if $y(t)$ crosses $9\lambda$ then $z(t)$ should be $-10\lambda = 12.5$ v to ensure that $y_\lambda = y(t) + z(t) \in [-\lambda, \lambda]$. Hence, the current design of the hardware can fold and sample signals eight times larger than ADC's dynamic range. This implies that the DVG output should take values from the set $\{0, \pm 2\lambda, \pm 4\lambda, \pm 6\lambda, \pm 8\lambda \}$. This requires the DAC to have five uniform voltage levels at its output (it produces only positive voltages), and a  3-bit DAC and hence a 3-bit counter are used as shown in Fig.~\ref{Fig:dcvg}. Instead of using an off-the-shelf DAC, we build a customized DAC for the hardware. By noting the DAC's output is a linear combination of its three input bits, we used adders LT1364 to realize the DAC. In Table~\ref{table:counter}, we list the values of bits and the counter (denoted as counter values). The three bits (a,b, and c) of the counter are used as input to the DAC, which converts the bits to an analog DC voltage. Here the resolution of the DAC is $\alpha = 1$ v.

We further analyze the working of the modulo hardware by considering a sinusoidal signal $y(t) = A\, \sin(2\pi f_0 t)$ where $A$ is amplitude, and $f_0$ is the frequency (in Hz). In this experiment, we set $\lambda = 1.25$. First, we analyze the folding ability of the hardware for different amplitude levels. Figure~\ref{Fig:Analysis_of_folding_ability}(a) and (b) depict screenshots of an oscilloscope capturing input $y(t)$ (in yellow), folded output $y_\lambda(t)$ (in green), and the DVG output $z(t)$ (in blue), for two signals with $f_0 = 1$ kHz, $A = 4\lambda$ and $f_0 = 2$ kHz, $A = 8\lambda$, respectively. We observed that the signals are folded back to lie within the dynamic range of the ADC as expected without clipping.

Next, we discuss the frequency response of the modulo ADC. As in any analog system, the modulo folder's response also depends on the input signal's frequency or bandwidth. In particular, beyond a particular frequency range, components of the hardware and the overall feedback loop may not respond quickly to fast changes in the input signal, as demonstrated in Fig.~\ref{Fig:frequency_response}. We observed that for 1kHz and 10 kHz, the hardware folds the signal accurately. However, for $f_0 = 20$ kHz, folding instants are not symmetric for positive and negative folds.

In the next section, we discuss several challenges of the modulo hardware and our proposed solutions.

\begin{figure}[!t]
	\centering
	\includegraphics[width= 3.2 in]{Figs/mod_td}
	\caption{Effect of the time delay of the feedback loop on the modulo operation.}
	\label{Fig:mod_td}
\end{figure}

\subsection{Artifacts During Folding}
Errors or other artifacts that arise during folding operations in hardware result from various reasons. One of the major issues that arise in a modulo ADC is the time delay in the feedback loop (See Fig.~\ref{Fig:folding}). To elaborate, consider a scenario where $y(t)<\lambda$ for $t<t_1$ and it crosses $\lambda$ at time $t_1$. To fold the output voltage to the dynamic range of the ADC, $z(t) = 2\lambda u(t-t_1)$ needs to be subtracted from $y(t)$. However, there is a finite delay between the trigger time $t_1$ to generating $z(t)$. If the time delay is $T_d$, then $z(t) = 2\lambda u(t-t_1-T_d)$ is subtracted, which causes distortion. To illustrate this effect, in Fig.~\ref{Fig:mod_td}, we considered a sinusoidal signal (in blue) and its folded versions with and without delay. We observe that in the absence of any time delay ($T_d=0$) the signal folds perfectly (shown in red) to stay within the dynamic range. However, for a non-zero value of $T_d$, foldings do not take place at the folding instants, and the output of the modulo operator (shown in black) still remains outside the dynamic range $[-\lambda, \lambda]$, which results in a clipped modulo operator output. The proposed hardware solution addresses this issue and avoids the undesired clipping as shown in Figs.~\ref{Fig:Analysis_of_folding_ability} and \ref{Fig:frequency_response}.

Our solution uses the fact that with a finite time delay, the amount of overshoot of a smooth signal can be bounded. To elaborate, assume that the signal that undergoes the modulo operation is Lipschitz continuous. Specifically, a signal $y(t)$ is Lipschitz continuous if there exists a positive real number $\mathrm{L}_y$ such that for any $T>0$ we have
\begin{align}
    |y(t) -y(t+T)|\leq \mathrm{L}_y\, T.
    \label{eq:lipschitz}
\end{align}
With the Lipschitz smoothness condition, we note that the amplitude of $y(t)$ can not change more than $\mathrm{L}_y\, T_d$ between any folding instant and time of its effect to take place. Hence, if we choose the dynamic range of the ADC to be $[-(\lambda+\Delta \lambda), (\lambda+\Delta \lambda)]$ where $\Delta \lambda = \mathrm{L}_y\, T_d$ then the signal will not clip. We show this extended dynamic region in the example in Fig.~\ref{Fig:mod_td}. Alternatively, instead of increasing the ADC's dynamic range, one can keep it to be $[-\lambda, \lambda]$ and reduce the threshold values for comparators. In this case, Comp-1 will trigger when the input crosses $\lambda-\Delta \lambda$, and Comp-2 will trigger when the input goes beyond $-\lambda+\Delta \lambda$. In this way, the time delay issue is addressed by the modulo circuit without altering ADC's dynamic range. In our hardware, we choose the former solution. Specifically, we used an oscilloscope to measure and display samples. The dynamic range of the oscilloscope's ADC was sufficiently higher than $[-\lambda, \lambda]$ to sample signals of interest without clipping signals due to the delay in the feedback loop.

In order to apply the solution, the signal must be Lipschitz continuous. In our design, the modulo operation input signal is always a bandlimited signal satisfying the Lipschitz smoothness condition \cite{bl_bound}. For a bandlimited signal $y(t)$, its Lipschitz constant $\mathrm{L}_y$ is directly proportional to its bandwidth $\omega_c$ \cite{bl_bound}. Hence, for a given value $\Delta \lambda$ and $T_d$ (both depend on the modulo circuit), $\mathrm{L}_y = \Delta \lambda/T_d$ is fixed and this restricts the maximum frequency of the input signal that can be faithfully folded. In the current design, we choose to implement the counter management using a TEENSY microcontroller, resulting in a $1 \mu$s time delay. Then for a sinusoidal signal $y(t) = A \sin(2\pi f_0 t)$, the Lipschitz constant is given as $L_y = 2\pi A f_0$. For $A = 8\lambda$, $\Delta \lambda = 0.5 \lambda$, and $T_d = 1 \mu$s, we note that the maximum operating frequency is 10 kHz which is in line with the experimental results discussed in Fig. \ref{Fig:frequency_response}.

\section{Results}
In this section, we demonstrate the modulo hardware's signal reconstruction capability. We focus on the folding and reconstruction of bandlimited and FRI signals. In the hardware, the folded measurements are generally  contaminated by different noises, including quantization noise. Since the performance of an unfolding algorithm depends on the noise levels, we first discuss a few simulated results to assess the performance of the $B^2R^2$ algorithm used for unfolding. Then we demonstrate the results from the hardware.

\begin{figure}[!t]
	\centering
	\includegraphics[width= 2.5 in]{Figs/quantization.png}
	\caption{Comparison of HOD, CPF, and $B^2R^2$ algorithms after the quantization process in terms of MSE when recovering a bandlimited signal from modulo samples with $\lambda = 1.25$ and OF = 3,6. For a given number of bits, $B^2R^2$ has the lowest MSE.}
	\label{Fig:quantization}
\end{figure}

\begin{figure}[!t]
	\centering
	\includegraphics[width= 2.5 in]{Figs/Gaussian.png}
	\caption{Comparison of HOD, CPF and $B^2R^2$ algorithms (with unbounded noise) in terms of MSE when recovering a bandlimited signal from modulo samples with  $\lambda$ = 1.25 and OF = 3,6. For a given SNR and OF, $B^2R^2$ has the lowest MSE.}
	\label{Fig:unbounded}
\end{figure}
\subsection{Simulated Results}
In this section, we compare our $B^2R^2$ algorithm with the \emph{higher-order differences} (HOD) approach \cite{unlimited_sampling17, uls_tsp} and \emph{Chebyshev polynomial filter}-based (CPF) method \cite{uls_romonov}. Although a comparison of these methods is analyzed in \cite{eyar_moduloicassp}, the settings are different here. Importantly, quantization noise is not considered in our previous work.

We consider the noisy measurements as
\begin{align}
            \tilde{y}_{\lambda}(n T_s) = {y}_{\lambda}(n T_s) + v(n T_s),
        \label{eq: noisy_samples}
        \end{align}
where $v(n T_s)$ is the noise term. In the simulations, $\lambda$ is set to be $1.25$ as in the hardware. We normalize the bandlimited signals to have a maximum amplitude of $10$. The SNR is calculated as $\text{SNR} = 20 \log\left(\frac{||y_{\lambda}(n T_s)||}{||v(n T_s)||}\right)$. Reconstruction accuracies of different methods are compared in terms of the normalized mean-squared errors (MSEs) as $ \frac{\sum |y(nT_s) - \hat{y}(n Ts)|^2}{\sum |y(nT_s)|^2}$, where $\hat{y}(n T_s)$ is an estimate of $y(n T_s)$. For different noise settings and over-sampling factors (OFs), we considered 100 independent noise realizations and calculated the average MSE for them. We first consider quantization noise and then present results for unbounded noise.
\begin{figure}[!t]
    \centering
    \includegraphics[width=0.3\textwidth]{Figs/SignalGenerator.png}
    \caption{Bandlimited signal generator.}
    \label{fig:UDRSignalGen}
\end{figure}

 In the first simulation, the unfolding algorithms are applied to quantized folded samples. The MSE in the estimation of bandlimited signals for a different number of bits and OFs is shown in Fig. ~\ref{Fig:quantization}. We observe that for a given $\text{OF}$, $B^2R^2$ algorithm results in the lowest MSE for less than 5 bits. For more than five bits, all the algorithms, except HOD with OF = 3, perform equally well. The results show that low-resolution quantizers can be used with the $B^2R^2$ algorithm for unfolding, which saves both power and memory requirements.

Next, for unbounded noise, we assume that the noise samples $v(nT_s)$ are independent and identically distributed Gaussian random variables with zero means. The variance of $v(nT_s)$ is set to achieve the desired SNR. We compare the methods for different values of SNR and OFs with $\lambda = 1.25$. Fig.~\ref{Fig:unbounded} shows the MSE of the different algorithms for OF $= 3$ and $6$. We note that our algorithm results in the lowest error for a given OF and SNR.

Given the advantages of the $B^2R^2$ algorithm over the other approaches, we present the hardware results in the next section by using this method.

\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[]{\includegraphics[width=3.2in]{Figs/BL1_scope_11_Clr.png}\label{fig:BL1_scope}} \\
		\subfigure[]{\includegraphics[width=3.2in]{Figs/BL2_scope_13_Clr.png}\label{fig:BL2_scope}}
	\end{tabular}
	\caption{Screenshots of the oscilloscope capturing the bandlimited input signals (yellow) and its folded output signals (green).}
	\label{fig:BL_scopeex1}
\end{figure}
\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[]{\includegraphics[width=3.2in]{Figs/BL1_rec.png}\label{fig:BL1}} \\
		\subfigure[]{\includegraphics[width=3.2in]{Figs/BL2_rec.png}\label{fig:BL2}}
	\end{tabular}
	\caption{Hardware results for bandlimited signals. The $B^2R^2$ algorithm is used to unfold $y_\lambda(t)$ (measured at the output of hardware), and the unfolded signal $\hat{y}(t)$ is plotted with bandlimited signal $y(t)$.}
	\label{fig:BL_ex1}
\end{figure}

\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[Screenshot of the oscilloscope capturing filtered FRI signal (yellow), its folded output (green), and the DVG signal (blue).] {\includegraphics[width=3.2in]{Figs/FRI1_1_Clr.png}\label{fig:FRI1_1k}} \\
		\subfigure[Filtered FRI signal with its folded and unfolded versions.]{\includegraphics[width=3.2in]{Figs/Ex1_lpf.pdf}\label{fig:FRI_LPF1}}\\
		\subfigure[FRI signal reconstruction.] {\includegraphics[width=3.2in]{Figs/Ex1_fri.pdf}\label{fig:FRI1_REC}} \\

	\end{tabular}
	\caption{Reconstruction of FRI signal ($L=2$) via the modulo hardware.}
	\label{Fig:FRI1}
\end{figure}

\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[Screenshot of the oscilloscope capturing filtered FRI signal (yellow), its folded output (green), and the DVG signal (blue).] {\includegraphics[width=3.2in]{Figs/FRI2_1_Clr.png}\label{fig:FRI2_1k}} \\
		\subfigure[Filtered FRI signal with its folded and unfolded versions.]{\includegraphics[width=3.2in]{Figs/Ex2_lpf.pdf}\label{fig:FRI_LPF2}}\\
		\subfigure[FRI signal reconstruction.] {\includegraphics[width=3.2in]{Figs/Ex2_fri.pdf}\label{fig:FRI2_REC}} \\
	\end{tabular}
	\caption{Reconstruction of FRI signal ($L=3$) via the modulo hardware.}
	\label{Fig:FRI2}
\end{figure}

\begin{figure}[!t]
	\centering
	\begin{tabular}{c}
		\subfigure[Screenshot of the oscilloscope capturing filtered FRI signal (yellow), its folded output (green), and the DVG signal (blue).] {\includegraphics[width=3.2in]{Figs/FRI3_1_Clr.png}\label{fig:FRI3_1k}} \\
		\subfigure[Filtered FRI signal with its folded and unfolded versions.]{\includegraphics[width=3.2in]{Figs/Ex3_lpf.pdf}\label{fig:FRI_LPF3}}\\
		\subfigure[FRI signal reconstruction.] {\includegraphics[width=3.2in]{Figs/Ex3_fri.pdf}\label{fig:FRI3_REC}} \\

	\end{tabular}
	\caption{Reconstruction of FRI signal ($L=5$) via the modulo hardware.}
	\label{Fig:FRI3}
\end{figure}

\subsection{Hardware Results for Bandlimited Signals}
In this section, we first present results for bandlimited signals. For generating bandlimited or lowpass signals, we used an Arduino microcontroller (See Fig.~\ref{fig:UDRSignalGen}) which converts the digital signal to an analog signal via a DAC. The digital signals were generated using MATLAB software. Two examples of 1khz bandlimited signal are presented in Fig. \ref{fig:BL1_scope} and Fig. \ref{fig:BL2_scope}. The modulo hardware folds the signals to stay within the dynamic range, as shown in Fig.~\ref{fig:BL_scopeex1}. The signals are sampled with an oversampling factor of five ($\text{OF}=5$), and the $B^2R^2$ algorithm is applied for unfolding. The unfolded or reconstructed signals are shown in Fig.~\ref{fig:BL_ex1}. We observe that the reconstruction is close to the true signals except for an amplitude scaling factor, which is the result of scaling within the hardware.

\subsection{Hardware Results for FRI Signals}
Before presenting the results for FRI signals, we briefly discuss the FRI signal model and its sampling and reconstruction mechanism for ease of discussion.
Consider an FRI signal consisting of a stream of $L$ pulses:
\begin{align}
	f(t) = \sum_{\ell=1}^L a_\ell h(t-t_\ell),
	\label{eq:fri1}
\end{align}
where the pulse $h(t)$ a real-valued known pulse. We assume that $\{a_\ell\}_{\ell = 1}^L$ are real-valued and $\{t_\ell\}_{\ell = 1}^L \subset (0, T_0] \subset \mathbb{R}$ for a known $T_0$.

The FRI signal model in \eqref{eq:fri1} is encountered in several scientific applications such as radar imaging \cite{bar_radar, bajwa_radar, sunil}, ultrasound imaging \cite{eldar_sos,eldar_beamforming,mulleti_icip}, light detection and ranging (LIDAR) \cite{castorena_lidar}, time-domain optical coherence tomography (TDOCT) \cite{blu_oct}, and other time-of-flight imaging systems. In these applications,  $h(t)$ is the transmitted pulse and $\{a_\ell \,h(t-t_\ell)\}_{\ell=1}^{L}$ constitute the reflections from $L$ point targets. The amplitudes $\{a_\ell\}_{\ell = 1}^L$ depend on the sizes of the targets and the delays $\{t_\ell\}_{\ell = 1}^L$ are proportional to the distances of the targets from the transmitter. Here $T_0$ denotes the maximum time delay of the targets. The signal $f(t)$ is specified by $\{a_\ell, t_\ell\}_{\ell=1}^L$ and can be reconstructed from its sub-Nyquist measurements acquired using an appropriate sampling kernel \cite{vetterli,eldar_sos,fri_strang, mulleti_kernal}. Given their widespread application, here we consider sampling and reconstruction of FRI signals by using our hardware prototype.

FRI signals can be perfectly reconstructed by applying high-resolution spectral estimation methods, such as the annihilating filter (AF) or Prony's method and its variants
\cite{prony, plonka, schmidt_music, barabell_rmusic, bdrao_rmusic,sarkar_mp,paulraj_esprit} to the Fourier measurements
\begin{align}
	S(k\omega_0) = \frac{F(k\omega_0)}{H(k\omega_0)} =  \sum_{\ell = 1}^L a_\ell \, e^{-\mathrm{j}k\omega_0 t_\ell}, \, k \in \{-K, \cdots, K\},
	\label{eq:Skomega}
\end{align}
where we assume that $H(k \omega_0) \neq 0$. Here $K \geq L$ and $\omega_0 = \frac{2\pi}{T_0}$ \cite{eldar_2015sampling}. The Fourier measurements $\{S(k\omega_0)\}_{k =-K}^K$ can be determined from the samples $(f*g)(nT_s)$ where $g(t)$ is an ideal lowpass filter with bandwidth $[-K\omega_0, K \omega_0]$ and $T_s = \frac{2\pi}{(2K+1)\omega_0}$. In practice, the duration of the pulse $h(t)$ is very short, and hence $f(t)$ has a wide bandwidth. This results in a large sampling rate (or Nyquist rate) if $f(t)$ is sampled directly. However, the filtered signal $y(t) = (f*g)(t)$ is bandlimited to $[-K\omega_0, K \omega_0]$, which is much smaller than that of $h(t)$ and the sampling rate is much lower than the Nyquist rate.

As in the bandlimited signal model, a modulo operation can be applied to the filtered signal $y(t)$ to avoid clipping. Then $y_\lambda(t)$ is sampled. Then to determine the Fourier samples $\{S(k\omega_0)\}_{k =-K}^K$, unfolding is first applied. Since the filtered signal is bandlimited, we use the proposed hardware for modulo folding and can apply the $B^2R^2$ algorithm from unfolding.

In our setup, to generate the FRI signals, we consider $h(t)$ to be a short pulse of bandwidth 30kHz (Nyquist rate = 60kHz). We consider three examples with $L=2, 3,$ and 5. The amplitudes and time delays are generated randomly. The maximum time delay is $T_0 = 0.1$ sec. Once generated, the FRI signal is lowpass filtered with a cutoff frequency of 1kHz. MATLAB is used to generate the samples of filtered FRI signals and then an Arduino microcontroller is used to generate the analog counterpart of them. The signal is then folded using the hardware, and the folded signals are sampled. The sampling rate is 10kHz which is five times higher than the sampling rate of the lowpass signal. Still, the rate is six times lower than the Nyquist rate, and hence the system operates at a sub-Nyquist rate.

We first applied the $B^2R^2$ algorithm to unfold the signal and then used ESPRIT \cite{paulraj_esprit} to estimate the time delays and amplitudes of the FRI signals.
In Fig.~\ref{Fig:FRI1}, Fig.~\ref{Fig:FRI2} and  Fig.~\ref{Fig:FRI3} we show sampling and reconstruction of FRI signals with $L=2,3,5$ respectively.
The FRI signals followed by a lowpass filter are presented in Fig.~\ref{fig:FRI1_1k}, Fig.~\ref{fig:FRI2_1k}, and  Fig.~\ref{fig:FRI3_1k}.
The reconstruction of the lowpass signals displayed in Fig.~\ref{fig:FRI_LPF1}, Fig.~\ref{fig:FRI_LPF2} and  Fig.~\ref{fig:FRI_LPF3}, where $y(t)$ described the LPF output, $y_\lambda(t)$ is the folded signal (output of the modulo hardware), and the unfolded signals are given by $\hat{y}(t)$. Fig.~\ref{fig:FRI1_REC}, Fig.~\ref{fig:FRI2_REC} and Fig.~\ref{fig:FRI3_REC} show location and amplitude of the true signal $f(t)$ and estimated FRI signal $\hat{f}(t)$.
The maximum error in the estimation of time delay is $-15$ dB which shows that the system can be used in applications like radar and ultrasound imaging.

\section{Conclusions}
 We presented a hardware prototype for the modulo folding system and showed that for different bandlimited and FRI signals, the hardware is able to fold the signal faithfully. In particular, we were able to sample signals with 8 times the dynamic range of the ADC roughly. We also  addressed the time delay issue of the modulo system and presented a hardware solution. The overall system operates five times below the Nyquist rate, which enables one to use low-rate, low-dynamic range, power-efficient ADCs.

\bibliographystyle{IEEEtran}

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