We welcome you, brave Writer, no matter where you are in your writing journey!
Are you finding space in your busy schedule and in your heart to let your pen free on the page for the first time?
Are looking for a community of writers to strengthen your weekly practice?
Are you already part of the Life in 10 family?
Life in 10 Minutes Writing Series are two hour sessions that meet over the course of six sessions. Classes range in size from six to thirteen students. We welcome writers of all ages, experience levels and walks of life.
The most empowering thing a person can do is to reclaim the story of their life. We carry shame and fear that the world will discover the truth - we've experienced pain, we've made mistakes, we are faking it a lot of the time. The truth is that none of us are born with an instruction manual and NO ONE knows what the hell they are doing.
If you have decided you want to stop hiding, stop pretending, and take back your power then ReStory is your gateway.
Learn to tell a great story; to find humor, lessons, and meaning in the challenging experiences of your life. You will connect with other creative people and a nurturing instructor in a safe environment. At the end you will stand-up to share your unique and important perspective with your classmates and invited guests. Each participant will prepare a 5 minute piece to be shared at the final performance.
Your story belongs to you. It has the power to change the world. Learn to tell it in a way that makes you feel proud of who you are and of all you've overcome.
Read more about Erin Mahone.
Writers are thieves--of their own lives. Learn how to tap into your experiences, memories and flashes of insight to jump start that novel, short story, poem, memoir blog or creative journal that's been lurking beneath the surface. In these "writing from life" workshops, we'll explore how to access the right side of the brain, side-step writer's block and get all of our words, thoughts and ideas onto the page, determining the genre only after the essential words have been written. Join me for a 6 week series of reading, writing and sharing work aloud in class, that will result in your own portfolio of raw material, fresh ideas and beginnings that beg for your return. Please bring a journal and pen or pencil as we write by hand. Coffee and tea provided!
Learn more about Cindy Cunningham.
In this class, we will massage the knots and unravel the tales traveling through your head. We will explore memory, character, dialogue and plot, with writing exercise and group discussions that will inspire you to get your story down onto the page. This class is open to all levels of writers, including those who have always wanted to write but never had the time.
Read more about Sadeqa Johnson.
Learn more about Valley Haggard.
Life in 10 Minutes Workshops are single day classes of varying duration. Classes range in size from six to thirteen students. We welcome writers of all ages, experience levels and walks of life.
Saturday, May 11th from 10am-1pm.
What places have shaped you as person? Where do you go to feed your true self? In this three-hour workshop we'll bring place to the forefront of our writing. We'll look at examples of memoirs and personal essays that successfully bring the physical world alive and practice going deeper into place in our own writing. This class is open to all experience levels and will involve a combination of close-readings of book excerpts and essays, discussion, and three guided writing exercises.
Read more about Elizabeth Ferris.
Friday, May 17th from 1pm-4pm.
Explore the healing process of transforming the raw material of your life into essay, lyric, poetry and prose.
Whether you're a long time writer, a brand spankin' new writer, or have lost writing and long for its return, Skip the Small Talk mini-marathons will provide you with a compassionate and gentle shove in the write direction.
These workshops are designed for female identifying writers who want to jump-start their writing process, get real, and go deep.
Skip the small talk, and join me for one or all Friday afternoon workshops this winter + spring!
Read more about Valley Haggard.
Saturday, May 25th from 10am-3pm.
Carving out the time and space we need to slow down and listen to our wants, needs, and the voice of our inner wisdom can be challenging at best. In this self-care workshop for women we will pamper ourselves through writing, meditation, divination and Reiki practices designed to free up energy and begin truly loving ourselves. We will create our own mantras and practice simple writing rituals to help center our hearts and our minds, assembling a full tool kit of self-care practices to take back into our busy lives.
Saturday, June 15th from 10am-1pm.
Have you always been fascinated with the idea of meditation but not sure where to start? Do you love to write but can't seem to get your thoughts on the page? In this class, we will explore the benefits of meditation, learn to meditate, and then explore the craft of writing with a deeper and clearer mind. Open to all.
Learn more about Sadeqa Johnson.
What elevates good writing into great writing? Concrete, significant details (CSDs.) In this three-hour workshop, we'll explore ways that you can fine-tune your writing through a focus on the specific. We'll look at examples of writing that capture the essence of CSDs and you will create your own significant details. You may choose to write nonfiction, poetry, or fiction (or a combination.) This class is open to all experience levels and will involve a combination of readings, discussion, and guided writing exercises.
Life in 10 Minutes Intensives are four session class series that are smaller in size, and condensed into a two week immersive experience. These classes are designed to delve deeply into their topics in an intimate classroom setting. Classes range in size from two to four students. We welcome writers of all ages, experience levels and walks of life.
June 17 & 18 and 24 & 25, 7-9pm .
Albert Camus famously called fiction, "the lie through which we tell the truth." In this 4-session intensive we'll take a deep dive into the world of fiction writing and explore how "lying" on the page can actually work to bring reality into sharper focus. We'll explore questions of craft and theme through a combination of close readings of short stories and novel excerpts, discussion, and workshopping of our own material. This class is ideally suited to beginning fiction writers and fiction-curious writers, as well as practiced fiction writers who are looking for new perspective on their work.
Because this is an intensive designed to maximize writers' exposure to the topic, some outside "homework" will be required. Outside work will not exceed one hour per session (for a total of 4 hours), and the instructor will provide all reading materials. During the second week of instruction, students will also have the opportunity to workshop a piece of writing for feedback from their instructor and classmates.


First, there is no one-size-fits-all policy for technology. The use of technology by companies is so varied—and the risks are so different—that a universal policy would ultimately cost you far more than needed. To deal with this, Southern Insurance Group of Texarkana focuses on solutions that are specifically tailored to your company's needs, helping to keep costs low while still providing your business with adequate protection.


Ionutzsteaua was a citizen of Romania.
He served one term as mayor of Baia Mare. He then moved to Ireland during the Victor Petrescu regime and served as mayor of Dublin. Ionutzsteaua was party president of Partidul Democrat and he was a member of eUniunea Gamerilor Democrati.
This page was last edited on 2 November 2015, at 19:06.


text:
\section{Introduction}\label{1_sec_introduction}

\IEEEPARstart{F}{ield-programmable} gate arrays (FPGAs) have become popular and been widely applied in various fields, such as communication, computation, deep learning, and digital signal processing, due to its configurability, fast development-cycles, and abundant resources. Because of the low-latency and low-power features, FPGAs also play an important role in highly real-time and embedded systems. With widespread applications, the security issues of the FPGAs are gaining more and more focus.
Since the function of the FPGA is fully determined by the bitstream used to configure the FPGA, it is possible to retrieve the design details of the circuit implemented in FPGA by reverse engineering the bitstream.

This paper focuses on the reverse analysis of circuit design function. Detecting known function blocks from the circuit design can play the role of pre-analysis and offer assistance to the analysis of the circuit's system function. After the function blocks are detected, the system function implemented on the circuit can be further found out.

We take the scenario shown in Fig.~\ref{fig1} as an example to demonstrate that FPGA function block detection helps analyze the circuit's system function.
In this scenario, circuit's system function refers to the application algorithm implemented on FPGA and the application algorithm contains different kinds of function blocks.
After bitstream access, function blocks contained in the application algorithm can be identified through FPGA function block detection from the bitstream. Then, the application algorithm can be found out or narrowed down to several candidates.

\begin{figure}[!t
\centerline{\includegraphics[width=3.5in]{fig1.pdf}}
\caption{For instance, an application scenario demonstrates that FPGA function block detection helps analyze the circuit's system function.}
\label{fig1}
\end{figure}

To identify the function blocks in FPGA designs,
researchers in~\cite{Ziener_FPL2006},~\cite{Couch_HOST2016} analyzed bitstreams or netlists, partitioned circuits, and compared the content of the partitioned circuits from bitstreams or netlists with existing designs using conventional algorithms.
However, the partitioning process is time-consuming and the imperfect partitioning can lead to incorrect matching results. Features for conventional algorithms need to be designed manually, and improperly selected features result in the performance degradation of conventional algorithms.
Deep neural networks (DNNs) have been used to classify arithmetic operator modules in circuits~\cite{Dai_HOST2017},~\cite{Fayyazi_DATE2019},~\cite{Mahmood_ICCE_Berlin2019}, due to its good performance, strong ability to learn from large amounts of data, and the advantage of no manually designing features.
Dai \emph{et al.}~\cite{Dai_HOST2017} and Fayyazi \emph{et al.}~\cite{Fayyazi_DATE2019} classified arithmetic operators from gate-level circuits, which requires the bitstream to be reverse engineered first.
Mahmood \emph{et al.}~\cite{Mahmood_ICCE_Berlin2019} classified arithmetic operators from partial bitstreams. However, the work in~\cite{Mahmood_ICCE_Berlin2019} lacks the processing of raw bitstream data and could only classify the circuit containing one hardware module.

Inspired by the work mentioned above, the goal of this paper is to detect one or more than one function block in the FPGA circuit design from a given complete bitstream by making use of the latest deep learning research results.
Since more than one function block is to be detected at the same time, object detection networks are used in this paper instead of the classification networks similar to the ones mentioned above.
Because of the discontinuity of the configuration bits for one element and the high degree of redundancy of configuration information, the raw bitstream data should be pre-processed.
Therefore, an effective representation of bitstream should be proposed so that DNN can make full use of its feature extraction capability.

In this paper, we propose an FPGA function block detection method based on deep learning using an image-coded representation of bitstream.
For the purpose of improving the detection accuracy and compressing the size of the dataset, the representation should reflect the adjacency of the programmable logic and remove the useless information.
The approaches taken are: 1) finding the mapping relationship between the configurable logic block (CLB) elements and the configuration bits, and 2) using only configuration bits of CLBs for representation.
Then, the bitstreams are transformed into images by the proposed representation and the deep learning techniques are applied by training an innovative object detection algorithm on the images.
Researchers~\cite{Liu_TC2019} have implemented a variety of application-specific encryption algorithms containing different cryptographic operators, such as Advanced Encryption Standard (AES), Secure Hashing Algorithm 1 (SHA-1), Message Digest Algorithm 4 (MD4), and so on, on FPGA devices. Our work takes the cryptographic operator detection as an example to verify the methodology. In summary, the main contributions of this paper include:
\begin{itemize}
\item A three-channel color image-coded representation of bitstream suitable for deep learning processing is proposed by analyzing the mapping relationship between the configuration bits and CLB elements.
\item A dataset, in which the images are transformed from bitstream files containing 10 kinds of cryptographic operators, is generated without manual annotation.
\item The deep learning techniques are applied to FPGA function block detection from bitstream for the first time by training a deep learning-based object detection algorithm on the dataset.
    The mean Average Precision (mAP) reaches 97.72\% for 10 kinds of function blocks when Intersection over Union (IoU) is 0.5.

\end{itemize}

The rest of the paper is organized as follows: Sec.~\ref{2_sec_background} briefly describes the background of FPGAs and deep learning-based object detection algorithms. Sec.~\ref{3_sec_Methodology} firstly introduces the overall process of the detection method and then describes each step of the method in details. The experimental results are presented in Sec.~\ref{4_sec_Experimental_results}. Sec.~\ref{5_sec_related_works} discusses the related work and Sec.~\ref{6_sec_conclusions} summarizes the findings.

\section{Background}\label{2_sec_background}
In this section, the basic knowledge of FPGAs and function block detection is presented at first (Sec.~\ref{2_1_background_FPGA}). Then, the background of deep learning and object detection algorithms is introduced (Sec.~\ref{2_2_background_deeplearning}).

\subsection{FPGA and Function Block Detection}\label{2_1_background_FPGA}

\textbf{FPGA.} FPGAs are widely applied in digital designs. Compared to application-specific integrated circuits (ASICs), FPGAs have the advantages of reconfigurability and flexibility, which bring about lower costs and shorter development time. There are several kinds of FPGAs, such as static random-access memory (SRAM) FPGA, flash memory FPGA, and anti-fuse FPGA. Although flash memory FPGA and anti-fuse FPGA have higher security over SRAM FPGA, these kinds of FPGAs have a more complex process and limited writing times. SRAM FPGA occupies the main market and is more widely applied in daily life than the other kinds of FPGAs.

With the increase of application demand, more and more resources are integrated into FPGAs. For example, Xilinx Zynq-7000 SoC includes embedded microprocessors in the FPGA system. Xilinx SoC usually consists of the processing system, programmable logic, and many other features all in one silicon chip. The processing system includes microprocessors, interconnection interface, external memory interface, and so on. The programmable logic includes CLBs, Input/Output Blocks (IOBs), Block RAMs (BRAMs), Digital Signal Processors (DSPs), and others. CLB resources are the logical resources for realizing combinational logic circuits and sequential logic circuits. A CLB element contains Look Up Tables (LUTs) and Flip-Flops (FFs). Switch Matrix connects the CLB to the other resources, allowing flexible wiring. CLBs are arrayed into a two-dimensional matrix in the programmable logic. BRAMs are used for dense storage, and DSPs are used for high-speed computing.

\textbf{Bitstream.} An FPGA bitstream is a binary file that contains configuration information for an FPGA design. In SRAM FPGAs, the bitstream is placed in external non-volatile memory. The programming process of an FPGA is to load a bitstream file into the FPGA. The reconfigurability of FPGA benefits from the bitstream file. However, the bitstream also brings about lots of security issues for FPGAs. There are many FPGA vendors providing bitstream encryption for FPGAs to improve the confidentiality of the bitstream.

\textbf{FPGA security.} Since the security of the processing system in FPGA corresponds to processor security, FPGA security here focuses on the security of programmable logic in the FPGA. Compared to ASICs, FPGAs are more vulnerable to be attacked because of the binary file used to configure the FPGA design. FPGA security threats include cloning, overbuilding, reverse engineering, tampering, spoofing, and so on. These FPGA security threats may lead to intellectual property (IP) theft, circuit design leakage, privacy issues, and even FPGA system damage.

The reverse engineering of FPGAs refers to analyzing the bitstream format and transforming the bitstream to the netlist~\cite{Quadir_2016_survey}. The netlist contains the components and connection information among the components. The reverse engineering of FPGAs consists of the following several steps: bitstream access, bitstream decryption~\cite{Moradi_CCS2011},~\cite{Tajik_CCS2017},~\cite{Ender_USENIXsecurity2020}, and bitstream reverse engineering~\cite{note_FPGA2008_bitstream},~\cite{Benz_FPL2012},~\cite{DING_2013_NCD},~\cite{Zhang_Access_2019}. The bitstream access and bitstream decryption are not the focus of this paper.

\textbf{Function block detection.} In this paper, a function block in the FPGA system design refers to a circuit block implementing a complex function, such as a cryptographic operator like SHA-1. A function block is more complex and occupies more hardware resources than a simple hardware module, such as an adder module or a multiplication module. Function block detection should not only pick out one or more than one function block from the FPGA design but also point out the locations of the function blocks in the FPGA device diagram. However, classification can only give one prediction result for one test sample. Therefore, function block detection means partition first, then classification for the partitioned sample. Function block detection plays a role of pre-analysis in the analysis of the circuit's system function.

\subsection{Deep Learning and Object Detection Algorithms }\label{2_2_background_deeplearning}

\textbf{Deep learning.} Deep learning has become a popular research field with many applications, such as image processing, speech recognition, medical diagnosis, unmanned ground vehicle, and so on. Deep learning makes it needless to design features manually because deep learning extracts high-level, abstract features from raw data by several layers~\cite{goodfellow_2016_deeplearning}. Convolutional neural networks (CNNs) and recurrent neural networks (RNNs) are popular DNNs, which are widely used in various fields. The deep learning model learns lots of experience from a large dataset. This process of learning is called training, and this dataset is called a training set. After training, the performance of the deep learning model is usually tested in another dataset, which is called a test set.

\textbf{CNN.} CNNs are one of the most important deep learning networks which gain great success in many applications. CNNs are a kind of DNN with at least one convolution layer, which uses convolution calculation instead of general matrix multiplication. CNNs usually consist of convolution layers, pooling layers, fully connected layers, and so on. Because of the convolution calculation, CNNs are able to extract local features of the image and have fewer parameters than fully connected neural networks. Therefore, CNNs achieve a quite good performance in two-dimensional image applications.

\textbf{Object detection.} The function of object detection algorithms is to find the location of the interesting objects in an image and to give a classification probability for each object. Object detection algorithms generally fall into two categories: conventional methods based on manually designing features and deep learning-based methods. Deep learning-based methods do not need specifically defined features and have been developed with good performance. To date, there are two groups of deep learning-based object detection algorithms. One is two-stage object detection algorithms based on region proposal and classification, such as R-CNN~\cite{Girshick_CVPR_2014_RCNN}, Fast R-CNN~\cite{Girshick_ICCV_2015_FastRCNN}, and Faster R-CNN~\cite{Ren_NIPS2015_FasterRCNN}. The other one is one-stage object detection algorithms based on regression, such as You Only Look Once (YOLO)~\cite{Redmon_CVPR2016_YOLOv1},~\cite{Redmon_CVPR2017_YOLOv2},~\cite{Redmon_YOLOv3_2018}, and Single Shot MultiBox Detector (SSD)~\cite{Liu_ECCV2016_SSD}. The biggest advantage of the one-stage object detection algorithms is the fast detecting speed with the necessary accuracy.

Some of the function blocks occupy a small part of the whole image transformed from the bitstream by the image-coded representation, and sometimes there is more than one function block in an image. Considering the characteristics of the function blocks in the image, object detection algorithms are more suitable for our work than other kinds of algorithms, such as the classification algorithms. Classification algorithms cannot work on the bitstreams containing more than one function block, because classification algorithms can only classify one category for each image.

Object detection is widely applied in various fields, such as face detection, object tracking, security, unmanned vehicle, robot, and so on. However, it has never been applied to FPGA function block detection. Our work combines the image-coded representation of bitstream and an object detection algorithm based on deep learning to realize the detection of function blocks in the FPGA bitstreams for the first time.

\textbf{YOLO.} YOLO is the first deep learning-based object detection algorithm with the idea of end-to-end training~\cite{Redmon_CVPR2016_YOLOv1}, which means YOLO does not have the process of region proposal and uses a single network. The object detection problem is regarded as a regression problem. YOLO extracts the features from images and predicts the location information of the bounding boxes and class probability directly. Compared to two-stage object detection algorithms, YOLO greatly improves the running speed and has better generalization ability. With the development of YOLOv1~\cite{Redmon_CVPR2016_YOLOv1}, YOLOv2~\cite{Redmon_CVPR2017_YOLOv2}, and YOLOv3~\cite{Redmon_YOLOv3_2018}, YOLO has significantly improved the speed, detection class number, location accuracy, and accuracy on small objects. From YOLOv2, YOLO uses convolution layers instead of the last fully connected layer and takes multi-scale training so that multi-scale input images can be predicted by the same network. Among various deep learning-based object detection algorithms, YOLOv3~\cite{Redmon_YOLOv3_2018} is the network with the best comprehensive performance since YOLOv3 achieves high accuracy and fast speed at the same time.

\textbf{SSD.} SSD~\cite{Liu_ECCV2016_SSD} is another classical one-stage deep learning-based object detection algorithm, which is also based on the idea of end-to-end training. SSD is able to detect multi-scale objects by computing the results from multiple feature maps with different sizes. The speed and accuracy of SSD are higher than YOLOv1 when SSD was presented. However, the performance of SSD is soon exceeded by YOLOv2 and YOLOv3.

\section{Methodology}\label{3_sec_Methodology}

\subsection{Overview}\label{3_1_overview}

The process of function block detection consists of the following steps, as is shown in Fig.~\ref{fig2}. First of all, the analysis of the FPGA bitstream format is carried out and the mapping relationship used for the representation of bitstream is found. Secondly, a large number of bitstreams are transformed into images by the image-coded representation of bitstream, and a dataset containing a lot of images is generated without manual annotation. Then, a process of deep learning training is carried out and a model with good performance is obtained. When testing, an FPGA bitstream should be transformed into an image, which passes through the deep network later. At last, the detection result is obtained. The process of dataset generation, deep learning training and testing could be implemented by scripts automatically. The rest of this section will describe each step in detail.

\begin{figure}[!t
\centerline{\includegraphics[width=3.5in]{fig2.pdf}
\caption{The process of function block detection method consisting of bitstream format analysis, image-coded representation of bitstream, dataset generation, deep learning training, and deep learning inference. }
\label{fig2}
\end{figure}

\subsection{Bitstream Format Analysis}\label{3_2_sec_bitstream_format_analysis}

The components of FPGAs are described in Sec.~\ref{2_1_background_FPGA}. The bitstream files are used to configure the programmable logic. The programmable logic of FPGA can be divided into several Clock Regions. Each Clock Region consists of many columns of CLBs, and \emph{q} CLBs make up a column of CLBs. For instance, Fig.~\ref{fig3} shows the Clock Regions of Xilinx Zynq-7000 SoC ZC702 Evaluation Board.
The dark blue area represents columns of CLBs, and the number of columns and rows of CLBs are marked in Fig.~\ref{fig3}. For Xilinx Zynq-7000 SoCs, a CLB element contains two slices, and each slice consists of 4 LUTs and 8 FFs~\cite{Xilinx_UG585_2018}. For Xilinx Zynq UltraScale+ MPSoCs, a CLB element contains one slice, and each slice consists of 8 LUTs and 16 FFs~\cite{Xilinx_UG574_2017}. There are two types of slices, SLICEL (logic) and SLICEM (memory) respectively.

\begin{figure}[!t
\centerline{\includegraphics[width=1.8in]{fig3.pdf}}
\caption{As an example, ZC702 FPGA consists of the programmable logic and the processing system. The programmable logic can be divided into 6 Clock Regions. The dark blue area represents columns of CLBs, and the digits in black show the numbers of columns and rows of CLBs of each Clock Region. The total of CLBs in ZC702 FPGA is 6,650.}
\label{fig3}
\end{figure}

The Xilinx FPGA bitstream consists of Head-of-File, FDRI (Frame Data Register Input) data, and End-of-File. Among these three parts, FDRI data contains the configuration information and is the main content. The configuration memory is arranged in frames, which are the smallest addressable segments of configuration memory space. Each frame contains \emph{m} 32-bit words (101 words for Xilinx Zynq-7000 SoCs~\cite{Xilinx_UG470_2018} and 93 words for Xilinx Zynq UltraScale+ MPSoCs~\cite{Xilinx_UG570_2020}). According to the information provided by Head-of-File, the length of FDRI data is known, which is decided by the FPGA devices.

Since the open official document does not mention how the FDRI data configure CLBs, our work finds it through lots of analysis. We have found that every successive \emph{n} frames of the FDRI data configure a column of CLBs (\emph{q} CLBs), as is shown in Fig.~\ref{fig4}. Except for the \emph{l} words in the middle of the frame, every \emph{p} words in the left \emph{m}-\emph{l} words of a frame correspond to a CLB from the bottom to the top of the column. For Xilinx Zynq-7000 SoCs, a CLB contains two slices. The \emph{p} words configure separately the two slices in a CLB from left to right. Therefore, each CLB in a column of CLBs needs \emph{p}$\times$\emph{n} words to configure, which are distributed at the same location in the \emph{n} frames.

\begin{figure}[!t
\centerline{\includegraphics[width=3.5in]{fig4.pdf}}
\caption{Every successive \emph{n} frames of the FDRI data configure a column of CLBs from bottom to top. The configuration data for one CLB is distributed at the same location in the \emph{n} frames.}
\label{fig4}
\end{figure}

In the \emph{n} frames of the FDRI data configuring the same column of CLBs, the first frame has a fixed position in the bitstream. The positions of every first frame can be found by configuring the different columns of CLBs repeatedly. As an example, the composition of the bitstream of ZC702 FPGA is shown in Fig.~\ref{fig5}. The number of frames configuring a column of CLBs (\emph{n}) is 36 for ZC702 FPGA. Sometimes the gap between two consecutive first frames is 64 frames instead of 36 frames, because there is a column of BRAMs between the two columns of CLBs, and a column of BRAMs need 28 frames to configure. After the positions of every first frame are found, the configuration bits for every CLB element can be extracted from the raw data by the Python script.

\begin{figure}[!t
\centerline{\includegraphics[width=3.5in]{fig5.pdf}}
\caption{The bitstream file is arranged in frames. As an example, the composition of a bitstream file of ZC702 FPGA and the positions of some first frames are shown. The number of frames configuring a column of CLBs (\emph{n}) is 36 for ZC702 FPGA.}
\label{fig5}
\end{figure}

\subsection{Image-Coded Representation of Bitstream}\label{3_3_sec_Imagelike_representation_of_bitstream}

When proposing an image-coded representation of bitstream, there are two challenges to be faced. The first challenge is that the configuration bits of one CLB element are not consecutive in a bitstream. In order to extract features from the image-coded representation, the representation should reflect the adjacency of the programmable logic. The discontinuity of the configuration bits makes it difficult to reflect the adjacency of the programmable logic by the representation. The approach taken is analyzing the bitstream format and finding the mapping relationship between the CLB element in the device location diagram and the configuration bits in the bitstream. So that the two-dimensional location distribution diagram of the programmable logic is obtained by the mapping relationship.

The second challenge is that not all configuration information in the bitstream file is useful for function block detection. This challenge leads to two bad effects: 1) Since our work focuses on the logic resources, the utilization information of other resources may confuse the function block detection. For instance, the utilization of BRAMs will change if the array size in the function block changes, so the utilization of BRAMs may be very different for the same kind of function blocks. However, the logic in the function block will not change according to the data size. Therefore, the configuration bits, which are irrelevant to the logic resources and helpless for function block detection, can be dropped. 2) The large size of images leads to a large image dataset and low speed of reading image during the deep learning training. For instance, the storage size of a bitstream of ZC702 FPGA is 3.86 MiB, which is fixed for one type of FPGA device. If all of the configuration bits in a bitstream are transformed into an image, the size of the image will achieve 1280$\times$1080$\times$3, which is too large for deep learning training. The approach taken is using only configuration bits of CLBs for representation. Since approximately 60\% of the configuration bits in a bitstream are used for configuring CLBs, using only configuration bits of CLBs can compress effectively and drop useless information at the same time.

On the basis of the above bitstream analysis (Sec.~\ref{3_2_sec_bitstream_format_analysis}), we propose a three-channel color image-coded representation of the bitstream. The device diagram of FPGA is divided into \emph{a}$\times$\emph{b} blocks since each block corresponds to a CLB. The representation of each CLB is done separately and the representation results of all of the CLBs are aggregated to obtain the entire device location map.

According to the analysis of the bitstream format (Sec.~\ref{3_2_sec_bitstream_format_analysis}), each CLB is allocated 4\emph{p}$\times$\emph{n} bytes configuration memory from successive \emph{n} frames. For Xilinx Zynq-7000 SoCs, each slice is allocated 2\emph{p}$\times$\emph{n}=144 bytes. For Xilinx Zynq UltraScale+ MPSoCs, each slice is allocated 4\emph{p}$\times$\emph{n} bytes (\emph{n} is different for different types of slices). The several bytes of configuration data for a slice are transformed into a separate three-channel RGB image with the proper height and width. For example, the configuration bits of a slice in Xilinx Zynq-7000 SoCs are transformed into a three-channel color image with 6$\times$8 pixels. A pixel with three channels occupies three bytes. As is shown in Fig.~\ref{fig6}, the configuration bits are considered as the image data arranged in the order of (channel, height, width). For Xilinx Zynq-7000 SoCs, the image-coded representation of bitstream has (\emph{a}$\times$6)$\times$(\emph{b}$\times$2$\times$8) pixels with three RGB channels. For Xilinx Zynq UltraScale+ MPSoCs, the size of the image-coded representation of bitstream is decided by the numbers of the SLICEL and SLICEM. The configuration bits for every slice can be transformed into the three-channel image-coded representation by the Python script after the configuration bits are extracted from the bitstream file.

\begin{figure}[!t
\centerline{\includegraphics[width=3.5in]{fig6.pdf}}
\caption{For Xilinx Zynq-7000 SoCs, the 36-word configuration bits of a slice are transformed into a three-channel color image with 6$\times$8 pixels.}
\label{fig6}
\end{figure}

\subsection{Generation of Dataset}\label{3_4_sec_dataset}

The image-coded representation of bitstream is used to transform a large number of bitstream files into images, which are gathered into a dataset for deep learning training and testing. Each bitstream file implements an algorithm and each algorithm contains one or more than one function block. In a practical application, one kind of function block has different constructions, such as the original one with no special design and the pipelined one. Therefore, each kind of function block is implemented in one or two constructions when the bitstreams are generated.

Multiple bitstream files containing various kinds of function blocks are needed for the training of the deep network. We generate a large number of bitstreams by EDA toolset (Xilinx Vivado). The constraint of the implementation region makes the function blocks placed in different locations in different bitstreams. Tcl (Tool Command Language)~\cite{Xilinx_UG835_2018} of Xilinx Vivado is used instead of a graphical user interface (GUI). The categories and locations of the function blocks in the FPGA device diagram can be extracted from the EDA toolset when the bitstreams are generated by Tcl scripts. Finally, the bitstream files are transformed into images using the Python scripts. And the Python scripts process the label information into annotation files for deep learning at the same time.

\subsection{Architectures of the DNNs and Training for Function Block Detection}\label{3_5_sec_dnn}

Since the deep learning techniques have not been applied to the FPGA function block detection, our work makes use of the image-coded representation of bitstream and the image feature extraction capabilities of DNNs. YOLOv3 and SSD are two classical one-stage deep learning-based object detection algorithms, which have fast speed and high accuracy at the same time, especially the speed is much faster than the speed of two-stage deep learning-based object detection algorithms. The reason we choose YOLOv3 and SSD is their high comprehensive performance. The architectures and training process of YOLOv3 and SSD used in our work are introduced briefly below.

\textbf{YOLOv3.} YOLOv3 consists of 75 convolution layers. The sizes of kernel/stride include 1$\times$1/1, 3$\times$3/1, and 3$\times$3/2. The backbone of YOLOv3 is Darknet-53~\cite{Redmon_YOLOv3_2018}. There are three output convolution layers with different sizes of feature maps for detecting objects of different sizes. The three output convolution layers have the same filter number according to the class number. In YOLOv3, we divide the input picture into grids, and each grid cell predicts \emph{box\_number} bounding boxes (\emph{box\_number} is 3 for YOLOv3). One objectness prediction, \emph{C} class predictions for \emph{C} classes, and 4 box offsets are predicted for each bounding box. The objectness prediction quantifies how likely the image in the box contains a generic object~\cite{Alexe_TPAMI2012_objectness}. Thus, the filter number of the output layers is 3$\times$(1+\emph{C}+4). For example, we apply YOLOv3 to the detection of 10 kinds of function blocks, so the number of classes \emph{C} is 10 and the filter number of the output layers should be 45.

When training YOLOv3, we take the pre-trained weights for the COCO dataset~\cite{COCOdataset_ECCV2014} as initial weights. During the first 50 epochs of the training process, the front layers are frozen to get a stable loss value, except the last three output convolution layers. From the 51st to the 100th epoch, all of the layers are unfrozen and trained with a smaller learning rate. When the training is finished, choose the model with the smallest validation loss value as the final model. Eventually, test the model on the test set.

\textbf{SSD.} SSD consists of 29 convolution layers and 4 max-pooling layers. The sizes of kernel/stride are the same as YOLOv3. The backbone of SSD is VGG-16~\cite{Simonyan_ICLR2015_VGG}. There are six output convolution layers for objects of different sizes. Similar to YOLOv3, the filter number of the output layers is \emph{box\_number}$\times$(\emph{C}+4). In SSD, \emph{box\_number} can be 4 or 6 for different output layers. Thus, the filter number of the output layers in SSD is 56 or 84 when the class number \emph{C} is 10.

When training SSD, we load the trained weights of VGG-16 as initial weights for the front layers. In the first stage of training, the front layers are frozen with the weights from the VGG-16 model. Then, the whole network is trainable in the second stage of training. The training process is similar to YOLOv3 introduced above.

\section{Experimental Results}\label{4_sec_Experimental_results}

\subsection{Experimental Setup}\label{4_1_sec_Experimental_setup}

For evaluation purposes, we use Xilinx Zynq-7000 SoCs and Xilinx Zynq UltraScale+ MPSoCs to evaluate our proposed methodology. All of the experiments in this section are performed in the following experiment setup unless otherwise stated. The bitstream files are generated by the Xilinx Vivado toolset without encryption. The versions of Xilinx Vivado toolset used by this work include Vivado 2016.3, Vivado 2017.2, and Vivado 2017.4. The scripts used for transforming bitstreams into images are running in Python 2.7.15. The training and testing of the deep learning are running in Keras 2.2.5 based on TensorFlow 1.10.0 for GPUs, with Python 3.5.6. A server running CentOS Linux 7.6, with an NVIDIA Tesla P100 GPU, is used to perform all of the experiments.

There are 10 kinds of function blocks to detect. The DNN YOLOv3 is used as the deep learning-based object detection algorithm unless otherwise stated. The DNN SSD is only used in the experiments in Sec.~\ref{4_5_6_sec}. The parameters for the training process of YOLOv3 and SSD are listed in TABLE~\ref{table1}.

\begin{table}[!t
\caption{Parameters for the Training Process of YOLOv3 and SSD.}
\begin{center}
\begin{threeparttable}[b]
\begin{tabular}{|c|c|c|c|}
\hline
\multicolumn{2}{|c|}{Deep neural network} & YOLOv3  & SSD \\
\hline
\multicolumn{2}{|c|}{Input size\footnotemark[1]} & 416$\times$416$\times$3  & 300$\times$300$\times$3 \\
\hline
\multicolumn{2}{|c|}{Optimizer} & Adam~\cite{Kingma_ICLR2015_adam}  & Adam \\
\hline
{The first stage } &	Batch size &	32 &	32 \\
\cline{2-4}
{of training} &	Learning rate &	0.001 & 0.001\\
\hline
{The second stage } &	Batch size &	16 &	32 \\
\cline{2-4}
{of training} &	Learning rate &	0.0001 & 0.01\\
\hline

\end{tabular}
\label{table1}
\begin{tablenotes}
  \item[1] The images are resized to the input size of DNN before fed into the DNN.
\end{tablenotes}
\end{threeparttable}
\end{center}
\end{table}

To characterize the performance of the object detector quantitatively, mAP under specific IoU is used as the performance metric, which takes into account of both precision and recall. In general, the performance is good when the IoU for the detected box and the ground truth is more than 0.5. In our work, two metrics are used, imitating the COCO dataset. One is the mAP at IoU=0.5 (mAP@0.5), which is the metric for the PASCAL VOC dataset~\cite{Everingham_2010_VOCdataset}. The other one is the mAP at IoU=0.75 (mAP@0.75), which is stricter than mAP@0.5.

\subsection{Bitstream Format Information}\label{4_2_sec_bitstream_analysis}

For the purpose of finding the mapping relationship used for the representation of bitstream, this work analyzes the bitstream format of Xilinx Zynq-7000 SoCs and Xilinx Zynq UltraScale+ MPSoCs. The analysis results of these two families of SoCs are listed in TABLE~\ref{table2}. The bitstream format information listed in TABLE~\ref{table2} is determined by the FPGA device family.

\begin{table}[!t
\caption{Bitstream Format Information Determined by the FPGA Device Family, taking Xilinx Zynq-7000 SoCs and Xilinx Zynq UltraScale+ MPSoCs as Examples.}
\begin{center}
\begin{tabular}{|c|c|c|}
\hline
Device family & \tabincell{c}{Xilinx Zynq-7000\\ SoCs}&	\tabincell{c}{Xilinx Zynq \\UltraScale+ MPSoCs}\\
\hline
\tabincell{c}{Number of words \\in a frame (\emph{m})}	&101	&93\\
\hline
\tabincell{c}{Number of CLBs \\in a column (\emph{q})}	&50	&60\\
\hline
\tabincell{c}{Number of frames \\configuring a column \\of CLBs (\emph{n})}&	36&	\tabincell{c}{29 for SLICEL\\
79 for SLICEM}\\
\hline
\tabincell{c}{Number of words \\in the middle of a frame \\ not configuring CLBs (\emph{l})}&	1&	3\\
\hline
\tabincell{c}{Number of words \\configuring a CLB (\emph{p})}	&2	&1.5\\
\hline

\end{tabular}
\label{table2}
\end{center}
\end{table}

In order to further analyze the bitstream format information determined by the FPGA device, this work takes three FPGA devices, namely Xilinx Zynq-7000 SoC Z-7020, Xilinx Zynq-7000 SoC Z-7030, and Xilinx Zynq UltraScale+ MPSoC ZU9EG, as examples. The bitstream format information of these three FPGA devices is listed in TABLE~\ref{table3}. The bitstream format information listed in TABLE~\ref{table2} and TABLE~\ref{table3} and the positions of every first frame are necessary for transforming the bitstreams into images. Similar bitstream format rules can be found when analyzing other FPGA devices and other FPGA device families.

\begin{table}[!t
\caption{Bitstream Format Information Determined by the FPGA Device, taking Xilinx Zynq-7000 SoC Z-7020, Xilinx Zynq-7000 SoC Z-7030, and Xilinx Zynq UltraScale+ MPSoC ZU9EG as Examples.}
\begin{center}
\begin{threeparttable}[b]
\begin{tabular}{|c|c|c|c|}
\hline
Device name &	\tabincell{c}{Xilinx \\Zynq-7000 \\SoC Z-7020\footnotemark[1]}&	\tabincell{c}{Xilinx\\ Zynq-7000\\ SoC Z-7030\footnotemark[2]}&\tabincell{c}{Xilinx Zynq \\UltraScale+ \\MPSoC\\ ZU9EG\footnotemark[3]}\\
\hline
\tabincell{c}{Number of Clock \\Regions in\\ programmable logic}& 6&	8&	25\footnotemark[4]\\
\hline
\tabincell{c}{Number of CLBs \\in total}&	6,650&	9,825&	34,260\\
\hline
\tabincell{c}{Number of slices \\in total} &13,300	&19,650& 34,260\\
\hline
\tabincell{c}{Number of frames \\of the FDRI data \\in total}	& 10,008	&14,796&	71,260\\
\hline
\tabincell{c}{Number of words \\of the FDRI data\\ in total}& 1,010,808	&1,494,396	&6,627,180\\
\hline

\end{tabular}
\label{table3}
\begin{tablenotes}
    \item[1] Evaluated on Xilinx Zynq-7000 SoC ZC702 Evaluation Board.
    \item[2] Evaluated on Xilinx xc7z030fbg484-3 FPGA.
    \item[3] Evaluated on Xilinx Zynq UltraScale+ ZCU102 Evaluation Board.
    \item[4] There are 28 Clock Regions in Xilinx Zynq UltraScale+ MPSoC ZU9EG device totally. However, there are 3 Clock Regions without programmable logic resources.
\end{tablenotes}
\end{threeparttable}
\end{center}

\end{table}

\subsection{Bitstream Representation}\label{4_3_sec_representation}

According to the bitstream format analysis results in Sec.~\ref{4_2_sec_bitstream_analysis}, the bitstreams are transformed into images by the proposed image-coded representation of bitstream. Taking Xilinx Zynq-7000 SoC Z-7020, Xilinx Zynq-7000 SoC Z-7030, and Xilinx Zynq UltraScale+ MPSoC ZU9EG as examples, the parameters for transforming the bitstreams into images are listed in TABLE~\ref{table4}.

\begin{table}[!t
\caption{Parameters for Transforming the Bitstreams into Images, taking Xilinx Zynq-7000 SoC Z-7020, Xilinx Zynq-7000 SoC Z-7030, and Xilinx Zynq UltraScale+ MPSoC ZU9EG as Examples.}
\begin{center}
\begin{tabular}{|c|c|c|c|}
\hline

Device name &	\tabincell{c}{Xilinx \\Zynq-7000 \\SoC Z-7020}&	\tabincell{c}{Xilinx \\Zynq-7000 \\SoC Z-7030}&	\tabincell{c}{Xilinx Zynq\\ UltraScale+ \\MPSoC \\ZU9EG}\\
\hline
\tabincell{c}{Image size \\of a slice}&	6$\times$8$\times$3&	6$\times$8$\times$3	&\tabincell{c}{7$\times$9$\times$3 \\for SLICEL,\\7$\times$23$\times$3 \\for SLICEM}\\
\hline
\tabincell{c}{Image size \\of a CLB}&	6$\times$16$\times$3&	6$\times$16$\times$3&	\tabincell{c}{7$\times$9$\times$3\\ for SLICEL,\\7$\times$23$\times$3\\ for SLICEM}\\
\hline
\tabincell{c}{Number of \\blocks the \\device diagram \\divided (\emph{a}$\times$\emph{b})}&	150$\times$57&	200$\times$60&	\tabincell{c}{420$\times$97\\ (46 for SLICEL,\\ 51 for SLICEM)}\\
\hline
\tabincell{c}{Size of the \\image-coded\\ representation\\ (bytes)}&	900$\times$912$\times$3	&1200$\times$960$\times$3&	2940$\times$1587$\times$3\\
\hline
\tabincell{c}{Bitstream \\length (bits)}&	32,364,512	& 47,839,328	&212,086,240\\
\hline
\tabincell{c}{Bitstream \\length, rounded\\ up (MiB)}&	3.86&	5.70&	25.28\\
\hline
\tabincell{c}{Compression \\ratio (\%)}	&60.86	&57.79&	52.80\\
\hline

\end{tabular}
\label{table4}
\end{center}

\end{table}

For instance, the bitstream length of ZC702 FPGA is 3.86 MiB. The size of the image-coded representation of bitstream is 900$\times$912$\times$3 bytes. So the representation compresses effectively the image to
(900$\times$912$\times$3$\times$8 bits/32,364,512 bits)$\times$100\%=60.86\%
of the original bitstream data. The effective compression mainly benefits from the drop of the configuration bits irrelevant to the logic resources. The parameters for transforming the bitstreams into images are set differently for the different FPGA devices and determined by the bitstream format information of FPGA devices.

The Vivado implemented designs and the image-coded representation of bitstream of Xilinx Zynq-7000 SoC Z-7020, Xilinx Zynq-7000 SoC Z-7030, and Xilinx Zynq UltraScale+ MPSoC ZU9EG are shown in Fig.~\ref{fig7}. The dark blue area in the Vivado implemented design represents columns of CLBs, the configuration bits of which are used for the bitstream representation. The corresponding relationship between the Vivado implemented design (shown in Fig.~\ref{fig7} (a), (c), and (e)) and the image-coded representation of bitstream (shown in Fig.~\ref{fig7} (b), (d), and (f)) for the same FPGA device proves that the mapping relationship between configuration bits and CLBs found by this work is correct and the image-coded representation of bitstream can reflect the adjacency of the programmable logic.

\begin{figure}[!t]
\centering
\subfigure[]{
\includegraphics[width=1.58in]{fig7a.pdf}
}
\hfil
\subfigure[]{
\includegraphics[width=1.58in]{fig7b.pdf}
}
\hfil
\subfigure[]{
\includegraphics[width=1.58in]{fig7c.pdf}
}
\hfil
\subfigure[]{
\includegraphics[width=1.58in]{fig7d.pdf}
}
\hfil
\subfigure[]{
\includegraphics[width=1.58in]{fig7e.pdf}
}
\hfil
\subfigure[]{
\includegraphics[height=2.5611in]{fig7f.pdf}
}
\caption{Vivado implemented designs and the image-coded representation. (a) Vivado implemented design and (b) the image-coded representation of bitstream of Xilinx Zynq-7000 SoC Z-7020. (c) Vivado implemented design and (d) the image-coded representation of bitstream of Xilinx Zynq-7000 SoC Z-7030. (e) Vivado implemented design and (f) the image-coded representation of bitstream of Xilinx Zynq UltraScale+ MPSoC ZU9EG.}
\label{fig7}
\end{figure}

In summary, the two challenges mentioned in Sec.~\ref{3_3_sec_Imagelike_representation_of_bitstream} have been overcome by the proposed image-coded representation of bitstream.

\subsection{Dataset Description}\label{4_4_sec_dataset}

For the purpose of training and testing the DNN models, a large number of bitstreams, which implement FPGA designs on ZC702 FPGA, are generated to make up the dataset. There are 15 kinds of application-specific encryption algorithms chosen for generating 15,104 bitstream files and these encryption algorithms contain 10 kinds of cryptographic operators. The application-specific encryption algorithms used for generating the dataset and the cryptographic operators contained are listed in TABLE~\ref{table5}. Each encryption algorithm used in this work contains up to 3 kinds of cryptographic operators. Each kind of cryptographic operator is implemented in one or two constructions. The pipeline means the cryptographic operator is implemented in a pipeline design, and the module means the cryptographic operator is implemented without special designs. For example, a bitstream implementing the encryption algorithm used for NTLM (NT LAN Manager) contains an MD4 pipeline or an MD4 module. A bitstream implementing the encryption algorithm used for PDF-R2 contains an MD5 (Message Digest Algorithm 5) pipeline and an RC4 (Rivest Cipher 4) module.

\begin{table*}[!t
\caption{Components of the Training Set and Test Set. }
\begin{center}
\begin{tabular}{|c|c|c|c|c|c|}
\hline
\tabincell{c}{Vivado\\ version}	& \tabincell{c}{Applications of \\encryption \\algorithms}&\tabincell{c}{Number of \\cryptographic\\ operators\\ contained}&\tabincell{c}{Cryptographic\\ operators}	& \tabincell{c}{Implementation constructions}&\tabincell{c}{Number of\\ bitstreams}\\
\hline
\hline
&	\emph{\tabincell{c}{For training \\and testing}}	&&&&\\
\hline
\multirow{13}{*}{2017.4}
&LM &1	&DES	&\tabincell{c}{DES pipeline; DES module}	&1,294\\

&NTLM	&1	&MD4	&\tabincell{c}{MD4 pipeline; MD4 module}	&1,135\\

&PDF-R2	&2	&MD5, RC4	&\tabincell{c}{MD5 pipeline, RC4 module}&2,252\\

&OFFICE 2003	&2	&MD5, RC4	&\tabincell{c}{MD5 pipeline, RC4 module}	& 419\\

&TrueCrypt	&3	&AES, Serpent, Twofish	&\tabincell{c}{AES module, Serpent module, Twofish module}	&1,842\\

&OFFICE 2007	&1	&SHA-1	&SHA-1 pipeline	&429\\

&WPA-2	&1	&SHA-1	&SHA-1 pipeline	&451\\

&	WINZIP	&1	&SHA-1	&SHA-1 pipeline	&542\\

&RAR3	&1	&SHA-1	&SHA-1 module	&165\\

&RAR5	&1	&SHA-256	&SHA-256 pipeline	&245\\

&7ZIP	&1	&SHA-256	&SHA-256 pipeline	&242\\

&OFFICE 2013	&1	&SHA-512	&SHA-512 module &303\\

&LINUX-SHA512	&1	&SHA-512	&SHA-512 module	&728\\
\hline
&Total				&&&&10,047\\
\hline
\hline
&	\emph{For testing only}&&&&	\\
\hline
\multirow{2}{*}{2016.3}
&	PDF-R2&	2&	MD5, RC4	&MD5 pipeline, RC4 module	&587\\
&	PDF-R5&	2&	MD5, RC4&	MD5 pipeline, RC4 module&	1,107\\
\hline
\multirow{2}{*}{2017.2}
&	PDF-R2&	2	&MD5, RC4&	MD5 pipeline, RC4 module&	587\\
&PDF-R5&	2	&MD5, RC4&	MD5 pipeline, RC4 module&	1,407\\
\hline
\multirow{2}{*}{2017.4}
&PDF-R5	&2&	MD5, RC4	&MD5 pipeline, RC4 module&	1,107\\
&	OFFICE 2010&	1	&SHA-1	&SHA-1 pipeline	&232\\
\hline
&	Total		&&&&		5,057\\
\hline
\end{tabular}
\label{table5}
\end{center}
\end{table*}

In order to arrange the experiments reasonably, 13 kinds of encryption algorithms in TABLE~\ref{table5} are chosen to make up the training set and the test set, including 10,047 bitstreams generated by Xilinx Vivado 2017.4 totally. The bitstreams for training and testing are divided into the training set and the test set randomly by 4:1. Two kinds of encryption algorithms, used for PDF-R5 and OFFICE 2010, implemented by Xilinx Vivado 2017.4 are just used for testing. Besides, to explore the effect of EDA tools, the bitstreams generated by Xilinx Vivado 2016.3 and Xilinx Vivado 2017.2 are used to test the performance of the trained model. These bitstreams are transformed into images to make up the dataset for training and testing in Sec.~\ref{4_5_sec_detection}.

\subsection{Function Block Detection}\label{4_5_sec_detection}

The experimental results of function block detection are evaluated on ZC702 FPGA. Firstly, the evaluation results on the test set with the same distribution as the training set are shown, as well as the evaluation results on the encryption algorithms not appearing in the training set. Then, the effects of EDA tools, input size of the DNN, and the data arrangement of the image-coded representation are discussed. Finally, another deep learning-based object detection algorithm SSD is applied and the performance of SSD is presented.

\subsubsection{Evaluation results on the test set}\label{4_5_1_sec}
The first 13 kinds of encryption algorithms listed in TABLE~\ref{table5} are chosen to make up the training set and the test set. Since the images transformed from the bitstreams of the 13 kinds of encryption algorithms are divided into the training set and the test set randomly by 4:1, the test set has the same distribution as the training set.

In this experiment, we train our detector on the training set for around 16 hours and test on the test set with the same distribution as the training set. The function block detection result of a bitstream file, which implements the encryption algorithm used for PDF-R2 on ZC702 FPGA, is shown in Fig.~\ref{fig8}, as an example. The function blocks included in this image are marked with boxes. Each box is labeled with the category and a classification probability.

\begin{figure}[!t
\centerline{\includegraphics[width=1.8in]{fig8.png}}
\caption{The function block detection result of a bitstream file implementing the encryption algorithm used for PDF-R2 on ZC702 FPGA.}
\label{fig8}
\end{figure}

TABLE~\ref{table6} shows the evaluation results under the metrics mentioned in Sec.~\ref{4_1_sec_Experimental_setup}. The performance of the detector is evaluated quantitatively on the test set. AP (Average Precision) @0.5 of 10 kinds of cryptographic operators are all beyond 85.33\% and mAP@0.5 reaches 97.72\%. Even under the stricter metric, mAP@0.75 reaches 95.87\%. It is evident that the detector has a good detection performance on the test set with the same distribution as the training set.

\begin{table*}[!t
\caption{Evaluation Results on the Test Set with the Same Distribution as the Training Set.}
\begin{center}
\begin{tabular}{|c|c|c|c|c|c|c|c|c|c|c|c|}
\hline
\tabincell{c}{Function blocks}&	\textbf{mAP}&	AES	&DES&	MD4&	MD5	&RC4	&Serpent&	SHA-1	&SHA-
256&	SHA-
512	&Twofish\\
\hline
AP@0.5 (\%)&	\textbf{97.72}&	93.61	&99.92&	100.00	&100.00	&99.52	&85.33	&100.00	&100.00	&98.78	&100.00\\
\hline
AP@0.75 (\%)&	\textbf{95.87}	&77.52	&99.76	&99.98&	99.23&	99.26&	83.85&	100.00	&100.00&	99.13&	100.00\\
\hline
\end{tabular}
\label{table6}
\end{center}
\end{table*}

The image-coded representation of bitstream can reflect the resource utilization of function blocks and the adjacency of the CLBs used. Different kinds of function blocks are different in these two aspects. The SHA-256 module nearly takes over all of the LUT resources of ZC702 FPGA. However, the RC4 module only occupies no more than 1\% of the FF resources and approximately 3\% of the LUT resources. When implemented in the same construction, two function blocks of the same kind are similar but appear in different locations in different images. Since the image-coded representation of bitstream keeps some characteristics of function blocks that can distinguish one kind of function block from another one, the proposed image-coded representation of bitstream is proved effective and applicable for generating a dataset for deep learning. The performance of the detector also demonstrates that YOLOv3 learns successfully how to detect the function blocks from the images.

Some kinds of cryptographic operators are well detected, such as SHA-1 and SHA-256. It is because these kinds of cryptographic operators occupy a large area of the images. It is not difficult to detect a box with an IoU over 0.5 or 0.75 with the ground truth.

Some kinds of cryptographic operators have relatively low AP, such as AES and Serpent. The reasons are as follows: 1) These kinds of cryptographic operators always occupy a small number of resources of FPGA. It is difficult to distinguish one function block with high resource utilization and the combination of several function blocks with low resource utilization. 2) There is more than one function block in an image. It is more difficult to detect a function block from a system with various function blocks than from a system with a single function block. The boundary between two function blocks in an image is hard to distinguish.

\subsubsection{Effectiveness of detecting cryptographic operators}\label{4_5_2_sec}

In this experiment, the trained model is tested on the bitstream files implementing the encryption algorithms, which do not appear in the training set, to confirm the capability to detect cryptographic operators. The training process is the same as mentioned in Sec.~\ref{4_5_1_sec}. We choose 1,339 bitstreams for testing in this experiment, which implement two kinds of encryption algorithms used for PDF-R5 and OFFICE 2010 and are generated by Vivado 2017.4. The function blocks in these bitstreams have the same implementation constructions as the ones in the training set.

TABLE~\ref{table7} shows the results of this experiment. The evaluation results on the encryption algorithms used for PDF-R5 and OFFICE 2010 show that the detector also has a good performance on the encryption algorithms not appearing in the training set, because the cryptographic operators in these encryption algorithms have the same implementation constructions as the ones in the training set. TABLE~\ref{table6} and TABLE~\ref{table7} demonstrate that the detector has the capability to detect the function blocks with the same constructions in the training set, no matter whether the encryption algorithms appear in the training set or not.

\begin{table}[!t
\caption{Evaluation Results on the Encryption Algorithms not Appearing in the Training Set.}
\begin{center}
\begin{tabular}{|c|c|c|c|}
\hline
\multicolumn{2}{|c|}{Function blocks} & AP@0.5 (\%) &	AP@0.75 (\%)\\
\hline
\multirow{2}{*}{PDF-R5}
&	(1) MD5 pipeline&	100.00&	99.60\\
\cline{2-4}
&	(2) RC4 module&	97.13	&94.98\\
\hline
OFFICE 2010	&(3) SHA-1 pipeline&	100.00&	100.00\\
\hline

\end{tabular}
\label{table7}
\end{center}
\end{table}

Although the RC4 module has appeared in the training set, the small occupied area of the RC4 module accounts for the relatively low AP. On the contrary, the SHA-1 pipeline occupies a large area. And the detector has the capability to distinguish SHA-1 from other cryptographic operators, which also have a large area, such as SHA-256. Therefore, the SHA-1 pipeline has a really high AP.

\subsubsection{Effect of EDA tools}\label{4_5_3_sec}
In this experiment, the model is trained on the bitstreams generated by Vivado 2017.4 and tested on the bitstreams generated by the other version of Xilinx Vivado, namely Vivado 2016.3 and Vivado 2017.2. The training process is the same as mentioned in Sec.~\ref{4_5_1_sec}. The bitstreams for testing implementing encryption algorithms used for PDF-R2 and PDF-R5, contain the function blocks with the same implementation constructions as the ones in the training set. The encryption algorithm used for PDF-R2 is included in the training set. However, the encryption algorithm used for PDF-R5 is not included. This experiment is set up to explore the effect of the EDA tools. Although the EDA tools are provided by the FPGA vendors, the corresponding EDA tools are updated continually.

The evaluation results are shown in Fig.~\ref{fig9}. The evaluation results on bitstreams generated by Vivado 2016.2 and Vivado 2017.2 are compared with the evaluation results on bitstreams generated by Vivado 2017.4. The AP of MD5 is not affected by the change of EDA tool. The AP of RC4 evaluated on other EDA tools, namely Vivado 2016.3 and Vivado 2017.2, is lower than the AP evaluated on Vivado 2017.4. Although there are some differences in placing and routing when optimizing the same design on the different versions of Vivado toolset, there is no big difference in the resource utilization of function blocks and the effect of EDA tools on the detection accuracy is really slight. It is evident that the model trained on bitstreams generated by Vivado 2017.4 can detect the function blocks from the bitstreams generated by Vivado 2016.3 and Vivado 2017.2, although the detection accuracy of some function blocks may decrease due to the really low resource utilization.

\begin{figure}[!t]
\centering
\subfigure[]{
\includegraphics[width=3in]{fig9a.pdf}
}
\hfil
\subfigure[]{
\includegraphics[width=3in]{fig9b.pdf}
}
\caption{Evaluation results on the bitstreams generated by different EDA tools. (a) The AP@0.5 and (b) the AP@0.75 of MD5 and RC4 evaluated on the bitstreams generated by different EDA tools. }
\label{fig9}
\end{figure}

\subsubsection{Effect of input size}\label{4_5_4_sec}

In this experiment, there are five models trained with different input sizes of YOLOv3. The purpose of this experiment is to explore the effect of the input sizes of YOLOv3 on detection accuracy. The images are resized to the input size of YOLOv3 before fed into the DNN. Since YOLOv3 is a fully convolutional network without any fully connected layers, the changes in the input size will not change the number of weight parameters in every layer. The hyperparameters of the models with different input sizes are the same as the model trained in Sec.~\ref{4_5_1_sec}. The input size of the model in Sec.~\ref{4_5_1_sec} is 416$\times$416$\times$3. The training set and test set are the same as set up in Sec.~\ref{4_5_1_sec} and Sec.~\ref{4_5_2_sec}. The bitstreams in this experiment are all generated by Vivado 2017.4.

The mAP of 10 kinds of function blocks on the test set with the same distribution as the training set is shown in Fig.~\ref{fig10} (a). The five models are also evaluated on the encryption algorithm used for PDF-R5, which has not appeared in the training set. The evaluation results on the encryption algorithm used for PDF-R5 are shown in Fig.~\ref{fig10} (b). Considering the evaluation results on the test set and the encryption algorithm not appearing in the training set shown in Fig.~\ref{fig10}, it is demonstrated that the model with the input size of 224$\times$224$\times$3 has the worse performance among these five models. Except for the model with the input size of 224$\times$224$\times$3, the other four models have a similar performance. There is no need to choose too large input size for the DNN, because the large input size leads to large computation.

\begin{figure}[!t]
\centering
\subfigure[]{
\includegraphics[width=3in]{fig10a.pdf}
}
\hfil
\subfigure[]{
\includegraphics[width=3in]{fig10b.pdf}
}
\caption{Evaluation results of five models with different input sizes on (a) the test set and (b) the encryption algorithm used for PDF-R5.}
\label{fig10}
\end{figure}

\subsubsection{Effect of the order in which the configuration bits of a slice correspond to the image}\label{4_5_5_sec}

In this experiment, there are three models trained on different image datasets. The three image datasets are transformed from the same bitstreams by different representation methods. The only difference among the three representation methods is the order in which the configuration bits of a slice correspond to the image. The first order is (channel, height, width), as is shown in Fig.~\ref{fig6}. The other two orders are (height, width, channel) and (channel, width, height), respectively. The training processes are the same as mentioned in Sec.~\ref{4_5_1_sec}. The bitstreams in this experiment are all generated by Vivado 2017.4. The purpose of this experiment is to explore the effect of the order in which the configuration bits of a slice correspond to the image.

The mAP of 10 kinds of function blocks on the test set with the same distribution as the training set is listed in TABLE~\ref{table8}. The three models are also evaluated on the encryption algorithm used for PDF-R5, and the evaluation results are listed in TABLE~\ref{table9}. It is demonstrated that the order, in which the configuration bits of a slice correspond to the image, has almost no effect on the detection accuracy. It is inferred that as long as the representation of bitstream can reflect whether each slice is used or not, the detection accuracy will not be affected.

\begin{table}[!t
\caption{Evaluation Results of Three Models with Different Orders, in Which the Configuration Bits of a Slice Correspond to the Image, on the Test Set. }
\begin{center}
\footnotesize
\begin{tabular}{|c|c|c|}
\hline

The order	&mAP@0.5 (\%)&	mAP@0.75 (\%)\\
\hline
\tabincell{c}{ (channel, height, width)}&	97.72	&95.87\\
\hline
(height, width, channel)&	97.46&	95.28\\
\hline
(channel, width, height)&	97.64	&95.71\\
\hline

\end{tabular}
\label{table8}
\end{center}
\end{table}

\begin{table}[!t
\caption{Evaluation Results of Three Models with Different Orders, in Which the Configuration Bits of a Slice Correspond to the Image, on the Encryption Algorithm Used for PDF-R5.}
\begin{center}
\begin{tabular}{|c|c|c|c|}
\hline

The order	&\tabincell{c}{ Function\\ blocks}	&\tabincell{c}{AP@0.5\\ (\%)}&\tabincell{c}{ 	AP@0.75 \\(\%)}\\
\hline
\multirow{2}{*}{(channel, height, width)}
&	MD5	&100.00&	99.51\\
\cline{2-4}
&  RC4	&97.13	&94.99\\
\hline
\multirow{2}{*}{(height, width, channel)}&
MD5	&100.00&	99.66\\
\cline{2-4}
&RC4&	96.90&	95.39\\
\hline
\multirow{2}{*}{(channel, width, height)}&
MD5	&100.00&	99.52\\
\cline{2-4}
&RC4	&96.44	&94.38\\
\hline

\end{tabular}
\label{table9}
\end{center}
\end{table}

\subsubsection{Application of other deep learning-based object algorithms to function block detection}\label{4_5_6_sec}

In this experiment, SSD is applied to bitstream function block detection to demonstrate the effectiveness of the methodology. In the methodology, it is not necessary to choose YOLOv3 as the deep learning-based object detection algorithm. The training set and test set are the same as used in Sec.~\ref{4_5_1_sec}. The bitstreams are generated by Vivado 2017.4.

The evaluation results of SSD on the test set are listed in TABLE~\ref{table10}, together with the evaluation results of YOLOv3 in Sec.~\ref{4_5_1_sec}. The evaluation results of SSD show that SSD also has the capability to detect function blocks. The methodology has generality to some degree and the other deep learning-based object detection algorithms with high performance can be applied. Compared with the performance of YOLOv3, the performance of SSD is evidently lower than YOLOv3. mAP@0.5 of SSD is slightly low than mAP@0.5 of YOLOv3. However, mAP@0.75 of SSD is much lower than YOLOv3. It is shown that the location accuracy of SSD is poor in this scenario.

\begin{table}[!t
\caption{Evaluation Results of YOLOv3 and SSD on the Test Set with the Same Distribution as the Training Set.}
\begin{center}
\begin{tabular}{|c|c|c|}
\hline

\tabincell{c}{Deep neural network \\(Input size)}&	mAP@0.5 (\%)&	mAP@0.75 (\%)\\
\hline
\tabincell{c}{YOLOv3 (416$\times$416$\times$3)}	&97.72 &	95.87\\
\hline
\tabincell{c}{  SSD (300$\times$300$\times$3)	}&96.34&	81.54\\
\hline

\end{tabular}
\label{table10}
\end{center}
\end{table}

\subsection{Processing Time}\label{4_6_secProcessing_time}
Taking Xilinx Zynq-7000 SoC Z-7020, Xilinx Zynq-7000 SoC Z-7030, and Xilinx Zynq UltraScale+ MPSoC ZU9EG as examples, the processing time of transforming a bitstream into an image is reported in Fig.~\ref{fig11}, together with the bitstream length. The processing time is measured on a single Intel Xeon Gold 5118 CPU@2.30GHz. It is evident that the processing time of transforming a bitstream into an image is almost proportional to the bitstream length, which is determined by the FPGA device.

\begin{figure}[!t
\centerline{\includegraphics[width=3in]{fig11.pdf}}
\caption{The processing time of transforming a bitstream into an image on a single Intel Xeon Gold 5118 CPU@2.30GHz. }
\label{fig11}
\end{figure}

As is shown in Fig.~\ref{fig12}, the processing time per image of the YOLOv3 inference process varies with the input size of the DNN. Before fed into the DNN, the images are resized to the input size of the DNN. Therefore, the processing time of YOLOv3 inference has no relationship with the size of the image-coded representation of bitstream. The confidence threshold is set as 0.5 and the IoU threshold is set as 0.45 for inference. The processing time is measured on an NVIDIA Tesla P100 GPU. It is shown that the processing time of YOLOv3 inference increases as the input size of YOLOv3 increases.
Besides, the processing time of the SSD inference process is 0.0803s per image, also measured on an NVIDIA Tesla P100 GPU. The thresholds are set the same as YOLOv3. The input size of SSD is 300$\times$300$\times$3.

\begin{figure}[!t
\centerline{\includegraphics[width=3in]{fig12.pdf}}
\caption{ The processing time per image of the YOLOv3 inference process on an NVIDIA Tesla P100 GPU.  }
\label{fig12}
\end{figure}

\subsection{Recap}\label{4_7_sec_recap}

Based on the above experimental results and analysis, the effectiveness of the proposed bitstream function block detection methodology is proved. The following points summarize the insights from the experimental results:

1) Similar bitstream format rules can be found in several FPGA devices by bitstream format analysis, which is the basis of the image-coded representation of bitstream. The image-coded representation can reflect the adjacency of the programmable logic and the image-coded representation has a suitable size without losing useful information.

2) The deep learning-based object detection algorithm has the capability to detect the function blocks with the same constructions in the training set, no matter whether the system designs appear in the training set or not.

3) The model trained on the bitstreams generated by one version of Xilinx Vivado can also detect function blocks from the bitstreams generated by other versions of Xilinx Vivado.

4) The model with too small input size has bad detection accuracy. The model with too large input size has no accuracy improvement while sacrificing the computation cost.

5) The order in which the configuration bits of a slice correspond to the image has almost no effect on the detection accuracy, as long as the image-coded representation of a slice can reflect whether the slice is used or not.

6) In the methodology, other deep learning-based object detection algorithms with high performance can also be chosen to detect function blocks from the bitstream.

\section{Related Works}\label{5_sec_related_works}

In this section, some related works about bitstream format analysis, bitstream reverse engineering, and deep learning-based circuit classification are presented.

An FPGA bitstream contains the programming information for an FPGA device, which configures the programmable logic into the FPGA. Because of the lack of disclosed information about the bitstream format from FPGA vendors, many works have analyzed the format of bitstream~\cite{Ziener_FPL2006},~\cite{leRoux2019},~\cite{DangPham_DATE2017_BITMAN},~\cite{Bozzoli_ARCSW2018_COMET}. Ziener \emph{et al.}~\cite{Ziener_FPL2006} extracted the content of LUTs in the bitstream of Xilinx Virtex-II and Virtex-II Pro FPGAs to identify IP cores in the FPGAs. Le Roux \emph{et al.}~\cite{leRoux2019} analyzed the bitstream of Xilinx Virtex-5 FPGAs to manipulate the configuration bits of LUTs for the purpose of reconfiguring the FPGAs in real-time. There are also some related works analyzing the bitstream format of the later Xilinx 7-series FPGAs~\cite{DangPham_DATE2017_BITMAN},~\cite{Bozzoli_ARCSW2018_COMET}. Dang Pham \emph{et al.}~\cite{DangPham_DATE2017_BITMAN} provided a tool called BITMAN that supports bitstream manipulations, such as module placement, module relocation, and so on. COMET~\cite{Bozzoli_ARCSW2018_COMET} is a tool supporting bitstream analysis, visualization, and manipulation. The manipulation of bitstream is to provide means to perform partial reconfiguration or fault injection.

There are many works implementing FPGA bitstream reverse engineering based on bitstream analysis. Some of them reverse the bitstream to a Xilinx Design Language (XDL) level representation of the netlist or a Native Circuit Description (NCD) file~\cite{note_FPGA2008_bitstream},~\cite{Benz_FPL2012},~\cite{DING_2013_NCD}. Some of them further reverse the netlist file to Register Transfer Level (RTL) code~\cite{Zhang_Access_2019}. These works analyze the bitstream format and gather databases containing the mapping relationship from the configuration bits in the bitstream to their related configurable elements. Reverse engineering is implemented through these databases. Bitstream reverse engineering aims at performing analysis or detecting hardware Trojan based on netlist or RTL code.

Dai \emph{et al.}~\cite{Dai_HOST2017} put forward a CNN method for arithmetic operator classification and detection from gate-level circuits rather than bitstream-level, and discussed the importance of representation of circuits for CNN processing. Fayyazi \emph{et al.}~\cite{Fayyazi_DATE2019} also presented a CNN-based gate-level circuit recognition method and used a vector-based representation for the CNN processing. The method can be used to detect the hardware trojans or classify the circuits of different arithmetic operators, such as an adder and an multiplier. Mahmood \emph{et al.}~\cite{Mahmood_ICCE_Berlin2019} proposed judging whether a partial bitstream contains a hardware module implementing an add operation using neural networks. Their work lacks the analysis and process of the raw bitstream data. Neto \emph{et al.}~\cite{Neto_ICCAD2019} also took advantage of the latest progress of DNNs in image classification by proposing a binary image-like circuit representation of Boolean logic function. However, the work in~\cite{Neto_ICCAD2019} just utilized the DNNs to choose the best optimization method for the partitioned circuits. And the binary image-like representation of Boolean logic function in~\cite{Neto_ICCAD2019} is different with the three-channel color image-coded representation in this paper, which is proposed to represent the configuration bits in the bitstream.

\section{Conclusions}\label{6_sec_conclusions}
In this paper, we have proposed an FPGA bitstream function block detection method built upon the deep learning techniques. At first, we analyze the bitstream format and find the mapping relationship between the configuration bits and the CLB elements. Then, we propose a three-channel color image-coded representation of bitstream, which reflects the adjacency of the programmable logic and transforms the bitstreams into images suitable for deep learning processing. A dataset is generated without manual annotation, in which there are 15,104 images transformed from bitstreams. The object detection algorithm based on deep learning is applied to detecting function blocks from FPGA bitstreams by training on this dataset. The process of dataset generation, deep learning training and testing could be implemented by scripts automatically. Experimental results show that mAP (IoU=0.5) for 10 kinds of function blocks reaches 97.72\% when using YOLOv3 as the object detector. The detector is also demonstrated to have the capability to detect the function blocks from the bitstreams implementing the system designs not appearing in the training set or from the bitstreams generated by other EDA tools.

\ifCLASSOPTIONcaptionsoff
  \newpage
\fi

\bibliographystyle{IEEEtran}

redpajama_set_name: RedPajamaArXiv


text:
News Forum - Thailand Pass scam: Authorities warn not to pay third party
The Ministry of Foreign Affairs put out a warning today via their spokesperson urging people not to be taken in by any scam attempting to charge you for registering for the Thailand Pass. The announcement came on the heels of the Covid-19 task force investigating reports of people claiming to have paid registration fees in order to apply for the Pass needed to enter Thailand First of all, the Thailand Pass programme has been suspended since December 22 along with the Test & Go entry scheme thanks to a sharp rise in Covid-19 infections as the Omicron variant takes hold […]
The story Thailand Pass scam: Authorities warn not to pay third party as seen on Thaiger News.
Or.....even beware of the original scams.
"...the Thailand Pass programme (sic) has been suspended since December 22..."
WRONG! I just, 3 days ago, applied on behalf of a friend. Accepted, and QR code received within 24 hours.
2 minutes ago, AMc said:
There was a grace period extended for many....of the last couple weeks.
The so call review is scheduled for tomorrow. In theory, they make a decision as to what program they're going with.
13 minutes ago, Rain said:
But wasn't that just for the "Test and Go" scheme?
Thailand Pass is the only route available now, as far as I know, due to it superseding the old COE pass. In any case, Thai Immigration issued her the QR code after my applying for her.
She'll be spending 10 days in quarantine at an ASQ hotel.
Sarisin
I wish reporting on here was accurate- only the test and go scheme is stopped, Thailand pass can still be applied for if you want to be forced to go to Phuket and other horrid islands, or 7 day AQ solitary in Bkk or 10 days for the selfish unvaxxed etc up to you. Personally i'd rather spend 2 weeks in a hotel room than ever having to visit Phuket ever again.
Edited January 14 by Sarisin
12 minutes ago, Sarisin said:
So do I ! ...................you can only enter via the Sandbox scheme now and BKK isn't part of the scheme.
People do everything for money these days
Jan 14 Faz locked this topic
The article is factually incorrect and has been reported to the Thaiger News team.

redpajama_set_name: RedPajamaCommonCrawl


Question: I have upped my free weights program recently and I have a feeling that I am not eating enough protein to sustain it. I am going to up my intake of protein. What is the best way?
Answer: Be careful when choosing the types of protein you eat. Despite our increased knowledge of nutrition, at least one out of five people are still eating a greasy bacon cheeseburger for lunch. Certainly it has protein, and plenty of it, but it also comes with an artery-clogging quantity of fat. That same person is probably having red meat at one or two more meals of the day, maybe bacon and eggs for breakfast or a big steak for dinner. That average diet is way too high in fat...and probably unnecessarily high in protein as well. While eating too much protein is not going to harm you the way eating too much fat is, it is still tough on the body.
Remember the alternate, non-animal sources of protein like rice, beans, seeds and nuts and bon appetit!


text:
The Role of Surfactant Force Field on the Properties of Liquid/Liquid Interfaces
2019-10-30T21:36:53Z (GMT) by Michael Servis Alex McCue Amanda Casella Aurora Clark
Surfactant-laden liquid/liquid interfaces mediate numerous chemical processes, from commercial applications of microemulsions to chemical separations. Classical molecular dynamics simulation is a prevalent method for studying microscopic and thermodynamic properties of such interfaces. However, the extent to which these features can be reliably predicted, and the variations in predicted behavior, depend upon the force field parameters employed. At present, the impact of force fields upon simulated properties is relatively understudied. Yet recent advances to sampling and analysis algorithms are increasing the interpretation of simulation data and therefore understanding force field dependence is increasingly relevant. In this study, the impact of the force field of the surfactant tri-n-butyl phosphate (TBP), as well as that of water, is investigated at a water/(n-hexane + surfactant) interface. Empirical charge scaling was employed to modulate the hydrophilicity of the surfactant. As anticipated, the relative hydrophilicity of TBP influences a number of properties, including the adsorbed concentrations of TBP at the interface, and macroscopic properties that result from hydrogen bonding interactions, such as interfacial tension and width. The dynamic properties of solvents at the interface are strongly modulated by the variation in hydrogen bond strength caused by different charge scaling of the TBP model. This includes the residence times of water at the interface, where stronger water-TBP hydrogen bonding causes long-lived residences. Interestingly, there are a number of features that are relatively insensitive to the TBP hydrophilicity. In one important case, the concentration of water-bridged TBP dimers was only impacted for the least hydrophilic model. As these dimeric species are the building block of surface protrusions that lead to water transport across the interface, this implies that collective organizational patterns and surface structures that derive from multiple driving forces (e.g. TBP hydrophilicity and organic solvent free energies of solvation) are less sensitive to individual force field parameters. Further, we note that competitive interactions can "cancel" the effects of changing TBP charge on interfacial properties. One example is the orientation and hydrogen bonding structure of interfacial water, where the direct TBP-water hydrogen bonding competes against the indirect TBP-induced interfacial roughness. In combination, these observations may assist future simulation studies in calibrating surfactant models to, or interpreting results of, a broad range of dynamic, structural and thermodynamic properties.
Computational Chemistry and Modeling
liquid/liquid interfaces molecular dynamics force field solvent extraction


text:
@implementation XFDialogAnimationUtil

+ (addAnimationEngineBlock)topToCenter {
    return ^float(UIView *view) {

        view.y = -view.height;

        POPSpringAnimation *springPosY=[POPSpringAnimation animationWithPropertyNamed:kPOPLayerPositionY];
        springPosY.fromValue = @(0);
        springPosY.toValue= @(view.maskView.centerY);
        springPosY.springBounciness=10;
        [view.layer pop_addAnimation:springPosY forKey:@"springPosY"];

        return 0;
    };
}

+ (addAnimationEngineBlock)centerToTop {
    return ^float(UIView *view) {
        POPSpringAnimation *springPosY=[POPSpringAnimation animationWithPropertyNamed:kPOPLayerPositionY];
        springPosY.toValue= @(-view.maskView.height);

        springPosY.springBounciness=10;
        POPSpringAnimation *springScaleXY=[POPSpringAnimation animationWithPropertyNamed:kPOPLayerScaleXY];
        springScaleXY.toValue=[NSValue valueWithCGPoint:CGPointMake(0.1, 0.1)];

        springScaleXY.springBounciness=20;
        [view.layer pop_addAnimation:springPosY forKey:@"springPosY"];
        [view.layer pop_addAnimation:springScaleXY forKey:@"springScaleXY"];

        return 0.5;
    };
}

@end

redpajama_set_name: RedPajamaGithub


10 things I'd do if I won the lottery & WIN £50 Lottoland credit!
I don't mean £10 or £100, I mean the jackpot – the sort of money that changes lives.
I've played the lottery for years now (check out Lottoland where you can bet on Lotto Plus and EuroMillionaire as well as international lotteries – scroll down to win £50 credit!) and although I've never won big money I haven't given up hope – because you've got to be in it to win it, right?
Here's what I'd do if I did win.
1. Absolutely nothing. If I won the sort of money that means I don't have to worry about money anymore I think the news would take a little while to digest. It might be tempting to rush out and start spending, but I think letting it sink in is probably a better idea.
2. Go on holiday. While letting the enormity of winning the jackpot sink in I'd book a holiday. A hot holiday. The sort of holiday with kids' clubs and baby sitting services so you can actually relax – the sort of holiday I haven't had since becoming a mum.
3. Pay off all our debts – and those of our family and friends. As a self employed stay-and-work-at-home mum with no paid holiday and eye watering nursery fees I can only dream what it must be like not to worry about money anymore. It sounds marvellous.
4. Buy a camper van. After hiring a VW California for Misery Guts's 40th birthday we're converts – the only thing is it cost £67,000 to buy new. Which is a bit out of our price range – unless we win the lottery, of course.
5. Install a wine fridge. You know the sort of one I mean – with shelves you can lay the bottles on and a glass door so they're not rolling around among milk and other awkward sized cartons at the bottom of the family fridge anymore.
6. Set up trust funds for the kids. Because camper vans and wine fridges are all very well, but we ought to think of the kids' futures too.
7. Buy Misery Guts an insulin pump. As a type 1 diabetic he injects insulin up to 15 times a day, but with a pump it goes directly into his body without the needles and puncture wounds. They're very expensive and although they are available on the NHS they're not easy to get. He's currently been on the waiting list for two years.
8. Learn to play the piano. I've always wanted to learn properly but have you seen the cost of lessons? Definitely not justifiable when you've got three kids and two at nursery.
9. See the Olympics in Japan in 2020. We lived in Tokyo in our early 20s and I've always wanted to go back, but five plane tickets to the other side of the world don't come cheap. The 2020 Olympics will take place over my 40th birthday and being there then would be an amazing way to celebrate.
10. Don't tell anyone! You might want to shout your new-found wealth from the rooftops but I reckon the less people who know the better.
I could easily come up with another 10 things I'd do if I won the lottery – and then another 10 – but these are the things I think I'd do first.
If you fancy being in with the chance of winning the jackpot we've teamed up with Lottoland to offer one lucky reader £50 credit to spend at Lottoland.
You can spend the credit on any lotteries of your choice – from the Irish Lotto to WorldMillions.
All you have to do to be in with the chance of winning is comment on this blog post saying what you'd spend the money on if you won big via the Rafflecopter form below.
The competition is open until midnight on Friday July 6, 2018 and entrants must be 18+. Terms and conditions apply. Good luck!
What would you do if you won the lottery? Any of the above, or something else? I'd love to know!
This post was written in collaboration with Lottoland.
towards a holiday to hawaii!
I'd buy a new house.
A much needed holiday somewhere nice.
I'd love to put money towards a holiday and to buy a house!