text:
lt's a bright sunny day and the sloping vineyards of Morey Saint Denis are in full leaf and looking at their best. I've just left Domaine Dujac, with celestial savours Iingering on my palate, and realize that there's a thirty-minute gap in my programme. Que faire? The famous Clos des Lambrays, one of Morey's four Grands Crus, is just around the corner and the wine would be well worth tasting. I don't have an appointment but the worst that could happen is a polite refusal. The gate is open, I knock on the bureau door, and a pleasant lady, saying that the gérant is away, kindly offers to let me taste the 2009.
I'm always a bit disconcerted by the Clos des Lambrays pale colour. The few times I've tasted it, it's always had a colour that's closer to a deep rosé than a full-blooded purple. Will the '09 be any different? And how important is depth of colour anyway?
2009 CLOS DES LAMBRAYS ****
A Iight crimson, this has a soft, reticent scent of wild strawberry, redcurrant, and violet. The flavour is of exceptional delicacy and fuller than the nose leads one to expect. There's a reprise of strawberry but a hint of wild cherry too. The aftertaste, with good minerality, is very delicate indeed, with tendrils of sub-flavour reaching out in different directions. It's a different kind of delicacy to that found in Chambolle wines – the most exquisite in all Burgundy – but that difference is hard to pin down. One thing is certain, this refined wine will need at least 8 years to come round and will evolve for a further decade at the very least.
I leave the Domaine still unsure about the essential nature of Clos des Lambrays but very much aware of its extreme subtlety and finesse. Some tasters who've sampled many vintages rate it very highly indeed, calling it a « classic wine » which « matures to perfection. » What I need, I tell myself, is a vertical tasting of top vintages!
I'm now on my way to pay my second visit to Domaine Jacques Frédéric Mugnier, which l'm now convinced is one of the region's very greatest estates. The Domaine not only owns choice plots in some of the most fabled vineyards of all; it also goes to almost superhuman lengths to coax forth the finest qualities inherent in each of them. Tasters who've followed their progress for far longer than I aver that every single year, even less propitious ones, brings fresh increments of excellence.
Until 2000 their total acreage amounted to just 4 hectares – a tiny estate indeed. But in that year the Domaine regained control over its 10-hectare Clos de la Maréchale, a fine Premier Cru at the southern end of Nuits Saint Georges. Over the previous 53 years it had been rented out under contract to the negociant house of Faiveley. At one stroke a tiny estate became a substantial one (at least by Burgundy standards).
M. Mugnier is a soft-spoken man, of average build, who conveys an impression of quiet resolution. Throughout the tasting that follows, we exchange impressions sotto voce, both of us trying to edge ever closer to an understanding of the essential nature of each successive growth. Most of my attention is focused on scrawling my impressions in my notebook, but so alert and attentive is M. Mugnier that I'm drawn into a murmured dialogue too. In some subtle way he coaxes forth your innermost thoughts on the matter. This in turn leads to the insight that this perfectionist man exerts a similar effect on each and every one of his wines, a kind of inductive approach to the fashioning and maturation of wine. How could they fail to unveil their deep-seated essences to such a winemaker?
2010 CHAMBOLLE MUSIGNY 1 ER CRU COMBE D'ORVEAU ***
Finesse is the keynote of this light-coloured wine, which exhales subtle scents of red rose, strawberry, and raspberry (tous les fruits rouges, as the French say). These carry through to the palate which, if light, is fat and of pronounced minerality. The gentle tannins promise a harmonious maturity around 2016-22.
2010 CHAMBOLLE MUSIGNY (blend of Village and Premiers Crus) ***
Noticeably darker, this has a full, noble aroma of red fruits, peony, and oriental spices. The lovely silky flavour is long and nuanced, with tannins giving a slightly gritty finish. Fuller than the previous wine, it should show best around 2018-24.
2010 CHAMBOLLE MUSIGNY 1 ER CRU LES FUEES ****
The robe is a vivid purple and the round, enveloping aroma evokes sumptuous black and red fruits and promises a velvety texture. The lovely flavour has multiple facets, ripe cherry to the fore. The finish is extremely long and spicy. A. superb wine to relish around 2020-32 – and probably beyond. Les Fuées lies immediately beside Bonnes Mares, one of the more powerful Grands Crus.
2010 CHAMBOLLE MUSIGNY 1 ER CRU LES AMOUREUSES ****(*)
Because of undigested malic acid and a fugitive hint of sulphur, this is altogether more backward. But one simply cannot miss the richness, concentration, and lurking power of this great wine. Ripe cherry and damson spring to mind. The flavour is packed with energy but it's still too early to form a complete impression of the wine's full delineation. The masterful aftertaste is full of substance and shows beautiful balance, even if the details don't show yet. Lots of minerality. Will improve for 30 years or more.
Les Amoureuses is one of the most sought-after of all Burgundies and, though only a Premier Cru, commands Grand Cru prices.
2010 BONNES MARES ****(*)
The colour is intense and the nose, still a bit sulphury, promises considerable volume and depth. The faint whiff of ginger comes from the oak. Still undergoing the malolactic fermentation, it is in a state of flux yet has a distinct centre of gravity. Even in this state of transition you cannot miss the volume, power, and complexity. A wine for the long term.
2010 MUSIGNY *****
This cherry-purple wine has a globular aroma that's pronouncedly mineral and packed with Pinot Noir fruit of the utmost ripeness. But if the Pinot traits are marked, the Musigny characteristics are even more in evidence: finesse, complexity, understated strength. The flavour is full and sappy and is reminiscent of raspberry, cherry, and pomegranate. And strikingly fresh. It's inevitable that so great a wine should be resolutely closed at this early stage but its greatness cannot be missed. The finish is firm and very mineral. Will improve for 30-40 years.
2010 NUITS SAINT GEORGES 1 ER CRU CLOS DE LA MARECHALE ***
This broad, muscular wine is of medium depth of colour and smells like damson, black cherry, leather, morel and truffle. It's faintly gamy but there's plenty of lush fruit too. The purposeful flavour is voluminous, with a reprise of those elements found on the nose, with the addition of dark chocolate. The crushed stone of the subsoil shows on the sweeping aftertaste. Best 2021-30 and doubtless beyond.
Though in a closed-up phase, this dark, assertive wine is full of substance and smells of black cherry, bilberry, liquorice, and truffle. The voluminous flavour fills the mouth with savage fruit while the finish, which opens out to include chocolate and plum, is persistent and full of nuances. Typically Nuits in its density, it has an underlying freshness too. The hint of prune and fig on the finish is testimony to the heat of the vintage and of the ripeness engendered about by that heat.
2009 MUSIGNY ****(*)
The Pinot Noir, which never gives black wines, can only achieve this exceptional depth of colour in the hottest of years. The nose is vast yet subtle, as round as a full moon. The masterful, homogeneous scent is a seamless meld of black cherry, graphite, sloe, and raspberry. The flavour, as powerful as that of an Hermitage, is mainly of black fruits, and is fresh and distinctly mineraI. The aftertaste comes in ripples. A massive wine, but one with poise and exceptional length.
M. Mugnier is a bit hesitant about it, as Burgundy growers always are when a wine is unwontedly full-bodied. "One can find such wines in Italy, in the Rhône" he murmurs.
I ask myself how Burgundy vintages now seen to be great – '69, '52, '47. etc. – looked when they were as young as these wines we're tasting now. Surely, in order to be able to age 30-60 years, they must have been powerfully structured· and dense at the very outset? And won't wines like this '09 Musigny gradually shed excess flesh and tannins as they age? We agree that this version at any rate, will grow increasingly classic as it matures. Great wines revert to type, slimming down when initially heavy and filling out if they start out light.
As if to shed more light on this puzzle M. Mugnier now uncorks two vintages of Chambolle Les Fuées, one of them classic (the '08), the other from the oven-hot 2009 vintage.
2009 CHAMBOLLE MUSIGNY 1 ER CRU LES FUEES ***
Richly-pigmented, densely aromatic, this smells mostly of black fruits including sloe. The flavour is packed with substance, suggesting black cherry, bilberry, and liquorice, and the finish is distinctly slatey. A stirringly full, concentrated wine – but not unmistakeably a Chambolle.
2008 CHAMBOLLE MUSIGNY 1 ER CRU LES FUEES ***(*)
The colour is lighter, the nose more buoyant and ethereal, suggesting a meld of red fruits and the most delicately-scented of flowers. A suspicion of mint too. The flavour is, quite simply, gorgeous, with a velvety texture and lots of finesse. But the refinement should not obscure the firm underlying structure. The finish is taut and very complex. Will be sublime around 2016-28.
I'm floating on air as I leave M. Mugnier. After such a tasting I must celebrate with a good lunch. The gods are on my side: I find myself outside a neat little restaurant I've never seen before. It has all the hallmarks of excellence: a shipshape appearance and a menu that's not only well-priced but offers genuinely imaginative, appetising dishes.
I enter and soon am seated in a surprisingly elegant (in so small and rustic a village) dining room, being served a delicious white wine by a young man who clearly could teach some Michelin-starred sommeliers a thing or two. The first course is most toothsome: a small slab of excellent foie gras through which run threads of tender oxtail meat. A first-rate mini-salad rests beside it. The main course is even better: delectable. lightly smoked cod with a wreath of wild asparagus deep-fried in batter. The cod flesh slides into buttery flakes at the lightest touch from the fork. The dessert frankly amazes me. Sweet apples have been thinly sliced and then formed into roses – three of them. Sweetly acidulous, and accompanied by a fine home-made ice-cream, they bring a memorable lunch to an end. The cost: 18 Euros, or less than many Paris three-star hotels charge for a mediocre breakfast.
The place is called Le Chambolle and is in the heart of Chambolle-Musigny.
Château de la Tour are the biggest proprietors in the Grand Cru Clos de Vougeot. with fully 5 hectares of vines. Most of the plants are old, or even very old, and yields are said to be as low as 29 hectolitres per hectare , or less than a half-bottle per vine. These factors are crucial. While the Cabernet-Sauvignon can give black, concentrated wines even at yields of 50 hl/ha, the unique varietal character of the Pinot Noir gets diluted when either bountiful nature, or a greedy vigneron, "fait pisser les vignes".
Owner is Pierre Labet, who says: "My dream: to recreate the wines of yesteryear." He refers to an era when vines gave very low yields indeed, giving wines so concentrated that the dregs left in a glass were more like congealed blood than a faint pink blush. "I was brought up on Nuits wines from 1895. We never drank anything younger than 50 years old!"
If he can realize this dream – and a handful of other domaines have already done so – then Burgundy as a region will take yet another step towards perfection. One sign of Labet's commitment to excellence is his policy of tasting each cuvée every morning and evening. This kind of vigilance allows incipient problems to be tackled before they can take hold.
In addition to his domaine-bottled Vougeot wines, M. Labet also produces a range of mostly Côte de Beaune reds and whites under the François Labet label.
A tasting from the latter range shows that a 2010 Bourgogne Blanc has a fresh scent of greengage and apple, with crisp acidity giving verve and precision. A 2010 Beaune Marconnets is naturally richer, both in pigment and savour, and is given zing by fresh acidity.
A '10 Meursault is still broader and fuller, with typical Meursault fatness, while a '10 Savigny 1er Cru Vergelesses is best of all among the whites, with an expressive. slightly waxy scent of white peach and white clay and a smooth, persistent finish.
I am impressed by the intense colour of the '10 Bourgogne Rouge (it has more colour than many a Premier Cru) and its rich, almost beefy flavour shows an unwonted degree of concentration for a generic red Burgundy. Several other reds show very well, most notably a '10 Beaune 1er Cru Coucherais, but the most complete of the series is:
2010 GEVREY CHAMBERTIN VIEILLES VIGNES ***
The plum and blackberry nose is still inchoate but unmistakeably dense while the fullish flavour shows not only persistence and a marked Gevrey character, but also real depth of flavour. Concentrated enough to accompany red meats, and even lighter game, it will drink well for at least 8 years. It is made from three plots of vines with an average age of 60 years.
Now to the Domaine wines.
2010 CLOS DE VOUGEOT ***(*)
This dark wine has a voluminous aroma of old-vine depth, of mingled red and black fruits and Iiquorice. The flavour shows excellent concentration and is full of Pinot Noir richness and intensity, in tandem with archetypical Clos de Vougeot rigour and complexity. The finish is long and mineraI, with all sorts of nuances, and the wine clearly won't peak for 20 years at least. It will then improve for many more years.
2010 CLOS DE VOUGEOT VIEILLES VIGNES ****(*)
Still darker, this super cuvée from century-old vines has a glorious, commanding scent of black cherry, chocolate, strawberry, and crème de framboise. The superb flavour presents these elements in tactile form, and the highly mineral aftertaste keeps on unfolding new sub-flavours that explode on the palate the way fireworks scintiIIate in the sky. A great wine that will live for decades.
At moments like this, I find myself wishing for a miracle, whereby the brilliant sample I'm tasting now could instantly be transformed into the state it will be in when fully mature, in some 40 years' time.
Dream on, I tell myself…
l'm now at Etienne Sauzet in Puligny-Montrachet to taste the 2009s. As always, one starts with the generic Bourgogne Blanc and works one's way through a series of Premiers Crus, each showing its own unique characteristics. and ends with several Grands Crus. As with all top vignerons, Gérard Boudot accords the same care and attention to the simplest wine as to the most prestigious.
2009 BOURGOGNE BLANC * (from two plots of old vines)
The clean-cut Chardonnay nose conjures up white rose and elderflower, with a hint of crab apple on the palate. The aftertaste is faintly chalky. To enjoy with seafood over the next 2-3 years.
2009 CHASSAGNE MONTRACHET ** (from a lieu-dit called Les Enseigneurs, not far from Bâtard Montrachet)
A pale yellow-gold with a green tinge, this has a crisp and precise aroma and flavour suggestive of greengage, elderflower, and apple. The persistent aftertaste is marked by the stony (limestone) subsoil. 2014-18.
2009 PULIGNY MONTRACHET ** (from 7 plots)
Smelling of hazelnut, honey, and white peach, this "Village" is well-structured and persistent. The minerality on the finish comes mostly from those plots closest to the neighbouring commune of Meursault, says M. Boudot.
2009 PULIGNY 1 ER CRU LA GARENNE ***
The nose is loaded with chlorophyll scents. with hints of fennel too. Apple aromas soon make their presence felt. White peach and elderflower creep into the flavour, which has several strands which continue to expand in the mouth. A delicate wine. « La Garenne has the poorest soil in all Puligny,» says M. Boudot. as if in explanation of this fragility.
2009 PULIGNY 1 ER CRU REFERTS ***(*)
A totally different wine, from lower slopes, showing much more richness. The full, grapy nose suggests russet apple and there's a reprise of apple in the mouth. The rich, voluminous flavour is long and there's a suggestion of bay leaf on the finish, which shows a steely firmness. This demands to be kept some 4-5 years before being enjoyed into the 2020s.
2009 PULlGNY 1 ER CRU FOLATIERES ***(*) (from 2 plots)
The more complex the wine, the more nuanced the colour. This has a shimmering green-gold hue, while the subtle, very expressive aroma calls to mind greengage, lime peel, white peach, and chlorophyll. The flavour is similarly crisp and expressive, and the aftertaste comes in waves turning towards russet pear at the very finish.
This should improve over a dozen years.
2009 PULIGNY 1 ER CRU CHAMP CANET **** (from 1.5 hectares of 60-year vines next to Les Perrières)
This luminious wine has a noble, concentrated aroma, of real weight, suggesting ripe greengage and chlorophyll. Rich and lushly fruity on the palate, it has a long, nuanced finish which flirts with heaviness without reaching it. There's a hint of crushed stone on the aftertaste. A 15-year wine.
2009 PULIGNY 1 ER CRU COMBETTES ****
An intense green-gold, Combettes has a big, thrustful aroma of apricot, russet apple, and chlorophyll. It's rich and grapy in the mouth ; ample minerality stipples the aftertaste. A big, balanced wine of great power (easy to take for a Grand Cru if tasted blind), it won't peak before end-decade and will continue to improve for a further 10 years or so.
2009 BATARD MONTRACHET ****(*) (from one plot in Puligny, one in Chassagne)
The rich, globular scent swirls out of the glass, evoking orange blossom and white peach, with a subtle hint of pineapple and acacia honey. It's a blossomy scent, with fugitive suggestions of elderflower and yellow rose. The flavour is silky, close-knit, and very long, with red delicacy showing on the protracted finish. The acidity is of the kind found in a perfect eating apple. This will be splendid with lobster or langoustine around 2020-30.
"We picked early, and quickly, in '09 to avoid overripeness. As you know, Bâtard can be on the heavy side sometimes and I feel we've avoided this," says M.Boudot. I agree, reflecting that this is an especially brilliant achievement in so hot a vintage as 2009.
2009 CHEVALIER MONTRACHET ***** (from white marne at the top end of the vineyard, where the soil is especially poor)
Faintly paler than the Bâtard (Chevalier is almost always a Iighter-structured but more refined wine) this sublime Grand Cru has a soaring scent of white rose, poire William, and elderflower. The subtle flavour, superbly balanced, is precise and long. The texture is exceptionally fine. A true Chevalier-Montrachet – the most refined of white Burgundies that will repay long keeping. To enjoy with the finest fish – scallops, sole, turbot, John Dory – or the most delicate of veal.
<< Back to : A taste of Burgundy – Part I


text:
German Federal Court of Justice upholds mass claims collection model in ground-breaking ruling
In a ground-breaking ruling of July 13, 2021, the German Federal Court of Justice, the Bundesgerichtshof (BGH), upheld a mass claims collection or 'Sammelklage-Inkasso' model that was primarily directed at enforcing group claims in court, rather than out of court[1].
What was the case about?
The ruling relates to a case concerning a mass claims structure that was set up in the aftermath of the Air Berlin insolvency in 2017 to help enforce air passenger claims. In this particular case, the claimant, a limited liability company registered as a legal services provider for debt collections, or 'Inkassodienstleister', collected claims, by way of assignment, from Air Berlin customers whose flights were cancelled as a result of the insolvency.
Grouping together multiple Air Berlin customer claims, the claimant then sued the former executive director of Air Berlin for repayment of the flight costs on the grounds of the alleged late filing of the insolvency.
Both the German First-Instance District Court and the Court of Appeal dismissed these claims, based namely on an assumed violation of the German Legal Services Act, the Rechtsdienstleistungsgesetz (RDG). On appeal, the BGH overruled the second-instance judgment and sent the case back to the Court of Appeal. In reviewing the disputed mass claim collection model from different legal angles, the BGH found the model set up by the claimant to be in line with the German RDG in all respects.
The BGH decision – mass claims collection model covered by debt collection permit
The BGH ruling held that a debt collector who plans to go to court right away to enforce claims, acts within the boundaries of its debt collection permit under the German RDG[2] regardless of whether individual or group claims are concerned.[3]
Noting that the permissibility of mass claim collection models has been highly debated in German jurisprudence, the BGH followed the more liberal stance, rejecting the prevailing view to date among German first-instance courts that have ruled against such cases. Notably, the BGH ruling placed the freedom to conduct business in Article 12 of the German Basic Law (Grundgesetz) at the center of its reasoning and confirmed that a narrow reading of "out-of-court legal services", permitted under the collection permit, was not justified as this would have disproportionately curtailed the debt collectors' fundamental freedom to conduct business.
Importantly, the BGH did not see a considerably heightened risk of unqualified legal services springing from the mass claims collection model, given that any registered legal services provider is required to submit certain professional legal qualifications to the registration authority, and that qualified attorneys-at-law are legally required to be involved when the case goes to court.
The BGH decision – mass claims collection model does not create conflicts of interest
The BGH went on to clarify that the mass claim collection model does not create conflicts of interest.[4] The BGH emphasized that the interests of firstly, the debt collector and its customers, and secondly, the interests of the individual customers within the group claim, are in principle aligned because they all share a common interest in achieving the most effective enforcement possible.
The BGH argued that the advantages of group enforcements outweigh any residual risks related to varying degrees of enforcement chances posed by claims bundled together in a group settlement. The residual risk may be that claims with weaker enforcement chances might negatively impact claims with stronger enforcement chances, however the advantages include the sharing of cost risks and enhanced bargaining power.
The BGH also held that the more parallel the claims, the lower the risk. By contrast, the more diverse the claims, the higher the risk. Nonetheless, these risks may be avoided by forming groups of sufficiently similar claims.
Any remaining differences in this sense would, according to the BGH, be negligible and therefore not justify invalidating the assignment of the customers' claims to the debt collector.
In conclusion – why is this ruling important?
The importance of the BGH's ruling cannot be overstated: it is not only a victory for legal services providers, such as debt collectors, but also significantly improves enforcement opportunities for consumers or companies.
[1] BGH Judgment, July 13, 2021, II ZR 84/20.
[2] German Legal Services Act (Rechtsdienstleistungsgesetz/RDG), Sections 10 (1), sentence 1 no. 1; 2 (2) sentence 1.
[3] BGH, Judgment, July 13, 2021, II ZR 84/20, Paras. 12 et seq.
[4] German Legal Services Act (Rechtsdienstleistungsgesetz/RDG), Section 4; BGH, Judgment, July 13, 2021, II ZR 84/20, paras. 45 et seq.
août 10 2021
Dr. Alex Petrasincu
Dr. Manuel Knebelsberger
Antitrust et concurrence
janv. 14 2022
Google finally amends Choice Screen remedy to prevent non-compliance proceedings in EU Android case
The AG's Opinion for the EUCJ in the Dutch air cargo litigation: the bigger picture
France, United Kingdom, Netherlands, Sweden, Belgium
FinTech et paiements électroniques : entre privacy et concurrence, l'Autorité de la concurrence publie les conclusions de son enquéte sectorielle
France, United Kingdom, Belgium
Google Ads to pay €1.27M antitrust damages for squeezing directory enquiry services provider, French court rules
France, United Kingdom

redpajama_set_name: RedPajamaCommonCrawl


text:
<?php

class Google_Service_CloudRuntimeConfig_ListVariablesResponse extends Google_Collection
{
  protected $collection_key = 'variables';
  public $nextPageToken;
  protected $variablesType = 'Google_Service_CloudRuntimeConfig_Variable';
  protected $variablesDataType = 'array';

  public function setNextPageToken($nextPageToken)
  {
    $this->nextPageToken = $nextPageToken;
  }
  public function getNextPageToken()
  {
    return $this->nextPageToken;
  }
  public function setVariables($variables)
  {
    $this->variables = $variables;
  }
  public function getVariables()
  {
    return $this->variables;
  }
}

redpajama_set_name: RedPajamaGithub


My name is Jennifer Austin-Walker and I have worked within the caring field for over 30 years. I have been privileged to work with various client groups and individuals. As a result, I have gained experience, knowledge and skills which have been invaluable during my career. In applying for this post I look forward to providing the best care and support for the clients with whom I will work.
I have experience in residential care and home care for older people where I would support clients with personal care, social activities, having conversations, shopping, paying bills and other activities which they required. The client's needs and desires were regularly assessed in order to maintain a up to date care plan which would inform the care worker, other health professionals and family. Providing a person centred approach to the work that I do is essential to the wellbeing of people with whom I will work.
My approach to life and situations is one of positivity which is something I convey in the work that I do. I encourage people that I work with and care for, to enjoy life. I am self motivated, caring, with integrity and trustworthiness, as evidence by my previous roles.


We would like to have a 1d and 7d graphs for the same variable on the same dashboard side by side. It this possible?
No, there's nothing currently to do that though it's possible to implement.
If you feel it'd be a useful addition, can you file a bug with the feature request and use case so that it can be tracked?
Provide an answer of your own, or ask Luis Rodrigues for more information if necessary.


A grandmother of 23 died and her husband suffered smoke inhalation after a house fire in Sydney's east on Thursday morning.
Emergency services were called about 6.20am to Carrington Road at Waverley, where they found a semi-detached house alight.
The first fire crews arrived to find thick smoke billowing from the rear of the house, a Fire and Rescue NSW spokesman said.
The semi-detached house was well engulfed in fire, the spokesman said, and first responders quickly called for back-up.
One of Mrs Yazigi's grandsons, who lives two doors down, said he was woken at 6am to the sound of sirens.
"Obviously [I've] seen the smoke come out grandparents' place, put on clothes like a madman and raced down and saw my grandfather, hysterical," Anthony Mitry said.
Anthony Mitry said his grandfather was not coping well after the house fire.
"I tried to console him and tried to understand what was going on, and was greeted with the bad news, unfortunately."
Even though fire crews were quick to enter the home, NSW Ambulance acting duty operations manager Paul Sweetland said there was nothing paramedics could do for Mrs Yazigi.
"On arrival at the scene, ambulance treated an 86-year-old male for smoke inhalation, who they transported to Prince of Wales Hospital in a stable condition," he said.
"Ambulance were later informed by Fire and Rescue NSW that unfortunately there was a deceased person within the building."
The owner of the property in Waverley is consoled after an elderly woman died in a fire in her home.
Mr Sweetland said the male patient was expected to make a "good recovery" from a medical point of view.
"He's being looked after by the doctors of Prince of Wales emergency, and Prince of Wales Hospital have been able to give the patient other support services," he said.
Mr Mitry said his grandfather was "not coping very well", but he was surrounded by family at the hospital.
"He was woken up by thick smoke, and couldn't do anything to find her or save her," he said.
Five fire crews were at the scene, battling the fierce blaze.
Five fire crews remained on the scene into the morning as they worked to control the smouldering fire in the roof space.
It was unclear whether the neighbouring semi-detached house needed to be evacuated.
Officers from the Eastern Suburbs Police Area Command have begun an investigation and a report will be prepared for the coroner.
Mr Mitry said his Mrs Yazigi's health was not the best, so it was unclear what had caused her death.
"[My grandfather] believes she must have gone into the lounge room and tried to start the heater," he said. "Whether she collapsed or not we don't know.
"She's quite a frail woman, not as mobile as you or me, but she's in a better place now."


Users and Groups – /etc/passwd, /etc/group, su, sudo, chsh, useradd, gpasswd, etc.
usermod – modify userid info, e.g. userid, comment, UID, GID, HOME, etc.
The GECOS/comments/name field gets its GECOS name because it was used on the original Unix systems to store GECOS mainframe account information for printing.
When a system has shadow passwords enabled (the default), the password field in /etc/passwd is replaced by an x and the user's real encrypted password is stored in the second field of /etc/shadow.
Each line in /etc/shadow contains the user's login userid, their encrypted password, and several fields relating to password expiry.
Used to create a new login account.
Also creates a group with the same name.
Usually the defaults are correct, but options let you change any of the information to be stored in the passwd and group files.
Sometimes called adduser, but sometimes adduser is a different program with different options (e.g. Ubuntu).
Remove an account from the password and group files.
By default, does not remove the HOME directory or any files under it.
To actually remove the home directory, you must use the -r option!
if you forget -r, you will leave a home directory with no owner!
drwx------   2 redshirt redshirt 4096 Nov 20 02:38 .
drwxr-xr-x. 13 root     root     4096 Nov 20 02:38 ..
drwx------   2  508  509 4096 Nov 20 02:38 .
drwxr-xr-x. 13 root root 4096 Nov 20 02:38 ..
drwx------   2 goldshirt goldshirt 4096 Nov 20 02:38 .
drwxr-xr-x. 14 root      root      4096 Nov 20 02:47 ..
Change any of the information about a user account. This command changes the stored information about the account, usually kept in the password and group files.
The command modifies each account attribute separately. For example: Changing the name of an account only changes its name. It doesn't change the groups for that user, nor does it change the home directory.
Modifying user account information does not always automatically move or modify all the files owned by the account in the file system. If you change some account information, you may still have to walk the entire file system to find files owned by the old account and change them to match the new values you have set.
Using both the -d and -m options, the usermod command is able to both change and move a home directory and all the files under it.
You have to exit all shells for a user (e.g. exit from all su or sudo) before you can change that user's accounting information.
The last argument on the usermod command line must always be the login name of the existing account you want modified. Never put a new account name or directory last. RTFM!
RTFM: Changing the HOME directory with -d changes only the field in /etc/passwd; it does not actually move the old HOME directory to the new location unless you also give -m.
If you have already used -d without using -m, you can't do the command a second time with -m – it will say "nothing changed", since you have already changed the name of the HOME in the password file. To do the command properly, you first have to put things back the way they were by using -d (without -m) to undo the change you made, then use -d with -m to redo the change.
Every file system object has "group" permissions; if you are not the owner of the object but are in that group, group permissions apply to you.
File system objects have only one owner and can be in only one group.
Logged in users can be "in" (members of) multiple groups.
BUT: At login, every user is given an initial group GID from the passwd file.
A user will belong to other groups (supplementary groups), if the user is a member of those groups in the /etc/group file.
When a system has shadow passwords enabled (the default), the password field in /etc/group is replaced by an x and the user's real encrypted password is stored in /etc/gshadow.
Starts a subshell as the new user, with that user's privileges.
Exiting the subshell goes back to the previous shell and previous user.
Remember to exit the subshell; don't keep nesting more and more subshells!
If you don't give a userid, it assumes you want to become the root user.
Ordinary (non-root) users need to enter the password for the new account.
A dash - or --login option (options must be surrounded by spaces) means use a full login shell that clears the environment, sets groups and goes to the specified user's home directory as if the user had just logged in.
Without the full login, the command will set privileges but will leave most of the existing environment unchanged, including an unchanged PATH and unchanged current directory (that may not grant the new user any permissions!).
Without the --login function, you get a new shell with new permissions but much of your existing shell environment and your current directory are unchanged. You may not have a $PATH that includes system administration commands.
$ whoami ; pwd ; echo "$PATH"
# whoami ; pwd ; echo "$PATH"
Execute a single command with other (usually root) privileges.
Safer way to do root tasks (avoids running a whole shell as root).
The password you type for sudo is your account password, not the root password.
The root account can use the visudo command to update file /etc/sudoers with the list of who is allowed to use sudo and which commands they are allowed to run.
For most actions that involve root privilege, use the sudo command to make the privilege change just for that one command. Do not start a root subshell (e.g. using su) until you have more experience. Mistakes made in a root subshell can destroy your system!
If you do start a full subshell using the su or sudo -s commands, remember to exit your subshell to return to your previous account. Don't keep layering multiple subshells inside each another.
These commands deal with both the user/owner and the groups/group.
The match between your logged-in user/groups and the file system owner/group determines the permissions you have on a file system object.
The id command tells you everything about your logged-in account.
On SELinux systems, you are also shown information about your security context.
The command that changes the owner and/or group of a file system object (e.g. of a file, directory, etc.) is chown. Only the root user can change the owner of an object. The owner of an object can change the group of an object to any one of his/her list of groups.


text:
Plant a Tree for Carol
Carol Lenore (Hannem) Krause
April 23, 1941 ~ November 21, 2020 (age 79)
Carol Lenore (Hannem) Krause, 79, of Bemidji, passed away peacefully at home on November 21, 2020 surrounded by her loving family.
Carol Lenore Hannem was born April 23, 1941 in Bemidji, Minnesota to Olaf and Leonore (Thorp) Hannem. She attended Central Elementary School and graduated from Bemidji High School in 1959. She worked for Lutheran Brotherhood for a year and then worked at First Lutheran Church making bulletins and answering phone calls.
In 1961, she met Curtis Krause and they married on March 17, 1962. After getting married she worked at Gambles for about a year. Deciding she wanted to do something different she sought out a job at the Welfare Service where she was employed for the next five years. She was then employed with the State of Minnesota for 25 years. Carol was an avid reader, loved baking, fishing, and swimming. She also loved to travel and spend time with family.
Carol is survived by her daughters, Karen Krause and Kelly Krause, Bemidji, Minnesota, son Keith Krause, Bemidji, Minnesota, grandchildren Katelin, Kyle and Brady Krause and sister Lois (Carl) Schultz, Aitken, Minnesota. Carol was preceded in death by her parents Olaf and Leonore, husband, Curtis, brothers, Jim, Ronnie and Paul Hannem.
Private graveside services will be held Monday, November 30th, 10:30 am, Greenwood Cemetery, Bemidji, Minnesota.
Memorials are preferred to The National Library Services for the Blind and Physically Handicapped, Cancer Society-Bemidji Chapter and the Kitchigami Regional Librar
To send flowers to the family or plant a tree in memory of Carol Lenore (Hannem) Krause, please visit our floral store.
You can still show your support by sending flowers directly to the family, or by planting a memorial tree in the memory of Carol Lenore (Hannem) Krause


It is our goal to provide quality and cost-effective residential garbage collection services and recycling to every customer in our Service Area. County Waste and Recycling provides garbage and recycling services to municipalities, single-family homes, individual subscription services and homeowner associations across the Capital Region.
Lookup your personalized Residential pickup SCHEDULE here.
Please contact us to learn more about our garbage and recycling rates and to schedule your waste and recycling removal service!
Check out County Waste and Recycling's convenient Recycling Guidelines for specific items that can and cannot be included in our curbside recycling program.
At County Waste, we provide a cart on wheels for your households refuse that you wheel to the curb each week. Our convenient roll carts feature large wheels for easy maneuverability, and provide a safe and secure place for your residential waste between pickup dates. Our residential roll carts are also available in a range of capacities allowing you to choose the size that best fits your residential waste collection needs.
Please place carts at the end of your driveway the night before.


text:
#ifndef _SAM4L_SCIF_COMPONENT_
#define _SAM4L_SCIF_COMPONENT_

/* ========================================================================== */
/**  SOFTWARE API DEFINITION FOR SCIF */
/* ========================================================================== */
/** \addtogroup SAM4L_SCIF System Control Interface */
/*@{*/

#define SCIF_I7149
#define REV_SCIF                    0x130

/* -------- SCIF_IER : (SCIF Offset: 0x000) ( /W 32) Interrupt Enable Register -------- */
#define SCIF_IER_OFFSET             0x000        /**< \brief (SCIF_IER offset) Interrupt Enable Register */
#define SCIF_IER_RESETVALUE         0x00000000   /**< \brief (SCIF_IER reset_value) Interrupt Enable Register */

#define SCIF_IER_OSC0RDY_Pos        0            /**< \brief (SCIF_IER) OSC0 Ready */
#define SCIF_IER_OSC0RDY            (0x1u << SCIF_IER_OSC0RDY_Pos)
#define SCIF_IER_DFLL0LOCKC_Pos     1            /**< \brief (SCIF_IER) DFLL0 Lock Coarse */
#define SCIF_IER_DFLL0LOCKC         (0x1u << SCIF_IER_DFLL0LOCKC_Pos)
#define SCIF_IER_DFLL0LOCKF_Pos     2            /**< \brief (SCIF_IER) DFLL0 Lock Fine */
#define SCIF_IER_DFLL0LOCKF         (0x1u << SCIF_IER_DFLL0LOCKF_Pos)
#define SCIF_IER_DFLL0RDY_Pos       3            /**< \brief (SCIF_IER) DFLL0 Ready */
#define SCIF_IER_DFLL0RDY           (0x1u << SCIF_IER_DFLL0RDY_Pos)
#define SCIF_IER_DFLL0RCS_Pos       4            /**< \brief (SCIF_IER) DFLL0 Reference Clock Stopped */
#define SCIF_IER_DFLL0RCS           (0x1u << SCIF_IER_DFLL0RCS_Pos)
#define SCIF_IER_DFLL0OOB_Pos       5            /**< \brief (SCIF_IER) DFLL0 Out Of Bounds */
#define SCIF_IER_DFLL0OOB           (0x1u << SCIF_IER_DFLL0OOB_Pos)
#define SCIF_IER_PLL0LOCK_Pos       6            /**< \brief (SCIF_IER) PLL0 Lock */
#define SCIF_IER_PLL0LOCK           (0x1u << SCIF_IER_PLL0LOCK_Pos)
#define SCIF_IER_PLL0LOCKLOST_Pos   7            /**< \brief (SCIF_IER) PLL0 Lock Lost */
#define SCIF_IER_PLL0LOCKLOST       (0x1u << SCIF_IER_PLL0LOCKLOST_Pos)
#define SCIF_IER_RCFASTLOCK_Pos     13           /**< \brief (SCIF_IER) RCFAST Lock */
#define SCIF_IER_RCFASTLOCK         (0x1u << SCIF_IER_RCFASTLOCK_Pos)
#define SCIF_IER_RCFASTLOCKLOST_Pos 14           /**< \brief (SCIF_IER) RCFAST Lock Lost */
#define SCIF_IER_RCFASTLOCKLOST     (0x1u << SCIF_IER_RCFASTLOCKLOST_Pos)
#define SCIF_IER_AE_Pos             31           /**< \brief (SCIF_IER) Access Error */
#define SCIF_IER_AE                 (0x1u << SCIF_IER_AE_Pos)
#define SCIF_IER_MASK               0x800060FFu  /**< \brief (SCIF_IER) MASK Register */

/* -------- SCIF_IDR : (SCIF Offset: 0x004) ( /W 32) Interrupt Disable Register -------- */
#define SCIF_IDR_OFFSET             0x004        /**< \brief (SCIF_IDR offset) Interrupt Disable Register */
#define SCIF_IDR_RESETVALUE         0x00000000   /**< \brief (SCIF_IDR reset_value) Interrupt Disable Register */

#define SCIF_IDR_OSC0RDY_Pos        0            /**< \brief (SCIF_IDR) OSC0 Ready */
#define SCIF_IDR_OSC0RDY            (0x1u << SCIF_IDR_OSC0RDY_Pos)
#define SCIF_IDR_DFLL0LOCKC_Pos     1            /**< \brief (SCIF_IDR) DFLL0 Lock Coarse */
#define SCIF_IDR_DFLL0LOCKC         (0x1u << SCIF_IDR_DFLL0LOCKC_Pos)
#define SCIF_IDR_DFLL0LOCKF_Pos     2            /**< \brief (SCIF_IDR) DFLL0 Lock Fine */
#define SCIF_IDR_DFLL0LOCKF         (0x1u << SCIF_IDR_DFLL0LOCKF_Pos)
#define SCIF_IDR_DFLL0RDY_Pos       3            /**< \brief (SCIF_IDR) DFLL0 Ready */
#define SCIF_IDR_DFLL0RDY           (0x1u << SCIF_IDR_DFLL0RDY_Pos)
#define SCIF_IDR_DFLL0RCS_Pos       4            /**< \brief (SCIF_IDR) DFLL0 Reference Clock Stopped */
#define SCIF_IDR_DFLL0RCS           (0x1u << SCIF_IDR_DFLL0RCS_Pos)
#define SCIF_IDR_DFLL0OOB_Pos       5            /**< \brief (SCIF_IDR) DFLL0 Out Of Bounds */
#define SCIF_IDR_DFLL0OOB           (0x1u << SCIF_IDR_DFLL0OOB_Pos)
#define SCIF_IDR_PLL0LOCK_Pos       6            /**< \brief (SCIF_IDR) PLL0 Lock */
#define SCIF_IDR_PLL0LOCK           (0x1u << SCIF_IDR_PLL0LOCK_Pos)
#define SCIF_IDR_PLL0LOCKLOST_Pos   7            /**< \brief (SCIF_IDR) PLL0 Lock Lost */
#define SCIF_IDR_PLL0LOCKLOST       (0x1u << SCIF_IDR_PLL0LOCKLOST_Pos)
#define SCIF_IDR_RCFASTLOCK_Pos     13           /**< \brief (SCIF_IDR) RCFAST Lock */
#define SCIF_IDR_RCFASTLOCK         (0x1u << SCIF_IDR_RCFASTLOCK_Pos)
#define SCIF_IDR_RCFASTLOCKLOST_Pos 14           /**< \brief (SCIF_IDR) RCFAST Lock Lost */
#define SCIF_IDR_RCFASTLOCKLOST     (0x1u << SCIF_IDR_RCFASTLOCKLOST_Pos)
#define SCIF_IDR_AE_Pos             31           /**< \brief (SCIF_IDR) Access Error */
#define SCIF_IDR_AE                 (0x1u << SCIF_IDR_AE_Pos)
#define SCIF_IDR_MASK               0x800060FFu  /**< \brief (SCIF_IDR) MASK Register */

/* -------- SCIF_IMR : (SCIF Offset: 0x008) (R/  32) Interrupt Mask Register -------- */
#define SCIF_IMR_OFFSET             0x008        /**< \brief (SCIF_IMR offset) Interrupt Mask Register */
#define SCIF_IMR_RESETVALUE         0x00000000   /**< \brief (SCIF_IMR reset_value) Interrupt Mask Register */

#define SCIF_IMR_OSC0RDY_Pos        0            /**< \brief (SCIF_IMR) OSC0 Ready */
#define SCIF_IMR_OSC0RDY            (0x1u << SCIF_IMR_OSC0RDY_Pos)
#define SCIF_IMR_DFLL0LOCKC_Pos     1            /**< \brief (SCIF_IMR) DFLL0 Lock Coarse */
#define SCIF_IMR_DFLL0LOCKC         (0x1u << SCIF_IMR_DFLL0LOCKC_Pos)
#define SCIF_IMR_DFLL0LOCKF_Pos     2            /**< \brief (SCIF_IMR) DFLL0 Lock Fine */
#define SCIF_IMR_DFLL0LOCKF         (0x1u << SCIF_IMR_DFLL0LOCKF_Pos)
#define SCIF_IMR_DFLL0RDY_Pos       3            /**< \brief (SCIF_IMR) DFLL0 Ready */
#define SCIF_IMR_DFLL0RDY           (0x1u << SCIF_IMR_DFLL0RDY_Pos)
#define SCIF_IMR_DFLL0RCS_Pos       4            /**< \brief (SCIF_IMR) DFLL0 Reference Clock Stopped */
#define SCIF_IMR_DFLL0RCS           (0x1u << SCIF_IMR_DFLL0RCS_Pos)
#define SCIF_IMR_DFLL0OOB_Pos       5            /**< \brief (SCIF_IMR) DFLL0 Out Of Bounds */
#define SCIF_IMR_DFLL0OOB           (0x1u << SCIF_IMR_DFLL0OOB_Pos)
#define SCIF_IMR_PLL0LOCK_Pos       6            /**< \brief (SCIF_IMR) PLL0 Lock */
#define SCIF_IMR_PLL0LOCK           (0x1u << SCIF_IMR_PLL0LOCK_Pos)
#define SCIF_IMR_PLL0LOCKLOST_Pos   7            /**< \brief (SCIF_IMR) PLL0 Lock Lost */
#define SCIF_IMR_PLL0LOCKLOST       (0x1u << SCIF_IMR_PLL0LOCKLOST_Pos)
#define SCIF_IMR_RCFASTLOCK_Pos     13           /**< \brief (SCIF_IMR) RCFAST Lock */
#define SCIF_IMR_RCFASTLOCK         (0x1u << SCIF_IMR_RCFASTLOCK_Pos)
#define SCIF_IMR_RCFASTLOCKLOST_Pos 14           /**< \brief (SCIF_IMR) RCFAST Lock Lost */
#define SCIF_IMR_RCFASTLOCKLOST     (0x1u << SCIF_IMR_RCFASTLOCKLOST_Pos)
#define SCIF_IMR_AE_Pos             31           /**< \brief (SCIF_IMR) Access Error */
#define SCIF_IMR_AE                 (0x1u << SCIF_IMR_AE_Pos)
#define SCIF_IMR_MASK               0x800060FFu  /**< \brief (SCIF_IMR) MASK Register */

/* -------- SCIF_ISR : (SCIF Offset: 0x00C) (R/  32) Interrupt Status Register -------- */
#define SCIF_ISR_OFFSET             0x00C        /**< \brief (SCIF_ISR offset) Interrupt Status Register */
#define SCIF_ISR_RESETVALUE         0x00000000   /**< \brief (SCIF_ISR reset_value) Interrupt Status Register */

#define SCIF_ISR_OSC0RDY_Pos        0            /**< \brief (SCIF_ISR) OSC0 Ready */
#define SCIF_ISR_OSC0RDY            (0x1u << SCIF_ISR_OSC0RDY_Pos)
#define SCIF_ISR_DFLL0LOCKC_Pos     1            /**< \brief (SCIF_ISR) DFLL0 Lock Coarse */
#define SCIF_ISR_DFLL0LOCKC         (0x1u << SCIF_ISR_DFLL0LOCKC_Pos)
#define SCIF_ISR_DFLL0LOCKF_Pos     2            /**< \brief (SCIF_ISR) DFLL0 Lock Fine */
#define SCIF_ISR_DFLL0LOCKF         (0x1u << SCIF_ISR_DFLL0LOCKF_Pos)
#define SCIF_ISR_DFLL0RDY_Pos       3            /**< \brief (SCIF_ISR) DFLL0 Ready */
#define SCIF_ISR_DFLL0RDY           (0x1u << SCIF_ISR_DFLL0RDY_Pos)
#define SCIF_ISR_DFLL0RCS_Pos       4            /**< \brief (SCIF_ISR) DFLL0 Reference Clock Stopped */
#define SCIF_ISR_DFLL0RCS           (0x1u << SCIF_ISR_DFLL0RCS_Pos)
#define SCIF_ISR_DFLL0OOB_Pos       5            /**< \brief (SCIF_ISR) DFLL0 Out Of Bounds */
#define SCIF_ISR_DFLL0OOB           (0x1u << SCIF_ISR_DFLL0OOB_Pos)
#define SCIF_ISR_PLL0LOCK_Pos       6            /**< \brief (SCIF_ISR) PLL0 Lock */
#define SCIF_ISR_PLL0LOCK           (0x1u << SCIF_ISR_PLL0LOCK_Pos)
#define SCIF_ISR_PLL0LOCKLOST_Pos   7            /**< \brief (SCIF_ISR) PLL0 Lock Lost */
#define SCIF_ISR_PLL0LOCKLOST       (0x1u << SCIF_ISR_PLL0LOCKLOST_Pos)
#define SCIF_ISR_RCFASTLOCK_Pos     13           /**< \brief (SCIF_ISR) RCFAST Lock */
#define SCIF_ISR_RCFASTLOCK         (0x1u << SCIF_ISR_RCFASTLOCK_Pos)
#define SCIF_ISR_RCFASTLOCKLOST_Pos 14           /**< \brief (SCIF_ISR) RCFAST Lock Lost */
#define SCIF_ISR_RCFASTLOCKLOST     (0x1u << SCIF_ISR_RCFASTLOCKLOST_Pos)
#define SCIF_ISR_AE_Pos             31           /**< \brief (SCIF_ISR) Access Error */
#define SCIF_ISR_AE                 (0x1u << SCIF_ISR_AE_Pos)
#define SCIF_ISR_MASK               0x800060FFu  /**< \brief (SCIF_ISR) MASK Register */

/* -------- SCIF_ICR : (SCIF Offset: 0x010) ( /W 32) Interrupt Clear Register -------- */
#define SCIF_ICR_OFFSET             0x010        /**< \brief (SCIF_ICR offset) Interrupt Clear Register */
#define SCIF_ICR_RESETVALUE         0x00000000   /**< \brief (SCIF_ICR reset_value) Interrupt Clear Register */

#define SCIF_ICR_OSC0RDY_Pos        0            /**< \brief (SCIF_ICR) OSC0 Ready */
#define SCIF_ICR_OSC0RDY            (0x1u << SCIF_ICR_OSC0RDY_Pos)
#define SCIF_ICR_DFLL0LOCKC_Pos     1            /**< \brief (SCIF_ICR) DFLL0 Lock Coarse */
#define SCIF_ICR_DFLL0LOCKC         (0x1u << SCIF_ICR_DFLL0LOCKC_Pos)
#define SCIF_ICR_DFLL0LOCKF_Pos     2            /**< \brief (SCIF_ICR) DFLL0 Lock Fine */
#define SCIF_ICR_DFLL0LOCKF         (0x1u << SCIF_ICR_DFLL0LOCKF_Pos)
#define SCIF_ICR_DFLL0RDY_Pos       3            /**< \brief (SCIF_ICR) DFLL0 Ready */
#define SCIF_ICR_DFLL0RDY           (0x1u << SCIF_ICR_DFLL0RDY_Pos)
#define SCIF_ICR_DFLL0RCS_Pos       4            /**< \brief (SCIF_ICR) DFLL0 Reference Clock Stopped */
#define SCIF_ICR_DFLL0RCS           (0x1u << SCIF_ICR_DFLL0RCS_Pos)
#define SCIF_ICR_DFLL0OOB_Pos       5            /**< \brief (SCIF_ICR) DFLL0 Out Of Bounds */
#define SCIF_ICR_DFLL0OOB           (0x1u << SCIF_ICR_DFLL0OOB_Pos)
#define SCIF_ICR_PLL0LOCK_Pos       6            /**< \brief (SCIF_ICR) PLL0 Lock */
#define SCIF_ICR_PLL0LOCK           (0x1u << SCIF_ICR_PLL0LOCK_Pos)
#define SCIF_ICR_PLL0LOCKLOST_Pos   7            /**< \brief (SCIF_ICR) PLL0 Lock Lost */
#define SCIF_ICR_PLL0LOCKLOST       (0x1u << SCIF_ICR_PLL0LOCKLOST_Pos)
#define SCIF_ICR_RCFASTLOCK_Pos     13           /**< \brief (SCIF_ICR) RCFAST Lock */
#define SCIF_ICR_RCFASTLOCK         (0x1u << SCIF_ICR_RCFASTLOCK_Pos)
#define SCIF_ICR_RCFASTLOCKLOST_Pos 14           /**< \brief (SCIF_ICR) RCFAST Lock Lost */
#define SCIF_ICR_RCFASTLOCKLOST     (0x1u << SCIF_ICR_RCFASTLOCKLOST_Pos)
#define SCIF_ICR_AE_Pos             31           /**< \brief (SCIF_ICR) Access Error */
#define SCIF_ICR_AE                 (0x1u << SCIF_ICR_AE_Pos)
#define SCIF_ICR_MASK               0x800060FFu  /**< \brief (SCIF_ICR) MASK Register */

/* -------- SCIF_PCLKSR : (SCIF Offset: 0x014) (R/  32) Power and Clocks Status Register -------- */
#define SCIF_PCLKSR_OFFSET          0x014        /**< \brief (SCIF_PCLKSR offset) Power and Clocks Status Register */
#define SCIF_PCLKSR_RESETVALUE      0x00000000   /**< \brief (SCIF_PCLKSR reset_value) Power and Clocks Status Register */

#define SCIF_PCLKSR_OSC0RDY_Pos     0            /**< \brief (SCIF_PCLKSR) OSC0 Ready */
#define SCIF_PCLKSR_OSC0RDY         (0x1u << SCIF_PCLKSR_OSC0RDY_Pos)
#define SCIF_PCLKSR_DFLL0LOCKC_Pos  1            /**< \brief (SCIF_PCLKSR) DFLL0 Locked on Coarse Value */
#define SCIF_PCLKSR_DFLL0LOCKC      (0x1u << SCIF_PCLKSR_DFLL0LOCKC_Pos)
#define SCIF_PCLKSR_DFLL0LOCKF_Pos  2            /**< \brief (SCIF_PCLKSR) DFLL0 Locked on Fine Value */
#define SCIF_PCLKSR_DFLL0LOCKF      (0x1u << SCIF_PCLKSR_DFLL0LOCKF_Pos)
#define SCIF_PCLKSR_DFLL0RDY_Pos    3            /**< \brief (SCIF_PCLKSR) DFLL0 Synchronization Ready */
#define SCIF_PCLKSR_DFLL0RDY        (0x1u << SCIF_PCLKSR_DFLL0RDY_Pos)
#define SCIF_PCLKSR_DFLL0RCS_Pos    4            /**< \brief (SCIF_PCLKSR) DFLL0 Reference Clock Stopped */
#define SCIF_PCLKSR_DFLL0RCS        (0x1u << SCIF_PCLKSR_DFLL0RCS_Pos)
#define SCIF_PCLKSR_DFLL0OOB_Pos    5            /**< \brief (SCIF_PCLKSR) DFLL0 Track Out Of Bounds */
#define SCIF_PCLKSR_DFLL0OOB        (0x1u << SCIF_PCLKSR_DFLL0OOB_Pos)
#define SCIF_PCLKSR_PLL0LOCK_Pos    6            /**< \brief (SCIF_PCLKSR) PLL0 Locked on Accurate value */
#define SCIF_PCLKSR_PLL0LOCK        (0x1u << SCIF_PCLKSR_PLL0LOCK_Pos)
#define SCIF_PCLKSR_PLL0LOCKLOST_Pos 7            /**< \brief (SCIF_PCLKSR) PLL0 lock lost value */
#define SCIF_PCLKSR_PLL0LOCKLOST    (0x1u << SCIF_PCLKSR_PLL0LOCKLOST_Pos)
#define SCIF_PCLKSR_RCFASTLOCK_Pos  13           /**< \brief (SCIF_PCLKSR) RCFAST Locked on Accurate value */
#define SCIF_PCLKSR_RCFASTLOCK      (0x1u << SCIF_PCLKSR_RCFASTLOCK_Pos)
#define SCIF_PCLKSR_RCFASTLOCKLOST_Pos 14           /**< \brief (SCIF_PCLKSR) RCFAST lock lost value */
#define SCIF_PCLKSR_RCFASTLOCKLOST  (0x1u << SCIF_PCLKSR_RCFASTLOCKLOST_Pos)
#define SCIF_PCLKSR_MASK            0x000060FFu  /**< \brief (SCIF_PCLKSR) MASK Register */

/* -------- SCIF_UNLOCK : (SCIF Offset: 0x018) ( /W 32) Unlock Register -------- */
#define SCIF_UNLOCK_OFFSET          0x018        /**< \brief (SCIF_UNLOCK offset) Unlock Register */
#define SCIF_UNLOCK_RESETVALUE      0x00000000   /**< \brief (SCIF_UNLOCK reset_value) Unlock Register */

#define SCIF_UNLOCK_ADDR_Pos        0            /**< \brief (SCIF_UNLOCK) Unlock Address */
#define SCIF_UNLOCK_ADDR_Msk        (0x3FFu << SCIF_UNLOCK_ADDR_Pos)
#define SCIF_UNLOCK_ADDR(value)     ((SCIF_UNLOCK_ADDR_Msk & ((value) << SCIF_UNLOCK_ADDR_Pos)))
#define SCIF_UNLOCK_KEY_Pos         24           /**< \brief (SCIF_UNLOCK) Unlock Key */
#define SCIF_UNLOCK_KEY_Msk         (0xFFu << SCIF_UNLOCK_KEY_Pos)
#define SCIF_UNLOCK_KEY(value)      ((SCIF_UNLOCK_KEY_Msk & ((value) << SCIF_UNLOCK_KEY_Pos)))
#define SCIF_UNLOCK_MASK            0xFF0003FFu  /**< \brief (SCIF_UNLOCK) MASK Register */

/* -------- SCIF_CSCR : (SCIF Offset: 0x01C) (R/W 32) Chip Specific Configuration Register -------- */
#define SCIF_CSCR_OFFSET            0x01C        /**< \brief (SCIF_CSCR offset) Chip Specific Configuration Register */
#define SCIF_CSCR_RESETVALUE        0x00000000   /**< \brief (SCIF_CSCR reset_value) Chip Specific Configuration Register */
#define SCIF_CSCR_MASK              0xFFFFFFFFu  /**< \brief (SCIF_CSCR) MASK Register */

/* -------- SCIF_OSCCTRL0 : (SCIF Offset: 0x020) (R/W 32) Oscillator Control Register -------- */
#define SCIF_OSCCTRL0_OFFSET        0x020        /**< \brief (SCIF_OSCCTRL0 offset) Oscillator Control Register */
#define SCIF_OSCCTRL0_RESETVALUE    0x00000000   /**< \brief (SCIF_OSCCTRL0 reset_value) Oscillator Control Register */

#define SCIF_OSCCTRL0_MODE_Pos      0            /**< \brief (SCIF_OSCCTRL0) Oscillator Mode */
#define SCIF_OSCCTRL0_MODE          (0x1u << SCIF_OSCCTRL0_MODE_Pos)
#define SCIF_OSCCTRL0_GAIN_Pos      1            /**< \brief (SCIF_OSCCTRL0) Gain */
#define SCIF_OSCCTRL0_GAIN_Msk      (0x3u << SCIF_OSCCTRL0_GAIN_Pos)
#define SCIF_OSCCTRL0_GAIN(value)   ((SCIF_OSCCTRL0_GAIN_Msk & ((value) << SCIF_OSCCTRL0_GAIN_Pos)))
#define SCIF_OSCCTRL0_AGC_Pos       3            /**< \brief (SCIF_OSCCTRL0) Automatic Gain Control */
#define SCIF_OSCCTRL0_AGC           (0x1u << SCIF_OSCCTRL0_AGC_Pos)
#define SCIF_OSCCTRL0_STARTUP_Pos   8            /**< \brief (SCIF_OSCCTRL0) Oscillator Start-up Time */
#define SCIF_OSCCTRL0_STARTUP_Msk   (0xFu << SCIF_OSCCTRL0_STARTUP_Pos)
#define SCIF_OSCCTRL0_STARTUP(value) ((SCIF_OSCCTRL0_STARTUP_Msk & ((value) << SCIF_OSCCTRL0_STARTUP_Pos)))
#define SCIF_OSCCTRL0_OSCEN_Pos     16           /**< \brief (SCIF_OSCCTRL0) Oscillator Enable */
#define SCIF_OSCCTRL0_OSCEN         (0x1u << SCIF_OSCCTRL0_OSCEN_Pos)
#define SCIF_OSCCTRL0_MASK          0x00010F0Fu  /**< \brief (SCIF_OSCCTRL0) MASK Register */

/* -------- SCIF_PLL : (SCIF Offset: 0x024) (R/W 32) pll PLL0 Control Register -------- */
#define SCIF_PLL_OFFSET             0x024        /**< \brief (SCIF_PLL offset) PLL0 Control Register */
#define SCIF_PLL_RESETVALUE         0x00000000   /**< \brief (SCIF_PLL reset_value) PLL0 Control Register */

#define SCIF_PLL_PLLEN_Pos          0            /**< \brief (SCIF_PLL) PLL Enable */
#define SCIF_PLL_PLLEN              (0x1u << SCIF_PLL_PLLEN_Pos)
#define SCIF_PLL_PLLOSC_Pos         1            /**< \brief (SCIF_PLL) PLL Oscillator Select */
#define SCIF_PLL_PLLOSC_Msk         (0x3u << SCIF_PLL_PLLOSC_Pos)
#define SCIF_PLL_PLLOSC(value)      ((SCIF_PLL_PLLOSC_Msk & ((value) << SCIF_PLL_PLLOSC_Pos)))
#define SCIF_PLL_PLLOPT_Pos         3            /**< \brief (SCIF_PLL) PLL Option */
#define SCIF_PLL_PLLOPT_Msk         (0x7u << SCIF_PLL_PLLOPT_Pos)
#define SCIF_PLL_PLLOPT(value)      ((SCIF_PLL_PLLOPT_Msk & ((value) << SCIF_PLL_PLLOPT_Pos)))
#define SCIF_PLL_PLLDIV_Pos         8            /**< \brief (SCIF_PLL) PLL Division Factor */
#define SCIF_PLL_PLLDIV_Msk         (0xFu << SCIF_PLL_PLLDIV_Pos)
#define SCIF_PLL_PLLDIV(value)      ((SCIF_PLL_PLLDIV_Msk & ((value) << SCIF_PLL_PLLDIV_Pos)))
#define SCIF_PLL_PLLMUL_Pos         16           /**< \brief (SCIF_PLL) PLL Multiply Factor */
#define SCIF_PLL_PLLMUL_Msk         (0xFu << SCIF_PLL_PLLMUL_Pos)
#define SCIF_PLL_PLLMUL(value)      ((SCIF_PLL_PLLMUL_Msk & ((value) << SCIF_PLL_PLLMUL_Pos)))
#define SCIF_PLL_PLLCOUNT_Pos       24           /**< \brief (SCIF_PLL) PLL Count */
#define SCIF_PLL_PLLCOUNT_Msk       (0x3Fu << SCIF_PLL_PLLCOUNT_Pos)
#define SCIF_PLL_PLLCOUNT(value)    ((SCIF_PLL_PLLCOUNT_Msk & ((value) << SCIF_PLL_PLLCOUNT_Pos)))
#define SCIF_PLL_MASK               0x3F0F0F3Fu  /**< \brief (SCIF_PLL) MASK Register */

/* -------- SCIF_DFLL0CONF : (SCIF Offset: 0x028) (R/W 32) DFLL0 Config Register -------- */
#define SCIF_DFLL0CONF_OFFSET       0x028        /**< \brief (SCIF_DFLL0CONF offset) DFLL0 Config Register */
#define SCIF_DFLL0CONF_RESETVALUE   0x00000000   /**< \brief (SCIF_DFLL0CONF reset_value) DFLL0 Config Register */

#define SCIF_DFLL0CONF_EN_Pos       0            /**< \brief (SCIF_DFLL0CONF) Enable */
#define SCIF_DFLL0CONF_EN           (0x1u << SCIF_DFLL0CONF_EN_Pos)
#define SCIF_DFLL0CONF_MODE_Pos     1            /**< \brief (SCIF_DFLL0CONF) Mode Selection */
#define SCIF_DFLL0CONF_MODE         (0x1u << SCIF_DFLL0CONF_MODE_Pos)
#define SCIF_DFLL0CONF_STABLE_Pos   2            /**< \brief (SCIF_DFLL0CONF) Stable DFLL Frequency */
#define SCIF_DFLL0CONF_STABLE       (0x1u << SCIF_DFLL0CONF_STABLE_Pos)
#define SCIF_DFLL0CONF_LLAW_Pos     3            /**< \brief (SCIF_DFLL0CONF) Lose Lock After Wake */
#define SCIF_DFLL0CONF_LLAW         (0x1u << SCIF_DFLL0CONF_LLAW_Pos)
#define SCIF_DFLL0CONF_CCDIS_Pos    5            /**< \brief (SCIF_DFLL0CONF) Chill Cycle Disable */
#define SCIF_DFLL0CONF_CCDIS        (0x1u << SCIF_DFLL0CONF_CCDIS_Pos)
#define SCIF_DFLL0CONF_QLDIS_Pos    6            /**< \brief (SCIF_DFLL0CONF) Quick Lock Disable */
#define SCIF_DFLL0CONF_QLDIS        (0x1u << SCIF_DFLL0CONF_QLDIS_Pos)
#define SCIF_DFLL0CONF_RANGE_Pos    16           /**< \brief (SCIF_DFLL0CONF) Range Value */
#define SCIF_DFLL0CONF_RANGE_Msk    (0x3u << SCIF_DFLL0CONF_RANGE_Pos)
#define SCIF_DFLL0CONF_RANGE(value) ((SCIF_DFLL0CONF_RANGE_Msk & ((value) << SCIF_DFLL0CONF_RANGE_Pos)))
#define SCIF_DFLL0CONF_FCD_Pos      23           /**< \brief (SCIF_DFLL0CONF) Fuse Calibration Done */
#define SCIF_DFLL0CONF_FCD          (0x1u << SCIF_DFLL0CONF_FCD_Pos)
#define SCIF_DFLL0CONF_CALIB_Pos    24           /**< \brief (SCIF_DFLL0CONF) Calibration Value */
#define SCIF_DFLL0CONF_CALIB_Msk    (0xFu << SCIF_DFLL0CONF_CALIB_Pos)
#define SCIF_DFLL0CONF_CALIB(value) ((SCIF_DFLL0CONF_CALIB_Msk & ((value) << SCIF_DFLL0CONF_CALIB_Pos)))
#define SCIF_DFLL0CONF_MASK         0x0F83006Fu  /**< \brief (SCIF_DFLL0CONF) MASK Register */

/* -------- SCIF_DFLL0VAL : (SCIF Offset: 0x02C) (R/W 32) DFLL Value Register -------- */
#define SCIF_DFLL0VAL_OFFSET        0x02C        /**< \brief (SCIF_DFLL0VAL offset) DFLL Value Register */
#define SCIF_DFLL0VAL_RESETVALUE    0x00000000   /**< \brief (SCIF_DFLL0VAL reset_value) DFLL Value Register */

#define SCIF_DFLL0VAL_FINE_Pos      0            /**< \brief (SCIF_DFLL0VAL) Fine Value */
#define SCIF_DFLL0VAL_FINE_Msk      (0xFFu << SCIF_DFLL0VAL_FINE_Pos)
#define SCIF_DFLL0VAL_FINE(value)   ((SCIF_DFLL0VAL_FINE_Msk & ((value) << SCIF_DFLL0VAL_FINE_Pos)))
#define SCIF_DFLL0VAL_COARSE_Pos    16           /**< \brief (SCIF_DFLL0VAL) Coarse Value */
#define SCIF_DFLL0VAL_COARSE_Msk    (0x1Fu << SCIF_DFLL0VAL_COARSE_Pos)
#define SCIF_DFLL0VAL_COARSE(value) ((SCIF_DFLL0VAL_COARSE_Msk & ((value) << SCIF_DFLL0VAL_COARSE_Pos)))
#define SCIF_DFLL0VAL_MASK          0x001F00FFu  /**< \brief (SCIF_DFLL0VAL) MASK Register */

/* -------- SCIF_DFLL0MUL : (SCIF Offset: 0x030) (R/W 32) DFLL0 Multiplier Register -------- */
#define SCIF_DFLL0MUL_OFFSET        0x030        /**< \brief (SCIF_DFLL0MUL offset) DFLL0 Multiplier Register */
#define SCIF_DFLL0MUL_RESETVALUE    0x00000000   /**< \brief (SCIF_DFLL0MUL reset_value) DFLL0 Multiplier Register */

#define SCIF_DFLL0MUL_MUL_Pos       0            /**< \brief (SCIF_DFLL0MUL) DFLL Multiply Factor */
#define SCIF_DFLL0MUL_MUL_Msk       (0xFFFFu << SCIF_DFLL0MUL_MUL_Pos)
#define SCIF_DFLL0MUL_MUL(value)    ((SCIF_DFLL0MUL_MUL_Msk & ((value) << SCIF_DFLL0MUL_MUL_Pos)))
#define SCIF_DFLL0MUL_MASK          0x0000FFFFu  /**< \brief (SCIF_DFLL0MUL) MASK Register */

/* -------- SCIF_DFLL0STEP : (SCIF Offset: 0x034) (R/W 32) DFLL0 Step Register -------- */
#define SCIF_DFLL0STEP_OFFSET       0x034        /**< \brief (SCIF_DFLL0STEP offset) DFLL0 Step Register */
#define SCIF_DFLL0STEP_RESETVALUE   0x00000000   /**< \brief (SCIF_DFLL0STEP reset_value) DFLL0 Step Register */

#define SCIF_DFLL0STEP_FSTEP_Pos    0            /**< \brief (SCIF_DFLL0STEP) Fine Maximum Step */
#define SCIF_DFLL0STEP_FSTEP_Msk    (0xFFu << SCIF_DFLL0STEP_FSTEP_Pos)
#define SCIF_DFLL0STEP_FSTEP(value) ((SCIF_DFLL0STEP_FSTEP_Msk & ((value) << SCIF_DFLL0STEP_FSTEP_Pos)))
#define SCIF_DFLL0STEP_CSTEP_Pos    16           /**< \brief (SCIF_DFLL0STEP) Coarse Maximum Step */
#define SCIF_DFLL0STEP_CSTEP_Msk    (0x1Fu << SCIF_DFLL0STEP_CSTEP_Pos)
#define SCIF_DFLL0STEP_CSTEP(value) ((SCIF_DFLL0STEP_CSTEP_Msk & ((value) << SCIF_DFLL0STEP_CSTEP_Pos)))
#define SCIF_DFLL0STEP_MASK         0x001F00FFu  /**< \brief (SCIF_DFLL0STEP) MASK Register */

/* -------- SCIF_DFLL0SSG : (SCIF Offset: 0x038) (R/W 32) DFLL0 Spread Spectrum Generator Control Register -------- */
#define SCIF_DFLL0SSG_OFFSET        0x038        /**< \brief (SCIF_DFLL0SSG offset) DFLL0 Spread Spectrum Generator Control Register */
#define SCIF_DFLL0SSG_RESETVALUE    0x00000000   /**< \brief (SCIF_DFLL0SSG reset_value) DFLL0 Spread Spectrum Generator Control Register */

#define SCIF_DFLL0SSG_EN_Pos        0            /**< \brief (SCIF_DFLL0SSG) Enable */
#define SCIF_DFLL0SSG_EN            (0x1u << SCIF_DFLL0SSG_EN_Pos)
#define SCIF_DFLL0SSG_PRBS_Pos      1            /**< \brief (SCIF_DFLL0SSG) Pseudo Random Bit Sequence */
#define SCIF_DFLL0SSG_PRBS          (0x1u << SCIF_DFLL0SSG_PRBS_Pos)
#define SCIF_DFLL0SSG_AMPLITUDE_Pos 8            /**< \brief (SCIF_DFLL0SSG) SSG Amplitude */
#define SCIF_DFLL0SSG_AMPLITUDE_Msk (0x1Fu << SCIF_DFLL0SSG_AMPLITUDE_Pos)
#define SCIF_DFLL0SSG_AMPLITUDE(value) ((SCIF_DFLL0SSG_AMPLITUDE_Msk & ((value) << SCIF_DFLL0SSG_AMPLITUDE_Pos)))
#define SCIF_DFLL0SSG_STEPSIZE_Pos  16           /**< \brief (SCIF_DFLL0SSG) SSG Step Size */
#define SCIF_DFLL0SSG_STEPSIZE_Msk  (0x1Fu << SCIF_DFLL0SSG_STEPSIZE_Pos)
#define SCIF_DFLL0SSG_STEPSIZE(value) ((SCIF_DFLL0SSG_STEPSIZE_Msk & ((value) << SCIF_DFLL0SSG_STEPSIZE_Pos)))
#define SCIF_DFLL0SSG_MASK          0x001F1F03u  /**< \brief (SCIF_DFLL0SSG) MASK Register */

/* -------- SCIF_DFLL0RATIO : (SCIF Offset: 0x03C) (R/  32) DFLL0 Ratio Registe -------- */
#define SCIF_DFLL0RATIO_OFFSET      0x03C        /**< \brief (SCIF_DFLL0RATIO offset) DFLL0 Ratio Registe */
#define SCIF_DFLL0RATIO_RESETVALUE  0x00000000   /**< \brief (SCIF_DFLL0RATIO reset_value) DFLL0 Ratio Registe */

#define SCIF_DFLL0RATIO_RATIODIFF_Pos 0            /**< \brief (SCIF_DFLL0RATIO) Multiplication Ratio Difference */
#define SCIF_DFLL0RATIO_RATIODIFF_Msk (0xFFFFu << SCIF_DFLL0RATIO_RATIODIFF_Pos)
#define SCIF_DFLL0RATIO_RATIODIFF(value) ((SCIF_DFLL0RATIO_RATIODIFF_Msk & ((value) << SCIF_DFLL0RATIO_RATIODIFF_Pos)))
#define SCIF_DFLL0RATIO_MASK        0x0000FFFFu  /**< \brief (SCIF_DFLL0RATIO) MASK Register */

/* -------- SCIF_DFLL0SYNC : (SCIF Offset: 0x040) ( /W 32) DFLL0 Synchronization Register -------- */
#define SCIF_DFLL0SYNC_OFFSET       0x040        /**< \brief (SCIF_DFLL0SYNC offset) DFLL0 Synchronization Register */
#define SCIF_DFLL0SYNC_RESETVALUE   0x00000000   /**< \brief (SCIF_DFLL0SYNC reset_value) DFLL0 Synchronization Register */

#define SCIF_DFLL0SYNC_SYNC_Pos     0            /**< \brief (SCIF_DFLL0SYNC) Synchronization */
#define SCIF_DFLL0SYNC_SYNC         (0x1u << SCIF_DFLL0SYNC_SYNC_Pos)
#define SCIF_DFLL0SYNC_MASK         0x00000001u  /**< \brief (SCIF_DFLL0SYNC) MASK Register */

/* -------- SCIF_RCCR : (SCIF Offset: 0x044) (R/W 32) System RC Oscillator Calibration Register -------- */
#define SCIF_RCCR_OFFSET            0x044        /**< \brief (SCIF_RCCR offset) System RC Oscillator Calibration Register */

#define SCIF_RCCR_CALIB_Pos         0            /**< \brief (SCIF_RCCR) Calibration Value */
#define SCIF_RCCR_CALIB_Msk         (0x3FFu << SCIF_RCCR_CALIB_Pos)
#define SCIF_RCCR_CALIB(value)      ((SCIF_RCCR_CALIB_Msk & ((value) << SCIF_RCCR_CALIB_Pos)))
#define SCIF_RCCR_FCD_Pos           16           /**< \brief (SCIF_RCCR) Flash Calibration Done */
#define SCIF_RCCR_FCD               (0x1u << SCIF_RCCR_FCD_Pos)
#define SCIF_RCCR_MASK              0x000103FFu  /**< \brief (SCIF_RCCR) MASK Register */

/* -------- SCIF_RCFASTCFG : (SCIF Offset: 0x048) (R/W 32) 4/8/12 MHz RC Oscillator Configuration Register -------- */
#define SCIF_RCFASTCFG_OFFSET       0x048        /**< \brief (SCIF_RCFASTCFG offset) 4/8/12 MHz RC Oscillator Configuration Register */
#define SCIF_RCFASTCFG_RESETVALUE   0x00000000   /**< \brief (SCIF_RCFASTCFG reset_value) 4/8/12 MHz RC Oscillator Configuration Register */

#define SCIF_RCFASTCFG_EN_Pos       0            /**< \brief (SCIF_RCFASTCFG) Oscillator Enable */
#define SCIF_RCFASTCFG_EN           (0x1u << SCIF_RCFASTCFG_EN_Pos)
#define SCIF_RCFASTCFG_TUNEEN_Pos   1            /**< \brief (SCIF_RCFASTCFG) Tuner Enable */
#define SCIF_RCFASTCFG_TUNEEN       (0x1u << SCIF_RCFASTCFG_TUNEEN_Pos)
#define SCIF_RCFASTCFG_JITMODE_Pos  2            /**< \brief (SCIF_RCFASTCFG) Jitter Mode */
#define SCIF_RCFASTCFG_JITMODE      (0x1u << SCIF_RCFASTCFG_JITMODE_Pos)
#define SCIF_RCFASTCFG_NBPERIODS_Pos 4            /**< \brief (SCIF_RCFASTCFG) Number of 32kHz Periods */
#define SCIF_RCFASTCFG_NBPERIODS_Msk (0x7u << SCIF_RCFASTCFG_NBPERIODS_Pos)
#define SCIF_RCFASTCFG_NBPERIODS(value) ((SCIF_RCFASTCFG_NBPERIODS_Msk & ((value) << SCIF_RCFASTCFG_NBPERIODS_Pos)))
#define SCIF_RCFASTCFG_FCD_Pos      7            /**< \brief (SCIF_RCFASTCFG) RCFAST Fuse Calibration Done */
#define SCIF_RCFASTCFG_FCD          (0x1u << SCIF_RCFASTCFG_FCD_Pos)
#define SCIF_RCFASTCFG_FRANGE_Pos   8            /**< \brief (SCIF_RCFASTCFG) Frequency Range */
#define SCIF_RCFASTCFG_FRANGE_Msk   (0x3u << SCIF_RCFASTCFG_FRANGE_Pos)
#define SCIF_RCFASTCFG_FRANGE(value) ((SCIF_RCFASTCFG_FRANGE_Msk & ((value) << SCIF_RCFASTCFG_FRANGE_Pos)))
#define SCIF_RCFASTCFG_LOCKMARGIN_Pos 12           /**< \brief (SCIF_RCFASTCFG) Accepted Count Error for Lock */
#define SCIF_RCFASTCFG_LOCKMARGIN_Msk (0xFu << SCIF_RCFASTCFG_LOCKMARGIN_Pos)
#define SCIF_RCFASTCFG_LOCKMARGIN(value) ((SCIF_RCFASTCFG_LOCKMARGIN_Msk & ((value) << SCIF_RCFASTCFG_LOCKMARGIN_Pos)))
#define SCIF_RCFASTCFG_CALIB_Pos    16           /**< \brief (SCIF_RCFASTCFG) Oscillator Calibration Value */
#define SCIF_RCFASTCFG_CALIB_Msk    (0x7Fu << SCIF_RCFASTCFG_CALIB_Pos)
#define SCIF_RCFASTCFG_CALIB(value) ((SCIF_RCFASTCFG_CALIB_Msk & ((value) << SCIF_RCFASTCFG_CALIB_Pos)))
#define SCIF_RCFASTCFG_MASK         0x007FF3F7u  /**< \brief (SCIF_RCFASTCFG) MASK Register */

/* -------- SCIF_RCFASTSR : (SCIF Offset: 0x04C) (R/W 32) 4/8/12 MHz RC Oscillator Status Register -------- */
#define SCIF_RCFASTSR_OFFSET        0x04C        /**< \brief (SCIF_RCFASTSR offset) 4/8/12 MHz RC Oscillator Status Register */
#define SCIF_RCFASTSR_RESETVALUE    0x00000000   /**< \brief (SCIF_RCFASTSR reset_value) 4/8/12 MHz RC Oscillator Status Register */

#define SCIF_RCFASTSR_CURTRIM_Pos   0            /**< \brief (SCIF_RCFASTSR) Current Trim Value */
#define SCIF_RCFASTSR_CURTRIM_Msk   (0x7Fu << SCIF_RCFASTSR_CURTRIM_Pos)
#define SCIF_RCFASTSR_CURTRIM(value) ((SCIF_RCFASTSR_CURTRIM_Msk & ((value) << SCIF_RCFASTSR_CURTRIM_Pos)))
#define SCIF_RCFASTSR_CNTERR_Pos    16           /**< \brief (SCIF_RCFASTSR) Current Count Error */
#define SCIF_RCFASTSR_CNTERR_Msk    (0x1Fu << SCIF_RCFASTSR_CNTERR_Pos)
#define SCIF_RCFASTSR_CNTERR(value) ((SCIF_RCFASTSR_CNTERR_Msk & ((value) << SCIF_RCFASTSR_CNTERR_Pos)))
#define SCIF_RCFASTSR_SIGN_Pos      21           /**< \brief (SCIF_RCFASTSR) Sign of Current Count Error */
#define SCIF_RCFASTSR_SIGN          (0x1u << SCIF_RCFASTSR_SIGN_Pos)
#define SCIF_RCFASTSR_LOCK_Pos      24           /**< \brief (SCIF_RCFASTSR) Lock */
#define SCIF_RCFASTSR_LOCK          (0x1u << SCIF_RCFASTSR_LOCK_Pos)
#define SCIF_RCFASTSR_LOCKLOST_Pos  25           /**< \brief (SCIF_RCFASTSR) Lock Lost */
#define SCIF_RCFASTSR_LOCKLOST      (0x1u << SCIF_RCFASTSR_LOCKLOST_Pos)
#define SCIF_RCFASTSR_UPDATED_Pos   31           /**< \brief (SCIF_RCFASTSR) Current Trim Value Updated */
#define SCIF_RCFASTSR_UPDATED       (0x1u << SCIF_RCFASTSR_UPDATED_Pos)
#define SCIF_RCFASTSR_MASK          0x833F007Fu  /**< \brief (SCIF_RCFASTSR) MASK Register */

/* -------- SCIF_RC80MCR : (SCIF Offset: 0x050) (R/W 32) 80 MHz RC Oscillator Register -------- */
#define SCIF_RC80MCR_OFFSET         0x050        /**< \brief (SCIF_RC80MCR offset) 80 MHz RC Oscillator Register */
#define SCIF_RC80MCR_RESETVALUE     0x00000000   /**< \brief (SCIF_RC80MCR reset_value) 80 MHz RC Oscillator Register */

#define SCIF_RC80MCR_EN_Pos         0            /**< \brief (SCIF_RC80MCR) Enable */
#define SCIF_RC80MCR_EN             (0x1u << SCIF_RC80MCR_EN_Pos)
#define SCIF_RC80MCR_FCD_Pos        7            /**< \brief (SCIF_RC80MCR) Flash Calibration Done */
#define SCIF_RC80MCR_FCD            (0x1u << SCIF_RC80MCR_FCD_Pos)
#define SCIF_RC80MCR_CALIB_Pos      16           /**< \brief (SCIF_RC80MCR) Calibration Value */
#define SCIF_RC80MCR_CALIB_Msk      (0x3u << SCIF_RC80MCR_CALIB_Pos)
#define SCIF_RC80MCR_CALIB(value)   ((SCIF_RC80MCR_CALIB_Msk & ((value) << SCIF_RC80MCR_CALIB_Pos)))
#define SCIF_RC80MCR_MASK           0x00030081u  /**< \brief (SCIF_RC80MCR) MASK Register */

/* -------- SCIF_HRPCR : (SCIF Offset: 0x064) (R/W 32) High Resolution Prescaler Control Register -------- */
#define SCIF_HRPCR_OFFSET           0x064        /**< \brief (SCIF_HRPCR offset) High Resolution Prescaler Control Register */

#define SCIF_HRPCR_HRPEN_Pos        0            /**< \brief (SCIF_HRPCR) High Resolution Prescaler Enable */
#define SCIF_HRPCR_HRPEN            (0x1u << SCIF_HRPCR_HRPEN_Pos)
#define SCIF_HRPCR_CKSEL_Pos        1            /**< \brief (SCIF_HRPCR) Clock Input Selection */
#define SCIF_HRPCR_CKSEL_Msk        (0x7u << SCIF_HRPCR_CKSEL_Pos)
#define SCIF_HRPCR_CKSEL(value)     ((SCIF_HRPCR_CKSEL_Msk & ((value) << SCIF_HRPCR_CKSEL_Pos)))
#define SCIF_HRPCR_HRCOUNT_Pos      8            /**< \brief (SCIF_HRPCR) High Resolution Counter */
#define SCIF_HRPCR_HRCOUNT_Msk      (0xFFFFFFu << SCIF_HRPCR_HRCOUNT_Pos)
#define SCIF_HRPCR_HRCOUNT(value)   ((SCIF_HRPCR_HRCOUNT_Msk & ((value) << SCIF_HRPCR_HRCOUNT_Pos)))
#define SCIF_HRPCR_MASK             0xFFFFFF0Fu  /**< \brief (SCIF_HRPCR) MASK Register */

/* -------- SCIF_FPCR : (SCIF Offset: 0x068) (R/W 32) Fractional Prescaler Control Register -------- */
#define SCIF_FPCR_OFFSET            0x068        /**< \brief (SCIF_FPCR offset) Fractional Prescaler Control Register */

#define SCIF_FPCR_FPEN_Pos          0            /**< \brief (SCIF_FPCR) High Resolution Prescaler Enable */
#define SCIF_FPCR_FPEN              (0x1u << SCIF_FPCR_FPEN_Pos)
#define SCIF_FPCR_CKSEL_Pos         1            /**< \brief (SCIF_FPCR) Clock Input Selection */
#define SCIF_FPCR_CKSEL_Msk         (0x7u << SCIF_FPCR_CKSEL_Pos)
#define SCIF_FPCR_CKSEL(value)      ((SCIF_FPCR_CKSEL_Msk & ((value) << SCIF_FPCR_CKSEL_Pos)))
#define SCIF_FPCR_MASK              0x0000000Fu  /**< \brief (SCIF_FPCR) MASK Register */

/* -------- SCIF_FPMUL : (SCIF Offset: 0x06C) (R/W 32) Fractional Prescaler Multiplier Register -------- */
#define SCIF_FPMUL_OFFSET           0x06C        /**< \brief (SCIF_FPMUL offset) Fractional Prescaler Multiplier Register */

#define SCIF_FPMUL_FPMUL_Pos        0            /**< \brief (SCIF_FPMUL) Fractional Prescaler Multiplication Factor */
#define SCIF_FPMUL_FPMUL_Msk        (0xFFFFu << SCIF_FPMUL_FPMUL_Pos)
#define SCIF_FPMUL_FPMUL(value)     ((SCIF_FPMUL_FPMUL_Msk & ((value) << SCIF_FPMUL_FPMUL_Pos)))
#define SCIF_FPMUL_MASK             0x0000FFFFu  /**< \brief (SCIF_FPMUL) MASK Register */

/* -------- SCIF_FPDIV : (SCIF Offset: 0x070) (R/W 32) Fractional Prescaler DIVIDER Register -------- */
#define SCIF_FPDIV_OFFSET           0x070        /**< \brief (SCIF_FPDIV offset) Fractional Prescaler DIVIDER Register */

#define SCIF_FPDIV_FPDIV_Pos        0            /**< \brief (SCIF_FPDIV) Fractional Prescaler Division Factor */
#define SCIF_FPDIV_FPDIV_Msk        (0xFFFFu << SCIF_FPDIV_FPDIV_Pos)
#define SCIF_FPDIV_FPDIV(value)     ((SCIF_FPDIV_FPDIV_Msk & ((value) << SCIF_FPDIV_FPDIV_Pos)))
#define SCIF_FPDIV_MASK             0x0000FFFFu  /**< \brief (SCIF_FPDIV) MASK Register */

/* -------- SCIF_GCCTRL : (SCIF Offset: 0x074) (R/W 32) gcctrl Generic Clock Control -------- */
#define SCIF_GCCTRL_OFFSET          0x074        /**< \brief (SCIF_GCCTRL offset) Generic Clock Control */
#define SCIF_GCCTRL_RESETVALUE      0x00000000   /**< \brief (SCIF_GCCTRL reset_value) Generic Clock Control */

#define SCIF_GCCTRL_CEN_Pos         0            /**< \brief (SCIF_GCCTRL) Clock Enable */
#define SCIF_GCCTRL_CEN             (0x1u << SCIF_GCCTRL_CEN_Pos)
#define SCIF_GCCTRL_DIVEN_Pos       1            /**< \brief (SCIF_GCCTRL) Divide Enable */
#define SCIF_GCCTRL_DIVEN           (0x1u << SCIF_GCCTRL_DIVEN_Pos)
#define SCIF_GCCTRL_OSCSEL_Pos      8            /**< \brief (SCIF_GCCTRL) Clock Select */
#define SCIF_GCCTRL_OSCSEL_Msk      (0x1Fu << SCIF_GCCTRL_OSCSEL_Pos)
#define SCIF_GCCTRL_OSCSEL(value)   ((SCIF_GCCTRL_OSCSEL_Msk & ((value) << SCIF_GCCTRL_OSCSEL_Pos)))
#define SCIF_GCCTRL_DIV_Pos         16           /**< \brief (SCIF_GCCTRL) Division Factor */
#define SCIF_GCCTRL_DIV_Msk         (0xFFFFu << SCIF_GCCTRL_DIV_Pos)
#define SCIF_GCCTRL_DIV(value)      ((SCIF_GCCTRL_DIV_Msk & ((value) << SCIF_GCCTRL_DIV_Pos)))
#define SCIF_GCCTRL_MASK            0xFFFF1F03u  /**< \brief (SCIF_GCCTRL) MASK Register */

/* -------- SCIF_RCFASTVERSION : (SCIF Offset: 0x3D8) (R/  32) 4/8/12 MHz RC Oscillator Version Register -------- */
#define SCIF_RCFASTVERSION_OFFSET   0x3D8        /**< \brief (SCIF_RCFASTVERSION offset) 4/8/12 MHz RC Oscillator Version Register */

#define SCIF_RCFASTVERSION_VERSION_Pos 0            /**< \brief (SCIF_RCFASTVERSION) Version number */
#define SCIF_RCFASTVERSION_VERSION_Msk (0xFFFu << SCIF_RCFASTVERSION_VERSION_Pos)
#define SCIF_RCFASTVERSION_VERSION(value) ((SCIF_RCFASTVERSION_VERSION_Msk & ((value) << SCIF_RCFASTVERSION_VERSION_Pos)))
#define SCIF_RCFASTVERSION_VARIANT_Pos 16           /**< \brief (SCIF_RCFASTVERSION) Variant number */
#define SCIF_RCFASTVERSION_VARIANT_Msk (0xFu << SCIF_RCFASTVERSION_VARIANT_Pos)
#define SCIF_RCFASTVERSION_VARIANT(value) ((SCIF_RCFASTVERSION_VARIANT_Msk & ((value) << SCIF_RCFASTVERSION_VARIANT_Pos)))
#define SCIF_RCFASTVERSION_MASK     0x000F0FFFu  /**< \brief (SCIF_RCFASTVERSION) MASK Register */

/* -------- SCIF_GCLKPRESCVERSION : (SCIF Offset: 0x3DC) (R/  32) Generic Clock Prescaler Version Register -------- */
#define SCIF_GCLKPRESCVERSION_OFFSET 0x3DC        /**< \brief (SCIF_GCLKPRESCVERSION offset) Generic Clock Prescaler Version Register */

#define SCIF_GCLKPRESCVERSION_VERSION_Pos 0            /**< \brief (SCIF_GCLKPRESCVERSION) Version number */
#define SCIF_GCLKPRESCVERSION_VERSION_Msk (0xFFFu << SCIF_GCLKPRESCVERSION_VERSION_Pos)
#define SCIF_GCLKPRESCVERSION_VERSION(value) ((SCIF_GCLKPRESCVERSION_VERSION_Msk & ((value) << SCIF_GCLKPRESCVERSION_VERSION_Pos)))
#define SCIF_GCLKPRESCVERSION_VARIANT_Pos 16           /**< \brief (SCIF_GCLKPRESCVERSION) Variant number */
#define SCIF_GCLKPRESCVERSION_VARIANT_Msk (0xFu << SCIF_GCLKPRESCVERSION_VARIANT_Pos)
#define SCIF_GCLKPRESCVERSION_VARIANT(value) ((SCIF_GCLKPRESCVERSION_VARIANT_Msk & ((value) << SCIF_GCLKPRESCVERSION_VARIANT_Pos)))
#define SCIF_GCLKPRESCVERSION_MASK  0x000F0FFFu  /**< \brief (SCIF_GCLKPRESCVERSION) MASK Register */

/* -------- SCIF_PLLIFAVERSION : (SCIF Offset: 0x3E0) (R/  32) PLL Version Register -------- */
#define SCIF_PLLIFAVERSION_OFFSET   0x3E0        /**< \brief (SCIF_PLLIFAVERSION offset) PLL Version Register */

#define SCIF_PLLIFAVERSION_VERSION_Pos 0            /**< \brief (SCIF_PLLIFAVERSION) Version number */
#define SCIF_PLLIFAVERSION_VERSION_Msk (0xFFFu << SCIF_PLLIFAVERSION_VERSION_Pos)
#define SCIF_PLLIFAVERSION_VERSION(value) ((SCIF_PLLIFAVERSION_VERSION_Msk & ((value) << SCIF_PLLIFAVERSION_VERSION_Pos)))
#define SCIF_PLLIFAVERSION_VARIANT_Pos 16           /**< \brief (SCIF_PLLIFAVERSION) Variant nubmer */
#define SCIF_PLLIFAVERSION_VARIANT_Msk (0xFu << SCIF_PLLIFAVERSION_VARIANT_Pos)
#define SCIF_PLLIFAVERSION_VARIANT(value) ((SCIF_PLLIFAVERSION_VARIANT_Msk & ((value) << SCIF_PLLIFAVERSION_VARIANT_Pos)))
#define SCIF_PLLIFAVERSION_MASK     0x000F0FFFu  /**< \brief (SCIF_PLLIFAVERSION) MASK Register */

/* -------- SCIF_OSCIFAVERSION : (SCIF Offset: 0x3E4) (R/  32) Oscillator 0 Version Register -------- */
#define SCIF_OSCIFAVERSION_OFFSET   0x3E4        /**< \brief (SCIF_OSCIFAVERSION offset) Oscillator 0 Version Register */

#define SCIF_OSCIFAVERSION_VERSION_Pos 0            /**< \brief (SCIF_OSCIFAVERSION) Version number */
#define SCIF_OSCIFAVERSION_VERSION_Msk (0xFFFu << SCIF_OSCIFAVERSION_VERSION_Pos)
#define SCIF_OSCIFAVERSION_VERSION(value) ((SCIF_OSCIFAVERSION_VERSION_Msk & ((value) << SCIF_OSCIFAVERSION_VERSION_Pos)))
#define SCIF_OSCIFAVERSION_VARIANT_Pos 16           /**< \brief (SCIF_OSCIFAVERSION) Variant nubmer */
#define SCIF_OSCIFAVERSION_VARIANT_Msk (0xFu << SCIF_OSCIFAVERSION_VARIANT_Pos)
#define SCIF_OSCIFAVERSION_VARIANT(value) ((SCIF_OSCIFAVERSION_VARIANT_Msk & ((value) << SCIF_OSCIFAVERSION_VARIANT_Pos)))
#define SCIF_OSCIFAVERSION_MASK     0x000F0FFFu  /**< \brief (SCIF_OSCIFAVERSION) MASK Register */

/* -------- SCIF_DFLLIFBVERSION : (SCIF Offset: 0x3E8) (R/  32) DFLL Version Register -------- */
#define SCIF_DFLLIFBVERSION_OFFSET  0x3E8        /**< \brief (SCIF_DFLLIFBVERSION offset) DFLL Version Register */

#define SCIF_DFLLIFBVERSION_VERSION_Pos 0            /**< \brief (SCIF_DFLLIFBVERSION) Version number */
#define SCIF_DFLLIFBVERSION_VERSION_Msk (0xFFFu << SCIF_DFLLIFBVERSION_VERSION_Pos)
#define SCIF_DFLLIFBVERSION_VERSION(value) ((SCIF_DFLLIFBVERSION_VERSION_Msk & ((value) << SCIF_DFLLIFBVERSION_VERSION_Pos)))
#define SCIF_DFLLIFBVERSION_VARIANT_Pos 16           /**< \brief (SCIF_DFLLIFBVERSION) Variant number */
#define SCIF_DFLLIFBVERSION_VARIANT_Msk (0xFu << SCIF_DFLLIFBVERSION_VARIANT_Pos)
#define SCIF_DFLLIFBVERSION_VARIANT(value) ((SCIF_DFLLIFBVERSION_VARIANT_Msk & ((value) << SCIF_DFLLIFBVERSION_VARIANT_Pos)))
#define SCIF_DFLLIFBVERSION_MASK    0x000F0FFFu  /**< \brief (SCIF_DFLLIFBVERSION) MASK Register */

/* -------- SCIF_RCOSCIFAVERSION : (SCIF Offset: 0x3EC) (R/  32) System RC Oscillator Version Register -------- */
#define SCIF_RCOSCIFAVERSION_OFFSET 0x3EC        /**< \brief (SCIF_RCOSCIFAVERSION offset) System RC Oscillator Version Register */

#define SCIF_RCOSCIFAVERSION_VERSION_Pos 0            /**< \brief (SCIF_RCOSCIFAVERSION) Version number */
#define SCIF_RCOSCIFAVERSION_VERSION_Msk (0xFFFu << SCIF_RCOSCIFAVERSION_VERSION_Pos)
#define SCIF_RCOSCIFAVERSION_VERSION(value) ((SCIF_RCOSCIFAVERSION_VERSION_Msk & ((value) << SCIF_RCOSCIFAVERSION_VERSION_Pos)))
#define SCIF_RCOSCIFAVERSION_VARIANT_Pos 16           /**< \brief (SCIF_RCOSCIFAVERSION) Variant number */
#define SCIF_RCOSCIFAVERSION_VARIANT_Msk (0xFu << SCIF_RCOSCIFAVERSION_VARIANT_Pos)
#define SCIF_RCOSCIFAVERSION_VARIANT(value) ((SCIF_RCOSCIFAVERSION_VARIANT_Msk & ((value) << SCIF_RCOSCIFAVERSION_VARIANT_Pos)))
#define SCIF_RCOSCIFAVERSION_MASK   0x000F0FFFu  /**< \brief (SCIF_RCOSCIFAVERSION) MASK Register */

/* -------- SCIF_FLOVERSION : (SCIF Offset: 0x3F0) (R/  32) Frequency Locked Oscillator Version Register -------- */
#define SCIF_FLOVERSION_OFFSET      0x3F0        /**< \brief (SCIF_FLOVERSION offset) Frequency Locked Oscillator Version Register */

#define SCIF_FLOVERSION_VERSION_Pos 0            /**< \brief (SCIF_FLOVERSION) Version number */
#define SCIF_FLOVERSION_VERSION_Msk (0xFFFu << SCIF_FLOVERSION_VERSION_Pos)
#define SCIF_FLOVERSION_VERSION(value) ((SCIF_FLOVERSION_VERSION_Msk & ((value) << SCIF_FLOVERSION_VERSION_Pos)))
#define SCIF_FLOVERSION_VARIANT_Pos 16           /**< \brief (SCIF_FLOVERSION) Variant number */
#define SCIF_FLOVERSION_VARIANT_Msk (0xFu << SCIF_FLOVERSION_VARIANT_Pos)
#define SCIF_FLOVERSION_VARIANT(value) ((SCIF_FLOVERSION_VARIANT_Msk & ((value) << SCIF_FLOVERSION_VARIANT_Pos)))
#define SCIF_FLOVERSION_MASK        0x000F0FFFu  /**< \brief (SCIF_FLOVERSION) MASK Register */

/* -------- SCIF_RC80MVERSION : (SCIF Offset: 0x3F4) (R/  32) 80MHz RC Oscillator Version Register -------- */
#define SCIF_RC80MVERSION_OFFSET    0x3F4        /**< \brief (SCIF_RC80MVERSION offset) 80MHz RC Oscillator Version Register */

#define SCIF_RC80MVERSION_VERSION_Pos 0            /**< \brief (SCIF_RC80MVERSION) Version number */
#define SCIF_RC80MVERSION_VERSION_Msk (0xFFFu << SCIF_RC80MVERSION_VERSION_Pos)
#define SCIF_RC80MVERSION_VERSION(value) ((SCIF_RC80MVERSION_VERSION_Msk & ((value) << SCIF_RC80MVERSION_VERSION_Pos)))
#define SCIF_RC80MVERSION_VARIANT_Pos 16           /**< \brief (SCIF_RC80MVERSION) Variant number */
#define SCIF_RC80MVERSION_VARIANT_Msk (0xFu << SCIF_RC80MVERSION_VARIANT_Pos)
#define SCIF_RC80MVERSION_VARIANT(value) ((SCIF_RC80MVERSION_VARIANT_Msk & ((value) << SCIF_RC80MVERSION_VARIANT_Pos)))
#define SCIF_RC80MVERSION_MASK      0x000F0FFFu  /**< \brief (SCIF_RC80MVERSION) MASK Register */

/* -------- SCIF_GCLKIFVERSION : (SCIF Offset: 0x3F8) (R/  32) Generic Clock Version Register -------- */
#define SCIF_GCLKIFVERSION_OFFSET   0x3F8        /**< \brief (SCIF_GCLKIFVERSION offset) Generic Clock Version Register */

#define SCIF_GCLKIFVERSION_VERSION_Pos 0            /**< \brief (SCIF_GCLKIFVERSION) Version number */
#define SCIF_GCLKIFVERSION_VERSION_Msk (0xFFFu << SCIF_GCLKIFVERSION_VERSION_Pos)
#define SCIF_GCLKIFVERSION_VERSION(value) ((SCIF_GCLKIFVERSION_VERSION_Msk & ((value) << SCIF_GCLKIFVERSION_VERSION_Pos)))
#define SCIF_GCLKIFVERSION_VARIANT_Pos 16           /**< \brief (SCIF_GCLKIFVERSION) Variant number */
#define SCIF_GCLKIFVERSION_VARIANT_Msk (0xFu << SCIF_GCLKIFVERSION_VARIANT_Pos)
#define SCIF_GCLKIFVERSION_VARIANT(value) ((SCIF_GCLKIFVERSION_VARIANT_Msk & ((value) << SCIF_GCLKIFVERSION_VARIANT_Pos)))
#define SCIF_GCLKIFVERSION_MASK     0x000F0FFFu  /**< \brief (SCIF_GCLKIFVERSION) MASK Register */

/* -------- SCIF_VERSION : (SCIF Offset: 0x3FC) (R/  32) SCIF Version Register -------- */
#define SCIF_VERSION_OFFSET         0x3FC        /**< \brief (SCIF_VERSION offset) SCIF Version Register */
#define SCIF_VERSION_RESETVALUE     0x00000130   /**< \brief (SCIF_VERSION reset_value) SCIF Version Register */

#define SCIF_VERSION_VERSION_Pos    0            /**< \brief (SCIF_VERSION) Version number */
#define SCIF_VERSION_VERSION_Msk    (0xFFFu << SCIF_VERSION_VERSION_Pos)
#define SCIF_VERSION_VERSION(value) ((SCIF_VERSION_VERSION_Msk & ((value) << SCIF_VERSION_VERSION_Pos)))
#define SCIF_VERSION_VARIANT_Pos    16           /**< \brief (SCIF_VERSION) Variant number */
#define SCIF_VERSION_VARIANT_Msk    (0xFu << SCIF_VERSION_VARIANT_Pos)
#define SCIF_VERSION_VARIANT(value) ((SCIF_VERSION_VARIANT_Msk & ((value) << SCIF_VERSION_VARIANT_Pos)))
#define SCIF_VERSION_MASK           0x000F0FFFu  /**< \brief (SCIF_VERSION) MASK Register */

/** \brief ScifGcctrl hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
  RwReg   SCIF_GCCTRL;        /**< \brief (SCIF Offset: 0x000) Generic Clock Control */
} ScifGcctrl;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

/** \brief ScifPll hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
  RwReg   SCIF_PLL;           /**< \brief (SCIF Offset: 0x000) PLL0 Control Register */
} ScifPll;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

/** \brief SCIF hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
  WoReg   SCIF_IER;           /**< \brief (SCIF Offset: 0x000) Interrupt Enable Register */
  WoReg   SCIF_IDR;           /**< \brief (SCIF Offset: 0x004) Interrupt Disable Register */
  RoReg   SCIF_IMR;           /**< \brief (SCIF Offset: 0x008) Interrupt Mask Register */
  RoReg   SCIF_ISR;           /**< \brief (SCIF Offset: 0x00C) Interrupt Status Register */
  WoReg   SCIF_ICR;           /**< \brief (SCIF Offset: 0x010) Interrupt Clear Register */
  RoReg   SCIF_PCLKSR;        /**< \brief (SCIF Offset: 0x014) Power and Clocks Status Register */
  WoReg   SCIF_UNLOCK;        /**< \brief (SCIF Offset: 0x018) Unlock Register */
  RwReg   SCIF_CSCR;          /**< \brief (SCIF Offset: 0x01C) Chip Specific Configuration Register */
  RwReg   SCIF_OSCCTRL0;      /**< \brief (SCIF Offset: 0x020) Oscillator Control Register */
  ScifPll SCIF_PLL[1];        /**< \brief (SCIF Offset: 0x024) ScifPll groups */
  RwReg   SCIF_DFLL0CONF;     /**< \brief (SCIF Offset: 0x028) DFLL0 Config Register */
  RwReg   SCIF_DFLL0VAL;      /**< \brief (SCIF Offset: 0x02C) DFLL Value Register */
  RwReg   SCIF_DFLL0MUL;      /**< \brief (SCIF Offset: 0x030) DFLL0 Multiplier Register */
  RwReg   SCIF_DFLL0STEP;     /**< \brief (SCIF Offset: 0x034) DFLL0 Step Register */
  RwReg   SCIF_DFLL0SSG;      /**< \brief (SCIF Offset: 0x038) DFLL0 Spread Spectrum Generator Control Register */
  RoReg   SCIF_DFLL0RATIO;    /**< \brief (SCIF Offset: 0x03C) DFLL0 Ratio Registe */
  WoReg   SCIF_DFLL0SYNC;     /**< \brief (SCIF Offset: 0x040) DFLL0 Synchronization Register */
  RwReg   SCIF_RCCR;          /**< \brief (SCIF Offset: 0x044) System RC Oscillator Calibration Register */
  RwReg   SCIF_RCFASTCFG;     /**< \brief (SCIF Offset: 0x048) 4/8/12 MHz RC Oscillator Configuration Register */
  RwReg   SCIF_RCFASTSR;      /**< \brief (SCIF Offset: 0x04C) 4/8/12 MHz RC Oscillator Status Register */
  RwReg   SCIF_RC80MCR;       /**< \brief (SCIF Offset: 0x050) 80 MHz RC Oscillator Register */
  RoReg8  Reserved1[0x10];
  RwReg   SCIF_HRPCR;         /**< \brief (SCIF Offset: 0x064) High Resolution Prescaler Control Register */
  RwReg   SCIF_FPCR;          /**< \brief (SCIF Offset: 0x068) Fractional Prescaler Control Register */
  RwReg   SCIF_FPMUL;         /**< \brief (SCIF Offset: 0x06C) Fractional Prescaler Multiplier Register */
  RwReg   SCIF_FPDIV;         /**< \brief (SCIF Offset: 0x070) Fractional Prescaler DIVIDER Register */
  ScifGcctrl SCIF_GCCTRL[12];    /**< \brief (SCIF Offset: 0x074) ScifGcctrl groups */
  RoReg8  Reserved2[0x334];
  RoReg   SCIF_RCFASTVERSION; /**< \brief (SCIF Offset: 0x3D8) 4/8/12 MHz RC Oscillator Version Register */
  RoReg   SCIF_GCLKPRESCVERSION; /**< \brief (SCIF Offset: 0x3DC) Generic Clock Prescaler Version Register */
  RoReg   SCIF_PLLIFAVERSION; /**< \brief (SCIF Offset: 0x3E0) PLL Version Register */
  RoReg   SCIF_OSCIFAVERSION; /**< \brief (SCIF Offset: 0x3E4) Oscillator 0 Version Register */
  RoReg   SCIF_DFLLIFBVERSION; /**< \brief (SCIF Offset: 0x3E8) DFLL Version Register */
  RoReg   SCIF_RCOSCIFAVERSION; /**< \brief (SCIF Offset: 0x3EC) System RC Oscillator Version Register */
  RoReg   SCIF_FLOVERSION;    /**< \brief (SCIF Offset: 0x3F0) Frequency Locked Oscillator Version Register */
  RoReg   SCIF_RC80MVERSION;  /**< \brief (SCIF Offset: 0x3F4) 80MHz RC Oscillator Version Register */
  RoReg   SCIF_GCLKIFVERSION; /**< \brief (SCIF Offset: 0x3F8) Generic Clock Version Register */
  RoReg   SCIF_VERSION;       /**< \brief (SCIF Offset: 0x3FC) SCIF Version Register */
} Scif;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

/*@}*/

#endif /* _SAM4L_SCIF_COMPONENT_ */


85 Charles Street is an exquisitely renovated, 20 ft-wide, 5-story, single-family townhome, ideally situated on one of the most charming tree-lined townhouse blocks in the West Village.
Meticulously renovated and modernized by Jim Joseph of Hottenroth + Joseph Architects, 85 Charles Street affords approximately 4,928 interior square feet, with 5 bedrooms, 4 full baths and 2 powder rooms. Wonderful private outdoor space is afforded in the large terrace off the Parlor Floor, and fully-finished roof deck with stunning city views, including the Empire State Building and Freedom Tower.
Outstanding home appointments include 3 wood-burning and 2 gas fireplaces, advanced security and sound systems, central air conditioning/heating, and an efficient dumbwaiter that scales the home from the First Floor to the Roof Deck.
Originally built in 1868 on the site of former Peter Warren and Abraham Van Nest Estates, this extraordinary townhome retains its restored original wide-plank pine flooring, fireplace mantels on the Parlor Floor, and Rosette-studded double entry doors.
85 Charles Street benefits from mixed-use zoning, which allows for a multitude of residential, retail, commercial and professional uses.
Perfectly positioned on a picturesque townhouse block in the heart of the West Village, 85 Charles Street lies in close proximity to the finest downtown dining, shopping, entertainment, and is just a short distance from public transportation.


Our vision is simple, treat all customers with trust, understanding, and confidence. Each customer should be treated exactly like we expect to be treated.... nothing less. Be easy to do business with and provide a reliable product so you will never have to hold a customer hostage with long term contracts. Fairness builds customer loyalty.
Telecom technology took a radical turn in the 90's. Customers needed a nimble telecom partner to stay on top of the technology shift. Vartel was created as a Value Added Resource for TELephony customers.
Most of the large telecom companies with investments in legacy telecom equipment were slow or could not make the turn quickly enough. Many of these companies are now gone.


The procedure comes with risks including infection and hearing problems.
A Facebook post showing a man with the center of his ears cut out went viral. It's called conch removal.
The procedure comes with risks, including infection and hearing problems.
This type of surgery can also be difficult to reverse as it requires two expensive surgeries, according to Paul Stanislaw, a reconstructive plastic surgeon.
Ear gauging, or stretching the ear lobe with jewelry, has been popular for years, but a new kind of dangerous ear modification is now being debated after a Facebook post showing a man with the center of his ears cut out went viral.
The modification is known as a "conch removal" and involves removing the inner cartilage of the outer ear. This leaves a big enough hole to see through the entire ear.
After the owner of a Swedish body piercing and modification shop posted the image of the conch removal to Facebook, it garnered over 39,000 comments and 17,000 shares.
"Fresh #conchremoval on @charlesvbentley who traveled around the world from Australia to have this procedure performed by me at @calmbodymodification," the post read. The post also suggested that the procedure can help people hear better from behind.
"For real, as a deaf person, can I just say f--- you?," one person wrote. "As an audiologist this is really making my eyes bleed," another wrote.
According to Paul Stanislaw, a board-certified plastic surgeon who focuses on facial reconstructive procedures, there is no proof that this type of surgery can make a person's behind-the-ear hearing better. "Ears were designed to hear better [from the] front and locate things and disrupt hearing in front of you."
Conch removal is also dangerous.
In the United States, only trained doctors with the appropriate medical licenses are allowed to perform surgeries, according to federal law. Surgery is defined as any procedures that involve removing skin or cartilage from the body, which means conch removal is illegal in the US for anyone without a license. In certain other countries (including Sweden), this isn't the case.
Dr. Stanislaw's biggest concern with conch removal is the risk for infection. "If bacteria gets in the cartilage, it's tough to treat that infection and [you] could be hospitalized and [have to] go on antibiotics. Infection would also scar up and ruin the rest of the cartilage," Stanislaw told INSIDER. An infection can occur if the conch removal isn't done under sterile conditions or the wound isn't properly cared for following the removal.
If the ear becomes infected, the delicate ear tissue will first become red and swollen, and then scar over and cause the ear to have a shriveled appearance, according to Stanislaw. Once the cartilage is shrunken, there is no way to re-inflate it.
This type of infection is less common with ear gauge modifications, since they target the soft ear lobe tissue rather than cartilage.
Another potential complication is excess water in the ears, since ear cartilage is designed to prevent water from entering the ear canals during swimming or showering.
Stanislaw has never encountered someone with a removed conch because US law makes it so difficult to find places that will perform the procedure. But he's reversed a number of ear gauge modifications, and based on those, believes an ear conch surgery reversal would be time-consuming and expensive.
Conch removal reversal would involve two separate procedures, according to Stanislaw. The first would involve sewing the remaining part of the ear against the bone behind the ear called the mastoid area. This would allow for more blood to flow to the ear and help a skin graft to grow. Then, for the second part of the procedure, Stanislaw would release the ear from its sewn up position and use the skin graft to replace the spot where the conch was formerly located.
Ear gauge reversal surgery is around $500 per ear, and Stanislaw estimates the cost would be even more for conch removal reversal since it's so complex.
When people get ear modifications reversed, it's usually out of need, not want. "I've repaired ear gauges on people and they're crying not out of pain but because it's like I'm taking away a part of their identity. It is very upsetting for people," Stanislaw said.
He said some of his patients opt to repair their ears after they've had trouble job-hunting; many employers won't accept them due to their body modifications.
"Our society is more progressive, but people still discriminate," Stanislaw said.


Did Luis Suarez cheat when he "deliberately" hand touched the jabulani ball during the last minute of Ghana versus Uruguay World Cup 2010 game at Soccer City Stadium?
FIFA's Laws of the game 2009/2010 booklet is freely available on the web for anyone to read.
My objective is to use it as a reference to determine as religiously as I can if one can call Luis Suarez a cheater or not.
The FIFA's law book among other things describes the actions the referee must take when confronted by an offence of a rule. Each offence has its associated penalty and the referee mandate is to apply it according to the law book.
and the FIFA law book says that as a result a penalty kick be awarded to Ghana and Luis Suarez be sent-off. Period.
Cheating by definition implies violating accepted standards of the game. Luis Suarez did not violate any standard, but committed two offences clearly specified in the FIFA laws booklet for which his team and him were punished accordingly.
Therefore, one can say that those who called him a cheater are either ignorant of the rules of soccer, or worse, are plain dishonest manipulators, since if Luis Suarez is called a cheater for what he did, then any player committing any offence of a rule of the FIFA "Laws of the Game" book could as well and rightfully so be called a cheater, something that is a non-sense.
Whether the "Laws of the Game" book is felt to be fair in the way it treats the Luis Suarez case, it's really another issue. While the FIFA laws book is in place, it is the only source one can honestly use to determine the answer to the posed question which cannot seriously in my opinion be based on the feelings of anyone.


text:
Valensa Awarded U.S. Patent for Eye-Health Formula
Jennifer Prince
EyePro MD is a softgel supplement that purportedly offers eye-health benefits related to its "super blend" of lutein, zeaxanthin, astaxanthin, and omega-3s.
Valensa International (Eustis, FL) announced that it has received a patent from the U.S. Patent and Trademark Office for its proprietary eye-health ingredient combination, EyePro MD. EyePro MD is a softgel supplement that purportedly offers eye-health benefits related to its "super blend" of lutein, zeaxanthin, astaxanthin, and omega-3 fatty acids from krill, algae, or perilla seed.
EyePro MD is produced through Valensa's own supercritical CO2 purification process and O2 peroxidation blocker technology, says the company, and is formulated with its proprietary Zanthin astaxanthin, XanMax lutein plus zeaxanthin, perilla seed–derived ALA omega-3 fatty acids, and seed-based phospholipids. It can also add omega-3 fatty acids from krill and algae oil. In addition, the formula is zinc-free, non-GMO, organic, and contains no allergens. The company notes that several studies have previously been conducted on the benefits of carotenoids for eye health functions, as well as research on astaxanthin for treatment of eye fatigue and protection from blue light.
"We have designed a small softgel loaded with a potent combination of ingredients that can be absorbed efficiently to optimize eye health," said John Minatelli, PhD, senior vice president of business development, Valensa, in a press release. "Now with the patent IP in place, distributors and manufacturers from the food and nutraceutical industry can include EyePro MD in their products knowing there's nothing else like it on the market."
The company recommends a daily dose of one EyePro capsule, or 250 mg, per day. EyePro MD was awarded Patent No. 9,610,313, and is available for distribution as a finished product or formulation under license.
Eye-Health Ingredient Research Update
Valensa to Launch "Nature Equivalent" Astaxanthin
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