The invention relates to a device, system, and method for expanding the memory capacity of a memory module. A control unit and memory bank switch are mounted on a memory module to selectively control write and/or read operations to/from memory devices communicatively coupled to the memory bank switch. By selectively routing data to and from the memory devices, a plurality of memory devices may appear as a single memory device to the operating system. That is, the invention expands the addressable memory banks on a module by making two smaller-capacity memory devices emulate a single higher-capacity memory device.
Various embodiments of the invention pertain to memory devices. At least one embodiment of the invention pertains to a controller and architecture that permits transparent bank switching of memory devices.
Memory devices have widespread use in electronic products. Many computing devices enable memory expansion by including one or more slots in which to couple a memory module. One type of commonly used memory module is the dual inline memory module (DIMM). Typically, memory modules include a small circuit board with contact pads along one edge to couple to a slot on another circuit board, such as a computer motherboard. In some cases, the contact pads are placed on two surfaces of the small circuit board along an edge of the small circuit board. In some implementations, the number and size of the contact pads may be defined by various bus or communication standards. In other implementations, the physical space available for such contact pads and/or electrical traces or buses may determine the number and size of the contact pads.
Memory devices are typically mounted on one or two surfaces of the small circuit board of the memory module. Dynamic random access memory (DRAM) chips are often used in memory module applications. The memory devices are communicatively coupled to the contact pads such that data may be sent to a memory module and stored in the memory devices. Various electrical paths are used to transfer data, specify a memory address, and control the flow of the data to and from the memory devices.
To access locations in memory devices, such as DRAM, a memory location is typically specified by the system over an address bus. This address is decoded to access the correct memory device. Some memory systems map memory addresses into a column and row. Row address and column address signals are time-multiplexed to permit a greater number of memory locations to be addressed without increasing the number of address lines.
As electronic devices become more sophisticated, the need for greater storage or memory increases. Since many electronic applications are restricted by industry standards and physical limitations prevent increasing a bus size (i.e., adding more contact pads and/or electrical paths to a memory module and/or system memory controller is often prohibitive) the maximum size of the addressable memory on a memory module may be limited. Thus, increasing the memory capacity of a memory module would require a larger bus size. This is often undesirable and impractical for backward compatibility of existing devices and established industry standards.
U.S. Pat. No. 6,526,473 describes a scheme to speed up the writing and reading cycles to memory devices. A control signal is used to connect only selected memory modules to a data bus at one time during a data transfer cycle in which data is input and output. By connecting only the addressed memory module(s) to the data bus, the load capacitance on the data bus is minimized. While this scheme provides ways to speed up writing to and reading from memory devices, it does not enable expanding the total memory capacity of a system beyond the limits of the data bus used.
U.S. Pat. No. 6,070,217 describes a scheme to maximize the memory capacity of a memory module while minimizing the capacitive loading of the data bus. Switches are placed between the bus interface and memory devices to activate or deactivate the line to the memory devices. When deactivated, the switches present high impedance thereby reducing the loading on the data bus. When a switch is activated, only the corresponding memory device is activated and adds a minimal capacitance to the data bus. While this patent presents a solution to bus loading, it does not enable expanding the total memory capacity of a system beyond the limits of the data bus used.
U.S. Pat. No. 6,414,868 describes a memory expansion module including an upper and a lower memory bank and a control unit that selects between the upper and lower memory banks based on an external bank select signal. That is, two memory banks are added to the memory module and the controller selects which memory bank to access based on an externally generated signal (i.e., high-order address bit). This scheme is undesirable as it is incompatible with modern memory devices (e.g., DDR and DDR2 SDRAM) and industry standards.
U.S. Patent Publication 2004/0000708 describes a stacked chip scale-packaged memory module that conserves board space while reducing bus impedance. A high-speed switching system, field effect transistor (FET) switches, is employed to select a data line associated with each level of a stacked memory module to reduce the loading effect on the data lines in memory access. The problem with this scheme is that while FET switches have a fast propagation delay, their switch time is too slow and imprecise to reliably comply with industry standards, such as the Joint Electron Device Engineering Council (JEDEC) standards, used in many memory applications.
The invention relates to a device, system, and method for expanding the memory capacity of a memory module. A control unit and memory bank switch are mounted on a memory module or, alternately, on a system motherboard to selectively control write and read operations to/from memory devices communicatively coupled to the memory bank switch. By selectively activating or deactivating the memory devices in real-time, separate smaller-capacity memory devices may emulate a single larger-capacity memory device. That is, the invention expands the addressable memory capacity on a module by making two smaller-capacity memory devices emulate a single higher-capacity memory device. A state machine is used to send Read/Write commands to the intended memory bank while sending no-operation commands to the other memory bank. This permits maintaining multiple memory banks communicatively coupled to the data bus without device activation and termination cycle delays.
One embodiment of the invention provides a system having a processor, a bus communicatively coupled to the processor to carry data to and from the processor, and memory sockets coupled to the bus. A memory module is coupled to a memory socket, the memory module including a control unit to receive memory address information from the bus, and a memory bank switch communicatively coupled to the control unit and the bus. The control unit maps a received logical address to a physical address corresponding to the particular memory bank configuration employed. It also directs commands to the memory banks to indicate which memory bank should be operational and which one should be passive (do nothing). The memory bank switch is designed to receive data information from the bus and direct the data information to a plurality of physical memory banks according to control signals from the control unit that maps one logical memory bank to a plurality of physical memory banks. The memory module further includes a plurality of memory devices coupled to the plurality of physical memory banks, the plurality of memory devices appearing as a single memory device to the system processor. That is, the emulated single memory device has the capacity of the combined plurality of memory devices.
The invention expands the memory capacity of a memory module by using a plurality of smaller-capacity memory devices that function as a single higher-capacity memory device. This is accomplished without the need to add more lines to the bus or any additional external signal. Moreover, the load on the bus is not increased because the memory bank switches present a single load to the bus, not the load of the individual memory devices coupled thereto. A control unit provides a state machine that controls the commands to a plurality of memory devices in multiple banks so as to read/write a single memory bank without the need to disconnect the other memory banks from the data bus.
FIG. 1 illustrates a computing system that includes a capacity-expanding memory device according to one embodiment of the invention.
FIG. 2 illustrates a block diagram of a capacity-expanding memory device according to one embodiment of the invention.
FIG. 3 illustrates a block diagram of an address and command processing system for a capacity-expanding memory device according to one embodiment of the invention.
FIG. 4 illustrates a block diagram of a data processing system for a capacity-expanding memory device according to one embodiment of the invention.
FIGS. 5 and 6 illustrate memory modules according to two different embodiments of the invention.
FIGS. 7A-F illustrate an address mapping table, or bank switch state machine, that may be used by the control unit to map a received address (primary address space) to one of the memory banks (secondary address space) according to one embodiment of the invention.
FIGS. 8A-B illustrate a command scheme for a control unit to operate multiple banks concurrently according to one embodiment of the invention.
FIG. 9 illustrates a plurality of bits that are squelched from the original extended mode register set (EMRS) command according to one embodiment of the invention.
FIGS. 10, 11, 12 and 13 illustrate different configurations of memory modules (e.g., DIMMs) that can be built using combinations of the control unit and bank switch according to various embodiments of the invention.
In the following description, certain terminology is used to describe certain features of one or more embodiments of the invention. The term "memory device" refers to any device capable of storing information, including DRAM. The term "memory module" refers to any package in which one or more memory devices are mounted (e.g., DIMM, SIMM, etc.).
One embodiment of the invention relates to a system that expands the memory capacity of a memory module without increasing the bus size. A controller and memory bank switch allow the use of separate smaller-capacity memory devices to emulate a single higher-capacity memory device to a host system. This effectively expands the number of addressable banks per memory module without the need for additional chip select lines on the main memory bus. For example, the invention expands the addressable memory banks on a module by making two smaller-capacity memory devices emulate a single higher-capacity memory device. In one implementation, the invention permits two separate SDRAM DDR devices to appear as a single higher-capacity SDRAM DDR device to a source device (e.g., microprocessor, memory controller, etc.).
FIG. 1 illustrates a computing system 100 that includes a capacity-expanding memory device according to one embodiment of the invention. The computing system 100 may include a processing unit 102 coupled to an input/output (I/O) controller 104 to receive and/or send information. The processing unit 102 may also be coupled to a memory module 106 to retain or store information. The memory module 106 may include an embodiment of the capacity-expanding memory device 108 that permits increasing the memory capacity without increasing the bus size or communication path 110 to and/or from the memory module 106. In one implementation of the invention, the bus size or communication path 110 to and/or from the memory module 106 is not modified to accommodate the capacity-expanding memory device 108. Thus, the capacity-expanding memory device 108 is compatible with existing system architectures and transparent to the rest of the system (e.g., microprocessor, operating system, etc.). Moreover, the resistive and/or capacitive load on the bus 110 is not increased because the memory module 106 presents a single load to the bus 110, not the load of the individual memory devices coupled thereto.
FIG. 2 illustrates a block diagram of a capacity-expanding memory system 200 according to one embodiment of the invention. In this embodiment of the invention, the capacity-expanding memory system 200 is communicatively coupled to a DIMM interface 202. The DIMM interface 202 may be coupled to a memory socket and communication bus over which data, memory addresses, commands, and control information are transmitted. The capacity-expanding feature of the invention is accomplished by a combination of a control unit 204 and one or more memory bank switches 206 & 208.
The control unit 204 receives memory addresses and commands over the DIMM interface 202. In one embodiment of the invention, memory bank switches 206 & 208 receive data information from the DIMM interface 202 via data buses 230 & 232, respectively. The control unit 204 is communicatively coupled to the dual memory bank switches 206 & 208 via a control bus 210 and indicates to the memory bank switches 206 & 208 how data from the DIMM interface 202 should be received and/or stored.
According to one embodiment of the invention, the DIMM interface 202 provides a range of data bits simultaneously (e.g., Data Group 0 through Data Group N). A first data group (i.e., Data Group 0) is received by a first memory bank switch 206 while a second data group (i.e., Data Group N) is received by a second memory bank switch 208. Each memory bank switch 206 & 208 is communicatively coupled to a plurality of memory banks that may have one or more memory devices (e.g., dynamic random access memory (DRAM)). Data may be read from or written to these memory devices using any known addressing scheme (e.g., mapping memory addresses into a column and row). For example, memory bank switch 206 includes Port A and Port B, coupled to data busses 234 & 236 respectively, through which it sends and receives data information to and/or from four memory banks (i.e., Bank 0, Bank 1, Bank 2, and Bank 3). The four memory banks (i.e., Bank 0, Bank 1, Bank 2, and Bank 3) 212, 214, 216, and 218 are also communicatively coupled to an address bus 220 through which they receive address and command information from the control unit 204. Clocking information (Ck/Ck#) is received from the DIMM interface 202. An external phase lock loop (PLL) 238 regenerates a clock signal that can be used by the components on the memory system 200. The switch 208 may contain an internal PLL which derives the clock provided to the memory devices from the output of the external PLL 238.
In one embodiment of the invention, the control unit 204 decodes a memory address received over the DIMM interface 202, determines to which memory bank the received address corresponds, and causes the memory bank switch 206 and 208 to activate the correct memory bank. For example, if the control unit 204 determines that a particular address is associated with, or mapped to, Bank 1 212 coupled to memory bank switch 206, then it causes Port B to be activated and Port A to be disabled so that the data is written to the correct memory bank 212. Additionally, each memory bank switch 206 and 208 includes signal drivers to drive data signals to and from the memory banks and to and from the DIMM interface 202. This reduces resistive and/or capacitive loading of the data bus coupled to the DIMM interface and the bus 110 while emulating a standard memory device interface.
The control unit 204 may map a received address in a number of ways without departing from the invention. For instance, the control unit 204 may simply associate the lower memory addresses with Port A and higher memory addresses with Port B. Although address information may be sent to all memory banks over address bus 220, the memory bank switch 206 and/or control unit 204 determine which memory devices or banks are accessed (for either Read and/or Write operations, or other operations). The control unit 204 may implement a state machine that controls memory bank switches 206 and 208 thereby controlling which memory banks/devices coupled to Ports A and B are accessed.
According to one embodiment of the invention, the operation of the switch 206/208 and control unit 204 will vary depending on the memory addressing scheme (e.g., column or row addressing) implemented. In column mode operation, to meet system timing requirements, write-data is sent to both ports A and B of the switch 206/208 and control unit 204 uses the data mask (DM) signal to select the target memory device. That is, the DM signal indicates to which target memory device (e.g., Bank 0 214, Bank 1 212, Bank 2 218, or Bank 3 216) the data is written. Note that the DM signal 217/219 at the switch 206/208 is controlled by the control unit 204. Memory read operations, in column mode, work in a similar way as memory write operations. Both memory devices (e.g., Bank 0 214 and Bank 1 212), coupled to ports A and B, are read and the data from the selected target memory device is multiplexed onto the DIMM interface 202. That is, only the data read from the selected target memory device is sent to the DIMM interface 202. Alternatively, when row/bank mode addressing is used, read and write commands are sent only to the targeted memory device. A NOP (no-operation) command is sent to the non-targeted memory device.
In one embodiment of the invention, a Serial Presence Detect (SPD) feature is implemented to collect and store the memory module configuration. The memory control configuration is communicated to the host system and stored. The memory module reports the total module memory capacity and data width along with the individual emulated memory device capacity that is formed by two or more small-capacity memory devices. The Serial Presence Detect operation is a standard feature of many DIMM modules.
In one embodiment of the invention, the control unit 204 is configurable via programmable pins (e.g., through logical pull-up or pull-down voltages, etc.) to have information about the type and size of memory devices coupled to the memory banks (e.g., Bank 0, Bank 1, Bank 2 and Bank 3). The control unit 204 is configured to recognize that a plurality of smaller-capacity memory devices is coupled to a particular memory bank switch. The control unit 204 then handles mapping the logical memory addresses it receives via the DIMM interface 202 to a corresponding bank for a particular memory bank coupled to the switches 206 and 208. This same principal is expanded when implementing a wider memory bus formed by several data groups composed of a plurality of memory bank switches and the associated memories.
The state machine implemented by the control unit 204 directs data to a particular memory bank based on the memory configuration of memory banks and the address received. For example, one or more of the address bits (e.g., in a column and/or row address bits) may be used to direct data to a particular memory bank.
FIGS. 7A-F illustrate an address mapping table, or bank switch state machine, that may be used by the control unit to map a received address (primary address space) to one of the memory banks (secondary address space) according to one embodiment of the invention. In this particular example, addresses are represented as memory rows and columns. Depending on the physical memory configuration detected, the control unit 204 selects a particular address bit (e.g., the most significant address column or row bit) from the received address to map to the memory banks. For example, where a DDR 1, 2×256 Megabyte (×4) configuration is used in the memory banks, the address bit corresponding to Column 12 is used to select a memory bank (banks on Port A or Port B). Also, where a DDR II, 2×1 Gigabyte (×8) configuration is used in the memory banks, the address bit corresponding to Row 14 is used to select a memory bank (banks on Port A or Port B). Thus, a primary space address received by the control unit 204 is mapped to a secondary space address corresponding to the memory banks.
According to one embodiment of the invention, an application specific integrated circuit (ASIC) contains both the memory bank switch 206 and control unit 204 functions on a single die. This die is configurable to operate as either the memory bank switch 206 or the control unit 204 through a selection pin or pad.
FIG. 3 illustrates a block diagram of an address and command processing system 300 for a capacity-expanding memory device according to one embodiment of the invention. This address and command processing system 300 may be implemented as part of the control unit 204. The command processing system 300 controls physical bank selection and bank switching direction. Memory addresses and command information are received from the DIMM interface 202, buffered in a register 302 and sent to all memory banks (e.g., Bank 0, Bank 1, Bank 2 and Bank 3) over address bus 220. The memory address and command information is also decoded 304 and memory configuration information 306 (e.g., DRAM type, etc.) is determined. The memory configuration information may be determined from preset information. A bank switch state machine 308 then determines which memory bank should be activated or accessed. In one embodiment of the invention, this state machine 308 is a logical translation table that maps a primary space address to a secondary space address based on the memory configuration present. For example, the state machine 308 may be the address mapping table illustrated in FIGS. 7A-F, which was previously described. The state machine 308 sends control information to the memory bank switches 206 & 208 via the control bus 210 to indicate which memory banks should be activated/deactivated or accessed.
In one embodiment of the invention, the control unit 204 maps one logical memory bank to two physical memory banks. This is accomplished by selectively enabling or activating one of the two physical memory banks (e.g., either Port A or Port B) while disabling or deactivating the other. In this manner, only one of the two physical memory banks is written to or read from. This scheme permits the operating system to generate memory addresses for a single, larger-capacity memory device while the control unit 200 maps that memory address to a plurality of smaller-capacity memory devices. Thus, the control unit 204 is able to map one logical memory bank to a plurality of physical memory banks.
One embodiment of the invention provides a novel scheme for performing operations in a first memory bank (i.e., Port A in FIG. 2) without disabling or deactivating a second memory bank (i.e., Port B in FIG. 2). This scheme permits the memory bank switch 206 to operate in real-time and without noticeable delays. For example, in one implementation of the invention, the control unit 204 (FIG. 2) operates to send commands or instructions to two or more memory banks (e.g., Ports A & B) concurrently. That is, the control unit 204 sends the intended instruction to the selected memory bank and sends a no-op (no operation) instruction to the other memory bank(s).
FIGS. 8A-B illustrate a command scheme for the switch/control unit combination to operate multiple banks concurrently according to one embodiment of the invention. In this implementation, two memory banks (i.e., DDR A and DDR B) are controlled by a control unit 204. An exemplary set of memory commands and/or operations are illustrated. Depending on which command is invoked and the memory addressing scheme used (e.g., column or row addressing), the control unit 204 operates to send either the same command to both memory banks (DDR A and DDR B) or different commands to each memory bank. For example, a "WRITE" command from the control unit 204 causes a "WRITE" operation to be sent to the intended memory bank (as determined by the address mapping) and a NOP command (no operation) to be sent to the other memory bank. Thus, data is written to a memory bank (e.g., banks on DDR A) while the other memory bank (banks on DDR B) receive a NOP. A "READ WITH AUTO PRECHARGE" (READAP) command would cause different actions depending on the addressing mode or memory configuration. If Row/Bank addressing is used, then a READAP command is sent to the intended bank while a NOP command is sent to the other bank. If Column addressing is employed, then the same READAP command is sent to both DDR A and DDR B. In Column addressing, the data mask (DM) signal (FIG. 2) may be used to select the target memory device (i.e., banks on DDR A or DDR B) to which data is written. Similarly, other instructions are implemented where either (1) the commands are sent to both memory banks/devices and a DM signal is used to select the targeted memory device or (2) the command is sent to the targeted device while a NOP command is sent to the non-targeted memory device. Thus, the control unit and switch architecture can control data to and from the memory banks without the delays caused by otherwise disabling the banks.
Note that RC MODE INVERT in FIGS. 7A-F refers to a feature that may be used for expansion to larger target DDR SDRAMs. The RC MODE INVERT input swaps between column and row mode to select the value of the addressing to configure the controller and memory switch, accommodating variations in future memory device organization.
Another feature of the invention squelches or suppresses extended mode register set (EMRS) commands from being passed to the SDRAMs. Instead of passing these commands directly to the memory devices, the control unit passes the command to the memory bank switch where the values are stored and one or more of the EMRS commands are squelched, modified, or suppressed. FIG. 9 illustrates a plurality of bits that are squelched from the original EMRS command according to one embodiment of the invention. The squelch function allows the memory devices to be configured to operate in conjunction with the controller/switch devices and host system, rather than be directly programmed by the host system.
FIG. 4 illustrates a block diagram of a data processing system 400 for a capacity-expanding memory device according to one embodiment of the invention. This data processing system 400 may be implemented as part of the memory bank switch 206. Data is transmitted from the DIMM interface 202 via the data bus 230 to bidirectional signal drivers 402 & 404 that transmit and receive data over separate data busses 234 and 236 to the different sets of memory banks. A read/write logic unit 406 determines whether data is being read from or written to the memory devices (e.g., 212). Memory configuration information 408 is obtained from the control unit. An off-chip driver (OCD) state machine 410 is used by the system for impedance calibration using this tuning mechanism to adjust buffer drive strength to the DIMM interface 202. Typically, this impedance calibration takes place in the memory devices themselves, but in the present invention the OCD function is shifted to the switch device that sits between the memory devices and the DIMM interface.
According to one embodiment of the invention, the control system 300 and memory bank switch system 400 may be implemented on the same semiconductor die. The semiconductor die may be configurable (via a selectable line/pin, for example) to operate as either a control unit 204 or a memory bank switch 206. The control unit 204 and/or memory bank switch 206 may be implemented as an application specific integrated circuit (ASIC). In one embodiment of the invention, the control unit and bank switch combination allows the use of a system with two separate SDRAM DDR devices to emulate a single, two-times capacity, SDRAM DDR device. In various embodiments of the invention, the control unit and bank switch combination may support SDRAM DDR1 and DDR2 specifications (incorporated herein by reference) with memory capacities of 256 Mb, 512 Mb, and 1 Gb in speed grades of 200/266/333/400 Mbps in DDR1 and capacities of 256 Mb, 512 Mb, 1 Gb, and 2 Gb in speed grades of 400/533 Mbps in DDR2.
FIGS. 5 and 6 illustrate memory modules according to two different embodiments of the invention. In FIG. 5, the memory module 500 includes a substrate 502 on which a plurality of memory devices 504 are mounted. The memory module 500 also includes an edge interface 506 that serves to communicatively couple the memory module 500 to a memory slot or to a communication bus (e.g., memory bus, etc.). A memory controller 510 is mounted on the substrate 502 and configured to control write and read operations to/from the memory devices 506. The memory controller 510 is communicatively coupled to the edge interface 506 and receives address, command, and control signals from the edge interface 506. The memory controller 510 is also communicatively coupled to one or more memory bank switch 508 to control data Read and/or Write operations to/from the one or more memory devices 504 & 512. Memory bank switch 508 is communicatively coupled to memory devices 504 & 512 to route data to and from one or more of the memory devices 504 & 512. The memory bank switch 508 is also communicatively coupled to the edge interface 506 to pass signals between the edge interface 506 and the memory devices 504 & 512.
The operation of the memory controller 510 and memory bank switch 508, as previously described, causes the memory devices 504 & 512 to emulate a single memory device having the total capacity of the combined memory devices 504 & 512. That is, the operating system addresses a single logical memory bank which is mapped by the controller 510 to the physical banks of memory devices 504 & 512. An external phase lock loop (PLL) 514 receives a clock signal from the edge interface 506 and provides a clock signal to the memory module components.
According to one embodiment of the invention, a memory controller 510 is a control unit 204 and the memory bank switches 508 are memory bank switches 206 as described above. In various embodiments of the invention, the memory bank switches 508 may be electrically coupled to two or more memory devices 504 & 512, thereby expanding the capacity of a memory module 500.
In one implementation of the invention, illustrated in FIG. 5, the memory devices 504 & 512 on the memory module 500 may be arranged as nine memory bank switches or sets 508 having two memory banks 504 & 512 each. Each memory device has five hundred and twelve (512) megabits (MBit) of DRAM. As a result of this arrangement, the memory module 500 uses 512 MBit DRAM devices but appears, to the system processor, as a 1 GBit DRAM device. As a result of this architecture, the memory module presents a single electrical load to the system and is compatible with existing standards (e.g., JEDEC compatible, etc.). The Joint Electron Device Engineering Council (JEDEC) standards, used in many memory applications, are incorporated herein by reference.
FIG. 6 illustrates another embodiment of the invention in which four banks of five hundred and twelve (512) megabits (MBit) memory devices 606, in a dual stacked configuration, are used. This memory module 600 uses a dual stack configuration (similar to that illustrated in FIG. 11) in which two control units 604 are employed, one control unit 604 on each side of the module 600. As a result of this arrangement, the memory module 600 uses 512 MBit DRAM devices which appear to the system processor as 2 GBit DRAM devices.
FIGS. 10, 11, 12 and 13 illustrate different configurations of memory modules (e.g., DIMMs) that can be built using combinations of the control unit and bank switch according to various embodiments of the invention. These configurations employ the control unit and bank switch previously described.
FIG. 10 illustrates a single chip-select memory configuration in which one control unit 1002 and one bank switch 1004 are used to control two memory banks 1006 & 1008, each memory bank having two memory devices 1010 & 1012 in separate data buses 1014 & 1016.
FIG. 11 illustrates a dual chip-select memory configuration in which two control units 1102 & 1104 and one bank switch 1106 are used to control two memory banks 1108 & 1110, each memory bank having four memory devices 1112.
FIG. 12 illustrates a single chip-select memory configuration in which one control unit 1202 and one bank switch 1204 are used to control two memory banks 1206 & 1208, each memory bank having one memory device 1210.
FIG. 13 illustrates a dual chip-select memory configuration in which one control unit 1302 and one bank switch 1304 are used to control two memory banks 1306 & 1308, each memory bank having two memory devices 1310 in one common bus.
Note that the fast switching between memory banks the switch and control architecture of the present invention permit memory access and distributed selection between memory devices at speeds not achievable in the prior art that complies with the standards for DDRI and DDRII. Field Effect Transistor (FET) based switches are too slow for the required high-speed switching as their switching speed is too imprecise. For example, the present invention can be implemented in DDRII systems operating at 533 MHz or higher.
a memory bank switch communicatively coupled to the control unit, the memory bank switch to receive data information and direct the data information to one of a plurality of physical memory banks in real-time according to control signals from the control unit.
a plurality of memory devices coupled to the plurality of physical memory banks, the plurality of memory devices appearing as a single memory device to external sources, wherein the memory bank switch includes signal drivers to present a single load to a bus coupled to the memory bank switch.
wherein the control unit sends a read or write command to the first memory device while sending a no-operation command to the second memory device to cause the memory bank switch to read data from or write data to the first memory device.
4. The system of claim 1 wherein the control unit is configured to identify extended mode register set (EMRS) commands and suppress them from being passed to the plurality of physical memory banks.
5. The system of claim 1 wherein the control unit and memory bank switch are both included in a single application specific integrated circuit that can be configured to operate as either the control unit or the memory bank switch.
a memory bank switch mounted on the substrate, the memory bank switch to transfer data information to and from two or more physical memory banks in real-time according to control signals from the controller that map one logical memory bank to the two or more physical memory banks.
a plurality of memory devices communicatively coupled to the two or more physical memory banks, the plurality of memory devices appearing as a single memory device to external data sources, the memory bank switch including signal drivers to present a single capacitive load to a bus coupled to the memory bank switch.
an edge interface along an edge of the substrate, the edge interface communicatively coupled to the controller to provide address information to the controller, the edge interface also communicatively coupled to the memory bank switch to provide data information to the memory bank switch.
10. The memory module of claim 6 wherein the memory module is a dual inline memory module compliant with a Joint Electron Device Engineering Council (JEDEC) standard.
the device being configurable to operate either as a memory control circuit or a memory bank switch circuit.
12. The device of claim 11 wherein the plurality of physical memory banks appears as a single memory bank to external data sources, the control unit is configured to receive a read or write command and send the read or write command to the first memory device while sending a no-operation command to the second memory device to cause the memory bank switch to read data from or write data to the first memory device.
13. The device of claim 12 wherein the single memory bank has the apparent capacity of the combined memory devices coupled to the plurality of physical memory banks.
14. The device of claim 11 wherein the memory bank switch circuit also retrieves data information stored in plurality of physical memory banks and transmits it to a bus.
a memory bank switch communicatively coupled to the control unit and the bus, the memory bank switch to receive data information from the bus and direct the data information to one of a plurality of physical memory banks according to control signals from the control unit that map one logical memory bank to a plurality of physical memory banks.
a plurality of memory devices coupled to the plurality of physical memory banks, the plurality of memory devices appearing as a single memory device to the processor.
17. The system of claim 16 wherein the single memory device has the capacity of the combined plurality of memory devices.
an edge interface along an edge of the memory module, the edge interface communicatively coupled to the control unit to provide address information to the control unit, the edge interface also communicatively coupled to the memory bank switch to provide data information to the memory bank switch.
19. The system of claim 15 wherein the memory module is a dual inline memory module compliant with a Joint Electron Device Engineering Council (JEDEC) dynamic random access memory (DRAM) standard.
20. The system of claim 15 wherein the memory bank switch also retrieves data information stored in plurality of physical memory banks and transmits it to the bus.
placing a memory bank switch on the substrate, the memory bank switch communicatively coupled to the control unit and the edge interface, the memory bank switch to receive data information from the edge interface and direct the data information to one of a plurality of physical memory banks according to control signals from the control unit that map one logical memory bank to a plurality of physical memory banks.
placing a plurality of memory devices on the substrate, the memory devices communicatively coupled to the plurality of physical memory banks, the plurality of memory devices appearing as a single memory device.


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Chris Graham (RGM 02/12/17)
Thank you for this interview it is an honour for me to interview such a Legend…
What did you want to do when you were at school for a career and what was your first job?
Throughout my school life I always wanted to get a job that involved drawing or art in some way, seemed to be the only thing I was really any good at or knew anything about. Art was the thing that kept my mates happy or bullies off my back throughout my school life. I would spend hours at home doing pencil drawings of Knight Rider, the A-Team, Airwolf or DangerMouse, bring the drawings into school the next day and distribute them out.
The only computers we had at school were BBC micros, not really the thing that was going to get me excited about a possible career in computers! (more likely to turn you off the idea!). I remember these as massive, great hulking things that almost required you to use your whole hand to push one of the keys down on the keyboard! (with a satisfying 'klunk' sound)
Chris done this for RGM
When I left school my first 'job' wasn't a job as such, It was working on a YTS (Youth Training Scheme). It was held in a classroom environment and involved producing different kinds of artwork with different materials. I was doing the thing I'd always wanted to do and being paid for it, but at £40 per week it was never going to get me anywhere.
What was your first computer is that your favourite computer or do you have a different favourite?
The Speccy was my first computer. My mate up the road had one and having played for hours on his, I had to have one too. It was like a box of dreams! Every game seemed to stretch your imagination and it felt like every game had endless possibilities. I remember playing Skool Days and thinking that there was nothing you couldn't do in it, it was like an interactive experience. I used to go home thinking of things I could try and do within the game when I was next around at my mates.
I completely loved the Speccy, it was my favourite home computer, followed very closely by the Amiga.
When and how did you to get into game industry?
Well, after discovering that there was more to the Speccy than just playing games, I started messing around with graphics. It was like stepping through a portal into another world! I could actually draw anything I wanted using all the graphical might of the Speccy(!). I began churning out graphics and screens and after a while this soon became a hobby. Eventually, after a long while, I began to show these screens to my friends who were genuinely surprised that I had kept my computer artwork secret for so long. I never really thought much of it, it was just something I enjoyed doing, didn't seem like I had broadcast it.
Many months passed then one day a friend of mine saw an advertisement for Codemasters in the back of one of those bi-weekly computer mags. It was a recruitment drive for artists to join the software company. One of my mates had saw this ad and suggested I go for it, I shrugged this off as a bad joke, my work was OK but nowhere near the level of some of the big names around at that time. This friend persisted with his suggestion for the next few weeks, eventually, after I had my head completely pecked, I said 'OK' but only if he were to write a covering letter for me, I might give it some thought.
Well, this 'friend' actually did produce a well written/crafted letter that surprised me as I thought he was trying to take the p*ss all this time! Anyway, I gathered some of my screens and graphics samples together and slapped them onto a C90. The cassette and letter where then fired across to Codemasters, I thought nothing more about.
About a week-or-so later, I came home from my YTS and was greeted by a large cardboard box that had been delivered to me. Inside, there was a big collection of Codemasters Speccy games along with a letter. The letter said that my artwork had been assessed and that they were very impressed with what they saw and would I be able to visit their offices for a chat. I was completely gob-smacked and I couldn't believe it.
What was your first day at Codemasters like and who made you feel welcome?
Tim Miller (programmer on ATV Simulator) was very kind and took me around all the offices at Codemasters. Back then it was converted farmhouse and a small bunch of porta' cabins. I sat with different programmers and artists throughout the first day and everybody was kind enough to explain what they did, what a normal working day was like and what people tended to do after work. I took very little in, I was completely starstruck.
When I first started work at Codemasters I had nowhere to stay so I was living from a hotel. Some weekends, when I was working at the offices, instead of getting a taxi back to Leamington Spa to my hotel, I'd sleep in a porta cabin overnight in a sleeping bag. I'd stay up most of the night playing games on all the different computers and consoles that surrounded me, it was heaven!
Your first project at Codemasters?
Strangely enough, Rockstar was my first project! They really shoved me into the deep-end with that one! After my initial talks with Codemasters they revealed that they wanted to create their first 'full price' game. It was to be a game based on the pop music industry, and they wanted me on-board straight away! Things seemed to move very fast after that and I
What is the funniest thing and most frustrating thing that happened to you at Codemasters?
I remember one time when the Darling brothers were racing an old, rusty moped around the fields at the back of their old farmhouse. They asked me and some other developers to join in taking it in turn to race this thing around a field. On my turn I hit a bump and was flung through the air before landing on the grass in a crunched up heap. I remember lying on the grass and laughing my head off about it, the whole situation, where I was with my life and how things had progressed. I lay back on the grass, looked up at the sky and waited for the inevitable alarm clock to wake me up for another day at YTS, it didn't. I felt like the happiest person alive.
While living in Leamington Spa I was involved in a nasty road traffic accident and ended up in a bad way in hospital. I was in there for some weeks and went through a phase of re-evaluating my life and which direction my life was taking me. I slowly fell out of love with the graphics side of the industry and wanted to try something new. I found this very frustrating as I knew I had the capability to continue doing what I did, it's just that my heart was no longer in it.
What is your favourite game you have worked on during your time at Codemasters?
All the games I had worked on at Codemasters were all great experiences for one reason or another. If pushed though, I'd have to say Rockstar was my favourite. It was my first project in the industry, it turned out OK and it's the one that raises a smile when mentioned in conversation.
I am a huge fan of Rockstar Eat My Hamster and really loved the game and music. Please tell us about the development of the game graphics?
Oh God, where do I start?! Colin Jones (programmer) wanted something along the lines of Spitting Image, but not Spitting Image at the same time(!). I found this very difficult as it was completely hard to create a characterisation of a famous popstar while keeping them recognisable all within the limitations of the area requested, plus not having them look like Spitting Image puppets.
I remember spending hours and hours in the library, in newsagents and in book stores trying to find photo references of all the artists that were going to be in the game. The same amount of time was spent on photocopiers trying to capture the images. Life before the internet was very tough J
It seemed like it took an eternity to create the characters. I stressed endlessly about how they looked and if people would recognise them. I would stay awake all night creating characters, deleting characters, re-starting characters, moving pixels a couple of places. There were some dark days and darker nights involved in their creation but they turned out alright in the end, I think.
Did you think there would be an issue with the Music Artist at the time?
I really didn't think any of my characterisations would have caused offence (soz, if it did…). Looking back, I could have been a hell of a lot more scathing with the graphics, but I was young and didn't fancy the idea of one o f the stars kicking-off because of something I had created.
When the game was released, I remember Boots refused to stock it because of some of the content that was published in the free magazine you got with the game. At the time, I thought that was pretty 'rock and roll'.
A few of the artist now are a bit dodgy in the game would you ever consider doing a remake this would be amazing maybe get Allister Brimble to do the music?
A re-make!? If the opportunity came along, I'd like to give it a go! I love the thought of the game with a modern make-over. You'd have Clive on his mobile and Cecil trying to broker some marketing deal via a dodgy website on his laptop. You could have your band appear on a 'I'm a rockstar, get me outta' here!' type TV show. You could give your stars their own 'FarceBook' accounts and create a website for their marketing. There's an absolute ton-of-stuff you could include in a game like that these days.
I understand that you done the graphics for Rockstar Eat My Hamster, Magicland Dizzy, Kwik Snax and the CJ's Elephant to name a few. Please tell me what the best part of making these games and the most frustrating parts?
I think I pondered on my graphics far, far too much, especially on Rockstar. I would lie awake at night and worry about the smallest thing, even if was about pixels being slightly out of place. I remember, a few times I would fire-up the Speccy in the middle of the night and shove a couple of pixels around some graphics I had been working on at that time. Crazy.
You did the graphics and some of the level design for Kwik Snax can you recall any of the levels you did?
I can't really recall individual levels as this was more a programmer-led creation, but I can recall the work that went into the intro sequence (the Dizzy Band). Lyndon Sharp (programmer) wanted to do so much more with it. Lyndon wanted the characters moshing, diving off the stage, an audience going wild and eventually the characters crowd surfing! Of course we were constrained by memory but the ideas we had were brill and it would have been awesome seeing Dizzy being held aloft by the baying crowds!
Did you work with the Oliver Twins if so do you have any interesting stories with your time working with them?
I never worked 'closely' with them but they were always around, doing stuff and I did speak to them, lovely chaps. Most of the talking was done after work, usually at one of the parties Richard Darling used to hold at his flat in Leamington Spa. Many chats with other developers usually happened at these get-togethers. Great times.
Are you surprised that Dizzy and Retro is so popular after all these years?
No, I'm not surprised about the popularity of either. Dizzy is a reflection of simpler times, simplicity of the earlier games and the simplicity of the character design. For many people playing these games, at the time, this would be their first steps into an interactive storyboard. Imagination is encouraged here, this in turn creates memories, many of these would have been magical and memorable. 'Retro' is this and much more, the sights and sounds of a particular time, playing older games allows users to venture back to their favourite time and the playing of older games allows these memories to become more 'real'.
Would you ever like to reunite the Oliver Twins for the new ZX Next Dizzy game?
That would be pretty awesome but I doubt they would return, I think they're wrapped up in too many other projects now. It would be a big boost for the ZX Next to have their name associated with a game, though.
Tell us what your current working on?
I left the industry quite a few years ago. As I mentioned earlier, my love for producing graphics faded, I needed a new direction, somewhere that was closer to home. I still wanted to be in the industry in some capacity and my mate informed me of a place that was taking people on. My mate had just got a job in the quality assurance department of a local software developer. I went for an interview there, was told I was 'over qualified' but ultimately managed to get myself a job there. I started working for Psygnosis back in 1992/93
Spent a good few years there, moved from QA to Evaluation through to level builder then eventually design. Worked on the first two Colony Wars games and also the PC game 'Lander'.
I moved to Warthog 1998/9 and helped with some level building on StarLancer. I also joined a few ex-Psygnosis (ex-Colony Wars) guys and lent them a hand in the creation of the game 'Star Trek Invasion' for the PlayStation1.
I left Warthog in 2000 and joined GenePool, with the same ex-Colony Wars guys. I helped in the design and level building of the game 'Wolverines Revenge'. Created initial designs and mission/environment designs for a PS2 Iron Man game.
Unfortunately the Iron Man game never saw the light of day, although we had a very impressive physics engine demo where you controlled Iron Man around a massive pool table, you could carry/manipulate the pool balls by using your repulsor beams and fly around the table and into the pockets. It was wicked.
When Genepool lost the licence for Iron Man it shut it's doors and closed. It came as a complete surprise to me, I was stunned. I landed on my backside but eventually found employment outside of the games industry. A few of the GenePool guys went to work in America for different software companies and have helped create a number of really big name titles that have become super-successful. I have stayed in touch with them and we often reminisce about the Psygnosis/Warthog/Genepool days.
I enjoy some modern games but feel more love for the smaller teams of the past I feel the fun factor has gone in modern games and are more like movie productions; games can be bug ridden now as patches can be made. in the past we didn't have updates and in app purchases. What is your view of our industry now?
I appreciate modern games and their immenseness and grandeur but they seem to lack soul. In getting bigger, faster and even more realistic, they lose a lot of the stuff older gamers seemed to have bucketloads of. Too much is delivered on a plate to todays gamers and everything is spoilered, like watching the trailer for a film you want to go and see, it maybe spoilered to hell but you'll still go and watch it, but you're only watching it for the spectacle.
Here are some questions about retro games:
My favourite computer was my Amiga and 2 of my favourite:-) and my favourite console the Megadrive do you have a favourite?
My Speccy was my favourite computer, followed very closely by the Amiga.
Hmmmm…my favourite retro arcade game is Gorf. I remember playing this endlessly in a big arcade in the Isle of Man while on my hols, late 70's/early 80's. I was completely chuffed when I destroyed the alien-octopus thing in its spaceship for the first time, I felt like a hero!
My favourite retro Speccy game is Fairlight. I remember my mate lending it to me one lunchtime at school. I legged it home and loaded it up to try it straight away. I remember being fascinated by the physics in it, how monsters helmets and other objects fell to the floor. The graphics were really well done and had a 'other worldly' feel about them. Also, it was the only game that allowed you to play as Bobby Ball 😉
Do you still game on the current consoles if so what's your favourite game?
Since I worked for Psygnosis/Sony there could only be one console for me, the PlayStation. I've grew with the console and I have all iterations of it, never really felt the need to get anything else (does that make me a Sony fan-boy?)
GTAV and Red Dead Redemption are really good games but I love the Just Cause series. I really like games that encourage you to try stuff out and to come up with your own way to complete levels/missions by utilising tools and weapons. Games that don't take themselves too seriously and give you a massive sandbox to get lost and experiment in. These are the games I have had most fun with.
Whats the worst game you have ever played?
Ha ha ha, couldn't possibly say! I've played some trite in my time, games that have virtually eaten away at my own life-force as I have attempted to wrestle some fun out of them. I couldn't pinpoint a single game though, sorry.
Finally, what game or feature would you like to see on Retrogamesmaster in the future?
If it's not been done already…Possibly a feature about retro games and how these would have to be re-imagined for todays PCs/consoles. How would a game like Scuba Dive be approached for todays market, get opinions from the developers of the original games.
Bill Harbison (RGM 30/07/16)
Doug Barnett (RGM 27/01/17)

redpajama_set_name: RedPajamaCommonCrawl


- Born in Spain from both parents stateless or if neither of the parent's originating countries gives the child their nationality. This situation requires a civil registry process to be followed where Spanish nationality is declared.
- Born in Spain from parents unknown. When a child's first known location is in Spain, then it's presumed to have been born in Spain.
- Adopted by a Spaniard. If someone is adopted after turning 18, then that person may elect Spanish nationality in the 2 years after the adoption.
- Descendants from Sephardic Jews who where thrown out of Spain in 1492.
Spanish Immigration Lawyers specialized in studying, working and residence visa applications for Spain.
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Words At War Episode 40 "Science At War" Released March 17, 1944.
Words At War, the series that brings you radio versions of the leading war book another adaptation of an important war book, "Science At War". How science has improved the art of making war, and defending against it.


Marrara Christian College is proud to offer a safe, fun, stimulating and nurturing Christian environment for our Preschool children. As part of the Marrara Christian College campus, Preschool students benefit from interaction with other year levels. Preschool operates from Tuesday to Thursday from 8:30am til 2:45pm.
In Marrara Christian College Primary School, the whole child is educated within the context of a Christian World View. Every student is valued as a uniquely created person. Whilst the Primary School is not academically selective in its entrance criteria, standardised test results demonstrate the progressive and rigorous academic development of all students. Opportunities for students to practice their sporting prowess and artistic skills are integrated into the routine of the school. This is a Godly school environment in which your child will safely achieve success.
Middle School at Marrara Christian College is a place where students are nurtured by teachers who care about them and have a commitment to helping families negotiate an interesting time of their lives. Our aim is to make study real, diverse, interesting and meaningful to students thereby establishing a strong academic and personal base for further study.
At Marrara Christian College, our Senior School has a vision to challenge, equip, empower and bring hope to young people accross the Teritory and beyond, through quality education from a Christian perspective, and into positive vocational pathways.
Recognised as a nation leading program, our FACT centre continues to provide a challenging environment for trainees and give hope, jobs and purpose to students and youth who struggle to find their place in the school and in life. Marrara Christian College continues to offer Cert II in Construction and Cert II in Engineering (Fabrication Welding) with trainees going out to industry with real skills and a work history, work ready.
All year levels from Year 3 to 12 are involved in the outdoor education focus at Marrara Christian College with camps of varying descriptions occuring each year. Building both character and team work as well as developing educational outcomes, the camps are recognised as highlights by both students and families. The college also provides many opportunities for sporting involvement and achievement through participation in City Wide School Sport Activities.
• If you are looking for a school your children can enjoy – we are the school for you.
• If you are looking for a school with a strong academic tradition – we are the school for you.
• If you are looking for a school whose staff love working with students from early learning to Senior – we are the school for you.
• If you are looking for a school that cares about who students become as much as how well they perform – we are the school for you.
• If you are looking for a school that is honest about what it believes and the values it teaches – we are the school for you.


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https://journals.humankinetics.com/browse?access=all&page=35&pageSize=10&sort=datedescending&t=PhysEdCoach&t_0=S256&t_2=S279&t_3=PsycBehavSportEx
Sources of Self-Efficacy During Marathon Training: A Qualitative, Longitudinal Investigation
Ashley Samson
There is evidence that an individual with a higher level of self-efficacy will persist longer and be more robust in their efforts than an individual with a lower level of self-efficacy (Feltz et al., 2008). As such, it follows that a high level of self-efficacy would be essential in a strenuous activity such as distance running. Therefore, the purpose of this study was to explore the evolution of efficacy beliefs over the course of a training program by following 26 participants training for a marathon. Participants completed individual interviews at three different time points throughout the training and that were analyzed for content relevant to the formation of efficacy beliefs for the marathon. Overall, the findings indicated that physiological/emotional states were the most frequently mentioned source of information throughout the duration of the experience. Further, the influence of past performance experiences gradually increased throughout the duration of the program.
In The Sport Psychologist Volume 28 (2014): Issue 2 (Jun 2014)
Toward an Understanding of Optimal Development Environments Within Elite English Soccer Academies
Andrew Mills, Joanne Butt, Ian Maynard, and Chris Harwood
This study examined the factors perceived by successful coaches to underpin optimal development environments within elite English soccer academies. A semistructured interview guide was developed to interview 10 expert coaches about the environments they create for players at a key stage in their development. The interviews were transcribed verbatim and inductively content analyzed. The results identified a wide range of factors resulting in a conceptual framework that explained how these factors interact to underpin an optimal environment. Subcomponents of this framework included organizational core (e.g., advocate a player-driven ideology), adaptability (e.g., embrace novel ideas & approaches), player welfare (e.g., understand players' world-view), key stakeholder relationships (e.g., build trust with parents), involvement (e.g., encourage players' ideas/feedback), and achievement oriented (e.g., establish an explicit pathway to senior level). Collectively, the findings highlight the importance of establishing strong, dynamic, organizational cultures at elite youth soccer academies. Ways that academies might be helped to establish such environments are discussed.
Volume 28 (2014): Issue 1 (Mar 2014)
A Case Study of Excellence in Elite Sport: Motivational Climate in a World Champion Team
Ken Hodge, Graham Henry, and Wayne Smith
This case study focused on the New Zealand All Blacks rugby team during the period from 2004 to 2011, when Graham Henry (head coach) and Wayne Smith (assistant coach) coached and managed the team. More specifically, this case study examined the motivational climate created by this coaching group that culminated in winning the Rugby World Cup in 2011. In-depth interviews were completed with Henry and Smith in March 2012. A collaborative thematic content analysis revealed eight themes, regarding motivational issues and the motivational climate for the 2004–2011 All Blacks team: (i) critical turning point, (ii) flexible and evolving, (iii) dual-management model, (iv) "Better People Make Better All Blacks," (v) responsibility, (vi) leadership, (vii) expectation of excellence, and (viii) team cohesion. These findings are discussed in light of autonomy-supportive coaching, emotionally intelligent coaching, and transformational leadership. Finally, practical recommendations are offered for coaches of elite sports teams.
Exploring Experiences of Running an Ultramarathon
Nicholas L. Holt, Homan Lee, Youngoh Kim, and Kyra Klein
The overall purpose of this study was to examine individuals' experiences of running an ultramarathon. Following pilot work data were collected with six people who entered the 2012 Canadian Death Race. Participants were interviewed before the race, took photographs and made video recordings during the race, wrote a summary of their experience, and attended a focus group after the race. The research team also interviewed participants during the race. Before the race participants had mixed emotions. During the race they experienced numerous stressors (i.e., cramping and injuries, gastrointestinal problems, and thoughts about quitting). They used coping strategies such as making small goals, engaging in a mental/physical battle, monitoring pace, nutrition, and hydration, and social support. After the race, nonfinishers experienced dejection or acceptance whereas finishers commented on the race as a major life experience. These findings provide some insights into factors involved in attempting to complete ultramarathons and offer some implications for applied sport psychology.
Fostering Life Skills Development in High School and Community Sport: A Comparative Analysis of the Coach's Role
Christiane Trottier and Sophie Robitaille
The aim of this study was to gain a deeper understanding of coaches' perceptions of their role in the development of life skills in adolescent athletes in two different sport contexts. Semistructured interviews were held with 24 coaches: 12 coaching high school basketball and 12 coaching community swimming. All coaches followed a holistic, athlete-centered approach. Coaches described the life skills they taught, their motivations, and the strategies they used to foster life skills development in practice. Although some differences between the two contexts were identified, the overall results indicate that all coaches fostered the development of life skills through various teaching and transfer strategies, and that coaches had two main motivations: athletes' needs and their own values. The main results are discussed in light of the literature on life skills in sport and positive youth development, and in terms of methodological considerations. The study concludes with some practical recommendations for coaches.
Imagery Intervention to Increase Flow State and Performance in Competition
Stefan Koehn, Tony Morris, and Anthony P. Watt
The purpose of this study was to examine the effectiveness of an imagery intervention for enhancing the experience of flow state and performance in junior athletes. On the basis of previous results, a tailored imagery script was developed to target critical flow dimensions, namely challenge-skills balance, clear goals, concentration on the task, and sense of control. It was hypothesized that the use of cognitive and motivational imagery would increase specific flow dimensions, which, in turn, would enhance flow state and competition performance. Participants in a single-case, multiple baseline A-B design study were four nationally ranked athletes. Following a 6-week baseline phase monitoring flow state and performance and a 6-week intervention phase using relaxation in conjunction with imagery techniques, three participants showed a sustained increase in flow experiences, and all four participants improved their service performance, groundstroke performance, and ranking-list position.
Preparing Footballers for the Next Step: An Intervention Program From an Ecological Perspective
Carsten H. Larsen, Dorothee Alfermann, Kristoffer Henriksen, and Mette K. Christensen
The purpose of this article is to present practitioners and applied researchers with specific details of an ecological-inspired program and intervention in a professional football (soccer) club in Denmark. Based on an ecological agenda, the aim is to reinforce the culture of psychosocial development in the daily practice of a professional football academy, provide the skills required to succeed at the professional level and create stronger relations between the youth and professional departments. The authors suggest six principles as fundamental governing principles to inform an intervention inspired by the holistic ecological perspective. Descriptions of the intervention program and findings are presented in four interconnected steps. Insights are provided into delivery of workshops, the supervision of the coach, on-pitch training, evaluation of the program, and integrating sport psychology as a part of the culture within the club.
Psyched for Sport (Volume 1)
Eric Bean
Psychosocial Predictors of Well-Being in Collegiate Dancers
Sarah Draugelis, Jeffrey Martin, and Alex Garn
Although many researchers have examined ill-being (e.g., injury and illness) in dancers, few researchers have examined well-being. In the current study, dancer's perceptions of the dance motivational climate, dance performance anxiety, dance self-concept, and their relationships to dance well-being were examined. A total of 182 university dance students from five universities completed surveys and a series of multiregression analyses were undertaken to predict well-being. Both dance self-concept and perceptions of a task climate were moderately related to well-being and contributed significantly to elements of well-being: vigor, enthusiasm, confidence, and dedication. An ego climate was unrelated to any of the four dimensions of well-being. Substantial variance was predicted in the various elements of engagement, ranging from 15% to 55%. In particular, two significant interactions indicated that a task climate may have protective effects against anxiety in terms of reducing the detrimental influence that anxiety may have on two forms of well-being: confidence and dedication.


text:
Brachystelma togoense är en oleanderväxtart som beskrevs av Rudolf Schlechter. Brachystelma togoense ingår i släktet Brachystelma och familjen oleanderväxter. Inga underarter finns listade i Catalogue of Life.

Källor

Oleanderväxter
togoense

redpajama_set_name: RedPajamaWikipedia


Today you'll start riding northward along the beautiful coastline of the Adriatic Sea. Crossing the marinas of Tricase Porto and Castro Marina, you'll finally get to one of the most amazing city of Salento: OTRANTO. If you want, you can have a delicious seafood dinner and take a walk throughout the historic centre and maybe buy some souvenirs from the local little shops. Overnight stay in Otranto.


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Letters are the great fixative of experience. Time erodes feeling. Time creates indifference. Letters prove to us that we once cared. They are the fossils of feeling. This is why biographers prize them so: they are biography's only conduit to unmediated experience. Everything else the biographer touches is stale, hashed over, told and retold, dubious, unauthentic, suspect. Only when he reads a subject's letters does the biographer feel he has come fully into his presence, and only when he quotes from the letters does he share with his readers the sense of life retrieved. And he shares something else: the feeling of transgression that comes from reading letters not meant for one's eyes.
This is the way things are, the place says. This is unmediated actuality, in all its multiplicity, randomness, inconsistency, redundancy, authenticity. Before the magisterial mess…the orderly houses that most of us live in seem meagre and lifeless—as, in the same way, the narratives called biographies pale and shrink in the face of the disorderly actuality that is a life…Each person who sits down to write faces not a blank page but his own vastly overfilled mind. The problem is to clear out most of what is in it, to fill huge plastic garbage bags with a confused jumble of things that have accreted there over the days, months, years of being alive and taking things in through the eyes and ears and heart. The goal is to make a space where a few ideas and images and feelings may be so arranged that the reader will want to linger a while among them, rather than to flee…But this task of housecleaning (of narrating) is not merely arduous; it is dangerous. There is the danger of throwing the wrong things out and keeping the wrong things in; there is the danger of throwing too much out and being left with too bare a house; there is the danger of throwing everything out.
Malcolm concludes: "Once one starts throwing out, it may become hard to stop. It may be better not to start. It may be better to hang onto everything…lest one be left with nothing." Obviously, she hasn't listened to her own advice, and we're all the better for it. But that doesn't mean that she—or the reader—has to be fine with the outcome.


The Ambassadors are a prestigious group of Chamber members who want to volunteer their time to be a more active member within the Chamber as well as within the Ruston-Lincoln business community.
Being an Ambassador offers you a unique opportunity. Ambassadors work with the Ruston-Lincoln Chamber of Commerce staff and Board of Directors to increase membership, improve member retention, strengthen awareness of Chamber benefits, volunteer their time to assist with various Chamber events, as well as being a part of the decision making of our business community.
Ron Veitch is the President of Anti Pest & Veitch and has served in the pest control industry since he was 5 years old when his grandfather, S.D. Veitch, founder of Anti Pest & Veitch would take him along crawling under houses on termite inspections. In his industry Ronnie served as secretary, vice president and president of the Northwest Louisiana Pest Management Association. He was also a State Regional Director serving on the Board of Directors of the Louisiana Pest Management Association.
In his community he is in the Lions Club where he was voted Lion of the Year in 1995. He has also served on the Board of Directors and as president of that organization. He has served as a director on the Board of Directors of the Minden South Webster Chamber of Commerce and was recognized for outstanding service as an Ambassador in that organization. He also served on the Board of Directors of Webster Habitat of Humanity and the Fuller Center for Housing. He is a volunteer speaker at YCP the Youth Challenge Program located at Camp Minden housing the National Guard. He is also active in the Christian Motorcyclist Association (CMA).
In his church he is an ordained deacon, he has served on the Missions Committee and is active in prison ministries conducted at Bayou Dorcheat and Wade Correctional Center. He is also a member of the Gideons.
He loves the outdoors and all things water and woods, fishing, scuba diving, boating, deer hunting and just enjoys being in God's creation. He has two adult children, Jason & Jennifer, and five grandchildren ranging in ages from 18 months to 13 years old.
Ron joined the Ruston-Lincoln Chamber of Commerce in 2017 and immediately became active in the community. Serving as an Ambassador gives him the opportunity to be present at new business starts and ground breakings and to meet those responsible for such a thriving economy. Even though he has to drive 30 minutes to be here, he rarely misses a Chamber event.
Interested in becoming an Ambassador? Find out about the program in the Ambassador Handbook.


Dr. Paul's Palm Springs Recovery is in an idyllic location. The environment there has been planned and designed to harbor peace, comfort and serenity. Known for its impeccable beauty, it is a perfect venue for healing, and to rebuild the pieces of our selves, be renewed and replenished.
Blue Lagoon caters to older adults that seek help in a substance abuse treatment program. At Blue Lagoon, they take into consideration many of the factors that specifically affect older adults, their interactions with drugs and alcohol as well as their course of treatment.


Sandy Anderson is the Senior Partner of DGA Forestry and has over 40 years' experience in forest management and consultancy in both the private and public sectors. He graduated from the University of Edinburgh in 1975 with a BSc Ecological Science (Honours Forestry) and gained an MBA with Distinction from Glasgow University in 1986. He has been a member of the Institute of Chartered Foresters since 1972.
From 1975 to 1987 he worked with the Forestry Commission gaining a wide range of experience in large scale afforestation projects, management of forest nurseries and management of district harvesting programmes within Dumfries and Galloway and South Ayrshire. Sandy joined the firm in 1987, became a partner in 1988 and senior partner in 2002.
In addition to Sandy's extensive experience in forestry management, he has been involved in over 60 windfarm projects within forestry plantations in a variety of roles, ranging from advice to Landowners on the negotiation of windfarm option agreements and leases; contributions to numerous Environmental Statements; management of forestry operations during the construction phase; preparation, contribution and review of Habitat Management Plans; specialist advice on specific topics; and acted as an expert witness at Public Inquiries.
James Anderson is a partner with the firm and originally qualified as an architect. He worked in London for many years delivering complex major social housing, high end residential, master planning and urban renewal projects. The project management and designs skills utilised in such projects are transferable to the forestry and windfarm projects carried out by DGA Forestry. James is experienced in ArcGIS, MapMaker GIS, AutoCAD and a wide range of other design programmes. He has now been involved in over 30 windfarm and overhead line projects within forestry plantations, including GIS mapping; forest design planning; and contributions to numerous Environmental Statements. Having worked with DGA as a self-employed consultant over a number of years James joined DGA full time in 2012 to assist with the expanding project workload. James is the lead on DGA Forestry's GIS mapping and data analysis and is also responsible for the operation of DGA Forestry's UAV platform.
Ewan Batchelor is a senior forest manager and joined DGA in October 2017. Ewan has spent several years working across Scotland within the forestry industry, most recently in the north east and will be working at DGA as a Forest Manager. Ewan will be responsible for a management portfolio that covers a broad swathe of Scotland and will be involved in all aspects of the forestry business, including report writing, plan preparation, field work and contract supervision. He is a graduate of the University of the Highlands and Islands with a BSc in Sustainable Forest Management.
Sam is a forest manager and joined DGA in July 2018. After graduating from Bangor University in 2016 with a BSc (Hons) in Forestry, Sam joined the Forestry Commission where he was latterly employed as a beat manager in Kielder forest. Sam has gained a broad range of experience working with the FC in all aspects of modern forestry in particular managing and supervising of forestry operations. As a Forest Manager at DGA, Sam will be responsible for a wide ranging management portfolio covering properties across the UK where he will be not only administering contracts, but carrying out the other roles of a forest manager such as preparation of reports, long term plans and grant applications.
Kendric is a forest manager who joined DGA in July 2017. He graduated from Cumbria University in 2016 with a BSc (Hons) in Forestry & Woodland Conservation. Kendric has gained a broad range of experience from his previous employment in Cumbria as a GIS technician and woodland surveyor and also from his time volunteering with the National Trust as a woodland ranger. Kendric manages woodlands across Scotland from south west Scotland to Argyll. He has also experience of supervising harvesting operations for various renewable energy projects across the country.
Dorothy MacLachlan joined DGA in 2015 to manage the day to day running of the office. With over 30 years' experience in the forestry sector, Dorothy deals with all aspects of the office management from organising stalking leases, maintaining records, to the coordination and implementation of office procedures.
Anne Anderson formally trained as a teacher. After a break to have their family Anne studied textiles and embroidery at Cardonald College in Glasgow and Newton Rigg College in Cumbria. She joined DGA in 2002 to assist with the office management, eventually becoming office manager and then a partner in the business in 2012.
Anne has been responsible for managing the office administration and company finances. Anne has now taken a step back from the business to pursue other interests, but is still responsible for both clients' and the company's accounts.


General Mitchell International Airport 2 miles. Midwest Airlines Center, Potawatomi Bingo Casino, Breweries, the Bradley Center, Summerfest, Marquette Univ, County Stadium, State Fair Park all within 10 miles. Our hotel is newly remodeled.


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Home / Gouvernment / Pedro Sánchez expected in Morocco in the coming weeks
Pedro Sánchez expected in Morocco in the coming weeks
August 29, 2021	Gouvernment Leave a comment 2,265 Views
Morocco and China signed a MoU to implement the Belt and Road Initiative
Staffan De Mistura expected in Morocco next week
King Mohammed VI has given his high instructions to prepare for the official visit to Rabat in the coming weeks of President Pedro Sánchez. After having clearly expressed his desire to resume relations with Spain, on the occasion of the Feast of the Throne, the monarch thus joins action with his word.
"With all sincerity and confidence, we aspire to continue working with the Spanish government and its President, His Excellency Mr. D. Pedro Sánchez, in order to open a new era in relations between the two countries, on the basis of trust, transparency, mutual respect and respect for commitments", declared Mohammed VI on August 20 in his speech on the occasion of the Feast of the Throne.
The two countries went through four months of crisis, which started with Spain's reception of the Polisario Front leader, Brahim Ghali. During the period, Morocco cut off all contact with Spain, and recalled to Rabat for consultations, its ambassador in Madrid, Karima Benyaich. To calm Morocco, President Sánchez thanked his former foreign minister, Arancha González Laya. The new Minister José Manuel Albares, in all discretion, worked to reestablish dialogue and resume relations on new bases.
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BioVentures and UAMS Commit to...
BioVentures and UAMS Commit to COVID-19 Technology Licensing Principles, Maximizing Access to UAMS Innovations
April 22, 2020 | LITTLE ROCK — BioVentures and the University of Arkansas for Medical Sciences (UAMS) have committed to a set of technology licensing principles that will allow for broad and equitable access to UAMS discoveries during the Global COVID-19 pandemic.
The COVID-19 Technology Framework was developed and established through a cooperative effort by Stanford University, Harvard University and the Massachusetts Institute of Technology. This framework provides a model by which critically important technologies that may help prevent, diagnose or treat COVID-19 may be deployed for the greatest public benefit in the shortest period of time.
"Consistent with UAMS's mission to improve the health, health care and well-being of Arkansans and of others in the region, nation and world, BioVentures is committed to translating and accelerating UAMS innovations into health improvements," said Nancy Gray, Ph.D., BioVentures president. "The seriousness and urgency of the COVID-19 public health crisis means that today we cannot wait for tomorrow. We need to help now in every way we can."
Gray said that with the best interests of the public in mind, BioVentures is glad to join in this cooperative effort with Stanford, Harvard and MIT and to commit to the guidelines stated in the framework below.
COVID-19 Technology Access Framework
We strongly believe that while intellectual property rights can often serve to incentivize the creation of new products, such rights should not become a barrier to addressing widespread, urgent and essential health-related needs.
To address the global COVID-19 pandemic, we are implementing technology transfer strategies to allow for and incentivize rapid utilization of our available technologies that may be useful for preventing, diagnosing and treating COVID-19 infection during the pandemic.
To achieve our goal, we commit to the following guidelines:
We are committed to implementing COVID-19 patenting and licensing strategies that are consistent with our goal of facilitating rapid global access. For most types of technologies, this includes the use of rapidly executable non-exclusive royalty-free licenses to intellectual property rights that we have the right to license, for the purpose of making and distributing products to prevent, diagnose and treat COVID-19 infection during the pandemic and for a short period thereafter. In return for these royalty-free licenses, we are asking the licensees for a commitment to distribute the resulting products as widely as possible and at a low cost that allows broad accessibility during the term of the license.
We are committed to making vigorous efforts to achieve alignment among all stakeholders in our intellectual property, including research sponsors, to facilitate broad and rapid access to technologies that have been requested to address the COVID-19 pandemic.
We are committed to making any technology transfer transactions related to addressing the COVID-19 pandemic our first priority, and to minimize any associated administrative burdens.
BioVentures is a technology commercialization organization and startup incubator focused on promoting a biomedical technology industry for Arkansas and translating research into products that benefit human health. BioVentures links the health care research minds to global markets to advance Arkansas' scientific and economic development.


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Intel's new laptop processors aim to topple Apple's mighty M1 chips
It's the battle of the hybrid architectures
Credit: Intel
Written by Joanna Nelius
Intel announced the latest additions to its mobile processor family during CES 2022—and it gave us a little sneak peek as to when we can expect to see its first discrete graphics card in decades. The company claims big performance boosts over its competitors, AMD and Apple, due to its hybrid architecture, which mixes different cores dedicated to either intensive or light tasks. We also got some new announcements relating to Intel's 12th-gen desktop processors. Read on for what we can expect from Intel in 2022.
Mobile processing
Building on its newest 12th-generation desktop processors, Intel is bringing its hybrid chip architecture to laptops in 2022. While we found Intel's 12th-gen chips a hassle to add to desktops, we are excited to see how Intel's latest processors fair in a mobile form factor, as their desktop counterparts offer incredible productivity performance for habitual emailers and content creators alike.
As in previous years, Intel will have three different mobile processor categories: the H-series for enthusiast gamers and anyone who needs a lot of power; the P-series for thin and light laptops that also serve up some serious performance; and the U-series for thin and light work machines. But at CES 2022 Intel focused only on the H-series.
All 12th-gen H-series mobile chips have up to 14 cores (six performance cores and eight efficiency cores), up to 5GHz clock speeds, memory support for DDR5-4800, DDR4-3200, LPDDR5-5200, and LPDDR4x-4267 RAM, PCIe 4.0, as well as Intel Wi-Fi 6E and Thunderbolt 4 connectivity. In total, there will be eight different SKUs covering Core i9, Core i7, and Core i5.
Intel's 12th-generation processors are coming to laptops in the first half of 2022.
Intel claims up to a 28% boost in gaming performance over its 11th-generation mobile processors (depending on the game) at 1080p with the graphics preset on High. Intel also claims an even bigger boost over one of AMD's fastest laptop processors, the Ryzen 5900HX, although Intel will have AMD's upcoming 6000-series processors to contend with.
The company also boasts up to a 33% decrease in 3D rendering time in Blender compared to its last generation of chips—and Intel also claims it can render images in the same program faster than Apple's M1 Pro and Max chips.
Evo-loution
All of Intel's 12th-gen H-series mobile processors will also be a part of Intel's Evo platform, which features long battery life, instant wake, and fast charging. But now, in addition to being outfitted with Intel's Iris Xe integrated graphics, users will have a choice to opt for an Intel Arc discrete graphics card instead—on certain laptop models, of course.
Intel Arc is the brand name for the company's upcoming high-end, consumer graphics cards—and the first discrete GPU Intel has made in decades. To compete with the likes of Nvidia and AMD, Arc GPUs will be ray-tracing compatible and incorporate AI-driven upscaling technology to boost in-game frame rates. Also like Nvidia and AMD, Intel has its own name for its resolution upscaling technology: Xe Super Sampling (XeSS); The PC version of Death Stranding will be one of the first games to support XeSS.
Additionally, Intel says users can speed up their video encoding by 1.4X thanks to its Deep Link Hyper Encode technology, which splits the work between Intel's integrated and discrete graphics.
Expect these new Evo-certified laptops to start arriving in the first half of 2022, with laptops featuring Arc graphics available sometime in Q1 2022. Look out for models from Acer, Asus, Dell, Gigabyte, HP, Lenovo, Samsung, MSI, and more.
Desktop processing
Intel's upcoming Core i9-12900KS will release by the end of March 2022.
As a surprise treat, Intel announced it will be adding a Core i9-12900KS CPU to its existing 12th-gen desktop line-up, which the company says can reach clock speeds of up to a whopping 5.5GHz. That's a 300MHz increase over the company's current flagship CPU, the Core i9-12900K! The Core i9-12900KS is set to ship by the end of Q1 2022, so sometime around the end of March 2022.
Intel didn't say much else about the Core i9-12900KS, but looking at that 'KS' suffix, we assume this upcoming desktop chip will be able to hit max clock speeds on all cores right out of the box; Intel has done this in the past with its previous flagship processors.
Intel has also added more 12th-gen SKUs to its line-up, 22 in total, across Core i9, Core i7, and Core i5 models.
To go with all those new chips, Intel also announced new motherboard chipsets are coming to market to support more gamers with different budgets and needs. Joining the enthusiast-level Z690 motherboard chipsets are the H670, B660, and H610. Unlike the Z690, these new chipsets will not support CPU overclocking but will support RAM overclocking (with the exception of the H610).
As always, we're looking forward to putting Intel's 12th-gen mobile chips to the test in our labs. For more CES 2022 news, catch up here.


Buying with Emotion | DRL Realty, Inc.
Ideally, most buyers should look at five to seven properties before making an offer. If you happen to fall in love with the first home you see, make sure you inspect the property thoroughly and try to find the flaws. Sooner or later, you'll learn that no home is perfect. Make sure you find a home based on what you need. Otherwise, you'll realize you overpaid for a home that doesn't meet your needs and that will be difficult to sell for a reasonable price down the line.
The current market has buyers thinking that there's always a better deal elsewhere. Many believe that they can get more for less. Unfortunately the market is always changing. For instance this year there's been a shortage of inventory. This is driving up home prices, making deals virtually impossible to find. If you find a home that meets your needs, have your agent do a comparable market analysis. Use this data to make a competitive offer. Do not constantly look for a better deal unless time is not a factor.
Buying a home means making a lot of tough decisions. From budget to location to size, you'll need to know exactly what you want. If you're indecisive about what you want, you'll lose many homes before you understand your needs.
Short-sale and foreclosure to buyers are buzz words for deal. This is not always true. Many buyers pay above market value for these homes. Have your agent do the comparable market analysis before making an offer.
An offer for a home that you are serious about purchasing should be competitive and realistic. Lowballing a seller may insult them and lengthen the process of negotiation.


Transport theory is the main tool to extract physical information from heavy-ion collisions (HIC), like the nuclear equation-of-state. In this workshop we review the challenges and demands on transport theory in view of new facilities and experiments, and of new astrophysical observations. We focus on energies and corresponding densities, where a hadronic representation is appropriate. At present, transport dynamics is treated essentially as a semi-classical 1-body description. Necessary extensions are the specification of fluctuations, the introduction of dynamical correlations and clustering, including short-range correlations, and the treatment of off-shell effects ofparticle with widths. The workshop will discuss these questions and develop ways to replace the empirical treatments often used today. One vehicle for this are code comparisons under controlled conditions for heavy-ion-collisions and box calculations to study the treatment of these effects in simulations and to estimate the systematical error of transport descriptions.


Historic Register. Brick and terra cotta: Water repellent and graffiti protection.
Brick: water repellent and graffiti protection. Still works. Applied in 1995.
Precast concrete panels water repellent protection.
Block & brick: water repellent and graffiti protection. Interior block graffiti protection.
Historic Register. Sandstone: Water repellent and graffiti protection.
Brick: water repellent and graffiti protection.
Block and poured-in-place concrete: water repellent and graffiti protection interior and exterior.
Brick: water repellent and graffiti protection. Planter boxes also protected.