The present invention relates in general to improved multiprocessor data processing systems, and in particular to an improved method and system for maintaining memory coherence in a multiprocessor data processing system. Still more particularly, the present invention relates to an improved method and system for maintaining translation lookaside buffer (TLB) coherency in a multiprocessor data processing system without requiring the utilization of interprocessor interrupts.
Designers of modern state-of-the-art data processing systems are continually attempting to enhance the performance aspects of such systems. One technique for enhancing data processing system efficiency is the achievement of short cycle times and a low Cycle's-Per-Instruction (CPI) ratio. An excellent example of the application of these techniques to an enhanced data processing system is the International Business Machines Corporation RISC System/6000 (RS/6000) computer. The RS/6000 system is designed to perform well in numerically intensive engineering and scientific applications as well as in multi-user, commercial environments. The RS/6000 processor employs a multiscalar implementation, which means that multiple instructions are issued and executed simultaneously.
The simultaneous issuance and execution of multiple instructions requires independent functional units that can execute concurrently with a high instruction bandwidth. The RS/6000 system achieves this by utilizing separate branch, fixed point and floating point processing units which are pipelined in nature. In such systems a significant pipeline delay penalty may result from the execution of conditional branch instructions. Conditional branch instructions are instructions which dictate the e taking of a specified conditional branch within a application in response to a selected outcome of the processing of one or more other instructions. Thus, by the time a conditional branch instruction propagates through a pipeline queue to an execution position within the queue, it will have been necessary to load instructions into the queue behind the conditional branch instruction prior to resolving the conditional branch in order to avoid run-time delays.
Another source of delays within multiscalar processor systems is the fact that such systems typically execute multiple tasks simultaneously. Each of these multiple tasks typically has a effective or virtual address space which is utilized for execution of that task. Locations within such a effective or virtual address space include addresses which "map" to a real address within system memory. It is not uncommon for a single space within real memory to map to multiple effective or virtual memory addresses within a multiscalar processor system. The utilization of effective or virtual addresses by each of the multiple tasks creates additional delays within a multiscalar processor system due to the necessity of translating these addresses into real addresses within system memory, so that the appropriate instruction or data may be retrieved from memory and placed within an instruction queue for dispatching to one of the multiple independent functional units which make up the multiscalar processor system.
One technique whereby effective or virtual memory addresses within a multiscalar processor system may be rapidly translated to real memory addresses within system memory is the utilization of a so-called "translation lookaside buffer" (TLB). A translation lookaside buffer (TLB) is a buffer which contains translation relationships between effective or virtual memory addresses and real memory addresses which have been generated utilizing a translation algorithm. While the utilization of translation lookaside buffer (TLB) devices provides a reasonably efficient method for translating addresses, the utilization of such buffers in tightly coupled symmetric multiprocessor systems causes a problem in coherency. In data processing systems in which multiple processors may read from and write to a common system real memory care must be taken to ensure that the memory system operates in a coherent manner. That is, the memory system is not permitted to become incoherent as a result of the operations of multiple processors. Each processor within such a multiprocessor data processing system typically includes a translation lookaside buffer (TLB) for address translation and the shared aspect of memory within such systems requires that changes to a single translation lookaside buffer (TLB) within one processor in a multiprocessor system be carefully and consistently mapped into each translation lookaside buffer (TLB) within each processor within the multiprocessor computer system in order to maintain coherency.
COMPUTER vol.23, no.6, June 1990, LONG Beach US pages 26 -36 TELLER 'Translation-lookaside buffer consistency' describes nine solutions to a cache consistency problem for shared memory microprocessors with multiple translation-lookaside buffers. Three of these require special purpose hardware cache consistency. Four of the software solutions rely on interprocessor interrupts which are not required by the invention. Of the remaining solutions the memory based TLB invalidate method is for TLBs which are separate from the processor and the validate method is not an invalidate method.
US patent publication 4733348 discloses a virtual memory multiprocessor with parallel purge operation implemented in hardware. The end of the purge operation of each processor can be set by a corresponding flip-flop. By checking the statuses of the flip flop the end of the purge operations of all the processors can be detected. The purge signal is sent individually to each processor rather than as a bus structure to all the processors at once. Moreover this prior art does not invalidate a particular TLB entry, rather the purge operation initiates an equalization of the contents of the TLB.
IBM Technical Disclosure Bulletin vol.33, no. 10A, March 1991, New York US pages 371 -374 'Early release of a processor following address translation prior to page checking' discloses a method for saving processor time between virtual address translation and checking a page access key. This disclosure is not concerned with cache coherency between a number of buffers but focuses on the process of a single Translation look-aside buffer.
The maintenance of translation lookaside buffer (TLB) coherency in prior art multiprocessor systems is typically accomplished utilizing interprocessor interrupts and software synchronization for all translations lookaside buffer (TLB) modifications. These approaches can be utilized to ensure coherency throughout the multiprocessor system; however, the necessity of utilizing interrupts and software synchronization results in a substantial performance degradation within a multiprocessor computer system.
It should therefore be apparent that a need exists for a method and system which may be utilized to maintain translation lookaside buffer coherency in a multiprocessor data processing system without the requirement for utilizing interprocessor interrupts.
executing the associated translation lookaside buffer invalidate instruction at all remaining processors among the plurality of processors only in response to an acceptance of the translation lookaside buffer invalidate bus structure at all remaining processors among the plurality of processors.
means for executing the associated translation lookaside buffer invalidate instruction at all remaining processors among the plurality of processors only in response to an acceptance of the translation lookaside buffer invalidate bus structure at all remaining processors among the plurality of processors.
Translation lookaside buffers (TLB) are often utilized in the data processing system to efficiently translate an effective or virtual address to a real address within system memory. In systems which include multiple processors which may all access system memory, each processor may include a translation lookaside buffer (TLB) for translating effective addresses to real addresses and coherency between all translation lookaside buffers (TLB) must therefore be maintained. The method and system disclosed herein may be utilized to broadcast a unique bus structure in response to an execution of a translation lookaside buffer invalidate (TLBI) instruction by an processor within a multiprocessor system. The bus structure is accepted by other processors along the bus only in response to an absence of a pending translation lookaside buffer invalidate (TLBI) instruction within each processor. Thus, a broadcast translation lookaside buffer invalidate (TLBI) instruction may only be executed by the other processors within a multiprocessor system if it has been accepted by all processors within the system. After initiating execution of a translation lookaside buffer invalidate (TLBI) instruction at all processors within the system, the execution of pending instructions is temporarily terminated until after the translation lookaside buffer invalidate (TLBI) instruction has been executed. Thereafter, the execution of instructions is suspended until all read and write operations within the memory queue have achieved coherency. Next, all suspended and/or prefetched instructions are refetched utilizing the modified translation lookaside buffer (TLB) to ensure that the address utilized is still valid.
The present invention thus provides an improved method and system for maintaining memory coherence in a multiprocessor data processing system. In particular of the present invention thus provides an improved method and system for maintaining translation lookaside buffer (TLB) coherency in a multiprocessor data processing system without requiring the utilization of interprocessor interrupts.
Figure 6 is a high level logic flowchart illustrating the synchronization of multiple translation lookaside buffer invalidate (TLBI) instructions within the multiprocessor data processing system of Figure 1 in accordance with the method and system of the present invention.
With reference now to the figures and in particular with reference to Figure 1, there is depicted a high level block diagram illustrating a multiprocessor data processing system 6 which may be utilized to implement the method and system of the present invention. As illustrated, multiprocessor data processing system 6 may be constructed utilizing multiscalar processors 10 which are each coupled to system memory 18 utilizing bus 8. In a tightly-coupled symmetric multiprocessor system, such as multiprocessor data processing system 6, each processor 10 within multiprocessor data processing system 6 may be utilized to read from and write to memory 18. Thus, systems and interlocks must be utilized to ensure that the data and instructions within memory 18 remain coherent.
As illustrated within Figure 1, and as will be explained in greater detail herein, each processor 10 within multiprocessor data processing system 6 includes a translation lookaside buffer (TLB) 40 which may be utilized to efficiently translate effective or virtual addresses for instructions or data into real addresses within system memory 18. In view of the fact that a translation lookaside buffer (TLB) constitutes a memory space, it is important to maintain coherency among each translation lookaside buffer (TLB) 40 within multiprocessor data processing system 6 in order to assure accurate operation thereof.
Referring now to Figure 2, there is depicted a high level block diagram of a multiscalar processor 10 which may be utilized to provide multiprocessor data processing system 6 of Figure 1. As illustrated, multiscalar processor 10 preferably includes a memory queue 36 which may be utilized to store data, instructions and the like which is read from or written to system memory 18 (see Figure 1) by multiscalar processor 10. Data or instructions stored within memory queue 36 are preferably accessed utilizing cache/memory interface 20 in a method well known to those having skill in the art. The sizing and utilization of cache memory systems is a well known subspeciality within the data processing art and not addressed within the present application. However, those skilled in the art will appreciate that by utilizing modern associated cache techniques a large percentage of memory accesses may be achieved utilizing data temporarily stored within cache/memory interface 20.
Instructions from cache/memory interface 20 are typically loaded into instruction queue 22 which preferably includes a plurality of queue positions. In a typical embodiment of a multiscalar computer system the instruction queue may include eight queue positions and thus, in a given cycle, between zero and eight instructions may be loaded into instruction queue 22, depending upon how many valid instructions are passed by cache/memory interface 20 and how much space is available within instruction queue 22.
As is typical in such multiscalar processor systems, instruction queue 22 is utilized to dispatch instructions to multiple execution units. As depicted within Figure 2, multiscalar processor 10 includes a floating point processor unit 24, a fixed point processor unit 26, and a branch processor unit 28. Thus, instruction queue 22 may dispatch between zero and three instructions during a single cycle, one to each execution unit.
In addition to sequential instructions dispatched from instruction queue 22, so-called "conditional branch instructions " may be loaded into instruction queue 22 for execution by the branch processor. A conditional branch instruction is an instruction which specifies an associated conditional branch to be taken within the application in response to a selected outcome of processing one or more sequential instructions. In an effort to minimize run-time delay in a pipelined processor system, such as multiscalar processor 10, the presence of a conditional branch instruction within the instruction queue is detected and an outcome of the conditional branch is predicted. As should be apparent to those having skill in the art when a conditional branch is predicted as "not taken" the sequential instructions within the instruction queue simply continue along a current path and no instructions are altered. However, if the prediction as to the occurrence of the branch is incorrect, the instruction queue must be purged of sequential instruction, which follow the conditional branch instruction in program order and target instructions must be fetched. Alternately, if the conditional branch is predicted as "taken" then the target instructions are fetched and utilized to follow the conditional branch, if the prediction is resolved as correct. And of course, if the prediction of "taken" is incorrect the target instructions must be purged and the sequential instructions which follow the conditional branch instruction in program order must be retrieved.
As illustrated, multiscalar processor 10 also preferably includes a condition register 32. Condition register 32 is utilized to temporarily store the results of various comparisons which may occur utilizing the outcome of sequential instructions which are processed within multiscalar processor 10. Thus, floating point processor unit 24, fixed point processor unit 26 and branch processor unit 28 are all coupled to condition register 32. The status of a particular condition within condition register 32 may be detected and coupled to branch processor unit 28 in order to generate target addresses, which are then utilized to fetch target instructions in response to the occurrence of a condition which initiates a branch.
Thereafter, a branch processor unit 28 couples target addresses to fetcher 30. Fetcher 30 calculates fetch addresses for the target instructions necessary to follow the conditional branch and couples those fetch addresses to cache/memory interface 20. As will be appreciated by those having skill in the art, if the target instructions associated with those fetch addresses are present within cache/memory interface 20, those target instructions are loaded into instruction queue 22. Alternately, the target instructions may be fetched from memory 18 and thereafter loaded into instruction queue 22 from cache/memory interface 20 after a delay required to fetch those target instructions.
As those skilled in the art will appreciate, each task within multiscalar processor 10 will typically have associated therewith an effective or virtual memory space and instructions necessary to implement each task will be set forth within that space utilizing effective or virtual addresses. Thus, fetcher 30 must be able to determine the real address for instructions from the effective addresses utilized by each task. As described above, prior art implementations of fetcher 30 typically either incorporate a complex translation lookaside buffer (TLB), sequence register and multiple translation algorithms or, alternately, such instruction fetchers are required to access a memory management unit (MMU) having such complex translation capability in order to determine real instruction addresses from effective or virtual instruction addresses.
Also depicted within multiscalar processor 10 is memory management unit (MMU) 34. Memory management unit, as will be described in greater detail herein, preferably includes a translation lookaside buffer (TLB) and all necessary registers and translation algorithms which may be utilized to translate each effective address within multiscalar processor 10 into real address within system memory 18. Fetcher units typically have a very low priority for accessing a memory management unit (MMU) and therefore some delay is expected in the obtaining of real instruction address utilizing a memory management unit (MMU).
With reference now to Figure 3, there is depicted a more detailed block diagram illustrating a translation lookaside buffer (TLB) and memory management unit (MMU) within multiscalar processor 10 of Figure 2. As illustrated within Figure 3, the relationship between cache/memory interface 20, fetcher 30 and memory management unit (MMU) 34 is depicted. As is typical in known memory management units, memory management unit (MMU) 34 includes a substantially sized translation lookaside buffer (TLB) 40. Those skilled in the art will appreciate that a translation lookaside buffer (TLB) is often utilized as a fairly rapid technique for translating from effective or virtual address to real address. Also present within memory management unit (MMU) 34 is PTE translator 42 and BAT translator 44. PTE translator 42 is preferably utilized to implement page table type translation and BAT translator 44 is utilized to translate address block type translations. Those skilled in the art will appreciate that these two translation algorithms are substantially different, in that a page table translation occurs within a system having consistently sized memory pages while an address block translation may result in a defined address block having, for example, a size ranging from twenty-eight kilobyte block to eight megabytes of memory.
Thus, upon reference to Figure 3, those skilled in the art will appreciate that by utilizing translation lookaside buffer (TLB) 40 in conjunction with PTE translator 42, all effective addresses within multiscalar processor 10 (see Figure 2), which utilizes the page table translation may be translated into a real address within system memory. Of course, those skilled in the art will also appreciate that a segment register may also be utilized for such translations. Alternately, address block translations may be accomplished utilizing only BAT translator 44. By providing multiple translation algorithms in the manner depicted, every effective or virtual address within multiscalar processor 10 may be translated into a real address within system memory by utilizing memory management unit (MMU) 34.
As those skilled in the art will appreciate fetcher 30 is utilized to couple fetch addresses to cache/memory interface 20 for target instructions which are selected by branch unit 28. For each target address coupled to fetcher 30 from branch unit 28 a fetch address is determined and coupled to cache/memory interface 20. In the depicted embodiment of the present invention, these addresses may often be determined by accessing translation lookaside buffer (TLB) 40 within memory management unit 34. Thus, it should be apparent that in order to maintain coherence within each multiscalar processor 10 within multiprocessor data processing system 6 it will be necessary to maintain coherence between each translation lookaside buffer (TLB) 40 within each multiscalar processor 10.
Referring now to Figure 4, there is depicted a high level logic flowchart which illustrates the initiation of a translation lookaside buffer invalidate (TLBI) instruction by one multiscalar processor within multiprocessor data processing system 6 of Figure 1. Those skilled in the art will appreciate that a translation lookaside buffer invalidate (TLBI) instruction is issued within the data processing system in order to invalidate an entry within a translation lookaside buffer (TLB) which might otherwise be utilized to translate effective or virtual addresses into real addresses within system memory. Such situations will, of course, occur as a result of the relocation of data or instructions within system memory or as a result of any other operation which modifies the translation relationship between an effective or virtual address and its real address within system memory.
As depicted within Figure 4, the process begins at block 50 and thereafter passes to block 52. Block 52 illustrates a determination of whether or not a translation lookaside buffer invalidate (TLBI) instruction is within the e "EXECUTE" position within a fixed point processor in a multiscalar processor within multiprocessor data processing system 6 of Figure 1. If this situation does not occur, the process merely iterates until such time as translation lookaside buffer invalidate (TLBI) instruction is detected within the "EXECUTE" position in a fixed point processor unit within the system. After detecting a translation lookaside buffer invalidate (TLBI) instruction the process passes to block 54. Block 54 illustrates the performance of the translation lookaside buffer invalidate (TLBI) instruction locally, upon the translation lookaside buffer (TLB) within the local multiscalar processor. Thereafter, the process passes to block 56.
Block 56 illustrates the arbitration for bus access by the local multiscalar processor and thereafter, the process passes to block 58. Block 58 illustrates a determination of whether or not access has been granted to bus 8 (see Figure 1) and if not, the process returns iteratively to block 56 to again attempt to arbitrate for bus access. After gaining access to bus 8, as determined at block 58, the process passes to block 60. Block 60 illustrates the broadcasting on bus 8 of a translation lookaside buffer invalidate (TLBI) bus structure, which is associated with the translation lookaside buffer invalidate (TLBI) instruction which has just been executed. Upon reference to the foregoing those skilled in the art will appreciate that an existing memory bus structure may be utilized with an expanded set of transaction codes and that the translation lookaside buffer invalidate (TLBI) instruction may be either an "index" based invalidate, or may comprise the broadcasting of a full virtual address of the page which is being invalidated by the translation lookaside buffer invalidate (TLBI) instruction.
Next, the process passes to block 62. Block 62 illustrates the determination of whether or not a "RETRY" message has been detected, indicating that one of the multiscalar processor systems within multiprocessor processing systems 6 has not accepted the broadcast translation lookaside buffer invalidate (TLBI) bus structure. If this occurs, the process returns to block 56 in an iterative fashion to once again attempt to broadcast the translation lookaside buffer invalidate (TLBI) bus structure in the manner described above. However, in the event a "RETRY" message is not detected, indicating that each multiscalar processor system within multiscalar data processing system 6 has accepted the broadcast translation lookaside buffer invalidate (TLBI) bus structure, the process then passes to block 64. Block 64 once again illustrates the arbitration by the local multiscalar processor for bus access and the process then passes to block 66. Block 66 illustrates a determination of whether or not access to the bus has been gained. If no access has been gained, the process returns iteratively to block 64 until such time as bus access has been gained.
Referring now to block 68, after gaining access to the bus block 68 illustrates the broadcasting of a "SYNCHRO" signal by the initially executing processor within multiprocessor data processing system 10. This signal is utilized to determine whether or not each multiscalar processor within the multiprocessor data processing system has executed the translation lookaside buffer invalidate (TLBI) instruction.
Referring now to block 70 in the event a "RETRY" message is detected, indicating that one or more processors within multiprocessor data processing system 6 have failed to complete the translation lookaside buffer invalidate (TLBI) instruction, the process returns iteratively to block 64 to once again attempt to obtain confirmation that all multiscalar processors within multiprocessor data processing system 6 have executed the translation lookaside buffer invalidate (TLBI) instruction. After receiving an indication that each processor has executed the instruction, the process passes to block 72 and returns.
With reference now to Figure 5, there is depicted a high level logic flowchart illustrating the processing of a translation lookaside buffer invalidate (TLBI) instruction throughout the multiprocessor data processing system of Figure 1 in accordance with the method and system of the present invention. As illustrated, this process begins at block 100 and thereafter passes to block 102. Block 102 illustrates a determination of whether or not the translation lookaside buffer invalidate (TLBI) bus structure which was broadcast along bus 8 has been detected at a multiscalar processor within multiprocessor data processing system 6. If not, the process merely iterates until such time as this event occurs.
Still referring to block 102, in the event a translation look aside buffer invalidate (TLBI) bus structure has been detected, the process passes to block 104. Block 104 illustrates a determination of whether or not the flag "TLBI PENDING" has been set, indicating that a previous translation lookaside buffer invalidate (TLBI) is still pending and has not yet completed execution. If so, the process passes to block 106 which illustrates the assertion of the "RETRY" message, indicating that the current multiscalar processor has not accepted the translation lookaside buffer invalidate (TLBI) bus structure. Thereafter, the process passes to block 108 and returns.
Referring again to block 104, in the event the flag "TLBI PENDING" is not set, the process passes to block 110. Block 110 illustrates a determination of whether or not any other multiscalar processor within multiprocessor data processing system 6 has asserted a "RETRY" message, indicating that the translation lookaside buffer invalidate (TLBI) bus structure was not accepted at another processor. If so, the process passes to block 112. Block 112 illustrates the ignoring of the translation lookaside buffer invalidate (TLBI) bus structure and the process then passes to block 108 and returns.
Referring again to block 110, in the event the "TLBI PENDING" flag is not set and no other processor within multiprocessor data processing system 6 has asserted a "RETRY" message, the process passes to block 114. Block 114 illustrates the setting of the "TLBI PENDING" flag and the process of executing the translation lookaside buffer invalidate (TLBI) instruction begins.
Referring now to block 116, the process illustrated therein depicts the terminating of the dispatching of instructions within the multiscalar processor and the storing of the addresses for those instructions which are pending within the queue within that processor. Next, the process passes to block 118. Block 118 illustrates a determination of whether or not the "EXECUTE" position within the fixed point processor has cleared, indicating that no pending instruction is about to execute. If not, the process merely iterates until such time as this condition occurs.
Still referring to block 118, after determining that the "EXECUTE" position within a fixed point processor is clear, the process passes to block 120. Block 120 illustrates the insertion of the associated translation lookaside buffer invalidate "TLBI" instruction into the "EXECUTE" position within the fixed point processor for this multiscalar processor. The process then passes to block 122. Block 122 illustrates the local performance of the translation lookaside buffer invalidate (TLBI) instruction.
Next, in accordance with an important feature of the present invention, the process passes to block 124. Block 124 illustrates a determination of whether or not all operations within memory queue 36 have achieved coherency. That is, each multiscalar processor within multiprocessor data processing system 6 is aware of the read and write operations which are pending within memory queue 36. In the event all operations within memory queue 36 (see Figure 2) have not achieved coherency, the process merely iterates until such time as this condition occurs. Thereafter, after all read and write operations within memory queue 36 have achieved coherency, the process passes to block 126.
Block 126 illustrates the purging of the instruction queue prefetch buffers. Upon reference to the foregoing those skilled in the art will appreciate that the fetcher will necessarily execute faster than the instruction queue and as a consequence may prefetch instructions from addresses which have been invalidated by the execution of the translation lookaside buffer invalidate (TLBI) instruction. Therefore, it will be necessary to purge the instruction queue prefetch buffers to assure that all instructions placed within those buffers are fetched after the modification to the translation lookaside buffer (TLB) has occurred.
Next, the process passes to block 128. Block 128 illustrates the branching by this multiscalar processor to the stored pending instruction address, utilizing the modified translation lookaside buffer (TLB). As described above, this step is necessary to ensure that the instructions placed within the execution position in the processor have been retrieved utilizing the most recent data within the translation lookaside buffer (TLB). Thereafter, the flag "TLBI PENDING" is cleared and normal dispatch and execution of instructions is resumed. Thereafter, the process passes to block 130 and returns.
Finally, with reference to Figure 6, there is depicted a high level logic flowchart illustrating the synchronization of multiple translation lookaside buffer invalidate (TLBI) instructions within the multiprocessor data processing system of Figure 1 in accordance with the method and system of the present invention. As illustrated, this this process begins at block 80 and thereafter passes to block 82. Block 82 illustrates the detection of a "SYNCHRO" signal by a multiscalar processor within multiprocessor data processing system 6. In the event this signal is not detected, the process merely iterates until such time as a "SYNCHRO" signal is detected.
After detecting a "SYNCHRO" signal, the process passes to block 84. Block 84 illustrates a determination of whether or not a translation lookaside buffer invalidate (TLBI) instruction is pending within the current multiscalar processor. This is preferably accomplished by checking the state of the "TLBI PENDING" flag within the processor. In the event the "TLBI PENDING" flag is not set, the process merely passes to block 88 and returns. Alternately, if the "TLBI PENDING" flag is set, the process passes to block 86. Block 86 illustrates the assertion by this processor of the "RETRY" message, indicating that synchronization has not yet been accomplished throughout the multiprocessor data processing system with respect to this translation lookaside buffer invalidate (TLBI) instruction.
Upon reference to the foregoing those skilled in the art will appreciate that the Applicants herein have presented a method and system for maintaining translation lookaside buffer (TLB) coherency in a multiprocessor system which does not require interprocessor interrupts and software synchronization and which achieves true coherency within each translation lookaside buffer (TLB) by broadcasting a bus structure associated with each translation lookaside buffer invalidate (TLBI) instruction which must be accepted by all multiscalar processors and by assuring that operations within the memory queue and instruction queues of each multiscalar processor are invalidated and thereafter completed utilizing the modified translation lookaside buffer (TLB). By inserting the translation lookaside buffer invalidate (TLBI) instruction into the execution pipeline within a multiscalar processor an effective branch to the next instruction will occur at the end of the execution of the translation lookaside buffer invalidate (TLBI) instruction, permitting subsequent instructions which have been prefetched to be discarded and refetched under the new context.
executing the associated translation lookaside buffer invalidate instruction at all remaining processors (10) among the plurality of processors only in response to an acceptance of the translation lookaside buffer invalidate bus structure at all remaining processors among the plurality of processors.
A method as claimed in Claim 1, including terminating execution of pending instructions within each cf the plurality of processors (10) in response to pending execution of the associated translation lookaside buffer invalidate instruction.
A method as claimed in Claim 2, including temporarily storing addresses of the pending instructions in response to pending execution of the associated translation lookaside buffer invalidate instruction.
A method as claimed in Claim 3, including inserting the associated translation lookaside buffer invalidate instruction into a processor unit within each of the plurality of processors (10) following termination of pending execution of instructions therein.
A method as claimed in Claim 4, including suspending execution of instructions within each of the plurality of processors (10) until such time as coherency is achieved with respect to all pending read and write operations within the system memory (18).
A system as claimed in Claim 6, including means for terminating execution of pending instructions within each of the plurality of processors in response to pending execution of the associated translation lookaside buffer invalidate instruction.
A system as claimed in Claim 7, further including means for storing addresses of the pending instructions in response to pending execution of the associated translation lookaside buffer invalidate instruction.
A system as claimed in Claim 8, including means for inserting the associated translation lookaside buffer invalidate instruction into a processor unit within each of the plurality of processors following termination of pending execution of instructions therein.
A system as claimed in Claim 9, further including means for suspending execution of instructions within each of the plurality of processors until such time as coherency is achieved with respect to all in pending read and write operations within the system memory.


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text:
Gionta claims Habs aren't 'far off'
By James O'BrienMay 18, 2010, 2:15 PM EDT
A 6-0 win usually indicates a serious imbalance, but as the playoffs have shown us time and time again, things can change very quickly. Brian Gionta admitted that the Canadiens were far behind the Flyers in Game 1, but seemed upbeat that the team could rebound with some minor tweaks.
Habs Eyes on the Prize has the story.
"We're not that far off," says Gionta, "It's a difficult way to start off, but we're to blame for that, and not a result of something special the Flyers were doing that we were unable to react to."
Gionta, who tried as he might to install himself in front of the Flyers goal and serve them some of their own medicine does not buy in that intimidation or size were factors in Game One.
"It's not as thought we were repeatedly knocked around. We simply weren't prepared," mentions Gionta, who along with Mike Cammalleri, was kept to one shot one goal.
"The Flyers excercise a consistent forecheck and we need to more the puck much quicker in order to force them to skate more. If they are applying puck pressure, one or two quick passes will destabilize them. From then on, they would not be coming at us so quickly."
It will be interesting to see how the Canadiens respond to that Game 1 drubbing. The team clearly deals with adversity well, even if some would reasonably argue that they've also had their fair share of lucky bounces. If the Habs could tie the series 1-1, the 6-0 defeat will just be a bad memory.

redpajama_set_name: RedPajamaCommonCrawl


text:
New Hyundai Tucson 2022 Hybrid, Release Date, Engine
Tucson / By alsulifan
New Hyundai Tucson 2022 Hybrid, Release Date, Engine – It appears just like the Korean carmaker is performed with all the increase of the SUV selection. Now it is transforming to the company's 2nd finest-marketing design to obtain some focus. Our company is referring to this Hyundai Tucson 2022, which is going to obtain a total redesign in the following calendar year. The test product continues to be traveling close to for a while. Still, it would wear an entire hide, indicating some quite significant style changes. Needless to say, we depend on novelties around other elements also, with regards to the interior design, different powertrain choices, and so forth.
Hyundai Tucson 2022 Redesign
At this stage, the design in the Hyundai Tucson 2022 will be quite possibly the most exciting point about this redesign. The screening version is utterly protected, so it is exactly about supposition. Judging around the spy pictures, we almost certainly will not see greater changes regarding the condition, even though some little dimension raise is feasible.
2022 Hyundai Tucson Exterior
On the opposite side, the latest style follows the brand's newest design words. What this means is a great deal of creativity removed from the newest Santa Fe. Also, numerous records advise a few unique specifics that can be included in the top finish in the well-liked crossover.
This is the best section within the car sector nowadays, brought by large titles just like Toyota RAV4, Honda CR-V, along with VW Tiguan. For that reason, any Korean carmaker needs to set a great deal of awareness of interior design, which will perform a crucial role nowadays in this auto marketplace. So, we depend on an entirely new structure and expect that this materials' good quality will boost, however, we will need to claim that the existing product presently appearance good following the latest update. Apart from new looks and components, we rely on better performance, therefore the innovative Hyundai Tucson 2022 ought to provide a bit more freight place and other points.
2022 Hyundai Tucson Interior
Hyundai Tucson 2022 Engine
We depend on no less than two engine choices inside the brand new Hyundai Tucson 2022. Probably, basic designs will come with a familiarized 2.4-liter 4-tube device, which will work for about 185 hp. That is a very respectable quantity of strength for day-to-day driving a car, but the majority of competition also provides better choices. So, we assume that Hyundai will perform the identical. The initial engine which comes to our thoughts can be a brand new 2.-liter turbo-4, which will work for about 235 horsepower. It feels like an ideal fit for the crossover of the sizing.
2022 Hyundai Tucson Engine
Hyundai Tucson 2022 Release Date And Price
By the most recent reviews, the latest Hyundai Tucson 2022 might struck the marketplace after that summertime. In terms of the particular price, we do not anticipate seeing considerable changes when compared to the existing design, which begins at around $23,500.


Hail is an open-source, scalable framework for exploring and analyzing genomic data.
lots more! Check out some of the new features in Hail 0.2.
Hail is a Python library with a scalable backend built on top of Apache Spark to efficiently analyze gigabyte-scale data on a laptop or terabyte-scale data on a cluster.
read over some of the How-To materials for inspiration.
Hail uses a continuous deployment approach to software development, which means features, bug fixes, and performance improvements land every day. We recommend updating the software frequently.
There are many ways to get in touch with the Hail team if you need help using Hail or would like to suggest improvements or new features.
post to the Discussion Forum for user support and feature requests.
chat with the Hail team and user community in Hail's Zulip chatroom.
Hail is maintained by a team in the Neale lab at the Stanley Center for Psychiatric Research of the Broad Institute of MIT and Harvard and the Analytic and Translational Genetics Unit of Massachusetts General Hospital.
Contact the Hail team: hail@broadinstitute.org.
Follow Hail on Twitter: @hailgenetics.
The Stanley Center for Psychiatric Research, which together with Neale Lab has provided an incredibly supportive and stimulating home.
Principal Investigators Benjamin Neale and Daniel MacArthur, whose scientific leadership has been essential for solving the right problems.
Jeremy Wertheimer, whose strategic advice and generous philanthropy have been essential for growing the impact of Hail.
We would like to thank Zulip for supporting open-source by providing free hosting, and YourKit, LLC for generously providing free licenses for YourKit Java Profiler for open-source development.


As part of the sociology seminar series here at Glasgow University, we had the pleasure of hosting Dr Bethan Harries (University of Manchester) from CoDE – Centre on Dynamics of Ethnicity. Bethan gave a paper entitled 'Young Adulthood and the Negotiation of Race in Contemporary Britain'. You can find the abstract for the paper below as well as an audio recording of her presentation.
Western cities are becoming more ethnically diverse and in many places becoming more youthful. The relationship between youth, young adulthood and race is undergoing significant social change. While some cogent areas of research such as education studies and cultural studies have maintained a focus on race and ethnicity, in youth and young adulthood studies more widely, 'post-subculture', race has been significantly absent (Harries et al forthcoming). This represents an oversight in social research. This paper draws on research with young adults and examines their relationship to and experience of living in a post-industrial cosmopolitan city. The city enables us to recognise the multiple ways in which racism manifests and explores the paradox that becomes apparent when the contemporary city is imagined as a tolerant multicultural space, i.e. beyond race, but is also a space through which race is reproduced. The paper considers how these conflicting processes are dealt with by young adults and examines the effects of the disjuncture between rhetoric and reality; between people's lived experience (of discrimination, racism and unequal treatment) and the growing discourse that says race no longer matters. Crucially, it considers whether strategies to silence race make it difficult to name racism, rather than working, as is sometimes the implied intention, as an anti-racist device.


Few cases of Zika virus disease have been reported in Jaipur, Rajasthan. The present outbreak in Jaipur, Rajasthan was detected through the ICMR surveillance system. As directed by Sh. J. P. Nadda, Union Health Minister, a 7-member high level Central team was deputed to Jaipur immediately following detection of first case to assist State Government in control and containment measures.
The situation is being reviewed at the level of Union Minister of Health and monitored on a daily basis by the Secretary, Health. A high level Joint Monitoring Group of Technical Experts headed by DGHS has met twice to monitor the preparedness and response measures.Another High Level Central Team is already placed in Jaipur (since 5th October, 2018) to further oversee and assist containment operations on the field. Till date a total of 22 positive laboratory confirmed cases have been detected. A Control Room has been activated at the National Centre for Disease Control (NCDC) to undertake regular monitoring of the situation.
All suspect cases in the defined area and mosquito samples from this area are being tested. Additional testing kits are provided to the Viral Research and Diagnostic Laboratories. The State Government has been supplied with IEC material prepared to create awareness about Zika virus disease and its prevention strategies. All pregnant mothers in the area are being monitored through NHM. Extensive surveillance and vector control measures are being taken up in the area as per protocol by the state government. The State Government has been supplied with IEC material prepared to create awareness about Zika Virus diseases and its prevention strategies.
Zika virus is a member of the Flaviviridae family and is transmitted to humans by mosquitoes. It is related to other pathogenic vector borne flaviviruses including dengue, West-Nile and Japanese encephalitis viruses but produces a comparatively mild disease in humans. In 2007, Zika virus caused an outbreak on the island of Yap in the Pacific.
The disease continues to be on disease surveillance radars of Union Health Ministry although it is no longer a Public Health Emergency of International Concern vide WHO notification since 18th November, 2016. The situation continues to be monitored regularly.


This review covers reports on the one-electron reductive cyclization reactions affording bicyclic compounds, such as hydrindans, perhydronaphthalenes, perhydroguaianes, and other systems including five-, six-, seven-, and eight-membered carbocycles using SmI2. The substrate is aldehyde, ketone, or ester. The effect of additives, such as H2O, MeOH, HMPA, and NiI2, was studied. The mechanistic aspects recently investigated are also introduced.


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The Best and Worst Democratic Presidential Candidate Websites of 2020
by Brett D. Gilman
Brett D. Gilman
Brett is the Managing Editor of this website. A former…
Mary Trump Shames America for Not 'Holding Powerful White Men Accountable for Anything'
The 2020 presidential election was an absolute rollercoaster. There were insults, attacks, the pandemic, and plenty of chest-beating brinksmanship. Russia did its best to influence proceedings, and the standing president appeared to lose his grip on sanity more and more as the days went by. We took an unexpected trip to Four Seasons Total Landscaping. It was a ball; it really was. From the nomination of candidates to the final days of the race, the internet was more important than ever before for candidates during this election cycle. This article zooms in on the Democratic candidacy and showcases some of the best and worst Democratic candidate websites of 2020.
The Worst
Let's get the awful websites over with first.
Steve Bullock
Montana governor Steve Bullock never really had a serious chance of becoming the Democratic presidential candidate: and his website reflects that. It scored very low on a number of important SEO ranking factors and received the least organic traffic of any candidate website as a result.
Colorado Governor John Hickenlooper didn't fare much better than Steve Bullock. His website scores poorly in a number of areas. Its sloth and poor mobile compatibility are particularly damaging factors.
Ohio Representative Tim Ryan's site was built using WordPress, but the usually SEO-friendly Content Management System has been somewhat abused by Ryan's web designers. The site loads extremely slowly and ranks very poorly in domain authority. He could have benefitted from hiring a company competent in WordPress maintenance and SEO optimization, which would have implemented some sweeping changes.
Now for something completely different; some good candidate websites.
Andrew Yang
[COMMENTARY/WATCH] Trump Was Willing to Do Anything to Stay in White House
Andrew Yang didn't do too well at the polls, but his website was top-notch. The Entrepreneurial candidate's website scored extremely well when it came to incorporating organic keywords, fitting in over 20,000 SEO-friendly examples.
The Massachusetts senator was an 'almost' candidate in 2020. Her website was rather good. It received 1.3 million unique visitors, loaded quickly, and was very SEO friendly. Warren's message was clear, and the design of the site was unobtrusive and intuitive.
Bernie Sanders might be a rather old fellow, but his message appealed directly to America's disenfranchised youth. His website felt just as youthful and spritely as his supporter base. It had almost 1 million backlinks from over 11 thousand domains, which is a very important ranking factor. Sanders' socially leaning message and policy points were on clear display throughout the site – leaving visitors absolutely sure of what he stood for. His site had the most unique visitors of any candidate, with 1.4 million people visiting. Sanders did not receive the presidential candidacy, but his successes will likely inspire other left-leaning political candidates.
You might have noticed that this article does not mention the winner of the Democratic presidential candidacy – and indeed the election – Joe Biden. His website was decidedly average and was rather confused in its messaging.
Andrew Yang bernie sanders Elizabeth Warren Four Seasons Total Landscaping John Hickenlooper Steve Bullock The Best and Worst Democratic Presidential Candidate Websites of 2020 Tim Ryan
Brett is the Managing Editor of this website. A former business executive turned teacher, activist, and writer, Brett also operates an anonymous Twitter account with a very large following.
Brett D. Gilman August 2, 2021
Bernie Sanders Says He Supports Primary Challengers For Manchin & Sinema
Elizabeth Warren: Biden Could Win Back Young Voters by Cancelling Student Debt
WATCH: Bernie Sanders Goes After Joe Manchin On Build Back Better Bill
WATCH: Elizabeth Warren Calls Out Elon Musk as 'The World's Richest Freeloader'
Critics Say Elon Musk is 'Worst Choice Ever' For TIME's Person Of The Year
MeidasTouch's "The Supporters" Mockumetary Lampoons MAGA World Celebrities


text:
import { EvpKDF } from '../index';

export = EvpKDF;

redpajama_set_name: RedPajamaGithub


text:
Swatch SISTEM51 turns the world upside down
MANILA, Philippines–In 1983, Swatch introduced a simplified, Swiss made quartz wristwatch with only 51 parts. The world's first plastic watch was made not by hand in the traditional Swiss manner, but on a fully automated assembly line.
Thirty years later, Swatch has done it again with SISTEM51. It is an automatic (self-winding) mechanical movement made from a total of 51 parts. The parts form five separate modules, which are welded into a single unit centered on a single screw.
Swatch SISTEM Black
SISTEM51 is the first and only mechanical movement with fully automated assembly. The high-tech escapement has no regulator; the rate is set at the factory with a laser, making the manual rate adjustments normally required by a mechanical watch unnecessary. The movement, which features a 90-hour power reserve, is made of ARCAP, an alloy of copper, nickel and zinc with exceptional anti-magnetic qualities. All parts are hermetically sealed within the case: no moisture, dust or foreign elements can interfere with performance, assuring a very long life and sustained accuracy over time (+/- 10 seconds per day).
Swatch SISTEM Blue
SISTEM51 is transparent. A distinguishing feature of Swatch from the outset, transparency is built into SISTEM51. Automatic movements are driven by an oscillating weight; the oscillating weight in SISTEM51 is a transparent disc that rotates freely around the central screw, offering fascinating views of the mechanics within. The oscillating weight and visible surfaces of the five movement modules are all printable, further enhancing the potential to add a creative soul to the back of this new watch.
Swatch SISTEM Red
SISTEM51 was conceived, developed and built entirely and exclusively in Switzerland, and in less than two years. Undeniably disruptive of the status quo in the Swiss watch industry, it was made possible by significant continuous investment on the part of Swatch Group in research and development and in key companies in Swatch's industrial environment. 100% Swiss made, SISTEM51 is a provocation, an audacious challenge to invest, like Swatch, in the future of the Swiss watch industry.
Swatch SISTEM White
SISTEM51 is now available in the Philippines at Swatch Shops in SM Megamall, Glorietta 1, Greenbelt 5 , TriNoma , Alabang Town Center , MarQuee Mall, Pampanga, SM Mall of Asia, SM City North EDSA, Greenhills V-Mall, Robinsons Place, Ermita, Sta. Lucia East Grand Mall, Festival Mall, Ayala Center, Cebu and SM City Cebu .
Like SwatchPH on Facebook: http://www.facebook.com/SwatchPH.
SISTEM BlackSISTEM BlueSISTEM RedSISTEM WhiteSISTEM51SwatchSwisswristwatch
jvillagracia
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The lack of PC Collector's Editions from Squaresoft is a bit disappointing.
To me, if there's no CE, it's not a Day-1 purchase, and at that point, I'd just as soon wait for the 'Complete' Edition.
Here's to hoping the Tomb Raider PC CE gets the green light.


Last night saw winners unveiled for the industry's first International Performance Marketing Awards.
The International Performance Marketing Awards landed for the first time last night (October 23) at the Hilton Bankside Hotel, welcoming over 300 performance marketers to celebrate the industry's growth and innovation globally.
Revealed live on the official IPMA Twitter account and now available to view in full below, the night's victors championed within 23 categories, each a badge of honour testament to their commitment to unrivalled client service and commitment to pioneering industry standards internationally.
The task of deciding the IPMA winners fell to the awards' panel of judges, represented by experts from the international offices of companies such as trivago, LinkedIn, Genie Ventures and Oath, among others.
Judge Adrian Cutler, Microsoft's agency director international, spoke of being "particularly impressed" with the standard of entries, highlighting the "tough competition" across the categories which cover regional-specific campaigns, international-level organisations and outside of the judges' remit, partner recommendations.
Perhaps most emblematic of the new award show's global direction, the Regional Awards saw competitors battle for Best Managed Affiliate Campaign and Best Performance Marketing Campaign or Strategy across multiple global markets.
Global performance marketing agency iProspect flexed its muscles early on with a campaign with General Motors for Best Performance Marketing Campaign or Strategy in the Middle East & Africa, taking on PMA newcomers, the Turkish-based Kubix Digital and Latitude Digital Marketing.
iProspect worked with GM to deliver the Middle East and Africa region "the car they never expected", in a campaign that delivered Cost per Rich Engagement of just 1 cent compared to a target of 23 and increased brand image indicators to 89% across key sales markets.
Opening a new Jakarta office to bolster its APAC footprint at the start of the year, Optimise's actions spoke louder than words, demonstrating unrivalled success in a region expected to overtake North America as the world's largest digital ad market within the next year.
Travel fare aggregator site Agoda saw 300% year-on-year sales growth thanks to work of Optimise in a campaign designed to deliver incremental sales on desktop, mobile web and in-app, across multiple markets in APAC.
In a category covering mature performance advertising markets such as the UK, Germany and Netherlands, it was no surprise that competition was incredibly tight in the Western Europe categories, and equally of little surprise that two established leaders took home the gongs.
Putting a focus on driving value through content, TUI sought holistic growth of its affiliate programme. Managed by CJ Affiliate, TUI's request was not only delivered, it was surpassed. Driving "enormous growth", effective return on investment stood at 38:1, well over twice as strong as the industry average.
Vouchercloud and Awin are behind fashion retailer TOPMAN's most innovative campaign to date; using a minimal budget, TOPMAN challenged discount partners to create a unique Christmas gifting campaign, resulting in the brand's market share increasing 41% and a revenue by 242% year on year.
The IPMAs were launched with one objective being to shine a light on the comparatively quiet engine rooms of markets such as LATAM. The success of Experiencias Xcaret in Mexico is a rare glimpse of affiliate marketing's value and intelligent application across the globe.
Tapping into the burgeoning US tourist industry in Cancun and with a mindset focused on campaign sustainability, Mexican tour experience company Experiencias Xcaret grew 141% in 2016 through affiliate, adding over 1,000 new partners and boasting an ROI of 1500%.
Optimise's current prowess across the globe is tangible, with the group returning in the regional categories last night to seal a LATAM win with its campaign for the esteemed brand Santander in the booming Brazilian market.
Supporting the launch of the new Santander credit card in Brazil, Optimise's performance-based native media campaign involved innovative use of data and commercial models to exceed volume targets by 45%, while optimising cost per lead rates to 48% under budget.
In North America, a shortlist of heavyweights vied for the title of Best Managed Affiliate Campaign with Awin, CJ Affiliate, Rakuten Marketing, Performance Horizon, OPMPros and SSENSE staking success on activity with brands such as Superdry, Marriott, Missguided and FedEx.
Citing US e-commerce expansion as a priority, Superdry worked with Awin to target key publishers in North America, driving treble digit revenue growth and a significant number of new customers; the region contributed 44% of global affiliate revenue in Q4 2016, now the largest revenue-driving territory in Superdry's affiliate mix.
Best Performance Marketing Campaign or Strategy in the same region, meanwhile, featured campaigns with Button and Ibotta, Mediacom and Emirates, Awin and MyProtein, CJ Affiliate and Lucky Brand, and OPMPros and Marriott.
With ambitions to become the number one airline in the global affiliate space, Emirates worked with Mediacom and Performance Horizon to roll out an innovative new commission model with the launch of the airline's Fort Lauderdale route campaign in the US; the result blasted expectations, paving the way for the strategy to go global.
Set to be one of the most rapidly developing global markets in the next two years according to a report by Zenith this year, the Eastern Europe categories proved that many are in an early position to seize on the region's growth with some promising campaigns bearing early fruit.
A fashion retailer leader in the Czech market, ZOOT.cz enlisted CJ Affiliate and VIVnetworks to orchestrate a shrewd program strategy that increased the program's new customer acquisition by 35% and achieved the desired level of content program revenue, ultimately raising the channel's value for the client.
Sportswear brand New Balance partnered with Awin to disrupt its affiliate presence and realign its brand image in Poland. Partnering with publisher Pro Position, a market-pioneering SEM campaign was launched which ultimately delivered a fourfold increase in clicks and a near doubling of sales in the region.
MEC overcame strict Apple brand restrictions with creative panache for client Vodafone, identifying and targeting an audience of three million consumers in the market for a new iPhone, in what resulted as the carrier's most successful display campaign to date and lowest ever CPA.
E-commerce in Scandinavia made an appearance last night with JVWEB and Swedish clothing brand Geggamoja.
A complement of unique technology and local knowledge sat at the heart of JVWEB's AdWords campaign for organic clothing company Geggamoja. Across Sweden and Europe, this campaign exceeded expected revenue by 36%, with continuations an immediate success.
Under the expertise of Marin and tapping into its innovative technology, renowned newspaper The Economist boosted new subscriptions by 66% through a highly-targeted Facebook video campaign; the result shattered targets while generating a 72% lower CPC than image-based ads.
Rewarded for two exceptional campaigns for household brands last night, MEC UK returned to scoop another accolade, pushing boundaries in programmatic efficiency for mobile carrier Vodafone.
Harnessing the concept of "marginal gains" was key to to improving and optimising already stellar performance in programmatic advertising for MEC's client - mobile carrier Vodafone - in a campaign which looked to other industries and fields of science for inspiration.
With a client roster including adidas, Reebok, Target and Warby Parker, Acceleration Partners drove $1 billion in revenue for its world-leading clients last year. The largest independent affiliate marketing agency in the US, the company allocates more resources to programmes than any other, continually raising the bar for the global industry.
It's no surprise that the shortlist for Best International Affiliate Network drew out a punchy roster, with Rakuten Marketing (US), CJ Affiliate (US), Awin (Germany) and Optimise (UK) taking on Awards' newcomers BitterStrawberry (Switzerland), MOBIDEA (Luxembourg) and Adcombo (Canada).
Awin's passion for affiliate marketing leads the network to create solutions that drive transformation for the entire industry; the network is firmly committed to making affiliate marketing easier, as well as providing unsurpassed data and insights.
Present in over 250 markets and six continents, BitterStrawberry.com is a mobile-oriented affiliate network active across the globe; its powerful performance tracker and analytics capabilities help publishers, affiliates and media buyers deep dive and easily optimize their campaigns.
30% of the world's largest brands, agencies and influencer platforms trust HYPR's data. Specialising in smart influencer search and discovery, HYPR provides real-time analytics for social influencers, while its targeted discovery platform opens up millions of highly-engaged influencers to its partners in just seconds.
Competing for one of the ceremony's most coveted titles, Spanish-headquartered Marfeel joined a US-heavy lineup featuring Button, HYPR, Rakuten Marketing, iProspect, Impact Radius, Lytics and Wickfire to compete for the title of Best Performance Marketing Technology.
Rakuten Marketing understands the complexities of the modern consumer journey, that's why it developed Cadence - a proprietary cross-channel, cross-device insights and attribution platform; the embodiment of data transparency and innovation that gives marketers a full view of their marketing performance.
Winners of the Industry Awards received streams of glowing praise from partners across the world, with clients praising customer service, pioneering technology and the ability to become "independent" as a result of their support.
An incredibly competitive and highly sought-after award, CJ Affiliate by Conversant has earned the round praise of an international client-base to be awarded the IPMA's Industry Choice of Network. Called "ahead of the curve" and lauded for "fantastic management" by a wealth of peers, CJ Affiliate is a multi-market affiliate leader and a worthy bearer of this coveted award.
The stellar competition vying for the Industry Choice of Agency award is a testament to the outstanding quality of champion iProspect. Partners from across multiple markets praised the agency's industry-leading support, expertise and innovation, as well as its firm commitment to advertising transparency.
Going against some of performance marketing's leaders in tech, HasOffers by Tune triumphed in the Industry Choice of Technology category. The company was praised by partners for usability, pioneering software, unrivalled support, and the independence it provides its clients across the globe.
With the International Performance Marketing Awards now behind us, eyes will now be set on the Performance Marketing Awards 2018, which return to the Grosvenor House Hotel in April next year with a slew of new categories.
The IPMAs also represent the first official networking event of PerformanceIN LIVE, the two-day international performance marketing show taking place at London's Old Billingsgate for the next two days (October 24-35). Find out more about attending here.


text:
Software Engineer Contracts in the South East
Software Engineer Vacancies
The median contractor rate for a Software Engineer was £425 per day in advertised job vacancies in the South East during the 6 months to 17 July 2019.
The first table below provides contractor rate benchmarking and summary statistics including a comparison to same period in the previous 2 years.
Rank change year-on-year +17 +70 -45
Contract jobs requiring a Software Engineer 299 316 158
As % of all contract IT jobs advertised in the South East 2.01% 1.85% 0.99%
As % of the Job Titles category 2.12% 1.96% 1.05%
Number of daily rates quoted 144 132 80
South East median daily rate £425 £450 £380
Median daily rate % change year-on-year -5.56% +18.42% +1.33%
England median daily rate £450 £450 £428
% change year-on-year - +5.26% +3.01%
South East median hourly rate £46.50 £45.00 £45.00
Median hourly rate % change year-on-year +3.33% - +5.88%
England median hourly rate £46.00 £43.00 £42.50
The following table is for comparison with the above and includes summary statistics for all contract IT job vacancies advertised in the South East. Most job vacancies include a discernible job title that can be normalized. As such, the figures in the second row provide an indication of the number of contract jobs in our overall sample.
All Contract IT Job Vacancies
Contract vacancies in the South East with a recognized job title 14,125 16,144 15,075
% of contract IT jobs with a recognized job title 94.80% 94.65% 94.61%
Number of hourly rates quoted 621 693 733
Median hourly rate % change year-on-year +18.42% +8.57% -12.50%
% change year-on-year +6.95% +1.08% -2.63%
Job postings that featured Software Engineer in the job title as a percentage of all IT jobs advertised in the South East.
Contractor Daily Rate Trend in the South East
This chart provides the 3-month moving average for daily rates quoted in contract jobs citing Software Engineer in the South East.
Contractor Daily Rate Histogram in the South East
The daily rate distribution of IT jobs citing Software Engineer in the South East over the 6 months to 17 July 2019.
Contractor Hourly Rate Trend in the South East
This chart provides the 3-month moving average for contractor hourly rates quoted in IT jobs citing Software Engineer in the South East.
Contractor Hourly Rate Histogram in the South East
The hourly rate distribution of IT jobs citing Software Engineer in the South East over the 6 months to 17 July 2019.
Contract Job Locations in the South East
The table below looks at the demand and provides a guide to the median contractor rates quoted in IT jobs citing Software Engineer within the South East region over the 6 months to 17 July 2019. The 'Rank Change' column provides an indication of the change in demand within each location based on the same 6 month period last year.
Thames Valley +1 111 £425 -5.56% 154
Hampshire +46 107 £400 +14.29% 81
Oxfordshire +14 51 £425 -5.56% 80
Berkshire +6 48 £425 +7.26% 53
Surrey -3 35 £500 +14.29% 46
Kent -1 21 £475 +11.76% 10
Buckinghamshire +12 12 £405 -10.00% 21
West Sussex +4 11 £438 +2.94% 23
East Sussex -18 7 £300 -9.09% 9
Sussex - 4 - -
M4 Corridor - 2 - -
Software Engineer Skill Set
For the 6 months to 17 July 2019, Software Engineer contract jobs required the following IT skills in order of popularity. The figures indicate the absolute number co-occurrences and as a proportion of all contract job ads across the South East region featuring Software Engineer in the job title.
4 102 (34.11%) C
5 86 (28.76%) C#
8 62 (20.74%) Security Cleared
10 58 (19.40%) JavaScript
11 53 (17.73%) .NET
11 53 (17.73%) SC Cleared
12 49 (16.39%) Embedded C
14 41 (13.71%) Microsoft Azure
15 40 (13.38%) Test Automation
17 33 (11.04%) Scrum
18 32 (10.70%) DevOps
19 30 (10.03%) Law
20 28 (9.36%) HTML
20 28 (9.36%) Mathematics
20 28 (9.36%) Algorithms
21 26 (8.70%) SQL Server
21 26 (8.70%) Web Services
22 25 (8.36%) Embedded C++
4 4 (1.34%) Apache Qpid
4 4 (1.34%) Jupyter
5 3 (1.00%) Tomcat
7 1 (0.33%) Apache Pig
7 1 (0.33%) Hyperledger
7 1 (0.33%) JBoss
7 1 (0.33%) WebSphere
1 11 (3.68%) Simulink
2 3 (1.00%) Adobe XD
2 3 (1.00%) InVision
1 9 (3.01%) Sparx Enterprise Architect
2 17 (5.69%) Amazon AWS
4 11 (3.68%) Azure Functions
5 7 (2.34%) GitHub
7 2 (0.67%) Amazon Alexa
7 2 (0.67%) Azure Active Directory
7 2 (0.67%) npm
8 1 (0.33%) Amazon ELB
8 1 (0.33%) Apigee
8 1 (0.33%) AWS Lambda
8 1 (0.33%) Azure Machine Learning
8 1 (0.33%) Data Lake Analytics
1 10 (3.34%) RS-232
2 9 (3.01%) RS-485
4 5 (1.67%) 5G
4 5 (1.67%) Ethernet
6 3 (1.00%) LTE
6 3 (1.00%) Modbus
7 2 (0.67%) DVB
7 2 (0.67%) Wireshark
7 2 (0.67%) ZigBee
8 1 (0.33%) Q.931
8 1 (0.33%) RTCP
8 1 (0.33%) RTP
8 1 (0.33%) Wi-Fi
4 9 (3.01%) Cosmos DB
5 8 (2.68%) Relational Database
6 7 (2.34%) Hadoop
6 7 (2.34%) PostgreSQL
7 6 (2.01%) SQL Server 2008
8 4 (1.34%) RDBMS
9 3 (1.00%) SQLite
10 2 (0.67%) Cloudera CDH
11 1 (0.33%) Azure SQL Data Warehouse
11 1 (0.33%) Blockchain
11 1 (0.33%) HDInsight
2 23 (7.69%) Selenium
4 20 (6.69%) Subversion
6 17 (5.69%) Jenkins
8 11 (3.68%) Visual Studio Team System
9 9 (3.01%) NUnit
9 9 (3.01%) WebDriver
10 8 (2.68%) Bitbucket
10 8 (2.68%) Mocha
10 8 (2.68%) SpecFlow
10 8 (2.68%) TeamCity
11 7 (2.34%) SonarQube
12 6 (2.01%) Eclipse
12 6 (2.01%) Maven
13 5 (1.67%) Ant
13 5 (1.67%) ClearCase
13 5 (1.67%) CppUnit
1 30 (10.03%) Law
4 9 (3.01%) Aerospace
5 8 (2.68%) Automotive
6 7 (2.34%) Games
8 2 (0.67%) Avionics
1 53 (17.73%) .NET
2 28 (9.36%) HTML
4 25 (8.36%) AngularJS
5 23 (7.69%) CSS
6 22 (7.36%) ASP.NET
7 21 (7.02%) XML
8 20 (6.69%) HTML5
9 18 (6.02%) ASP.NET Web API
9 18 (6.02%) RESTful
10 17 (5.69%) JSON
11 16 (5.35%) REST
12 12 (4.01%) Redux
12 12 (4.01%) Spring
13 11 (3.68%) Vue.js
14 10 (3.34%) WCF
4 12 (4.01%) Embedded Systems
6 8 (2.68%) CAN bus
7 7 (2.34%) Foreign Exchange (FX)
8 6 (2.01%) Life Science
9 5 (1.67%) Derivative
10 3 (1.00%) Device Driver
10 3 (1.00%) Robotics
11 2 (0.67%) Client/Server
11 2 (0.67%) Data Protection Act
11 2 (0.67%) Digital TV
11 2 (0.67%) Enterprise Software
11 2 (0.67%) Field-Programmable Gate Array
11 2 (0.67%) IPTV
11 2 (0.67%) Public Cloud
2 20 (6.69%) Windows
4 11 (3.68%) FreeRTOS
6 9 (3.01%) Embedded Linux
7 3 (1.00%) CentOS
7 3 (1.00%) Debian
7 3 (1.00%) Ubuntu
8 2 (0.67%) Android
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Where does the LDS practice of Naming and Blessing Children come from?
This practice appears to be a syncretistic form of infant baptism. Again, another example of Western Christianity's influence on Mormon religious life.
I am very interested in more information on this subject. Please let me know of any research done on this topic.


text:
Q: How to fix "Avoid passing null as the view root" in android? In my android app, I create a dialog like this:
private void handleEdit() {
    LayoutInflater inflater = getLayoutInflater();
    View dialoglayout = inflater.inflate(R.layout.dialog_gallery, null);

    final AlertDialog d = new AlertDialog.Builder(this)
    .setView(dialoglayout)
    .setTitle(R.string.edit)
    .setNegativeButton(R.string.cancel, null)
    .create();

    CheckBox mainCB = (CheckBox)dialoglayout.findViewById(R.id.main);
    CheckBox usedCB = (CheckBox)dialoglayout.findViewById(R.id.used);
    mainCB.setChecked(image.getIsMain());
    usedCB.setChecked(image.getApproved());

    mainCB.setOnClickListener(new OnClickListener() {
        @Override
        public void onClick(View arg0) {
            if (Network.isNetworkAvailable(GalleryScreen.this)) {
                new Async_update_image_state(GalleryScreen.this, fish, image, !image.getIsMain(), image.getApproved(), false);
                d.dismiss();
            } else {
                Popup.ShowErrorMessage(GalleryScreen.this, R.string.no_internet, false);
            }
        }
    });

    usedCB.setOnClickListener(new OnClickListener() {
        @Override
        public void onClick(View arg0) {
            if (Network.isNetworkAvailable(GalleryScreen.this)) {
                new Async_update_image_state(GalleryScreen.this, fish, image, false, !image.getApproved(), true);
                d.dismiss();
            } else {
                Popup.ShowErrorMessage(GalleryScreen.this, R.string.no_internet, false);
            }
        }
    });

    d.show();
}

But I get a warning on View dialoglayout = inflater.inflate(R.layout.dialog_gallery, null); underlining the null.
Avoid passing null as the view root (needed to resolve layout parameters on the inflated layout's root element)

What does this mean and how can I fix it?
Thanks.

A: When inflating a layout for use in a dialog, You can safely pass null here and ignore the warning.
From This Link

The issue here is that AlertDialog.Builder supports a custom view, but
  does not provide an implementation of setView() that takes a layout
  resource; so you must inflate the XML manually. However, because the
  result will go into the dialog, which does not expose its root view
  (in fact, it doesn't exist yet), we do not have access to the eventual
  parent of the layout, so we cannot use it for inflation. It turns out,
  this is irrelevant, because AlertDialog will erase any LayoutParams on
  the layout anyway and replace them with match_parent.

A: Instead of :
inflater.inflate(R.layout.dialog_gallery, null);

do:
inflater.inflate(R.layout.dialog_gallery, parent, false);

Using a @SuppressLint annotation as suggested by Eugen in the comment above might "suppress" the warning, but it doesn't solve the problem.Using null as an argument for the ViewGroup will cause you problems in the future.

A: this works for me
View.inflate(getActivity(), R.layout.dialog, null);

without any warnings nor errors.

A: Instead of
inflater.inflate(R.layout.dialog_gallery, null);

try
inflater.inflate(R.layout.dialog_gallery, null, false);

It will not attach view to the parent that is null in your case.
See details on Android Reference

redpajama_set_name: RedPajamaStackExchange


Corporate wellness means motivating employees to choose to live a healthier lifestyle, rather than forcing them to do so.
Forward-thinking companies have thrown the rigid work environment out the window. Companies are taking a holistic approach to employment, not just targeting performance reviews, but cultivating an environment that promotes healthy living, inspires creativity and collaboration, reduces employee stress and sick days, and encourages an engaged and happier workforce.
The emphasis on employee wellness is paying off. According to Harvard Business Review, on average, employers who invest in health and wellness saw savings of $6 in healthcare for every dollar invested. Companies like Johnson and Johnson saved $250 million on health care costs over the past decade; from 2002 to 2008.
As more corporations include wellbeing in their employee benefits, some stand out more than the rest. From free spinning classes and fitness gamification to meditation workshops and in-office massages, these companies excel in employee wellness.
Google has become famous for its non-traditional approach to the work environment that promotes work-life balance. Benefits include on-site healthcare services including access to a physician, chiropractor, physical therapist, and masseuse. Employees can stay in shape by attending exercise classes, using community bikes, or taking advantage of free entry to fitness centers. Google even throws in cool courses like guitar lessons, coding degree programs, cooking classes, and more.
Workers can fuel themselves throughout the day at the campus cafes and micro kitchens stocked with nutritious, color-coded meals and snacks as well as smaller plates for portion control. Employees also receive financial guidance from financial advisors. All of that comes with flexible work hours along with paid vacation and volunteer time. Talk about a good deal!
Intuit, a company that develops financial, accounting, and tax preparation software, really focuses on stress management and mental well-being. As a part of their "Fit for Life" program, employees get reimbursed for expenses related to physical, emotional, and financial well-being.
Their Well Minds program specifically covers costs for mindfulness and meditation classes that help with stress management. When entering a conference room, you'll find a "mindfulness moment" on the whiteboard giving tips for stress management. Intuit workers also get rewarded for stress-reducing activities like tracking monthly mediation minutes, taking a walk, engaging in breathing exercises, and listening to calming music.
Fitbit products measure the level of activity using wearable technology that tracks steps walked, heart rate, quality of sleep, steps climbed, diet, and other fitness activities. So it comes as no surprise that a company dedicated to personal health would strive to promote wellness among their employees. Working for Fitbit, you automatically get 50 percent discounts on their devices along with health benefits and affordable doctors. Employees also get flexible work hours with the option to take plenty of vacation. Fitbit even has its own Commerce product line so that companies can host corporate wellness programs for their employees.
Houston Methodist, a Texas medical center with seven locations throughout Houston, stands out as a perfect example of an organization putting the Fitbit Commerce program into action. They first enrolled in the Fitbit program back in 2014, supplying 11,000 devices to their 4,000 employees.
Using the Fitbit devices, Houston Methodist hosts Fitbit Challenges like a 10,000 steps goal, Beat Your CEO Challenge, or Battle of the Sexes Competition. Their "Pick Up Your Pace" program lets employees earn points for reaching goals for a certain number of steps, monthly visits to fitness centers, attending fitness classes, or recreational sports participation. Employees have won as much $10,000 in prize drawings through this wellness program!
Working at this investment publication comes with all kinds of perks, from free spinning classes and fitness boot camps to in-house massages. Chief Wellness Fool, Sam Whiteside, loves how promoting employee wellness encourages collaboration in the office. "I'm able to pull different 'Fools' from different departments that may have had only one conversation before, but come together and collaborate in a fitness class."
Each month, Whiteside releases a monthly health newsletter within the company called The Flex. Every issue proposes a new challenge to get staffers moving. That can mean pushups during meetings or walking around the building. Staff love the opportunity to mix up the routine and do something new around the office.
Employees also get free personal training sessions and wellness consultations. Whiteside described, "We discuss goals, and that gets the conversation going. When they know that I care, that's where the difference is made. I love personal training, but being a force that people can count on is huge for wellness."


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namespace Ausar
{
	namespace Sound
	{

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}


text:
Anti-elephant poaching story goes viral in China
Mongabay.com
Elephant in South Africa. Photo by Rhett A. Butler.
A newspaper story about the impact of the ivory trade has gone viral in China, raising awareness among millions of Chinese, reports the Wildlife Conservation Society (WCS).
The story, published November 15 in Southern Weekly, has been shared widely across Chinese web sites and social media, according to the conservation group.
"The total views of the original Southern Weekly Tweets and Retweets on Weibo (China's Twitter/Facebook hybrid) exceeded 10 million. Most of these "netizens," or members of the Chinese online public, were from Tier 1 Chinese cities (Beijing, Chongqing, Guangdong), the most significant consumers of ivory," said WCS in a statement.
"The article was reposted on 24 online discussion forums or Bulletin Board Systems (BBS) including Mop and Tianya, two of the most popular in China. Thousands of comments were generated on the Tianya BBS forum alone. Overall over 5,000 comments on the article were posted on Weibo, BBS fora, and other websites."
The story received wide play outside environmental news, being picked up on finance sites, according to WCS.
"This represents an important shift for the topic of ivory from the specialist environmental pages to the mainstream debate," said the group.
The poster reads: Protect the pandas of Africa – elephants. When the buying stops the killing can too. Image courtesy of WildAid.
The article, titled "The Blood Ivory: Behind the Largest Ivory Smuggling Cases in China", identified Chinese consumption as the main driver of elephant poaching. It noted links between the ivory trade and terror and rebel groups in Africa.
The ivory trade has exploded in recent years due to surging demand from middle class consumers in China. Conservationists estimate that up to 35,000 elephants may have been killed in 2012 alone.
The carnage has spurred several NGO's, including WCS, to step up campaigns targeting both the supply and demand sides of the trade. In September, the Clinton Global Initiative (CGI) gave these efforts a boost when it launched a massive push to catalyze support for stopping "blood ivory".
The poster reads: Do you want to own ivory dripping with blood? When the buying stops the killing can too. Image courtesy of WildAid.
But reaching Chinese buyers has remained a challenge. Therefore WCS welcomed the news that elephant ivory is now garnering attention in China.
"To have the influential mainstream media make the link between the elephant crisis and the Chinese demand for ivory is hugely significant," Cristián Samper, WCS President and CEO, said in a statement.
"In China, it's not just what is said but who says it," added Joe Walston, Executive Director of WCS's Asia Program. "To have the Southern Weekly give its front page to an article highlighting China's role in the ivory trade is monumental. This is no longer a fringe topic."