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Handbook of Semiconductor Manufacturing Technology
DK4126—Prelims —31/5/2007—20:41—SRIDHAR—240429—XML MODEL CRC12a – pp. 1–15 DK4126—Prelims —31/5/2007—20:41—SRIDHAR—24...
Author: Yoshio Nishi | Robert Doering
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DK4126—Prelims —31/5/2007—20:41—SRIDHAR—240429—XML MODEL CRC12a – pp. 1–15
Foreword to the Second Edition
In 1958, the year of the invention of the integrated circuit, the price of a single silicon transistor was about $10. Today, it is possible to buy more than 20 million transistors at that price. Not only the transistors but an equal number of passive components and a set of interconnections that permit the devices to function as a dynamic random access memory also can be bought for that price. This cost reduction is unprecedented. This progress was due to the work of tens of thousands of very capable engineers throughout the world. Every step of the fabrication process, from the preparation of pure silicon materials to the final packaging operations, has been carefully examined, reinvented, and improved. Highly automated equipment have been developed for the manufacturing processes. This book provides an overview of the current status of this work, and takes a look at the expected future growth of the semiconductor industry. These cost reductions have tremendously expanded the field of electronics. In 1958, the most common electronic products were radio and television sets, and the semiconductor market represented about $218 million. But now semiconductors are used in everything from automobiles to x-ray machines, and its worldwide market exceeds $200 billion. The success story is not yet over as the industry is expected to achieve remarkable growth in the future.
Jack S. Kilby
Preface to the Second Edition
The primary purpose of the second edition of this handbook is to serve as a reference to the practitioners and developers of semiconductor manufacturing technology. Most of the chapters deal with individual process, equipment, material, or manufacturing "control/support/infrastructure" technologies. However, we have supplemented these with a few overview chapters that provide additional background. There is a significant content of graphs, tables, and formulas, which experts in each subfield might find useful. However, unlike a "mostly numbers handbook," we have embedded such compact reference information into a basic description of current and anticipated practice in integrated circuit manufacturing. Although this handbook is not as tutorial as a typical textbook, we have attempted to make each chapter highly readable to nonspecialists in this field. We hope that the book is useful to the scientific community involved in the development and manufacturing of semiconductor products as well as to the students in this field. Note that the book mainly addresses silicon-based manufacturing, although many of the topics are applicable to building devices on other semiconductor substrates. Generous reference lists/bibliographies are also included for the benefit of readers. Making the best use of the freedom given by editors, the authors have used a breadth of approaches, as well as styles, across the chapters. Some have provided more "historical information," while the others have insisted more on "prognostication." There are chapters that stick pretty closely to the "traditional basics" and others that emphasize the current/future R&D challenges in the area. This flexibility has provided the authors an opportunity to express their personal perspectives and sense of excitement about what is important today and in the near future in this field. Of course, semiconductor manufacturing technology has become so specialized that many of the chapters required multidisciplinary expertise, which in turn has widened perspectives used in the book. It was definitely challenging to provide up-to-date reference data in a field as broad and rapidly changing as semiconductor manufacturing technology. For example, note the increase in page count found in the National/International Technology Roadmap for Semiconductors editions published from 1992 to 2005. We are glad to publish the second edition of this book, in which we have tried to anticipate what will be most relevant to readers in 2006 and beyond. While most of the authors, who are distinguished technologists in industry and academia, have updated their chapters from the first edition, some others have provided entirely new chapters on topics of current interest in semiconductor manufacturing or its R&D horizon. This continued scaling and evolution of device construction have also resulted in new issues and perspectives, which have influenced the topics as well as their treatments and relationships within this book. Our authors have responded to this challenge with an excellent coordination between and within chapters. The scenario in semiconductor industry, like when the first edition was published, still remains exciting and we again appreciate this opportunity to share the technical knowledge and experience of the authors/colleagues with the readers.
In addition to thanking the authors, we also like to acknowledge the contributions of Tim Wooldridge, our assistant editor. We have all enjoyed working on this project and hope that the readers too find the book interesting and useful.
Robert Doering and Yoshio Nishi
Robert Doering is a senior fellow and a technology strategy manager at the Texas Instruments (TI). His previous positions at TI include manager of Future-Factory Strategy, director of Scaled-Technology Integration, and director of the Microelectronics Manufacturing Science and Technology (MMST) Program. The MMST Program was a 5-year R&D effort, funded by the DARPA, the U.S. Air Force, and the TI, which developed a wide range of new technologies for advanced semiconductor manufacturing. The major highlight of the program was the demonstration, in 1993, of sub-3-day cycle time for manufacturing 350-nm CMOS integrated circuits. This was principally enabled by the development of 100% single-wafer processing. He received a BS degree in physics from the Massachusetts Institute of Technology in 1968 and a PhD in physics from the Michigan State University in 1974. He joined the TI in 1980, after serving several years as the faculty of the physics department at the University of Virginia. His research was based on the nuclear reactions and was highlighted by the discovery of the giant spin–isospin resonance in heavy nuclei in 1973 and by the pioneering experiments in medium-energy heavy-ion reactions in the late 1970s. His early work at the TI was on SRAM, DRAM, and NMOS/CMOS device physics and process flow design. His management responsibilities during the first 10 years at the TI included advanced lithography and plasma etching as well as CMOS and DRAM technology development. Dr Doering is an IEEE fellow and chair of the Semiconductor Manufacturing Technical Committee of the IEEE Electron Devices Society. He also chairs the National Research Council Board of Assessment for the NIST Electronics and Electrical Engineering Laboratory. He represents the TI on many industry committees, including the Technology Strategy Committee of the Semiconductor Industry Association, the board of directors of the Semiconductor Research Corporation (SRC), the Technical Program Group of the Nanoelectronics Research Corporation, and the Corporate Associates Advisory Committee of the American Institute of Physics. Dr Doering is also one of the two U.S. representatives to the International Roadmap Committee, which governs the International Technology Roadmap for Semiconductors. He has authored/presented over 150 publications and invited papers/talks and has 20 U.S. patents. Yoshio Nishi is a professor in the Department of Electrical Engineering (research) and also in the Department of Material Science and Engineering at the Stanford University since May 2002. He also serves as the director of the Stanford Nanofabrication Facility of National Nanotechnology Infrastructure Network of the United States and director of research of the Center for Integrated Systems. He received a BS degree in materials science and a PhD in electronics engineering from Waseda University and the University of Tokyo, respectively. He researched on semiconductor device physics and silicon interfaces in the Toshiba R&D, which resulted in the discovery of ESR PB Center at SiO2–Si interface, the first 256-bit MNOS nonvolatile RAM, SOS 16-bit microprocessor, and the world's first 1-MB CMOS DRAM. In 1986 he joined Hewlett-Packard as the director of the Silicon Process Lab, and then established the ULSI Research Lab.
Dr Nishi joined the TI, Inc. in 1995 as the senior vice president and the director of R&D for the semiconductor group, implemented a new R&D model for silicon technology development, and established the Kilby Center. Since May 2002, he became a faculty member at the Stanford University, and his research interest covers nanoelectronic devices and materials including a metal gate/high-k MOS, a device layer transfer for 3D integration, nanowire devices, and resistance change nonvolatile memory materials and devices. He has published more than 200 papers including conference proceedings, and he coauthored/edited nine books. He holds more than 70 patents in the United States and Japan. During the period of 1995–2002, he served as a board member of the SRC and the International Sematech, the NNI panel, the MARCO governing council, and other boards. Currently, he serves as an affiliated member of the Science Council of Japan. Dr Nishi is a fellow of the IEEE, a member of the Japan Society of Applied Physics and the Electrochemical Society. His recent awards include the 1995 IEEE Jack Morton Award and the 2002 IEEE Robert Noyce Medal.
Michael Ameen
Axcelis Technologies, Inc. Beverly, Massachusetts
Nick Atchison
Multigig, Inc. Scotts Valley, California
Sanjay Banerjee
Department of Electrical and Computer Engineering University of Texas at Austin Austin, Texas
Gabriel G. Barna
Process Development and Control Silicon Technology Development Texas Instruments, Inc. Dallas, Texas
Robert Baumann
Component Reliability Group Silicon Technology Development Texas Instruments, Inc. Dallas, Texas
Ivan Berry
Duane S. Boning
Stephanie Watts Butler
Silicon Technology Development Texas Instruments, Inc. Dallas, Texas
Jeff Byers
KLA-Tencor Austin, Texas
Andreas Cangellaris
Department of Electrical and Computer Engineering The University of Illinois Urbana, Illinois
Freescale Semiconductor, Inc. Austin, Texas
Sorin Cristoloveanu
Institute of Microelectronics, Electromagnetism and Photonics Grenoble, France
Francois M. d'Heurle
IBM Thomas J. Watson Research Center Yorktown Heights, New York
Vallabh H. Dhudshia
G. K. Celler
SafeFab Solutions Plano, Texas
Mei Chang
SEMATECH Austin, Texas
Soitec USA Peabody, Massachusetts
Applied Materials, Inc. Santa Clara, California
Walter Class
C. Rinn Cleavelin
Silicon Technology Development Texas Instruments, Inc. Austin, Texas
Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge, Massachusetts
Louis Breaux
Luigi Colombo
Will Conley
Alain C. Diebold
Girish A. Dixit
Novellus Systems, Inc. San Jose, Califonia
Simon Fang
United Microelectronics Corporation Hsin-Chu City, Taiwan
Leonard Foster
Facilities Department Texas Instruments, Inc. Dallas, Texas
Gene E. Fuller
Strategic Lithography Services Punta Gorda, Florida
Glenn W. Gale SEZ AG Villach, Austria
Ce´sar M. Garza
Hans-Joachim Gossmann
Axcelis Technologies, Inc. Beverly, Massachusetts and Advanced Micro Devices Hopewell Junction, New York
Gautum Grover
Cabot Corporation Aurora, Illinois
John R. Hauser
Electrical and Computer Engineering Department North Carolina State University Raleigh, North Carolina
Robert H. Havemann
Howard Huff SEMATECH Austin, Texas
G. Dan Hutcheson
VLSI Research, Inc. Santa Clara, California
Frederick W. Kern, Jr.
Hitachi Global Storage Technologies San Jose, California
Brian K. Kirkpatrick
Vincent Korthuis
Michael Lamson
Christian Lavoie
IBM Thomas J. Watson Research Center Yorktown Heights, New York and De´partement de Ge´nie Physique
E`cole Polytechnique de Montre´al Montre´al, Canada
Wen Lin
Consultant Allentown, Pennsylvania
Erdogan Madenci
Department of Aerospace and Mechanical Engineering University of Arizona Tucson, Arizona
Jonathon Reid
Novellus, Inc. San Jose, California
Syed A. Rizvi
Nanotechnology Education and Consulting Services San Jose, California
Texas Instruments, Inc. Santa Cruz, California
Andrew J. McKerrow
Stephen M. Rossnagel
J. W. McPherson
Leonard Rubin
Silicon Technology Development Texas Instruments, Inc. Dallas, Texas Silicon Technology Development Texas Instruments, Inc. Dallas, Texas
Mohammed J. Meziani
Department of Chemistry and Laboratory for Emerging Materials and Technology Clemson University Clemson, South Carolina
Hiro Niimi
E. T. Ogawa
Sylvia Pas
Pankaj Pathak
Devadas Pillai
Intel Corporation Chandler, Arizona
Shahid Rauf
IBM Thomas J. Watson Research Center Yorktown Heights, New York Axcelis Technologies, Inc. Beverly, Massachusetts
Dieter K. Schroder
Electrical Engineering Department Arizona State University Tempe, Arizona
Bruno W. Schueler Revera Inc. Sunnyvale, California
Thomas E. Seidel
AIXTRON, Inc. Sunnyvale, California
Thomas Shaffner
National Institute of Standards and Technology Gaithersburg, Maryland
Gregory B. Shinn
Terry Sparks
Greg S. Strossman
XPS/ESCA and TOF-SIMS Services Evans Analytical Group Sunnyvale, California
Ya-Ping Sun
P. J. Timans
Mattson Technology Fremont, California
Ting Y. Tsui
Eric M. Vogel
Li-Qun Xia
Lawrence C. Wagner
Shi-Li Zhang
Department of Electrical Engineering University of Texas at Dallas Dallas, Texas
Peter L. G. Ventzek
Semiconductor Quality Department Texas Instruments, Inc. Dallas, Texas
Brad VanEck
Samuel C. Wood
Responsive Learning Technologies Los Altos, California
School of Information and Communication Technology Royal Institute of Technology Stockholm, Sweden and School of Microelectronics Fudan University Shanghai, China
Introduction to Semiconductor Devices John R. Hauser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Overview of Interconnect—Copper and Low-K Integration Girish A. Dixit and Robert H. Havemann . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Silicon Materials Wen Lin and Howard Huff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
SOI Materials and Devices Sorin Cristoloveanu and George K. Celler . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Supercritical Carbon Dioxide in Semiconductor Cleaning Mohammed J. Meziani, Pankaj Pathak, and Ya-Ping Sun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1
Ion Implantation
Glenn W. Gale, Brian K. Kirkpatrick, and Frederick W. Kern, Jr. . . . . . . . . . . 5-1
Michael Ameen, Ivan Berry, Walter Class, Hans-Joachim Gossmann, and Leonard Rubin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1
Dopant Diffusion
Oxidation and Gate Dielectrics C. Rinn Cleavelin, Luigi Colombo,
Sanjay Banerjee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1
Hiro Niimi, Sylvia Pas, and Eric M. Vogel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
Silicides
Rapid Thermal Processing
Low-K Dielectrics
Christian Lavoie, Francois M. d'Heurle and Shi-Li Zhang . . . . . . . . . . . . . . . . . . . . . . . . . . .
P.J. Timans . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ting Y. Tsui and Andrew J. McKerrow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Li-Qun Xia and Mei Chang . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Atomic Layer Deposition
Thomas E. Seidel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stephen M. Rossnagel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Damascene Copper Electroplating
Jonathan Reid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chemical–Mechanical Polishing Gregory B. Shinn, Vincent Korthuis, Gautum Grover, Simon Fang, and Duane S. Boning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Optical Lithography
Photoresist Materials and Processing Ce´sar M. Garza, Will Conley, and Jeff Byers . . . . . . . . 19-1
Photomask Fabrication
Plasma Etch
Equipment Reliability Vallabh H. Dhudshia . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1
Overview of Process Control
In-Line Metrology Alain C. Diebold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1
In-Situ Metrology
Yield Modeling
Electrical, Physical, and Chemical Characterization
Dieter K. Schroder, Bruno W. Schueler, Thomas Shaffner, and Greg S. Strossman . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reliability Physics and Engineering
Effects of Terrestrial Radiation on Integrated Circuits Robert Baumann . . . . . . . . . . . . . . . . 31-1
Integrated-Circuit Packaging
Gene E. Fuller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Syed A. Rizvi and Sylvia Pas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peter L.G. Ventzek, Shahid Rauf, and Terry Sparks . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stephanie Watts Butler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gabriel G. Barna and Brad VanEck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ron Ross and Nick Atchison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Louis Breaux and Sean Collins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lawrence C. Wagner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . J.W. McPherson and E.T. Ogawa . . . . . . . . . . . . . . . . . . . . .
Michael Lamson, Andreas Cangellaris, and Erdogan Madenci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
300 mm Wafer Fab Logistics and Automated Material Handling Systems Leonard Foster and Devadas Pillai . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-1
Factory Modeling
Economics of Semiconductor Manufacturing
Samuel C. Wood . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G. Dan Hutcheson . . . . . . . . . . . . . . . . . . . . . . .
34-1 35-1
Appendix A: Physical Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 Appendix B: Units Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 Appendix C: Standards Commonly Used in Semiconductor Manufacturing . . . . . . . . . . . . . . . . . . . C-1 Appendix D: Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-1 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-1
Introduction to Semiconductor Devices 1.1 1.2 1.3
Introduction.......................................................................... 1-1 Overview of MOS Device Characteristics .......................... 1-3 MOSFET Device Scaling ...................................................... 1-8
Manufacturing Issues and Challenges............................... 1-22
John R. Hauser North Carolina State University
Scaling Rules
Performance of Scaled Devices
MOSFET Gate Stack Issues † Channel Doping Issues † Source/Drain Contact Issues † Substrate and Isolation Issues † Thermal Budget Issues
Advanced MOS Device Concepts...................................... 1-44
SOI Substrates and Devices † Multiple Gate MOS Devices † Transport Enhanced MOS Devices † MOSFETS with Other Semiconductors † Advanced Semiconductor Device Concepts
1.6 Conclusions......................................................................... 1-53 References ........................................................................................ 1-53
The silicon metal oxide semiconductor field effect transistor (MOSFET) has emerged as the ubiquitous active element for silicon very large scale integration (VLSI) integrated circuits. The competitive drive for improved performance and cost reduction has resulted in the scaling of circuit elements to ever-smaller dimensions. Within the last 35 years, MOSFET dimensions have shrunk from a gate length of 5 mm in the early 1970s to 45 nm today, and are forecast to reach less than 10 nm at the end of the projected shrink path in about 2020. While this process has been driven by market place competition with operating parameters determined by products, manufacturing technology innovations that have not necessarily followed such a consistent path have enabled it. This treatise briefly examines metal oxide semiconductor (MOS) device characteristics and elucidates important future issues which semiconductor technologists face as they attempt to continue the rate of progress to the identified terminus of the technology shrink path in about 2020. In the early days of semiconductor device development (the 1950s), the bipolar junction transistor was the dominant semiconductor device. As large-scale integration of devices developed in the 1960s, the MOSFET became the preferred device type and has eventually grown to dominate the use of semiconductor devices in integrated circuits (ICs). This has been predominantly due to the development of complementary MOS devices (CMOS), where digital logic circuits can be formed that exhibit extremely low power dissipation in either of the two logic states. Complementary MOS is not only a device technology, but also a logic circuit technology that dominates the IC world because of the advantages of very low power dissipation over other forms of semiconductor circuits. Thus, over time in 1-1
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the general scheme of ICs, bipolar semiconductor devices have come to be used in only special applications. Because of this dominance of MOS devices in large-scale ICs, only the MOSFET will be reviewed in this discussion. In the late 1960s, the semiconductor industry emerged from the era of wet processing, contact printing, and negative resist at approximately 10 mm minimum gate lengths to face considerable problems related to particulate reduction, dry processing, and projection printing. Positive resist overcame the resist-swelling problem and provided improved resolution, but at the cost of particle generation caused by brittle resist and railed wafer handling equipment in use at that time. Whole wafer projection printing improved the resolution and yield, but required the use of larger wafers to offset the additional capital cost. Dry processing was the banner developmental thrust of the period. Plasma processing, initially conducted in a pancake reactor between opposing electrodes dramatically increased yield, but required a trained artisan to achieve uniformity and throughput. Sputter metal deposition replaced evaporation that had earlier produced substrate stress voiding problems. Wafer size was increased to offset the cost of the more sophisticated and expensive process equipment. Dynamic random access memory factories were the workhorses to develop and prove out the next technology generation. The MOSFET began to emerge in the 1970s as the device technology for VLSI, although large-scale integration (LSI) bipolar technology persisted longer than many forecast. In the early 1980s, Japanese semiconductor manufacturers seized manufacturing technology leadership with major capital commitments, dramatically increasing manufacturing yield and factory efficiency, to capture a major share of the Dynamic random access memories (DRAM) market. Quality became a major issue when it was reported that quality levels of Japanese memories were consistently and substantially better than American manufacturers. As the cost of manufacturing equipment development escalated, a transition began with the emergence of dedicated manufacturing equipment companies, reducing the value of proprietary process development and enhancing the value of product definition and circuit design. Major semiconductor companies initially pressured these equipment vendors to "customize" each production tool to their proprietary specifications, inhibiting reduced costs of capital equipment. Japan became a major supplier of semiconductor manufacturing equipment, further exacerbating problems for the U.S. semiconductor industry. This scenario produced a strategic inflection point in the IC production: U.S. vendors of DRAM suffered financial losses and many ultimately exited the mass memory market. This situation spawned cooperation among the major U.S. semiconductor manufacturers, resulting in the establishment of the Semiconductor Research Corp. (SRC) in 1981 and of SEMATECH in 1988. Both of these pursued the concept of industrial collaboration in semiconductor research and the concept of equipment "cost of ownership", leading to significant collaboration with IC manufacturers and equipment vendors. Wafer size was again increased to reduce the cost of IC manufacturing. Meanwhile, the relentless march of the technology to smaller feature size continued. This was made possible by stepand-repeat projection printing, reduced generation of particulates and single wafer processing replacing many batch processing steps. Microprocessor technology emerged with dynamic memory as a separately addressed technology requirement. Subsequently, the microprocessor manufacturing technology led the race toward smaller device structures and higher complexity on the chip. Dynamic memory continues to advance with smaller memory cell size and ever increasing memory size. Manufacturing equipment automation, cleanliness (for particle reduction) and efficient factory management through cost of ownership reductions have become the overriding issues to be addressed. Yield was increased in the 1980s and 1990s three- and fourfold to the levels unheard of in the early years of IC manufacturing. The collaborative work of SEMATECH and the U.S. semiconductor industry led to an initial "roadmap" of semiconductor technology in 1992 and to the subsequent revisions approximately every 2 years. Significantly aided by SRC and SEMATECH, the U.S. regained the technology and market leadership by the early 2000s in the world semiconductor markets. Since the 1990s, enhanced collaboration among semiconductor companies has occurred to continually recognize and address technology problems associated with the continuing decrease in device feature size. Old issues have persisted and many new ones have arisen. Among the most important issues are: (1)
Introduction to Semiconductor Devices
the increasing capital cost of manufacturing plants, (2) the increased difficulty of lithographic processes as feature sizes decrease, (3) the increasing cross-talk and capacitive loading on-chip as frequency of operation is increased, (4) power dissipation problems, (5) fundamental device limits as feature sizes approach the nanometer range, and (6) the need for enhanced metrology and test equipment. In addition, system and circuit design have presented additional sets of problems that have been separately addressed by a computer-aided design (CAD) industry that arose in a similar fashion to the manufacturing equipment industry. Today at device feature sizes below 50 nm, the semiconductor industry faces unprecedented problems with the task of continuing affordable feature size scaling with the continued improvement of the manufacturing processes. As will be subsequently discussed, fundamental device scaling issues have changed at around the 100–50 nm feature size and many new materials and processes are being required to continue scaling to the ultimate limits imposed by semiconductor device physics. Key areas for advancement of the MOSFET include advanced gate dielectrics, gate contacts, source/drain structures and contacts to the source/drain, and the possible replacement of bulk CMOS with silicon on insulator (SOI) CMOS or eventually with more complex three-dimensional device structures that might perform improved circuit functions. To implement these new materials and smaller device dimensions, new manufacturing methods and equipment will be required with tighter tolerances, lower manufacturing cost of ownership, and increased process control. Improved predictability from improved technology computer-aided design (TCAD) is necessary to avoid the expense of process development on the manufacturing line. Thus, the battle continues to ever increase device density and lower costs through smaller device dimensions as the infusion of semiconductor devices continues into a still rapidly growing electronics market.
Overview of MOS Device Characteristics
The MOSFET, is the predominant semiconductor device, in large-scale ICs. The basic physics behind the device can be understood with reference to Figure 1.1, which shows a cross-section of the basic components of an n-channel device. In the MOS device, a voltage applied to the gate (VG in Figure 1.1) controls the current flow between the drain and the source. The physical mechanism of control is through controlling the mobile charge density of a channel of electrons near the interface between the silicon and an insulator. The gate-to-semiconductor structure acts in many ways like a capacitor with the channel charge controlled by the gate-to-source voltage. One difference with a simple capacitor is the existence of a threshold voltage VT, which is required at the gate to establish the onset of a conductive channel. This is due to the background doping density of the substrate, which for an n-channel device as shown is of opposite conductivity type or p-type. The applied gate voltage must establish a depletion layer of some width with an accompanying voltage before the conductive channel of electrons, begins to dominate the capacitor charge. A typical capacitance–voltage characteristic for an n-MOS transistor is shown in Figure 1.2 for the case of source and drain tied together. For voltages less than VT in the figure, only a depletion region (with positive charge density) exists or an accumulation layer of holes (positive charge) exists for a large negative gate voltage (with negative gate charge). The minimum in the capacitance corresponds to a maximum value of the depletion layer established in the semiconductor substrate. The width of this maximum depletion layer can be expressed as:
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 43si kT lnðNa =ni Þ Wdm Z q2 Na
ð1:1Þ
where Na is the acceptor doping density in the semiconductor and ni is the intrinsic carrier density. This also occurs theoretically when the surface potential has achieved the value:
Handbook of Semiconductor Manufacturing Technology Gate, VG < VT
Drain, VD > 1 ID ~ 0
Depletion region p type
(a) "off" state, VG < VT, no channel exists
Source, VS = 0
Gate, VG > VT
Drain, VD > 0 ID = f(VG,VD)
p type
Depletion region
(b) "on" state, VG > VT, conductive channel exists
FIGURE 1.1 Schematic of basic n-channel metal oxide semiconductor field effect transistor (MOSFET). (a) In "off " state, (b) In "on" state.
js Z 2ðkT=qÞlnðNa =ni Þ Z 2fB
The rapidly increasing capacitance curve for voltages above VT is indicative of the rapid establishment of an inversion layer above the depletion layer, which in this case, is a conductive channel of electrons. The heavily doped nC source/drain regions shown in Figure 1.1 are used to make "ohmic" contact to the conductive channel so that a voltage difference between the source and the drain will result in current flow from the positive voltage at the drain terminal to the negative voltage at the source. In the "off " stage as illustrated in Figure 1.1A, the drain current is very small (ideally zero) and in the "on" state as illustrated in Figure 1.1B, the drain current is a function of both VG and VD. The larger the gate voltage, the larger will be the density of conduction channel electrons and the larger will be the device drain current. Ideally, for gate voltages significantly above the threshold voltage, the gate-to-channel looks
C /COX
Surface accumulation
Inversion – conductive channel established
VT Gate voltage (V)
Gate C–V curve for MOSFET with drain and source at same voltage.
like a capacitor of dielectric thickness equal to the gate oxide thickness and the capacitance approaches a constant as seen by the curve in Figure 1.2 for large positive gate voltages. A typical graph of ID vs. VD for several gate voltages is shown in Figure 1.3. This is for a long-channel device that shows little of the "short-channel" effects to be subsequently discussed. The I–V characteristic exhibits three distinct regions of operation: (1) cutoff or subthreshold, where VG!VT, (2) the triode region, where VD!VGKVT, and (3) the saturation region, where VDOVGKVT and the current is approximately independent of drain voltage as shown in Figure 1.3 for large drain voltages. Ideally in the subthreshold region the current would be zero, but the conductive channel does not go abruptly to zero at the threshold voltage, so an exponentially decreasing current exists in the subthreshold region due to an exponentially decreasing inversion charge density. This is best illustrated by the typical log plot of
0.00020 VGS = 1.2 V
Leff = 9.97 μm W = 10 μm 0.00015
Id (A)
1.0 V 0.00010 0.8 V 0.00005
0.00000 0.0
0.4 V 0.2 V 1.2
Vds (V)
FIGURE 1.3 Typical ID –VD characteristic for long n-channel metal oxide semiconductor field effect transistor at constant gate voltages.
10−4 VD = 2.0V
Subthreshold region
10−5
VD = 0.25V
10−6 10−7
Triode and saturation region
10–8 10−9 10–10 −0.50
VG (V)
Typical ID –VG MOSFET characteristic in the subthreshold region.
ID vs. VG at two drain voltages as shown in Figure 1.4. As can be seen in the figure, the current is approximately linear on the log plot over the voltage region below the threshold voltage. The standard first-order model for MOSFET terminal current is the set of equations [1]:
8 ðaÞ Subthreshold region > > > < ID Z ðbÞ Triode region > > > : ðcÞ Saturation region
Io expðKqðVT KVG Þ=mkTÞ
for VG ! VT
mn Cox ðW=LÞðVG KVT KVD =2ÞVD VD ! VG KVT mn Cox ðW=2LÞðVG KVT Þ2
for VG O VT and
for VG O VT and VD O VG KVT ð1:3Þ
These are approximate equations that help to define the three major regions of operation as (a) subthreshold region, (b) triode region (or linear region for small values of VD), and (c) saturation region. The equation for the subthreshold region must be matched to the conduction region equation in a manner such that the value and first derivative of the current are continuous. The equations are used here to illustrate the major dependences on the device parameters. The device and structural dependences occur through the effective channel length L, the channel width W, the channel mobility mn, and the inversion layer capacitance Cox. An additional parameter frequently used to characterize the subthreshold region is the current slope factor:
S Z mðkT=qÞlnð10Þ xðkT=qÞlnð10Þð1 C 3si tox =3ox Wdm Þ
In this equation, a model for the ideality factor m is also given in terms of the oxide thickness and the maximum depletion layer width. This value is frequently compared to an ideal subthreshold slope factor of (kT/q) ln(10)Z60 mV/decade at room temperature. For short-channel devices, additional parameters are needed to provide even a first-order description of device current. A typical set of current characteristics for a short-channel MOSFET are shown in Figure 1.5. In this particular case, it is the characteristic of an n-channel device with an oxide thickness of approximately 1.7 nm, a channel length of approximately 97 nm, and a channel width of 10 mm. What constitutes a short-channel device is not readily defined simply in terms of the effective channel length. As devices have been scaled to ever smaller dimensions over the years, the concept of a short-channel
Leff = 0.097 μm W = 10 μm
Vgs = 1.2V
0.004 0.6 V 0.002 0.000 0.0
0.4 V 0.2
Typical ID –VD characteristic for short n-channel MOSFET at constant gate voltages.
device has been pushed to ever smaller dimensions. This scaling is discussed in a subsequent section. However, devices that can be characterized as short-channel devices exhibit certain important deviations from the ideal device equations as described by the set of Equation 1.3. One important feature is the lack of a clear current saturation region for large drain voltages as can be seen in comparing Figure 1.3 and Figure 1.5. This lack of ideal current saturation is known to be due primarily to two physical effects. One is the channel-length modulation, whereby an increase in drain voltage reduces the effective channel length. As can be seen from Equation 1.3, a decrease in L will cause a resulting increase in the device current even for the equation describing the current saturation region. The second effect is a dependence of device threshold voltage on drain voltage with the threshold voltage decreasing with increasing drain voltage. Again in Equation 1.3, we can see that this will result in an increasing device current. This decrease in threshold voltage is due to an incomplete shielding of the channel from the drain voltage and depends strongly on the three parameters: oxide thickness, maximum depletion layer thickness, and effective channel length. This is a two-dimensional potential feedback effect from the drain to the channel. This is discussed in more detail in a subsequent section, but for a typical drain current characteristic, is typically described by a so called drain-induced barrier lowering (DIBL) factor. The channel-length modulation effect is frequently included in the basic device model by the use of a factor (1ClnVD), which is used to multiply Equation 1.3 in the triode and saturation regions. A first order model for DIBL can be taken as DVTZsVD in all regions of operation. These are the two most important modifications of the basic device equations needed for short-channel effects. Both of these modifications will result in a finite slope on the I–V characteristic at the large drain voltages in the classical current saturation region. Most of the finite slope seen in Figure 1.5 can be accounted for by a DIBL effect (with sx0.22). A key factor in the dominance of MOSFETs is the ability to produce complementary n- and p-channel transistors with similar device characteristics. The figures given so far have been for n-channel devices in which a positive gate voltage is required to establish a conductive channel and current flows from the most positive of the source/drain contacts to the most negative. A discussion of the p-channel devices would be essentially the same, except for the reversal of all operating voltages and current directions. A negative voltage at the gate first depletes an n-type substrate and then establishes a conductive channel of holes (positive charge) after the threshold voltage is exceeded. Positive current can then flows from the most positive of the source/drain contacts to the most negative with the most negative contact identified as the drain contact. Figures showing the I–V characteristics of the p-channel devices would be very similar to Figure 1.3 through Figure 1.5 with the current and voltage directions reversed. One major
difference should, however, be noted and this relates to the mobility parameter (which would be mp in Equation 1.3), which is about a factor of 2.0–2.5 times smaller for holes than for electrons. However, the current supplied by a p-MOS can be equal to that of an n-MOS by increasing the (W/L) ratio for the p-MOS to compensate for the lower hole mobility. It is frequently assumed that (W/L) for the p-MOS devices is approximately 2.5 times that of the n-MOS devices, although logic gates may require other ratios of the device dimensions in order to achieve desired switching speeds.
MOSFET Device Scaling
The primary driving factor behind the exponential increase over the past 40 years of IC functionality, commonly referred to as Moore's law, has been the ability to continually scale MOS devices to ever smaller dimensions. This is illustrated in Figure 1.6, which shows a series of experimental devices (production and experimental devices) spanning the major technology nodes from 130 to 32 nm, and the expected production times from 2001 to 2009 [2]. Figure 1.7 shows a cross-sectional drawing of a typical MOS device drawn approximately to scale in both the vertical and horizontal dimensions for devices in the range of the 130- to 32-nm nodes. Critical dimensions on the figure are the physical gate length LP, the gate oxide thickness tox, and the effective channel length Leff (same as L in Equation 1.3). Of particular note is the very thin nature of the gate oxide when compared with other device dimensions such as the effective channel length. This structure shows a typical channel contacting structure consisting of the source/drain extension junction (depth XJ) and a deeper drain contact junction (depth XJC). Devices typically have a silicide layer extending nearly to the edge of the drain extension layer and a metal source/ drain and gate contact layer, which are not shown in this simplified drawing. These layers can be seen in the actual cross-sectional views of Figure 1.6. Also not shown in Figure 1.7 are sub-channel doping layers under the gate in the region of Leff for controlling threshold voltage, punch-through and DIBL. These are discussed in more detail later.
Accelerated scaling of planar transistors 130-nm node
90-nm node 70-nm length (production in 2001)
65-nm node
45-nm node 50-nm length (production in 2003) 30-nm prototype 32-nm node (production in 2005) 20-nm prototype (production in 2007)
15-nm prototype (production in 2009)
FIGURE 1.6 Illustration of device scaling from the 130-nm node to the 32-nm node. (From Marcyk, G., INTEL Corp., ftp://download.intel.com/technology/silicon/Marcyk_tri_gate_0902.pdf)
Spacer tsw
tgate
Gate contact
Drain extension
XJC
Drain contact
Substrate body
FIGURE 1.7 Metal oxide semiconductor device cross-section drawn approximately to scale in vertical and horizontal directions.
Since first published in 1992, the International Technology Roadmap for Semiconductors (ITRS) [3] has been the benchmark document for guiding the scaling of MOS devices. Each edition of this document has projected future scaling trends and future device and IC system performance for the next 15 years. The 2004 update [4] projects development to the year 2019 when there is a considerable concern that the end of any practical CMOS scaling will have been reached due to fundamental material and device limits. Several of these limits and problems will be subsequently discussed. Figure 1.8 shows some important projected scaling results from both the 1997 and the 2004 ITRS documents. The figure shows several device parameters in terms of major technology generations and the year (or expected year) of its 1000 Open data points — 1997 ITRS Closed data points — 2004 ITRS LTN
LL LP
10 tox = EOT
tciv = Inversion CET
Supply voltagedd Golden era of scaling
VDD (V)
Dimension (nm)
LTN = Technology node LL = Printed gate length LP = Physical gate length XJ = Junction depth at channel tciv = Cap. equivalent thickness
tox = EOT
VDD
EOT = Equivalent oxide thickness
250 180 130 90 65 45 32 (1997) (1999) (2001) (2004) (2007) (2010) (2013)
22 16 (2016) (2019)
Technology generation (nm) and year
FIGURE 1.8 devices.
Dimensions of several important metal oxide semiconductor device parameters as projected for scaled
introduction into production. The technology generation nodes need some discussion. In the 1997 ITRS, the nodes were listed as 250, 180, 130, 100, 70, and 50 nm. In the 2004 ITRS, the last three of these nodes have been changed to 90, 65, and 45 and the additional nodes of 32, 22, and 16 are included. One of the intents of the major technology nodes is to identify device scaling that will result in an increase in device packing density by a factor of 2 (a doubling of device density each generation along Moore's curve). Ideally, pffiffiffi then each technology generation represents a shrink in linear device dimension by a factor of 1= 2 Z 0:707. With this in mind the 90-nm dimension is considerably closer to an ideal shrink than was the original 100 nm specification. Thus, the 1997 data points are plotted using the 2004 node identifications to be consistent with the 2004 document. Also to be noted from the expected dates of introduction, the time between the major nodes is not a constant time interval. For the 250, 180, and 130 nodes, the time interval is only 2 years, while for the remaining nodes the projected time interval is 3 years. This indicates some of the expected difficulty in achieving the expected shrinks beyond the 130 nm node. Several lengths are shown in the graph from the 2004 ITRS. First, the upper curve labeled LTN corresponds to the major technology node, which is identified with the expected half-pitch of densely packed DRAMS circuits. For the critical MOS device dimensions, especially of "high performance" (HP) logic devices, other critical dimensions are defined as LL, the lithographically printed gate length; and LP, the physical gate length after etching of the gate contact material. Also shown in the figure are projections for the depth of the extension junction used to contact the conductive channel. As can be seen by the approximate straight lines on the log scale of Figure 1.8, all of these dimensions are projected to scale as some constant fraction of the technology node dimension. It should be noted that, the 2004 ITRS did not distinguish between the technology node and the physical device dimension, so there was some confusion about these dimensions in the earlier ITRS documents. It should be noted that, the 2004 ITRS develops different scenario for HP logic circuits and for low power circuits. While the line width parameters are common for different applications, other parameters such as dielectric thickness and supply voltage, which are included in Figure 1.8 are application dependent. In general, parameters discussed in this chapter are for the HP logic circuits, since these applications place the most severe constraints on the device performance and will probably be the most difficult one to achieve with scaled devices. Other very key device parameters are the gate dielectric thickness and the logic level power supply voltage. First, considering the supply voltage VDD, in the 2004 ITRS, it was projected to decrease to about 0.5 V by the 45-nm node or by the end of the 2004 projected roadmap. The 2004 ITRS provides a very different scenario with the 45-nm node having a supply voltage of 1.0 V and the value decreasing to 0.7 V at the 16-nm node or the end of the roadmap. This is a major rethinking of the voltage limits for scaled CMOS devices. Along with this has been a major change in the projected decrease in dielectric thickness. In the 2004 ITRS, the oxide thickness was projected to reach about 0.9 nm (actually listed as !1 nm) at the 45-nm node. Actually the 2004 ITRS projects even thinner tox or equivalent oxide thickness (EOT) values than did the 1997 ITRS. In this case, EOT in recognition that the gate dielectric will most likely not be a pure oxide, but some enhanced oxide for reduced gate leakage. This is explored in more detail in a subsequent section. An additional parameter introduced in the 2004 ITRS is the "equivalent electrical thickness in inversion" (tciv) as also plotted in Figure 1.8. This is also labeled "inversion CET" in Figure 1.8 for inversion capacitance equivalent thickness (CET). It should be noted that, the supply voltage and oxide thickness values used here are for so called HP devices such as would be used in the state-of-the-art microprocessors. Other MOS devices needed for low power applications would not be scaled as aggressively, but would be optimized for other considerations. The HP device scaling is emphasized here as it typically represents the most severe scaling constraint in terms of material properties and device dimensions. A brief discussion is needed for the inversion CET capacitance as this is a critical parameter for MOS device operation. Referring back to Figure 1.1, the conductive channel induced by the gate voltage into the semiconductor substrate acts much like the plate of a capacitor with the gate electrode as one plate and the conductive channel as the other electrode. Ideally, the capacitance of the gate-to-channel is that of a
capacitor with dielectric constant equal to that of the gate insulator and thickness of the gate insulator tox or EOT. For such an ideal case, the CETwould equal the EOT. However, this is not quite correct, especially when the dimensions get very small. First, if the gate is polysilicon with a finite doping density, there is a finite depletion layer that exists in the polysilicon gate. This essentially adds to the equivalent dielectric thickness of the gate-to-channel capacitor structure. The ITRS projections for the ultimately scaled devices assume that this additional thickness will be eliminated by the use of appropriate metal gates. In addition, the charge in the semiconductor is not exactly a sheet charge, but exhibits some finite thickness. Even in the classical model of the surface charge the conductive channel has some finite width. An in-depth analysis of the conductive channel must consider quantum mechanical confinement effects of the carriers within a surface potential well and this results in an additional thickness of the conductive channel [5–7]. The net result is that, the charge centroid of the conductive channel is some distance below the dielectric– semiconductor interface. This adds an additional thickness to the oxide, which must be included in an expression describing the charge–voltage relationship for the MOS gate. This additional thickness is estimated as 0.4 nm in the ITRS tables. This additional 0.4-nm value accounts for the difference in the EOT and inversion CET values of Figure 1.8. In terms of the gate capacitance characteristic, this effect reduces the maximum capacitance values in either accumulation or inversion as illustrated in Figure 1.9. This shows several theoretical C–V curves for a 100 nm!100 nm capacitor on a p-type substrate and for a 1-nm thick oxide. Several curves are shown for a substrate doping density of 4!1018/cm3 (This value is used in order to give a threshold voltage of a few tenths of a volt). Curve (a) is the ideal C–V curve for a 1-nm oxide assuming an ideal gate contact, such as a metal and ignoring quantum confinement channel effects. Curve (b) is for a metal gate and including quantum channel effects. Finally, curves (c) and (d) are for nC polysilicon gates doped to 2!1020/cm3 and 1!1020/cm3, respectively and including quantum effects. Comparing curves (a) and (b), one sees that the major influence of the channel quantum effects is to increase the voltage for channel inversion (or threshold voltage) and to lower the peak capacitance in both accumulation and inversion. As previously discussed and reported [8,9], these are due to the shift of the channel charge centroid away from the surface due to quantum confinement effects. These make the capacitor structure appear to have a larger effective thickness and lower capacitance in the accumulation region where the conductive channel is formed. This increased thickness is represented by the tciv values in Figure 1.8 and as previously stated, this increase is estimated in the ITRS as about 0.4-nm independent of the physical oxide thickness. This accounts for the difference in the tox and tciv curves in Figure 1.8. 400 350
(a) Ideal, metal gate, no QM
Capacitance (pF)
200 150 100 50 0 −3
(a) Metal gate, QM
(d) 4×1018/cm3
NB = tox = 1nm (c) Poly, 2×1020/cm3, QM (d) Poly, 1×1020/cm3, QM −2
0 −1 Gate voltage (V)
Theoretical C–V for a thin gate dielectric, including QM effects and poly depletion effects.
Curves (c) and (d) in Figure 1.9 illustrate the further reduction in inversion layer capacitance due to the use of a polysilicon gate. In the inversion region (large positive gate voltages), the polysilicon has a finite depletion layer, which adds an additional effective thickness to that of the oxide and quantum confinement effects. The capacitance values represent induced charge per unit voltage, so the differences between curves (b) and (c) or (d) represent reductions in transconductance that would occur due to polysilicon depletion. If the polysilicon doping density could be increased without limit, the polysilicon depletion effect could be minimized. However, from literature reports, it appears that it will be very difficult to get electronically active doping densities much above 1020/cm3 for nC polysilicon and above the mid to upper 1019/cm3 for pC polysilicon. For these doping densities, the polysilicon depletion represents a significant reduction in gate capacitance for a thin EOT dielectric. In terms of MOS device performance, the important gate thickness related parameters in Figure 1.8 are the supply voltage, which represents maximum gate-to-source voltage and the inversion capacitance equivalent thickness, tciv. A first order approximation for the Cox parameter in Equation 1.3 is:
Cox Z 3ox =tciv Z Capacitance=unit area
This capacitance multiplied by VGKVT will then give the maximum channel induced charge per unit area. The possibility of using advanced dielectrics, such as high-k dielectrics in place of silicon dioxide is discussed in a subsequent section. One important conclusion that can be gleamed from Figure 1.8 is that the projected scaling relationships have changed significantly from the 1997 to the 2004 ITRS document. The 1997 projections were essentially the case of "constant field" scaling, where all device dimensions and the voltage were projected to scale with the same factor as the technology node and the physical gate length. This type of device scaling had (in 1997) been practiced for many technology generations and can be said to constitute the "golden era of scaling" as identified in the figure for technology nodes above the 90-nm node. During this golden era of scaling, it was relatively easy (in retrospect) to scale MOS devices with relatively small changes in the device structure from generation to generation. The relative dimensions of MOS devices were close to those shown with the device cross-section illustrated in Figure 1.7. However, as Figure 1.8 shows scaling projections beyond the 90-nm node represent a significant departure from that of the golden era of scaling and away from that of constant field scaling. As subsequently discussed, this is due to the fact that several fundamental semiconductor and device limits are being approached and scaling beyond the 90-nm node becomes considerably more difficult than during the golden era of scaling. Figure 1.10 shows the projected scaling of two other MOS device dimensions, the gate contact thickness and the spacer thickness. Overall, these are seen to scale with approximately the same scaling factor as the technology node as projected by both the 1997 and 2004 ITRS documents.
An obvious advantage of device scaling is the ability to pack more and more devices and electronic functionality within the same given silicon chip area. This has been the major driving force to propel the electronics industry along Moore's curve. Along with the increased packing density is of course, a desire to continue to improve the performance of the resulting circuits in terms of operating speed as well as maintaining some control over the power dissipation. Thus, it is important to understand how device scaling and in particular, how the ITRS scaling scenario affects fundamental MOS device performance. For digital circuits, three of the most important device parameters are: a. Maximum saturated drain current (Idsat) when VGZVDZVDD. b. Off-state drain leakage current (Ioff ) when VGZ0, VDZVDD. c. Device capacitances.
100 tgate = Gate thickness 10
tw = Spacer thickness
1 Open data points — 1997 ITRS Closed data points — 2003 ITRS 0.1
Technology generation (nm)
Projected scaling of gate and spacer thickness.
In turn, the saturated drain current depends on further device parameters, such as threshold voltage and DIBL, which then become important device parameters. A frequently used first order model for saturated drain current is [1]
Idsat Z Wvsat Cox ðVG KVT KVdsat Þ Idsat Z
Wmn Cox 1 ðV KVT K Vdsat ÞVdsat Leff ð1 C Vdsat mn =vsat Leff Þ G 2
where mn is the average channel mobility and vsat is the high field saturated drift velocity of the channel carriers (electrons or holes). The first equation comes from looking at the saturated velocity equation for current near the drain, while the second equation comes from integrating the channel potential equation along the channel. While these are first order model equations, they do include much of the major device physics of transport along the surface channel. Both of these equations must be satisfied at the drain saturation voltage from which we can evaluate
L v Vdsat Z eff sat mn
"sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi # 2ðVG KVT Þmn 1C K1 Leff vsat
For maximum drive current, the gate voltage is set to the power supply voltage. Using this expression in either of Equation 1.6 can then give the maximum saturated drain current. If we define the following quantities
ðVG KVT Þmn ; Leff vsat
Vdsat ðVG KVT Þ
then the saturated drain current can be expressed as
Idsat Z Wvsat Cox ðVG KVT ÞFI ðXÞ;
where FI ðXÞ Z 1KX and X Z
i 1 hpffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1 C 2Y K1 Y
An upper limit on FI(X) is FI(X)/1 as carrier velocity saturation becomes the dominant factor limiting the saturation current. The surface-channel mobility mn is not exactly a constant as assumed in deriving this set of device equations, but is known to depend on the effective surface electric field [10], which can be expressed as
Eeff x
Vgap Cox VG C VT C 2 KfB 23Si 2
ð1:10Þ
where fB has the usual meaning as in Equation 1.2 and Vgap is a voltage corresponding to the silicon bandgap (1.1 V). Under most conditions (Vgap/2–fB) can be neglected and
Cox 3 ðV C VT Þ Z ox ðVG C VT Þ xðVG C VT Þ=6tciv 23Si G 23Si tciv
The last expression has previously been used by Hu [11] as an approximation to the effective surface field. From these first order device current equations, there are three "field" terms that are of importance: (a) (VG–VT)/Leff, (b) (VGCVT)/6tciv, and (c) (VG–VT)/tciv The first field is a lateral electric field along the channel, while the second term is the effective field in the semiconductor at the surface, and the last term is the excess electric field across the gate dielectric, which is responsible for the channel charge. This is somewhat less than the oxide electric field, which can be some 20%–25% larger due to the depletion layer charge needed before establishing the conductive channel. In terms of the MOS device performance, a critical parameter is the effective channel length, Leff. However, this is not a parameter specified by the ITRS projected scaling values. This value is critically dependent on the contacting junction formation techniques and not just on the physical line width. In order to make good ohmic contact to the channel, the effective channel length must be somewhat less than the physical gate length, so that the contacting layer extends under the gate oxide for some small distance. In order to carry forward with the analysis here, some value is needed for the effective channel length. For use here, this has been assumed to be 0.7 times the physical channel length. This essentially means that the effective channel length is assumed to be one technology generation ahead of the physical gate length and to remain a fixed percentage of the physical gate length for each technology generation. Manufacturing problems associated with achieving all the ITRS parameters are covered in subsequent sections. Figure 1.11 shows plots of these three fields according to the ITRS scaling rules for each major technology node. The open data points are obtained from the 1997 roadmap values, while the open data points are from the projected scaling in the 2004 roadmap. First, we note that the three fields are approximately constant using the 1997 parameters. This is again indicative of the essentially constant field scaling during the golden age of scaling. For the 2004 scaling projections, one sees that the vertical fields, Ec and Eeff in the figure are approximately constant for projected nodes of 65 nm and below. There is a projected increase in these fields by about a factor of 2 in the 2004 ITRS values as compared with the 1997 ITRS values. This increase will have two effects: (1) a possible increase in gate leakage due to the increased gate field and (2) a decrease in average surface carrier mobility due to the increased effective surface field. The major change reflected in the 2004 projections is the greatly changed functional nature of the lateral MOS device field, Elat in Figure 1.11. This is due to the reduced scaling of supply voltage relative to the scaling of the effective channel length. In terms of MOS device operation, this will enhance velocity saturation effects as the point along the channel where velocity saturation occurs will occur closer to the source contact with the increased average lateral field. In terms of the device current of Equation 1.9, this will make the FI(X) factor closer to unity. In summary, for the device electric fields, the 2004 projected scaling is essentially a constant field scaling for the vertical MOSFET fields and an ever increasing lateral device average field.
107 Ec = (VDD – VT)/tciv
Field (V/cm)
Open data points — 1997 ITRS Closed data points — 2004 ITRS Eeff = (VDD +VT)/6tciv
Note large increase in 2004 ITRS Elat = (VDD – VT)/Leff
Golden era of scaling 250 180 130 90 65 45 32 22 16 (1997) (1999) (2001) (2004) (2007) (2010) (2013) (2016) (2019) Technology generation (nm) and year
Projected scaling of various device field parameters.
To complete the model parameters, a value of mobility and saturation velocity is needed. For the carrier saturation velocity, the value of 1!107 is frequently used for long-channel devices. There may be some tendency for this value to increase at small device dimensions because of velocity overshoot effects. However, for an initial calculation this will not be considered. The electron mobility is strongly dependent on the effective surface electric field because of surface scatterings. At a peak effective surface field of 1!105 V/cm, the surface mobility of electrons varies from approximately 250 cm2/V s to approximately 320 cm2/V s [10]. So for, the 1997 scaling an average value of 280 cm2/V s can be used. For the 2004 scaling projections, the peak surface effective field is expected to increase to about 2!105 V/cm. Unfortunately, this increase in effective surface field will result in a reduction in surface mobility by about a factor of 2 (in this region of field, the surface mobility is approximately inversely proportional to the surface field). In order to illustrate the separate effects of the lateral field and the reduced surface mobility, results will be shown for the 2004 parameters using both 280 and 140 cm2/V s. The consequences of these projected scaling rules can be seen with respect to the first order device parameters in Figure 1.12. For the 1997 constant field scaling, the parameters are essentially constant for each technology generation as expected. For the 2004 scaling, the drain saturation voltage is seen to be an ever decreasing function of the technology generation, being about 0.33 times the excess voltage above threshold for the 90-nm node and decreasing to about 0.20 times the excess voltage for the 16-nm node. This is a direct consequence of the increased lateral field as seen in Figure 1.11. This in turn causes an increase in the FI device equation factor as seen in the figure. This has a simple physical interpretation of representing the fraction of the Vsat velocity that the carriers have achieved when current saturation occurs. Because of the higher lateral fields, the figure shows that this factor slowly increases with the shrinking of device dimensions. The final important parameter is the device current or rather the projected current per unit length of gate. This is shown for the first order model and the above parameters in Figure 1.13. For the 1997 constant field parameters, this value is constant at about 760 mA/mm (or mA/mm using the ITRS notation). For the 2004 projected scaling parameters, the maximum saturated drive current is projected to increase somewhat from the 90-nm node to the 45-nm node, but then stay relatively constant to the 16-nm node. The model values are close to the ITRS desired roadmap values to the 45-nm node, but then
Handbook of Semiconductor Manufacturing Technology 1.00
Device factors ( )
Open data points — 1997 ITRS Closed data points — 2004 ITRS
mn = 280 cm2/Vs mn = 140 cm2/Vs
Vdsat /(VDD – VT)
0.20 VT/VDD 0.00
250 180 130 (1997) (1999) (2001)
90 65 45 32 22 16 (2004) (2007) (2010) (2013) (2016) (2019)
Projected scaling of various metal oxide semiconductor device current density factors.
fall below the ITRS projected values. By comparing the saturated current values to the model equations, one can see that most of the projected increase in drive current comes about from the increase in the Cox(VG–VT) value or in the increase in the vertical electric field seen in the effective and oxide fields in Figure 1.11. A small amount of the increase comes from the increased lateral field because of the upper limit of the carrier saturation velocity. 2500 Open data points — 1997 ITRS Closed data points — 2004 ITRS
2004 ITRS roadmap values
Idsat (μA/μm) or (A/m)
Simple model predictions mn = 280 cm2/ V s
mn = 140 cm2/ V s
Simple model predictions
250 180 130 90 65 45 32 22 16 (1997) (1999) (2001) (2004) (2007) (2010) (2013) (2016) (2019) Technology generation (nm) and year
Projected scaling of n-metal oxide semiconductor saturated drain current at maximum gate voltage.
2000 Open data points — 1997 ITRS Closed data points — 2004 ITRS
Idsat (μA /μm) or (A/m)
1500 Simple model predictions mp = 70 cm2/ V s
mp = 35 cm2/ V s
1000 2004 ITRS roadmap values (50% of nMOS values)
Projected scaling of p-metal oxide semiconductor saturated drain current at maximum gate voltage.
A similar set of calculations can be made for holes, using a surface mobility of approximately 70 and 45 cm2/V s for the 1997 and 2004 parameters, respectively, and using a vsat value of 8.4!106 cm/s. These values give the projected p-channel current values shown in Figure 1.14. In this case, one can again see that there is a considerable increase in the projected saturation current using the 2004 scaling parameters. In this case, the increase comes both from the increased lateral field and from the projected increase in the surface charge density due to the increased surface field with the larger power supply voltage. In this case, the simple model predicts p-channel saturated current values slightly larger than the ITRS projected values. The relative enhancement of the p-channel current with respect to the n-channel current arises in the simple model, because the ratio of saturated velocities for holes-to-electrons is larger than the corresponding ratio of low field mobilities. The increased lateral field, with scaling, pushes both types of devices closer to the velocity saturation limit, hence increasing the p-channel saturation current by a larger factor than the n-channel saturation current. The relative ratio of hole-to-electron current remains essentially constant for constant field scaling in both the vertical and lateral dimensions. The simple model neglects at least two important factors that must be considered in any more realistic estimate of current drive. First, the DIBL and channel-length modulation effects cause an increase in current above that predicted by such a first order model. As indicated in Figure 1.5, this can cause a relatively large percentage increase in the available drive current at the supply voltage value. A reasonable enhancement value might be a 25%–30% increase in current. A second neglected factor is the effects of source and drain series resistance. These resistances reduce the current drive by effectively reducing the internally applied gate-to-source voltage. In order to minimize this latter effect, the source/drain contacts must be very carefully constructed and this becomes more difficult as device dimensions shrink. Typical source/drain resistances can easily reduce the available current drive by 25%–30%. Thus, these two neglected factors tend to somewhat offset each other with one increasing current drive and the other decreasing current drive. For the purpose here, it will be simply assumed that these effects tend to offset each other and that the simple model gives reasonably good first order approximations to the available current drive at the projected ITRS scaling. In any case, the user should not place high confidence in the exact projected values, but only accept them to within some 25%–30% of accuracy. Difficulties in
achieving the scaled parameters and possible enhancements are discussed in a subsequent section on manufacturing issues. Device current drive is important because it relates to other important parameters, such as switching speed or logic gate delay, and power dissipation. In terms of logic gate delay, the important parameters can be obtained from the simple equation
Idsat Z CL DVL =Dt
where CL is the gate load capacitance and DVL is the change in load voltage in time Dt. From this, we can calculate a gate delay as
td Z CL DVL =Idsat
This illustrates the importance in saturated drive current in achieving ever smaller gate delays, which can translate into higher system clock frequencies. While the load capacitance is a complex combination of device capacitances and wiring layout capacitances, it is generally agreed that to the first order, the load capacitance is expected to vary directly with the lithography dimension or with the technology generation. In the golden era of scaling, the saturation current per unit gate length was approximately constant, implying that the saturation current was also varying directly with the technology generation. pffiffiffi Also the logic voltage level was scaling directly with the technology generation. Thus, if we let aðx 2Þ be a scale factor (or perhaps the inverse scale factor) per technology generation, then for constant field scaling
CL f 1=a;
DVL f 1=a;
Idsat f 1=a and
td f ð1=aÞð1=aÞ=ð1=aÞ Z 1=a
The last line is the most important, where the constant field scaling gives a gate delay, which decreases by approximately 0.707 (1/a) per technology generation. This affords a path for the system level clock frequency to increase by about 40% (by a factor aZ1.414) for each technology generation. This has been used by the industry during the golden era of scaling to not only increase the packing density and functionality, but also to rapidly increase the clock frequency of microprocessors by many factors of 2. The projected scaling in the 2004 ITRS makes it considerably more difficult to continue decreasing the gate delay. This arises because the highly desired decrease in logic voltage level has been considerably slowed. A detailed look at the projected scaling of the power supply voltage in Figure 1.8 shows that the decrease has changed to about 15% per technology generation rather than the previous 30% per generation. To a first order approximation then
pffiffiffi DVL f 1= a
In order to maintain a gate delay that then improves in the same manner as for constant field scaling, one must require a slower decrease in saturation drain current than with the technology generation. The required decrease in saturation current is then the same as that of the power supply voltage. If we then use the scaling factors:
pffiffiffi Idsat f 1= a
pffiffiffi td f 1=a but it requires that Idsat =W f a
pffiffiffi DVL f 1= a;
then one finds
This last equation summarizes the important gate delay projections from the 2004 ITRS. The gate delay is projected to continue to decrease directly with the technology generation, but in order to achieve this, the saturated current per gate width must be forced to increase with each technology generation.
The 2004 ITRS clearly states that the proposed scaling scenario is based upon this important assumption. The projected linear increase in saturated current per unit width seen in Figure 1.13 and Figure 1.14 for n- and p-channel devices is a direct consequence of this assumption. Under this scenario, four technology generations require a doubling of the saturated drive current per unit length and this is essentially the projection seen in Figure 1.13 and Figure 1.14 for the ITRS projected values. Another possible scenario would be to accept a device scaling that produces a constant current per unit width and accept a slower decrease in gate delay per technology generation. If one considers keeping the pffiffiffi saturated current per unit gate length constant then this leads to a tdf1= a instead of the relationship of Equation 1.17. In this case, four technology generations would be required to double the clock frequency instead of the two generations with the projected ITRS scaling. Another very important scaling parameter is the power dissipation per gate and the power density or power per unit gate area. Traditionally, power dissipation in CMOS circuits has been dominated by the dynamic switching power because of the very low gate and drain currents in the two stable logic states. Considering only this dynamic power for one gate, this can be expressed as
1 2 f pg Z CL VDD 2 pg C V2 f Z L DD Ag 2Ag
where CL is the load capacitance that is being switched at some frequency f. The first form expresses power per gate, while the second form represents power density or power per unit gate area Ag. While both of these are important, the power density is probably the more important factor as present ICs are close to perceived limits in terms of handling power per unit area. For constant field scaling with the scaling of Equation 1.14 this becomes
pg ð1=aÞð1=aÞ2 f f f f =a Ag ð1=aÞ2
To keep constant power per unit gate area, one can then increase the clock frequency directly with the scaling factor per generation or double the clock frequency with every two technology generations. Of course, one must also consider total chip power, which for increasing chip areas would continue to increase with each generation. However, if power per unit area is the limiting factor, the decreased gate switching speed can be directly employed with the increased system level clock frequencies. Things have now, however, changed with the 2004 ITRS projections due to the slower rate of decrease in supply voltage. The decrease in voltage squared will no longer offset the decreasing area and in fact, both the capacitance and the voltage decrease are needed to offset the decreasing area and one obtains with the 2004 ITRS scaling
pg ð1=aÞð1=aÞ f f ff Ag ð1=aÞ2
The power per unit area is now directly proportional to the clock frequency and any increase in the clock frequency will result in an increased power density! This is an important implication of the slowed voltage scaling of the 2004 ITRS. IC design and performance is no longer in the golden era of scaling that prevailed for many generations before about the 90-nm node. For system applications, one needs to take a little more general interpretation of the clock frequency in the above equations. For a large system not all gates will be operating at any given time and only the active gates contribute to the dynamic power dissipation. Thus, we can expand the interpretation of the
frequency to an equivalent clock frequency with
f Z fclk fact
where the two factors are the clock (clk subscript) frequency and the fraction of gates that are active (act subscript). It is then the product of the system level clock frequency and the fraction of active gates that must remain constant with the 2004 ITRS scaling. Thus, the clock frequency could still be increased by 40% per technology node, provided an additional 40% of the gates were inactive at all times and the average power per gate would not change. These tradeoffs obviously offer many possible alternatives, such as the possibility of doubling the circuit functionality and keeping the same clock frequency at a new technology node. For example, two microprocessors at the same clock frequency could be implemented, instead of increasing the clock frequency and reducing the percentage of active circuits. In addition to the dynamic switching power, static power dissipation is becoming a major design parameter for scaled circuits. The MOS off-state drain leakage current, Id,leak, consists of components due to (1) gate leakage, (2) drain-substrate leakage, and (3) drain-to-source leakage. As covered in more detail later, all of these components tend to increase exponentially with the decreasing device dimensions. How to control these in the manufacturing process is a major challenge. For the purposes of proper circuit operation and power management, these parasitic and undesirable currents must be kept below some upper limit. Static off-state power dissipation can be expressed as
poff Z VDD Id;leak
Limits for the allowable leakage current comes not from the fundamental device limits, but from circuit and system limits on the allowable values of static off power that can be managed in a given IC application. In general, one desires a low value of off-to-on state leakage current. Acceptable past values for MOS devices have been in the range of 1!10K5 to 1!10K4 and acceptable values were not even specified in the 1997 ITRS. Figure 1.15 shows the off-to-on current ratios specified in the 2004 ITRS for the 90- to 22-nm technology nodes. Three curves are shown for (1) HP, (2) low operating power (LOP), and (3) low standby power (LSP). While there is some increase projected in the allowable leakage with scaled devices, we can see that the projected leakage is in the range of 1!10K4, 1!10K5 and 1!10K7 for
Id, leak /Idsat
Low operating power 2004 ITRS Values
10−6 Low standby power
45 32 22 Technology generation (nm)
Projected ratio of allowable offstate leakage current to saturated drain current.
the three applications, respectively. Difficulties in achieving these numbers are further discussed in the manufacturing section. Static power dissipation at the system level is becoming much more of a problem with further scaling of devices and is a major consideration with highly desirable low power applications and especially LSP applications. In terms of the future scaling of off-state power per unit device area, consider the best case scenario, where leakage current remains a constant multiple of saturated device current. In this case and for the 2004 ITRS scaling factors of Equation 1.16, one obtains
pffiffiffi pffiffiffi poff ð1= aÞð1= aÞ f Za Ag ð1=aÞ2
This indicates that the expected off-state power per unit gate area is expected to increase with future generations even with a fixed off-to-on current ratio and will increase even faster with the increased offstate current shown in Figure 1.15. This is another indication that power management is to become more and more of a major technology limiter. Various power-down techniques can perhaps be used to help and manage this problem at the circuit and system level, as there does not appear to be any solution at the basic device level. These various scaling rules can be conveniently summarized in a table, such as Table 1.1. For the most generalized scaling, it is assumed that different scaling could possibly be used with the following parameters: (1) device width and length (aL), (2) oxide thickness (aox), (3) supply voltage (av), (4) saturation current (aI), (5) wiring capacitance (aW), and (6) effective clock frequency (aF). In the case of traditional constant field scaling, all of these parameters have the same value. For the major technology nodes, the length scaling factor is approximately 1.414. The third column in the table summarizes the approximate scaling for the 2004 ITRS, where the supply voltage and oxide thickness scales at approximately half the rate of the technology generation. This table is a convenient summary of the ITRS scaling discussed previously in this section, and summarizes some of the difficulties this presents in regard to control the power density and increase the clock frequency for future ICs.
Technology Scaling Rules for Generalized Scaling, Constant Field Scaling and 2004 ITRS Scaling Rules
Physical Parameter
Device dimensions (L,W) Metal oxide semiconductor (MOS) oxide capacitance thickness Supply voltage Idsat Idsat/W Doping density Wiring length or wiring cap MOS device area Logic gate area Wiring capacitance Logic gate delay (td) Logic clock frequency Gate power dissipation Gate power density Off state current Off state power density
Generalized Scaling
Constant Field Scaling (Golden Era or Scaling)
2004 ITRS Scaling (aLZ1.414 for Each Major Technology Node)
1/aL 1/aox
1/a 1/a
1/aL pffiffiffiffiffi 1= aL
1/av 1/aI 1 a2L =av 4 a2L 1/aW 1=a2L 1=a2W 1/aW aI/(aWav) aF aF =ðaW a2v Þ aF a2L = aW a2v 1/aI a2L =ðav aI Þ1
1/a 1/a 1 a4a2 1/a 1/a2 1/a2 1/a 1/a a 1/a2 1 1/a 1
pffiffiffiffiffi 1= aL pffiffiffiffiffi 1= a pffiffiffiffiffi L aL 2 a3=2 L 4 aL 1/aL 1=a2L 1=a2L 1/aL 1/aL aF aF =a2L aF pffiffiffiffiffi R1= aL RaL
Manufacturing Issues and Challenges
The scaling projections in the previous section and those developed by the industry in the ITRS represent a desirable set of device goals in terms of device dimensions and performance that are needed to continue the exponential growth in IC system performance in future years. The scaling projections and device performance projections do not necessarily take into account physical material and device structure limits that may make it very difficult, if not impossible to achieve these goals. Some considerations of physical limits are incorporated into the scaling projections, especially in regard to limits on gate dielectric thickness. These considerations are the fundamental reason that the projected scaling for power supply voltage and oxide thickness were fundamentally changed between the 1997 and 2004 ITRS document. It was simply realized that achieving the projected oxide thicknesses in the 1997 document were physically impossible. Likewise, some of the projections in the 2004 ITRS for device performance and/or size scaling may prove to be physically impossible to achieve. This section presents some of the major challenges faced by the semiconductor industry in achieving the dimensional and performance scaling of CMOS devices discussed in previous sections. Very serious manufacturing problems exist in achieving the projected scaling to the end of conventional CMOS devices.
MOSFET Gate Stack Issues
The gate stack design is the key part of the MOSFET. It has been recognized for some time that continuing to scale the gate stack with the same materials of silicon dioxide and polysilicon will not produce acceptable devices for gate oxide thicknesses approaching 1 nm and beyond. Unlike in the golden era of scaling, innovative approaches, in both the gate dielectric and contacting material, are necessary. The gate stack (see Figure 1.7) is composed of (1) the oxide–silicon interface, (2) the gate insulator, and (3) the gate contact layer. For devices approaching the end of the roadmap, the gate oxide performance at a projected thickness of less than 1 nm is critical. The SiO2 cannot be utilized at these dimensions. Aside from reproducibility and manufacturability issues, tunneling currents are the major problem. Figure1.16 shows experimental gate oxide tunneling currents for oxide thickness ranging from 3.5 to 1.4 nm at an applied voltage, where direct tunneling dominates the current [12]. While these currents are large, they must be evaluated in terms of what might be an acceptable level in a particular device application. It has been experimentally shown that good device characteristics can be achieved with very thin oxides, provided the gate length is sufficiently short [13]. A gate current of 1 A/cm2 was suggested early on as an upper limit [12]. However, it is now generally accepted that the allowable gate current can be much larger from a device performance point of view. The ITRS document for HP devices lists acceptable gate current densities as high as 1!104 A/cm2. It is important to understand how such large gate currents can be considered as acceptable. If one assumes that an Ioff/Ion ratio of 10K4 as shown in Figure 1.15 for HP devices is acceptable and that half the off-state leakage can be due to gate current, then we can write
Ig Ig I Z % 5 !10K5 d Ag WLp WLp
The worst case (lowest limit) will occur for the minimum drain current, which occurs for p-MOS devices and ranges in terms of current per unit width from about 500 to 1000 A/m for the 90- to 16-nm nodes. Then using the lower value, we can obtain
Ig ð2:5 !10K4 A=cmÞ ð2500A=cm2 Þ % Z Ag Lp ðLp =nmÞ
For the 90- to 16-nm technology generation, this gives values from about 68 to 417 A/cm2. For an n-MOS gate, the limits would be about a factor of 4 larger, keeping the same ratio of off-to-on current. As from the previous section, the 2004 ITRS projects even larger ratios of off-to-on current for the smaller device dimensions. In any case for the HP devices, the gate current density can be quite large and cannot degrade the device performance. For LOP and LSP device applications, the current density must be considerably lower. Even though the current densities may seem high from conventional wisdom about a dielectric, the total currents can be a small fraction of the saturated drain current. Limits to gate current come not from degradation in device performance, but from overall chip power considerations. It is now certainly known that SiO2 for the MOS gate will be used at considerably smaller device dimensions than thought some few years ago. However, the data in Figure 1.16 illustrates the gate leakage problem with SiO2. For a given voltage, the current increases about a factor of 10 for each decrease of about 2-nm in oxide thickness due to direct tunneling through the oxide. The 2004 ITRS projects that oxynitrides, which are somewhat better than pure SiO2, will not satisfy the leakage current requirements at the 45-nm node and beyond, and that improved gate dielectric materials are needed for future technology generations. The purpose here is not to try to project exactly when alternative dielectrics will be required, but to discuss the potential advantages of improved gate dielectrics. The potential for reduced gate leakage with advanced dielectrics can be seen from the first order equation for carrier tunneling probability T through a barrier of height Vb and thickness td [14]:
1 sffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2mqV b A ðaÞ Low Fields : [email protected] t Z2 d 0 1 sffiffiffiffiffiffiffi 3=2 4 2m ðqV Þ b ðbÞ High Fields : [email protected] td A 3 Z2 qV
where V/tb is the electric field across the barrier. From this, we can identify the important material and device parameters determining tunneling current: 104 N – MOSFET Measurement
Gate current density (A/cm2)
tox (Å) 15
100 10−1
Gate voltage (v)
FIGURE 1.16 Measured and simulated gate currents for thin SiO2 gate stacks. (From Taur, Y., D. A. Buchanan, W. Chen, D. J. Frank, K. E. Ismail, S-H. Lo, G. A. Sai-Halong et al., Proc. IEEE, 85, (1977): 486.)
pffiffiffiffiffiffiffiffiffi mVb td pffiffiffiffi 3=2 ðbÞ High fields : mVb td
ðaÞ Low fields :
When considering different possible gate dielectric materials, a device constraint is the need to maintain the same capacitance across the dielectric, so that the same channel charge can be induced into the semiconductor with the same gate voltage. From the capacitance equation, we can see that for the same capacitance the dielectric thickness would vary directly with the dielectric constant as:
td Z
3d f 3d C
We can thus define a tunneling current "figure of merit" which captures the important material and device parameters for comparing the tunneling current of different dielectrics as:
pffiffiffiffiffiffiffiffiffi ðaÞ Low fields : mVb 3d pffiffiffiffi ðbÞ High fields : mVb3=2 3d
Since these parameters appear as negative quantities in the exponential factor, whichever material has the largest value of this parameter will, in theory, have the lowest tunneling current. If only the dielectric constant varied between materials, one would always want a dielectric material with a very high dielectric constant. However, there is a strong tendency for materials with high dielectric constants to also have smaller bandgaps, which must translate into lower barrier heights. Figure 1.17 shows some of the most important potential high-k dielectrics and their bandgap values vs. dielectric constant. While the high-k materials tend to have smaller bandgaps from the above figure of merit, one can see that a doubling of the dielectric constant is more important than a reduction in the barrier height by a factor of 2. The tunneling current is very sensitive to the tunneling barrier thickness. Table 1.2 shows values of these figure of merit parameters for several materials, assuming that the effective mass is the same for all the materials. This is done because of the lack of reliable effective mass values for the various materials. Two sets of values are shown for several of the materials because of some uncertainty with regard to dielectric constant and barrier height. When two values are given, the first set corresponds to a very optimistic set and the second term corresponds to the low range of
Conduction band offset (eV)
4 SiO2 3
ZrO2 Ta2O5
BaZrO3 0
15 20 25 Dielectric constant (K)
Variation of conduction band offset with Si for various high-k dielectrics.
Introduction to Semiconductor Devices TABLE 1.2 Material SiO2 Si3N4 Ta2O3 TiO2 HfO2 ZrO2
Tunneling Figure of Merit Parameters for Several Dielectrics 3d
Vb(V)
Low Fields Vb1=2 3d
High Fields Vb3=2 3d
3.9 7.8 25.0 25.0 50.0 30.0 28.0 20.0 24.0 20.0
6.75 11.0 30.6 36.2 50.0 30.0 34.3 23.7 28.4 22.8
20.3 22.1 45.9 76.1 50.0 30.0 51.4 33.1 39.7 29.6
expected values. In general, more improvement is seen to be theoretically possible at low fields than high fields; and higher dielectric constant materials offer larger potential improvements even though they tend to have reduced barrier heights. The larger parameters in the table would be expected to show the lowest leakage currents, all other things being equal. It must be remembered that the values in the table do not account for any possible differences in tunneling effective mass between the different materials. In most cases, one would expect the tunneling mass to be smaller in the higher-k dielectrics and to negate some of the potential advantage of the higher-k materials. The case of Si3N4 is interesting because the low field parameter projects an improvement in the tunneling current, while the high field parameter projects little improvement in the tunneling current over that of SiO2. For the present and future MOS devices, the low field regime is the most important and thus, one does expect an improvement with nitrides and oxynitrides, and oxynitrides have been verified by many investigators to show reductions in tunneling currents [15,16]. This is the first route for manufacturers toward reducing leakage currents in MOS devices and has been implemented already by the IC manufacturers. A high-k dielectric such as HfO2 with a dielectric constant of 28 can be made about 28/3.9Z7.2 times physically thicker than SiO2 and give the same capacitance or same inversion layer charge at the same gate voltage. In such a case, a 7.2-nm thick HfO2 dielectric would have an EOT of only 1.0-nm and may be potentially much easier to manufacture and control. The ITRS anticipates the use of alternative high-k dielectrics for future technology generations and expresses the dielectric thickness in terms of EOT values. In terms of real physical thickness (td) of a dielectric layer, the EOT can be expressed as
EOT Z td ð3ox =3d Þ
In experimental measurements such as capacitance measurements, only the EOT value can be determined unless one has a separate independent measurement of physical thickness or dielectric constant. However, for MOS device applications it is the EOT value that is important in terms of induced channel charge in inversion. In addition to appropriate barrier height and dielectric constant, any alternative gate dielectric must form a stable compound and stable interface with silicon as well as the gate contact material at any subsequent processing temperatures. There are potential problem areas with all potential high-k dielectrics and the search for the most appropriate high-k gate dielectric represents an important research area. The most promising material appears to be HfO2 and alloys of this with silicon, the so called Hafinum silicates. The quality of the dielectric-silicon interface is critical for achieving high channel mobility. It is not clear that the required low surface state densities, low fixed charge and smooth interface can be achieved with any material combination other than silicon–silicon dioxide. If such an interface layer is required, it may be extremely difficult to achieve EOT below about 0.5 nm as this may be the range of interface oxide needed for good oxide-silicon properties. Some recognition of this is inherent in the ITRS projections as the end-of-roadmap EOT value is projected to be approximately 0.5 nm.
The need for high-k gate dielectrics has been at the forefront of gate stack research since the 1997 ITRS and much research has been done on a wide variety of MOS devices with high-k dielectrics. Many researchers have demonstrated orders of magnitude improvements in the gate tunneling currents over pure SiO2 for EOT values in the range of 1–1.5 nm [17,18]. Researchers have also reported capacitors and transistors with EOT values approaching the 0.5 nm range. The fundamental approach for reducing tunneling currents as expressed in the figure of merit of Equation 1.29 is now well established. However, some problems have continued to be prevalent in the search for the ideal high-k gate dielectric. Many of the lowest EOT experiments have shown unacceptable reductions in surface mobility. Also many samples have shown unacceptable field-dependent threshold voltage shifts. The ideal way to transition an MOS surface interface from silicon into a high-k dielectric has proven to be a somewhat elusive goal, but progress is continually being made and the future of scaled MOS devices seems to include, of necessity, a high-k material in order to reduce the gate tunneling currents to acceptable levels. Gate oxide reliability has always been a major concern as MOSFET devices are scaled. Operating voltages must remain below some maximum value, which is typically set by the requirement of a 20-year lifetime for devices when operated at maximum voltages. Previously reported work on SiO2 has shown that gate oxide lifetime is determined primarily by the electric field applied to the oxide. In the era of constant field scaling, the oxide field tended to stay constant with scaled device dimensions. To the same order of approximation as involved in Equation 1.10, one can write:
Eox xðVDD C ðVbi K2fB Þ=2Þ=tciv xVDD =tciv
Since the threshold voltage tends to be about 20% of the supply voltage, the oxide equivalent dielectric field according to the ITRS projected scaling rules should be about 1.24 times the Ec curve shown in Figure 1.11. Assuming this to be the case, the oxide equivalent dielectric field should remain below about 1!107 V/cm. The term equivalent dielectric field is used here as the dielectric will most likely not be pure SiO2, but some more appropriate high-k material. Previous studies of SiO2 have shown that it can achieve 20-year lifetimes, provided the oxide field remains below about 8!106 V/cm [11]. The values in Figure 1.11 prior to the 65-nm node are consistent with this as an upper limit on the oxide field. Thus, there are potential dielectric reliability problems with scaling beyond the 90-nm node as the gate field is projected to increase. An additional factor that is somewhat unknown is the reliability of dielectrics with the very large tunneling currents that are projected in the dielectrics. Carriers transiting the oxide by pure tunneling are not expected to interact with the atoms creating any defects. However, some small fraction of the carriers will interact in the dielectric and create defect centers, which contribute to reliability problems. If a dielectric is sufficiently thin, charge trapping should not be a problem. For SiO2, it has previously been observed that charge trapping effects tend to become negligible at thicknesses around 4–6 nm, because any trapped carriers can rapidly tunnel out of the oxide into the gate or substrate [19,20]. Hot carrier reliability is expected to greatly improve voltages below approximately 3 V, since few carriers can gain sufficient energy to create interface states or shallow oxide traps. Finally, as the dielectric EOT becomes thinner, the amount of interface charge or dielectric charge needed to shift the device threshold voltage by a small voltage such as 1 mV keeps increasing, so the scaled devices are much more tolerant to interface and dielectric charges. This is one of the positive aspects of scaled devices. For the high-k dielectrics which are expected to be used with the scaled devices, reliability is still somewhat unknown. However, one trend in the right direction is the reduced magnitude of the dielectric field with increased dielectric constant. For example, an oxide field of 1!107 V/cm for SiO2, with a dielectric constant of 3.9, corresponds to a dielectric field of less than 2!106 V/cm for a high-k dielectric with a constant of 20. This provides considerable encouragement that reliability of high-k dielectrics will not be a major problem at the expected fields. Some preliminary data on the reliability of high-k dielectrics has been encouraging, and it may in fact be possible to increase the effective dielectric field as proposed in the ITRS without degrading long-term device lifetime. As this is written, there are still
considerable problems to be resolved for the gate dielectric to be used as researchers attempt to approach EOT values in the 0.5-nm range. In addition to the gate insulator, the gate contact is a critical part of the gate stack. This has typically been polysilicon and more typically both nC and pC polysilicon for n- and p-channel devices, respectively. In the early history of MOS devices, the replacement of metal gates by polysilicon was one of the key developments leading to rapid improvements in yield of early ICs. The MOS device has, however, continued to maintain the name MOS device. The use of polysilicon has become a major problem for continued device scaling, because the finite depletion layer associated with the gate charge in the polysilicon is causing significant drops in the current drive and transconductance of MOS devices. The polysilicon depletion effect becomes more important with scaling, because the oxide field (see Figure 1.11) remains essentially constant with scaling. This means that the charge per unit area in the gate polysilicon remains constant with scaling. In turn, the voltage drop in the polysilicon for the same gate doping density remains constant. Thus, since voltage levels decrease with scaling, the polysilicon voltage drop becomes a larger fraction of available device voltage and current drive is reduced with each technology generation. To maintain a constant dielectric field with polysilicon depletion requires a further decrease in an already very thin dielectric. Simulated C–V curves for nC polysilicon on a p-type substrate have been shown in Figure 1.9. This was previously used to discuss primarily the quantum size effects in the silicon substrate that cause an effective increase in the equivalent dielectric thickness for the capacitance and for the channel inversion charge. The typical effect of a polysilicon gate as compared with a metal gate can be seen by comparing curves (c) and (d) with curve (b) which includes only quantum confinement effects. The capacitance values represent charge per unit voltage, so the differences between the curves (c) and (d), and curve (b) represent reductions in transconductance or channel charge that would occur due to polysilicon depletion. If the polysilicon doping density could be increased without limit, the polysilicon depletion effect could be minimized. However, from literature reports, it appears that it will be very difficult to achieve electronically active doping densities much above the 1!1020/cm3 for n-type silicon and above the mid to upper 1!1019/cm3 for p-type polysilicon. As can be seen from Figure 1.9, this represents a significant degradation in current drive capability for devices beyond the 90-nm node. To overcome the polysilicon depletion effect, there are two approaches: (1) attempt to very heavily dope the polysilicon with values near 1!1021/cm3 needed, or (2) replace polysilicon with a metal gate. The most fruitful approach appears to be the metal gate approach, which is at this time being extensively pursued by the industry. For metal gates, two different metals with two work functions (WF) are needed—one for n-channel and one for p-channel devices. This is required to provide appropriate metal WFs to essentially replace the WFs of nC and pC polysilicon. Metals are needed with WFs near the conduction and valence bands of the underlying silicon. For a direct replacement for nC and pC polysilicon, WF values of 4.1 and 5.2 eV are needed. For possible metal gates, a wide variety of WF values exist in the elemental metals ranging from below 3.0 eV for metals, such as Li, Rb, Sr, Cs, Ce, Pr, and Eu; to over 5.0 eV for metals such as Ni, Se, Rh, Pd, Ir, Pt, Ru, and Au. However, most of the elemental metals have significant problems when used as gate contact materials over either SiO2 or the most promising high-k dielectrics such as the Hf silicates. The low WF metals tend to be too reactive, while the high WF metals tend to have adhesion problems. The latter adhesion problem can be controlled by the use of capping layers and bilayers of metals such as RuTa, RuMo, or TiPt have shown considerable promise for p-type MOS devices [21–23]. As a general class of materials, the metal nitrides and metal silicides are much more stable than the elemental metals and considerable research has been done on such compounds for possible metal gates. Some of the most promising of these are TaN [24], TiN [25], TiAlN [26], TaSiN [26], and HfN [27]. Metal silicides have been extensively used as source/drain contact materials for CMOS, so the possible extension of this technology to MOS gates is an attractive approach. For such an application, the metal silicide must extend completely to the gate dielectric and such a silicide process has been referred to a "full silicidation" (FUSI) process [28].
The threshold voltage of a MOS device depends not only on the fundamental or intrinsic WF of the metal gate, but also on the presence of any possible charge dipole layers within the silicon/dielectric/metal gate structure. Such dipole layers are possible at either of the dielectric interfaces or at an internal interface between a high-k dielectric and an interface oxide or nitride layer. Such dipole charge layers are known to pin the Fermi level for most metal-semiconductor interfaces near the midgap energy. For an MOS gate contact, such dipole layers will result in some effective WF that differs from the intrinsic gate WF. Evidence for such dipole layers have also been found for many metal-high-k interfaces. Typically, such dipole layers result in an effective WF more toward the midpoint of the Si bandgap and away from the band edges. Some of the most promising metal gate materials are summarized below: A. p-MOS (desired WF w5.2 eV): Pt (5.4 eV), Ru (5.2 eV), Ti (4.6 eV), Mo (4.7 eV), TaAlN (4.9 eV), TiN (4.8 eV), CVD TaN (5.1 eV), and B doped FUSI NiSi (5.1 eV) B. n-MOS (desired WF w4.1 eV): Ta (4.2 eV), Ti (4.2 eV), TaSiN (4.2 eV), and As doped FUSI NiSi (4.6 eV) As of this review, the most appropriate metal gates and integration approach has not been determined. However, the future of MOS devices most likely involves a return to the dominant use of metal gates.
Channel Doping Issues
The proper selection of substrate doping and engineering of the doped layers beneath the gate are key to optimum performance of the MOSFET device with respect to important parameters, such as threshold voltage, peak channel mobility, DIBL, subthreshold current slope, and drain-to-source punch-through voltage. Many of the issues regarding channel doping can be understood with reference to Figure 1.18, which illustrates the important charge regions under the channel. First, and perhaps most important, there are depletion regions under the gate (represented as Xdm(y)) and depletion regions surrounding the source/drain junctions (represented as Xsd and Xdd). The doping density under the channel controls the depth of all these depletion regions with larger doping densities required to obtain thinner depletion regions as device dimensions are scaled. Of primary importance is the requirement that the junction depletion regions do not overlap under the gate or else junction, punch-through will occur and large drain-to-source currents can flow. As the junction built-in voltage does not scale with device scaling, this requirement becomes more difficult to satisfy with scaling. Vs
L O
Y Xdm (y)
Xsd Depletion boundary
Xj Xdd
X p -Substrate
FIGURE 1.18 Charge sharing model for VT reduction and other short-channel effects. (From Arora, N., MOSFET Models for VLSI Circuit Simulation, Springer, New York, 1993.)
Controlling short-channel effects are very critical to the ability to properly scale MOS devices. The most important of these are: (1) threshold voltage reduction, (2) DIBL effect, and (3) subthreshold current slope parameter. While these parameters are frequently expressed in terms of complex function of device parameters, such as junction depths, doping, oxide thickness, etc., they are primarily functions of the two-dimensional geometry shown in Figure 1.18. The dotted lines within the depletion regions are intended to represent the regions of charge controlled by the various electrodes (gate, source, and drain). One way to look at the drain voltage dependence of VT is that part of the underlying depletion region is controlled from the source and drain, and not from the gate electrode. The fraction of charge controlled by the gate depends on the width of the depletions and junction depth relative to the gate length L. If the same relative size of the junction depths and depletion regions is maintained at each technology generation, then the relative importance of short-channel effects should remain the same. To achieve this, the depletion region widths must be scaled in the same manner as other device dimensions. Another way of viewing the drain voltage dependence of VT is that the potential under the center of the gate is controlled not only by the gate charge, but is also influenced by the source and the drain depletion region charges. Adding more charge at the depletion regions will shift the potential under the gate, resulting in more channel charge for the same gate voltage. Drain induced barrier lowering and changes in VT arise from similar physical effects. At zero drain bias, there will be some lowering of VT due to the source/drain charges. As the drain bias is increased, more charge at the drain depletion region will result in a larger effect and a further reduction in threshold voltage; hence a voltage-dependent threshold voltage or DIBL. This again is primarily a geometrically determined parameter depending on the junction depths, oxide thickness, and depletion layer depth relative to the channel length. Low DIBL requires that the field lines from the drain terminate on charges other than those in the channel. This is determined by the degree to which the gate is electrically shielded from the drain. Maintaining a fixed relative geometry is again the key to control the DIBL at small device dimensions. Each 10 mV of VT reduction caused by DIBL will increase the Ioff current by two to three times. However, DIBL does increase Idast as well as increasing transconductance of the device. An optimum tradeoff occurs for a DIBL that is approximately 10% of VDD. The channel doping densities and doping profile must be selected to obtain a proper device threshold voltage and to control short-channel effects. Some of the implications of this, with respect to the doping of the scaled devices, is now explored and discussed. To control depletion layer punch-through, the channel must be sufficiently heavily doped under the gate region. There are several possible ways this can be achieved. First, the channel could just be uniformly doped with some large doping density in the region identified as the substrate body in Figure 1.7. However, since the channel mobility is degraded by a large bulk impurity density, there are reasons for desiring a lightly doped region just under the gate where the inversion channel exists. This can be accomplished by use of a retrograde channel doping such as shown in Figure 1.19, where a lightly doped region is shown directly under the gate with a more heavily doped region deeper into the substrate. This is frequently referred to as a super steep retrograde doping profile. Such a profile also gives added flexibility with respect to threshold voltage control, since the threshold voltage can be controlled somewhat by adjusting the depth of the lightly doped layer. The super steep retrograde doping profile, however, does not provide sufficient flexibility to achieve all the desired goals of the channel doping for short-channel devices. For example, the doping density needed to control punch-through, and limit the size of the junction depletion layers can be too large to give a desired low threshold voltage even when the heavily doped layer is located some distance under the gate oxide. In such cases, it has been found highly desirable to employ another doping technique that allows a non-uniform lateral doping density under the gate. This is the pocket implant technique illustrated in Figure 1.20. This is also frequently referred to as a superhalo doping. By the use of shallow angled implants, using the gate as a mask, heavily doped pockets can be formed in the substrate adjacent to the source/drain contact implants. These heavily doped pockets can provide the heavily doped regions needed to terminate the junction depletion regions and control punch-through. However, they can leave a more lightly doped substrate under the center of the gate region, so that an acceptable threshold voltage can be achieved. For greatest flexibility, this should be combined with the super steep retrograde doping
Spacer tsw n+
Lp Gate contact tox Lightly doped
tgate Drain extension
n+ p-type, Heavily doped, NB Drain contact
Channel structure and doping for super steep retrograde channel doping.
profile. In this manner, one can somewhat separate the problem of punch-through control from that of threshold voltage control. However, this becomes more and more difficult with dimensional scaling because of the large doping densities required, and because of the small dimensions over which the doping profiles need to vary by large factors. To a first order approximation, the doping density for a given depletion width of the drainto-substrate p–n junction with the drain side, which is very heavily doped is given by
NB Z
23s ðVj C Vbi Þ F qW 2
where NB is the light side doping density, Vj is the applied junction bias voltage (maximum of VDD), Vbi is the built-in junction potential (w0.9–1.1 V for NBO1017/cm3), W is the width of the depletion region, and the factor F accounts for the curvature of the p–n junction. For a planar junction, FZ1; for a cylindrical junction where Rj is the radius of the p–n junction (Rjy0.65XJ), F is given by
2½W=ðW C Rj Þ ln
WCRj Rj
2 Rj K1 WCRj
For shallow junctions, the cylindrical junction approximation is more accurate than the planar junction approximation. To prevent the depletion layer punch-through, W must scale with feature size
Lp Gate contact tox
tgate Drain extension n+
XJC Heavily doped "pocket" implant
Drain contact n+
Example of heavily doped pocket implants for punch-through control.
and scaling W means that doping density NB must scale somewhat faster than the inverse feature size, since VjCVbi does not scale as fast as feature size. Figure 1.21 shows the required doping densities according to these equations as a function of technology generation from the 90- to 16-nm node. Using the ITRS projections for dimensions, the factor F is approximately constant for each technology generation, depending only on the ratio of W to Rj Two potential limits are shown for the depletion layer: one for Leff/4 and one for Leff/2. The first giving a highly desirable limit, while the latter providing probably an upper limit on the acceptable value of the depletion layer width. For the two cases, FZ0.806 and 0.885, respectively, so the junction curvature does not give very much smaller limits than a planar junction with the values being only 12%–20% lower in value as can be seen in Figure 1.21. Also shown in the figure is a "mean" curve representing the geometrical mean of the Leff/4 and the Leff/2 curves for the case of a cylindrical junction. This can be taken as typical of the desired peak doping densities to control the junction depletion region depth with future scaling. While the Leff/2 value might seem too large, the bulk of the depletion region will be confined between the two deep drain contact junctions of XJC as shown in Figure 1.7. The spacing between these junctions can be two or more times the effective channel length. Thus, a depletion layer extension of Leff/2 from these junctions is not unreasonable. These required doping values are quite large and there are significant consequences of such large doping densities to be subsequently discussed. As a point of reference, Frank et al. have published a typical pocket implant doping profile for a 25-nm effective channel length device [29,30] and this is shown in Figure 1.22. Their peak doping density is somewhat above 1!1019/cm3 with a maximum depletion region depth of about Leff/2. In comparing with Figure 1.21, this would correspond to the 90-nm technology node and this one data point compares very well with the Leff/2 curves in Figure 1.21. Large doping densities as shown in Figure 1.21 will give ever increasing drain-to-substrate leakage currents as the densities required for punch-through control are in the degenerate range and approach those of tunnel junctions. A model for junction tunnel current has previously been presented by Moll [31] as
Doping density (cm−3)
Abrupt junction Cylindrical junction
Doping density to limit depletion layer width to Leff /4 Mean
1020 Leff /2
FIGURE 1.21 Doping densities required for punch-through control with different limits on the maximum width of the depletion layers.
Gate tox = 1.5 nm
Source n-type:
2.0 ×1019 1.5 ×1019 1.0 ×1019 5 ×1018 0
25 nm y= 1.2 V 0.8 V
p -type:
1.0×1019 5×1018
0.4 V y = −0.4 V
FIGURE 1.22 Doping concentrations for a 25-nm gate length device. (From Frank, D. J., R. H. Dennard, E. Nowak, P. M. Solomon Y. Taur, and H-S. P. Wong, Proc IEEE, 89, (2001): 259; Taur, Y. C. H. Wann, and D. J. Frank, IEDM Tech. Digest., 789, 1998.)
" pffiffiffiffiffiffiffiffiffi # pffiffiffiffiffiffiffiffiffi 3 2m q EVj 4 2m Eg3=2 pffiffiffiffiffi exp K Jt Z 3qZE 4p2 Z2 Eg
where m is the tunneling effective mass taken as 0.19m0, Vj is the applied junction voltage, Eg is the bandgap energy and E is the electric field taken here for an abrupt junction as
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi qNB ðVbi C Vj Þ Ey 23s
Calculations based upon this model are shown in Figure 1.23 for doping densities in the range of 1! 1019 to 1!1021/cm3 covering the range shown in Figure 1.21. Two curves are shown corresponding to the expected maximum device voltages. Shown across the top of the figure is the corresponding electric field over the range of 1–10 MV/cm. The values of current are similar to the values reported by Frank et al. [29], which includes some experimental data points. If one compares the doping densities in Figure 1.21 with the tunneling currents in Figure 1.23, it can be seen that there are large potential problems with junction leakage for the smallest device dimensions. If one makes the same assumptions about allowable magnitudes of drain leakage current as for gate leakage current and assumes a somewhat optimistic scenario that the tunneling current can be confined to a spatial depth corresponding to the junction depth, then we can approximate
Jt %
ð2:5 !10K4 A =cmÞ ð2500A =cm2 Þ Z XJ ðXJ =nmÞ
This would indicate that the junction leakage current would exceed allowable limits around the 32-nm technology generation. Requirements for the control of depletion layer punch-through and tunneling currents probably limit the ability to scale bulk CMOS to dimensions somewhat less than the ultimate 2004 ITRS limits. Alternative device structures such as fully depleted (FD) SOI or double gate (DG) structures may be ultimately required. Such structures will be discussed in a section 1.5.2. One approach for reducing the junction electric field that might come to mind is to dope the deep contacting junction more lightly, so that the junction is not basically a one-sided junction, but have the
Introduction to Semiconductor Devices Peak electric field (MV/cm) 3 4 5
Tunneling current (A/cm2)
106 105 1.0 V
V = 0.5V
101 100 10−1
Model calculations for triangular barrier
10−2 10−3 10−4 10−5 10−6 19 10
FIGURE 1.23 electric fields.
1020 Doping density (cm−3)
Estimated drain-to-substrate leakage current for various punch-through doping densities and peak
depletion region extend more into the deep contacting junction. However, as will be subsequently shown, the deep contacting junction must be as heavily doped as possible in order to obtain an acceptable contact resistance to an external contact. Thus, there is little that can be done in practice to reduce the peak electric field by reducing the doping density on the source/drain contact side of the junction. In addition to controlling the depletion regions from the source/drain junctions, the substrate doping is important in setting the device threshold voltage. In a given technology, one generally desires devices with various channel lengths from some minimum channel length to larger channel lengths. It is thus desirable to have a device threshold voltage for the minimum channel length that is not very different from that of a long-channel threshold device. For a long-channel device, if one assumes a retrograde doping profile as shown in Figure 1.19, then first order calculations can be made from the standard semiconductor equations regarding the relationship between threshold voltage, width of the lightly doped layer, and the doping in the heavily doped layer. To look at important trends and magnitudes, it will be assumed that the doping density in the lightly doped layer may be neglected and that the depth of the lightly doped layer is xI, and that the depletion layer extends to a depth xB into the heavily doped layer. The model for substrate charge is then
( rZ
for 0! x! xI
KqNB
for xI ! x! xI C xB
Using this substrate charge density, one can evaluate the surface potential for the threshold-channel condition and evaluate the theoretical threshold voltage for a given bulk doping density and given depth of the lightly doped layer [32]. Inversely, one can determine the bulk doping density required for a desired threshold voltage, given the depth of the lightly doped layer and the other device parameters such as oxide thickness. One finally needs a gate WF, which can be conveniently taken as at the band edges of the semiconductor. One complication is the need to correct the standard equations for quantum confinement effects. This can be done with various published correction models or one can use the
Handbook of Semiconductor Manufacturing Technology VT Design value (V) 1021
XI = XJ /2 1020
Short channel devices with barrier lowering due to source/drain regions
XI = XJ /4 XI = 0
XI = XJ /2
Long channel devices
XI = XJ/4 XI = 0
Calculated values from NCSU cvc program
Open circles are for short channel device design including estimated DIBL Closed circles are for long channel device design with no DIBL included
45 32 Technology generation (nm)
FIGURE 1.24 Doping densities for long- and short-channel devices needed with the retrograde doping model to achieve the design values of threshold voltage at each technology generation.
simplified approach of the ITRS to assume that these effects make the oxide thickness appear to be 0.4nm thicker than the physical thickness. Some of the important results of such an evaluation are shown in Figure 1.24 for the 90- to 16-nm technology generations using the dimensional parameters of the 2004 ITRS. Concentrate first on the three lower curves in the figure with solid circles as data points, which are the results for the calculation outlined above that would represent long-channel threshold voltages of the values seen on the top axis of the figure. The values are seen to be in the 1!1018 to 3!1018/cm3 range. The results are essentially independent of n- or p-channel type. Three curves are shown for lightly doped layer thicknesses of 0, xJ/4 and xJ/2 representing the most practical thicknesses of lightly doped surface layers. As seen by the curves, there is little difference in the required doping density for either the different technology generations or on the thickness of the lightly doped layer. For the calculations shown in the curves, quantum confinement effects were estimated by the technique of increasing the oxide thickness by 0.4 nm. Also shown in the figure are required doping densities for the device structures as determined by the NCSU cvc software, which includes a more detailed model for the quantum confinement effects, and which solves more exactly the device equations. These are the square data points and should be compared with the lower xIZ0 curve. These points are just slightly higher in value that those obtained with the much simpler model and provide some additional justification of the simple model of increasing the effective oxide thickness by 0.4 nm to account for the QM effects. The NCSU cvc software cannot be used to compare the other curves, as it assumes a uniformly doped substrate. These values indicate why one cannot simply heavily dope the entire substrate to control the punch-through effect. The doping densities required for the proper threshold voltage are much lower than the densities shown in Figure 1.21 that are required for punch-through control. As one decreases gate length from the long—to the short—channel case, moving toward a case as shown in Figure 1.22, several physical effects occur. First, the shielding of the source/drain depletion regions from the channel will become less effective and the threshold voltage will begin to decrease. Second, as the channel length becomes very small, the doping densities from any pocket implants will
begin to overlay and cause an increase in the doping density under the center of the gate. In the minimum channel length design, as shown in Figure 1.22, one can see considerable enhancement of the doping density under the center of the gate due to the overlap of the pocket implants. This increase in effective channel doping tends to increase the threshold voltage. Thus, with a pocket implant or halo structure one has two competing effects: one tending to reduce the threshold voltage and one tending to increase the threshold voltage. This can greatly delay the rolloff of threshold voltage with decreasing channel length and allows much shorter channel lengths than would be otherwise possible. As a function of decreasing channel length, it is not unusual for the threshold voltage to first increase and then decrease with decreasing channel length. The decrease in threshold voltage with channel length has been extensively studied both theoretically and experimentally. Various models predict that the decrease in threshold voltage is an exponential function of distance of the source/drain from the center of the channel (Leff/2) and depends on a length parameter that is a function of the geometry of the channel structure [33–38]. The other expected dependency is on the charge in the depletion layer, which gives the model form
DVT f
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi VD C Vbi expðKLeff =2lÞ
If we assume contributions from both the source and drain then
DVT Z VDB ð1 C
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1 C VDD =Vbi ÞexpðKLeff =2lÞ
In this, it has been assumed that the source is at zero volts and the worst case drain condition is with the drain voltage at the supply voltage. The Vbi parameter is the equilibrium junction voltage (about 1 V), VDB is the proportionality constant and l is the exponential decay length. It should be noted that, not all authors use the same notation for the exponential term. In some cases, the l term has just been called l [37] or L and in some cases the exponential term has been expressed as KpLeff/2L [29], which gives a different meaning to the length scale factor. The data of Wann et al. is consistent with the numerical values
VDB yVbi ðy1 VoltÞ LDB yðtox ðxI C xB ÞxJ Þ1=3
If one uses this model for the reduction in threshold voltage, this can be included in the simple model previously discussed for substrate doping, and one can evaluate the required increase in channel doping for obtaining a desired threshold voltage. The upper three curves in Figure 1.24 illustrate the results of including this model of channel threshold voltage reduction combined with the requirement at minimum channel length to have the same threshold voltage as for the long channel case. In other words, if the channel doping densities are as given by the upper three curves under the center of the channel for a minimum channel length device, the channel reduction effect will be offset by the increased voltage due to the increased doping. The required doping densities of the upper three curves are in the range that one might expect to achieve with the overlapping doping densities of a pocket implant. A very accurate design of a pocket implant and the substrate doping density profile requires twodimensional computer simulations. However, the above first order calculations illustrate that with a properly designed pocket implant, with an increased doping density under the channel for a minimum channel length device it may be possible to offset most of the DIBL effect and obtain the required low threshold voltages for scaled devices. If all dimensions are scaled together, the design problem is similar at each technology generation. However, the manufacturability of future scaled devices becomes more questionable, because the doping densities must increase and the dimensions over which the densities must change values become smaller.
Handbook of Semiconductor Manufacturing Technology 120
DIBL at VDD (mV)
XI = 0
90 XI = XJ /4
FIGURE 1.25 Estimated device drain-induced barrier lowering (DIBL) for nominal short-channel devices using a retrograde doping profile to set long-channel threshold voltage.
The model calculations also provide estimates of the value of DIBL that might be expected for such scaled devices. Assuming that DIBL is just the drain voltage manifestation of Equation 1.39, one can write
DIBL Z VDB ð
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1 C VDD =Vbi K1ÞexpðKLeff =2lÞ
Plots of this are shown in Figure 1.25 for different assumptions on the width of the lightly doped surface layer. Controlling DIBL really means controlling the device relative geometry and if the relative geometry can be maintained as this modeling assumes, DIBL is expected to remain relatively constant and within acceptable limits (!100 mV in Figure 1.25). A final important geometrical parameter is the subthreshold slope parameter. A model for this parameter has previously been given as Equation 1.4 and depends on the ratio of oxide thickness (corrected for QM effects) and the substrate depletion layer depth. For the retrograde doping model and the doping parameters in the previous figures, the predicted value of S is given in Figure 1.26. A small value of S (ideal value of 60) results from a deep depletion region and this is achieved for the long channel design. The increased substrate doping required at short channels degrades the slope parameter, but the resulting values are still very good. Again, if one can keep the relative geometry the same, the subthreshold parameter remains in good control, but the subthreshold slope is expected to degrade with short-channel length devices.
Source/Drain Contact Issues
The typical drain contact structure, shown in Figure 1.27, consists of the drain contact junction of depth XJC and the drain extension of depth XJ. Although the initial purpose of the shallow drain extension was to reduce the peak electric field near the drain end of the conductive channel, and thereby reduce hot electron injection, as devices are scaled to lower voltages, the reduced field is not as important for this purpose. However, the shallow extension is required to reduce short-channel effects, as discussed in the previous section, while the deeper contacting junction is necessary to accommodate the thickness of the silicide contact layer and to minimize junction leakage. XJC should not be larger than required to meet these conditions, since a larger value requires a thicker oxide spacer and a longer tab extension with
80.0 X I = XJ/2
S (mV/decade)
75.0 XI = 0
X I = XJ /2
Open circles are for short channel device design and including estimated DIBL Closed circles are for long channel device design with no DIBL included
Estimated subthreshold slope factors for long and short-channel devices.
increased resistance in order to minimize short-channel effects. The source/drain resistance design should minimize both parasitic effects and contact resistance [39–42]. There are three major components of source/drain resistance: (1) an accumulation layer resistance due to the gate overlap with the drain region, (2) a spreading resistance as carriers spread from the channel into the XJ junction, and (3) a bulk junction resistance due to the length of the drain extension over the XJC and silicide contact. The latter two components are especially significant with regards to scaling to smaller device dimensions. Referring to Figure 1.27, Rtab the resistance of the drain extension can be estimated as
Rtab y
r[tab WXJ
Rtab W yrsc [tab
where r is the resistivity of the drain extension, [lab is the length of the drain extension, and rsc is the sheet resistance of the drain extension. Without employing a two-dimensional analysis, a reasonable estimate for the tab extension length is 0.5LP or half the physical gate length. For a constant sheet resistance, the RtabW product is then expected to scale as the device dimensions. Several authors have studied the spreading resistance problem [39,40,43] and the analytical approximations from these studies can be written as
Metal Gate
Rtab
XSI
Silicide Rc XJc
XJ Body
Illustration of the major components of source or drain resistance.
Rsp x
2r lnðbXJ =XC Þ pW
where XC is the inversion accumulation layer thickness and b is a constant that varies from 0.37 to 0.90 depending on the method of derivation. For the purpose of this discussion, an intermediate value of 0.58 [43] will be used. This resistance is to be added to the bulk extension resistance of Equation 1.42 to give the total extension resistance of:
Rtab W xrð[tab =XJ Þ 1 C
2XJ lnðbXJ =XC Þ Z rð[tab =XJ ÞFtab p[tab
The spreading resistance increases the extension resistance by the quantity in brackets in the above equation (factor Ftab). In order to estimate the magnitude of this term, a typical channel inversion/accumulation layer thickness must be estimated and this depends on the surface field or the surface inversion/accumulation layer density. For a typical oxide field of approximately 1!107 V/cm, an inversion/accumulation layer density of around 2!1013/cm2 is expected. The work of Stern can then be used to estimate an average inversion/accumulation region thickness of about 2.5 nm [5,6]. The quantity in brackets Ftab, in the above equation can then be expected to range from about a factor of 2.08 at the 90-nm node to about 1.0 at the 16-nm node. Any component of the source/drain resistance must be compared with the channel resistance, Rsat, which in the on-state can be defined as:
Rsat Z VDD =Idsat
Circuit simulations show that when the external source and drain resistances are equal to about 10% of this value, the saturated drain current will be reduced by about 8%. Thus, an acceptable value of resistance will be estimated as one, where the source or drain component is less than 1/20 of this value (5% contribution for each source and drain component). Using Equation 1.9 for the saturated drain current gives
Rsat W Z
VDD tciv y vsat Cox ðVDD KVT ÞFI 0:85vsat 3ox FI
In the second form of the equation, the approximation VT/VDDZ0.15 has been used. If the factor FI were an exact constant, then the RsatW product would be expected to scale directly with the capacitance EOT. For the device model previously discussed, it is found that FI varies from about 0.65 to 0.80 for n-channel devices over the 90- to 16-nm nodes and varies from about 0.46 to 0.67 for corresponding p-channel devices. Calculated results for RsatW are shown by the upper four curves in Figure 1.28 for the 90- to 16-nm technology nodes. Two curves are shown for both n- and p-channel devices. The open circle data points are calculated from the device model of Equation 1.9 for Idsat, while the solid data points come from using Equation 1.45 and the 2004 ITRS values of Idsat The two approaches give similar trends and magnitudes, with the 2004 ITRS current values giving slightly larger values. Also the values are higher for p-channel devices than for n-channel devices because of the lower saturated drain currents for p-channel devices. The general trend is for RsatW to become slightly lower for smaller device dimensions. These values and Equation 1.44 can now be used to estimate required values of the extension junction resistivity. Using the 10% of channel resistance requirement leads to
ρtab or Rsat W (Ω cm)
Rsat W p-channel devices
10−1 n-channel devices 10−2
1.6 ×1019 2.1×1019
rtab for p-channel rtab for n-channel
9.9 ×1019
Open data points from device models Solid data points from Idsat of 2004 ITRS
FIGURE 1.28 Estimated RsatW values and resulting contact tab sheet resistances for scaled metal oxide semiconductor devices. Estimated for approximately a 10% reduction in saturated drain current.
rð[tab =XJ ÞFtab !
1 R W 20 sat
r! 0:025Rsat W In the final expression llab/XJ is assumed to be constant (approximately equal to 1.0) and the worst case value of Ftab(2.0) has been taken. This limit on extension junction resistivity is shown as the lower two curves in Figure 1.28 for n- and p-channel devices. Also shown in the figure are values of doping density corresponding to these resistivity values at the end points of the technology nodes. For example, for a p-channel MOSFET, the estimate is that the drain extension must be doped to at least 1.6!1019/cm3 for the 90-nm node and at least 6.9!1019/cm3 for the 16-nm node. Corresponding values for n-channel devices are 2.1!1019 and 9.9!1019/cm3. If drain extensions are formed by ion implantation with approximately Gaussian profiles, then the peak doping densities would be some 2–3 times the average values. In terms of sheet resistances, the corresponding limits are 1500U/cm2 to 2400U/cm2 for n-channel devices and 3000U/cm2 to 4800U/cm2 for p-channel devices. The required doping densities for the drain extensions are not too severe. However, the technology for producing junctions as shallow as needed for scaled devices is a critical technology that must be developed. A final important resistance contribution comes from the deep contacting junction of depth XJC and the contact resistance between the silicon and silicide layer. The most important component of this resistance is the contact resistance between any top metal or silicide layer to the silicon. A model for this resistance is [41]
RC Z
rsc WLc0
where rsc is the contact resistance (in U/cm2) and Lc0 is an effective window length for uniform current flow with negligible resistance contribution from the sheet resistance of the XJC junction. The effective window length can be expressed as:
Lc0 Z Lc tanhðLc =Lt Þ pffiffiffiffiffiffiffiffiffiffiffiffiffi Lt Z rsc =Rsd
where Lc is the physical contact length, Lt is known as the transfer length and Rsd is the sheet resistance of the underlying silicon comprising the XJC junction. The effective window length has two limiting cases of Lc0 xLc for Lt[Lc and L 0 c xLt for Lt/Lc. In all cases Lc0 % Lc and therefore,
Rc R
rsc WLc
A good device contact design will have Lc>Lt. However, there is little advantage in making Lc larger than about 2Lt. If LcZLt, the contact resistance is 30% larger than the right hand side value and for LcZ 2Lt the contact resistance is only about 8% larger than the right hand side. Thus, making Lc larger than about 2Lt, does not appreciably lower the contact resistance, but adds additional junction capacitance. It will be assumed here that these simpler approximations apply and that the right hand side of Equation 1.50 provides a good estimate of the contact resistance. This requires that the contact junction have a sheet resistance satisfying the equation:
Rsd ! rsc =4L2c
With these reasonable simplifying assumptions, in order for the contact resistance to contribute less than 5% of the device resistance one must have
Rc W x
rsc 1 % R W 0 rsc % 0:05ðRdsat WÞLc Lc 20 dsat
For the estimates of device resistance in Figure 1.28, and estimated values of contact length, limits on the allowable contact resistance can be obtained. For this, we can estimate the contact length as approximately two times the MPU half-pitch, which is the same as the technology node. Figure 1.29 shows the resulting required contact resistance values from this estimate for technology generations from 90- to 16-nm using the 2004 ITRS estimates of parameters and of saturation current. The values are essentially the same as those presented in the 2004 ITRS. The values are seen to be somewhat lower for n-channel devices as expected due to the larger saturated current of an n-channel device. The values range from the around 1!10K7 to the upper 1!10K9 O-cm2. These are very low
Contact resistance (Ω - cm2)
10−6 Upper limit values for 10% Contribution to device resistance 10−7
p-channel devices
n-channel devices
2004 ITRS Idsat values used 10−9
Estimated allowable source/drain contact resistances for scaled devices.
values and achieving such low contact resistances remains one of the major challenges of future MOS devices contacting structures. To carry the analysis one step further, the contact resistance is typically assumed to be due to tunneling through the barrier between a metal (or silicide acting as a metal) and a heavily doped semiconductor. For such a model,
" rsc f exp
# pffiffiffiffiffiffiffiffiffiffi 3s m fB pffiffiffiffiffiffi h NB
In this, the important material parameters are the metal-semiconductor barrier height fB and the semiconductor doping density near the barrier NB. A small contact resistance requires a small barrier height and/or a large doping density. For typical silicides on silicon, the barrier height is close to half the bandgap due to pinning of the Fermi level near the center of the bandgap. With a barrier height of around 0.5 V and for other silicon parameters, the predicted contact resistances for doping densities of around 2!10 20 is around 1!10K7 O-cm2 [44]. This is consistent with the best contact resistances experimentally achieved with metal (or silicide) contacts on silicon. However, considerably lower values are needed for scaled MOS devices with projected values more than 10 times smaller required for the end-of-roadmap devices. Considerable research work is underway on techniques for achieving the required low contact resistances. The most promising approaches involve the use of SixGe1Kx (SiGe) as an interface material between the silicon contact junction and the silicide or metal contact. The primary advantage of SiGe for this application is the lower bandgap, which can result in much lower contact resistances as predicted by Equation 1.53. Another advantage of SiGe is that the maximum doping density has been shown to be larger than that for pure Si and large doping densities can be achieved at low temperatures [45–48]. The optimum Ge concentration for low contact resistances appears to be in the range of 20%–30% and contact resistances as low as 1!10K8 O-cm2 has been demonstrated on both n- and p-type material [45–48]. Achieving the required values of drain extension and contact resistance is one of the major challenges of future MOS transistors. One modification to the basic device structure that helps these resistance values is the raised or elevated source/drain structure as shown in Figure 1.30. In this approach, the heavily doped drain contact is elevated above the original surface by using a selectively grown epitaxial layer. A silicide layer is formed on top of the epitaxial silicon layer either by selective deposition or conventional reacted metal. The structure has several advantages for aggressively scaled devices. First, the spacer oxide can be thinner than in conventional structures and this can greatly reduce the extension resistance as previously discussed. Second, the nC contact layer can be sufficiently thick to contain the silicide layer without an excessively deep contacting junction or without excessive junction leakage. Third, the selective layer can potentially be heavily doped during growth to obtain a low contact Spacer
Silicide n+ Selective epitaxy layer n+ Body
Illustration of the major components of an elevated source/drain contacting structure.
resistance. A final potential advantage relates to the possible mechanical stress that can be incorporated into a transistor from the SiGe contact structure. This is discussed in a subsequent section. However, a disadvantage of the elevated source/drain contact structure is that two selective epitaxy processes are required for both n- and p-channel devices since for CMOS both types of devices are required. The elevated S/D structure is expected to become essential for the ultimate scaling of MOS devices. Also associated with the source/drain structure is a parasitic source and drain-to-substrate capacitance. To minimize this capacitance, the length of the contacts should be as small as possible. However, the overriding factor is probably the contact resistance so that one cannot reduce the contact length and the parasitic capacitance must be accepted. One means to reduce the parasitic capacitance is the use of SOI wafers and the advantages of such structures are explored in a subsequent section. Because the source/drain resistances do not scale with the fundamental device dimensions in the same manner as device current, the source/drain resistances are major potential barriers to achieving the ultimate performance of scaled MOS devices. Creative structures and approaches will be required to extend scaling to the ultimate dimensions. The elevated source/ drain structure with heavily doped SiGe contact layers is one such approach.
Substrate and Isolation Issues
The substrate and isolation refers to those components of the integrated circuit that provide electrical isolation between the devices and prevents undesired device interactions such as latch-up in CMOS. Isolation has conventionally been achieved by the LOCOS structure. However, because of well-known scaling problems, such as large "'birds beak"' regions, new isolation techniques such as trench isolation have become essential for highly scaled CMOS. The 2004 ITRS assumes that shallow trench isolation (STI) will be the standard isolation technology for highly scaled CMOS. There do not appear to be major barriers to implementing implement trench isolation such as shown in Figure 1.31, although there are always technical challenges in performing fine line etches with high aspect ratios and uniformly filling with an insulator. The ability to implement improved isolation is essential to achieving the full benefits of increased scaling in terms of increased packing density. Latch-up control is expected to become less of a problem as operating voltages decrease and for voltages below 0.6 V should no longer be a problem.
Thermal Budget Issues
The scaling of MOS devices to ever thinner device layers necessitates going to lower thermal budget processing achieved by lower temperatures and/or shorter processing times. Some estimates of allowed thermal budgets can be made based upon expected device layer thicknesses. For example, the channel doping profile for a retrograde doping structures must not be deeper than the source/drain junction depth. Also the source/drain extension junction must be very shallow to control short-channel effects. These junctions must be considerably less than the feature size. If we make the assumptions that the peak
n+ poly
(STI)
n-FET
p+ poly n+
p+ (STI)
p-well
p-FET
p+
n-well Shallow trench isolation
Shallow trench isolation.
doping densities are approximately 100 times the background doping density and that 50% of the junction pffiffiffiffiffiffiffiffi depth can arise from diffusion, one can establish a maximum allowed value of the quantity 4Dt which is approximately 0.23XJ, where D is the impurity diffusion coefficient and t is the time at which diffusion occurs. This is essentially the amount of allowed diffusion, which ranges from approximately 4.7 to 0.8 nm at the 90- and 16-nm nodes. D is typically modeled as a function of temperature with two parameters D0 and E as:
D Z D0 expðKE=kTÞ
Figure 1.32 shows allowable times at different temperatures for the 90- to 16-nm technology nodes based upon the above defined amount of junction diffusion and previously given diffusion coefficient values [49]. Curves are shown for B and As impurities, but results for P are very close to B and results for Sb are very close to As. Results are shown for temperatures of 9008C and below as results for 10008C are probably too short to be practical for the device dimensions in these generations. While there may be some variations from the values depending on the amount of allowed diffusion, these values do not include any transient enhanced diffusion rates, which may reduce the allowed diffusion times ever further. These results illustrate the need for low thermal budget processes for ultra scaled MOS devices. For the same total process time, the temperature has to be reduced by more than 100oC in moving from the 90- to 16-nm nodes. Such low thermal budgets will also push processing toward single wafer, rapid thermal processing steps and will place much more emphasis on the control of transient enhanced diffusion processes. Limitations on the allowed processing temperature will become more of a concern as devices are scaled to ever smaller dimensions. This coupled with the very shallow layers with required very high doping densities will make ion implantation followed by annealing, more problematic for future devices. The times presented in Figure 1.32 do not appear to be sufficient to provide dopant activation and simultaneously to suppress transient enhanced diffusion. At some point other doping technologies will be required to achieve and maintain the required doping profiles. Possible alternative doping techniques include: (1) low temperature (8008C or less) epitaxy (or selective epitaxy), (2) diffusion from a doped glass source, (3) diffusion from a low temperature Ge/Si alloy which can be subsequently etched, (4) direct gas source diffusion in an rapid thermal processing (RTP) system, (5) gas immersion, laser diffusion (GILD), and (6) planar doping layers using atomic layer epitaxy. Of these many possibilities, low temperature 106
Time at temperature (S)
As (or Sb) 700°C
800°C 800°C
900°C B (or P)
For sqrt(4Dt) =0.22 XJ 90
FIGURE 1.32 not included.
Limits to thermal budget for As and B with future device generations. Transient enhanced diffusion is
epitaxy will probably find a major role as it will also probably be required for elevated source/drain structures for low resistance contacts as discussed in the previous section. With low temperature epitaxy, thin heavily doped layers can be achieved that are very difficult if not impossible to achieve by other techniques. However, with selective epitaxy, separate hard masking is required for making both n- and p-type S/D regions. GILD with projection masking (PGILD) does not require resists or hard masking and may become an important doping technology. Regardless of the doping technique, obtaining the required shallow junctions and very heavily doped regions will be a major challenge for scaled technologies. Silicon on insulator as discussed in the next section may also offer some advantages over bulk MOS in this regard.
Advanced MOS Device Concepts
While bulk CMOS has been the standard technology for many device generations, new substrate and device concepts may be essential to achieve the ultimate scaling of MOS devices. Some of the most promising approaches being explored are briefly discussed in this section.
SOI Substrates and Devices
The possible switch of substrate material to SOI at some future point may be essential for achieving the ultimate MOS device dimensions. Silicon on insulator devices have already been used in some applications for improved speed of operation. In SOI, the MOS devices are formed within a thin silicon layer formed by various techniques over an insulating layer (typically oxide or oxynitride). From the MOS device point of view, two types of situations can exist. If the semiconductor layer is sufficiently thick that the surface depletion layer under the gate terminates within the silicon layer, the device is a partially depleted (PD) device. If the silicon layer is sufficiently thin such that the silicon material under the gate is fully depleted (FD) before the inversion layer forms, the device is a FD device. In PD SOI, even though the material under the gate is only PD, the source/drain junctions can extend through the silicon layer giving reduced parasitic capacitances and higher operating speed for a given technology generation. Device isolation and latch-up control are simplified for SOI with fewer processing steps required. This can potentially offset the higher substrate costs and potentially lower yield. From a device viewpoint, there are some drawbacks to PD SOI due to a floating body effect. To eliminate such effects, a contact is required to the body increasing somewhat the area associated with a given transistor. However, a separate body contact can be of advantage in some logic approaches where threshold voltage switching is used with a separate body voltage. A major advantage of an SOI substrate is that the depth of the contacting source/drain junctions can be controlled by the thickness of the silicon layer over the oxide layer. This applies to both FD and PD devices and is in one way, the shallow junctions required for deeply scaled MOSFETs can be achieved. For PD devices, this is the major advantage of an SOI substrate as the device characteristics and scaling properties are essentially the same as for the bulk MOS devices. Most of the potential advantages and limitations of FD SOI devices are very similar to DG MOS devices as discussed in Section 1.5.2, so a discussion of the FD MOS device is combined with the DG device. The discussion there will show that the feasibility of FD SOI devices is questionable at the 90 nm and below technology generations because of excessive short-channel effects. One disadvantage of the SOI wafer is the power dissipation capability, which is less than a conventional Si wafer because of the poorer thermal properties of an oxide layer. For HP circuits with a high percentage of active devices, this can be a major disadvantage as power dissipation is becoming more of a limiting factor for scaling as discussed in section 1.3.2.
Multiple Gate MOS Devices
Considerable research and modeling has been performed in recent years on multiple gate MOS devices. One of the most extensively studied multiple gate devices is the DG device shown in simplified form in
Drain Top gate
Thin channel
Bottom gate
FIGURE 1.33 structure.
Simplified schematic of dual gate MOSFET structure. Wrap around gate device also has similar
Figure 1.33. The structure consists of a thin conductive channel sandwiched between two control gates consisting of dielectric and gate contact material. Heavily doped source and drain regions extending slightly under the gates make contact to the inversion regions. The DG device is typically assumed to be sufficiently thin as to constitute a FD region within the semiconductor channel. A major advantage of the DG device is that the current drive can potentially be twice as large as that of a single gate device since an inversion layer can exist near both the gates. For very thin channels, these two charge layers can merge into a single conductive layer within the channel. The practical fabrication of such DG devices is very difficult and no universally accepted technique has been developed for such structures. Some techniques attempt to fabricate such structures using a planar arrangement in which the channel length and width are in the plane of the silicon wafer. This has many advantages in that the W and L device ratio can be controlled by the lithography in much the same way as conventional MOS devices. However, forming the dual gates above and below a planar thin silicon channel is very difficult, especially in obtaining exact alignment of the two gates. Such techniques typically use some form of SOI layer for the thin silicon channel. Other fabrication approaches, move the plane of the conductive channel out of the wafer surface and into the vertical direction or perpendicular to the wafer surface. The so called "finfet" is one such example, where the width dimension of the channel is taken in the vertical direction [50,51] with the channel length parallel to the wafer surface. (Also similar to the DELTA FET [52]). The gate then typically wraps around the top of the channel. Variations of this approach are the "tri-gate" device, where the channel width is increased and the gate occurs on the top and two sides of the channel. Another approach is to place the channel in the vertical direction with current flow in the vertical direction from a bottom source contact to a top drain contact. In this approach, the gate can completely surround the channel giving the so called "gate-all-around" or "surrounding-gate" device. All of these multiple gate devices have somewhat similar properties and similar advantages and disadvantages. The dual gate structure will be discussed here as an example of all such multiple gate devices. For the DG structure as in Figure 1.33 important properties are the control of threshold voltage and short-channel effects. This structure has been extensively studied theoretically [33–37,53] and the exponential decay factor for controlling short-channel effects has been shown to be
sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 3si 3 t 1 C ox si tsi tox lZ 23ox 43si tox
It has been reported that short-channel effects are acceptable, if Leff/2lO3. If we use this value in Equation 1.39 to estimate threshold voltage reduction, this value is consistent with a threshold voltage reduction of about 0.12 V, where 0.1 V is sometimes taken as a limit on acceptable short-channel effects.
From the above limit, an equation for the upper limit on silicon thickness can be obtained as
2sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 3 23si tox 4 1 3ox Leff 2 1C K15 tsi % 3ox 18 3si tox
For a given effective channel length and oxide thickness, this can be used to estimate the allowed thickness of the silicon layer. However, before computing such values, some thought should be given to the oxide thickness term. This equation was derived without consideration of any second order effects such as Quantum size effects, which cause the inversion channel to not be located at the oxide interface, but some distance into the silicon. Also the derivation did not consider the possible use of high-k gate dielectrics. The latter effect can be taken into account by using the EOT value, since tox always appears divided by 3ox. For oxide thickness, it is probably most appropriate to replace the tox term by the inversion capacitance oxide thickness value (tciv as used here) to thereby correct for quantum size effects. Figure 1.34 shows predicted limits on silicon thickness for the 90- to 16-nm technology nodes. Two limit curves are shown, one using tciv and one using tox in Equation 1.56. While both show similar trends, the limit for tciv is slightly smaller than for tox as would be expected. Regardless of which limit is used, the most striking results is the very small value of the required silicon thickness, which ranges from approximately 5–7 nm for the 90-nm node, to approximately 0.4–0.7 nm for the 16-nm node. However, these values are consistent with other published results. For example, it has been published in Ref. [29] that a 5-nm Si film with a 1.5-nm oxide can be scaled to a channel length of about 20 nm. These three values are all consistent with the 65-nm node data in Figure 1.34. Other researchers have suggested that the thickness of a Si layer may be somewhat thicker than shown in Figure 1.34 as determined by the above analysis. For example Doyle et al. suggest that an acceptable relationship for DG devices is tsi!2Leff/3 [54]. This limit is about a factor of 2 larger than the values seen in Figure 1.34. Such a value would extend the range of possible DG devices, but at the expense of larger short-channel effects. Other curves shown in Figure 1.34 for reference are the effective channel length and the two possible values to use for oxide thickness. Also shown in the figure is a horizontal line at approximately 3 nm indicating that for Si thicknesses below this value quantum box effects must be considered. This arises because the width of the surface inversion layers is on the order of 3–4 nm in Si with holes having a slightly broader distribution than electrons [55]. When the thickness of a semiconductor layer 102 Double gate silicon thickness estimates
Thickness (nm)
Leff 101
tsi using tox tsi using tciv
Quantum box effects
tciv
tox Surround gate Si thickness can be about 1.4 times thicker Single gate SOI about 2 times thinner 10−1
Thickness of Si for double gate (DG) MOSFET needed to control short-channel effects.
approaches this value, quantum size confinement effects will begin to exist. This will cause the energy level for the conduction electrons (or holes) to increase and for the required device threshold voltage to increase. Because of this, it has been projected that it will not be practical to use channel thicknesses very much below approximately 5 nm [29]. This is a very serious potential problem and makes the projections for using DG devices beyond about the 45-nm node very questionable. In the previous section, the possibility of FD single gate MOS devices on SOI was discussed. In many ways, a single gate FD device on SOI looks like one half of a DG structure. If one splits the DG device along the center line parallel to the gate oxide and replaces half of the device by a thick oxide one has essentially a SG SOI device. It might then be expected that the FD SOI single gate device would have essentially the same limits as shown in Figure 1.34 for silicon thickness. However, the limits are not quite these, but are more restrictive. For a FD SOI device, there is an additional feedback path from the drain to the gate through the thick oxide at the bottom of the channel. This causes the short-channel effects to be more severe than for the DG structure. Several investigators have shown that the short-channel effects for single gate FD device occur at about twice the channel length as for the DG FD device. Thus, for single gate SOI devices the allowed silicon thickness can be taken as approximately one-half the values given in Figure 1.34. This makes the values very small and brings into question the feasibility of FD SOI devices at 90 nm and below. A major difference between bulk CMOS devices and SOI and the DG device is the ability to compensate for some of the short-channel effects by the use of overlapping halo implants with bulk CMOS. To achieve a similar effect with DG devices would require some type of lateral variation of channel impurity density in DG devices. This might be possible in vertical-channel devices where the vertical channel is etched from within a deposited semiconductor layer, but would seem to be very difficult to achieve in most DG devices structures. The discussion has so far been on the DG device where much theoretical work has been done. For other multiple gate device structures, such as, the tri-gate, finfet, or surround gate device structure, the thickness of the allowed silicon structures may be slightly larger than for the DG structure. An estimate can be provided by the cylindrical FD device structure, where it has been shown that the natural scale length is about 30% smaller as compared with the DG structure. This means that the silicon thickness for a cylindrical gate device can be about a factor of 1.4 larger than for the DG structure. The short-channel properties of MOS devices are controlled primarily by the aZLeff/2l parameter. This was discussed earlier for bulk MOS devices in connection with the threshold voltage reduction and DIBL. For FD devices, it has been shown that [35]
S xðkT=qÞlnð10Þ
1 1K2expðKLeff =2lÞ
This has also been shown to apply approximately to the surround gate device, which represents a limiting case of a multiple gate device. A plot of this equation is shown in Figure 1.35. For FD devices the long-channel value of subthreshold slope approaches the ideal value of approximately 60 mV/dec. As the figure shows, the value degrades rapidly for values of Leff/2l less than about 3.0, which represents the limit used in estimated the allowed value of Si thickness in Figure 1.34. The threshold voltage reduction due to short-channel effects can be estimated with the same equations as previously used (see Equation 1.39). This gives the predicted short-channel effect shown in Figure 1.36, which shows three curves for different drain voltages. Again the predicted threshold voltage decreases rapidly for Leff/2l less than about 3.0. These theoretical curves are very similar to the published results obtained by much more complete two-dimensional numerical simulations of FD MOS devices. Although, there may be some uncertainty in the exact value of Leff/2l at which a given value of threshold voltage reduction occurs, this curve should provide a reasonable first order estimate of the effect. Also shown as a vertical line is the limit used to establish an upper limit on Si thickness of FD devices and this is seen to occur at a threshold voltage reduction of about 0.1 V, which is probably a reasonable value when the actual threshold voltage must be on the same order of value.
Handbook of Semiconductor Manufacturing Technology 100 Subthreshold slope (mV/dec)
Theory for DG and SG SOI Values for surround gate are slightly lower
60 Limit used for estimating silicon thickness 50
Leff/2l
Variation of DG subthreshold slope factor on normalized effective channel length.
For FD devices, the long-channel threshold voltage has been estimated as [37]
VT Z
8 qN t t A si ox > > > < 3
for single gate SOI
qNA tsi tox > > > : 23
for double gate
These represent simply the voltage required to fully deplete the Si layer. From this we can see that the accuracy of the threshold voltage depends on the accuracy with which the thickness of the Si layer can be controlled. For a 10% variation in threshold voltage, the Si layer thickness needs to be controlled to about 10%, i.e., for a 5-nm Si layer the thickness control must be about 0.5 nm [29]. Such requirements of tight thickness control coupled with the very thin layers will prove very difficult to meet for future devices. 0.1 0.0
Solid line is VDD = 1V
∆V T (V)
VDD = 2V
−0.2 −0.3 −0.4 −0.5
Limit used for estimating silocon thickness 0
L eff/2l
Variation of DG MOSFET threshold voltage on normalized effective channel length.
At present, the most promising techniques for producing SOI layers are SIMOX, Smart Cut and Bonded Wafers. All of these have great difficulty in obtaining such thin layers with the thickness control projected as needed for future MOS devices. Some fundamental breakthroughs are needed in fabrication thin layers for FD SOI devices as well as for multiple gate devices. The most recently researched multiple gate devices, such as the finfet or tri-gate devices do not alleviate the requirement of ultra-thin Si layers for FD devices. For such devices, the thickness of the Si fin used in fabricating the devices must satisfy the same requirements as a DG device. This means that to control short-channel devices, the thickness of the Si layer must be considerable less than the channel length as indicated in Figure 1.34. In fact, the channel thickness must be four to five times less than the channel length. In most of the out-of-plane multiple gate device concepts, the channel thickness must be controlled by an etching process with this minimum width controlled by the lithographic process. This means that the channel length must be four to five times larger than the minimum lithographically defined dimension. This will greatly limit the current capability of such devices and may in fact completely offset any current enhancement advantage of such multiple gate devices. Another problem with out-of-plane MOS devices is that one does not have control of both L and W by the lithographic process, but one of these is controlled by the thickness of some Si layer. This makes it very difficult to adjust the W/L ratios as needed to compensate for the lower mobility of holes and to compensate for the delay times of various logic gates as well as adjusting this ratio for various analog applications. The W/L ratio can only be adjusted in steps by using multiple devices again offsetting some of the advantages of multiple gate devices. Other major problems with existing techniques for producing SOI material is the degradation in material quality with thin layers. Most experimental results have shown a degradation in carrier mobility when the SOI layer thickness is reduced below about 10 nm [29]. While it is uncertain if this is just a material quality problem or a fundamental problem with increased scattering processes, it remains a serious problem with existing SOI techniques. For the reasons outlined above, multiple gate FD MOS devices face very formable obstacles in competing with bulk MOS devices. Controlling short-channel effects require very thin FD Si layers with respect to channel length and manufacturing techniques for producing such thin layers are not available with electrical properties comparable to bulk Si. Breakthroughs will be required in the manufacture of such multiple gate devices, if they are to become the mainstream MOS devices. A final summary of some of the multiple gate MOS concepts is shown in Table 1.3 along with some of the potential advantages and weaknesses.
TABLE 1.3 Concept
Summary of Some Multiple Gate FET Concepts Tied Gates (NgatesO2)
Side Wall Conduction (Finfet, Tri-gate)
Double Gate, Planar Conduction
Higher Id and thicker fin
Particular strengths
Thicker Si body
Higher Id, improved S, and improved SC effects Ease of integration
Potential weakness
Limited device width and corner effects
Higher Id, improved S, and improved SC effects Bulk compatible and good Si thickness control Limited width
Fin thickness and shape
Independent, Double Gate, Planar Conduction
Vertical Conduction, Wrap Around Gate
Improved SC effects
Improved SC effects and 3D integration
Electrically adjustable threshold voltage Difficult integration and degraded S
Litho independent gate length Single gate length process integration
Source: Selected from 2004 International Technology Roadmap for Semiconductors, http://www.itrs.net/Links/2004Update/ 2004Update.htm
Transport Enhanced MOS Devices
One technique for enhancing the current capability of MOS devices at small dimensions is the application of appropriate mechanical strain to the silicon channel region [56–60]. Mechanical strain causes important changes in the internal band structure of the Si. Figure 1.37 illustrates some of the important changes in the bands [60]. For the conduction band, strain splits the sixfold degenerate energy bands along the 100 crystal directions into two groups of bands. With sufficient strain, all the electrons can be transferred essentially into the lower group of bands and if transport is along the appropriate crystal direction, the electrons will behave along the channel as if they had a smaller effective mass than for the unstrained Si. For the valence band, strain again splits the degenerate heavy and light hole bands into two bands with each band having a smaller effective mass than the heavy hold band in the unstrained Si. The most effective type of stress depends on the direction of stress relative to the MOS channel, and for p-channel devices should be compressive stress along the channel length dimension or tensile stress along the width dimension. For n-channel devices, the stress should by tensile stress along either channel direction. The smaller effective mass of electrons or holes resulting from the splitting of the degenerate energy bands can enhance carrier transport along the channel. A very simple illustration is for the carrier mobility, which can be expressed in the most basic form as
qhti m
where hti is the mean time between scattering events and m* is the effective mass. A smaller effective mass in this equation will result in a larger mobility. This is somewhat oversimplified as the mean time between scattering events may also depend on effective mass. However, for Si, the net result of appropriate mechanical stress is to give an enhanced low field carrier mobility and this has been experimentally Unstr. Si
Conduction band ∆2 Valleys
Strained Si ∆4
∆6
∆4 Valleys
mt < m I
mt mt Strained Si
Valence band Bulk Si
E out-ofplane
∆E ≤ 38
10%Ge
LH Spin-orbit
FIGURE 1.37 Effects of Si strain on energy bands. (From Ieong, M., B. Doris, J. Kenzierski, D. Rim, and M. Yang, Science, 306, (2004): 2057.)
verified for both electrons and holes. The mobility enhancement factor has been found to be as large as 1.83 for electrons and 1.53 for holes at low fields [56–60]. Just as important as mobility for determining current drive is the saturated drift velocity of electrons or holes. The saturated drift velocity arises physically because of the rapid generation of optical phonons when the carrier energy in a high electric field exceeds the optical phonon energy (Eopx0.05 eV for LO phonon). A somewhat oversimplified model for the saturated drift velocity predicts [61]
rffiffiffiffiffiffiffiffiffiffiffiffiffi 8Eop vsat x 3pm
From this, one can see that a reduction in the effective mass should result in a larger saturated drift velocity. From the device model in Section 1.3.2, one can see that a larger low-field mobility and a larger saturated velocity will both contribute to a larger device current for all other parameters remaining fixed. The application of mechanical stress will likely become a standard technology to enhance device current as devices are pushed to ever smaller dimensions. Reported results indicate that the MOS drive current can be enhanced by 15%–25% with the use of mechanical stress. There are several possible ways by which mechanical stress can be obtained in MOS devices. One approach uses a stress relaxed SiGe layer between a Si device layer and a Si substrate. When the SiGe layer is sufficiently thick, the stress will relax in the layer producing a SiGe layer with a lattice constant larger than that of pure Si. When a sufficiently thin Si layer is then grown expitxially on top of the SiGe layer, the resulting Si lattice will seek to match that of the SiGe layer giving a larger lattice spacing in the plane of the film and a Si film under tension. Other possibilities for stress include deposited films of various types that are under stress at room temperature, such as nitride films. For optimum p- and n-channel devices, the p-channel device should be under compression, while the n-channel device should be under tension. One attractive means of accomplishing this has been reported (by Intel) and consists of separate approaches for the two types of transistors [62,63]. For the p-channel device, a SiGe layer is selectively grown in the source/drain regions of the transistor. Since, the SiGe layer has a larger lattice constant, it tends to expand in the source/drain region putting the Si channel under uniaxial, compressive strain. For the n-channel devices a high tensile silicon nitride film is deposited over the top of the transistor resulting in a uniaxial, tensile strain in the n-channel device [62,63]. There are certainly questions as to how well such techniques will work for multiple-channel length devices, but strain optimization will probably be an important tool in the future device designer's toolbox.
MOSFETS with Other Semiconductors
Another possible approach to the enhanced transport is to move to another semiconductor such as SiGe alloys for the active region of the MOS devices. Other more exotic semiconductors such as InSb (with very high mobilities) may also be considered. These are certainly research issues to be pursued. However, one must not just look at carrier mobility, but at such parameters as saturated drift velocity which is probably more important than low field mobility. For Ge, the saturated drift velocities are known to be lower than for Si because of a lower optical phonon energy (see Equation 1.60). The use of SiGe with a small Ge concentration might give an enhancement from mobility before the loss due to lower velocity saturation occurs, but this is not obvious. For any move away from Si as the channel material, obtaining an acceptable gate dielectric will also be a formable task. Because of all the multitude of problems with any alternative semiconductor it is not clear that such concepts for enhanced transport will be practical in the real world or for cost competitive CMOS ICs.
Advanced Semiconductor Device Concepts
As Si CMOS devices are scaled to their ultimate limit in size, there is continued and growing interest is exploring new semiconductor device concepts that might have lower size limits or lower power
requirements that could continue the integration of electronic functions to even greater densities and higher performance. While there is no guarantee that such efforts will be successful, they must be pursued so that all possible avenues for extending the electronics revolution beyond the fundamental Si limits can be explored. Viewed in the broad context, MOS devices are charge-based devices. A gate voltage controls the conductive charge in the MOS channel. As such, all charge-based devices are limited by the capacitance, voltage and current capability. This is captured succinctly in the CV/I term related to switching speed. All charge-based device concepts will have somewhat similar limitations and it is difficult to envision other materials and physical arrangements of charge-based devices competing with Si-based MOS devices both from a significant performance advantage and from a cost perspective. Thus, advanced device concepts for beyond Si MOS limits are probably best sought in device concepts that are not charge-based device concepts. Some of the most important avenues are 1. Molecular and biological-based devices. In these concepts the properties of individual molecules are used for transport and charge storage. Potential advantages are the small possible size of individual molecules, which might constitute a single device. 2. Spintronics. These concepts seek to use the properties of spin with its two quantized states to represent and process information. Potential advantages are the storage and manipulation of information on a single electron. 3. Quantum interference devices. Involves concepts for performing logic operations using the wave nature of electrons and the quantum interference effects between electron waves. Again the potential advantage is the potential size of devices. 4. Phase change devices. This broad classification involves using phase changes to store and process information such as, crystalline-amorphous, magnetic-nonmagnetic, or metal-insulator phase changes. Potential advantages are breaking the dependence on charge-based concepts. 5. Optical switches. Involves concepts to use photons for information processing and storage instead of electrons. Another non charge-based approach. Much research is needed in any of these areas to bring forth alternative device concepts that can successfully compete with Si-based MOS devices. Some of the most promising non-MOS device concepts are summarized in Table 1.4. Some of these are still charge-based devices that have potentially smaller size TABLE 1.4
Summary of Some New Device Concepts
Supported architectures
Cell size (pitch) Density (#/cm2) Switch speed Circuit speed Switching energy (J) Binary throughput (Gbit/ns/cm2) Operating temperature
1D such as Carbon Nanotube
Resonant Tunneling Devices
Conventional Conventional and cross Cellular bar Neural Networks (CNN) 100 nm 100 nm 3!109 3!109 Unknown 1 THz 30 GHz 30 GHz 2!10K18 O2!10K18 86 86 RT
Single Electron Molecular-Based Quantum Devices Devices Cellular Automata (QCA)
Spin-Based Transistors
Memory based
QCA
40 nm 6!1010 1 GHz 1 GHz 1!10K18 10
Unknown 1!1012 Unknown Unknown 1.3!10K16 Unknown
60 nm 3!1010 30 MHz 1 MHz O4!10K17 0.06
100 nm 3!109 700 GHz 30 GHz 2!10K18 86
RT or cryogenic
Cryogenic
Source: Selected from 2004 International Technology Roadmap for Semiconductors, http://www.itrs.net/Common/ 2004Update/2004Update.htm
limits than MOS devices and some are new non charge-based device concepts. In all cases, any new device must provide very low power, be compatible with high levels of integration at very low cost and must provide logic level gain in a three-terminal device. Since, relatively little is known about how such devices could be integrated in large numbers, many of the entries in the table must be taken as best estimates. Only the future will tell if any of these devices will replace MOS devices or find a role in complementing MOS devices.
It is obvious that Si MOS devices will be pushed to their ultimate limits of scaling. Exactly what technology generation is the ultimate limit for Si devices is somewhat debatable and many experts in the past have predicted the premature demise of scaled Si MOS devices. History has proven that Si MOS device concepts can be pushed much further that most experts envision at any particular point in time. However, there are limits both from a physics point of view and perhaps from an economic point of view. As discussed in previous sections, the golden era of easy scaling has passed and scaling beyond about the 90-nm node becomes increasingly difficult and increasingly requires more new materials and innovative concepts for continued scaling. Scaling may continue to the end of the roadmap (in about 2018) or scaling may simply become too difficult or too costly to continue to the end of the roadmap. In any case, scaling Si MOS devices to the 16-nm node will require significant innovative concepts to achieve the predicted dimensions and device performance. To achieve the ultimate limits of semiconductor devices the general trends in manufacturing must certainly be toward ever thinner dimensions in all vertical as well as all horizontal dimensions. This in turn of necessity must push manufacturing toward lower thermal budget processing. At the same time from economic reasons, manufacturing is pushed toward larger wafer sizes. The continued downsizing of MOS devices will require that many new materials such as, high-k gate dielectrics and metal gates be introduced into the manufacturing process. New processes, such as selective epitaxy and selective depositions will be required. Device structures will require the control of interface layers, such as the dielectric–silicon interface to atomic dimensions. Such control will in turn require higher levels of automation in the manufacturing process and more in-situ monitoring of the manufacturing process. Although the continued scaling of MOS devices is becoming more difficult, the IC industry appears equal to the task of pushing MOS devices to the ultimate limits at near atomic dimensions.
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Overview of Interconnect—Copper and Low-k Integration Girish A. Dixit Robert H. Havemann Novellus Systems, Inc.
2.1 Introduction.......................................................................... 2-1 2.2 Dual Damascene Copper Integration ................................. 2-6 2.3 Copper/Low-k Reliability................................................... 2-16 2.4 Conclusion .......................................................................... 2-19 References ....................................................................................... 2-20
Over the past decade, integrated circuit scaling and performance needs have driven significant changes in interconnect materials and processes at each successive technology generation. Foremost among these changes has been the transition from aluminum to copper conductors [1–7]—a transition that is virtually complete for logic devices and now underway for memory devices [8,9]. The primary impetus for this ongoing transition has been a need for the improved performance afforded by copper's lower resistivity as compared with aluminum as well as by copper's ability to accommodate higher current densities. The need for improved performance has also driven a concomitant change in the insulator surrounding the conductor, which for logic devices has transitioned from the traditional silicon dioxide dielectric to materials with lower dielectric constant (low-k), such as F-doped oxides and C-doped oxides. The simultaneous integration of copper with low-k dielectrics presented a significant challenge to the industry, and, while the manufacturing use of copper interconnects has become pervasive, each successive technology generation offers new challenges in terms of meeting density, performance, and reliability requirements. This chapter will provide an overview of copper and low-k interconnect integration including process architectures, materials, performance, and reliability issues as well as future scaling challenges and potential technology directions.
The Information Revolution and enabling era of silicon Ultra-Large-Scale-Integration (ULSI) have spawned an ever-increasing level of functional integration on-chip, driving a need for greater circuit density and higher performance. For classical transistor scaling, device performance improves as the gate length and the gate dielectric thickness are scaled. Only recently have new materials, such as high-k gate dielectrics and metal gates been considered as essential for continued transistor scaling. In contrast, as the chip wiring (interconnect) is scaled, performance degrades as both resistance and current density increase due to the smaller cross-sectional area of the scaled conductor. The introduction of copper metallization served as an enabler for continued interconnect scaling due to its lower resistivity 2-1
(w1.8 m-ohm-cm) as compared with traditional AlCu metallization (w3.3 m-ohm-cm) as well as its ability to accommodate higher current density [10,11]. An additional consequence of scaling is an increase in sidewall capacitance as conductors are placed in closer proximity to one another. While metal thickness can be reduced to mitigate the increase in sidewall capacitance, the consequences of this approach are increased resistance and current density. Alternative circuit design solutions, such as increasing conductor spacing and/or adding extra levels of interconnect with relaxed design rules, have the drawbacks of reduced density and increased cost. The introduction of low-k dielectrics provided a materials solution that mitigated sidewall capacitance [12–18] and provided more latitude in the co-optimization of process architecture and circuit design. Previous analyses [19–25] have highlighted the interconnect performance issues that are incurred as integrated circuit design rules continue to scale. As illustrated in the International Technology Roadmap for Semiconductors (ITRS) (see Figure 2.1), a chief concern is the increasing latency or ResistanceCapacitance (as in RC delay of inverter circuit) (RC) delay of global wiring [26,27]. Since local and intermediate interconnects tend to scale in length, latency is dominated by global interconnects connecting large functional logic blocks, as shown in Figure 2.2. Future increase in microprocessor chip size predicted by the ITRS [27] bring heightened concern, since interconnect latency is proportional to the square of the length. While design solutions such as the use of repeaters (as shown in Figure 2.1) or reverse scaling may mitigate latency in the near term, these approaches typically result in larger chip size and/or more levels of interconnect, leading to higher product cost. For local and intermediate wiring levels, crosstalk is an additional interconnect performance issue that must be considered. Signal crosstalk is given by the ratio of line-to-line (sidewall) capacitance to total capacitance as shown in Figure 2.3. As transistor operating voltage continues to scale downward, interconnect crosstalk and noise levels must be reduced to avoid spurious transistor turn-on. Since crosstalk is dominated by interconnect sidewall capacitance (as is overall capacitance for minimum feature size as shown in Figure 2.3), process-related solutions, such as the use of thinner metallization 100
Reference: R. Ho & M. Horowitz Gate delay (fan out 4)
Global wire signal delay increases with scaling
Local (scaled)
Relative delay
Global with repeaters Global w/o repeaters
Repeater insertion reduces global delay
Local wire signal delay improves with scaling 0.1 250
Process technology node (nm)
FIGURE 2.1 Relative delay for logic gate Fan Out (as in Fan Out of inverter circuit) (FOZ4) vs. both local and global interconnects as a function of technology node. (From Deodhar, V. V. and Davis, J. A., Tech. Dig. Int. Symp. Circuits Syst., V-349–V-352, 2003.)
Overview of Interconnect—Copper and Low-k Integration A chip
A more advanced chip
Macro circuit
Scaled macro circuit
Local wire in a macro Global wire between macros
FIGURE 2.2 Example scaling of global vs. local interconnects: length of global interconnects does not scale relative to chip size, whereas the length of local interconnects is reduced by the scaling factor.
Capacitance (×10–16 Farad/μm)
and/or low-k dielectrics must be implemented to enable continued scaling. This is yet another reason why copper and low-k dielectrics have become an essential part of the Integrated Circuit (IC) scaling engine. As operating frequency continues to increase power dissipation in the interconnect system, which is proportional to both switching frequency and capacitance, has become a significant portion of the overall power dissipated in the chip as shown in Table 2.1 and discussed in several recent papers [28–37]. Thus, the need to limit interconnect power dissipation provides yet another impetus for capacitance reduction in addition to latency concerns. Typical high performance designs utilize a hierarchical or "reverse scaling" metallization scheme (Figure 2.4), where widely spaced "fat wires" are used on an upper global interconnect and power levels to minimize RC delay and voltage drop. Maintaining power distribution at constant voltage through equipotential wires to all Vdd bias points requires increasingly lower resistance global wires as operating voltage continues to scale and switching frequencies increase. This need has been partially addressed by the introduction of ball-grid-array packaging technology [38–40] that Crosstalk ~ C L–L / (C L–L+ C L–G)
C L–L
C Total 2.0
C L–G
1.0 C L–G
0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Feature size (μm)
Line-to-line capacitance = C L–L Line-to-ground capacitance = C L–G
FIGURE 2.3 Simulation of interconnect capacitance as a function of feature size assuming fixed metal height and equal line/space. Line-to-line capacitance dominates as feature size decreases. Interconnect crosstalk is given by lineto-line capacitance divided by the total capacitance.
TABLE 2.1 Selected Overall, Technology Characteristics Based on the 2005 International Technology Roadmap for Semiconductors Year MPU (Microprocessor Unit) ⁄2 pitch MPU patterned gate length (nm) DRAM 1⁄2 pitch (nm) MPU: frequency of on-chip clock for high performance (MHz) MPU: frequency of chip to board for high performance (MHz) High volume-MPU (cost-performance) chip size at production (mm2) High volume-MPU (cost-performance) Mtransistors/cm2 DRAM memory chip size at production (mm2) DRAM memory chip Gbits/cm2 Maximum power w/high performance heat sink (watts) Maximum power (watts)—battery (Hand-held) Minimum logic Vdd—(maximum performance) volts Minimum logic Vdd—(lowest power) volts (battery power) 1
90 54 80 5204 3125 111
45 30 45 15,079 9536 140
174 88 1.22 167 2.8 1.1 0.9
276 110 1.94 189 3.0 1.1 0.8
32 21 32 22,980 18,625 140
1104 93 9.23 198 3.0 0.9 0.60
2209 93 18.46 198 3.0 0.8 0.50
4,417 93 36.93 198 3.0 0.7 0.5
Source: From International Technology Roadmap for Semiconductors, published by the Semiconductor Industry Association, 2005.
distributes individual power feeds across the chip. However, new packaging technologies will undoubtedly be required to alleviate the increasing level of power dissipation generated on-chip. Over the past decade, the aforementioned device scaling and performance needs have driven dramatic changes in interconnect materials and processes at each successive technology generation. While the motivation for moving from aluminum to copper metalization and from oxide to low-k dielectrics is clear, significant material and process innovation has been and will continue to be required to meet the interconnect goals set forth in the ITRS. A summary of key interconnect requirements from the ITRS [26] is shown in Table 2.2. The smaller feature sizes and higher aspect ratios projected for copper dual damascene structures necessitate thinner and more conformal metal barriers to prevent copper diffusion into surrounding dielectrics. While advanced physical vapor deposition (PVD) barrier/seed deposition technologies have proven to be extendable to at least the 45 nm technology node new metal deposition techniques, such as atomic layer deposition (ALD), will ultimately be required to achieve ultra-thin
FIGURE 2.4 Example of hierarchical interconnect architecture used in 90 nm node digital signal processor (DSP) (Courtesy of Texas Instruments).
Overview of Interconnect—Copper and Low-k Integration
TABLE 2.2 Selected Interconnect Technology Projections from the 2005 International Technology Roadmap for Semiconductors 2005
MPU ½ pitch
MPU gate length (nm)
Number of metal levels
Number of optional levels – ground planes/capacitors 2
Jmax (A)/cm – intermediate wire (at 105 C) Metal 1 (Cu) wiring pitch (nm)
4 8.91×105 180
4 5.15×106 90
Metal 1 A/R
Metal 1 barrier/cladding thickness (nm)
Cu thinning at minimum Metal 1 pitch due to erosion (nm), 10% x height, 50% areal density, 500 μm square array
Metal 1 effective resistivity (assumes conformal barrier and includes electron scattering effects) (μΩ-cm)
Metal 1 RC delay (ps) over 1mm with effective resistivity
Intermediate wiring pitch (nm)
Intermediate wiring barrier/cladding thickness (nm)
Cu thinning at minimum intermediate pitch due to erosion (nm), 10% x height, 50% areal density, 500 μm square array Intermediate metal effective resistivity (assumes conformal barrier and includes electron scattering effects) (μΩ-cm)
Intermediate wiring dual damascene A/R (Cu wire/via)
Intermediate wiring RC delay (ps) over 1mm calculated using effective resistivity shown above
Global wiring barrier/cladding thickness (nm)
Cu thinning of global wiring due to dishing (nm), 100 μm wide feature
Global metal effective resistivity (assumes conformal barrier and includes electron scattering effects) (μΩ-cm)
Global wiring RC delay (ps) over 1mm calculated using effective resistivity shown above
Interlevel metal insulator-effective dielectric constant (k)
Minimum global wiring pitch (nm) Global wiring dual damascene A/R (Cu wire/via)
Minimum expected bulk dielectric constant (k) Manufacturing solutions exist Manufacturable solutions are known Manufacturable solutions are not known
barriers. Likewise, while improvements in copper electroplating technology have enabled extendibility through multiple generations, new chemistries and techniques must be developed to accelerate bottomup fill and plate on high resistivity seeds, as feature size continues to decrease. Paralleling the development of advanced copper metallization techniques is an equally important effort focused on lower k dielectric materials. The integration of new low-k dielectrics brings numerous reliability concerns that include thermally- or mechanically-induced cracking or adhesion loss, poor mechanical strength, moisture absorption, lower dielectric breakdown voltage/time dependent dielectric breakdown (TDDB), texture effects and poor thermal conductivity. The reduced mechanical strength of porous low-k dielectrics is of particular concern in both processing (especially during chemical–mechanical polishing (CMP)) and packaging. Thus, mechanical properties, such as hardness, modulus, cohesive strength, cracking limit, and crack propagation velocity have been key metrics for ongoing materials development. For so-called "porous" ultra-low-k (ULK) materials, co-optimization of deposition chemistry with porogen removal and anneal has yielded dielectric materials that are compatible with advanced manufacturing requirements [41–48]. However, while current progress is encouraging, past history underscores the difficulty of introducing new low-k materials into production and much work remains to be done.
In general, a key integration challenge for ULK materials and for scaling copper damascene is the extendibility of CMP techniques. In addition to accommodating more mechanically fragile and chemically hydrophobic dielectric materials, future CMP processes must also contend with tighter dishing and erosion specifications. The decrease in metal thickness dictated by scaling means that to maintain design tolerances for resistance and capacitance, tighter control of vertical dimensions is required in the damascene processes (see Table 2.2). Achieving these goals will likely require co-optimization of both electroplating and planarization techniques as well as enhanced in situ process control. While significant copper and low-k process integration challenges lie ahead, several generations of copper/low-k production provide a solid foundation for moving forward. The next section will describe some of the key process integration challenges and solutions that have contributed to the successful implementation of copper/low-k interconnects in high volume production.
Dual Damascene Copper Integration
Subtractive etch, the approach used in fabricating aluminum-based interconnects is inapplicable in the fabrication of copper-based interconnects, due to the lack of volatility of copper–halide complexes at moderate temperatures. As a result, copper interconnect fabrication requires a damascene approach whereby the metallization is inlaid into interconnect geometries which are pattern-transferred into the Positive pattern
Metal etch
Dielectric deposition
Negative pattern
Dielectric etch
Metal deposition Metal Dielectric Metal CMP
Dielectric planarization by CMP
Subtractive etch (Al)
Photoresist Etch stop (dielectric)
Damascene (W, Cu)
FIGURE 2.5 Comparative process flows associated with the fabrication of interconnect structures using subtractive and damascene technologies.
Overview of Interconnect—Copper and Low-k Integration TABLE 2.3
Key Process and Performance Differences for Subtractive vs. Damascene Interconnect Technologies Key Differences—Subtractive vs. Damascene Subtractive
Dual Damascene
Interconnect resistance variance depends mostly on line width variance (driven by litho/etch bias, wet cleans) Resistance variance mostly constant with increasing width and thickness CLL variance depends on line width variance CXO variance depends on line width/depth variance Via depth fixed for each level of interconnect Self limiting oxidation of Al Chemical–mechanical polishing (CMP) limited to single material
M3 CXO
M2 CLL
M1 CLG Sub
Interconnect resistance variance depends on line width/depth variance (driven by litho/etch bias, wet cleans, etch depth uniformity) Resistence variance may change with increasing width and thickness CLL variance depends on line width/depth variance CXO variance depends on line width/depth variance Via depth function of layout(width of overlying line) Cu oxidation no self limiting Chemical–mechanical polishing (CMP) of composite structure
dielectric of interest. A flow comparison of the subtractive and damascene sequences is illustrated in Figure 2.5. A dual damascene process also offers lower fabrication cost due to the limited use of chemical–mechanical planarization processes compared to the multiple uses of this unit process in the subtractive etch fabrication of interconnects. In addition, low via resistances are achieved through the reduction of the number of high resistivity interfaces in the interconnect structure. However, the dielectric etches and metal fill processes face higher aspect ratios due to the dual damascene structure. Table 2.3 lists key differences between the two approaches. Dual damascene copper interconnects may be fabricated using two primary schemes; via first scheme or trench first scheme as outlined in Figure 2.6. Continued scaling of interconnect geometries also requires integrating low permittivity materials into the copper interconnect structure. The chemically amplified materials used in the photolithographic steps of pattern transfer exhibit increased sensitivity to the impurities in the chemical vapor deposited low permittivity dielectric materials. Interactions between impurities (N, H, and combinations of these) in the low permittivity dielectric films and the UV lithography resist lead to a loss of sensitivity of the photoactive compounds in the pattern definition layers. The interaction between the amine groups and photoactive compounds in the resist may lead to
Resist Sacrificial fill Via first approach
Metal Dielectric barrier Low-k dielectric
Trench first approach
Comparison of via first vs. trench first dual damascene approaches.
Handbook of Semiconductor Manufacturing Technology Top down SEM images
Undeveloped photoresist
Trench litho
No contact between Via/M2
FIGURE 2.7 The schematic representation of resist poisoning (left), scanning electron microscopy (SEM) top down, and cross-section micrographs illustrating the pattern disruption due to undeveloped resist. (From Dixit, G., Proceedings of the International Reliability Physics Symposium, Tutorial Notes, 2004.)
undeveloped resist thus preventing the formation of all the required features in a multilevel interconnect structure. Figure 2.7 shows the phenomenon of resist poisoning occurring in the trench pattern step of a via first dual damascene scheme [49]. Various modifications to the sequence and details of process steps used in the fabrication sequence may be employed to overcome the risk of resist poisoning. Figure 2.8 outlines the various schemes used in dual damascene fabrication [50,51]. In the self-aligned approach shown in Figure 2.8a, the via level dielectric, or interlayer dielectric (ILD) and an etch stop layer (typically silicon nitride or silicon carbide for inorganic ILDs and oxide for organic ILDs) are sequentially deposited, followed by pattern and etch of via into the etch stop layer. The dielectric for the trench is then deposited onto the patterned etch stop layer. The trench features are delineated into this dielectric and the trench etch is extended to complete transferring the via pattern from the etch stop layer into the interlayer dielectric. The etch stop layer defines the trench height, while maintaining a vertical profile of the via sidewall. The etch stop layer is removed from the bottom of the trench during the final etch step, which simultaneously clears the dielectric barrier from the bottom of the via. The chief advantage of the buried via approach is that all patterning is done on planar surfaces; major disadvantages include the need for an etch stop layer (which increases sidewall capacitance), the need for high etch selectivity to the etch stop layer and susceptibility to partial via definition if trench and via are misaligned. Partial vias present a potential reliability issue and, thus, this integration scheme should be avoided unless ample alignment tolerance is provided in the product design. Via first approach for dual damascene has been a workhorse for the industry. In this scheme, the entire dielectric stack (including intervening etch stop layer if desired) for a given interconnect level is deposited prior to pattern definition. The vias are then patterned and etched down to the etch stop layer as shown in Figure 2.8b. The high aspect ratio vias are filled with a sacrificial inorganic material to protect the underlying etch stop layer during the trench etch. The sacrificial fill material also assists the trench patterning process by limiting the variation in resist thickness over via. The etch rate of the sacrificial fill material is required to be similar or slightly higher than the etch rate of the dielectric during the trench etch. Bottom anti-reflective layers (BARC) are frequently used as sacrificial fills in via first dual damascene.
Resist (a) Self aligned approach
Sacrificial fill Metal Dielectric barrier Low-k dielectric
(b) Via first approach
Dielectric hard mask Metallic hard mask
(c) Via first tri layer approach
(d) Dual top hard mask approach
FIGURE 2.8 Schematic flows of improvised via first and trench first approaches to overcome challenges in the pattern transfer process for low-k porous dielectrics.
In the trench first approach, via is patterned on the etched trench, which may present significant topography. In case of misalignment, partial vias can only be avoided by extended overetch to ensure that the full ILD/inter-metal dielectric (IMD) thickness is cleared, which taxes etch selectivity to the via etch stop layer (not protected by a BARC as in the case of via first approach). Via first tri-layer approach (Figure 2.8c) utilizes a sacrificial dielectric film, such as undoped silicon dioxide deposited on top of the sacrificial via fill material, to improve the fidelity of the pattern transfer process. A low temperature dielectric deposition process is preferred to ensure compatibility with the sacrificial fill materials, whose glass transition temperatures reside below those of conventional dielectric deposition processes. The dielectric film serves as a barrier to prevent interaction between the resist and contaminants from the underlying low dielectric constant materials, thus enhancing the robustness towards resist poisoning. The low etch rate of the silicon dioxide during the low-k etch process and further separation between the low-k dielectric and the UV resist offers advantages in controlling the sidewall roughness of the resultant features. Figure 2.8d depicts one of the trench first dual damascene sequences with two hard mask layers [52,53]. The sacrificial hard mask stack is comprised of a dielectric/metal nitride bilayer. Materials such as titanium nitride may be used as a metal hard mask. The optical transparency of this material is a key requirement to ensure alignment between the successive pattern steps and the transparency requirements limit the useable thicknesses of these films. The process steps typically involve pattern and etch of the trench features into the metal hard mask followed by via pattern. Following via etch; a sacrificial fill of via may be utilized prior to completing the trench etch with the metal nitride mask. Typical post-etch resist removal processes include an oxidizing plasma which in turn may also cause oxidation and loss of carbon from the sidewalls of the trench features. The oxidation damage to low-k materials is undesirable as it leads to an increase in the dielectric permittivity. Due to the absence of resist following the trench etch, an oxidizing plasma clean is unnecessary and the post-etch clean may be accomplished through the use of
Process and Integration Challenges for Different Dual Damascene Schemes Damascene Schemes
Self-aligned
Risk of forming partial vias, worse with scaling Additional k impact due to middle etch stop layer Has not been reported in any practical use Difficult to clear resist puddle in trench (depth of focus) Risk of misalignment leading to partial vias Alignment issue aggravated with scaling Resist poisoning Fencing (different etch rates of dielectric/sacrificial via fill) Resist poisoning and lithography rework Low-k damage in post etch cleaning Trench etch process requires further optimization to control profiles and limit fencing Sacrificial dielectric compatibility with sacrificial fill layer Multiple materials in stack (etch selectivity management) Significant etch process challenge, may require multiple tools Top hard mask compatibility with Cu Chemical–mechanical polishing (CMP)
Trench first
Via first Via first tri layer Dual top hard mask
solvents, thus eliminating the risk of oxidizing the low-k material. This approach involves a metal etch step to define the trench into the metal nitride and this may require additional process equipment compared to the approaches without metal hard masks. Table 2.4 summarizes the challenges in the various dual damascene schemes. Integrating low permittivity materials with porosity, high carbon content, and marginal mechanical properties present challenges in the areas of interface engineering, pattern transfer, and metallization. Figure 2.9 summarizes various issues that may be faced during the dual damascene integration of copper with low dielectric constant materials. In order to lower the effective interconnect capacitance between successive generations of integrated circuits, it is necessary to reduce the dielectric constant of the bulk dielectric as well as the dielectric etch stop layer. As a result, the commonly used etch stop layer such as silicon nitride is replaced with nitrogen doped silicon carbide. The presence of carbon in the etch stop E-CD control due to CMP dishing, erosion Reliability: EM, BTS: B/S, ECP, anneal
Top CD spacing
CMP C/U Dishing
Cu filling of trench and via; B/S, ECP
Side wall barrier
Voids
Uncontrolled etch bottom Corrosion
Etch profile
Via to Cu, Etch, pre-clean Contact to W Plug: Etch, pre-clean
adhesion fence
Cu filling
Post CMP dielectric passivation Effective dielectric constant w/Etch Etch profiles and selectivity
Metal barrier for Cu
FIGURE 2.9 Schematic representation of issues faced in the integration of Cu/low-k dielectric interconnect structures. (From Dixit, G., Proceedings of the International Reliability Physics Symposium, Tutorial Notes, 2004.)
layer as well as in the bulk dielectric leads to a concern for interface delamination, as the carbon in both these films may segregate preferentially to the surfaces [54,55]. Innovative pre- and post-dielectric deposition treatments are utilized to denude the surfaces of the excess carbon so as to promote the strong interfacial adhesion between the various films in the dielectric stack. The local changes in the film concentrations may in turn present challenges to the dielectric etch and post-etch cleaning processes as the etch rates at the interfaces may differ from the etch rates of the bulk materials. Plasma etch of the multilayer dielectric stack challenges the etch unit processes in maintaining the etch selectivity between the different layers, while simultaneously producing acceptable profiles of the resultant via and trench features [56,57]. Intervening etch stop layers in via/trench architecture degrade the effective capacitance of the structure and such layers are undesirable. Eliminating the intermediate etch stop may result in features with non-optimal shapes, such as facets, micro-trenches, or fences as shown in Figure 2.10. Tailoring the etch unit process to meet the varying requirements of etch rate and selectivity between the different materials, with minimal loading effects, is of primary importance in designing out the intermediate etch stop layers from the dual damascene structure. The impact of resist removal processes on the dielectric properties of low dielectric constant materials needs careful evaluation [58–61]. The chemical plasmas used for stripping the residual resist and by-products of etch adversely affect the carbon concentration of the low-k materials. The porous structure of the low-k material is then susceptible to adsorb moisture and may exhibit a large increase in permittivity. Figure 2.11 shows the impact on the final trench structure produced after etch, ash, and solvent clean. Undesirable undercut of the sidewall is noted with the case of an unoptimized resist removal process. Figure 2.12 shows the lateral carbon concentration profile on the trench sidewall for structures exposed to different resist removal plasmas. A reduction in the carbon concentration close to the sidewall is seen for both types of processes and the width of the zone with variable carbon content differs significantly between the two processes. These physical changes to the low-k dielectric material lead to alteration of the electrical properties as seen in Figure 2.13 where the normalized product of resistance and capacitance of an interconnect structure is plotted for different resist removal processes. The choice of an optimum etch in the dual damascene scheme is thus of high importance to achieve effective electrical performance.
Micro-trench Faceting Fencing
FIGURE 2.10 SEM cross-section images illustrating undesirable results, such as micro-trenching, faceting, and fencing encountered due to non-optimized pattern transfer. (From Dixit, G., Proceedings of the International Reliability Physics Symposium, Tutorial Notes, 2004.)
No ash
Standard ash
Optimized ash
FIGURE 2.11 SEM cross-sections of trenches etched into a porous low-k dielectric. The post-etch ash induced damage to the dielectric is noted in the form of an undercut of the low-k material by the buffered hydrofluoric acid (HF) decoration and results in unwanted line width gain. (From Dixit, G., Proceedings of the International Reliability Physics Symposium, Tutorial Notes, 2004.) Oxidizing chemistry
Reducing chemistry
EELS-O EELS-C 30 nm
1.5×105 100 nm Counts
EELS-O EELS-C
1.0×105
5.0×105 20,000 0 (a)
100 150 Position (nm)
FIGURE 2.12 Transmission electron microscope (TEM) electron energy loss spectroscopy (EELS) profiles of carbon and oxygen concentrations across the dielectric between trenches. Varying widths of the carbon loss zone are noted with different post-etch ash chemistries. (From Dalton, T. J., Fuller, N., Tweedie, C., Dunn, D., Labelle, C., Gates, S., Colburn, M., et al., Tech. Dig. IEEE Int. Interconnect Tech. Conf., 154–56, 2004.)
Normalized RC
4 5 6 Ash chemistry
FIGURE 2.13 A plot showing a normalized RC product, measured on an interdigitated metal comb structure, as a function of different post-etch ash processes. Damage to the dielectric leads to higher capacitance and higher RC product. (From Dixit, G., Proceedings of the International Reliability Physics Symposium, Tutorial Notes, 2004.)
In order to address the downstream process compatibility, dual damascene features fabricated in low-k dielectric materials may contain sacrificial layers, such as dielectric or metal hard masks, which remain prior to metallization and are removed during the chemical–mechanical polish of copper. These sacrificial layers contribute to increase the aspect ratios of the damascene feature and additional stress on the dielectric etches and copper fill processes. The liner/barrier processes for contact and via schemes typically includes an inert ion based sputter pre-clean that ensures consistent ohmic contact between the under/overlying metallic layers. The sputter pre-clean redistributes the material removed from the interface of interest and the sputtered species are deposited onto the sidewall of the features (Figure 2.14). In the case of copper low-k interconnects, the redeposited film presents an additional challenge, as this material may then diffuse into the porous dielectric, thus degrading the intra-metal isolation and increasing the risk of copper contamination of the entire structure. The outdiffusion of the redeposited material into the dielectric and the resultant free volume within the interconnect feature also contributes to increased risk in stress migration of interconnects. The high aspect ratios due to the presence of sacrificial layers in the dual damascene flow challenge the capability of the physical vapor deposition process in providing continuous conformal deposition. The ease of integration between the physical vapor deposited layers and subsequent electroplating of copper has led to the need to extend the physical vapor deposition process for copper barrier and seed layers. In order to overcome the line-of-sight limitations of physical vapor deposition, innovative approaches such as resputtering of the barrier layer are utilized to improve the coverage of the barrier layers on the sidewalls of the vias and trenches. The resputter in copper barrier deposition may also be used to eliminate the inert ion sputter pre-clean process. In the barrier first approach [62], the copper barrier resputter step is tuned to achieve a controlled penetration of the via into the underlying metal. Due to the varying aspect ratios of via in the dual damascene architecture, the bottom coverage of barrier may vary significantly in vias within different trench geometries. As a result, in achieving a controlled recess of the via, the dielectric in certain trench geometries may be exposed during the resputter step, thereby leading
Process sequence Step 1: pre-clean + Ar+ Ar
Cu from bottom of via sputtered onto the via sidewalls Stress migration Under thermal stress the Cu originally sputtered on the sidewall diffuses into the dielectric further exposing weak points in the barrier
Step 2: barrier
Step 3: Cu seed & fill
Barrier coverage can be compromised by agglomerated Cu Cu originally sputtered onto the sidewall during PC
Cu from the via bottom
FIGURE 2.14 Schematic representations of process sequence of pre-clean in the Cu barrier/seed deposition and its impact on failure of via (TEM cross-section) subjected to thermal stress. (From Dixit, G., Proceedings of the International Reliability Physics Symposium, Tutorial Notes, 2004.)
FIGURE 2.15 SEM cross-sections illustrating the damage that may be caused to the trench dielectric due to un-optimized resputtering in the copper barrier deposition process.
to micro trenching or trench bottom roughening as seen in Figure 2.15. The rough trench bottom poses a reliability risk due to the possibility of micro voids between the barrier and copper seed interface. Precise control of the barrier deposition parameters to achieve differentiated barrier thicknesses in the bottom of trench and via features is necessary to eliminate damage to the dielectric and roughening during the resputtering process. The composition of the Ta(N) layer as well as the crystallographic texture of the Ta deposited on top of the Ta(N) play a key role in determining the continuity of the copper seed deposited on top of the barrier [63]. A continuous seed with good adhesion is necessary to ensure complete filling of the electroplated copper into the dual damascene features. As the interconnect geometries scale into the sub-100-nm regime, the thickness of the copper seed deposited in these features also needs to be scaled down to prevent pinch-off prior to the electroplating step. Electroplating on thin copper seeds with relatively high sheet resistance is challenged by the terminal effect in the plating cell, whereby the voltage drop across the wafer diameter induces a large non-uniformity in the electroplated film thickness and may also lead to voiding within the features. Continued development in barrier/seed deposition and electroplating of copper is required to extend these processes to future generations of interconnect. The resistivity of copper in sub-50 nm features is significantly higher compared to the resistivity in wider lines (Figure 2.16) [64,65]. The relatively high volume of these narrow lines occupied by the highly resistive Ta(N)/Ta barriers, smaller grain size of the copper in narrow features compared to wider features as well as the sidewall roughness of the damascene trenches all contribute to the increased resistivity. Thin high efficiency barriers, such as atomic layer deposited Ta(N) and integration of these materials with thin low resistivity seed layers for electroplating is necessary to ensure the extendibility of copper metallization to decanano scale interconnect features. A number of difficulties are encountered in the chemical–mechanical planarization processes of copper low-k dielectrics. Carbon doped low dielectric constant materials exhibit lower hardness and modulus. While the dual damascene pattern transfer may be accomplished through the use of suitable hard mask layers, in order to realize the maximum benefit in overall capacitance of the interconnect sacrificial masking layers need to be removed during the chemical–mechanical planarization processes. The exposure of the low-k materials to the polishing environment presents hurdles in maintaining acceptable dishing and erosion of the copper low-k structures during chemical–mechanical planarization processes.
Resistivity (μΩ -cm)
Blanket films large grain no grain scattering
Non-optimized copper process
2.0 optimized copper fill and anneal 1.5
Thickness/width (nm)
FIGURE 2.16 Measured copper resistivity as a function of line width. Resistivity increases at smaller line widths due to electron scattering from grain boundaries and sidewalls. Optimization of plating chemistry and post-plate anneal for large grain growth reduces grain boundary scattering.
Precise control of the shear force applied during the polishing process is necessary to achieve good process performance as well as to minimize mechanical damage to the low-k materials [66–73]. The hydrophobic nature of porous low-k materials with inferior wetting characteristics requires the implementation of advanced vapor drying techniques to minimize defects, such as residues of the polishing slurry and watermarks. The 90 and 65 nm generation devices have been successfully integrated with copper and low permittivity materials with bulk dielectric constants in the range of 2.9–3.1. Numerous challenges have been overcome in achieving good device yields and reliability with this first generation of porous films. Further scaling of interconnects with forthcoming device generations will require the integration of even lower permittivity materials (2.2!k!2.9) that enable sizeable reductions in the interconnect capacitance. The inevitable degradation of mechanical properties with lower permittivity insulators poses formidable challenges to the integration of these materials into multilevel interconnect structures. Modifications to existing dual damascene fabrication schemes and processes may offer means to overcome some of the difficulties in the pattern transfer module. While the hierarchical reverse scaling approach of interconnect architecture offers some relief in the RC delay of the intermediate and global metal levels, continued scaling of physical dimensions demands the extension of lower permittivity dielectrics into the higher levels of multilevel interconnects. Lower permittivity materials also entail higher residual tensile stresses, increasing the risk of crack initiation and propagation. Engineering the packaging related processes [74–79] to accommodate devices with multiple levels of porous materials with low mechanical strength is a key to realize the successful implementation of low permittivity materials for intermediate and global interconnections. The increasing resistivity of the copper with thinner and narrower lines raises serious concern about the extendibility of copper metallization. Efforts to reduce the relatively high volume of high resistivity barrier layers within the metal lines are hampered by the difficulties in reliable integration of atomic layer deposited barrier films with the copper metallization. Novel design approaches to comprehend and accommodate resistivity-dependent interconnect line width may be necessary to overcome the projected increase of line resistance as well as the increased variances in line resistance due to the pattern-dependent limitations of chemical–mechanical planarization processes. Ultimately, the extendibility of copper metallization with low permittivity insulators will depend on the economic and practical factors that dictate the new cost sensitive era of consumer devices.
Copper/Low-k Reliability
Copper metallization offers significant reliability improvement as compared with aluminum metallization, but also presents several new integration and reliability challenges. Since copper readily diffuses into silicon and most dielectrics, copper leads must be encapsulated with metallic (such as Ta and TaN) and dielectric (such as SiN and SiC) diffusion barriers to prevent electrical leakage between adjacent metal leads and degradation of transistor performance. Copper diffusion is greatly enhanced by electric fields imposed between adjacent leads during device operation (w1E5 V/cm), so absolute barrier integrity is crucial to long-term device reliability (see Figure 2.17). Validation of barrier reliability required a new test procedure—bias temperature stress (BTS)—now prevalently used by the industry [80–83]. The electromigration behavior of copper also differs from aluminum in that surface diffusion tends to dominate over grain boundary diffusion. This difference may be one reason that preliminary data show deterioration in copper reliability at very small feature sizes (i.e., a large ratio of surface area to crosssectional area) [84]. From a resistivity standpoint, it is still important to maximize copper grain size to reduce grain boundary scattering, but as compared with aluminum, grain size plays a lesser role in determining copper's electromigration behavior. Yet another key difference is that copper, unlike aluminum, does not form a self-limiting passivation oxide that provides protection from chemical attack. Indeed, oxidized copper generally has poor adhesion to metal and dielectric diffusion barriers, which leads to severe degradation in electromigration performance (see Figure 2.18). Thus, it is essential to chemically remove residual copper oxide before in situ deposition of a hermetic dielectric diffusion barrier (see pretreatment effects in Figure 2.19). As shown in Figure 2.20, dielectric barrier hermeticity is also important from the standpoint of preventing moisture absorption in low-k dielectrics, which can degrade both dielectric constant and electrical breakdown. In addition to electromigration effects, inherent stress gradients in copper metallization can also lead to void migration even without the assistance of an electric field. Stress gradients in copper are a consequence of damascene processing (i.e., encapsulation) and subsequent thermal cycling (see Figure 2.21), with higher stress levels generally promoting the likelihood of void formation. Pre-existing
FIGURE 2.17 Example of dielectric barrier failure leading to copper diffusion and subsequent shorting between interconnects.
Example of void formed by copper electromigration.
Interfacial O(atoms/cm2)
No CuxO Reduction
Permeable SiC
Hermetic SiC
%Adhesion failures(Tm
Tb >Tm
FIGURE 3.7 Convection patterns in a Czochralski melt due to (a) thermal convection, (b) crystal rotation and (c) crucible rotation. (From Lin, W., Oxygen in Silicon, ed. Shimura, F., Academic Press, 1994, chap. 2. Reproduced with permission from Elsevier.)
growth, in Equation 3.5. Secondly, the rotating crystal draws a uniform flow from the central region of the melt, perpendicular to the interface over the radius and spins it outward radially near the surface, Figure 3.7b. As a result, the convection flow by the crystal rotation has the effect to counter and reduce the thermal convection flow, and the convection flow induced by the crucible rotation (has same general flow pattern as thermal convection. See Figure 3.7c). The magnitude of the flow induced by the crystal rotation is characterized by the dimensionless Reynolds number NRe:
NRe Z ur 2 =y;
where u is the crystal rotation rate and r is the crystal radius. While forced convection, i.e., the crystal rotation, has the effect of overriding the harmful thermal convection, the net effect depends on the relative magnitude of the two components. The relative effect of 2 2 the two components may be expressed by the ratio, NRe =NGr . If NRe O NGr , the crystal rotation will effectively isolate the segregation process at the growth interface from the thermal convection in the melt [33]. Therefore, small melt and high crystal rotation would suppress the effect of thermal convection. 3.3.2.3.3 Macroscopic Radial Impurity Uniformity In the silicon growth from a homogeneous melt, the radial uniformity is controlled by the uniformity of boundary layer thickness across the interface. In Equation 3.4, if the growth rate is assumed to be uniform across the interface, then the radial uniformity of the impurity is determined by the variation in boundary layer thickness. It may be shown [34], in the case of dopant in silicon, that the rate of change in keff with respect to the variation in diffusion boundary layer thickness is very sensitive in the range of layer thickness encountered in the silicon CZ growth. The effect is greater for n-type than for the p-type dopant in silicon. The relevance of the melt convection condition to the radial impurity incorporation is the following. In the absence of thermal convection, the result of the crystal rotation would be a uniform diffusion boundary layer over the crystal radius at the interface. Hence, if the crystal rotation is the only source of convection, no radial segregation will result from the fluid flow effect and impurity incorporation is uniform across the crystal radius. In real crystal growth, however, the thermal convection flows form a general pattern in the crucible, as rising streamlines along the crucible wall, which fall in the center following a gradually curved path (see Figure 3.7a). This path results in a stagnation point near the center of the crystal interface. Therefore, when thermal convection is strong compared to the forced convection, the diffusion boundary layer thickness at the outer region of the interface may be reduced by the thermal convection velocity, while the effect is small in the region near the center of the interface. Thus, thermal convection flow causes a radial variation in a boundary layer thickness. If the segregation coefficient of the dopant involved, k0, is smaller than unity, one finds a
DK4126—Chapter3—23/5/2007—18:40—ANBARASAN—240432—XML MODEL CRC12a – pp. 1–78.
significant radial variation in impurity incorporation; it is high in the center and low in the outer region of the crystal. The greater the k value deviates from unity, the greater the radial variations. By the same principle, increased crucible rotation can cause variations in the boundary layer thickness and radial gradient in incorporation. As discussed above, harmful thermal convection effects can be suppressed by increased crystal rotation and small melt growth. Lin and co-workers [17,23] have demonstrated such effects by using a double crucible arrangement (see Figure 3.6a). The use of a smaller diameter and a low aspect ratio of inner crucible reduced the effect of thermal convection. The improvements on radial dopant uniformity and random dopant concentration fluctuations, and characteristic of the thermal convection, were observed for As, P, Sb, and oxygen for which the segregation coefficients deviated significantly from unity. 3.3.2.3.4 Microscopic Inhomogeneity In general, the microscopic inhomogeneity of impurity in CZ silicon crystals is a result of growth rate fluctuations and impurity segregation during crystal growth. The growth rate fluctuations cause variations in the impurity incorporation levels. The lattice strain associated with local impurity concentration variations give rise to the so-called "striations," which are revealed by chemical etching or x-ray topography. Severe microscopic dopant inhomogeneity corresponds to a large variation in carrier concentration and is not desirable in silicon materials used for device fabrication, especially when such variation is comparable to the device feature size. This is an important consideration in VLSI/ULSI fabrication. Large oxygen striations can result in preferential precipitation, often observed as concentric ring patterns in etched wafers following thermal processing. In CZ silicon growth, there are several sources of microscopic growth rate variations which are discussed below. 3.3.2.3.4.1 Non-Centrosymmetric Thermal Distribution in the Silicon Melt In large-melt silicon growth, finite thermal asymmetry exists about the center of the melt. During crystal growth, as the crystal is rotated about the growth axis, the interface experiences slightly different temperatures at different positions in the melt. Therefore, the growth rate of a given crystal element parallel to the crystal axis, fluctuates periodically, as illustrated schematically in Figure 3.8. In general, the fluctuation is most pronounced in the crystal elements furthest from the crystal center. The periodicity of the fluctuation is determined by the average growth rate, f, and crystal rotation rate u, as f/u. The variations in the impurity incorporation level that correspond to the growth rate variations are commonly referred to as "rotational striations." When the equilibrium segregation coefficient (k0) of the element involved is less than unity, the fluctuation in the impurity incorporation level is in phase with the growth rate fluctuation. If k0O1, the fluctuations will be out of phase (see Figure 3.8). The relationship may be realized readily by examining the Equation 3.4. 3.3.2.3.4.2 Thermal Convection-Related Temperature Fluctuations Growth rate fluctuations caused by thermal convection related temperature variations are mostly random in nature and etched striations are characteristically aperiodic. When thermal convection is significant, the microstriations bear the signature of high-frequency fluctuations in the order of tens of hertz. 3.3.2.3.4.3 Automatic Diameter Control-Induced Perturbation Growth-rate fluctuation can be further perturbed by the ADC commonly employed in silicon crystal growth. The crystal pull-rate is slaved by optically monitored crystal diameter variations, in order to maintain a preset diameter. The pull-rate adjustments are both "instantaneous" (a few seconds) and "long term" (minutes). The long term pull-rate adjustment determines the average growth rate. The instantaneous pull-rate adjustment imposes modifications on the microscopic growth rate fluctuations resulting from thermal asymmetry and thermal convection. The net effect is to smear the periodic nature of the impurity fluctuation resulting from the melt thermal asymmetry.
Silicon Materials
w f Growth rate f fw Impurity incorporation
For K0 1
FIGURE 3.8 Schematic illustration of growth rate fluctuation and its relationship with microscopic impurity fluctuations in CZ crystal. Here, f and u are growth rate and crystal rotation rate, respectively. (From Lin, W. and Stavola, M., J. Electrochem. Soc., 132, 1412, 1985. Reproduced with permission from Electrochemical Society.)
Oxygen Incorporation and Segregation in Czochralski Silicon Growth
3.3.2.4.1 Incorporation Mechanism Unlike most intended dopants in silicon CZ crystal growth, which show "normal freezing" behavior under normal growth conditions, oxygen is an unintended dopant that enters the silicon melt continuously by dissolving the silica crucible. The incorporation behavior of oxygen into silicon is the result of complex interplay among crucible dissolution, surface evaporation, thermal convection and forced convection, as shown in Figure 3.9. In a side-heated CZ hot-zone, the dissolution of the silica crucible is the highest at the side wall of the crucible. The silicon melt dissolves SiO2 and absorbs its oxygen. The oxygen-rich silicon melt would rise along the crucible wall, following the thermal convection flow pattern to near the melt surface, and then to the melt center where it is drawn toward the crystal for incorporation by the forced convection induced by the crystal rotation. When the oxygen-rich melt is near the surface, a great portion of the oxygen is evaporated through the free surface. The oxygen concentration incorporated into the growing crystal, therefore, is proportional to the oxygen concentration in the melt adjacent to the growing crystal. During steady-state growth, there exists a dynamic equilibrium of oxygen between the four controlling factors in the system. Due to the difference in thermal characteristics of different hot-zone designs, the oxygen incorporation behavior varies from one grower design to another. The major oxygen-controlling factors are discussed in the following. 3.3.2.4.1.1 Effect of Surface Evaporation and Crucible Dissolution In the absence of thermal and forced convection (a hypothetical case), the melt oxygen concentration is proportional to the ratio of melt-crucible contact area to the available free surface area. In such a case, the transport of oxygen would depend entirely on diffusion. This ratio constantly decreases as the aspect ratio is reduced during the growth. The variation of this ratio is the basic characteristic of the axial oxygen profile of CZ silicon, in which the concentration is observed to gradually decrease from the seed end toward the tang end (for example, see Figure 3.15). However, the dependence of concentration on this geometric ratio is influenced by the crucible dissolution rate and ambient pressure. The dissolution rate
Si crystal
Si melt
Silica crucible
Crucible dissolution
Thermal convection
Surface evaporation
FIGURE 3.9 Schematic of a silicon Czochralski growth system showing relationship among oxygen-controlling factors. (From Benson, K. E., Lin W., and Martin, E. P., Semiconductor Silicon 1981, eds. Huff, H. R., Kregler, R. J., and Takeishi, Y., Electrochemical Society, Princeton, NJ, 1981, 33. Reproduced with permission from Electrochemical Society.)
of the silica is material density and temperature dependent. Therefore, using crucible with an inner wall made of "porous silica," for example, would enhance the dissolution rate. Increasing the melt-crucible contact area by using corrugated inner surface will obviously serve similar purpose. Mathematical modeling of the observed oxygen incorporation behavior based on dissolution and evaporation, as carried out by Carlberg et al. [35], is merely a first-order approximation. In actual silicon growth, oxygen incorporation and uniformity are greatly affected by thermal convection and forced convection. No modeling effort thus far accurately takes these factors into account. A study of oxygen evaporation from the melt surface was made using "shoulder" growth of a 300mm-diameter crystal from a 350-mm-diameter crucible. In this experiment, the effect of the free melt surface evaporation on the oxygen level during crystal crown growth was examined. Figure 3.10 plots oxygen concentration variation in the grown silicon, as the melt surface is covered by the growing "shoulder." The relationship between oxygen concentration and available surface is not linear. When the crystal shoulder diameter is small (!125 mm), the oxygen evaporation (and therefore the oxygen concentration of the growing crystal) is very sensitive to the diameter change. When the majority of the surface is covered with the crystal, the evaporation seems to remain nearly constant. By extrapolating the curve in Figure 3.10, the oxygen concentration corresponding to a very small and to a maximum size of crystal (when the melt is fully covered) may be obtained. The maximum oxygen evaporation accounts for about 30% of the available dissolved oxygen. This value is much lower than generally conceived, that over 90% of the dissolved oxygen from crucible is evaporated from the melt surface [36]. More discussion of the oxygen incorporation behavior on the 300-mm-diameter crystal growth will be made in a later section. Lin and Hill [17] studied the effect of ambient pressure on the oxygen distribution in the melt and grown crystal, via crystal growth experiments. Based on the experimental evidence, physical models of oxygen distributions in large silicon melts were proposed and are shown schematically in Figure 3.11. It is shown that the thermal convection is the main oxygen transport mechanism when the melt aspect ratio is high in a large melt growth. The oxygen-rich flow conforms with the suggested thermal convection
Crystal diameter (mm)
Oxygen concentration (ppma)
0.3 0.4 0.5 0.6 Crystal cross-section area
Crucible cross-section area
FIGURE 3.10 Oxygen concentration measured as a function of fraction of melt surface being covered by the growing crystal during crown growth. The crystal crown accounts for less than 10% of the initial charge. (From Lin, W. and Benson, K. E., Annual Review of Materials Science, 17, 273, 1987. Reproduced with permission from Annual Reviews.)
pattern shown in Figure 3.7a. Experimental results also showed that under atmospheric pressure, the oxygen distribution is not uniform near the melt center, where a stagnant region of low oxygen concentration exists. The nature of this non-uniformity is displayed in crystals' radial oxygen profiles near the seed end, in Figure 3.12a. However, as the crystal growth progresses, the forced convection due to crystal rotation modulates the oxygen distribution and results in the local mixing, and the gross nonuniformity near the stagnant region is largely diminished. On the other hand, under the reduced pressure, Figure 3.12b, the oxygen distribution in the melt is more uniform near the surface of the melt. The grown crystal possesses better radial oxygen uniformity. When thermal convection is not significant, as in the case of a low aspect ratio configuration, the melt oxygen is both diffusion rate-dependent and crucible dissolution rate-dependent. The melt tends to be uniform in oxygen. Both enhanced forced convection and ambient pressure have little effect on the oxygen uniformity. 3.3.2.4.1.2 Effect of Crystal and Crucible Rotations For a given system, i.e., fixed starting melt geometry and hot-zone thermal distribution, etc., the parameters that can significantly alter the oxygen incorporation are crucible and crystal rotations, and growth rate variations. The effect of crystal/crucible rotation on the fluid flow patterns were studied in the past by simulation using fluid of similar viscosity as that of silicon melt at room temperature [37]. Figure 3.13 shows the fluid flow patterns due to various combinations of crystal and crucible rotations. In the real crystal growth, however, the flow patterns can be significantly altered by the presence of thermal convection. The results of the simulations provide very useful information on the effect of rotational parameters. Kakimoto et al. [38,39] observed thermal and forced convection flows of silicon melt directly during Czochralski growth using x-ray radiography with solid tracers, for various crystal and crucible rotation speeds. The effect of non-axial, symmetrical temperature distributions on the thermal convection flows was clearly observed. The suppression of thermal convection by crystal rotationinduced forced convection was also evidenced. One way to gain information on the flow properties of a growing system is to analyze grown crystals following parametric growing experiments. One finds that forced convection is effective in controlled oxygen incorporation.
Reduced pressure
FIGURE 3.11 Schematic representations of oxygen distribution in silicon melt at high and low melt level configurations. The dots and lines represent oxygen concentration. (a) At atmospheric pressure. (b) At reduced pressure. (From Lin, W. and Hill, D. W., Silicon Processing, ASTM STP 804, 1983, 24. Reproduced with permission from ASTM.)
As discussed previously, crystal rotation rate determines the magnitude of the upward melt flow. This flow can serve as oxygen transport from crucible bottom to the growing interface. The net effect on the overall flow pattern and oxygen incorporation depends on its magnitude and rotational direction relative to the crucible rotation. Figure 3.14 shows an "uncommon" oxygen profile of silicon grown under high crystal rotation (30 rpm) with crucible in iso-rotation mode (2 rpm). At about 30% of melt solidified, the oxygen incorporation underwent a mode change and sharply increases to a very high concentration level (w25 ppma). This behavior indicates that as the melt aspect ratio is reduced during the crystal growth, at some transition point, the strong forced convection takes over as the dominant transport mechanism which draws oxygen-rich melt from the crucible bottom to the growing interface. Crucible rotation develops radial pressure gradients, which enhance the thermal convection flow arising from non-vertical temperature gradient as shown in Figure 3.7c. Therefore, fast crucible rotation helps the transport of oxygen from near the crucible wall to the growing crystal and enhances incorporation. Figure 3.15 shows the effect of crucible rotation on the incorporation level. Fast melt flow also results in a thinner melt-crucible boundary diffusion layer, a condition that will enhance crucible dissolution. Figure 3.16 shows several axial oxygen concentration profiles of silicon grown with several combinations of crystal/crucible rotation rates, under both counter- and iso-rotation conditions in the same grower and a reduced pressure. These results show that the forced convection induced by crystal/crucible rotations has very significant effects on the melt flow pattern, even in the presence of thermal convection. The bulk of the incorporation behavior is consistent with, and can be interpreted from, the simulated flow patterns (see Figure 3.13).
g = 0.51 20
13 ppma
g=0.77
g = 0.33
g = 0.22 17 ppma
Percent transmission
Near seed
25 Radial distance (mm)
Radial distance (mm)
FIGURE 3.12 Radial profiles of 9 mm IR transmission at various stages: gZfraction solidified. (a) At atmospheric pressure. (b) At reduced pressure (18 torr). Oxygen concentration is computed in accordance with ASTM F121-80. (From Lin, W. and Hill, D. W., Silicon Processing, ASTM STP 804, 1983, 24. Reproduced with permission from ASTM.)
3.3.2.4.1.3 Incorporation in pC and nC silicon crystal growth Degenerately doped n- and p-type silicon, in the concentration range of 1018–1019 atoms/cm3 are common substrate materials for n/nC and p/pC epitaxial structures for complementary metal–oxide– silicon (CMOS) ICs. Unlike the lightly doped silicon, oxygen precipitation behavior in degenerately doped silicon is drastically different depending on the conductivity type [41]. In this resistivity range (0.005–0.02 ohm–cm), oxygen precipitation is retarded in Sb-doped silicon while the kinetics are at their peak for p-type, boron-doped silicon. The possible sources of differences in precipitation kinetics in pC and nC were investigated. Oxygen diffusion mechanism was found not to be affected by the presence of heavy Sb or light boron [42]. The nucleation mechanisms for oxygen precipitates have been thought to be different in pC and nC. Experimentally, the oxygen incorporation in nC and pC have been found to be different from the lightly doped silicon [43]. Figure 3.17 shows the axial oxygen distribution in 100 mm diameter pC(0.005–0.01 ohm–cm) and C n (0.02–0.08 ohm–cm) crystals as measured by SIMS, compared to the distribution band of pK (8.20 ohm–cm) grown with the same conditions. It is seen that on the average, the pC crystals exhibit about 25% higher incorporation rate than nC crystals (with pC contents higher than pK, while nC are lower). Other studies [44,45] also show the dependency of oxygen incorporation on doping level, but to different degrees. In considering the oxygen incorporation mechanism, it would not be surprised to find that the dependency obtained would vary somewhat depending on the melt size, melt aspect ratio, etc., used in the crystal growth experiments. Several possible mechanisms behind the dependency of oxygen incorporation on the dopant concentration have been suggested [46–48]. Some data indicate that the reduced oxygen incorporation into heavily Sb-doped silicon is due to Sb2O3 evaporation from the melt,
Crucible dominating
Isorotation Large
Counterrotation Crystal dominating Large
FIGURE 3.13 The variation of Czochralski flow patterns with relative directions and magnitudes of crystal and crucible rotations. (From Carruthers, J. R. and Nassau, K., J. Appl. Phys., 39, 5205, 1968. Reproduced with permission from AIP.)
thus reducing oxygen concentration in the melt [46]. Others explain the lower oxygen incorporation observed in heavily Sb-doped silicon as due to accelerated SiO evaporation from the melt caused by simultaneous evaporation of elemental antimony [48]. In the case of pC crystal growth, the enhanced oxygen incorporation is speculated due to enhanced crucible dissolution by heavily boron-doped silicon melt. It is pointed out here that the difference in oxygen incorporation level cannot account for the difference observed in precipitation kinetics in pC and nC. The difference in the nucleation mechanism probably plays a significant role. 3.3.2.4.2 Oxygen Segregation and Microscopic Inhomogeneity Solute segregation during the solidification of a binary system is determined by the nature of its phase diagram near the solvent's melting temperature. The equilibrium segregation coefficient of the solute is a physical constant and is related to the slopes of the liquidus and solidus immediately adjacent to the melting temperature, above the primary phase of the equilibrium phase diagram as is shown in Figure 3.18. The equilibrium segregation coefficient, k0 can be lesser or greater than 1 and can be deduced readily when the equilibrium phase diagram near the primary phase is established. In practice, when the solidification is not under equilibrium condition, the liquidus and solidus will shift in positions and segregation coefficient will deviate from k0. Solute segregation phenomenon can be demonstrated by a controlled directional solidification of a binary alloy, in which the solute concentration along the direction of solidification will follow Equation 3.1. If the solution is in good mixing condition and solidification rate is small, the k value can approach k0.
24 22 30/ 2
18 16 14 12 0.0
Fraction solidified
FIGURE 3.14 Axial oxygen profile of silicon grown with crystal rotation of 30 rpm and crucible rotation of 2 rpm (in iso-rotation). The dashed line represents profiles due to normal growth. (From Lin, W., Oxygen in Silicon, ed. Shimura, F., Academic Press, 1994, chap. 2. Reproduced with permission from Elsevier.)
25 Crucible rotation
5 10 Crystal rotation 28 rpm
FIGURE 3.15 Oxygen profiles at various crucible rotation rates, with crystal rotation rate (in counter rotation) held at 28 rpm. (From Moody, J. W., Semiconductor Silicon 1986, eds. Huff, H. R., Abe T., and Kolbeson, B., Electrochemical Society, Pennington, NJ, 1986, 100. Reproduced with permission from Electrochemical Society.)
23 18 kg charge DC heating
0.4 0.5 0.6 0.7 Fraction solidified
FIGURE 3.16 Axial oxygen profiles of silicon crystal grown with several combinations of crystal and crucible rotation rates. (From Lin, W. and Benson, K. E., Annual Review of Materials Science, 17, 273, 1987. Reproduced with permission from Annual Reviews.)
In the growth of CZ silicon, the dopant segregation behavior is similar to the solute in the directional solidification of a binary alloy and the dopant distribution along the grown crystal will follow Equation 3.1. If the dopant is non-volatile, such as boron or phosphorus, and melt is in complete mixing, the k value approaches the equilibrium value. However, in the case of oxygen, the incorporation behavior is quite different from the dopant element. The crucible dissolution rate, the oxygen transport mechanisms 30 100 mm silicon growth 18 kg charge
Oxygen concentration (ppm)
10 P −IR
P + Sims
N + Sims 0
0.4 0.6 Fraction solidified
FIGURE 3.17 A comparison of oxygen incorporation levels of lightly doped p and heavily doped p and n (pC and nC) silicon crystals grown under identical conditions. (From Oates, A. S. and Lin, W., J. Cryst. Growth., 89, 117, 1988. Reproduced with permission from Elsevier.)
Solute segregation Csolid
Cliquid
K0 < 1
= k0
s Cs
conc K0 > 1
s Cl
FIGURE 3.18 Schematic showing relationship between k0 of solute and slopes of liquidus and solidus in a binary system. (From Lin, W., Proceedings of 2nd International Symposium on Advanced Science and Technology of Silicon Materials, Kono, 1996, 288. Reproduced with permission.)
(thermal- and forced- convection) used and surface evaporation rate determine the melt oxygen concentration near the growing interface for incorporation [23]. Therefore, the oxygen in the silicon melt during CZ growth is a dynamic system. Depending on the growth parameters employed, the oxygen concentration and its profile along the grown crystal can be drastically different from those expected from a "normal freezing" behavior of the dopant element. Figure 3.16 shows oxygen concentration profiles from several CZ crystals grown using different parameters but with the same grower and setup. From these profiles, it appears that there is no common "segregation" behavior for oxygen displayed by these CZ silicon crystals. In fact, these axial oxygen distributions are not the results of oxygen segregation during silicon solidification. One can certainly fit the power function of Equation 3.1 to any of the profiles in Figure 3.16 and obtain a k value. But the k value so obtained does not describe the segregation behavior of oxygen during silicon freezing, but merely represent the characteristics of the oxygen concentration change in the melt, near the growing interface in a particular growing process. Therefore, it is inappropriate and incorrect to assign the k value so obtained as a "segregation coefficient" of oxygen. More importantly, it must be emphasized that the k value so obtained has absolutely no relationship with the equilibrium segregation coefficient of oxygen, which is a physical constant. Although oxygen segregation is not visualized readily at the macro level, it is realized at the micro level at the growing interface in CZ silicon growth. In general, the degree of impurity incorporation (i.e., the effective segregation coefficient) at the growing interface is determined by the crystal growth rate f, at the interface, the boundary layer thickness d (a function of crystal rotation) and equilibrium segregation coefficient k0, as may be described by BPS expression, Equation 3.4. In the BPS expression, the k0 and diffusion coefficient D are material constants, and f and d are crystal growth parameters. If the crystal and crucible rotations are maintained constant, then the only parameter can cause variation in oxygen incorporation rate is the growth rate. An analysis of Equation 3.4 shows that the conditions listed in Table 3.1 are true. It is clear from the table that the impurity incorporation rate can fluctuate with the changing growth rate, unless the equilibrium segregation coefficient k0 is unity. However, k0Z1 is not consistent with the phase rule [49]. Furthermore, it is also realized that the change in keff is greater when k0 is further deviated from unity. In large diameter CZ silicon crystals, non-uniform oxygen
Handbook of Semiconductor Manufacturing Technology TABLE 3.1 Directions of Incorporation Rate Change in Response to Crystal Growth Rate Changes for k0!1 and k0O1 Equilibrium Segregation Coeff K0 O1 O1 !1 !1 Z1
Crystal Growth Rate f Z \ Z \
Impurity Incorporation Rate Keff \ Z Z \ keffZk0
There is no response in incorporation rate with growth rate change when k0Z1.
incorporation in the form of so-called oxygen striations are usually observed. The striations are results of impurity segregation due to fluctuations in the microscopic growth rate. The existence of oxygen striations in CZ silicon is an evident that oxygen in silicon does segregate and that k0 for oxygen is not unity. 3.3.2.4.2.1 Equlibrium Segregation Coefficient, k0, of Oxygen The k0 value of oxygen defines the basic segregation characteristics and therefore the effective incorporation rate during the silicon growth. The k0 has been of interest to researchers in order to understand the microscopic oxygen incorporation and resulting precipitation characteristics in silicon. However, the details of the phase equilibrium of the Si–O system for the Si-rich alloys have not been extensively studied. Many investigations for the k0 value of oxygen have only been carried out in the last three decades. The efforts can be divided into two categories. The first is a direct method, by oxygen concentration analysis on quenched oxygen–silicon alloys, as is commonly done in phase diagram studies. The second approach is to deduce the k0 value from the silicon crystal growth experiments. One major factor affecting the k0 determination is the accuracy of the oxygen concentration analysis. In this regard, infrared absorption using single crystal is more accurate and less uncertain than oxygen analyses on quenched samples using other methods such as differential thermal analysis. Due to the variety of methods used and accuracy of the oxygen concentration determination, the k0 values reported over the years certainly do not show a great consensus. A range of k0 values have been reported by various authors [27,50–55], ranging from greater to less than unity and including unity. Among the various k0 studies, the use of crystal growth experiments and analysis via the BPS relation has been considered a very accurate and repeatable approach. Lin and Hill [52] first applied the approach by growing a small diameter (14 cm) crystal in a large system in a controlled experiment. The oxygen incorporation level was observed to change with a change in crystal growth rate and it shows that oxygen does segregate during silicon solidification. From such an experiment, an equilibrium segregation coefficient of approximately 0.25 was deduced. Similarly, Lin and Stavola [53] studied the origin of microscopic oxygen inhomogeneity and its effect on oxygen precipitation using large-spacing oxygen striations prepared by a manually controlled crystal growth. The periodic nature of the oxygen profile shown in Figure 3.19 is a result of growth rate fluctuations and oxygen segregation. With k0!1, the oxygen fluctuations and growth rate fluctuations are "in phase" (i.e., the maxima and minima of the oxygen fluctuations coincide with the microscopic growth rate fluctuations) see Table 3.1. The growth rate fluctuations are due to asymmetrical temperature distribution in a large silicon melt. These results again show that oxygen segregates significantly, which corresponds to a non-unity equilibrium segregation coefficient. The phase analysis [53] showed that k0!1 for oxygen and that oxygen behaves similarly to arsenic in silicon (i.e., k0w0.3). More recently, Iino et al. [55] used a similar approach to study the k0 of oxygen by analyzing oxygen striations in comparison with that due to phosphorus. They obtained k0 values between 0.13 and 0.37 (averaged to 0.21). The range of values obtained are in good agreement with the values obtained by Lin et al. [52,53].
[Oi] in ppma
FIGURE 3.19 Top: IR 9 mm profile parallel to crystal axis showing periodic oxygen fluctuations. Bottom: micrograph of etched silicon after heat treatment showing precipitation bands corresponding to high oxygen regions of the fluctuations (top). (From Lin, W., Proceedings of 2nd International Symposium on Advanced Science and Technology of Silicon Materials, Kono, 1996, 288. Reproduced with permission.)
3.3.2.4.2.2 Microscopic Inhomogeneity and Oxygen Precipitation Oxygen segregation produces inhomogeneity when there is a perturbation in the growth rate. The thermal treatment experiments of silicon containing microfluctuations in oxygen concentration show that the precipitation is not uniform. Figure 3.19 bottom is a micrograph after the sample was heat treated at 10508C for 5 h following chemical etching. It shows heavy precipitate bands corresponding to high concentration regions of oxygen in the fluctuations. The precipitation density in the low oxygen region appears to be insignificant. The difference in the precipitation densities in the high and the low oxygen regions, however, cannot be accounted for by the difference in their [Oi], approximately 9% (concentration fluctuation is w4.5% about the mean). Furthermore, the fact that the precipitation occurs at the sample surface suggests that no denudation takes place. Apparently, the oxygen outdiffusion near the sample surface is suppressed by a fast nucleation/growth mechanism in the high oxygen band regions, while the precipitation kinetics at the low oxygen regions seem retarded. These preferential precipitation bands correspond to concentric ring patterns often observed in the oxidized- or heat-treated wafers following chemical etching. An example is shown in the x-ray topography in Figure 3.20. The oxygen precipitation kinetics in CZ silicon with microfluctuations is not strictly proportional to oxygen concentration. It is likely that the preferential precipitation of oxygen in the high [Oi] regions reflects the large number of nuclei available in the same regions. It is reasonable to postulate that the mechanism for inhomogeneous precipitation behavior involves the preferred nucleation of the precipitates at microdefect centers introduced during crystal growth. Such defects, ranging from several hundred angstroms to tenths of a micron in size, have been related to temperature fluctuations and remelting phenomenon at the growing interface. The grown-in microdefects in CZ silicon have been extensively studied in recent years. Basically, as in the FZ silicon, two types of microdefects may be formed during crystal growth [58]; D defects are vacancy agglomerates in nature and their formation and density are growth rate dependent. The D defects form when the growth rate is above a critical value, below which the A-defects formation are favored. The A defects are clusters of silicon self-interstitials in the form of dislocation loops. In a crystal's "D defect region," where the vacancy concentration is excessive (greater than the equilibrium value), defects such as
FIGURE 3.20 X-ray topography of heat treated CZ wafer showing concentric oxygen precipitation bands at high oxygen regions of the concentration fluctuations. (From Shimura, F., Semiconducto Silicon Technology, Academic Press, New York, 1989, 258. Reproduced with permission from Elsevier.)
crystal originated pits (COP), flow pattern defects (FPD) and laser scattering tomography defects (LST) have been observed and they have been shown to cause degradation of MOS devices (mainly gate oxide integrity) [59]. Further discussion on grown-in microdefects and their relevance to crystal growth parameters will be made later in this chapter. Nakajima et al. [60] studied the distribution of as-grown D defects in the silicon crystal in relation to microscopic growth rate fluctuations on large striated silicon crystals. The study revealed that LST defects occur at the maxima of the growth rate fluctuations, while FPD defects occur at the minima. See Figure 3.21. This result means that the LST defects occur at the high oxygen concentration regions of the [Oi] fluctuations. The LST defects have been speculated as oxygen precipitates in nature (they can be annihilated by high-temperature anneal in hydrogen) [61]. It is assumed that its formation may be the result of either (a) nucleation of oxygen precipitates on vacancy clusters or (b) direct interaction of oxygen atoms with non-clustered point defects. The existence of LST defect centers (a current crystal as shown in Figure 3.19 was grown with a growth rate of 1.5 mm/min) suggests there are far more nuclei available in the high oxygen regions than in the low oxygen regions. When subjected to precipitation heat treatment(s), as the oxygen precipitation progresses in the bands of high nuclei density, self-interstitials are ejected and flood the neighboring low oxygen regions, where the precipitation has not started. The supersaturated self-interstitials would raise the nucleation barrier in the low oxygen regions of the fluctuations and retards its precipitation process [62]. In the current discussion, the occurrence of the microdefects in the high oxygen regions may be a major factor in the formation of observed preferential precipitation. It would be interesting and useful to conduct a similar experiment with a crystal grown with microfluctuations in oxygen, but without D defects by using a low-growth rate. Such an experiment would clarify the role of microdefects in the observed preferential oxygen precipitation. 3.3.2.4.3 Controlled Oxygen Silicon Crystal Growth 3.3.2.4.3.1 Normal Czochralski Growth For ease of discussion, oxygen concentrations in silicon crystals for IC applications may be conveniently classified into high, medium, and low concentration ranges. If we designate 14–17 ppma (ASTM -F121-80)
Microscopic growth rate
Growth direction
Crystal LSTD FPD
Solid-liquid interface LSTD nuclei FPD nuclei
Axial growth distance
FIGURE 3.21 Schematic showing the occurrence of laser scattering tomography (LST) and flow pattern density (FPD) defects at maxima and minima of the growth rate fluctuations, respectively, of the CZ growth. (From Nakajima, K. et al., Semiconductor Silicon 1994, eds. Huff, H. R., Bergholz, W., and Sumino, K., Electrochemical Society, Pennington, NJ, 1994, 168. Reproduced with permission from Electrochemical Society.)
as the medium range, the concentrations above and below this range are referred to as high and low concentrations, respectively. From previous discussions, it is seen that the forced convection is an effective tool for controlling oxygen incorporation. In order to achieve a desired oxygen level with an axial uniformity in a silicon crystal, the following procedure may be carried out. Experimentally, for a given crystal growing system, one can establish oxygen incorporation profiles as a function of crystal/crucible rotation rates via studies, such as shown in Figure 3.15. Using selected rotational parameters at different stages of crystal growth, one can develop and tailor the growth processes to grow crystals of desired oxygen concentration with substantial axial- and radial-uniformity. Figure 3.22 shows an example of using variable crucible rotation rates to change the oxygen incorporation levels during the growth, while the crystal rotation rate is maintained constant. It shows that the crucible ramping to a higher rotation rate effectively raises the oxygen level and changes the oxygen concentration profile. The incorporation level can be further enhanced when alternate ramping-up and -down of crucible rotation at medium and high rates are employed, as shown in the Figure 3.22. Presumably, the action causes local "disturbance" and thinning of the boundary layer between the crucible and the melt, thus increases crucible dissolution. The example in Figure 3.22 demonstrates the usefulness of forced convection in the enhancement or retardation of oxygen incorporation. With the proper use of forced convection, including the use of alternate rampingup and -down of the crucible rotations, the increased uniform axial incorporation for high and medium ranges of oxygen can be achieved. Concentration profiles a and b of Figure 3.23 are oxygen profiles using variable crucible rotations for high and medium oxygen concentration levels. In the crystal growing systems, where the forced convection alone cannot achieve the level/uniformity desired, additional sources of oxygen may be added by increasing the melt-crucible contact surface.
0.4 0.5 0.6 Fraction solidified
Crucible rotation
FIGURE 3.22 Axial oxygen profile of a silicon crystal showing the effect of crucible rotation rate on oxygen incorporation level. (From Lin, W. and Benson, K. E., Annual Review of Materials Science, 17, 273, 1987. Reproduced with permission from Annual Reviews.)
Methods such as sand-blasting of the crucible surface [63] and the addition of an extra quartz rod/ring placed at strategic locations [64] have been used. Figure 3.24 shows a crucible design with its bottom surface fabricated in a corrugated configuration. It is shown that the additional contact sources uniformly increase the incorporation level, curve b of Figure 3.25, as may be compared with curve c, 24
Oxygen concentrarion (ppma)
FIGURE 3.23 Uniform axial oxygen profiles of silicon crystals using variable crucible rotation rates during growth (curve a and b), as compared with that due to normal growth (curve c). (From Lin, W., Oxygen in Silicon, ed. Shimura, F., Academic Press, 1994, chap. 2. Reproduced with permission from Elsevier.)
FIGURE 3.24 Schematic of the cross-sectional view of the crucible design with corrugated crucible bottom. (From Lin, W., Oxygen in Silicon, ed. Shimura, F., Academic Press, 1994, chap. 2. Reproduced with permission from Elsevier.)
grown with a normal crucible. Curve a shows an oxygen profile resulting from the silicon growth with extra quartz material adhered to the crucible bottom surface as an added oxygen source under normal growth conditions. It is pointed out that profiles a, b, and c are obtained for a fixed set of crystal and crucible rotations. When variable forced convection parameters are applied, the concentration profiles may be tailored to improve axial uniformity as shown in Figure 3.23. Curve a of Figure 3.23 is the result of using variable crucible rotation on crystal growth with additional quartz material adhered to the crucible bottom.
18 b 16
FIGURE 3.25 Axial oxygen profiles showing enhanced incorporation by (a) extra quartz adhered to crucible bottom and (b) corrugated crucible bottom. Curve (c) is due to normal growth and curve (d) is due to the use of forced convection conditions for low-oxygen incorporation. (From Lin, W., Oxygen in Silicon, ed. Shimura, F., Academic Press, 1994, chap. 2, Reproduced with permission from Elsevier.)
While thermal convection, crucible, and crystal rotations all have effects on the oxygen incorporation level, these parameters also have a great impact on the radial oxygen gradient. The relevance of these parameters to radial impurity uniformity has been discussed in Section 3.3.2 of this chapter. In order to achieve radial oxygen uniformity, the melt flows causing the radial non-uniformity in diffusion boundary layer thickness have to be suppressed. For example, when using a high crucible rotation rate to enhance oxygen incorporation, the radial oxygen uniformity is degraded unless, a high crystal rotation in the opposite direction is used. As discussed earlier, the crucible rotation creates a fluid flow in the same general direction as the thermal convection (see Figure 3.7c). Such flow will cause the diffusion boundary layer to be thinner at the edge than at the center of the interface. Consequently, more oxygen is incorporated at the center than at the edge of the crystal. The increased crystal rotation suppresses the effect of crucible rotation and thermal convection flows, and results in a thinner diffusion boundary layer. The thickness variations in the thinner boundary layer would cause less radial gradient in oxygen incorporation. The faster crystal rotation also results in more mixing in the melt, adjacent to the growing interface and tends to improve the melt concentration uniformity. It should be mentioned that there exists a drastic decrease in oxygen concentration in the CZ crystal's radial oxygen profiles near the crystal's periphery region. This is due to oxygen out-diffusion during the crystal growth following solidification. In large melt growth, the controllability for low level oxygen incorporation is more limited than that for the medium and high incorporation levels, due to the domination of thermal convection function as the transport of oxygen-rich melt. This is enhanced for the growth of the crystal portion near the seed end. The curve d in Figure 3.25, represents a typical range of concentration profiles in the low oxygen range (11–14 pima) that may be obtained with the experimental hot-zone used. In this range, further uniformity of the profile can be obtained by increasing the incorporation level of the lower concentration portion of the profile using crucible ramping. However, suppressing the seed-end oxygen incorporation by forced convection is usually not an efficient process. It often results in degradation in the oxygen radial gradient and other disadvantages in growth conditions and crystal properties. From the above discussion, one realizes that in normal CZ growth, the small and/low-aspect-ratio melt configurations facilitates the incorporation of low-levels of oxygen due to the reduction of thermal convection. Such a growth environment may be obtained by growing silicon from a small/shallow inner crucible in a double-crucible type set-up. Axial uniformity as well as concentration control using a double-crucible set-up has been demonstrated [65]. Although, such an apparatus is more involved than a normal CZ growth, as the CZ charge size continues to increase, the concept of a small/shallow melt growth in a double-crucible is capable of extension to continuous CZ growth, to be discussed later in this section. For silicon materials requiring low oxygen and low microdefect density, however, the most effective method is growth under an applied magnetic field. For very low level oxygen incorporation (a few parts per million atomic), crucibles made of non-oxygen containing materials, such as Si3N4, have been used for silicon crystal growth [66,67]. In this case, the source of oxygen is from the silica beads added in the silicon melt. The oxygen incorporation is controlled by the ratio of the surface area of the SiO2 beads to the free melt surface. In general, the oxygen incorporation in normal CZ silicon growth from a large melt can be controlled within G1.5 ppma of the normal concentration range of interest. 3.3.2.4.3.2 Magnetic Field Applied Czochralski Growth (MCZ) From the previous discussion, it is clear that the thermal convection in a large silicon melt plays a major role in determining many aspects of the crystal quality of CZ silicon. In particular, oxygen concentration as well as dopant and oxygen uniformity are of concern. The ability of a magnetic field to suppress the thermal convection in electrically conducting fluids was demonstrated in the 1960s in crystal growth experiments [68]. In 1970, a transverse magnetic field was applied for the same purpose in CZ growth of indium antimonide [69]. The application of a magnetic field across an electrically conductive melt increases the effective kinematic viscosity of the melt [70] and thus, suppresses the thermal convection and related temperature fluctuations in the melt.
Hoshi et al. [71] first reported CZ silicon crystal growth under an applied transverse magnetic field. Aside from a reduction/elimination of impurity striations, MCZ displayed the potential for growing lowoxygen, low-microdefect, and higher resistivity CZ silicon for applications in power devices and imaging devices such as CCD. Since 1980, various types of magnetic field configurations [72,73] in terms of field directions (VMCZ for vertical, HMCZ for horizontal, and cusp magnetic field) and the magnet types used (normal conductive or superconductive), have been developed and crystal growth studies have been carried out. Figure 3.26 shows a comparison of the magnetic field direction/distribution of the three MCZ methods. In general, both VMCZ growth and HMCZ growth have been shown to reduce temperature fluctuation and related growth rate fluctuations, resulting in reduced impurity striations. However, the magnetic field effects on impurity incorporation behavior vary widely depending upon the field direction with respect to the growth axis and the field strength. For example, increased field strength enhances oxygen concentration under a vertical field [74], whereas oxygen incorporation is retarded under an increased transverse magnetic field [75]. Therefore, a transverse magnetic field facilitates the
Hr Hz
FIGURE 3.26 Schematics showing arrangements for magnetic Czochralski; (a) horizontal magnetic field, (b) vertical magnetic field and (c) cusp magnetic field. The arrows indicate field directions.
incorporation of low (!5!1017 atoms/cm3) to medium (5–10!1017 atoms/cm3) oxygen concentrations, whereas a vertical field facilitates the growth of silicon with medium to high (O1018 atoms/ cm3) oxygen concentrations. In fact, extremely high oxygen concentrations, near or above the solubility limit, can be incorporated under certain growth conditions with vertical magnetic fields [76,74]. Forced convection induced by crystal and crucible rotations can also perturb the oxygen incorporation under a magnetic field. Several large diameter MCZ crystal growth experiments from large melts have provided information on the difference in oxygen incorporation behavior between HMCZ and VMCZ. For example, Ohwa et al. [76] made a comparison of oxygen incorporation behavior between VMCZ and HMCZ using the same puller, as is shown in Figure 3.27. In the HMCZ mode, a low level of oxygen concentration (w4 ppma) is incorporated in a horizontal magnetic field of 0.25 Tesla (2500 G) with good axial uniformity. The crystal rotation shows no effect on the incorporation level under this condition. However, it is shown in another study [75] that, under HMCZ, an increase in crucible rotation increases the oxygen incorporation level. As in the normal CZ, high crucible rotation often results in some degradation in radial uniformity. In such an instance, the use of a higher crystal rotation rate would help to reduce the oxygen radial gradient. Figure 3.27 also shows that, in VMCZ mode, higher oxygen concentration may be incorporated using a magnetic field strength one-third of that for HMCZ. Unlike HMCZ, the oxygen incorporation level in VMCZ is a strong function of crystal rotation and the
Solubility limit
Oxygen concentration (× 1017 cm−3)
VMCZ 0.08 Tesla 25 kg 15 rpm 2 rpm
HMCZ 0.25 Tesla 30 kg 25 rpm 15 rpm
FIGURE 3.27 Oxygen profiles of silicon crystals grown under horizontal and vertical applied magnetic fields under the conditions indicated. The data show that crucible rotation rate has significant enhancement effect on oxygen incorporation under vertical magnetic field. (From Ohwa, M. et al., Semiconductor Silicon 1986, eds. Huff, H. R., Abe T., and Kolbesen, B., Electrochemical Society, Pennington, NJ, 1986, 117. Reproduced with permission from Electrochemical Society.)
incorporation switches to a much higher level through a sharp transition during the crystal growth. Both the incorporation level and the transition point are clearly a function of crystal rotation, indicating that under VMCZ mode, the crystal rotation induced forced convection acts as a major transport mechanism. Figure 3.28 shows models proposed by Hoshi et al. [77] for the magnetic damping of the melt flow for VMCZ and HMCZ. In view of the model for VMCZ, the melt flow from outer to center regions of the melt (flow perpendicular to the vertical magnetic flux) are retarded. Under this condition, the forced convection induced by the crystal rotation is an effective transport for the oxygen-rich melt from the crucible bottom to the growing crystal. As the melt aspect ratio is reduced during the crystal growth, at some transition point, the forced convection would take over as the dominant transport mechanism and the incorporation level is sharply increased. The occurrence of this "transition" seems to depend on the crystal rotation used, the higher the crystal rotation, the sooner this transition occurs during the growth. It is interesting to note that the observed "transition" in incorporation level for the VMCZ growth is similar to that discussed earlier for normal CZ growth under high crystal rotation (30 rpm) with the crucible in iso-rotation mode (2 rpm) (see Figure 3.14). In both cases, the behavior is attributed to strong crystal-rotation-induced convection. In the case of HMCZ, the model of Hoshi et al. shows that the transverse magnetic flux damps the vertical melt flow near the wall, due to thermal convection and crucible rotation, resulting in retarded oxygen transport and therefore, a low level of oxygen incorporation. The forced convection induced by the crystal and crucible rotations is more effective in the transverse direction, parallel to the magnetic flux. Thus, the increased crucible rotation would help crucible dissolution and transport of the oxygen-rich melt follow flow path delineated in the model. The results by Ohwa et al. discussed above and other large-diameter, large-melt VMCZ growth indicate that oxygen incorporation (and other growth characteristics) in VMCZ is affected by many variables and is not easily controlled. Furthermore, impurity segregations were observed to depend on the vertical field strength [78,79]. The segregation coefficient of the impurity (such as phosphorus, gallium, carbon, and oxygen) tends to increase (towards unity) as the magnetic field increases. However, the radial uniformity of these impurities is significantly degraded in a vertical field [74]. For example, the radial oxygen gradient in a 100-mm-diameter silicon crystal can reach 30%–50% when grown in a high vertical field. These properties are not desirable. The change in segregation and severe degradation of the radial
Magnetic flux Forced convection by ws Forced convection by wc Oxygen flow
wc VMCZ
wc HMCZ
FIGURE 3.28 The effect of vertical and horizontal magnetic field on damping melt flow in Czochralski crucible. (From Shimura, F., Semiconducto Silicon Technology, Academic Press, New York, 1989, 258. Reproduced with permission from Elsevier.)
gradient found for growth in VMCZ has not been reported for HMCZ growth. From considerations of growth control ability and crystal properties, HMCZ is the preferred approach for MCZ growth. The HMCZ method can grow large diameter silicon with oxygen levels ranging from a few parts per million atomic to over 20 ppma with axial concentration uniformity. The CZ crystal growth under an applied cusp magnetic field was designed to minimize the undesirable characteristics of VMCZ discussed above [80,81]. A CZ growing system with cusp magnetic field uses two sets of coils (often superconducting) co-axially with the crystal, which are energized in opposing directions [82], as shown in Figure 3.26c. In this arrangement, the crystal-melt interface is located in the symmetry plane between the two coils and is maintained in this position throughout the growth by adjusting the crucible height. The resulting magnetic field distribution in the growing system is represented by the dotted lines in Figure 3.26c. Essentially, the major and significant magnetic components are vertical magnetic field orthogonal to the crucible bottom, Hz, and the radial field orthogonal to the sidewalls of the crucible, Hr. The melt free surface has no orthogonal magnetic field component. As discussed earlier, the crucible erosion rate and evaporation rate at the melt free surface are the factors determining the oxygen concentration in the bulk melt, and therefore the incorporation level. The erosion rate at the sidewall is believed to be under diffusion control. The orthogonal components of the magnetic field at the sidewall and bottom have the damping effect on melt flows parallel to the crucible surface (such as thermal convection flows), resulting in thicker diffusion boundary layer, and thus a lower erosion rate. At the melt free surface, on the other hand, the boundary layer controlling the oxygen evaporation is determined by the radial melt flows, such as Marangoni flows and centrifugal flows pumped outwards from the crystal by the crystal rotation induced forced convection. But these flows are not damped since there are no orthogonal magnetic field components at the melt free surface. Thus, the oxygen level can be reduced by retarding the crucible erosion while leaving surface evaporation unaffected. The degree of oxygen level reduction is proportional to the applied field strength generated by the two coils. However, when the melt surface is located away from the symmetry plane of the cusp magnetic field, the melt surface will be subjected to the effect of orthogonal magnetic components, resulting in reduced oxygen evaporation and increased oxygen level [79]. In general, the main application of cusp magnetic field applied CZ growth is in the low oxygen incorporation in addition to the usual advantages of magnetic CZ, such as reduced temperature fluctuations in the melt, etc. The orthogonal components acting on the melt surface and on the crucible walls can be controlled independently. Thus, the controllability of the magnetic field is the main benefit such that the desired incorporation level with good axial uniformity can be achieved. The crystals so grown are without degradation in radial properties and abnormal segregation behavior of the dopant experienced by the VMCZ incorporation. However, it is essential to optimize the crystal and crucible rotation condition to match the applied field strength and fraction of solidification, during the growth, in order to achieve radial and axial uniformity of oxygen and dopant [83].
3.3.3 3.3.3.1
Grown-In Microdefects Relevance to Growth Parameters
Microdefects are formed in normal "dislocation-free" melt-grown silicon crystals due to condensation or agglomeration of excess point defects at or near the growing interface. In the 1970s, the so-called A and B defects were observed in FZ crystals [84]. The A defects were identified as small "extrinsic" dislocation loops and B defects the embyros for the A defects as characterized by transmission electron microscopy (TEM) [164]. The defects are the result of condensation of Si self-interstitials and they can be electrically active when decorated, as may be revealed by EBIC (electron beam-induced current) [85]. Fast growth rates were found to eliminate the A and B defects [84]. The other type of defects, termed "D" defects in FZ crystals were attributed to the condensations of excess vacancies. In recent years, the microdefects in as-grown CZ silicon have been studied extensively. Defects similar to D and A defects found in FZ silicon have been observed in CZ silicon [86]. The major findings and their relevance to crystal growth are discussed in the following.
In a CZ silicon grown with a "normal" growth rate, the cross-section can often be divided into two regions: the inner region is vacancy-rich and the outer concentric region is silicon self-interstitial rich. The two regions are separated by a concentric ring border that can be characterized by populations of oxidation induced stacking faults (OSF) upon oxidation of the wafer as is shown in the schematic in Figure 3.29. Empirically, it has been found that the diameter of the "OSF ring" is reduced when the growth rate is reduced and vice versa. The microdefects have been observed inside the OSF-ring by several detection methods; Crystal originated pits (COPs) as revealed by repeated standard clean 1 (SC1) of the wafer surface (as small scattering centers) [87] (see Figure 3.30), flow pattern defects (FDPs) as delineated by the Secco etch of the wafer surface without agitation [88], laser scattering tomography (LST) defects [89] or by an optical precipitate profiler (OPP). Their respective defect densities have been correlated with the crystal growth rate (Figure 3.31) and with the defect densities of the gate-oxide integrity (GOI) measurements (Figure 3.32). Furthermore, from the correlation such as shown in Figure 3.33, it was speculated that the defects detected inside the OSF-ring by different methods have a common origin, i.e., they are agglomerates of vacancies in nature and are referred to as "D" defects. Systematic studies have found that COPs, FPDs, and LSTs are same defects revealed by different detection methods [90]. The defects in the region outside the OSF-ring are referred to as "A" defects, which have been shown not to affect GOI, but degrade DRAM performance and yield. "A" defects are normally observed as "large pits" following Secco etch of the wafer surface. Due to the harmful effect of the D defects on the gate oxide quality and A defects on DRAM, it is desirable to minimize the formation of clusters of either of these point defects, but to achieve a nominal low level of each type. In the extreme case, the diameter of the OSF-ring shrinks to zero and whole wafer is free of "D" defect. Experimentally, the OSF-ring diameter was found to increase as the growth rate is increased. However, the dependence of the ring diameter on the pull rate behave remarkably different for different crystal diameters or when the surface cooling condition is changed via, for example, an added radiation shield [91]. A radiation shield serves to isolates the crystal surface from the radiation heat from the heater and silicon-melt surface, resulting in an increase in surface cooling rate and therefore, an
A-Defect area OSF area D-Defect area
FIGURE 3.29 Schematic showing a ring region (oxidation induced stacking faults region upon oxidation) separating A-defect-rich and D-defect-rich areas.
12 CZ 1
Number of COP (a.u.)
10 Polished
1h SC1 6
2h SC1 3h SC1
4h SC1
2 0 .12 – .14
.16 –.18
.14 – .16
.18–.20
>.30
LPD Size (μm)
FIGURE 3.30 Light scattering point counts due to crystal originated pits (COPs) defects as a function of length of standard clean 1 (SC1) clean solution treatment and "particle size." (From Wagner, P. et al., Proceeding of 2nd International Symposium on Advanced Science and Technology of Silicon Materials, Kono, 1996, 101. Reproduced with permission.)
increase in axial thermal gradient in the crystal near the liquid–solid interface. The net effect depends on the heat shield design. Crystal growth experiments with various designs of heat shields show that the OSF-ring diameter, and therefore the fraction of the silicon wafer containing D defects, depends not only on the crystal growth rate, but also the axial thermal gradient in the crystal at the growing interface. Based on the experiments, von Ammon et al. [91] found that there exists a constant critical value of V/G(r)Z
FPD density (cm2)
Growth rate (mm/min)
FIGURE 3.31 Flow pattern defect density as a function of CZ crystal growth rate. (From Yamagishi, H. et al., Semiconductor Silicon 1994, eds. Huff, H. R. and Bergholz, W., and Sumino, K., Electrochemical Society, Pennington, NJ, 1994, 124. 58. Reproduced with permission from Electrochemical Society.)
Breakdown yield (> 8MV/cm) (%)
100 80 60 40 20 0 100
CZ–1:Oi=7.1–12.8 CZ–2:Oi=14.1–15.6 ×1017(atoms/cm3) FZ–1:N2 doped FZ–2:N2 non–doped
102 FPD density
(1/cm)2
FIGURE 3.32 C-mode oxide break yield as a function of flow pattern defect density. (From Yamagishi, H. et al., Semiconductor Silicon 1994, eds. Huff, H. R., Bergholz, W., and Sumino, K., Electrochemical Society, Pennington, NJ, 1994, 124. Reproduced with permission from Electrochemical Society.)
FPD density (1/cm2)
CcritZ1.3!10K3 cm2 minK1 KK1, which allows a calculation of the radial position r of the OSF-ring, if the pull rate V and radial variation of the axial temperature gradient G(r) are known [91,92]. The empirical formula can be explained based on Voronkov's theory [93,94] which predicted a change from vacancy to Si interstitial type defects at a critical value of V/G. Based on the empirical equation, Figure 3.34 shows a computed dependence of OSF ring diameter on the crystal pull rate for various crystal diameters. It shows that the larger the crystal diameter, the slower the pull rate is required to completely eliminate the vacancy type defects [95]. At 100-mm-diameter, a pull rate of 0.65 mm/min is required for vacancy defect-free growth, while a much lower pull rate, 0.35 mm/min, is required to
CZ : 7.1–15.6 3 ×1017(atoms/cm ) FZ−1:N2 dope FZ−1:N2 non−dope
101 102 COP density (1/5" wafer)
FIGURE 3.33 Correlation between COPs and FPDs. (From Yamagishi, H. et al., Semiconductor Silicon 1994, ed. Huff, H. R., Bergholz, W., and Sumino, K., Electrochemical Society, Pennington, NJ, 1994, 124. Reproduced with permission from Electrochemical Society.)
OSF-ring diameter D (%)
100 100 mm 80
300 mm 400 mm
0.6 0.7 0.8 Pull rate V (mm/min)
FIGURE 3.34 Oxidation induced stacking faults-ring diameter as a function of crystal pull rate for different crystal diameters. (From von Ammon, W., Proceedings of 2nd International Symposium on Advanced Science and Technology of Silicon Materials, Kono, 1996, 233. Reproduced with permission.)
eliminate the vacancy defects for the 300-mm-diameter crystal. Too low a pull rate, however, presents a problem in maintaining a stable and steady growth rate, which is essential for dislocation-free growth. The above discussions on the occurrence of the D defects are for lightly doped silicon crystal growth. The defect formation mechanism is apparently different for heavily doped boron silicon. It is found that the diameter of OSF ring [95] and COP density [96,97] decrease dramatically with increasing boron concentration (for resistivity !20 m ohm–cm, Figure 3.35). This effect was attributed to Fermi-level effects of boron-vacancy pairs [98]. The other probable explanation was based on the modification of the generation mechanism and/or diffusivity of the intrinsic defects in the strained silicon lattice, induced by the high concentration of smaller-sized boron atoms compared to silicon.
COP> 0.12 μm (a.u.)
10 CZ I CZ II
10 12 14 Resistivity (mΩ − cm)
FIGURE 3.35 Crystal originated pits density as a function of crystal resistivity, showing that the crystal is essentially COP-free when the resistivity is less than 10 m ohm–cm. (From Wagner, P. et al., Proceedings of 2nd International Symposium on Advanced Science and Technology of Silicon Materials, Kono, 1996, 101. Reproduced with permission.)
W SiO2 Si–SUB
55° 100 nm
FIGURE 3.36 Cross-sectional transmission electron microscopy (TEM) observation of an oxide defect. (From Itsumi, M. et al., Proceeding of 2nd International Symposium on Advanced Science and Technology of Silicon Materials, Kono, 1996, 270. Reproduced with permission.)
Defect Structures
Although the microdefects in CZ silicon have been detected for quite sometime by various methods as mentioned above, only recently the detailed structures have been revealed by TEM and it is meaningfully correlated to the features detected by the other methods. Modern day bulk defect detection methods, such as IR Laser Scattering Tomography and precision thinning/etching tools, such as FIB (Focused Ion Beam) make it possible to isolate bulk defects in a small thin sample to be studied by TEM. Since the most significant impact of the microdefects in silicon is on the GOI failures, the defects were first observed by TEM as voids by Parks et al. [99], as the origin of oxide defects. The octahedral voids were also observed to exist under the dielectric breakdown sites of thermal oxide films by the Cu decoration method [100], Figure 3.36. The TEM also identified the LST defects in the silicon
2 nm 2 nm [100] [110]
50 nm (a)
10 nm (b)
FIGURE 3.37 Cross-sectional TEM view of LST defects Photo in (a) is an enlarged view of (b) showing oxide layer at void-crystal interface. (From Itsumi, M. et al., Proceedings of 2nd International Symposium on Advanced Science and Technology of Silicon Materials, Kono, 1996, 270. Reproduced with permission.)
Si−SUB
FIGURE 3.38 Schematic representation of an octahedral defect structure. (From Itsumi, M. et al., Proceedings of 2nd International Symposium on Advanced Science and Technology of Silicon Materials, Kono, 1996, 270. Reproduced with permission.)
bulk as octahedral voids. [101–103]. In general, the TEM findings on the D defects can be summarized as voids bounded by {111} planes having a structure of two inverted pyramids, Figure 3.37 and Figure 3.38. The analyses by the energy dispersive x-ray spectroscopy (EDXS) indicated that there are no other signals except silicon. The silicon signal is weaker inside the defect than its surrounding, an evidence of a cavity. Their typical size is 0.1–0.2 mm and they often appear as twins or triplets, although the individual defect is usually an incomplete octahedron (some tops of the octahedrons are cut to result in a complex polyhedrons). The sidewalls of the octahedron are lined with an oxide layer; EDXS and Auger spectroscopy analyses suggested that the oxide is SiO2 and is approximately 2 nm thick, Figure 3.37b. The void structure with oxide linings in the sidewalls make it unique as a CZ crystal defect, since CZ crystal growth incorporate significant amount of interstitial oxygen. The formation mechanism of the octahedron void defects is not clear. It involves complex interplay between several crystal growing factors. The temperature fluctuations at the growing interface, the growth rate (and axial thermal gradient in the crystal) and dwell time at a critical temperature range (several temperature ranges have been proposed in between 900 and 11008C [104,105]) in the post-freezing crystal all play a role. Several models have been proposed [106].
3.4 3.4.1
Trends in Large Diameter Silicon Growth Evolution in Crystal Diameter
As semiconductor technology continues to advance, the IC production is projected to be in sub-60 nm technology generation in 2008 [ITRS]. In parallel with the design rule decrease, the increased circuit design complexity results in an increased chip size. This has been the major driving force for increased wafer diameter for the last 30 years, that is, to increase the required number of IC's per wafer in order to reduce IC manufacturing cost. Figure 3.39 shows the wafer diameter evolution in the industry, since wafer diameter was about 1 00 in 1960. The 200 mm was initiated in the late 1980s. In 1995, the
Wafer diameter (mm)
Evolution of silicon crystal diameter.
development of 300 mm wafer was initiated, targeting for IC manufacture in the 0.25–0.18 mm design rule generation, although the 300 mm era only began in earnest in about 2002 at smaller design rules. Concurrently, Japan launched a project for the development of the 450 mm wafer era technology. In the up-scaling of the wafer diameter, in the 300–450 mm-diameter range, the most significant technical challenges are in the crystal growth. The growing process is far more complex than in the past. Unlike small diameter crystals, the dislocation-free as-grown yield will dominate the cost of the manufacturing of 300–450 mm-diameter wafers. To economically produce large diameter silicon crystals, one needs to employ a large charge size for growing a long crystal. A charge greater than 200 kg for 300 mm-diameter crystal growth or 450 kg for a 450 mm crystal is necessary. At this melt size, the thermal convection is severe. The temperature fluctuations associated with the thermal convection will make initial thin neck growth more difficult. The thermal convection would also result in higher oxygen incorporation in the crystal. It is common to apply an external magnetic field, such as a cusp magnetic field, to the large melt to reduce the thermal convection effect and the melt-crucible interaction. When growing a CZ crystal weighing 150 kg or more employing a thin neck growth to achieve the initial dislocation-free seed, one must consider the risk of fracturing of the thin neck due to the crystal weight exceeding the fracture strength of silicon. An estimate strictly based on fracture strength in tensile mode [107] predicts that the crystal weight limit is about 200 kg when the smallest neck is w4 mm in diameter (a targeted neck diameter commonly used for necking). However, for 400–450-mm diameter growth, the crystal weight needs to be in the range of 400–500 kg to be comparable with the 200 mm crystals in production economics. At this weight level and to avoid neck fracture, the "Dash Neck" diameter needs to be larger than 6 mm, a diameter that is difficult to achieve dislocation free structure in the necking process. One of the solutions is to devise a "crystal suspending system" to help support the crystal weight through a "subsidiary cone" grown following the dislocation-free neck is established
Wire Seed holder Dash necking
Crystal suspending system
Subsidiary cone Necking for suspending Cone Si single crystal >400 kg
Silicon melt >450 kg
FIGURE 3.40 Schematic of a suspending system for weight support of large diameter growing crystal. (From Yamagishi, H. et al., Proceedings of 2nd International Symposium on Advanced Science and Technology of Silicon Materials, Kono, 1996, 59. Reproduced with permission.)
[108]. An example of such a proposed device is shown in Figure 3.40. Another crystal weight related problem is the "creep" phenomenon at the high stress concentration region at the "plastic temperature," O9008C. The intersection of the crystal neck and "crown" is such a region [110]. When the stress from the crystal weight (plus the meniscus column and surface tension in the melt) exceeds the critical resolved shear stress for slip, slip dislocations will be generated and propagated down the crystal, along the slip systems, h110i/(111). Two possible consequences may result. If the slip exits the crystal, the dislocation-free growing process will not be interrupted, but the crystal length above this point will not be useful. If the dislocation reaches the growing solid–liquid interface, the continued growth will not be dislocation-free. The latter case occurs when the crystal length, L, is less than LZR tan 54.748, where R is the radius of the growing crystal. Besides weight related problems, the large diameter silicon requires growth rate reduction as well. As the crystal diameter is increased, dissipation of the massive latent heat of solidification from the freezing interface becomes more difficult, since the heat transfer paths are longer. This can be understood from the heat balance shown in Figure 3.3. In silicon crystal growth, a sufficiently high growth rate is essential to maintain a steady crystal growth, in order to maintain the dislocation-free structure. One can enhance the growth rate by enhancing the heat transfer rate via increased crystal surface cooling. Radiation shields have been used to reduce the radiation effect from the melt and the heater [91]. However, by doing so, the thermal gradient is increased resulting in more curved isotherms and interface shapes, enhancing the condition for higher thermal stress. The stress-induced slip can
occur causing structure loss. In the severe case, the high thermal stress can cause crystal cracking. Eventually, the growth rate issue may be a limiting factor in determining the maximum diameter for CZ silicon. The increase in diameter has a profound effect on the crystal's cooling rate and, therefore, the microdefect formation. If the growing crystal's V/G is above the critical value, D defects are generated within part of, or entire radius. It is now understood that the formation of D defects (vacancy clusters), such as COPs, FDPs, and LSTs, the defect density is a function of the dwell time in the temperature range of 9008C–11008C. [104,105]. Slow cooling reduces GOI defect density. As the crystal diameter is increased, the crystal cooling rate decreases, and the dwell time at 9008C–11008C increases. It was estimated that for the 300 mm crystal, the dwell time in this temperature range is 50% longer than that of the 200 mm, 100% for the 400 mm case [95]. Therefore, the diameter increase causes the reduction in D defect density. The D defects on wafer surface cause oxide thinning and its density is directly correlated with the defect density in the GOI test. Therefore, it appears that the diameter increase certainly has a positive effect on the microdefect density. If the diameter increase requires a decrease in the growth rate, then V/G may be in the region that the entire crystal is Si interstitial rich. The defects are in the form of small dislocation loops (A and B defects). From the available reports, it appears that the A and B defects have no effect on the GOI, but may cause junction leakage in devices such as charge storage in DRAM, as crystallographic defects, especially if decorated with metallic, are potential recombination centers. The Si self-interstitial-rich silicon also does not favor oxygen precipitation, as SiO2 induces excess Si atoms in the crystal. Therefore, oxygen precipitation in such silicon may be impeded. This factor plus the fact that the large diameter crystals are low in oxygen (most are grown with MCZ) will require significant research to assure internal gettering in these materials. It appears that the large diameter crystals grown today and in the foreseeable future will contain either vacancy or self-interstitial type microdefects or both using the "normal" crystal growing processes. However, with the understanding of the relationship between intrinsic point defects and V/G during the crystal growth, a growth process may be designed to grow defect-free silicon (Pure silicon or Nearly Perfect Crystal), which is free of COPs and dislocation loops [111]. The schematic in Figure 3.41 shows the relationship between V/G and grown-in defect concentration. There is a region of V/G within which the concentrations of vacancy and interstitials are below the threshold of defect formation. In order for a crystal to be in the defect-free, a narrow range of V/G value has to be maintained across the growing interface during the whole growing process. The vertical thermal gradient can vary from center to edge of the growing crystal, and it is also a function of crystal length grown (or the size of the remaining melt). Therefore, maintaining V/G to a target value presents major challenges in process design as well as the design of grower's hot-zone thermal characteristics. With the availability of defect-free silicon, via growing process control, the device makers have more options in materials selection based on factors related to cost, nature of the processing, etc. The epitaxial wafers and hydrogen (or argon) annealed wafers [113] are also widely used. The current hydrogen/argon annealing process can provide a 5–10 mm deep defect-free zone and, with designed thermal ramping, can provide nuclei for internal gettering (IG; by temperature ramping during anneal). The epitaxial silicon layer has a higher quality than the melt grown bulk silicon. The layer is essential free of interstitial oxygen, carbon, and microdefects, and lower in surface particle and metal contamination than the bulk wafer. The DRAM manufacturing group has been the largest user of the polished wafers. The microdefect problem associated with the bulk wafer may drive a significant fraction of the DRAM manufacturers to switch to epitaxial wafers. Two possible epi structures exist: p/pC and pK/pK. The former has also been popular with the microprocessor and application specific integrated circuit (ASIC) manufacturers, the advantages including improved gate oxide quality, internal gettering, latchup immunity, etc. The pK/pK approach is useful to "mask" the microdefect problems in the polished pK wafers. The microdefects, neither dislocation loops nor voids are not found to extend into the epitaxial layer during the epitaxial growth [114].
[V ] or [I ]
Agglomerate of vacancy
(v/G)*/COP (v/G)*OSF
COP(Void defects) V-rich
(Pure silicon) (v/G)*L/DL
I-rich
Oxygen precipitates
v/G 0.5 mm
(OSF nuclei) Agglomerater of interstitial silicon (Large dislocation loop)
FIGURE 3.41 Schematic showing grown-in defects depending on the V/G ratio, where V is growth rate and G is the thermal gradient at the solid/melt interface. (From Rozgonyi, G. A., Semiconductor Silicon 2002, ed. Huff, H. R., Fabry, L., and Kishino, S., Electrochemical Society, Pennington, NJ, 2002, 149. Reproduced with permission from Electrochemical Society.)
Continuous Czochralski Silicon Growth
The idea of continuous CZ growth is due to the fact that, as the silicon diameter continues to increase the maximum grown crystal length of the batch CZ process is limited by the charge size. The initial motivation of the approach of the continuous growth was for the increased crystal length and thus improved throughput and operation cost of the CZ grower. A continuous CZ growth based on a two-container system was first demonstrated by Fiegl [24]. In addition to increased crystal length, many other desirable crystal properties were also demonstrated, such as improved axial uniformity of both
+ Dopant Co
Co / k Co
FIGURE 3.42 Schematic showing a generalized two-container arrangement for crystal growth from a constant volume melt by continuous feed. (From Lin, W. and Benson, K. E., Annual Review of Materials Science, 17, 273, 1987. Reproduced with permission from Annual Reviews.)
dopant and oxygen concentrations. In particular, the arrangement affords the use of a small and shallowmelt CZ set-up in the growing container. In many ways, the two-container arrangement with crystal pulling from a constant melt volume is the same as the double-crucible operation. Figure 3.42 is a generalized two-container system reconfigured from a constant-volume double-crucible, where V1 and V2 are the melt volumes in the outer and inner crucibles, respectively, in a double-crucible set-up. The reconfigured arrangement facilitates the addition of polysilicon and dopant. Only the outer crucible (the feeder) needs to be lifted or adjusted for the melt level control for constant volume/melt level in the growing crucible. The system offers the same advantages as the double crucible in an axial uniformity in dopant and oxygen and the benefit of a small melt effect. Figure 3.43 shows the uniform axial oxygen profile obtained due to "constant volume" growth. The uniform axial dopant profile at concentration C0 is obtained when the initial doping of the growing crucible is C0/k and the feeding crucible concentration is maintained at C0. The incorporation behavior of impurities in the feed material is similar to one-pass
Dopant concentration
Oxygen concentration
Increased v2
Decreased v2
Impurity concentration
KC I
V Volume solidified
FIGURE 3.43 Axial oxygen, dopant and impurity concentrations along the crystal grown from the arrangement shown in Figure 3.43. The oxygen concentration level can be adjusted by changing the melt volume (From Lin, W. and Benson, K. E., Annual Review of Materials Science, 17, 273, 1987. Reproduced with permission from Annual Reviews.)
Diameter 100 mm Pull speed 100 mm/h P-type
10 5 kg
40 60 80 Crystal length (cm)
FIGURE 3.44 Uniform axial oxygen distributions from "constant volume" continuous-feed silicon growth. The oxygen level is shown to depend on the melt size. (From Fiegl, G., Solid State Technol., August permission from Solid State Technology.)
zone leveling [22] with the "zone width" being equivalent to the melt volume in the growing crucible, V2. In the continuous growth mode, V1 is the total melt volume passing from the feeding (outer) crucible to the growing crucible before V2 is consumed and reduced. The oxygen concentration level is determined by the volume and aspect ratio of the melt in the growing crucible (see Figure 3.44). While the continuous "feed and pull" system with two containers appears straightforward, many engineering challenges remain to be solved or improved for the method to be practical. Among the problems to be solved are the liquid melt transfer and establishment of thermal stability and radial thermal symmetry in the melt while receiving replenishment melt from an external source. In recent years, with the availability of high-purity, small-diameter silicon beads (w0.1–1 mm) from the fluidized bed process, "feed and pull" may be carried out in a double-crucible arrangement as illustrated in Figure 3.45a and b. In case of configuration in Figure 3.45a, the partition between the inner and outer crucibles can be inserted, after the polysilicon charge is completely melted, before the seeding begins [115]. Crystal length of 2 m grown under such continuous "feed and pull" mode was demonstrated. If the total melt volume is kept constant, the partition separating both the melt concentrations becomes
Poly Si +dopant
Poly Si +dopant Co
Co/k Co
Co/k
Silica baffle
FIGURE 3.45 Crystal growth from double-crucible arrangements with (a) constant melt level or (b) constant inner melt volume, maintained by continuous-feed (c) crystal growth from a single container equipped with a circular silica baffle. Melt level is keep constant by continuous feed. The melt concentration is maintained at C0/k. (From Lin, W. and Benson, K. E., Annual Review of Materials Science, 17, 273, 1987. Reproduced with permission from Annual Reviews.)
unnecessary. The resulting "one melt" growth retains the advantages of double-crucible arrangements, Figure 3.45c. In this arrangement, the oxygen concentration level is controlled, as in the two-container case, by the melt volume and aspect-ratio. However, the application of forced convection for an additional oxygen incorporation control is more restricted than for standard batch processes. Furthermore, in this design, the single crucible contains a physical barrier to prevent unmelted silicon particles from reaching the growing crystal and a baffle that reduces thermal convection. One may also view the continuous feed mechanism as playing the role of the outer crucible, which supplies silicon with dopant concentration C0 (the intended concentration in the crystal). The small-diameter polysilicon beads add a new dimension to the development of continuous "feed-and-pull" silicon growth. Shiraish et al. [116] uses liquid-feed for continuous crystal growth of large diameter silicon (150 and 200 mm-diameter crystals). In this approach, the polysilicon rods are melted into liquid silicon immediately above the growing melt, inside the growing chamber, and continuously fed into the CZ melt. The continuous-mode growth provides flexibility where the melt volume and aspect ratio of the growing crucible can be adjusted for oxygen incorporation level. This is especially important for the low oxygen incorporation, which cannot be easily attained in the standard CZ growth with a melt size of 80 kg or larger.
Wafer Preparation
Silicon semiconductor devices are mostly fabricated on polished wafer or epitaxial wafer. Thus, the first step in device fabrication is the preparation of mirror polished, clean, and damage-free silicon surfaces in accordance with the specifications. As the design rule of device fabrication advances into the deep submicron region, the device processing and performance are more sensitive to the starting material's characteristics. The requirements of the geometrical tolerance of the polished wafers as well as their bulk characteristics are becoming more stringent. The polished wafers are prepared through the complex sequence of shaping, polishing, and cleaning steps after a single crystal ingot is grown. Although the detailed shaping processes vary depending on the manufacturer. The processes described below are generic in nature. Newly introduced processing technologies will be discussed where appropriate. Figure 3.46 is a flow chart showing a generic wafer shaping process. The single crystal ingot is first evaluated for crystal perfection and resistivity, before it is surface ground to a cylindrical shape of a precise diameter. Flat(s) or a notch with preferred crystallographic orientations are ground on the ingot surface parallel to the crystal axis. The primary flat or notch, for example, is positioned perpendicular to a h110i direction on a (100) wafer and is used for alignment of the wafer in the device processing with automated handling equipment. The primary flat, or notch, also serves as an orientation reference for chip layout, since devices fabricated on wafers are crystallographically oriented. The existence of secondary flat on the wafer, shorter than the primary, is used to identify the wafer surface orientation and conductivity type [117].
The slicing operation produces silicon slices from the ground ingot. Slicing defines the critical mechanical aspects of a wafer, such as thickness, taper, warp, etc. The slicing is commonly carried out by an inner diameter (ID) circular saw (Figure 3.47a), after the ingot is rigidly mounted to maintain an accurate crystallographic orientation as previously determined by x-ray diffraction. The ID saw uses a thin stainless steel blade bonded with diamond particles on the inner edge of the blade. Recently, the development of multiple-wire saws has enabled the silicon slicing to result in high throughput and superior mechanical properties such as significantly reduced bow and wrap. Figure 3.48b shows a schematic of a multiple-wire saw. In this arrangement, parallel, equally spaced, and properly tensioned stainless steel wires spun across two pulleys are part of a single stainless steel wire winding through a complex set of pulleys. Cutting of multiple slices results when the ingot is pressed against the traveling wires under injection of slurry. Although the cutting rate is much slower than the ordinary ID saw (ordinary ID saw is 80–100 times higher
Wafer shaping process Crystal growth Ingot surface grinding, orientation flattening or notching Wafer slicing by ID or multiple wire saw Edge / notch rounding Lapping or grinding (both sides) Edge polishing Donor anneal (p− only) Double-side or single-side polish
Backseal poly Si, LTO, etc. Pace (option)
CMP (final polish) Epitaxy
Final cleaning and packaging
Flow chart describing generic steps involved in wafer preparation employing modern technologies.
rate), as many as 300 slices can be produced simultaneously. Besides higher throughput, the multiple-wire saw has other major advantages over the ID saw. Slicing by the multi-wire is actually the result of low speed grinding/lapping action by the slurry. Improved bow, warp, TTV, and taper are much easily obtained than with the ID saw. In addition, the slow lapping action by the moving wire results in small kerf loss, which affords more slices per inch of ingot. It is shown that the kerf size loss is very close to the diameter of the wire used. The multiple-wire saw offers material savings (reduces kerf loss by 30% compared to the ID saw), increased productivity, and improved wafer mechanical properties. It has been used for slicing 200and 300-mm-diameter wafers and is expected to be used for the future "diameter generations."
Chemical Etching
Chemical etching of the slices is done to remove mechanical damage induced during the previous shaping steps-ingot surface grinding and slicing. The etching can be carried out by either an acidic solution or a caustic etchant. The acidic system is mostly based on HNO3–HF system (or with modifiers such as acetic acid [118]). The surface material removal is the result of two-step reactions. The Si surface is first oxidized by HNO3 to form SiO2, followed by its removal by HF. The acid etch produces a smooth and shiny surface. However, since the reaction is exothermic, temperature control is critical in order to maintain uniform etching. Caustic etching uses a alkaline solution [119], such as KOH, with certain stabilizers. The KOH etch offers a uniform etching rate, but produces a rougher surface than the acid
Silicon ingot
Crystal ingot
Wire ID blade ID saw
Multiple wire saw
FIGURE 3.47 Schematics showing the traditional inner diameter (ID) saw and recently developed multiple-wire saw for silicon wafer slicing.
etch, since KOH etching rate is crystallographic orientation dependent. Chemical etching of the slice may be repeated after subsequent mechanical operations, such as edge rounding and lapping/surface grinding to remove mechanical damage.
Edge Rounding
The square edge of sliced silicon wafers is rounded by an edge grinder. The rounded-edge wafers greatly reduce mechanical defects, such as edge chips and cracks induced by wafer handling. Edge chips and cracks can serve as stress raisers, which facilitate the onset of wafer breakage or plastic deformation, and slip dislocations during thermal processing. In addition, the rounded edge eliminates the occurrence of epitaxial crown (thicker epitaxial layer at the wafer edge) in the epitaxial deposition process and pile-up of the photoresist at the wafer edge. The shape of the rounded edge usually follows an industrial standard (i.e., SEMI standard) in which the edge profile fits within the boundary of a standard template. However, variations from the "standard" exist. In some applications, the rounded edge is modified to be more "blunt" in order to facilitate the chemical–mechanical polishing (CMP) operation for inter-level dielectric planerization. In this case, the "blunt" edge supposedly prevents the wafer from slipping out of the template during polishing. Other applications require more "rounded" edge shapes for increased strength. Often, a compromise on the edge profile is required.
Lapping/Grinding
The lapping of the silicon slice surface takes place when the slice is ground between two counter rotating cast iron plates in the presence of an abrasive slurry, usually a mixture of micron-sized alumina or silicon carbide particles suspended in a solution. The purpose of lapping operation is to remove the nonuniform damage left by slicing, and to attain a high degree of parallelism and flatness, both global and local. In fact, post-lapping slices possess the best mechanical characteristics in the entire shaping process flow. The subsequent mirror-polishing operation generally degrades the flatness characteristics attained by the lapping operation. However, lapping with slurry also introduces fresh damage to the silicon surface, which requires subsequent chemical etching and chemical–mechanical polishing for removal. Chemical etching and CMP of the silicon surface degrades the wafer flatness. To circumvent this situation, surface grounder (with a precision grinder bonded with diamond particles) on both sides of the wafer is employed to achieve surface flatness with reduced surface damage. With the reduced surface damage, the need for chemical etching and CMP is also reduced and good mechanical properties may be retained.
Polishing is accomplished by a chemical–mechanical polishing process involving a polishing pad and a slurry. The polishing slurry is usually an alkaline colloidal solution containing micron-sized silica particles. While CMP is used to remove surface damage and to produce a mirror-finished surface, it also degrades the wafer flatness achieved by lapping/grounding. Therefore, it is essential to optimize operational parameters so as to minimize the polishing time and flatness degradation. Double-side polishing (CMP on both front and back surfaces simultaneously) has been found to result in superior flatness than the single side polishing arrangements. The combination of surface grinding (on both the sides of the wafer) and double-side CMP has shown to result in a superior total indicator reading (TIR), total thickness variation (TTV) and local flatness. Such an approach is becoming a standard manufacturing process for large diameter wafers (R300 mm) preparation. The wafer preparation via mechanical methods (i.e., grinding, CMP etc.,) has its limits in the degree of flatness that it can achieve. To supplement and to fine tune the local topography for further improvement in local flatness, tools such as plasma assisted chemical etching (PACE) [120] have been developed. Such a tool employs a spatially confined plasma with a scanning mechanism to allow material removal to be controlled as desired over the wafer surface. The PACE utilizes low energy neutral ions (i.e., /1 eV) rather than energetic ions, which are involved in reactive ion etching. Therefore, PACE produces minimum or no subsurface damage.
Wafer surface contamination can affect electronic device performance. The contaminants can be attached to the wafer surface physically or chemically. Cleaning of the wafers is necessary at many steps in device fabrication processes, as well as during the wafer shaping processes. The silicon wafer must be free of contamination before it is shipped to the device fabrication line. The cleaning process for the removal of surface contaminants during wafer shaping and polishing processes is discussed below. In general, the contaminants can be classified as molecular, ionic, or atomic. Typical molecular contaminants include waxes, resins, and oil used in polishing and sawing operations, and material from the plastic containers used for slice transport and storage. Molecular contaminants are absorbed on the wafer surface by weak electrostatic forces. They should be removed before subsequent cleaning involving chemical reactions. The ionic contaminants, such as NaC ClK, and FK are present after wafer treatments in HF-containing or caustic solutions. They are attached to the wafer surface by chemical absorption. The atomic contaminants of concern are due to the transition metal atoms, such as Fe, Ni, and Cu. The transition metals and ionic species can cause degradation in device performance. Chemical cleaning is an effective method to remove contaminants on the wafer surface. Many chemical cleaning processes have been developed. The process that is widely used in the semiconductor industry is the so-called "RCA Clean" [121], which consists of two consecutive cleaning solutions, including H2O–H2O2–HN4OH (Standard clean 1, SC1) and H2O–H2O2–HCl (Standard clean 2, SC2). The SC1 clean, with volume ratios typically 5:1:1 is to remove organic contaminants by both the solvating action of NH4OH and strong oxidizing action of H2O2. The NH4OH can also form soluble complexes with some metals such as gold, copper, nickel, and cobalt. The SC2 clean, with typical volume ratios of 6:1:1 removes transition and alkali metals from wafer surface, and prevents redeposition from the solution by forming soluble metal complexes (with ClK). The SC1 can also remove particles physically attached to wafer surface by etching effect of NH4OH which detaches the particles from the wafer surface. The K to the wafer repulsion effect of the opposite charges transferred from the electrolyte NHC 4 and OH surface and detached particle, respectively, prevent the particles from redepositing on the wafer surface. A modified RCA Clean [122], by adding a brief etch in diluted HF solution after SC1 was designed to eliminate the thin oxide layer grown on silicon surface due to the SC1 process. The thin oxide resulted from the SC1 was thought to hinder surface for cleaning by the SC2. Many modifications of the "RCA clean" exist (published and unpublished). Most of the modifications are on the volume ratios. For
example, in order to reduce silicon surface roughness, there is a trend to greatly reduce the volume fraction of the NH4OH in SC1 from the original formula. The effect of surface roughness of silicon on the gate oxide integrity has been reported as significant when the oxide thickness is thinner than 5 nm, although the literature is often not consistent, probably due to different process conditions. Other chemical cleaning solutions/processes, such as piranah (H2SO4–H2O2–H2O), ozonated water, etc., have also been shown to be effective. However, the "RCA clean" and its modified versions have been the most popular cleaning processes used by the semiconductor silicon manufacturers.
Epitaxial Growth Silicon Epitaxial Wafer
An epitaxial silicon wafer refers to a structure where an epitaxial layer is grown on a single crystal silicon substrate by chemical vapor deposition (CVD), normally at a high temperature. The CVD process usually involves the hydrogen reduction of high purity silicon tetrachloride (SiCl4), trichlorosilane (SiHCl3), or dichlorosilane (SiHCl2) to form solid silicon. An added source gas in the reaction, such as diborane (B2H2) or arsine (AsH3) provides dopant atoms for n- or p-type electrical carriers, respectively, in the epitaxial layer. The primary purpose of the epitaxial growth is to create a layer with a different, usually lighter, concentration of electrically active dopant than the substrate. Depending on the IC characteristics, the epi layer must meet a set of specifications for thickness, electrically active dopant concentration, sharpness of the epi-substrate interface, defect density, and contamination. The epitaxial layer was initially applied to bipolar devices. Typically, a lightly doped layer is grown over a substrate containing a pattern (often referred to as sub-collector) of opposite type impurity by diffusion or ion implantation. The structure allows a vertical transistor to be built with a minimum of collector resistance and readily permits junction isolation between devices (see Figure 3.48). The most common application of the epitaxial layer in CMOS device processing involves a lightly doped layer over a heavily doped substrate of the same conductivity type, i.e., either p/pC or n/nC structure. The p/pC is by far the dominant universal epitaxial structure. It has been used by CMOS-based logic, microprocessor, ASIC, and some DRAM manufacturers. Figure 3.49 is a schematic of a CMOS structure built on pKlayer of the p/pC wafer. It is realized today that p/pC wafer has many advantages over the bulk pK wafers. The initial motivation for using such a structure was to reduce the metal–oxide–silicon (MOS) device's leakage current. Since a lightly doped bulk substrate has a higher concentration of minority carriers, the carriers can diffuse hundreds of micrometers to space-charge layers and are collected as reverse-bias leakage currents. This minority-carrier diffusion current can dominate over leakage current generated within the space-charge layers, especially at higher operating temperatures (R408C) [123]. A technique that can circumvent this problem is to form a pK layer (w1015 atoms/cm3) as an epi layer grown on a heavily doped substrate (w1019 atoms/cm3) [124,125]. The pC substrate has few minority carriers (electrons), so the minority carriers are only generated from the thin epi layer. Thus, the diffusion current
Isolation diffusion P
Base contact
Emitter contact
n+ n+ buried
Collector contact
Substrate contact
n epi collector
P substrate
The role of epi layer in a bipolar device.
Input Vdd
p epi
n well
p+ substrate
The role of epi layer in a complementary MOS device.
from the substrate is suppressed, even though the minority-carrier diffusion lengths (in the epitaxial layer) are long; the minority-carrier diffusion length is small in the pC substrate. This is especially important in preserving holding times in dynamic nodes (e.g., DRAM) [123]. Since its initial application in CMOS, many added beneficial functions have been found to be associated with the p/pC structure. The major ones include its effects in minimizing soft errors, preventing latch-up of the device, and providing sites gettering of harmful impurities. From the device design view point, using p/pC structure for CMOS fabrications is the best solution for avoiding latch-up without resorting to circuit design modifications, such as adding "guard rings," etc. The latch-up is due to the turn-on of a parasitic 4-terminal, n–p–n–p lateral transistor between neighboring NMOS and PMOS transistors, as shown in Figure 3.49. However, if the formation of a vertical parasitic p–n–p is favorable with the presence of pC substrate, the turn-on of the lateral 4-terminal device may be suppressed. In a first approximation, in order to suppress the lateral p–n–p–n device, the effective epi thickness (taking into account the boron up-diffusion after device processing) must be smaller than the separation of two neighboring n–p transistors. Latch-up simulators are available to provide information for designing latch-up-free design layout, from which an appropriate epi thickness may be estimated. pC Substrates in p/pC wafers have been found to serve as an excellent intrinsic gettering sites. Two effects have been observed. The first is the gettering effect due to pC silicon's high efficiency in generating oxygen precipitates–dislocation complexes. The oxygen precipitation in pC, with resistivity around 10 m ohm–cm, has fast kinetics and can result in a precipitate density, which is more than an order of magnitude higher than in pK (10 ohm–cm) under a Lo–Hi annealing condition [41]. Much of the oxygen precipitation behavior is discussed in Section 3.7. The second gettering effect by the pC silicon is due to the "segregation" effect, which drives metallic impurities to the pC region from the pK epi layer under a "segregation" annealing [126]. The pC, like other highly doped (degenerately doped) silicon regions, such as diffused phosphorus layers, source/drain regions in the CMOS structure, have long been observed to getter metal impurities and perceived as due to an enhanced solubility effect. The segregation effect of the impurities (such as Fe) was proposed to be due to the difference in the Fermi levels of pC and pK silicon [127]. One of the unique features associated with the p/pC structure is the possible existence of misfit dislocations at the epi-substrate interface (see Figure 3.50). These dislocations can act as gettering sites as well. It is well known that doping with boron causes the silicon crystal lattice to contract (w0.014 A/ atom% boron added) [128]. The vast difference in the boron doping levels in p/pC(w1019 atoms/cm3 in the substrate while the epi layer is doped with 1015 atoms/cm3) results in a lattice mismatch between the epitaxial layer and the substrate during CVD deposition [129]. Under this condition, the epitaxial growth is accompanied by lattice stress, tensile on the epi layer side, and compressive on the substrate side. The misfit stress increases as the layer continues to grow, until the local stress exceeds the elastic limit at the deposition temperature, at which time the stress is partially relaxed by forming misfit dislocations at the epi-substrate interface. The onset of misfit dislocation formation during epi deposition is a
FIGURE 3.50 Cross-sectional view of an etched p/pC epi wafer, showing etched misfit dislocation pits at the episubstrate interface.
function of the degree of lattice mismatch, deposition temperature, and deposition thickness. The unrelaxed misfit stress will contribute to both the wafer bow and the wrap. It should be reminded that the misfit dislocations formed on the (100) p/pC epi structure are contained in the (100) interface, with a Burger's vector of the form bZa/2h110i [130]. Since the (100) plane is not a glide plane in the silicon lattice, the dislocation is immobile; it is "locked" [131] in the interface. Furthermore, the dissociation of such a dislocation into two mobile dislocations in two inclined {111} slip planes is energetically unfavorable. However, it is possible to move misfit dislocations in silicon by a "climb" mechanism under high stress conditions. Experimental evidences [129] show that the movement is towards the substrate side, i.e., the side with the smaller lattice constant. The misfit dislocations so formed are stable and could contribute to the gettering effect. They present no harmful effect to the epi layer structure. Perhaps the most fundamental difference between the polished bulk wafer and pK layer of the p/pC wafer is that CVD silicon is superior in quality. The epi layer is free of oxygen and carbon incorporation. The incorporation of dopant is uniform and free of local fluctuations (such as striations in CZ materials discussed in Section 3.3.2.4.2). In general, CVD epitaxial silicon has been recognized as superior materials for GOI in device processing than bulk CZ silicon (see Figure 3.51). More significantly, in deep sub micron design-rule technologies, CVD silicon epitaxial material is of vital importance and beneficial to gate oxide integrity. Chemical vapor deposition epitaxial silicon layer is also free of grown-in microdefects stemming from the agglomerations of point defects encountered in the melt grown silicon (CZ). Grown-in "D" defect (such as COPs, LSTs, and FDPs) density in CZ silicon has been correlated with the oxide defect density. The issue of grown-in defects is discussed in Section 3.3.3. However, the defects due to agglomeration of point defects in CZ growth tend not to extend into the epitaxial layer during CVD deposition. It has been demonstrated that as thin as 0.3 mm epitaxial layer, grown on a CZ substrate containing COPs can mask the harmful effect of COPs [114]. In consideration of the impact of grown-in microdefects on device yield and reliability, many device manufacturers will be prompted to switch from bulk CZ wafers to p/pC or even pK/pK epitaxial wafers.
Heteroepitaxy
Heteroepitaxial growth refers to epi deposition, where the deposited layer and substrate's lattice constants are slightly different due to difference in chemical composition, although they may be of the same crystal
1.6 Defect density, D0 (cm−2)
p − / p + epi p − bulk Pre-heat treated p − bulk
5.5 v Voltage
0.2 10 v
FIGURE 3.51 Defect density (D0) extracted from voltage measurements on thin oxide grown on three different silicon surfaces. (From Boyko, K. C., Feiller R. L., and Lin, W. Unpublished.)
system. Heteroepitaxy has been employed in the fabrication of new emerging Si materials and advanced device processing. For example, strained silicon growth, SiGe alloy deposition for recessed S/D, SiGe for a heterojunction bipolar transistor (HBT) via selective epitaxy, are among the recent applications. In heteroepitaxy, due to a difference in crystal lattice constant across the interface, there exist a strain in the grown epitaxial layer in order to accommodate the lattice mismatch. The layer is pseudomorphic when the layer thickness is thinner than a certain critical thickness [132], above which the stress in the film is partially relaxed by the formation of dislocations. Figure 3.52 shows a lattice model for strained pseudomorphic epi layers in two different heteroepitaxy arrangements. In both cases, the epi thickness is thinner than its critical thickness. In Figure 3.52a situation, the epi layer is in a state of biaxial compressive strain, and in Figure 3.52b, a state of biaxial tensile strain. When the pseudomorphic layer continues to grow in thickness and reaches a certain critical thickness [132], the epi layer partially plastically relaxes and releases the lattice strain by generation of misfit dislocations at the growing interface. This is shown in Figure 3.53. The completely relaxed heteoroepitaxial layer is in equilibrium state. As will be discussed in the following sections, both pseudomorphic and relaxed epi layers have their applications.
Selective Epitaxial Growth
Compared to blanket silicon epitaxy discussed above, selective epitaxy growth (SEG) has not been widely used. Silicon bipolar transistors have used, selective epi other than SiGe for improved performance. A 1988 IBM paper [133] reports on a selective epitaxy base transistor, which forms the base with borondoped selective epi rather than boron implantation. The development of the SiGe HBT made use of the SEG in bipolar and BICMOS fabrication in the 1990s. The SEG has also been used to make the source and drain (S/D) elevation for CMOS transistors to solve the problem on silicon real estate limitation. The process becomes indispensable with SOI processing. More recently, SEG has been employed for growing recessed S/D with SiGe to induce uniaxial compression strain in the PMOS channel. The SEG of silicon has been studied from the early days of silicon technology [134–136]. In SEG of silicon, epitaxial deposition only takes place on "windows" of bare silicon, single crystal substrate of a patterned wafer. Nucleation is suppressed elsewhere in regions that is covered by silicon dioxide (or silicon nitride). The major difference in SEG process from that of conventional epitaxial growth is the addition of extra HCl to the SiH2–H2 or SiH2Cl2–H2 chemistries, although the by-product of the
Strained epi layer A Tensile Interface
Substrate B (a)
Strained epi layer C Compressive Interface Substrate D
FIGURE 3.52 Lattice model of strained pseudomorphic layers grown with (a) Lattice A!Lattice B, and (b) Lattice COLattice D. Layer A is in biaxial tensile strain and layer C is in biaxial compressive strain. Layer A and Layer C are thinner than their respective "critical thickness."
chlorine-containing source gas also provides the selectivity. Figure 3.54 illustrates the SEG on a patterned wafer. A SEG process at a reduced pressure and a high temperature along with a careful pre-deposition clean (such as high temperature H2 bake) can result in a grown silicon layer with minimum crystalline defects. When doing SEG on (100) substrates, {311} facet growths are found to be common at the edges of the pattern [136]. When the edges of the pattern are aligned in the h100i directions, {311} facets will be situated in the corners, and their size and effect are minimized. 3.6.3.1
SEG Growth of SiGe for HBT
The epitaxial growth of SiGe is the heart of the heterojunction NPN transistor technology. The modern SiGe HBT was developed in the 1990s. A SiGe HBT is similar to a conventional Si bipolar NPN transistor
Relaxed epi layer
Interface Substrate
FIGURE 3.53 Lattice model of heteroepitaxy after strain relaxation accompanied by generation of misfit dislocations. The relaxed epi layer is thicker than the critical thickness.
SiO2 P+
n–well P+
FIGURE 3.54 Schematic illustration of a typical selective epitaxy growth (SEG) process for device isolation: (a) oxide deposition; (b) window formation; (c) epi growth (d) n-well drive-in. (From Borland, J. O. and Drowley, C. I., Solid State Technol., 28, August, 1985, 141. Reproduced with permission from Solid State Technology.)
except for the base. SiGe, a material with narrower bandgap than Si, is used as the base material. The Ge composition is typically graded across the base, with the Ge decreasing from the collector side to the emitter side (peak concentration ranging from 10 to 25 atom% Ge, depending on the application). This creates an accelerating electric field (sloped conduction band) for minority carriers moving across the base, as schematically shown in Figure 3.55. A direct result of the Ge grading in the base is higher speed, and thus higher operating frequency, fTw100 GHz. Typically, thin SiGe a few tens of nanometer thick is deposited selectively on the substrate (collector) at a moderate temperature (6508C–7508C) and a reduced pressure of a few torr using SiH2Cl2, GeH4, B2H2, and HCl. The boron doping level of the layer is
Ge/B content
12% Ge 1019 B
Energy (eV)
HBT 30 <E 0.12 mm (1E6/cm3)
Annealed 10
0.01 N-conc: 5E13
N-conc: 5E14
FIGURE 3.69 Comparison of void density on low and medium nitrogen doped 300 mm silicon before and after anneal (12008C/1 h). (From Muller, T. et al., Semiconductor Silicon 2002, eds. Huff, H. R., Fabry, L., and Kishino, S., Electrochemical Society, Pennington, NJ, 2002, 194. Reproduced with permission from Electrochemical Society.)
There are two major issues in growing and preparing high resistivity CZ silicon. First, in the CZ silicon growth, high resistivity corresponds to a low intended doping level. The contaminants (such as Group III and V elements) dissolved from the silica crucible will have greater impact on the doping accuracy and the high-resistivity limit. Boron contamination is a concern, which is an impurity in the quartz sand, used for fused silica crucible fabrication. Complete removal of boron impurity from fused silica is not an easy task. One can avoid the contaminants from the natural quartz sand by using synthetic SiO2 for fabrication of the silica crucible and to achieve higher resistivity. But significantly higher costs will prevent using this approach for high-volume production. However, with the use of high purity silica crucible, or crucible coated with high purity material, CZ silicon with 1000 ohm–cm or higher may be obtained. The second issue is that the high resistivity CZ silicon is susceptible to more interference from the "low temperature oxygen donor" formed at 3008C–5008C (highest formation rate is at 4508C), arising from the formation of oxygen–silicon complexes, SiOx. Oxygen donors are formed in as-grown crystals during crystal cool down following crystal growth. They can be annihilated by annealing the wafers at 6508C– 7008C, followed by quenching in an inert ambient. The "true" resistivity of the grown silicon can then be measured. However, donors can be formed again during the wafer processing when experiencing temperatures in the neighborhood of 4508C and the remaining [Oi] is significant. In CMOS processing, considerable "back end" processing occurs near 4508C, and can provide an environment for thermal donor regeneration. Thermal donor formation causes resistivity change and dopant compensation in the substrate (even conductivity type can change). In some cases, degradation of device parametric performance has been attributed to donor formation. Since thermal donor concentration is a power function (power O1) of interstitial oxygen concentration [189], maintaining low value of [Oi] is essential during the "back end" processing. Two general approaches may be used: (1) to incorporate a Hi–Lo–Hi-type thermal cycle before or at the beginning of an IC processing sequence, in order to form a DZ near the wafer surface (oxygen is depleted in the active region) and a highly precipitated bulk (oxygen is consumed in precipitates). Care must be taken not to over precipitate oxygen which causes softening of the wafer strength [174]; (2) to grow high-resistivity silicon using MCZ method for low [Oi] such that only a few thermal donors may be formed during IC processing [190]. An MCZ wafer with low [Oi] can still provides a mechanical strengthening effect; however, low or no oxygen precipitation is to be expected for the benefit of internal gettering. See configuration in Figure 3.66(d).
Modern Ultra Large Scale Integration ICs, fabricated with design rules approaching 45 nm, depends on the availability of highly perfect silicon single crystals, which are prepared exclusively by the CZ crystal growth method. The silicon material prepared today, polished wafer or epitaxial wafer, must meet the challenges imposed by the stringent requirements of the starting materials for current and future design rule generations, as guided by the Starting Materials Road Map of the ITRS. In parallel with the design rule decrease, both chip size and circuit complexity increase. There is a continued push for an increased wafer diameter in order to reduce IC manufacturing cost. In the up-scaling of the wafer diameter, in the 300–450 mm range, the most significant technical challenges are in the crystal growth. The major issues include crystal weight support, reduced growth rate, and growing long crystals from "ultra-large" charge capacity and/continuous growth. The dislocation-free as-grown yield will dominate the cost of manufacturing 300–450 mm-diameter wafers. Furthermore, the grown-in microdefects, have vital impacts on the GOI and proper function of memory devices. With in-depth understanding of the relationship between intrinsic point defect concentration and crystal growing parameters, the microdefect-free crystal growth processes (i.e., for crystals free of D and A defects) have been developed. To circumvent the microdefect problem in polished wafers, pK/pC epi and hydrogen/argon-annealed wafers continue to be widely used for IC fabrication. MCZ is the growth method for large-capacity, large diameter silicon crystals growth for reducing thermal convection and better control
of oxygen. Consequently, the interstitial oxygen contents of the large diameter silicon (R300 mm) are generally lower than the smaller diameter silicon grown with normal CZ. Lower oxygen content makes it difficult, if not impossible, to exercise internal gettering by oxygen precipitation under the low thermal budget of deep sub micron design rule device processing. Heteroepitaxy technology has played an important role in the manufacturing of emerging strained silicon as starting materials and in fabricating device modules via selective epitaxy during IC processing, such as HBT base, RSD, recessed S/D, and FinFET. These epitaxial depositions cause either enhancement in device performance or solve Si real estate limitations. As the design rule reduces the requirements for wafer mechanical dimension control, particulate, as well as metal contamination, become more stringent. To achieve improved flatness for sub-100 nm IC fabrication, new techniques in wafer shaping and polishing have been implemented, these include surface grinding in conjunction with reduced chemical etching, double-side polishing, and plasma assisted chemical etching. Finally, for improved wafer contamination control, purer starting raw materials, process chemicals, proper equipment maintenance, and wafer handling are essential. Semiconductor silicon materials have been the backbone for IC fabrication since its infancy. As IC technology evolved through several generations, the silicon materials have also gone through many changes in order to meet the challenges of design rule reduction and demands for improvement in device performance. Today's silicon materials are results of decades' continued effort in research and development. While this review covers science and engineering of silicon materials preparation and its behavior upon processing, the history of silicon materials research and development for the last 50 years, and current applications of silicon materials in the IC are subjects of recent review papers by Huff [200] and Tsuya [201], respectively.
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SOI Materials and Devices 4.1 4.2
Introduction.......................................................................... 4-2 SOI Basics: A Tutorial .......................................................... 4-3
SOI Wafer Fabrication Methods-Some Details.................. 4-6
Sorin Cristoloveanu Institute of Microelectronics, Electromagnetism and Photonics
George K. Celler Soitec USA
What It Is: A Definition † How It Is Made: A Very Brief Description † How SOI Devices Work Wafer Bonding † Smart Cute Technology † Bond and Etchback † ELTRAN † SIMOX † Other Fabrication Methods
Advanced Wafer Engineering............................................. 4-18
Crystal Orientations † Strained Silicon-on-Insulator Ge-on-Insulator and Other on-Insulator Substrates
Physical Characterization of SOI Wafers.......................... 4-24
Si and BOX Thickness Measurements † Surface Roughness † Structural Defects † Stress (Strain) Measurements by Raman Spectroscopy † Inspection for Particles and Other Defects
Electrical Characterization ................................................. 4-26
Wafer Characterization: J-MOSFET Characterization
Partially-Depleted SOI MOSFETs ..................................... 4-28 Kink Effect † Hysteresis and Latch † Parasitic Bipolar Transistor (PBT) † Transient and History Effects
Fully Depleted SOI MOSFETs ........................................... 4-29
Threshold Voltage † Subthreshold Slope † Transconductance † Meta-Stable Dip † Volume Inversion † Transition from Partial to Full Depletion
Scaling Trends ..................................................................... 4-33 Short Channels Mobility Issues
† †
Narrow Channels † Channel Thickness † Ultra-Thin Gate Dielectrics † Novel BOX
Multiple-Gate SOI MOSFETs ............................................ 4-40
Double-Gate MOSFETs † Triple-Gate MOSFETs Gate-All-Around MOSFETs † Four-Gate FET
4.11 MEMS and Photonic Applications of SOI....................... 4.12 Conclusions......................................................................... Acknowledgments ............................................................................ References .........................................................................................
4-45 4-45 4-46 4-46
DK4126—Chapter4—23/5/2007—18:46—CRCPAG—240433—XML MODEL CRC12a – pp. 1–52.
Silicon-on-insulator (SOI) technology was initiated almost half a century ago for the fabrication of radiation-hard circuits. During 1970s and 1980s several SOI materials and structures were conceived for dielectrically separating the thin, active device volume from the silicon substrate [1,2]. The background idea is that in a bulk silicon MOS transistor, only a superficial layer approximately 100-nm thick is actually useful for electron transport, whereas the substrate causes undesirable effects. An example of a transistor made in SOI is shown in Figure 4.1 [3]. The overwhelming success of bulk-Si CMOS confined SOI technology to niche applications until late 1990s. Then several factors have increased the interest in SOI: invention of new fabrication methods for SOI materials (Unibond, ELTRAN, ITOX–SIMOX) and their optimization, need for lower power and higher speed circuits, emerging limitations of bulk CMOS scaling. Silicon-on-insulator transistors are now unchallenged in extending the frontiers of ultimate CMOS scaling. This chapter is designed to offer a comprehensive tutorial on state-of-the-art SOI technologies. Section 4.2 introduces the basic concepts. Section 4.3 describes, in some detail, methods of fabricating conventional SOI substrates, while Section 4.4 includes novel modifications of SOI that further improve device performance. In Section 4.5 and Section 4.6, physical and electrical characterizations of SOI wafers are described. The physical mechanisms involved in the operation of fully depleted (FD) and partially depleted (PD) SOI MOSFETs are discussed in Section 4.7 and Section 4.8, respectively. Section 4.9 and Section 4.10 are dedicated to more advanced concepts related to the MOSFET miniaturization. We show that SOI is the necessary technology for CMOS scaling [3,4]. The SOI MOSFET is the smallest device conceivable in the CMOS world. We focus on the unusual dimensional effects that may take place in a small volume. The short-channel, narrow-channel and thin-body effects are addressed by including the impact of the gate and buried insulators. We finally show that 3D coupling effects govern the operation and optimization of advanced multiple-gate MOSFETs. As soon as SOI wafers entered the "toolbox" of device engineers, many applications other than high performance fully scaled CMOS also emerged, such as BiCMOS for power and high voltage devices [5] and circuits for high temperature environments [6,7]. Also more options became available for circuits that are resistant to ionizing radiation [7,8]. Section 4.11 covers the use of SOI wafers in the area of micro-electro-mechanical systems (MEMS) and for the emerging microphotonic chips. Micro-electro-mechanical system applications of SOI take advantage of mechanical properties of the monocrystalline films, which are superior to those of polycrystalline Si [9]. Currently there is also much interest in utilizing SOI in various photonic applications. These usually rely on high refractive index contrast between Si and SiO2, which permits photon confinement in small waveguides etched out of the top monocrystalline Si film [10]. For a reader that is interested in further details on SOI material fabrication and device physics, complementary useful information can be found in our previous review article [3].
G S Box
Si Substrate
Cross-section of a thin-film SOI MOS transistor.
SOI Materials and Devices
SOI Basics: A Tutorial
What It Is: A Definition
The most general definition of SOI involves a structure that consists of a layer of monocrystalline Si on an insulating dielectric film that is placed on a support "handle" substrate [1–3]. A predominant implementation of SOI, and some would argue the real definition is a monocrystalline Si film on amorphous SiO2 on a single crystalline Si substrate. The fact that the top Si layer must be monocrystalline, but separated by an amorphous insulating film from the single crystalline handle substrate, poses a significant technical difficulty. Epitaxial deposition methods require a crystalline template; therefore it is not possible to grow a suitable device layer directly on SiO2. In terms of production volumes, 200 and 300 mm Si wafers predominate, with a layer of about 150 nm of thermally grown SiO2 separating the single crystalline handle wafer from a single crystalline Si film that is 100 nm or less in thickness. Such wafers are primarily used for advanced CMOS applications. Somewhat thicker Si and SiO2 films are needed for power and high voltage devices, for photonic applications and for some MEMS structures. These non-CMOS devices are often fabricated in older facilities that currently employ smaller wafer diameters (4, 5, and 6-in.). In addition to the applications mentioned above, that rely on what is known as "thin SOI," where thin is anything with the Si film lesser than 3–5 mm in thickness, there are some niche applications, primarily in the MEMS field, that utilize Si layers from 5 to 100 mm thick. Currently (year 2007), 80%–90% of the SOI substrates for the advanced electronic applications produced worldwide are made by Smart Cute technology that utilizes wafer bonding and layer transfer from a "donor" or "seed" wafer to a support handle wafer. The remaining 10%–20% of wafers are made by either in situ buried oxide (BOX) synthesis from implanted oxygen ions (SIMOX process) or by wafer bonding followed by mechanical grinding and etching (BESOI). Sometimes, in a process known as ELTRAN, an electrochemically formed porous Si layer is used to facilitate layer transfer after bonding of two wafers. In the main body of this chapter we focus our attention primarily on commercially relevant fabrication methods, but we also list numerous other approaches that were tried in the past.
How It Is Made: A Very Brief Description
Here we summarize the most common ways of making SOI wafers (see also Table 4.1). More details and the physical mechanisms are provided later in the chapter. 4.2.2.1
Smart Cute technology relies on transfer of a high quality layer from one wafer to another. In typical applications, a thin layer of Si that is coated with thermal oxide is moved from its original donor or seed wafer to another Si wafer that is coated with only native oxide. The process sequence starts with oxidizing the donor wafer, followed by implanting ions, typically hydrogen, through the oxide and into silicon. Then the donor wafers and the handle wafers are very carefully cleaned to remove any particles and to provide surface chemistry that is most favorable to wafer bonding. Wafer pairs are properly positioned with respect to each other, lightly pressed together and the fusion wave spreads and makes the wafers stick together. In the following step, wafer pairs are split along the hydrogen-weakened zone that was previously produced within the donor wafers. Typically thermal energy provides a sufficient impetus for the split to occur, but mechanical force is used in some cases instead of heating. After the split, some finishing procedures are used to make the surface of the newly made SOI wafers smooth, and an annealing step strengthens the bonded interface. The donor substrates, which were split off the SOI wafers and are now thinner by a micron or less, are repolished in preparation for making another batch of SOI wafers.
Bond and Etchback
Bond and etchback SOI (BESOI) consists of bonding together of two oxidized and properly cleaned silicon surfaces, followed by a combination of mechanical grinding and chemical etching of a very significant fraction of one of the wafers in the two-wafer sandwich. By its very nature, this process is useful when the final Si film should be R5 mm, and is not practical for thin films. 4.2.2.3
ELTRAN
ELTRAN, which stands for epitaxial layer transfer, is another process that is based on wafer bonding. It utilizes a layer of porous Si formed by well-known electrochemical processes as the weak zone that facilitates the transfer of a Si film from the donor wafer to a new handle wafer. In order for this process to work, the top surface of the porous region has to be sealed by thermal annealing in hydrogen to provide a template for epitaxial Si growth. After the epitaxy and oxide formation, wafer pairs are bonded, and then a fine water jet is used to cut through the weak porous layer. Surface finishing steps complete the process. 4.2.2.4
SIMOX
SIMOX is an acronym for separation by implantation of oxygen. This method relies on synthesis of BOX inside silicon by means of implanting a sufficient density of oxygen ions under a superficial layer of crystalline Si. The main challenge is placing enough oxygen under the surface of Si, while preserving the single crystalline nature of the superficial silicon. Temperatures of the order of 5008C–6008C during implantation prevent amorphization of the superficial layer of silicon. Much higher annealing temperature, greater than 13008C, subsequent to implantation causes segregation of the implanted oxygen into a continuous buried layer of SiO2.
How SOI Devices Work
An SOI circuit is composed of single-device silicon islands, dielectrically isolated from each other and from the underlying substrate. The lateral isolation offers compact design and simplified technology, whereas the vertical isolation via the buried insulator (BOX) allows achieving thin films (Figure 4.1), and eliminates most of the detrimental substrate effects (latch-up, punch-through, etc.). Since the source and drain regions extend down to the BOX, the junction surface, leakage current, and junction capacitance are naturally reduced. The implications are improved speed, lower power dissipation, and higher temperature of operation [1,2]. In a typical MOS–SOI transistor (Figure 4.1), the current flows between source and drain. It is controlled primarily by the gate and secondarily by the substrate bias that acts as a back gate. Two inversion channels, front and back, can be formed, the main at the front Si–SiO2 interface, and the other at the Si–BOX interface. They are independent in PD MOSFETs (Figure 4.2a) and coupled in FD MOSFETs (Figure 4.2b). The very thin drain and source regions make SOI devices to be less affected by short-channel effects, originated from "charge sharing" and from drain-induced barrier lowering (DIBL) [3,4]. Silicon-on-insulator MOSFETs are also rather tolerant to transient radiation effects. Silicon-on-insulator circuits present a definite advantage in the highly competitive domain of high performance microprocessors. They also offer very beneficial characteristics for low-power and low-voltage circuits, where a small gate voltage shift is needed to switch the transistors from off- to on-state. Fully depleted MOSFETs benefit from a quasi-ideal subthreshold slope (60 mV/decade at room temperature). Operation at equal voltage consistently shows about 20%–30% increase in performance for SOI as compared to bulk silicon circuits. Conversely, operation at equal low-power dissipation may yield more than 100% performance gain. It is recognized that SOI circuits perform like bulk-Si circuits from the next technology generation. Even more importantly, ultra-thin film SOI MOSFETs have the unique capability of length scaling beyond the frontiers of bulk CMOS, thus enabling the Moore's law to extend further. In the past, SOI circuits were handicapped by the cost of SOI wafers and by the unavailability of dedicated libraries for design. Silicon-on-insulator technology was then utilized only for circuits with
VG Gate N+ S
Gate N+ P
D Box
Front channel
Depleted film
Floating body (a)
Back channel (b)
Basic architecture of (a) partially depleted (PD), and (b) fully depleted (FD) CMOS transistors on SOI.
high added value. But, in the late 1990s, the range of SOI applications has broadened considerably. Also, SOI has been recognized in the International Technology Roadmap of Semiconductors (ITRS) as the best option for many families of CMOS circuits. Currently, high-end microprocessors are being fabricated on SOI (IBM, AMD, Freescale, Sony, etc.). RF SOI devices also show unchallenged capability. Extremely low-power circuits for mobile communication, portable processors operated with one-battery supply (0.5–1.2 V), and even battery-free systems (for watches) are currently fabricated with SOI technology. The SOI versatility has been taken advantage of, for conceiving capacitor-less DRAMs. Globally, SOI is an ideal substrate for systems-on-chip (SOC). The FD CMOS/SOI circuits can still operate successfully at temperatures beyond 3008C (for aeronautics and automobiles): the leakage currents are much smaller and the threshold voltage is less temperaturesensitive than in bulk Si [11]. Silicon-on-insulator circuits for the space industry can also be radiationhard. High voltage SOI devices take advantage of the dielectric isolation. Power transistors can have lateral configuration (for example, LD-MOSFETs for lighting applications) or vertical configuration. A vertical power device (IGBT, LDMOS, VMOS, etc.) can be integrated in a thick SOI film or in the non-SOI section of mixed SOI-bulk wafers. They can be rendered "smart" by being located next to a low-power SOI CMOS circuit [12]. Innovative device architectures and functions are based on the unique SOI features such as the adjustment of the thickness of the Si overlay and BOX, and the implementation of additional layers underneath the BOX. The 3D circuits containing consecutive thin silicon and BOX layers have been demonstrated with epitaxial lateral overgrowth (ELO) and zone melt recrystallization (ZMR) methods (See Table 4.1 for definitions of ELO and ZMR). For example, a 3D image-signal processor contains: arithmetic units and memories in bulk Si bottom level, fast A/D converters in an intermediate SOI layer, and photodiode arrays in an upper SOI layer [13]. The SOI family also includes optical devices: switches, waveguides, and modulators. Silicon-on-insulator is an ideal material for microsensors and MEMS, where thin membranes are required; the interface between the BOX and substrate is a perfect etch-stop plane. Many transducers for detection of pressure, acceleration (airbags), gas flow, temperature, radiation, magnetic field, etc., have successfully been integrated on SOI [1,14]. Most of the Si nanoelectronic devices (SET, tunneling transistors, quantum dots and wires) have used SOI, either for process simplicity or for ultra-thin film capability [15,16]. Since quantum and tunneling effects become usual in standard SOI MOSFETs, the idea is to take advantage of them by importing device concepts from III–V semiconductors into the Si family. Resonant tunneling transistors can be accommodated in ultra-thin SOI films. In addition, band-to-band tunneling diodes (NC–PC) exhibit current–voltage characteristics with negative resistance (N-shape characteristics). Silicon-on-insulator
Different Methods of SOI Formation Method
DI—dielectric isolation [78] SOS—Si-on-sapphire [79] SOZ—Si-on-zirconia [80] Recrystallization from the melt: (a) Laser-seeded [81] (b) Laser-unseeded [82] (c) ZMR—zone melt recrystallization with a hot wire [83] (d) LEGO—lateral epitaxial growth over oxide— stationary lamp heater [84] ELO—epitaxial lateral overgrowth [85] SPE—solid phase epitaxy [86] FIPOS—full isolation with porous oxidized silicon [87] Heteroepitaxy of crystalline insulators, followed by single crystalline Si [88] SIMOX—Separation by IMplantation of OXygen [61] Wafer bonding and etch-back [25] Smart-Cute process-layer transfer facilitated by ion implantation [39] ELTRAN process-layer transfer facilitated by porous silicon [58] SON—silicon-on-nothing [89]
Description Oxide-isolated "tubs" of monocrystalline Si supported by a polycrystalline "handle" wafer. Si film epitaxially grown on sapphire substrates. Si film epitaxially grown on ZrO2 substrates. Rapid melting of polysilicon films deposited over SiO2 layer grown on a Si wafer, followed by controlled crystallization in a strong temperature gradient: Cw laser beam raster-scanned across the surface, with via holes that connect the polysilicon film with the single crystalline substrate. As above, but no seeding vias in the oxide. A long and narrow molten zone is swept once across the entire wafer. A thick Si film is melted simultaneously across the entire wafer. Gradients due to seeding vias control crystallization. Selective Si epitaxial deposition, starting from via holes in SiO2 and spreading laterally over the oxide. Oxidized Si wafers with via holes through the SiO2 are coated with amorphous Si, which is epitaxially crystallized. Porous Si is formed locally under islands of crystalline Si, then it is oxidized to form isolation. CaF, ZrO2, spinel, Al2O3 and other crystalline insulators have been used. BOX layer is synthesized in situ from implanted oxygen. Two wafers are bonded with an oxide layer in between. One of the wafers is thinned by grinding and etching. One wafer is implanted, typically with H or noble gas ions. The Si layer above the implanted region is transferred to a handle wafer by wafer bonding and splitting along the implanted region. Epitaxial layer is grown on a porous Si region and transferred by bonding and splitting to a handle wafer. Successive epitaxy of SiGe and Si films on a Si substrate is followed by removal of the sacrificial SiGe, which leaves lithography-defined small cavities. The cavity walls can be coated with SiO2.
has the merits of reducing the parasitic leakage current and using the back-gate biasing, which modifies the local carrier concentration. The fabrication of tiny Si islands for Single-Electron Transistors is easier in very thin SOI. For example, a SET inverter is composed of nanometer-scale islands formed by anisotropic sacrificial oxidation combined with local stress effects (lower oxidation rate on the sidewalls). Two such SET islands, properly interconnected and biased, give rise to an inverter with gain higher than unity [16].
SOI Wafer Fabrication Methods—Some Details
Two fundamentally different approaches to SOI wafer fabrication are in commercial use. The predominant one is based on bonding of two wafers together. Afterwards one of the substrates in the bonded wafer pair must be transformed into a thin film of uniform thickness, low stress, and excellent crystallinity. The thinner the required film, the more difficult is this task. Another basic approach to SOI fabrication, known as SIMOX, involves direct synthesis of SiO2 inside a Si wafer.
First we describe the science and technology of bonding of two wafers together, as this is generic to all wafer-bonding-based approaches. The different paths from a bonded wafer pair to a finished SOI wafer are explained next. Then the details of the SIMOX method, which does not include bonding, are given. And for completeness and historical background, at the end of this section we list a variety of other methods that are scientifically interesting, but that have not led to any significant commercial activity, and also two methods that predate what we now define as SOI and that have lost much of their commercial importance.
Wafer Bonding
Just like two glass plates can stick together, properly cleaned Si wafers can be bonded simply by pressing them together at one point. Clean and hydrophilic-oxidized Si surfaces stick together because of attractive forces between water molecules trapped at the interfaces. This initial bonding is relatively weak, of the order of 0.1 J/m2. A subsequent heat treatment causes outdiffusion of water molecules from the bonding interface region, their dissociation followed by reaction with Si at the Si/SiO2 interfaces that leads to a slight increase in the SiO2 thickness. Several excellent reviews on the science and technology of wafer bonding have been published [17–20]. A chapter by Haisma in Ref. [20] details the rich history of patents related to bonding of wafers and of other structures [21]. It includes other types of bonding, such as anodic bonding that has many important applications, but is unsuitable for making silicon-based electronic devices. Here we only consider direct wafer bonding that is also known as fusion bonding. The nature of bonding forces depends on the materials being placed in contact and on the surface preparation (surface chemistry). Van der Waals forces will hold together two very flat and very clean surfaces, for example, in ultra-high vacuum environment. These forces depend on polarizability of atoms or molecules on two surfaces placed very close (!1 nm) to each other. Spierings et al. [22], have estimated the surface bond energy of 0.0075 J/m2 for two fused silica surfaces held together by Van der Waals interactions. Direct bonding of two clean silicon surfaces, which is gaining some technological importance, would likely rely on Van der Waals forces. Formation of SOI wafers by wafer bonding relies on another mechanism, that of chemical assistance through hydrogen bonds and water molecules. After wafer cleaning in an RCA solution [23] followed by a water rinse, the surfaces are coated with OH groups, which attract water molecules—i.e., the surfaces are hydrophilic. Hydrogen bridges and water molecules initially hold two such surfaces together. The strength of "water" bonding of two oxidized Si surfaces is 0.10 J/m2 according to Stengl [24]. The actual bond energy depends on the details of surface preparation, bonding conditions, and ambient. The field of wafer bonding for SOI applications was initiated by Lasky at IBM [25]. He showed that bonding only required proper cleaning of the wafer surfaces followed by applying some slight mechanical force. Independently of Lasky and about the same time, Frye et al. [26] at Bell Labs showed that wafers could be bonded by pressing them together by means of electrostatic forces. Since Lasky's method did not require electric field, it became the dominant approach. The evolution of IR transmission spectra for light that was propagated along the interface between two oxidized Si wafers was investigated in some detail by Weldon et al. as a function of thermal annealing [27]. They looked mainly at the case where both Si surfaces were coated just with a chemical (native) oxide that formed during a modified RCA cleaning step. In these experiments, spectra associated with Si–O, Si–H, and O–H stretching vibrations were detected and studied. Based on the interpretation of the spectra, the following model of the bonding mechanism emerged. Immediately after the wafers are fused together at room temperature, there are a few monolayers of water trapped between two native oxide films, each approximately 4 A˚ thick. Heating samples to 3008C eliminates about 75% of water by diffusion through the thin oxides to the Si interfaces, where an additional 4 A˚ of oxide is formed. The oxidation reaction liberates molecular hydrogen. When the bonded wafer pair is heated further, up to 8008C, the remaining water diffuses away from the bond interface, so that interfacial hydroxyl groups on opposing surfaces can couple into bridging siloxane
bonds that begin to fuse the two wafers together:
Si–OH C HO–Si/ Si–O–Si C H2 O The water produced in the reaction above causes further oxidation of Si and the liberated H is trapped in the newly formed oxide. After further heating of the samples up to 11008C, a complete closure of the interface occurs by coupling of the remaining interface hydroxyl species and diffusion of the hydrogen into the Si bulk:
Si–OH C HO–Si/ ½Si–O–Si
C 2H; H/ HðsiliconÞbulk
The results for Si wafers with a thermal oxide instead of a chemical oxide are similar, but about 40% less water is trapped initially between wafers—possibly because the surface of the thermal oxide is smoother. In order to systematically measure the strength of the bonded interface between two wafers, Maszara et al. [28] introduced a double cantilever or crack opening method. In this approach, a wedge is pushed from one side between two bonded wafers and the length of the debonded area is correlated with the wedge thickness and elastic coefficients of the wafers that are being separated. Measurements showed that the bond energy immediately after bonding can vary across a large range for two oxidized Si wafers [22]. However, after 50–100 h in room ambient, the bond energy usually saturates at a value of 130G4 mJ/m2. This saturation is caused by hydrogen bridges that gradually fill gaps between two somewhat imperfect surfaces [29]. After the initial room temperature bonding, annealing at elevated temperatures fuses the wafers. The bond strength reaches a maximum value of approximately 2 J/m2 after a heat treatment at 11008C [28]. In a recent paper, a quantitative description of the dynamics of the adhesion process was proposed and compared with experiments [30]. The model is consistent with data and with literature results. On this basis, the authors suggest that the bonding front velocity can become a method for nondestructive determination of the bonding energy. Exposing either one or both surfaces to oxygen plasma before bonding them together can significantly enhance the room temperature bonding energy [31–33]. Approximately the same enhancement can also be achieved with nitrogen or argon plasma. The mechanism of the enhancement appears to be related to the plasma-induced surface damage and not to surface-trapped charges, as some initially postulated. The damage increases surface porosity, which accelerates outdifusion of water from the interface between two bonded wafers.
Smart Cute Technology
Michel Bruel of LETI discovered that the blistering effect, well known [34–37] in the ion implantation community and also in the nuclear reactor field, could be harnessed to produce very well-controlled transfer of thin layers from one semiconductor substrate to another. A patent on forming SOI films by controlled exfoliation was filed in 1991 [38], and technical publications on this subject started appearing in 1995 [39,40]. This important discovery led to a new way of making SOI wafers and greatly accelerated transition of SOI into the commercial arena. Bruel's method, utilizes various gas ions—most commonly, hydrogen—for implantation as an atomic scalpel that cuts through Si wafers. Hydrogen ions, when implanted to a dose of greater than 5!1016 cmK2, produce fine microcavities in the Si lattice. Some hydrogen ions attach themselves to the dangling Si bonds in the microcavities, while others fill these voids. If such an ion-implanted wafer is heated up, typically to 4008C–5008C, more hydrogen segregates into the voids in the form of molecular hydrogen, H2, the pressure builds up to a point of fracture, and the surface of Si becomes pockmarked with blisters. This is clearly an undesirable effect of ion implantation. For an implant dose exceeding approximately 1017 cmK2, blistering may occur even without the heat treatment. Blistering phenomena caused by surface bombardment with hydrogen or inert gases have been seen in the past. Extended defects
produced by lower doses of hydrogen in silicon were detected and analyzed by Johnson et al. [41] and by Cerofolini et al. [42]. Johnson et al. even reported observing hydrogen platelets and microcracks [41]. The essence of Bruel's invention was the realization that the effect, which was always considered deleterious, could be utilized to produce a highly fragile planar zone that would facilitate controlled cutting through the crystalline lattice. The most important ingredient of Bruel's method was a stiffener placed on the top of the implanted wafer. This thick and stiff layer prevents blistering and redirects the pressure that builds up in microcavities in a lateral direction, as shown schematically in Figure 4.3. After the stiffener is attached to the suitably implanted wafer, some form of force is applied to split the crystal. Heating of the wafer builds up pressure within the weakened plane that can cause a split. Alternatively, application of a mechanical or other stress will also cause cleavage of the crystal. 4.3.2.1
The idea of controlled exfoliation and layer transfer was developed into a commercial process for SOI that is known as the Smart Cute technology. In this method, a typical sequence of steps required to make SOI wafers is shown in Figure 4.4. A seed wafer, from which a layer of Si will be removed, is oxidized to a desired thickness. This oxide will become the BOX after bonding. The next step is hydrogen implantation through the oxide and into Si with a dose that is typically greater than 5!1016 cmK2. After the implantation, the seed wafer and the handle wafer are carefully cleaned in order to eliminate any particles and surface contaminants, and to make both surfaces hydrophilic. Wafer pairs are aligned and contacted so that the fusion wave can propagate across the entire interface [30]. A batch of bonded wafer pairs is loaded into a furnace and heated to a temperature of 4008C–6008C, at which point the wafers split along the hydrogen implanted plane. The as-split wafer surface has a mean roughness of a few nanometers. A light touch-polish or other surface treatment brings the same surface roughness as in the standard bulk Si
FIGURE 4.3 A schematic drawing illustrating the importance of a "stiffener" layer. At the top a microcavity filled with gas, typically hydrogen, forms a blister that is about to burst. At the bottom, the stiffener redirects the pressure in the lateral direction.
1 Initial silicon 2 Oxidation 3 Smart Cut implantation
B A H+ ions A A
4 Cleaning and bonding
B A
5 Smart cut 6 Annealing 1100°C and CMP 7 Wafer A refresh
B Si bulk
SOI wafer
Or New A
New B
Smart Cut schematic.
wafers, i.e., Ra!1 A˚ across 1!1 mm2. The seed wafer is reclaimed and, if necessary, repolished so that it can be used again. There are several important practical aspects to the method of controlled transfer of a layer of Si, the thickness of which is approximately defined by ion implantation energy, to a handle wafer. This approach makes it possible to reuse the seed wafer several times, thus reducing the final cost of the SOI wafer. It is the premium seed wafer that defines the quality of the SOI film, whereas the handle wafer only serves as a mechanical support and can have less stringent parameters. Defining film thickness by implantation energy leads to a much better thickness uniformity control than is possible with either mechanical or chemical thinning. For that reason BESOI techniques are typically limited to films thicker than 5 mm, where the absolute thickness control is easier. The thickness of the silicon film and/or BOX can be adjusted in a wide range in the Smart Cute process by tuning the implant energy and oxidation time. The thickness of the silicon film in current applications typically runs from about 5 nm to 1.5 mm. The thickness of the silicon dioxide is typically set at 5 nm to 5 mm. Unibondw wafers are thus adaptable to most device architectures, from ultra-thin CMOS to thick-film power transistors and sensors. It is also worth noting that only conventional equipment is needed for mass production of 8 and 12 00 wafers. 4.3.2.2
Hydrogen-Induced Splitting
In this section, we describe the physical mechanisms that come into play when ion implantation into silicon generates certain types of damage that eventually lead to splitting of a thin layer away from the main substrate. This splitting can be achieved by implanting hydrogen or noble gas ions. Here, we will limit the discussion to hydrogen, as its interactions with silicon are best understood and most experimental data are available for this case [43]. Later we will also consider the co-implantation effects of hydrogen and helium [44,45]. High-dose hydrogen implantation into Si produces platelets that tend to trap hydrogen. For HC implant doses greater than 2!1016 cmK2 at 60 keV, the initial platelet density is high enough so that some of them grow through the thermal cycle at the expense of smaller ones that are dissolved. This is a typical case of coarsening of the structure by means of Ostwald ripening. For HC doses lesser than 2!1016 cmK2 at the same implant energy, the platelet concentration in a standard silicon wafer is usually insufficient to trap H for extended times at elevated temperatures. Low platelet density and their small size are not favorable for producing microcracks.
4.3.2.2.1 Implanted Silicon Wafers—No Annealing Aspar and his associates analyzed in detail the as-implanted Si wafers by transmission electron microscopy (TEM) [46,47]. Additional information on hydrogen chemical bonds, inside the silicon matrix, was obtained by infrared absorption spectroscopy in the multiple internal transmission configuration [48]. After implantation of hydrogen doses in the range of a few 1016–1017 HC cmK2, there are no defects at the Si surface, but XTEM micrographs indicate the presence of platelets or microcavities confined around the maximum hydrogen concentration depth, Rp. These platelets are visible in high resolution TEM and when using bright field conditions far from any Bragg diffraction. For an approximately 6!1016 HC cmK2 implantation dose, the platelets are about 1–2 atomic planes in height and about 10 nm in diameter [49]. In (100) wafers, most of the platelets lie on the (100) planes parallel to the surface, and to a lesser extent on the (111) planes. Recently some platelets that are perpendicular to the (100) surface were also observed [50]. The platelets can be observed by TEM before any heat treatment, and their diameter grows during annealing, while the density goes down and the total volume stays approximately constant. By coupling infrared light into as-implanted wafers [51], Aspar et al. obtained spectra, which showed that hydrogen is bound to silicon mainly as monohydride species [48]. Si–H bonds at (111) surfaces and Si–H2 bonds at (100) surfaces can also be observed. They correspond to the presence of (100) and (111) platelet-like defects observed by TEM in the implanted region. The size of the (100) microcavities depends on the implantation conditions and can vary from small platelets up to microcracks. In some extreme cases, these microcracks located around the projected range Rp can have a size of several microns, and even lead to formation of the blisters that are optically visible at the wafer surface. For instance, a high dose hydrogen implantation of 2!1017 HC cmK2 leads through growth of the platelets to the microsplitting phenomenon. 4.3.2.2.2 Annealed Hydrogen-Implanted Silicon Wafers In wafers implanted with a few 1016–1017 cmK2 hydrogen ions, heating induces growth of microcavities and results in the formation of microcracks, as shown in Figure 4.5. A quantitative TEM study of the thermal evolution of the platelets requires the use of specific imaging conditions [46,47], so that the size distribution, density, and overall volume occupied by the cavities can be measured as a function of the
Micro-cracks 5 nm
Microcracks in a "weakened" zone after hydrogen implantation and thermal treatment.
thermal history. For 6!1016 HC cmK2 samples implanted at 70 keV, the first minutes at 4508C cause the growth of the (100) microcavities that are parallel to the surface, while their density decreases and the total volume remains approximately constant. This is consistent with an Ostwald ripening mechanism for growth of larger microcavities at the expense of smaller ones that shrink and disappear. In the process, hydrogen diffuses from the small cavities to the larger ones. The results are in agreement with an earlier study of a wafer implanted with a lower, 3!1016 cmK2, hydrogen dose [47]. Splitting kinetics for different crystalline orientations were first reported by Zeng et al. [52], and investigated in more detail by Bourdelle et al. [53]. Arhenius plots obtained by the latter for splitting along (100), (110), and (111) planes are presented in Figure 4.6. 4.3.2.3
Hydrogen and Helium Co-Implantation
A weakened zone can be produced inside a Si crystal not only with hydrogen, but also with other implanted species, in particular with helium and other noble gases. However, hydrogen, either alone, or in tandem with another species, is preferred because of its reactivity with the internal surfaces of a semiconductor. For example, a study of co-implantation of HC and HeC has demonstrated that each plays a somewhat different role. Hydrogen interacts chemically with the implantation damage to produce platelet-shaped microvoids. HeC, implanted after the hydrogen, fills the cavities and provides most of the pressure that causes splitting of a Si film from the bulk substrate. Agarwal et al. [44], have demonstrated that splitting could be achieved with doses as low as 7.5!1015 cmK2 HC and 1016 cmK2 HeC. In contrast, under the same implantation and annealing conditions, HeC alone requires a significantly higher dose of 2!1017 cmK2 and HC alone requires 6!1016 cmK2. According to Agarwal, reversing the sequence of implants in the low-implant dose case does not provide the same benefits as the "hydrogen first" case. More recent evidence indicates that implantation conditions, and in particular the relative implantation depth for the two species, plays an important role. Lagahe-Blanchard et al. have shown that the advantage of HC implant first disappears, if the projected range Rp of HeC ions is greater than that of HC ions [54]. They also demonstrated that co-implantation can improve the quality of transferred Si layers and provide better splitting kinetics. Increasing the total co-implant dose to 5.5!1016 cmK2 made
T(°C) −2
t(min)
0.9 Ea~0.35 eV Ea~0.29 eV Ea~0.33 eV
−5 ln (1/t )
−10 −11
1/kT
Arhenius plots for splitting along three crystal orientations: (100), (111), and (110).
possible thermal splitting at a significantly reduced thermal budget, a feature that has significant practical advantages, especially when heterostructures are made [54,55]. Nguyen et al. [45] investigated in great detail the damage formation caused by co-implantation as a function of the implant sequence and ion energy. Their analysis of TEM and IR spectra explains how subtle changes in amorphization trends for four sets of initial parameters lead to slightly different conditions for splitting and it shows how they affect the quality of as-split surfaces.
Bond and etchback SOI, also known as BESOI, is very useful for forming thick Si films that are dielectrically isolated from the substrate [17,21,25]. Films thicker than 10 mm are relatively simple to make by standard grinding, etching, and polishing methods (see Figure 4.7). Without any specific thickness markers or etch-stop layers it is difficult to control film thickness and uniformity to less than 1 mm, but for thick film applications this degree of precision is often adequate. Better thickness control can be obtained by introducing etch stop layers or at least depth markers. For example, if there is a heavily boron-doped buried layer many micrometers under the surface, it will sharply reduce silicon removal in a KOH etch bath. Thin SiGe layers or oxygen implants can play a similar role. One significant disadvantage of the BESOI process is that two Si substrates are always consumed to make one SOI wafer. Etch stop layers, if needed, require additional process steps, typically growth of thick epitaxial layers. Bond and etchback SOI wafers are used in many MEMS applications, where 10–100 mm thick films are often required. Some high power and/or high voltage devices also take advantage of these structures.
Si wafer 2
Grinding, polishing, and etching x-Si
x-Si
Bond and etch SOI (BESOI) schematic.
In Section 4.2.2.3, we have already indicated that porous Si is the key to the ELTRAN process. Porous silicon is formed when Si is anodized in an HF solution, an electrochemical process that was first described in detail by Uhlir in 1956 [56]. In the electrolytic cell, a random network of nano-pores is etched out in Si. Baumgart et al. were the first to show that porous Si surface is still an acceptable template for epitaxial Si deposition [57]. Yonehara et al. demonstrated that it is possible and practical to grow device quality single crystalline Si films on the top of porous Si layers [58]. They utilized high temperature annealing in hydrogen, which greatly increases the mobility of Si atoms, to seal the pores at the surface, thus improving the quality of the substrate for the subsequent Si growth. After Si epitaxy and oxidation to form what will become the buried oxide, the donor wafer is bonded to a Si handle wafer. To complete layer transfer, the wafer stack is fractured mechanically along the porous Si layer that is mechanically weak. A fine water jet, aligned with the wafer plane and incident at the perimeter of the wafer pair that is rotated in front of it, breaks the wafers apart. The ELTRAN team further improved the quality of as-split surfaces by modifying the physical properties of the porous layer [59]. The size and density of pores are a function of the current conditions during anodization. For best results, very fine pores are formed at the donor wafer surface, with a second coarser layer positioned deeper into the substrate, as shown schematically in Figure 4.8. The built-in interfacial stress at the boundary between these two porous layers facilitates water jet-induced cracking along the planar interface, leading to a more uniform cleavage. The finishing steps for the newly formed SOI wafers consist of etching away of the residual porous Si followed by surface smoothing by a second application of hydrogen annealing at about 11008C. The original donor wafer, from which a thin layer of porous Si was split-off, can be reclaimed, polished, and used again.
SIMOX Basic Concepts and Early Results
In mid-1970s, Izumi and his coworkers at NTT started investigating SOI formation by direct synthesis of SiO2 from implanted oxygen ions. Experiments on BOX formation were initiated with an Extrion 20020a ion implanter [60]. In 1978, Izumi et al. demonstrated a 19-stage CMOS ring oscillator made in the new material, which they called SIMOX [61]. In these early attempts to form SOI, enough oxygen needed to be implanted to reach the stoichiometric concentration of oxygen in the buried SiO2 layer already during implantation. To achieve a Si film of about 200 nm, 200 keV ion energy was necessary, and approximately 2!1018
Large pores Wafer A (reusable) Small pores Epi-Si
Wafer B
ELTRAN schematic.
oxygen ions cmK2, a dose 100 times above a typical implant dose utilized in device processing. Because of this high dose, crystalline lattice damage was very extensive. In fact, at room temperature, the entire layer penetrated by the ions would have been completely amorphized. To preserve single crystalline nature of the Si overlayer, thermal annealing was needed concurrent with the implantation. At temperatures greater than 5008C, the dynamic annealing of damage during implantation leaves monocrystalline Si near the Si surface, where the ion energy is highest and thus there is less displacement damage. After implantation, very high temperature annealing is required to react oxygen ions with Si in order to form SiO2 while annealing the damage in the Si layer above and in the Si substrate below the oxide. Evolution of the SIMOX structure during oxygen implantation is shown in Figure 4.9 [62]. 4.3.5.2
High Temperature Annealing
Conventional furnaces with fused silica liners are limited to temperatures lesser than 12508C. The microstructure quality and device yields after 12508C anneals were poor. Annealing at very high temperatures was developed to improve the microstructure. Dissolution of oxide precipitates at elevated temperatures depends on Ostwald ripening that causes growth of the precipitates with a radius above a critical value at the expense of the smaller ones that are dissolved [63]. At temperatures Ta above 13008C the critical radius approaches infinity—only the planar BOX remains. Annealing of SIMOX structures at 13008C for several hours [63] or at 14058C in a lamp furnace for 30 min [64,65] demonstrated the feasibility of forming atomically sharp and planar interfaces between Si and the buried oxide. The dependence of SIMOX microstructure on annealing temperature is well documented [66,67]. All SIMOX wafers that are currently produced undergo annealing at 13008C or above (typically w13508C) in furnaces with either polysilicon or SiC tubes.
SOI by oxygen implantation Increasing dose O+
Single crystal silicon
Defective single crystal silicon
f c ≈ 1.4 × 1018 0 cm−2 at 200 KeV
FIGURE 4.9 Evolution of a separation by implantation of oxygen (SIMOX) structure during oxygen implantation. (Adapted from Hemment, P. L. F., Reeson, K. J., Kilner, J.A., Chater, R. J., Marsh, C., Booker, G. R., Davis, J. R., and Celler, G. K., Nucl. Instr. Meth. Phys. Res., B21, 129, 1987.)
Implant Optimization
Temperature Ti of the Si substrates during implantation also plays a critical role in achieving good microstructure of SOI wafers. In early SIMOX wafers, 1010 cmK2 threading dislocations were typical. Reduction to 106 cmK2 threading dislocations was achieved by increasing implantation temperature to approximately 6008C [68]. To further reduce the defects, the dedicated oxygen implanters had to be improved and optimized for very high doses. To avoid sputtering of metals from the walls of the implantation chamber and onto the wafers, the chamber interior was coated with silicon. 4.3.5.4
Low-Dose SIMOX
SIMOX technology has greatly evolved and improved since the first device demonstrations by Izumi et al. [61]. The efforts to reduce defect density and cut down the cost of processing were helped by the devicescaling trend that required moving to thinner films. Thinner Si film means lower implant energy, and thinner BOX translates into a lower implant dose. Lower oxygen dose, in particular, helps in improving crystalline quality of the wafers. Cutting the oxygen dose is not entirely trivial; mechanisms that allow formation of a planar and uniform BOX are not understood well enough to make theoretical predictions of optimum implantation conditions. Experimentally a few "sweet spots" were identified. For example, a high quality planar BOX was obtained at a much lower dose of 4!1017 cmK2 by modifying the implant and anneal conditions [69]. This low-dose BOX is about 100-nm thick, suitable for the sub-0.25-mm CMOS devices. The feasibility of even thinner BOX films has been demonstrated with OC implantation of just 2!1017 cmK2 at 65 keV, followed by 4 h anneal at 13508C, which resulted in a 56-nm thick oxide [70]. 4.3.5.5
ITOX Process
The success of SIMOX with a thin BOX was greatly facilitated by a discovery and development of a procedure known as internal oxidation (ITOX). Synthesized BOX is prone to have some pinholes or Si pipes that electrically short the Si film to the substrate. However, when an SOI wafer is oxidized at approximately 13508C, a small fraction of oxygen that diffuses through the surface oxide also diffuses through the silicon film (instead of oxidizing the Si surface) and reacts with it at the Si/BOX interface [71]. This internal oxidation improves the stoichiometry of the BOX, giving it properties much closer to those of thermally grown SiO2, reduces or closes Si pipes, and as shown schematically in Figure 4.10, it slightly increases the overall thickness of the BOX. Commercially available SIMOX wafers, known by trade names like MLD (modified low dose) and Advantoxe, fine-tune the processing parameters and add some additional improvements. For example, the SIMOX structure was modified by adding a low dose (1015 cmK2) room temperature implant after
Superficial thermal oxide
Surface SiO2 Si film
BOX + ITOX
BOX 0.2 μm
Before oxidation
After oxidation
Schematic representation of the internal oxidation (ITOX) process.
the "standard" hot implant [72]. This additional step leads to a more planar BOX layer with fewer Si inclusions, since it amorphizes the Si just above the peak of oxygen concentration Rp. 4.3.5.6
Patterned Buried Oxide
SIMOX SOI substrates are normally formed by a blanket oxygen implantation. But there are some applications, such as SOC and microprocessors with embedded DRAMs, where it might be useful to have BOX only in some parts of the wafer, with other areas remaining as conventional bulk Si. Attempts to implant oxygen locally through a thick-patterned masking layer were started already in 1980s [73,74]. In these experiments, after the standard 2!1018 cmK2 oxygen dose was implanted, the boundary between the SOI and bulk regions was extremely defective because of high stresses at the oxide edges. After low dose SIMOX was developed, the density of defects at the boundary was reduced considerably, but it was still high enough to potentially cause problems with device yield and reliability. Cohen and Sadana, reduced further the number of defects in the transition region between SOI and bulk [75]. They used a blanket low-dose oxygen implantation, followed by a touch-up amorphizing OC implant at room temperature and then by patterned internal oxidation (ITOX process). This led to a thicker BOX in regions exposed to oxidation (but also much thinner Si in the same areas). In the extreme case of a subthreshold OC implant dose of 1.5!1017 cmK2, the BOX was discontinuous under the oxidation mask. Ogura [76] used a different approach in which oxygen precipitated into BOX layers only in regions that were previously damaged by HeC implantation. Researchers from Shanghai have recently reported interesting results on forming low-dose patterned BOX by carefully optimizing the dose and energy conditions, followed by 13008C anneal in Ar with 3% O2 [77]. Good results were obtained at 3.5!1017 cmK2 @100 keV and at 2!1017 cmK2 @ 50 keV.
Other Fabrication Methods Overview—SOI Menagerie
Over the years, there have been many attempts to utilize localized templates and then extend epitaxial growth from these templates to other regions, but these approaches, although scientifically interesting, have not led to many practical solutions. The situation is somewhat different when the insulator is not amorphous, but monocrystalline. Heteroepitaxial growth of Si on a bulk crystalline sapphire, became a commercial technology known as SOS, but was found to be of limited utility except for rad-hard CMOS. Several other approaches have been studied, which significantly enlarged our body of knowledge about the microstructure and morphology of thin silicon films. These methods, including those already discussed by us, are summarized in Table 4.1 that is reprinted from Celler and Cristoloveanu [3], and an interested reader can obtain the details by following the references listed in the Table. The great variety of approaches did not lead to commercial applications. Many of these techniques require intimate integration of SOI fabrication with device making—in other words, the SOI is patterned and the pattern is device- or circuit-dependent. This means that the SOI fabrication needs to be completed by the same production line that makes devices. Complexity of doing both discouraged most semiconductor chipmakers. There were two interesting exceptions in the past, DI and SOS. And to complete the picture, there is also an interesting recent approach, silicon-on-nothing (SON), in which the isolation layer is formed as a part of the device fabrication process. All three methods are briefly explained below. 4.3.6.2
DI Technology
This technology was developed at TI by Bean and Runyan for bipolar and high voltage applications [78]. The approach required one starting bulk Si wafer, patterning and deep etching, thick oxide, and deposition of very thick polysilicon at high temperatures. The technology provided complete dielectric isolation between large regions of single crystalline Si. It was suitable for some large devices and high voltages. The detrimental aspect was the presence of a
polycrystalline handle wafer—dimensional stability (and with it wafer flatness, bow, and warp) was inferior to conventional Si wafers. LEGO process was an attempt to preserve the unique structure of DI wafers while providing a single crystalline Si handle wafer [84]. A related development to produce power devices in very thick films is ongoing [90]. 4.3.6.3
Heteroepitaxy played an important role in the early days of SOI. SOS [79] is about as old as DI, and the main motivation for its development was radiation hardness. Since the crystalline quality of as-grown epitaxial Si on Al2O3 is rather poor, post-epi steps are usually added. Commonly they include a Si implant that amorphizes the most defective Si near the alumina interface. In the subsequent solid phase epitaxial regrowth, the template is the near-surface Si that has better crystalline quality. 4.3.6.4
Silicon-on-nothing process consists in growing by selective epitaxy a sacrificial SiGe layer in STIpredefined regions of a bulk-Si wafer. A silicon film with suitable thickness (20 nm or less) is then epitaxially grown. Selective etching of the SiGe layer leaves an empty space (air-gap) underneath the film. The suspended Si membrane can be used to fabricate gate-all-around (GAA) transistors. Alternatively, the air-gap can be filled with a dielectric in order to form a localized SOI structure, integrated in the bulkSi wafer [89,91].
Advanced Wafer Engineering
The International Technology Roadmap for Semiconductors points out that the performance of Si devices should be improving by approximately 17% per year. For many years now such improvements were being achieved primarily by shrinking the device dimensions, i.e., device scaling and advances in lithography provided the needed performance. More recently, it has been realized that just shrinking the device dimensions is no longer sufficient. New or improved materials and novel configurations of existing materials have become essential. "New" materials and modification of existing materials are now pervasive in IC manufacturing. They include Cu interconnects as a replacement for Al, low-k dielectric to separate the layers of interconnects, development of high-k dielectric to replace the traditional SiO2 gate dielectric. In addition to these device-scale improvements, modifications to the starting wafers can also greatly enhance performance of the circuits that are built on them [92]. Below, we describe some of such wafer-scale modifications. They range from extremely simple solutions, such as rotation of the wafer crystalline plane, to much more complex in which charge carrier mobilities are enhanced by modifying basic properties of silicon, i.e., its lattice parameters. In almost all of these wafer-scale solutions, the ability to bond wafers, and in particular a transfer of layers from one substrate to another that is enabled by Smart Cut, plays a key role.
Crystal Orientations A Rotation within the (100) Plane
Silicon-on-insulator wafers produced by layer transfer add a new degree of freedom to the fabrication process, namely the possibility of choosing different crystal orientations for the thin active layer and the handle wafer below it. Traditionally, Si wafers were made with the (100) crystalline orientation of the surface and a notch (or a flat in smaller diameter wafers) that defined the !110O direction in the wafer plane. The (100) surface was chosen in the early days of MOS technology as it yielded the lowest density of interface states, Dit. With advanced surface preparation techniques available today, this selection is less significant. The notch (flat) location defines the alignment of the edges of rectangular silicon die with the (110) preferred cleavage planes of Si. This alignment was essential when wafers were divided into die by
scribing and breaking, and it is still of some importance today when wafers are cut with a saw, since it helps to maintain smooth edges of the die. Currently, when every enhancement of charge mobility is important, the traditional configuration with transistor channels in the (100) plane and the current flow in the !110O direction is less than ideal. Specific shapes of conduction and valence bands in silicon lead to different optimum configurations for the mobilities of electrons and holes [93]. For the NMOS, electrons have the highest mobility in the conventional (100) plane, and both !100O and !110O directions of the current flow are approximately equivalent [94,95]. But for PMOS, there is about 16% mobility advantage when the channel in the (100) wafer is aligned with the !100O direction [94]. This can be easily implemented in SOI by rotating the thin film by 45 degrees around the axis normal to the wafer plane, so that the !110O in the handle coincides with the !100O direction of the active device film (See Figure 4.11) [95]. 4.4.1.2
Other Crystalline Planes
Because of the difference in the shape of electronic bands for electrons and holes, the crystalline plane that provides the best performance for NMOS devices, namely the (100), is far from optimum for the PMOS. PMOS performance can be greatly enhanced simply by choosing wafers with the (110) surface plane. Hole mobility is then almost doubled in comparison to the (100) configuration, and it is true even for extremely thin (110) oriented films, of the order of 6 nm [96]. Unfortunately, this comes at a significant penalty to the NMOSFET performance, as shown in the data of Figure 4.12 [97]. The question then arises what is the best way to independently optimize crystalline orientations for NMOS and PMOS. One option relies on using conventional wafers and varying the device architecture [98], another option involves wafers that are engineered to provide access to both crystalline orientations [97,99]. Nonplanar transistors such as FinFETs are described in Section 4.10 of this chapter. It suffices to say here that in such structures the transistor channel plane is perpendicular to the wafer plane. Doris et al. [98], have proposed utilizing a mix of planar transistors for NMOS and FinFETS for PMOS in order to get both the (100) plane for the former and the (110) plane for the latter, assuming that the current flow direction in the PMOS is parallel to !110O. The main problem with this scheme is that the circuit architecture becomes complex, and integration of planar and non-planar devices on the same wafer is not trivial. The second option for simultaneous use of two different crystalline orientations moves the burden from device fabrication to the wafer level. Hybrid orientation technology (HOT) is based on forming SOI wafers in which crystalline orientation of the Si film is different than that of the handle wafer [97,99]. It should be clear that only technologies based on wafer bonding make such structures possible. HOT SOI wafers are typically made by Smart Cut, so that the Si film is (100) and the handle is (110) or vice versa. In the first case, NMOS devices are made in SOI, while regions that will be dedicated to PMOS
Handle wafer
4:1 @ 22 nm
Contact ≈110 nm
FIGURE 21.28 Illustration of International Technology Roadmap for Semiconductors etched contact feature scaling roadmap with the impact on the feature aspect ratio compared to the gate electrode. The dashed line represents the contact aspect ratio referenced to the gate electrode height.
DK4126—Chapter21—23/5/2007—18:30—ANBARASAN—240450—XML MODEL CRC12a – pp. 1–69
process tools or new technologies for patterning, CVD or etch. So the same or preferably a reduction in feature aspect ratio can significantly reduce the risk and complexity for the introduction of the next technology node. 21.4.1.4
Imaging Resolution, Control and Line Edge Roughness
Assuming that immersion lithography in combination with alternative patterning techniques will be able to achieve the resolution requirements, then from a more practical standpoint, LER as defined in the final feature, may be the most critical technology challenge at the 45–32 nm technology nodes.110 "Roughness" has not improved from the 90 to 65 nm nodes and in most cases it has worsened as device features have been scaled, the impact continues to become more critical. While a known phenomena at 90 and 65 nm, LER effects in device performance and reliability will become critical at the 45–32 nm technology nodes. A number of investigators have modeled and verified the electrical effects of the LER for various devices and have shown that it is not be significant effect compared to other process variations until 45 nm and below.110–112 For example, a line CD variation of 8 nm (LER of 4 nm on each side) at 100 nm has very little effect on the transistor performance but at 30–20 nm it becomes the dominant variable. As for current and previous technology nodes discussed also in Section 21.3, phenomena like templating make sequences of etches, their interaction with photoresists in process integrations as important as single etch processes in role roughness plays in CD control. With respect to aspect ratio scaling, studies show that LER can be a function of photoresist thickness where thinner photoresist results in less LER— another case for the use of thin photoresist.
Device Roadmap Etch Challenges for 45–32 nm Technology Nodes
Even though the transistor technology is discussed in other chapters of the handbook, it is probably worth a short review of some critical issues that may effect etch process development. Another approach to the device performance and critical scaling requirements is the introduction of novel device structures. These structures may compensate for material and process limitations such as patterning while meeting the device requirements. Novel transistor structures may likely dominate the scaling challenge due to cost and timing of the next generation lithography. As with alternative masking schemes, alternative device structures may provide a more timely and lower risk approach to meeting the device performance scaling challenges compared to the introduction of new materials into the classical planar MOSFET. These structures such as the FinFET transistor can be fabricated with existing materials—silicon and oxynitride dielectrics. Refractory metals and metal oxide dielectrics are more difficult to process, are expensive and pose cross-contamination risks. At the 45 nm technology node, the device low power performance requirement will exceed the likely capability of planar device scaling with thermal oxide or nitride where the standby gate leakage may actually exceed the device on (ion) current. The reliability and the short channel effects may also limit the operating voltage requirements. To meet these requirements, the use of high-k gate dielectric materials will be required. These offer new challenges to etch since these will most likely be a refractory metal oxide or silicate. Since pinning effects significantly limit the polysilicon gate material, the use of metallic gate may also be required. There may well be a metallic gate electrode etch that has to stop on a metallic oxide and both layers may be very difficult to etch.113,114 High-k material etch process chemistries are described by Sha and Chang.115 21.4.2.2
Novel Transistor Structures
There are a number of alternative or novel transistors being investigated including a number starting with the classical planar structure. For example, a fully silicide integrated gate electrode (FUSI) where the gate is formed in polysilicon and than a metal is deposited over the top of the gate. Then the gate is completely converted into silicide thus eliminating the need to etch a refractory metal. Improved device performance can be also be achieved by use of ultra-thin silicon active region operating in the fully depletion MOSFET
S/D Extensions
Lateral SiGe Etching
Dielectric filling
Mono-Si film S
SiGe (a)
FIGURE 21.29 Illustration of the basic silicon-on-nothing process: (a) Selective SiGe/Si epitaxy and integration of the gate stack, (b) source drain (SD) areas etch and selective removal of the SiGe layer, (c) tunnel filling with dielectric layers, and (d) selective epitaxy of the SD areas to contact the Si-channel.
mode such as can be fabricated thin silicon on insulator (SOI). This approach requires only one midband gap metal gate material. Also, a similar novel structure can be build using a sacrificial layer that can be replaced with a thinner dielectric isolation layer. The silicon-on-nothing (SON) transistor structure offers the possible advantage of using epitaxy on a bulk substrate that has more planar silicon integration; so most of the etch processes are consistent with planar CMOS.116 However, to form the dielectric isolation under the active region, a sacrificial layer must be removed and a dielectric deposited under the active region, as illustrated in Figure 21.29. This is accomplished by the use of an high selective isotropic etch of a sacrificial layer of epitaxy SiGe under the thin active silicon layer. Since this is a lateral etch, it must be very isotropic and have very high selectivity to the very thin silicon layer. As similar novel structures are devised, new requirements may need this type of isotropic removal of thin sacrificial layers. 21.4.2.3
Ultra Thin Silicon Structures
One planar structure device that can address a number of the electrical scaling issues is the fully depleted transistor on ultra-thin silicon layer on insulator (FDSOI) planar structure.99,100 Other than the aggressive gate CD scaling, the major etch issue with this type of structure is the use of very thin active SOI. The active silicon layer under the gate structure can be on the order of 100 A˚, making the etch selectivity even that more critical. Since there must be a selective epitaxy layer deposited to reduce the source/drain resistance, the surface must have almost no damage or residue since there is very little material to be able to remove any damage or residue. Multi-gate devices have been showed to have tremendous device improvement without the dependence on extremely effective oxide thickness scaling. But the fabrication of such double gate planar structures is difficult with the close gate alignment, contacting the bottom gate, multiple-layer processing, etc. Several self-aligned gate structures such as the gate all around reduce some of the alignment issues but involve very complex process sequences. Multi-gate device (Figure 21.30)117 are also interesting since the higher gate to channel ratio reduces the requirement on the oxide thickness and the narrow channel for speed performance. The device performance of multi-gate CMOS transistors has been shown by a number of investigators.118 However, most of the original schemes when applied to the traditional planar device structures are very cumbersome to fabricate such as using a buried gate electrode. However, such a device that may be simpler to fabricate is a gate-all-around version of the SON transistor since it is a planar structure and the deposition of the gate electrode can occur after the sacrificial layer is removed under the active region. This also forms a self-aligned gate electrode. To address these device issues, the vertical transistor or FinFET was developed since the active region is a very thin vertical element.100,119–121 Even though this structure involves high aspect ratio features and topography, it utilizes standard thickness SOI substrates and oxynitride gate dielectric used for 65 nm high performance devices and has been shown to be extendable to possibly the 22 nm technology node.
LGate
HFin
TFin
FIGURE 21.30 Illustration of the FinFET transistor. (Reprinted from Nowak, E. J., Aller, I., Ludwig, T., Kim, K., Joshi, R. V., Chuang, C.-T., Bernstein, K., and Puri, R., IEEE Circuits Dev., 20, 20, 2004. With permission. Copyright 2004 IEEE.)
Front End of Line Etch Processes
Gate Etch
The application of metallic gate electrode materials with high-k metal oxide or silicate dielectrics is very likely the dominant technology for the classical planar complementary metal-oxide-semiconductor fieldeffect transistor (CMOSFET) device structures going into the 45–32 nm technology nodes (ITRS roadmap). These materials are needed to meet the device speed and dielectric leakage requirements. Most of the refractory metals, silicide, and metal oxide materials identified as possible candidates are more difficult to etch than polysilicon since these typically have less non-volatile etch by-products and the reduced effectiveness of a hard mask at these dimensions. The use of selective epitaxy in active regions may increase the requirement for less etch residue and mechanical damage. 21.4.3.2
Dual Metal Gate
Maximization of CMOS performance for the classical planar device structures will probably also require dual metal electrode materials with matched work functions for both n- and p-type devices (Figure 21.31). Not only does this mean additional etch processes for quite different materials, but depending on the integration, both materials may have to be etched as a stacked layer. This also places additional selectivity requirements on the opposite doped type regions. To attempt to simply the integration, one metal gate material is deposited on the high-k dielectric and then removed where the other type devices will be fabricated. Then, the next gate electrode is deposited usually followed by polysilicon deposition. This means that the first etch must not etch or damage the high-k dielectric that will have detrimental effects on the devices made over this dielectric. The gate patterning must etch both metal layers on some of the die and only the second metal over the remaining part (see Figure 21.31). Again, this places significant selectivity challenges for the gate etch since the area with one metal layer will be exposed to additional etch of the high-k dielectric. 21.4.3.3
High-k Dielectric Etch
Following the gate etch and usually the spacer formation, the high-k dielectric must be removed. Unlike the classical silicon oxides, these materials do not etch in HF solutions and often depends on the amount
Resist Oxide TiN HfO2
TiN removal PMOS NMOS
Oxide (PMOS)
PMOS NMOS
TiN (NMOS)
HF clean PMOS NMOS
TaSiN
HfO2 (light contrast) Oxide (NMOS) (PMOS)
TiN (PMOS)
HfO2 (Light contrast) (NMOS)
FIGURE 21.31 Schematic of a dual-metal gate process flow with corresponding scanning electron micrographs (SEM) images of a static random access memory (SRAM) bit cell array showing the different layers for the N-channel metal-oxide semiconductor (transistor) and P-channel metal-oxide semiconductor (transistor) regions. (From Samavedam, S., La, L., Smith, J., Dakshina-Murphy, S., Luckoski, E., Schaeffer, J., Zalava, M. et al., Symposium on VLSI Technology, 24, 2002.)
of damage during the gate etch or other process conditions such as thermal treatments. Similar to the metal gate materials, these are also difficult to dry etch as they can have some morphology and have metallic component that is less volatile such as hafnium or zirconium, and as a result the selectivity to silicon substrate is typically not as good. Unfortunately, due the scaling issues and fabrication of the transistors on ultra thin silicon regions the required selectivity is significantly higher. Considerable effort is underway to identify possible dry etch solution but as no totally satisfactory solutions have been developed, a different approach such as atomic layer etching (ALE) may be required. However, it is difficult to focus on all the possible etch schemes since there is not a clear technology direction that will be taken by the industry. But there are some clear challenge differences for some of the likely alternative options, and these should be considered in the etch technology development and ultimate capabilities or these will define the next etch technology. For example, the planar, ultra thin body transistor structure or SON requires the removal of a very thin sacrificial layer under the very thin active silicon region116 (Figure 21.29). This etch by definition must be highly isotropic. Wet chemical etching has been used but this is very limited and the mechanical stresses on these extremely thin structures may be unacceptable except for investigation and feasibility tests. A chemical downstream etch has been shown to give highly isotropic etch using fluorine chemistry such as CF4.122 However, this is a timed etch since it does have an effective end point capability, and there is a loss of selectivity when the SiGe is completely removed (endpoint). An alternative process using an ICP chamber operated in a remote low power plasma mode with no bias power.123 This has been shown to the same or higher selectivity with improved uniformity and the capability to monitor the plasma using optical emission. Probably the leading candidate for the next generation novel structure is the vertical dual-gate on ultra-thin silicon or the FinFET structure (Figure 21.30). There are a number of different multi-gate, dual gate, or tri-gate variations that have been proposed, and each offer some slightly different etch challenge. The most basic structure will probably be a simple vertical fin formed in a SOI substrate with initially classical doped polysilicon gate electrode on silicon oxynitride dielectric. The silicon etch uses typical gate chemistries except that it is a very high aspect ratio, 10:1 and greater, depending on the device performance requirements. This has many of the concerns expressed about the difficulties of processing high aspect ratio features.
Spacer Etch
Another process that has been impacted is the gate spacer etch. Although very similar to previous technology nodes, this process is also affected by the feature scaling. This means that not only will the spacer be narrower with a higher aspect ratio, but also the uniformity requirements will increase to reduce the variation on the device performance. Similar to the gate etch, it is more difficult to etch with very high selectivity to be able to stop on the high-k gate dielectric compared to silicon oxynitride films. Also, on novel structures such as the FUSI or FinFET, there may be multi-type film stacks such as metal gates or even more extremely high feature aspect ratios. Of course, there is still the inevitable device scaling, which puts more requirements on the hard mask and photoresist trim process capabilities. As mentioned previously, a key to improved patterning process capability will be the use of multi layer patterning especially with an organic hard mask layer. This will probably be more compatible to the new gate materials and the lower thermal budget that may be required. Also, the multiple layers allow the opportunity to optimize the feature sizing methods such as trimming. 21.4.3.5
STI or Isolation
For those devices that may still use bulk silicon, there is even more CD control and probably the same LER requirements as the transistor gate. Improved transistor isolation will mean even higher aspect ratios and profile controls since the use of low-k dielectrics maybe needed to improve cross talk similar to the metal interconnects. These typicallly have the same feature gap fill issues as the current TEOS CVD films but be more difficult to implement for the planarization and oxide recess through the following etch and clean steps. Low-k dielectric even Fluorinated TEOS (FTEOS) introduces new concerns about other chemical effects or "contamination" of the active region. Recent device performance has been seen with the use of a stressor layer in the bottom of the STI regions. This again adds complexity and control requires for the etch and module integration. There will likely be a number of silicon etch processes required for the various electrical isolation steps such as for FDSOI transistor. The trend to more SOI structures, even to ultra-thin silicon structures offer actually less challenges for etch since the etch needs only to pattern very thin silicon layers over BOX. In fact this is a significant factor in selection of different device integration strategies. 21.4.3.6
Contact Feature Etch Challenges
Contact is always a very critical closed feature that has to be fabricated since it has the minimum sizing to allow the highest possible circuit density. And usually it is a very high aspect ratio feature since as mentioned before, the gate electrode stack and dielectric capping layers are not scaling with the technology. Similar to the current technology nodes, the requirement for contact and interconnect become more difficult with scaling but contact is more difficult to image with extremely low defectivity or missing patterns. A relatively thick photoresist is needed for the high anti-reflection (coating) (AR) oxide etch process, so a high photoresist exposure dose is required and, along with high pattern density image proximity effects, results in a small process window. These factors have prompted the increased use of silicon containing bilayer or multi-layer resist strategies at the 65 nm node and will probably become required at 45 nm and below. Also the roughness (similar to LER) that occurs during patterning is also a significant problem at contact since this marginality in the process is indicative of a high defective process and can also impact contact resistance and reliability. So the lithography challenge is some ways except for CD uniformity is more difficult than gate since there is not a post-develop "trick" that has been shown effective in reducing the printed image sizing. Some techniques such as material "repair" or treatment have been shown to improve the resist selectivity after develop but these do little to reduce the sizing. There have been a number of attempts to increase the post-developed contact sizing by the addition of a polymer (resist) that reacts with the contact sidewall similar to the resist poisoning phenomenon. After a second develop step, there is a layer remaining on the sidewalls of the original photoresist that effectively reduces the contact pattern CDs.124
Back End of Line Etch Processing and Ultra Low-k Dielectrics
As device scaling has meant the increase in device speeds, the BEOL has not been a significant limitation to circuit performance until recently. Significant performance effects have been seen at 90 and 65 nm high performance circuits due to the BEOL resistivity and capacitance increasing line capacitance coupling. At 45 nm some have suggested that this may actually be a more significant limitation than the transistor performance. The trend in the industry to compensate this effect has been to introduce low-k dielectric materials. But this is proving to be more difficult than expected and the copper line resistivity has been shown to also be a critical issue. The copper line resistivity is increasing more than predicted for a given scaling factor. There are several effects such as barrier metal thickness, as well as significant grain boundary and surface effects at these dimensions. So the BEOL metallization may become the new limitation for continuing on Moore's Law scaling roadmap.125 This scaling requirement for 45 nm requires smaller CD but, for lower copper line resistivity, this means deeper metal trench structures or higher aspect ratios. But as the line depth increase so does the line capacitance losses, which requires the use of even lower-k effective dielectric structures or integrations and to maintain this during processing. It also could result in the use of a thicker barrier to maintain step coverage or mandate the use of a different process to improve step coverage such as atomic layer deposition (ALD). As expected etch can have a direct impact on these parameters. 21.4.4.1
Challenge of Etching Ultra Low-k Dielectrics
The porous or porogen containing ULK materials under investigation for the 45 nm BEOL generally etch much faster than previous inter-layer dielectrics such as TEOS or carbon doped oxide (SiCOH). However, there a number of issues with these materials that impact our ability to etch. For example, these films' dielectric properties are very sensitive to subsequent processing such as CMP, cleaning and photoresist removal. A more dense oxide cap layer is therefore used to protect the bulk film. But as the structures are etched, the exposed sidewalls are subject to the damage. To prevent this sidewall damage, various modifications have been made to the processing such as the ashing and etching chemistries. Another approach is to help minimize the exposure of the low-k material. A dual hard mask integration approach helps since the trench pattern is etched in the top hard mask layer and the resist can be stripped without exposing the low-k to the plasma, usually a standard oxygen process. In this trench first sequence, the via pattern is then applied and etched into the second hard mask layer and through the low-k dielectric, stopping on the etch stop/diffusion barrier at the bottom. The via layer resist is removed while only the less critical via sidewalls are exposed. The trench features can now be etched through the top hard mask layer and the etch stop layer (ESL) opened to the copper. This improves feature alignment and reduces the exposure of the metal sidewalls to oxidizing chemistries that can significantly impact the dielectric properties. In addition, considerable investigation has been done into alternative photoresist removal processing and chemistries.126,127 Most of these rely on reducing chemistries such as NH3 or N2/H2, or on less oxidizing mixtures such as CO or CO2/O2. Photoresist removal can also can be done in situ or immediately following the dielectric etch in the same chamber, but there can be significant chamber wall effects depending on the etch chemistries and reactor design. If reactive polymers are deposited on the sidewalls, then these can be released during the photoresist removal step increasing the etch or damage to the low-k material sidewalls. 21.4.4.2
New Porous ULK Dielectrics
To reduce the emissivity of the dielectric, the pore density and size must be increase and this leads to obvious impact on the mechanical properties. This worsens the etch sidewall damage since more of the layer becomes carbon-like or porous. To help alleviate some of the mechanical and process issues with the porous dielectric films, a different low-k material is being developed where the porosity in not introduced until after the etch and metal deposition process steps. This is referred to as a "solid first" approach.128
The as deposited film contains clusters of a polymeric material that decompose at low temperature than the bulk film. So after CMP, metallization and dielectric deposition processing such as the cap layer or several metal layers, the layer is heated to above this temperature and the porogen decomposes leaving voids in the matrix dielectric layer. This reduces much of the mechanical issues since the porogen containing film is denser and has higher modulus. Also, the lack of pores reduces the diffusion of reactant species that can remove carbon within the layer or damage the layer during etch and resist removal. The dielectric etch performance is also improved since the film density results in better etch profile control. This approach has a number of processing advantages, but there are still many questions concerning the reliability due to high film stress that results from the significant shrinkage of the film during the porogen removal process. 21.4.4.3
Metal Line Resistivity
A significant line resistivity effect is due to the thickness of the diffusion barriers such as tantalum, tantalum nitride or TiN.129 Even though this is primarily a deposition process limitation, the side wall roughness and more importantly the profile shape following etch can be significant in the ability of given deposition process to provide continuous uniform barrier coverage. As mentioned before, there is often an oxide or cap layer used to protect the ULK material. With the high etch rates for the low-k dielectric and the possible residual chamber effects a significant undercut or notched profile can occur during etching and resist strip. This can be very problematic for deposition even ALD. Again LER and sidewall texture can contribute to part of the increasing line resistivity by requiring thicker barrier thicknesses to have the required reliability. Porosity of the ULK dielectric also contributes to this issue and some have even proposed a separate deposition to "seal" the pores to improve barrier coverage and limit metal diffusion. Lastly, the effects of surface scattering is only made worst for rough surfaces. 21.4.4.4
The Ultimate Low-k: Air
As the challenges increase to find a material that meets the dielectric properties and that can be processed while maintaining the required effective k value, many as the best approach consider a structure change. This is similar to high performance transistor where the integration may have to resort to using a novel structure instead of difference materials such as the structure illustrated in Figure 21.30. As previously mentioned, the BEOL interconnect may offer biggest challenges to meet the technology performance requirements at 45 nm and below. Even lower emissible dielectric material will probably be available but the integration of these into a more manufacturable process seems to offer un-surmountable difficulties. For most of the proposed air gap integrations there is actually a significant reduction in the challenges to the etch processing since these usually would reuse previous generation materials such as TEOS, low-k dielectrics or sacrificial organic layers (Figure 21.32). These have previously been extensively utilized in previous generations and the etch processing is well characterized and understood. In some proposals, organic layer can be used as the metal line layer such as the porogen material so the line etch is basically similar to the dry develop process used for similar multilayer resist processing. For most air gap structures, there remain several issues besides the inherent reliability of these structures including the etch and metallization process interactions of having unlanded vias on air spaces. Although this may seem to be a significant issue, in fact in practice, these may not actually be as critical. First, most of these can be mitigated by layout, sizing and the use of via etch processing that provide taper or smaller bottom CD's. In most processing, the effects of unlanded via structures have been observed and these effects are more significant in the porous low-k materials due to the higher etch rates. In misaligned test structures, deep very small voids are etched along the sides of metal lines, but in almost all analysis these do not form voiding of the subsequent metallization processing nor have via failures been reported for such features. In actual circuits layouts, there are other more significant effects of such misalignment such as resistance or shoring that require sufficient alignment and overlay control where
CoWP (a)
(b) Non-conformal dielectric
Airgap (c)
FIGURE 21.32 Schematic representation of air gap formation using non-conformal chemical vapor deposition (CVD) technique: (a) Once the metal layer is completed, (b) a self-aligned cap layer is deposited on the copper lines, (c) the dielectric is etched between the line (d) followed by a non-conformal CVD process to form air gap spaces.
this misalignment has not been a problem for full dielectric structures. But more data is needed for the air gap structure to determine the actual mechanisms and the possible impact on reliability and yield.
Nanotechnology—22 nm and Beyond
Device Roadmap Challenges
In the past several years, a number of investigators have predicted the end of the silicon era as we approached the threshold to nanotechnology. Even the definition of where nanotechnology begins is a topic within itself, but most agree that the 22 nm node is well at this technology. It is very risky to attempt to project the future, but that is more the case for semiconductor technology development trends, especially more than one generation out. If the 45–32 nm nodes will be the transitional phase with the introduction of some new materials and structures, there is little disagreement that the 22 nm node will be at the nanotechnology level and maybe at the limit of silicon technology.94,110,130,132–134 Since every physical limit of the conventional technology will be pushed if not exceeded, new structures and materials will be needed at almost every element to be able to build such structures, but it appears that silicon will still be the fundamental base for the technology. The devices will have to be scaled truly to the atomic level as illustrated in Figure 21.33 and Figure 21.34, and so the process technology must also start to perform at this level. A number of investigators have attempted to forecast the most likely path and, if we assume a normal 15 year Intellectual property (IP) development cycle,135 these projections should start to be a bit more focused on the most likely scenarios. These forecasts usually involve the transition from classical planar CMOS on bulk silicon substrate to planar on ultra thin silicon active region such as FDSOI. This will probably quickly migrate or will be introduced with high-k dielectrics and metal gates if the manufacturing issues are resolved in the next several years. The next performance boost will probably be similar devices but with multi-gates.136 These seem to be consistent with the ITRS roadmap and could be introduced later in the 45 or 32 nm nodes.1 The possible alternative to this migration is the FinFET structure as described earlier (Figure 21.33). It offers the advantages of both ultra-thin silicon and multigate performance. And because of the simpler technology, it can provide the needed performance but much sooner than the next level of scaled planar technology will likely be available. Nanowire transistor
G Lg
xide ried o
Double-gate Fin FET (Tsi = 2/3 Lg)
Omega Fin FET (Tsi = Lg)
Nanowire Fin FET (Tsi = 2Lg)
FIGURE 21.33 Evolution of FinFET device to nanowire structure. (Reprinted from Yang, F.-L., Lee, D.-H., Chen, H.-Y., Chang, C.-Y., Liu, S.-D., Huang, C.-C., Chung, T.-X. et al., IEEE Symposium on VLSI Technology, 196, 2004. With permission. Copyright 2004 IEEE.)
could then be the next evolutionary extension of the current FinFET structures and is projected to provide further enhanced device characteristics so that the extreme scaling (beyond the lithographic limit) may not be needed137,139 (Figure 21.34). Not only would this be a step function in the technology roadmap, but also most investigators now see this as the logical progression to continue the device scaling of a 45 nm FinFET that can be scaled to 22 nm nanowire transistors. The introduction of carbon nano-tube FET carbon-nanotube field-effect transistor (CNFET) could also use the same basic structure with the silicon nanowire active region being replaced with carbon tube, so yet further scaling to single electron quantum dot structures134,140–142 (Figure 21.35).
N+ Poly-Si gate
Buried oxide Lg = 5 nm (b)
Buried oxide
FIGURE 21.34 Transmission electron microscopy cross-sections of nanowire structure. (Reprinted from Yang, F.-L., Lee, D.-H., Chen, H.-Y., Chang, C.-Y., Liu, S.-D., Huang, C.-C., Chung, T.-X. et al., IEEE Symposium on VLSI Technology, 196, 2004. With permission. Copyright 2004 IEEE.)
Poly-Si gate
Source Substrate
Quantum dot Buried oxide
112700 3.0 K X300 K 100 nm
FIGURE 21.35 Extension of FinFET like structure to quantum dot device structure. (Reprinted from Zhuang, L., Guo, L., and Chou, S. Y., Appl. Phys. Lett., 72, 1205, 1998. With permission. Copyright 1998, American Institute of Physics.)
If many of the FEOL roadmap limits seem to be have been pushed out, the critical BEOL interconnect is just now being addressed - increasing copper line resistivity.143 Even at the 32 nm node, the increase in copper resistivity may actually limit circuit performance. There does not appear to be any obvious solution to the resistivity issue at 22 nm since ultra thin barrier, high aspect ratio, and design options will need to be pushed to their extreme to allow 32 nm to meet the technology requirements. The only possible migration will be in further reduction of the line-to-line capacitance. As previous discussed, low dielectric emissivity can significantly improve the resistance-capacitance product (RC) delay losses and air gap can approach k values close to 1.0.133 So as the resistivity continues to increase without much opportunity to reduce it, improving the interconnect losses at 22 nm must take advantage of the air gap structures. Besides the issues previously discussed for air gap structures, the requirement to attempt anything that will reduce resistance will likely drive the thickness of the lines up that will further strain the patterning requirements with increasing feature aspect ratios. Extending the previous materials discussions, there is in some ways even less uncertainty about the alternative materials for the 22 nm technology than for 45–32 nm; because for now, the scaling can only be accomplished with a FinFET type structure for the basic CMOS transistor. The materials needed to meet the device requirements will probably be developed at 45–32 nm for the FDSOI and other planar devices. For example, the FinFET devices are capable of meeting the 45 nm targets with polysilicon and silicon oxynitride but by the 32–22 nm nodes, these too will probably require high-k dielectrics and metal gate electrode materials. Since there are already feasibility demonstrations of device structures at the 22 nm scaling, there is a high probability that new technologies such as ALD can be scaled to this level.
Imaging Limitation and Etch Interactions
Beyond extending optical immersion lithography to the 32 nm node, an alternative approach for gate fabrication may be the use of a hard mask formed by a spacer process on a sacrificial material.138 This has some definite limitations and requires double patterning—one for the minimum gate CD and one for the contacts and larger features, i.e., anything greater than the minimum. As in the current lithography development thrust, LER becomes even more challenging for lithography and etches with w9 nm physical gate length and total gate roughness of 1 nm.1
Extension of Existing (45–32 nm) Etch Technology Node
As with the 45–32 nm technologies, the critical etch challenges will probably be the feature aspect ratio and selectivity requirements to be able to meet the scaling roadmap targets. With appropriate masking technique resolution at 22 nm does not appear to present any significant roadblocks but still a number of challenges. Unfortunately, the aspect ratio become even more difficult with a number of critical steps approaching or exceeding 4:1. Beside the contact etch ratio that will probably exceed 4:1, the BEOL copper metal resistivity is increasing as the line become smaller and this will drive the integration to have deeper metal trench structures as well.102 Even though 22 nm will use material processing characterized for previous generations such as high-k dielectrics and metal gates, the selectivity challenges are even more difficult since the layers become extremely thin. These will be even more difficult along with the probable use of 3D transistor structures may require a different approach—ALE. This is analogous to ALD now being developed or already introduced into standard CMOS technology. Atomic layer etching can be modified to provide etch conditions ranging from highly anisotropic to purely isotropic. For 3D structures such as the SON transistors previously discussed and nanowire structures, isotropic etch processes may be needed and these will require the same precision control of any anisotropic process144 (Figure 21.36). Primarily chemically driven selective etch processes may no longer provide the capability since in many cases the polymer level through which the etch chemistry reaction must proceed is thicker that the feature size. So like with ALD, the ALE reactant species must be adsorbed on the surface, and then energy is supplied to cause these molecules to react. So for each layer or cycle, the chemistry and reaction rate can be precisely controlled. Use of thermal energy such as with a heated substrate stage or blanket radiation such as in rapid thermal processor will result in isotropic etching. The use of a directional energy source such as ion bombardment, electron beam or collimate photon beam will result in very anisotropic process. Since many of the materials may have similar composition such as metal and their oxides, ALE does not need to have a chemical selectivity mechanism; but in principle, the desired number of atoms is removed per cycle. Even in those etch processes that do require quite the same level of control selectivity or do not lack the chemical etch selectivity properties, the 22 nm technology will still require significant improvements in process control. As discussed in an open panel forum at the American Vacuum Society Symposium 2003, industry process technology leaders expressed the need for a paradigm shift in equipment and process control—from one of controlling equipment parameters such as power, pressure, temperature to one of being able to adjust ion energies, into densities, ion species, etc. One technique that offers most of these is neutral beam etching. Similar to ion implantation where the beam properties can be precisely
FIGURE 21.36 Example of a 3D nanowire structure fabricated using isotropic etch. (Reprinted from Milanovic, V. and Doherty, L., In Proceedings of ASME International Mechanical Engineering Congress and Exposition (IMECE), 33392, 2002. With permission. Copyright 2002, ASME.)
p3 – 28 120 / 200
Resist Poly-Si
50 nm 10.0 kV
X100 K
FIGURE 21.37 Polysilicon profiles using Cl2/SF6 neutral beam etch. (Reprinted from Noda, S., Nishimori, H., Ida, T., Arikado, T., Ichiki, K., Ozaki, T., and Samukawa, S., J. Vac. Sci. Technol. A, 22, 1507, 2004. With permission. Copyright 2004, American Institute of Physics.)
determined, so does the large area ion beam provide similar controls but for the entire substrate to be able to maintain low process times. Although neutral ion beam may see limited introduction for 45–32 nm technologies, it is difficult to imagine that the current RIE technique will be extendable to the 22 nm level for most critical etch applications. S. Noda et al. have reported excellent results using neutral beam processing of polysilicon gate etch145 (Figure 21.37). One such early application of neutral beam processing has been the demonstration of photoresist strip on ULK porous dielectrics.146,147
Process and Equipment Requirements
It has been shown that generally new process equipment is needed about every other generation.131 This is true for deposition with the probable wide use of atomic level deposition at the 45–32 nm technologies for the deposition of high-k gate dielectrics and copper BEOL diffusion barriers. This equipment scenario will probably be the case for lithography and etch at the 22 nm node. For etch, the need to have increased selectivity and atomic level control will drive the introduction of ALE. This equipment could be the same used for deposition today with slight optimization for the chemistry and reaction mechanisms. In addition, current etch tools could also be easily modified to include the capability to cycle gas injection and ion bombard for an ALE process while maintaining the flexibility to run more tradition RIE conditions. However due to the very low etch rates, these ALE processes will probably be limited to very thin films where there is not a good chemical selectivity mechanism. For other processes with either every increasing aspect ratio such as contact etch and the thicker layer etching where ALE may not prove viable, the stringent process selectivity and feature definition requirements still must be achieved. These requirements will probably drive equipment designs to allow lower and selectable ion energies, and maybe the possibility of selecting the ion species and higher directionality. An example of a critical process is the FinFET fin and gate etches where the aspect ratio is increasing while the CD is rapidly scaling down. Also, the gate etch must be done over the topography of the fin structure as illustrated in Figure 21.38 and serves as another example of the process complexity tradeoff as a function of feature aspect ratio.133 As mentioned already, neutral beam etch seem to offer
Tsi Lgate
Tsi Fin height = ½ Wgate
I~Wgate/Lgate → lateral scaling
I~2 Fin height Lgate×Nfin → vertical dimension not litho limited
FIGURE 21.38
Comparison of planar device and FinFET aspect ratio and scaling requirements.
this level of ion level control. The basic design is simply an ICP source with an ion extraction grid or a high aspect ratio "neutralization" plate (Figure 21.39). There are number of ICP sources that can be readily modified to add this feature.
Challengers to Silicon beyond 22 nm
There is already intense research into the alternative materials for silicon; but of these, the carbon nanotubes is probably the most likely next material. There are a number of properties that exceed those of silicon such as resistivity, strength, etc., but the more important is that it appears to be compatible with
DC Pulse modulation On/Off = 50/50-100μ sec RF 13.56 MHz DC
+ − + − + − + − + − + − +− + − + − + − + − + − + − + − − + − + − + −
Top carbon plate Quartz tube Bottom carbon plate
RF 600 kHz
Neutral beam
Wafer Stage
FIGURE 21.39 Schematic diagram of an experimental neutral beam etch chamber. (Reprinted from Noda, S., Nishimori, H., Ida, T., Arikado, T., Ichiki, K., Ozaki, T., and Samukawa, S., J. Vac. Sci. Technol. A, 22, 1507, 2004. With permission. Copyright 2004, American Institute of Physics.)
silicon processing. For example, it could be used in the standard process as the active channel region for the transistor where the source-drain and gate element can be fabricated in silicon.148,149 Due to the low resistivity and mechanical stability, carbon nanotubes may also find applications in the BEOL such as via since these may facilitate the columnar growth.150,151 However, there is almost as intense effort ongoing with silicon structures that could extend similar nano-column or tube structures in silicon, so only at time in the future will there be an end of the roadmap for silicon etching.134,135,152
Modeling of Plasma Etching Processes
Plasma etching processes are physically and chemically complex phenomena, and are often difficult to thoroughly characterize experimentally. Considerable attention has therefore been paid to computational modeling of plasmas and etching processes in the last 15 years. Some aspects of plasma processes can now be reliably analyzed using commercially available software, while other areas remain topics of intense research. With growing complexity of plasma processing applications, introduction of new materials at an unprecedented pace, and structure dimensions approaching nanometer scale, it is imperative that modeling will play a strong role in design of future plasma processing tools and processes. A brief review of plasma models is included in this section. More details can be obtained in the cited references. Attention here will focus only on computational models. The importance of analytical models (e.g., Refs. 2 and 153) can however not be deemphasized as they remain invaluable tools for plasma tool design and engineering analysis. Computational plasma process models can generally be sub-divided into three categories: equipment models, feature scale models, and atomistic models. These models are often inter-coupled to analyze complicated problems but large disparity in time and spatial scales makes simultaneous simulation of all pertinent physical and chemical phenomena very challenging. Equipment models typically address gas flow in the plasma reactor, plasma generation, chemistry within the plasma, reactor electrodynamics, plasma interactions with driving circuits and sheath dynamics. These models address phenomena on relatively large spatial scales (cm) and moderate time scales (ns–ms). Feature scale models simulate etching and related surface phenomena within small structures. Analysis often relies on macro-variables (sticking coefficients, sputtering yields, etc.), to represent surface processes. Feature scale models address issues on small spatial scales (mm) and relatively long time scales (seconds). A new class of models utilizes molecular dynamics (MD) or ab-initio techniques to investigate etching relevant surface processes from first principles. These models address issues on very small spatial (nm) and small temporal (fs–ps) scales. Kinetic, fluid and hybrid techniques were all explored in the early days of multi-dimensional plasma reactor modeling. Kinetic models include particle-in-cell models154 which self-consistently track macroparticles and their interactions and models that attempt to directly solve the Boltzmann equation155 to determine important plasma properties. As these techniques are computationally expensive and it becomes progressively difficult to represent the complexity of actual plasma processes, these techniques are primarily used now for research or specialty applications. Fluid156 and hybrid157 techniques however have been explored in considerable detail and several commercial software158,159 based on these techniques are available. In fluid and hybrid plasma model, Maxwell equations are solved in conjunction with equations governing species mass, momentum, and energy balance to determine important plasma properties. Electrons generally drive etching relevant plasmas and have a broad energy distribution that strongly impacts their transport properties and plasma chemistry. Fluid and hybrid models either assume a Maxwellian electron energy distribution, solve Boltzmann equation to determine electron energy distribution or use Monte Carlo techniques. Fluid plasma models have been coupled to models of external driving circuitry,160 kinetic models that compute quantities not well captured by fluid models (e.g., ion and neutral energy and angular distribution at surfaces),161 and surface physics models.162 It is fair to state that plasma equipment modeling is a mature area and plasma reactor dynamics can be simulated with reasonable fidelity. Uncertainty with plasma chemistry5 (atomic and molecular processes,
heavy particle reactions) is often the only hurdle that hinders the use of plasma equipment models for an even broader set of applications. Plasma equipment models have been successfully applied to the modeling of capacitively coupled plasma etchers (single frequency, dual frequency,163 magnetized164), ICP sources,157 ECR,165 and helicon166 plasmas. Fair to adequate mechanisms exist for many of the commonly used plasma etching gases. Feature scale models have immensely grown in maturity in the last few years. Several techniques have been explored for feature scale modeling and they all remain equally important for problem solving. Broadly speaking, feature scale modeling has been done using Monte Carlo methods,167 string based methods168 and level set methods.169 In Monte Carlo models, surface and material underneath is represented using macro-particles. Plasma species, whose characteristics are either assumed or determined using plasma equipment simulations, are then bombarded on the material stack. A surface reaction mechanism is used to determine how the structure evolves in time. Monte Carlo simulators allow representation of detailed surface processes and can easily account for sub-surface processes. However, to overcome the statistical noise in the simulations, large number of particles often have to be used slowing down simulations considerably. In string based methods, the surface of the structure is represented using a set of inter-connected strings in 2D models (or patches in 3D simulations). Using fluxes of plasma species, impingent flux on the structure surface is determined. Fluxes on material surface are used in conjunction with a surface mechanism to determine how the strings or patches evolve in time. String based techniques are computationally fast and it is relatively straight-forward to implement most surface processes. Representation of sub-surface material and simultaneous etching and deposition is nonetheless a non-trivial task in string based models. Level set methods have been used for both etching and deposition modeling. The material is represented by a function, one of whose equipotential planes coincides with the structure surface. Simulation methodology is similar to string based models although the surface is evolved by solving a differential equation governing the function. Level set method is slower than string based technique but simulations are numerically more stable. Representation of sub-surface materials and simultaneous etching and deposition are however challenges level set methods share with string based models. Feature scale models have been applied to the modeling of a wide variety of plasma etching processes including polysilicon38 and photoresist28 etching, and SiO2170 and low-k171 dielectric etching. Molecular dynamics models have in recent years started playing a major role in unearthing the fundamentals of plasma etching. In the MD models, quantum mechanical interactions between atoms (both material and plasma based) are represented using pseudo-potentials that are either determined experimentally or using ab initio quantum mechanics models. These pseudo-potentials are used in classical mechanics models to simulation the dynamics on the material surface in contact with the plasma. Molecular dynamics models have been used to understand the formation of reactive layers on a variety of films, and the role that different ions and radicals play in plasma etching or surface passivation. These models have examined Cl2172 and fluorocarbon173 etching of Si, fluorine etch of SiO2174 and fluorocarbon etching of SiO2.175
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Equipment Reliability 22.1 22.2 22.3 22.4
Introduction ...................................................................... 22-1
Basic Definitions † Reliability of a Repairable System † Reliability Metrics
Reliability Metrics Calculations ....................................... 22-4 Applications of Reliability Metrics .................................. 22-5
Desired Values Values
Confidence Limits Calculations....................................... 22-6
Confidence Limit Calculations for Theoretical Values † Confidence Limit Calculations for Observed Values
Precise Use of the Reliability Metrics.............................. 22-7 Maintainability Metrics .................................................... 22-8 High-Level Equipment Performance Metrics................. 22-8
An Example of Reliability and High Level Performance Metrics Calculations ....................................................... 22-11
Availability (Uptime) and Utilization Metrics † Overall Equipment Efficiency † Cost of Ownership † Hierarchy of Equipment Performance Metrics
Given Values
SafeFab Solutions
Analytical/Theoretical Values
Metrics Calculations
Four Steps to Better Equipment Reliability ................. 22-12
Know Goals and Requirements † Design-In Reliability Build-In Reliability † Manage Reliability Growth
Reliability Testing............................................................ 22-20
Use of Equipment Reliability Discipline in Business Practices ........................................................................... 22-24 SEMI E10......................................................................... 22-25
Types of Reliability Tests † Generic Steps for Reliability Tests † Reliability Tests throughout the Equipment Program Life Cycle Phases
Benefits of Using SEMI E10
Key Elements of SEMI E10
References ....................................................................................... 22-27
Reliability has been widely used to measure equipment performance in military and commercial industry since the early 1940s. Since then, the importance of the reliability has grown at a phenomenal rate. Now, reliability is a key equipment characteristic that has significant influence over equipment production efficiency and cost of owning and operating a piece of equipment. In addition, better reliability leads to a 22-1
competitive advantage. In the semiconductor manufacturing equipment industry, reliability plays even greater role enabling semiconductor manufacturers to compete globally. Currently, some semiconductor manufacturers also track high-level metrics, such as overall equipment efficiency (OEE) or cost of ownership (CoO), for equipments in their factories. Reliability is a key element of such metrics. This chapter provides basic working knowledge of equipment reliability discipline, how to define, how to calculate reliability and related metrics, and their inter dependencies. Also, included are their application to semiconductor manufacturing operations and ways to improve them.
Basic Definitions
Equipment is defined as a combination of components, parts, assemblies, modules, accessories, and embedded software integrated to perform the intended functions. At least one component must fail to cause the equipment to fail to perform its intended functions. Most semiconductor manufacturing equipments are repairable systems. A repairable system is one, which after failing to perform at least one of its intended functions, can be restored to perform all of its intended functions by any method other than replacing the entire system. A repairable system can be restored by replacing, repairing, adjusting, or cleaning the appropriate component(s); and/or reloading embedded software. All the subject matter presented here refers to such repairable systems, either semiconductor manufacturing equipment or other repairable systems. 22.1.1.2
Equipment has many characteristics of interest to us, such as weight, volume, footprint, throughput rate, price, etc. One of the important characteristics is reliability as defined below. Reliability is a longevity measure of failure-free operation period of any equipment. It can be expressed in many different ways. One way is using the following formal definition. Reliability is the probability of performing intended functions continuously without a failure (stoppage or interruption) for a specified time under the stated operational conditions. Mathematically, it is written as:
RðtÞ Z Pr½T O t
ð22:1Þ
where t, specific time of interest; T, random variable; R(t), reliability at time t; Pr[], probability of. Example:
Rð1000 hÞ Z Pr½T O 1000 h Z 0:95
In this example, 95% of the equipment units should continue operations past 1000 h. Four key points of the above formal definition require further explanation. 22.1.1.2.1 Failure A failure is defined as any unscheduled event that changes the equipment to a condition, where it cannot perform one of its intended functions. Any part failure, out of adjustment or contaminated parts, software or process recipe problem, facility or utility supply malfunction, or human error could cause the failure. 22.1.1.2.2 Intended Functions Every piece of equipment has its intended functions, whether they are formally documented or not. However, a given reliability level applies to a given set of functions that the equipment was designed to accomplish. If the equipment is used for functions other than its intended design, the same reliability
level may not apply to these new functions. It is the manufacturer's responsibility to see that users understand equipment's intended functions and vice versa. 22.1.1.2.3 Specified Time The reliability level changes as the equipment ages. It is necessary to include equipment age in establishing a reliability level. Without inclusion of such a time element, any reliability level is ambiguous. Such situations can mislead a user about the specific reliability level. 22.1.1.2.4 Stated Operational Conditions Factors such as operating environment, operating stress level, operating speed, operator skill level, and maintenance procedures and policies can affect the reliability of any equipment. Therefore, a given reliability level applies to a specified set of the operational conditions. If the value of any factor varies from specified operational conditions, the reliability level may differ. Example: the reliability of a blower in a card cage, operating in its ambient environment at 60% of its rated power, will be 0.85 at 2 years after installation.
Reliability of a Repairable System
In a repairable system, the distribution of failure intervals between successive failures is of prime interest. If we assume that: 1. Each component failure is an independent renewal process, i.e., when a component fails, it is replaced by a new component and this does not affect any other components 2. The system is a series system with many independent components. Then, under very generic conditions, the system-level failure is a superimposed renewal process [1]. The time between two successive failures approximately follows an exponential distribution as shown below.
f ðtÞ Z eKðt=qÞ Z leKlt
where f(t), probability density function (PDF) at time t; q, mean life; l, failure rateZ1/mean life. Note that the failure rate is constant for exponential PDF. The reliability function for the exponential PDF is given by:
RðtÞ Z eKðt=qÞ Z eKlt
The exponential distribution is one of the most popular, simple, and widely used PDF in reliability discipline. This approximation makes reliability analysis of a repairable system very easy. We need to know only one parameter (either mean time between failures (MTBF) or failure rate l) of the distribution to be able to perform system-level reliability analyses.
Reliability Metrics
The reliability metrics are various terms used to quantify the numerical value of reliability levels. In semiconductor manufacturing industry, we use neither reliability R(t) nor failure rate (l) to measure level of equipment reliability. Instead, we use metrics based on mean life. These metrics consist of at least four words, as shown in Figure 22.1. Two of them, MEAN and BETWEEN, are mandatory. Other words relate to the measures of life and events. Using the algorithm given in Figure 22.1, we can define metrics appropriate for any situation. Take the word MEAN, select a word for measure of life; take the word BETWEEN, and select the desired event.
Life-units
Events Failures
Wafers Cycles
Down events
Maintenance action
YYYYYY
Reliability metrics algorithm.
Examples 1. Mean time between failures 2. Mean cycles between unscheduled maintenance 3. Mean wafers between failures. These metrics are widely used to track reliability of semiconductor manufacturing equipment and are recommended by the Semiconductor Equipment Manufacturing International (SEMI), an association of semiconductor manufacturing equipment suppliers, in SEMI Specification E10-0304E for definition and measurement of equipment reliability, availability, and maintainability (RAM) [2].
Reliability Metrics Calculations
To calculate the numerical value of equipment reliability metrics, we need to know two basic elements of the reliability discipline, (a) number of events of interest that stops equipment from performing its intended function(s) in a given life period, and (b) amount of life-units the equipment was in operational condition during the same period. Use the following equation to calculate the desired metric.
Reliability metric Z
Operational life period Number of events during the same operational life period
As shown in Figure 22.1, semiconductor manufacturing events are categorized as failures, down events, scheduled maintenance or unscheduled maintenance. Operational life period may be expressed in calendar time, productive time, number of cycles, or number of wafer processed. Based on these variations, some popular reliability metrics for semiconductor manufacturing equipment are given by:
MeanðproductiveÞ time between failures ðMTBFp Þ Z
Productive time Number of failures that occur during productive time
Mean cycles between failures ðMCBFÞ Z
Total equipment cycles Number of failures
ð22:6Þ ð22:7Þ
The above formulae also apply to any measure of life by replacing "cycles" with the desired measures. For example,
Mean wafers between failures ðMWBFÞ Z
Number of wafers processed Number of failures
Section 22.8 contains an example of calculations for the above metrics.
Applications of Reliability Metrics
Applications of reliability metrics are terms that originate from the reliability related activities and they are used with appropriate metrics. For example, reliability goal originates from a goal-setting activity. Goal is an application of any reliability metric, e.g., goal MTBF. The applications of these metrics can be divided into the following three categories, depending upon the origin of the activities they represent: 1. Desired values 2. Analytical/theoretical values 3. Observed values.
Desired Values
In this category, the value of metric levels originates from the activities that deal with desires of equipment manufacturers and users. For example: 1. The MTBF goals are what a manufacturer (or a user) wants his equipment to perform. Therefore, goal applications belong to the Desired Value category. When system-level goals or requirements are broken into department level goals or requirements, based on some logical justification, they generate the applications known as allocation, budgeting, or apportionment, which also belong to the Desired Value category. System-level reliability goals, allocated to subsystem and component, and corresponding operating environments are part of the respective design specifications for reliability. Therefore, design specification is also an application of the reliability metrics and falls in this category.
In this category of applications, the value of metric levels originates from appropriate theoretical activities, such as modeling, part count calculation, and stress analysis. Following are two typical examples of the Analytical/Theoretical Values applications: 1. Inherent reliability. The values are derived from design assessment, assuming benign environments and no error in design, manufacturing, and operation. The inherent reliability is the best achievable level. 2. Expected reliability. The values are based on theoretical calculations using theoretical or observed reliability level of the parts used in the equipment.
Observed Values
This category represents situations in which the metrics level is established based on actual in-house tests, field tests, or field operations of the equipment. The following are three typical examples: 1. Observed values. The values are derived from actual in-house tests, field tests, or field operations. These values are not altered or adjusted. 2. Assessed/Adjusted values. When observed values are adjusted to account for non-relevant failures (such as facility problems or out-of-spec consumable), they become assessed/adjusted values. 3. Confidence limit values. These values are the observed values adjusted to account for number of failures observed as described in Section 22.4. Figure 22.2 below shows the most commonly used terms for reliability metrics and their applications. The reliability metrics can be converted from one category to another. For example, if we know MTBF, we can convert it to failures per 1000 h. Applications of the metrics can neither be converted from one to another nor mixed. However, they can be compared (for example, goal value vs. observed values).
Confidence Limits Calculations
When we deal with reliability metrics, either analytical or observed, we always face a question, how much confidence do we have in the result. It varies depending upon the type of theoretical calculations made (to derive theoretical values) or number of failures observed and amount of productive time (or other measures of life) contained within the observed period. The confidence is expressed by calculating confidence limits of the calculated or observed values. Generally we are interested in lower confidence limit. Therefore, the calculation methods shown below show lower limit calculations only. Similar methodology is used to calculate upper confidence limits.
Reliability terms Reliability metrics Probabilistic
Mean life
MWBF
F/106 h
% Failed
UM's/106 Cycles
% Uptime
MTBF Pr [T >1000 h] = 0.95 Pr [S] = 0.80
Goals Requirements Design specifications Allocations Budget Apportionment Warranty
Calculated Inherent Assessed Predicted Expected
Observed Assessed Field value
Summary of reliability metrics and their applications.
Confidence Limit Calculations for Theoretical Values
To calculate the confidence limit, we must have an underlying probability distribution for the calculated values. The underlying distribution depends upon the distribution of the MTBF or other values of the parts used in the calculations. Applying a law of large numbers, this distribution could be a normal distribution with a mean of the calculated values (m), for the reliability metric under consideration, and their standard deviation (s). In such cases, use the formulae given in Table 22.1 to calculate the lower confidence limit. For example, if m and s of the calculated MTBF values are 500 and 100 h respective, then
80% lower confidence limit for calculated MTBF Z 500K0:842 !100 Z 415:8 h:
Confidence Limit Calculations for Observed Values
Formulae given in Section 22.2 for reliability metrics provide single value estimates for the observed performance. The lower confidence limit for any observed reliability metric (MTBFp, MWBF, MCBF, etc.,) depends upon number of failures observed and amount of productive time (or other measures of life) contained within the observed period. It is calculated using the following formula.
P% lower confidence limit for the observed metrics Z ðobserved valueÞ !ðappropriate factor for the confidence levelÞ
ð22:10Þ
For the semiconductor equipment industry, any value between 80 and 95% confidence levels is an accepted norm for reliability work. See Table 22.2 for the multiplier factor values at 80, 90, and 95% confidence levels [2]. Section 22.8 contains an example of lower confidence limit calculations.
Precise Use of the Reliability Metrics
We need the following items to fully and precisely define the reliability level of a real-life situation. 1. 2. 3. 4. 5. 6. 7. 8.
Appropriate application (e.g., goal) Appropriate reliability metric (e.g., MTBF) Appropriate numerical value (e.g., 5000) Appropriate unit for the metric (e.g., hours) Appropriate set of intended functions (e.g., metal etch process) Age of the equipment when the metric and value apply (e.g., two months after installation) Appropriate set of operational conditions (e.g., clean room environment) Appropriate confidence level (e.g., 80%) for confidence limit values.
For examples: 1. Goal MTBF is 5000 h, 2 months after installation, when used as metal etcher in clean room environment. 2. Part count calculations for poly etcher model E3000 shows inherent failure rate of 2.00 failures per 1000 h (MTBFZ500 h) under the assumptions listed (needs to have a list of all assumptions used TABLE 22.1
Formulae for Calculating Lower Confidence Limit of Theoretical Values
Confidence Limit 70% Lower confidence 80% Lower confidence 90% Lower confidence 95% Lower confidence
Formula Used limit limit limit limit
mK0.525s mK0.842s mK1.282s mK1.645s
TABLE 22.2
Multiplier Factors for the Lower Confidence Limit Calculations
Number of Failures 1 2 3 4 5 10 15 20 30
80% Confidence
in the calculations, such as operating conditions, part functions, etc.). Assuming sZ100, 80% lower confidence limit for the calculated MTBFZ415.8 h. 3. Observed MCBFZ20,000 cycles. When the facility related failures are discounted, the adjusted MCBFZ30,000 cycles. Ninety percent lower confidence limit MCBFZ21,030 cycles (based on three equipment failures). Equipment is 6-month old and used as an oxide etcher.
Maintainability Metrics
There is no direct relationship between reliability and maintainability. Reliability deals with the operational life longevity and failures of equipment, while maintainability deals with restoring the equipment operation and the time it takes to restore it. However, both disciplines are complementary; both support high-level equipment performance metrics described in Section 22.7. Formally, maintainability is the probability that the equipment will be restored to a specific operational condition (able to perform its all intended functions) within a specified period of time, when the maintenance is performed by personnel having specified skill levels and using prescribed procedures, resources, and tools. Maintenance can be either unscheduled or scheduled. One of the most popular measures of maintainability is mean time to repair mean time to repair (MTTR), given by:
Mean time to repair ðMTTRÞ Z
Total repair time Number of repair events
Repair time includes diagnosis, corrective actions, and verification tests, but not maintenance delays.
High-Level Equipment Performance Metrics
Recently, some semiconductor manufacturing equipment users have started using high-level equipment performance metrics to make equipment purchase decisions and improve equipment performance. In addition, these high-level equipment performance metrics are becoming increasingly important to compete in the global market because they satisfy customer's reliability requirements in an optimum manner. Equipment reliability is the key element of these high-level metrics. The proper level of reliability is the one that yields the optimal value of the high-level metric being considered. Three most widely used high-level equipment performance metrics in semiconductor manufacturing are: 1. Availability (Uptime) and utilization 2. Overall equipment efficiency 3. Cost of ownership.
Availability (Uptime) and Utilization Metrics
Availability is a joint measure of reliability and maintainability. It is defined as the probability that equipment will be in a condition to perform its intended functions when required. Percentage uptime is one of the most widely used metrics for availability in semiconductor manufacturing. Since equipment down time can be attributed to either the equipment, equipment supplier, or the equipment users, the uptime calculations vary accordingly. The following three kinds of uptime calculation are used in semiconductor manufacturing: (a) equipment dependent, (b) supplier dependent, and (c) operational. Equipment dependent uptime includes effect of down time caused by scheduled and unscheduled maintenance inherent with the equipment (design) and it is given by:
Equipment dependent uptime ð%Þ Z
Equipment uptime !100 ðEquipment uptime C DTE Þ
where DTEZEquipment dependent down timesZ(unscheduled repair timeCunscheduled and scheduled time to change consumables and chemicalsCproduct test timeCpreventive maintenance time). Equipment uptime includes productive, engineering, and standby times. It does not include nonscheduled time such as holidays, shutdowns, non-working shifts, etc. [2]. Supplier-dependent uptime includes effects of all equipment dependent down times (DTE) and maintenance delays caused by the equipment supplier. It is given by:
Supplier-dependent uptime ð%Þ Z
Equipment uptime !100 ðEquipment uptime C DTE C supplier caused maintenance delaysÞ
Operational uptime includes effects of all down time caused by the scheduled and unscheduled maintenance inherent with the equipment, maintenance delays caused by the equipment supplier and user, and any other down time caused by the equipment user (such as facility related down time). It is given by:
Operational uptime ð%Þ Z
Equipment uptime !100 ðEquipment uptime C Equipment down timeÞ
The above uptime formulae do not include non-scheduled time, such as vacation, holidays, shutdowns, etc. Total utilization includes all time when the equipment is utilized productively. It measures the overall asset efficiency and is given by:
Total utilization ð%Þ Z
Productive time !100 Total time
Overall Equipment Efficiency
Overall equipment efficiency is the most recent high-level equipment performance metric. It was developed as an equipment effectiveness metric in Japan to measure the effectiveness of a manufacturing technique called total productive maintenance (TPM). Originally, it was called overall equipment effectiveness. Semiconductor Equipment Manufacturing International Metric Committee changed it to overall equipment effectiveness [3]. Semiconductor Equipment Manufacturing International and the American Institute of Total Productive Maintenance (AITPM) are currently the major sponsor of the OEE metric in the U.S.A. Overall equipment efficiency is an all-inclusive metric of equipment productivity, i.e., it is based on reliability (MTBF), maintainability (MTTR), utilization (availability), throughput, and yield. All the above factors are grouped into the following three submetrics of equipment efficiency.
1. Availability 2. Performance efficiency 3. Rate of quality. The three submetrics and OEE are mathematically related as follows:
OEE ð%Þ Z Availability !Performance Efficiency !Rate of Quality !100
Now let us look at each OEE sub-metric in more detail. 22.7.2.1
We have already defined availability in Section 22.7.2. We can use any uptime metric in this equation depending upon which OEE we are calculating. For example, equipment-dependent OEE calculations use equipment-dependent uptime and so forth. 22.7.2.2
Performance Efficiency
The performance efficiency is based on losses incurred from idling, minor stops, and equipment speed losses. It is given by:
Performance efficiency Z
Theoretical CT !actual PPH Actual CT !theoretical PPH
where CT, cycle time; PPH, throughput rate in parts (units) per hour. 22.7.2.3
Quality Rate
The quality rate is a measure of output quality and is given by:
Quality rate Z
Total part produceKnumber of rejects Total parts produced
where rejects are defined as any produced part that does not meet the production criteria. 22.7.2.4
Simple OEE
There is a simple and quick way to calculate OEE without going into elaborate calculations of the above three sub-metrics.
Simple OEE ð%Þ Z
ðNumber of good units produced in t calendar hoursÞ !100 ðt !theoretical PPHÞ
Note that this value gives only rough estimate for the OEE. It does not give any indication of improvement activities direction. There are many other ways to calculate OEE depending upon the use of the measured values. See Ref. [3] for some of the most popular ways to calculate OEE for semiconductor industry.
Availability and OEE are the most widely used high-level metrics, but they have the following shortcomings. They do not include: 1. 2. 3. 4. 5. 6.
Acquisition and operational cost Effect of the production volume Product scrap loss because of poor quality output Consumable cost Waste disposal cost Taxes, insurance, and interest expenses.
To overcome the above shortcomings, SEMATECH developed a CoO model [4], which calculates the true CoO per good unit produced in a given time period, usually a calendar year. The CoO depends upon the equipment acquisition cost, equipment reliability, equipment maintenance and operational costs, production throughput rate, throughput yield, and equipment utilization. The basic CoO is given by the following equation.
CoO per unit Z
FC C OC C YLC P !THP !U !Y
where Fixed costs (FC). The FC are typically determined from a variety of items such as: purchase price, taxes and duties, transportation costs, installation cost, start-up cost, and training cost. It also depends upon allowable depreciation schedule and the length of the time period under consideration. Operating costs (OC). Operating costs for a piece of equipment are consumable, material, maintenance and repair, parts, waste disposal, and operators for the time period under consideration. Yield loss costs (YLC). Yield loss costs are those associated with lost production units that are directly attributable to equipment performance during the time period under consideration. Time period (P). Time period under consideration, usually a calendar year expressed in hours. Throughout rate (THP). Throughput rate is the actual average (for the time period under consideration) production rate of the equipment, expressed in parts per hour. Utilization (U). As defined in Section 22.8.1, expressed in fraction. Throughput yield (Y). Throughput yield also known as quality rate, is the fraction of good units produced. It is determined by
Total units producedKDefective units produced Total units produced
Table 22.3 contains an example of a simple CoO calculation. See [4] for more elaborate CoO calculations.
Hierarchy of Equipment Performance Metrics
Figure 22.3 depicts the hierarchy of equipment performance metrics. As shown in the figure, when we add time dimension to quality and safety, it becomes reliability. Reliability and maintainability jointly make up availability. When production speed efficiency and production defect rate are combined with availability, they become OEE. Acquisition and operational cost make up life cycle cost (LCC) See Ref. [1] for detailed description of LCC. When scrap, waste, consumables, tax, and insurance cost are added to LCC and the total is normalized by the production volume, it becomes CoO.
22.8 An Example of Reliability and High Level Performance Metrics Calculations 22.8.1
Assume that the following values are given for the reliability and other performance metrics calculations. Theoretical throughputZ50 wafer per hour Productive timeZ1200 h Observed throughputZ40 wafer per hour Number of defective wafersZ105 Number of failuresZ3 Total unscheduled down timeZ20 h (including supplier maintenance delay timeZ5 h and repair timeZ15 h)
A Typical Simple Cost of Ownership (CoO) Calculations CoO Input Data
Equipment acquisition costZ$1,000,000 Throughput rateZ20 units/h Operation costZ$800,000/year in 2004 Labor rateZ$50/h in 2004 Mean time between failure (MTBF)Z200 h UtilizationZ75%
Equipment lifeZ5 years, straight line depreciation Throughput yieldZ0.98 Part costZ$50,000/year in 2004 Pre ventive Maintenance timeZ10 h/month Mean time to repair (MTTR)Z2 h Inflation rateZ4% per year CoO Calculations Year
Cost factors Depreciation ($) Operational cost ($) Repair and maintenance cost ($) Yield loss ($) Total cost ($) Good unit produced CoO per unit ($)
200,000 800,000 66,320 250,000 1,116,320 128,772 8.67
2007 200,000 899,891 74,601 281,216 1,255,708 128,772 9.75
PM timeZ50 h Facility down timeZ8 h No operator standby timeZ2 h Non-schedule (holiday) timeZ24 h.
The following equipment performance metrics are calculated based on the above values. Observed mean productive time between failures (MTBFp)Z(1200)/3Z400 h Observed mean wafers between failures (MWBF)Z(1200!40)/3Z16,000 wafers Eighty percent lower confidence limitZ400!0.701Z280.4 h for MTBFp Eighty percent lower confidence limitZ16,000!0.701Z11,216 wafers for MWBF Observed mean time to repair (MTTR)Z(20K5)/3Z5 h Equipment uptimeZ1200C2Z1202 h Equipment dependent down times (DTE)Z(20K5)C50Z65 h Equipment dependent uptime (%)Z(1202)!100/(1202C65)Z94.87% Supplier dependent uptime (%)Z(1202)!100/(1202C65C5)Z94.49% Operational uptime (%)Z(1202)!100/(1202C65C5C8)Z93.90% Total utilization (%)Z(1200)!100/(1202C65C5C8C24)Z92.02% Simple OEE (%)Z(1200!40K105)!100/((1202C65C5C8C24)!50)Z73.46%.
Four Steps to Better Equipment Reliability
Four basic steps to better equipment reliability are: 1. 2. 3. 4.
Know goals and requirements Design-in reliability Built-in reliability Manage reliability growth during a. Reliability tests b. Field operations.
2008 200,000 935,887 77,585 292,465 1,305,937 128,772 10.14
Cost of ownership (CoO)
Production volume
Scrap cost
Waste costs
Life cycle cost (LCC)
Overall equipment efficiency (OEE)
Acquisition cost
Production speed efficiency
Quality/defect rate
Availability (uptime)
Maintainability (MTTR and PM time)
Reliability (MTBF)
Consumable taxes, insurance and interest costs
Hierarchy of high-level equipment performance metrics.
All reliability improvement activities belong to one of these steps.
Know Goals and Requirements
If what is required is unknown, then, it probably will not be achieved. Therefore, the first step to better reliability is to know the reliability goals and requirements, whether you are an equipment manufacturer or a user. If you are an equipment manufacturer (supplier), you need to understand the exact reliability requirements of your customer 1. Be aware of the reliability level of your competitor's product 2. Know what reliability level is required in the market place. Considering the above inputs, set reliability goals for the equipment line at the beginning of each equipment program. If you are a customer, then it is your responsibility to make sure that equipment suppliers know your exact requirements. In either case, the reliability goals or requirements must include, at minimum, the items shown in Table 22.4.
Goal Allocation
Once the system level goals are known, the equipment manufacturer must break down the equipment and system-level goals into "bite-size" goals for sub-systems, modules, and components. This makes it relatively easy for subsystem, module, or component engineers to achieve their respective product goals. 1. The process of breaking down the equipment and system-level goals into the next levels of subgoals, based on some logical justification, is called apportionment, budgeting, or allocation. This process is just like breaking down division-level budgets into department-level budgets. One widely used method is known as Advisory Group on Reliability of Electronic Equipment (AGREE) allocation method. In this method, appropriate weight factors, based on the complexity and criticality of the components are used in the calculations as shown below.
MTBFi Z MTBFs
h X iZ1
Wi =Wi
where MTBFi, goal MTBF of the ith component; MTBFs, system level MTBF goal; Wi, weighting factor for ith component based on its complexity (1Zsimple, 10Zmost complex, sometime the weight factors are based on the inherent failure rate). An example of AGREE method calculations If a system consists of five modules, the system level MTBFS goalZ500 h, and the weight factors for each module are as follows: For Module 1, W1Z6 For Module 2, W2Z10 For Module 3, W3Z3, For Module 4, W4Z6 For Module 5, W5Z5 Then: MTBF goal for Module 1 (MTBF1)Z500!(30/6)Z500!5Z2500 h MTBF goal for Module 2 (MTBF2)Z500!(30/10)Z500!3Z1500 h MTBF goal for Module 3 (MTBF3)Z500!(30/3)Z500!10Z5000 h MTBF goal or Module 4 (MTBF4)Z500!(30/6)Z500!5Z2500 h MTBF goal for Module 5 (MTBF5)Z500!(30/5)Z500!6Z3000 h. TABLE 22.4
Must Include Items in the Reliability Requirements/Goals Item
Reliability metric and level that equipment should attain Time factor, age at which equipment should attain the reliability level Operational conditions: Temperature Humidity Duty cycle Throughput rate Process to be used Operator skill level PM policies to be followed Shipping mode Installation procedure Confidence level for attaining the reliability level Acceptable evidences for attaining the required reliability level
Examples Mean time between failure (MTBF)Z700 h Four months after installation Temperature range: 708F–758F Humidity range: 40%–45% Relative Humidity 12 h/day 15 wafers/h High density plasma etch Grade 12 or equivalent Monthly PM policy Air-cushioned truck Install by a special installation team 80% confidence that observed MTBF is equal or greater than the goal value Attaining the reliability level based on the field data, four months after installation
Design-In Reliability
This is the most important and elaborate step to achieve better equipment reliability. Design-in reliability is a process in which reliability improvement goals are considered concurrently with other technical aspects at every activity of the design phase. Figure 22.4 depicts the design-in reliability process. Six major blocks of the process are 1. 2. 3. 4.
Use proper parts properly Use proper design techniques Design to withstand effect of external factors Avoid failures through scheduled maintenance
Know reliability requirements
STEP 2-A
Use proper parts correctly - Selection and specification control - Derating
Design to withstand effect of external factors - Environmental - Human factors - Software factors
STEP 2-D
Avoid failures through scheduled maintenance - Periodic preventive maintenance - Predictive maintenance
Meet reliability goals?
Go to next phase
Process of design-in reliability.
STEP 2-C
STEP 2-F
STEP 2-E
Use proper design techniques - Design simplifications - Redundancy - Protective techniques
Modeling and design assessment
STEP 2-B
5. Hold design reviews 6. Assess reliability of the design using modeling techniques. Reference [5] contains a detailed description of each block. The following is a brief summary. 22.9.2.1
Use Proper Parts Properly
Use of the proper parts properly makes up the most crucial block of the design-in reliability process. It consists of the following activities: Part selection. Before selecting any part and its supplier, determine the part type needed to perform the required functions and the environment in which it is expected to operate. The general rule for part selection is that, whenever possible, the designer should strive to use proven parts in the design and select a supplier who has proved historically to meet or exceed the part reliability requirements. Part specification. For each reliability sensitive part, its procurement specification should include: 1. Details of the intended application(s) 2. Reliability requirement level for the intended application(s) 3. Part screening procedure 4. Part qualification procedure 5. Acceptable evidences for attaining the required reliability level Part derating. Once the part is selected, perform an analysis to compare the expected stress level for the intended applications with those of the part's rated (capacity) stress level. A technique known as derating is used to improve design reliability. In this technique, a part is selected, so that it will operate at less severe stress than it is rated as capable of operating. For example, if the expected power level is 10 W for a device, select parts that are rated for significantly higher than 10 W power. Use the appropriate derating factors for various electronics components given in Table 22.5. 22.9.2.2
Use Proper Design Techniques
Use of proper design techniques is another most crucial block of the design-in reliability process. It consists of the following activities: Design simplification. Anything that can be done to reduce the complexity of the design will, as a general rule, improve reliability. If a part is not required, eliminate it from the design. Wherever possible, reduce the number of parts through combining functions. Redundancy. This is one of the most popular methods in design to achieve the needed level of reliability. Redundancy is the provision of using more than one part to accomplishing a given function so that all parts must fail before causing a system failure. Redundancy, therefore, permits a system to operate even though some parts have failed, thus increasing system reliability. For example, if we have a simple system consisting of two identical redundant (parallel) parts, the system MTBF will be 1.5 times that of the individual part MTBF. Protective Technique. This design technique includes a means to prevent a failed part or malfunction from causing further damage to other parts. The following are some of the popular protective techniques used in equipment designs: 1. Fuses or circuit breakers to sense excessive current drain and to cut off power to prevent further damage 2. Thermostats to sense over-temperature conditions and shut down the part or system operation until the temperature returns to normal 3. Mechanical stops to prevent mechanical parts from traveling beyond their limits 4. Pressure regulators and accumulators to prevents pressure surges
Equipment Reliability TABLE 22.5
Derating Factors for Commonly Used Components Component
Capacitors, general Capacitors, ceramic Capacitors, supermetallized, plastic film, any tantalum Capacitors, glass dielectric, fixed mica Connectors Quartz crystals Diodes EMI and RFI filters Fuses Integrated circuits (all kinds) Resistors (all kinds) Thermistors Relays and switches
Transistors Wires and cables
Stress Category
Derating Factor
Voltage Voltage Voltage temperature Voltage temperature Current Voltage Temperature Power Voltage Current Voltage Current Current
0.5 0.5 at !858C 0.3 at !1258C 0.5 at !858C Less than 858C 0.5 at !858C Less than 858C 0.5 0.5 Less than 1258C 0.25 0.75 0.5 0.5 0.75 0.7 at !258C 0.5 at O1258C 0.7 0.8 0.75 0.8 0.5 0.5 0.75 for resistive load 0.4 for inductive load 0.2 for motors 0.1 for filament 0.75 Less than 1058C 0.6
Voltage Current Power Voltage Power Power Current
Breakdown voltage Junction temperature Current
5. Self-checking circuits (and software) to sense abnormal conditions and make necessary adjustments/compensations to restore normal conditions 6. Interlock to prevent inadvertent operations 7. Homing sequence for computer shut-downs 22.9.2.3
Design to Withstand Effect of External Factors
The operating environment is neither forgiving nor understanding. It methodically surrounds and affects every part of a system. If a part cannot sustain the effects of its environment, then reliability suffers. First, the equipment manufacturer must understand the operating environment and its potential effects. Then, he must select designs and materials that are able to withstand these effects or he must provide methods to alter and control environmental conditions within acceptable limits. Equipment design engineers must consider means to withstand the following external factors affecting reliability: 1. 2. 3. 4. 5. 6. 7. 8. 9.
Heat generation causing high temperatures Shock and vibration Moisture High vacuum Explosion Electromagnetic compatibility Human use Utilities supply abnormalities (power, water, gases, chemicals, etc.) Software design.
Avoid Failures through Scheduled Maintenance
One way to improve reliability is to minimize the number of failures that occur during operation. This can be achieved in two ways: 1. Select parts that fail less frequently 2. Replace a part before its expected failure time. The latter method is known as scheduled maintenance (SM). This technique is used when it is not feasible to find a part that fails less frequently. If such a situation is properly comprehended during the design phase, it can be avoided through one of the following SM techniques. Periodic preventive maintenance. This is a fixed-period-driven maintenance procedure in which parts that are partially worn out, aged, out-of-adjustment, or contaminated, are replaced, adjusted, or cleaned before they are expected to fail. This way, system failures are forestalled during the system operations thus reducing the average failure rate. Predictive maintenance. This is a condition-driven scheduled preventive maintenance program. Instead of relying on a fixed period of life units to schedule maintenance activities, predictive maintenance uses direct monitoring of appropriate indicators to determine the proper time to perform the required maintenance activities. 22.9.2.5
Design reviews are an essential element of the design-in reliability process. The main purposes of a design review are to assure that: 1. 2. 3. 4.
Customer requirements are satisfied The design has been studied to identify possible problems Alternatives have been considered before selecting a design All necessary improvements are based on cost trade-off studies.
Conduct design reviews on a regular basis from the initial design feasibility study through the pilot production phase. An effective design review team should have representation from each functional area involved in developing the equipment. 22.9.2.6
Reliability Assessment of the Design
Once the equipment design starts taking shape, it must be assessed to determine its reliability level and the system level effect of failure rate of each part. Modeling techniques determine analytical value of the reliability level. Failure mode and effects analysis (FMEA) technique determines the system level effect of part failures. Failure mode and effects analysis also identifies improvement opportunities. There are many commercially available software packages that perform modeling and FMEA. 22.9.2.7
Design Verification Tests
Once design is firmed, conduct design verification test to determine the reliability level under the expected use conditions (see Section 22.10). If the observed reliability level is lower than the expected, identify areas for improvement and implement corrective actions (design changes).
Build-In Reliability
Building-in reliability is a process that assures all parts, subsystems, modules that are made and assembled according to engineering drawings and specifications without degrading the designed reliability or introducing new failure modes. Important steps of this process are: Assembly instructions. Prepare detailed instructions for each assembly step. These instructions should include proper parts, materials, step-by-step assembly procedures, tools, limitations, inspection procedures, etc.
Training. To minimize assembly errors, it is essential that every assembly operator be trained in basic assembly methods and in all the assembly operations assigned to him or her Burned-in. All parts and the system itself should be properly and adequately burned-in, debugged, or stress-screened before shipment. Product reliability acceptance test (PRAT). Conduct a PRAT on randomly selected units before shipping to assure the reliability level of the product line as it is shipped. Packaging and shipping. Equipment must be packed properly for the intended shipping mode. Select shipping mode that does not impart any undue stress on the equipment.
Manage Reliability Growth
Effectively managing reliability growth opportunities is a continuous improvement process. Equipment manufacturers learn from in-house reliability tests (see Section 22.10) or actual field experience. All problems observed during the reliability tests (either in-house or customers place) are documented and given to a central body (such as Failure Review Board (FRB)) for further analysis and disposition. If required, corrective actions are developed and implemented. Similarly, during field operations, customer works with the equipment supplier to collect, record, and analyze equipment failures, both hardware and software. They capture predetermined types of data about all problems observed with a particular equipment line and submit the data to the supplier. The FRB, at the supplier's site, analyzes the failures. The resulting analysis identifies corrective actions that should be developed, verified, and implemented to prevent failures from recurring. A popular system named "Failure Reporting and Corrective Action System" (FRACAS) is used to manage this process. As shown in Figure 22.5, FRACAS is a closed-loop feedback communication channel to report, analyze, and remove failure causes. Now let us look at three key elements of FRACAS in more detail. 22.9.4.1
Failure Data Reporting
All the failures, observed either during in-house test or at customer's site, must be recorded so all relevant and necessary data is captured in a systematic manner. A simple, easy-to-use form that is tailored to the respective equipment line should be used to record and report failure data. (Figure 22.6 depicts a typical failure reporting form). If the data volume justifies the cost of administering FRACAS, the data form can be computerized to communicate failure data. Internet and electronic mail are the most recent ways to report failure data. 22.9.4.2
Failure Review Board
The FRB is a multifunctional self-managed team that reviews, facilitates, and administers failure analysis. It also participates in assigning, developing, verifying, and implementing the resulting corrective actions. To do this job effectively, all the functional departments involved in the product line must participate on the FRB. Also FRB members must be empowered to assume responsibility, investigate failure cause, develop corrective actions, and ensure implementation of corrective actions. 22.9.4.3
Any systematic action taken to eliminate or reduce the frequency of equipment failure (hardware or software) is a corrective action. Such actions may include part designs or material changes, part supplier changes, assembly procedure changes, maintenance procedure changes, operational changes, training changes, or software changes. All corrective action plans and their verification and implementation should be reviewed by the FRB on a regular basis. The FRB should also maintain a log of the corrective action status including open and closed corrective actions.
Reliable equipment
In-house test
Corrective action verification test
Failure data reports
Failure Reporting and Corrective Action System (FRACAS) process flow.
Reliability Testing
No matter how many or how extensive the analyses we perform to calculate the reliability level of equipment, it is almost impossible to calculate the effect of all the factors that affect the reliability level. Even after engaging a meticulous reliability modeling software programs to do the reliability level calculations, we cannot theoretically derive the exact reliability level that will be observed in a reliability test or when equipment is installed at the customer's site. This inability of our theoretical efforts necessitates performing reliability tests to find the actual reliability level of the equipment configuration of interest. The tests validate theoretical calculations and provide a proof for the expected performance indices. Reliability testing is also a very important activity of the reliability improvement programs. Information generated during the reliability test is vital to design engineers for initial designs and subsequent redesigns or refinements, and to the manufacturing engineers for fine-tuning the manufacturing process. The reliability tests also provide vital information to program managers showing technical progress and problems of an equipment line. Reliability tests can be performed at any level of integration, i.e., at the component level, part level, module level, subsystem level, or system level. Not only that, they can be performed during any equipment program life cycle phase. Among the numerous reasons to conduct reliability tests are: 1. To determine the reliability level under the expected use conditions 2. To qualify that the equipment line meets or exceeds the required reliability level
SERVICE REPORT NO. _______ Received By:
Customer System ID
Equipment Serial No.
Module Serial No. Ref. Report NO.
Service Category:
Install Courtesy Telephone Fix Training Problem/Symptoms/Reason for Service Call
Warranty Update
PM UM
Development Others
Repair & Maintenance Action(s)
Replaced
Status of Equipment Upon Leaving
Complete Date Time Customer Remarks
Service Engineer's Signature Customer's Signature
A typical failure report form.
3. To ensure that the desired level is maintained throughout the equipment life cycle phases. 4. To improve reliability by identifying and removing root failure causes.
Types of Reliability Tests
Since reliability testing is included in all the equipment life cycle phases, and they are conducted for numerous reasons, it follows that the testing includes many types of tests. The following reliability tests are commonly seen during a typical equipment program. 1. Burn-in tests 2. Environmental stress screening (ESS) tests
3. Design verification tests 4. Reliability development/growth tests 5. Reliability qualification tests. Burn-in Tests. These test are conducted to screen out parts that fail during the early life period. They are performed at part, subsystem, or system level. Most failures observed during these tests are due to manufacturing workmanship errors, poor quality parts, and shipping damage. System level burn-in tests are also known as debug tests. Environmental Stress Screening Tests. As the title indicates, the ESS tests are conducted in an operating environment that is harsher (stressed) than the normal environment of expected use. The main purpose of the test is to weed out parts that, otherwise, would not fail under normal operating environment. This test increases confidence that all received parts are of good quality and they will last longer (i.e., have better reliability). Design Verification Tests. Design verification tests are conducted to ensure that a desired reliability level is achieved during the design phase under the expected use conditions. Most of these tests are run at the system level. Reliability Development/Growth Tests. Reliability development/growth tests are conducted to ensure that a desired reliability level is achieved during a given equipment program life cycle phase and it is improving (growing) as the program moves further along the life cycle phases. Most of these tests are run at the system level. Reliability Qualification Tests. These test are conducted to qualify that the component or equipment meets or exceeds the reliability level. These are pass–fail tests. If the demonstrated reliability level is equal or better than the required level and confidence, the equipment (or its program) is considered as meeting the requirement–passing the test or qualifying the equipment.
Generic Steps for Reliability Tests
Three overall steps of any typical reliability test are: 1. Test plan development 2. Test conducting 3. Test data analysis and reporting. 22.10.2.1
Test Plan Development
A well thought-out reliability test plan includes the following: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14.
Test objectives Hardware, software, and process to be used Operational stresses and environment Resources required (including consumable) Sample size and test length Test procedure Data to be acquired Data form to be used Data analysis techniques Data reporting and reviewing procedures Pass–fail criteria, if required Expected outcome for each test Types of test reports Schedule of key test activities.
The reliability test plan should be formally documented and approved by high-level managers.
22.10.2.1.1 Test Length The test length depends upon the desired confidence in the test results and the expected level of reliability (MTBF). Tests need to run long enough to increase confidence in the test results. However, we never have enough resources or time to test for an extended period. Therefore, statisticians have developed a method to determine the minimum test length needed to make correct decision with the required confidence in that decision. For repairable equipment, minimum test lengths are calculated to ascertain certain minimum MTBF level (target MTBF) with certain confidence, by
Minimum Test Length with P% Confidence Z ðTarget MTBFÞ !u
where P%, desired confidence level; target MTBF, MTBF to be proved or expected; u, appropriate multiplier for P% confidence from Table 22.6. For example, if we need to prove target MTBF of 100 h, with 80% confidence in the decision, the minimum test length is calculated as follows. Target MTBFZ100 h uZ1.61 from Table 22.6 for 80% confidence level These give a minimum test lengthZ100!1.61Z161 h If we observe no or one failure in the 161 h-long test, we meet the target MTBF of 100 h. 22.10.2.1.2 Test Conducting During this step, the reliability test is conducted according to the test plan. All deviations from the formal test plan should be recorded and approved. A formal log of test events is kept to record key test parameters associated with each event. 22.10.2.1.3 Test Data Analysis and Reporting All the data collected during the test are appropriately analyzed, and conclusions are made. Use the formulae given in Section 22.2, Section 22.4, Section 22.6, and Section 22.7 to determine the observed reliability level, the associated confidence limits, and other performance parameters. You can also use SEMI E10 [2] formula to calculate the desired metrics. Failure Review Board and other interested groups should review the test data, results, and conclusions. To close a test project, a formal test report must be issued containing test objectives, test procedures, findings, conclusions, and recommendations.
22.10.3 Reliability Tests throughout the Equipment Program Life Cycle Phases Reliability tests are scattered throughout the equipment program life cycle phases. They play a very important part in the reliability improvement process. Table 22.7 lists the appropriate tests for each phase.
Minimum Test Length Multiplier u Confidence P%
Multiplier u
Handbook of Semiconductor Manufacturing Technology TABLE 22.7
Reliability Tests throughout the Equipment Life Cycle Phases
Life Cycle Phase
Reliability Test
Concept and feasibility Design
No formal reliability test Part-level reliability qualification Design verification and reliability development Accelerated test Part-level reliability qualification Design verification Reliability qualification Reliability growth Accelerated test Burn-in Environmental stress screening System-level reliability qualification Accelerated test Reliability growth Burn-in Environmental stress screening Reliability qualification Product reliability acceptance test Accelerated test Reliability growth None recommended
Pilot production
Phase out
22.11 Use of Equipment Reliability Discipline in Business Practices To achieve equipment reliability goals/requirements, equipment manufacturers and users must include equipment reliability in their business practices as described below. Equipment suppliers. They must use equipment reliability throughout the various equipment-life cycle phases as shown in Table 22.8. Beside these activities, equipment suppliers must insists that their component suppliers use equipment reliability in their business practices. Similarly, all dealing with their customers must include equipment reliability. For example, any reference to reliability requirement in either request for quotation (RFQ) or purchase order (PO) documents must
Uses of Equipment Reliability in Suppliers' Business Practices
Activities Using Equipment Reliability Discipline
Concept and feasibility
Goal setting Apportionment Reliability plans Preliminary modeling Design-in reliability Design assessment and modeling Design verification testing Failure mode and effect analysis (FMEA) Part life tests Design review System test and reliability level assessment Design review Failure reporting, analysis, and corrective action system (FRACAS) FRACAS Product reliability assurance tests (PRAT)
Prototype Phase and Pilot production phase Production phase
include items shown in Table 22.4. If a customer does not specify reliability requirement clearly, the supplier must let the customer know that specific reliability requirements are lacking in the PO and must be clarified. Equipment users. A need for equipment reliability discipline begins when a user initiates an equipment search. At that time, the user must know the reliability requirements of the equipment they are going to acquire. These requirements must include items shown in Table 22.4. Whenever a user decides to evaluate equipment in his own factory, the reliability level calculations must be based on the formula given in Section 22.2, Section 22.4, Section 22.6, and Section 22.7. All the RFQ's and PO's must include appropriate reliability metrics. After the equipment has been purchased and installed in the factory, equipment users must accurately track the reliability performance level. They must implement continuous equipment improvement activities, such as failure reduction or OEE improvement programs. Table 22.9 summarizes the uses of equipment reliability by equipment users in their business practices.
SEMI E10
This chapter cannot end without describing SEMI E10, a Semiconductor Equipment and Materials International (SEMI) specification for definition and measurement of equipment RAM. A task force (consisting of semiconductor manufacturing equipment suppliers and users) developed it under the SEMI Metrics Committee. The SEMI E10 Guideline was issued in 1986 and revised several times. With a revision in 1996, SEMI E10 became a SEMI Standard and SEMI specification in 2000. See Ref. [2] for the latest revision of SEMI E10 (SEMI E10-0304E).
To create synergy between semiconductor equipment suppliers and users, they must work together for mutual gains, understand RAM expectations of each other, and speak the same language when talking about equipment RAM metrics. SEMI E10 Specification provides this language (a common basis for communication between users and suppliers of semiconductor manufacturing equipment) by providing specifications for measuring RAM metrics of equipment in manufacturing environments. For equipment suppliers, SEMI E10 RAM metrics are useful at each product life cycle phase, from early equipment design and development through production. From equipment users point of view, SEMI E10 provides an industry-wide and company-wide uniform specification to collect, analyze, track, compare (machine to machine, wafer fab to wafer fab, and industry wide), and report equipment RAM data. Accurate data collection of time allocation in each state is essential to calculate the accurate RAM metrics. Automation efforts to collect the data are also based on SEMI E10 definitions and formulae. Both CoO and factory capacity analyses use SEMI E10 RAM metrics. They also provide a basis for specifying reliability performance in equipment PO agreements. The long-term benefits of SEMI E10's TABLE 22.9
Uses of Equipment Reliability in Equipment Users' Business Practices Users Activity
Equipment search Equipment evaluations Sending RFQ's Sending purchase orders Equipment performance tracking Equipment improvement programs Using high-level equipment performance metrics
Reliability specifications and observed value calculations Observed failure rate (or MTBF) and confidence limit calculations Reliability specifications and all the reliability metrics used in the RFQ's Reliability specifications and all the reliability metrics used in the PO's Observed failure rate (or MTBF) and confidence limit calculations Observed failure rate (or MTBF) and confidence limit calculations Reliability elements of the high-level metrics
Operations time
Non-scheduled time - Unworked shifts, holidays - Installation, modification, rebuild or upgrade - Off-line training - Shutdown/startup
Engineering time
Unscheduled downtime
- Process experiments - Equipment experiments - Software qualifications
Manufacturing time
Productive time - Regular production - Work for 3rd party - Rework - Engineering runs
- Maintenance delay - Repair time - Change of consumables/chemical - Out of spec Input - Facility related
Scheduled downtime - Maintenance delay - Production test - Preventive maintenance - Change of consumables/chemical - Setup - Facility related
- No operator - No product - No support tool
FIGURE 22.7 Categorization of total time into SEMI E10 states. (SEMI E10-0304E. Specification for Definition and Measurement of Equipment Reliability, Availability, and Maintainability (RAM), SEMI International Standard, Equipment Automation/Hardware, San Jose, CA 2004.)
international acceptance and use are the improved relationships between users and suppliers of semiconductor (SC) manufacturing equipment that will stimulate a spirit of cooperation and partnership, promoting further improvements in equipment performance. These will lead to greater business success for both users and suppliers.
Two key elements of SEMI E10 are (a) events, scheduled, unscheduled, or non-scheduled, that stop equipment from performing its intended functions, and (b) arrival and departure times for the events. Events are categorized as scheduled or unscheduled. Unscheduled events are called failures. SEMI E100304E defines the failure events as follows. Any unscheduled downtime event changes the equipment to a condition, where it cannot perform its intended function. Any part failure, software or process recipe problem, facility or utility supply malfunction, or human error could cause the failure. SEMI E10-0304E uses the arrival and departure times of the scheduled, unscheduled, or non-schedule events to break down total calendar time into various time blocks as shown in Figure 22.7. These time blocks are defined as equipment states and become the basis for equipment RAM metric calculations similar to those given in Section 22.2, Section 22.4, Section 22.7, and Section 22.8 [2].
References 1. 2. 3. 4. 5.
Dhudshia, V. H. Hi-Tech Equipment Reliability: A Practical Guide for Engineers and the Engineering Managers. Sunnyvale, CA: Lanchester Press, 1995. SEMI E10-0304E. Specification for Definition and Measurement of Equipment Reliability, Availability, and Maintainability (RAM). San Jose, CA: SEMI International Standard, Equipment Automation/Hardware, 2004. SEMI E79-0299. Standard for Definition and Measurement of Equipment Productivity. San Jose, CA: SEMI International Standard, Equipment Automation/Hardware, 1999. SEMATECH. Cost of Ownership Model. Austin, TX: SEMATECH, Inc., 1992 (Technology Transfer #91020473B-GEN). SEMATECH. Design Practices For Higher Equipment Reliability—Guidebook. Austin, TX: SEMATCH, Inc., 1993 (Technology Transfer #93041608A-GEN).
Overview of Process Control 23.1 23.2
Introduction to Control of Systematic Yield Loss......... 23-2 The Control-Type Categories .......................................... 23-4
Abnormality Control Methods † Compensation (Target Tracking) Control Methods † Advanced Process Control: Combination of Both
History of Process Control in Semiconductor Manufacturing................................................................... 23-7 Characterization of Control Needs in Semiconductor Manufacturing................................................................... 23-9
The Four Expected Sources of Variation Requiring Compensation † Timescale of Variations † Pilots, Look-Aheads, Metrology, and Operational Practices
Basic Concepts of All Control Techniques ................... 23-14
Specific Abnormality Detection and Control Methods ..................................................... 23-18
Process Qualification † Process Capability Indices † Types of Errors: False Positives and False Negatives
Univariate Statistical Process Control † Fault Detection by Testing That There Is a Fault † Other Abnormality Control Methods and Use of Equipment Signals † Definition of the Sensitivity vs. Robustness Challenge
Specific Compensation Control Methods .................... 23-20
When Are Benefits Realizable? † Controller Goals: Tracking the Target, Rejecting Disturbances, and Ignoring Noise † Feedback/Feedforward Control † Common Compensation Control Methods Used for Run-to-Run Control † Real-Time Compensation Control Methods
Monitoring the Supervisory Run-to-Run Controller and the Controller System Advanced Process Control ............................................................... 23-34 The Other Type I, Type II Errors: Detection of Change in Overall System † Methods for Monitoring the Supervisory Controller
Stephanie Watts Butler Texas Instruments, Inc.
Continuous Process Improvement................................ 23-35 Benefits of Reducing the Effective Noise of the System Comparing How Different Machines React
23.10 Summary ......................................................................... 23.11 Acronyms and Glossary.................................................. References ....................................................................................... Further Reading .............................................................................
23-36 23-36 23-37 23-40 23-1
Introduction to Control of Systematic Yield Loss
There are several different chapters in this handbook dedicated to control. As these chapters demonstrate, there are several types of control, each aimed at removing yield loss due to a particular source. All of the various control methods combined in their entirety can be viewed as "factory control." Other articles have been focused on this synergistic concept of combining the control techniques of different areas and data sources into one holistic approach to controlling the fabrication facility [1]. Thus, this chapter will not discuss the concept of factory control further. However, the readers should consider this concept as they learn more of each of the control methods in each chapter. The increasing importance of systematic yield loss has been documented by a study by Keithley Instruments: "among the findings were that wafer misprocessing new accounts for more yield and reliability problems than contamination" [2]. This misprocessing includes both unintentional and intentional sources. Unintentional misprocessing includes operator and automation errors. Intentional misprocessing is the use of a recipe as requested by the engineer, but which recipe, coupled with the current state of the equipment, will result in less than desired results. This chapter will focus on methods other than those for defect and contamination control. In other words, this chapter will focus on methods for detecting and controlling misprocessing, also termed systematic yield loss. Consequently, for the remainder of the chapter, the term "process control" will be used to designate controlling the equipment and the process to ensure that desired results are achieved. Another reason for the application of process control is the need for improved productivity. In order to meet the historical trend of 30% per function per year reduction in cost, fab and equipment productivity must improve. In some cases, the yield is already high, but the overhead to achieve that yield is unacceptably costly. As this chapter demonstrate, application of certain types of control lead to improved productivity due to the reduction in pilot and look-ahead usage, with the yield remaining the same or even improving. Systematic yield loss and misprocessing can be considered to be from two sources. The first source is an abnormality, i.e. unusual process behavior. The second source is expected, but undesirable, variation. Thus, control methods can be divided into three categories: † Methods based upon detecting abnormalities and correcting them † Methods based upon actively compensating for expected sources of variation † Methods based upon a combination of compensation and abnormality detection In practice, which control method is used is based upon how the engineer and organization view the situation. In other words, two people may view the same situation differently and consequently feel differently about which method is more appropriate. The purpose of this chapter is to provide the readers sufficient knowledge of the different methods and their assumptions so that they can judge which method is most appropriate. In addition, this chapter will provide a cursory overview of some of the emerging techniques so that the readers can identify new technology they feel is necessary for the future. How to locate the additional knowledge, information, and resources required for implementation of any of the methods is also provided. Figure 23.1 explains what and how information is provided in this chapter, and the corresponding section number. Interdependencies of the various sections are shown so that the reader can decide which sections they may desire to read first. The chapter begins with a more complete definition of the three control categories listed above. All control methods discussed in this chapter will be relegated to one of the three control-type categories. A history of how control developed in the semiconductor industry enables the reader to understand why certain techniques have become popular and how different supplies came into being. To comprehend what control techniques are appropriate, a thorough understanding of the characteristics of the control need is necessary, i.e., the ability to dissect any systematic yield loss into its control characteristics is necessary before one can judge the appropriateness of any technique. The dissection of the control need characteristics also identifies the behaviors of the abnormal and expected
Section II Control categories Advanced process control
Abnormality control methods
Section III History Who
Compensation control methods
Where Section VIII Math/specifics of controller monitoring
CIM/MES
Section IV Characterization of control needs in semiconductor manufacturing
Section XI Bibliography References Resources Information
Section IX Continuous process improvement methods
Section VI Math/specifics Section VII Math/specifics
Section V Process qual Process capability indices error rates
Explanation of what is covered in which sections.
variation and the situation in which it will occur. This explanation of the sources of systematic yield loss and how it relates to the different categories of control methods is the foundation for the entire chapter. The chapter then switches to preparation for the introduction of specific technologies, with first the explanation of process qualification and process capabilities and their role in control. The chapter then becomes more technical as a review of some of the mathematics highlights the assumptions involved. Because of the importance of the concept of error rates which are encountered explicitly in abnormality control methods and implicitly in compensation control methods, a simplified discussion of error rate cause and relationships will be given before any specific techniques are presented. This review of errors will be referred to frequently in the subsequent sections, since optimizing error rates is one of the predominant drivers when determining which control technique to use. Then specific abnormality and compensation control techniques are presented. The compensation control section also stresses the requirements for successful application of compensation control, i.e., just because the systematic loss is high does not always mean one can apply compensation control to reduce it. The mathematics of abnormality control methods is not covered extensively because there are many excellent texts and articles, which cover this area. Instead, mathematical concepts that are then revisited in the section on compensation control are introduced. The chapter concludes with a short review of the final, but most important, items of any control system, i.e., monitoring the supervisory controller and continuous process improvement. A bibliography is also included which the reader should find invaluable. Due to the large volume of literature, it would be impossible to review each article. Instead, the bibliography allows the reader to find further information about specific techniques and applications. The bibliography includes pointers to companies and web pages as well. A glossary provided at the end of the chapter assist the reader with definitions and acronyms. It is hoped that the material presented in this chapter will provide a strong foundation to allow the reader to comprehend other materials referred to in the bibliography.
The Control-Type Categories
As noted above, systematic yield loss and misprocessing can be considered to be from two sources. The first source is an abnormality, i.e., unusual process behavior. The second source is expected, but undesirable, variation. Thus, control methods can be divided into three categories: † Methods based upon detecting abnormalities and correcting them † Methods based upon actively compensating for expected sources of variation † Methods based upon a combination of compensation and abnormality detection Each of the above categories described below. The major supposition of each of the methods will be elaborated. The characteristics of the abnormal and expected variation and the situations in which it will occur described in the Section 23.4 characterization of control needs in Semiconductor manufacturing.
Table 23.1 lists various groups of abnormality control method. The supposition is that there is normal variation ("common cause") and abnormal variation ("special cause"). Compensation is assumed to be undesirable or impossible for normal variation, while abnormal variation must be fixed, usually by repair performed by a human. Thus, these techniques can also be considered manual control. The groups of methods listed in Table 23.1 vary due to the source of data used by the method, but also by the final purpose of the method. Thus, note that some of the methods do not actually include a methodology for what action to take upon detecting an abnormality, i.e., they are really monitors only rather than controllers. The basis of all the methods is the use of a technique to detect the abnormal variation (fault) in the presence of normal variation. Within a group of methods, as well as between group to group the biggest difference is the particular fault detection technique used. Because of the normal variation, one encounters difficulty in developing a technique that always detects abnormal variation without falsely identifying some normal variation as a fault also. While different fault detection techniques are developed to be more mathematically appropriate to the physics of the situation, they are also developed to achieve better error rates of erroneously declaring an abnormality. Fortuitously, techniques that are more appropriate mathematically for the situation usually yield better error rates. The mathematics of the error rates will be presented later.
Compensation (Target Tracking) Control Methods
Table 23.2 lists various groups and alternative terms of compensation control methods; Run-to-Run control is also known by a variety of terms that are listed in Table 23.3. The supposition in compensation control is that there is expected non-random variation and random noise. Compensation is assumed desirable and possible for the expected non-random variation. Classically in the other industries in which TABLE 23.1 Terms and Groupings of Process Control Methods That Are Based upon Abnormality Detection and Correction (Manual Process Control) Statistical process control (SPC) Statistical process monitoring (SPM) Multivariate SPC or SPM Real-time SPC Equipment monitoring Excursion detection and control Fault detection (or fault identification) Fault isolation Fault classification Diagnosis Fault prognosis
TABLE 23.2 Terms and Groupings of Process Control Methods That Are Based upon Compensation for Expected Variations (Automatic Process Control) Model-based process control Sensor-based process control Engineering process control Algorithmic SPC Automatic process control Automated process control Feedback/Feedforward control Specific types of control algorithms fuzzy logic, model predictive control, robust control, etc. Run-to-run control (batch to batch) Real-time control (within a batch)
compensation control methods were first developed, the compensation was determined by running calculations on computers. Thus, these techniques can also be considered automatic control. This idea of compensating for expected variation can be seen in Figure 23.2, where the goal of the controller is to reduce the variance around the target to the inherent random noise in the system. A concept that Box and Hunter have been introducing in recent presentations is that compensation control transfers the variance from the output, where it is expensive, to the input, where it can be less expensive [3]. Thus, compensation control results in cost savings. The groups of methods listed in Table 23.2 vary due to the source of data used by the method, the types of algorithms, and the time scale over which the algorithms run. Within a group, the methods vary due to the use of different algorithms for deciding the compensation. Different groups of methods are more appropriate for some types of variations. The compensation control methods all decide (1) when to make an adjustment, (2) what variables to adjust, and (3) how much to adjust those variables so that the desired results will be achieved. Different methods do a better job of compensation based upon the particular source of variation, the dynamics of that source, the random noise level, and the particular controller goals that the engineer desires. Tracking the target is typically the predominant controller goal, and thus the term "target tracking" to refer to compensation control methods. However, other goals exist in addition to target tracking [4].
Advanced Process Control: Combination of Both
Compensation control methods should also be aware of unexpected variation (or abnormality). This situation is when the controller operates on a system with different variances than for which the controller was designed. In other words, the random and/or non-random variances are different than expected. Although the controller may still drive the output to target, the overall quality of the result is suspect since operating in this regime has never been qualified. Thus, unmeasured variables and the metrology itself may be out of specification. The desired controller behavior would be for the controller to detect the change in process behavior and generate an alarm. Note that this situation can also arise in the abnormality based methods when the output appears to be on target but in reality the system has drifted to a state where the metrology and the system are out of specification. In this case, abnormalitybased methods have no extra ability to detect the system change. Fortuitously, the compensation behavior provides another way to determine if the system is behaving as expected. In other words, the compensation based controller can monitor not only the output changes, but how the output changes TABLE 23.3
Alternative Terms for Run to Run Control
Run-to-run (run-to-run) control Supervisory control Recipe adjustment Recipe synthesis
Run-by-run (run-by-run) control Batch-to-batch control Recipe generation Recipe tweaking
Mean is off target
Variance includes systematic variation Run number
Target With control
Mean=Target
Variance= Inherent noise
Run number Target
Driving the output mean to the target and shrinking the variance to the inherent random noise.
in response to a given change in input as well, to determine if the over-all system has changed behavior resulting in better detectability. This desire to monitor for abnormalities in the compensation based controller leads to the concept of merging both methods into one. The merging of both compensation and abnormality based methods is called Advanced Proess Control (APC) in the semiconductor industry. The supposition in APC is that there is expected non-random (systematic) variation, expected random noise, and unexpected variation (which may be non-random or random). Compensation is assumed desirable and possible for the expected non-random (systematic) variation. Unexpected variation is to be detected and an alarm generated preventing the controller from operating under these conditions. Thus, a "fault" is a change in the variation of the system away from the expected variation. In other words, APC decides: † † † †
When to make an adjustment What variables to adjust How much to adjust those variables. If the system is responding and acting as expected, such as by checking that adjustments are not to frequent or too large or that the system has not drifted too far.
Because of the number of decisions made in APC, it is also defined as a documented analysis methodology for deciding how to run a single piece of equipment or a group of equipment to achieve desired results. Another view of APC is shown in Figure 23.3 in which the various components which run at different time scales are shown. The various controllers, monitoring systems, and data sources are shown. Manufacturing enterprise system (MES) which stores the product and process specifications, as well as tracks work in process (WIP). The Recipe is the setpoints and parameters for all the controllers on the equipment, i.e., it tells the equipment how to operate. Each layer builds upon the previous layer by using data from the previous layer plus additional information to achieve that layer's goal of abnormality detection or compensation. Metric generation is explicitly shown in Figure 23.3 due to its importance. To emphasize that it is the controller data that is monitored to detect a system fault, the abnormality detection part of APC has also been termed "statistical process control (SPC) on the controller" or "controller SPC."
Continuous process improvement Monitor control system Supervisory (Run to Run) controller Metric generation from post run data
Goals, info from MES
Monitor regulatory controllers Recipe
Metric generation from real-time data Real-time Sensors
Regulatory controllers
In-line and on-line metrology data
FIGURE 23.3 Components of advanced process control (APC): Optimum performance by integration of each layer. Real-time regulatory control includes endpointing; MES is manufacturing enterprise system (also known as computer integrated manufacturing system); supervisory run-to-run controller has historically been referred to as "model-based process control"; monitor for regulatory controller has historically been referred to as "fault detection and classification"; monitor for supervisory controller has historically been referred to as "statistical process control on the controller" or "overseen."
It is also common to see APC define as:
APC Z MBPC C FDC where MBPC is model-based process control, which is commonly used for the supervisory run-to-run controller and FDC is Fault Detection and Classification, which is a common generic term for monitoring the regulatory controller. It also implies Fault Classification and Fault Prognosis. A similar concept, algorithmic Statistical Process Control, was being investigated at approximately the same time in the process industries [5,6]. The major difference is that Algorithmic Statistical Process Control focuses only on controlling the "quality variables," i.e., only the outer three layers with ex situ data of Figure 23.3, i.e., the layers utilizing at-line and on-line data for supervisory control and monitoring of the supervisory controller. A similar philosophy of merging the best of SPC and automatic control was also being investigated by a few in the statistical and control communities [7–14]. In these investigations, it varied whether the focus was on real-time or run-to-run control. However, generally, the focus was on only one of the loops (real time or run-to-run), rather than synergistic linkage of compensation control and abnormality detection at all levels.
23.3 History of Process Control in Semiconductor Manufacturing While real-time compensation control techniques had existed for a few decades in the petrochemical, process, and aerospace industries, the development of control systems in the semiconducting industry initially was not based upon work in these other industries. While some of the academic and industrial control people were involved in more than just the semiconductor industry, an explanation of the history
will show that the independence was due predominantly to the systems environment lack of real-time process and product sensors on commercial equipment, focus on Statistical Process Control, which evolved into run-to-run (batch-to-batch) control, and real-time controller monitoring. Initially most semiconductor processing equipment had very little process control other than temperature controllers on furnaces. However, by the mid to late 1980s, pressure controllers, mass flow controllers, and temperature controllers were becoming quite common on most tools. Lithography exposure equipment had better controllers for dose, focus, and alignment. Feedback control of unit processes was now being recognized as necessary for consistently achieving future smaller device geometries. As part of this recognition, the Semiconductor Research Corporation (SRC) and SEMATECH began focusing funding in the area of process control. Control was considered part of Computer Integrated Manufacturing (CIM) or Factory Science, and therefore this topic was included in the CIM and Factory Sciences Areas. An SRC Workshop (first CIM workshop) was held at the University of California at Berkeley in 1986. A second workshop was held the next year at the Massachusetts Institute of Technology. These workshops helped focus attention on process control. An SRC workshop on Real-time Tool Control was held on February 1991 in Canada, co-hosted by Techware (now Brooks Automation Canada). A SRC/DARPA CIM workshop was held in August 1991. SEMATECH then began hosting Advanced Equipment and Process Control workshops from the summer of 1991. The list of workshops is included in Table 23.4. Initially, these workshops focused on real-time process control. However, due to the lack of commercial real-time process sensors, the apparent huge hurdle to be overcome by process equipment suppliers, and a very strong interest by semiconductor manufacturers, the focus of the workshops became more increasingly focused on run-to-run control and regulatory controller monitoring. Semiconductor manufacturers could implement these controls without involvement of the equipment supplier. In addition, large benefits could be achieved in both these areas. While the workshops were driving the academic, industrial, and equipment research communities, a revolution was occurring on the factory floor. The need for increased control and the incompatibility of traditional Statistical Process Control (SPC) with many semiconductor processes was resulting in the invention of compensation control and advanced abnormality detection methods by fab process engineers [15]. So, although the typical fab process engineer was not versed in control theory, they also were working in areas traditional control theory mainly did not exist: run-to-run (batch-to-batch) control and regulatory control monitoring (batch monitoring). In addition, statisticians heavily assisted the fab engineers, a situation unusual in the process and petrochemical industries. The result was a different theoretical background for compensation control. Finally, the strong link to the Manufacturing Execution System (MES) was not present in other industries. Thus, the unique systems environment hindered the application of traditional process industries control theory to the semiconductor industry, while simultaneously enabling the development of this new area of run-to-run control. In addition, because of the strong Statistical Quality Control fab environment, the integration of various levels of control resulted in the concept of Advanced Process Control (APC) presented in the last section. TABLE 23.4
SEMATECH Advanced Equipment and Process Control Workshops
30 July to 1 August 1991, Austin, Texas 3–5 March 1992, Mesa, Arizona October 1992, Austin, Texas 19–22 April 1993, Dallas, Texas October 1993, Dallas, Texas Fall 1994, San Antonio, Texas Fall 1995, New Orleans, Louisiana Fall 1996, Santa Fe, New Mexico Fall 1997, Lake Tahoe, Nevada Fall 1998, Vail, Colorado
Title of workshop has changed through the years.
By the mid-1990s, traditional and modern control theory relevant for run-to-run control was being integrated into the fab-invented and statistically-based techniques [16,17]. In addition, the regulatory control monitoring (equipment signal monitoring) theories from semiconductor manufacturing and process industries were being cross-fertilized. Also, changes at process equipment vendors and the emergence of commercially available process sensors were resulting in the re-emergence of real-time control focus. While the control theory from other industries is being exchanged, the unique systems environment has resulted in unique systems solutions for the semiconductor industry. For further explanation of the systems issues, see Ref. [18]. Because of the emphasis in the industry on run-to-run control, regulatory control monitoring, and the concept of Advanced Process Control (APC), these areas will be more heavily focused upon in this chapter. The ability to understand exactly what are the control needs, i.e., why are abnormality and compensation control methods needed, is imperative to deciding which control technique is appropriate. This understanding will also provide insight into how control evolved in the industry since it was focused on meeting the needs of the semiconductor industry. The next section will present a dissection of the different control needs in the semiconductor industry. This dissection is based upon the historical observation of what are common control needs process to process and fab to fab.
23.4 Characterization of Control Needs in Semiconductor Manufacturing The benefits of control have been observed by many and presented in a variety of articles, as well as at the SEMATECH workshops [19,20]. Table 23.5 provides a list of benefits that can be achieved with the right control method. The benefits can be considered direct and indirect. Direct benefits impact the cost or quality of manufacturing in an easily observed manner. Indirect benefits lead to cost or quality improvements in manufacturing, sales, or design in a less than obvious manner. There are other benefits which are not listed in Table 23.5 because they are software dependent. Two such software-enabling benefits are the removal of paper logbooks from the fab, and the integration of qual data and producing data into our database. All the benefits listed in Table 23.5 can be lumped into three categories as shown in Figure 23.2 and Figure 23.4. The compensation controllers continuously drive the output to target, thereby improving TABLE 23.5
Detailed Benefits due to Advanced Process Control Direct Benefits
Reduced pilot and look-ahead usage Reduced number of quals and qual time Reduced set-up time Reduced cycle time (due to qual and set-up time) Reduced scrap (outlier reduction) Accommodate inherent machine/chamber difference Reduced (tighter) distribution around target Increased equipment uptime and productivity Decreased equipment repair time Decreased post-maintenance recovery time Improved data-driven maintenance and qual schedules Improved qualification of equipment kits Reduced capital costs (increased life of equipment) Data drive sampling plan
Indirect Benefits Improved productivity of operators and engineers Improved customer satisfaction Continuous improvement of equipment (Pareto sources of variation) Faster learning cycle for process development (faster device ramp) Process and product understanding Accommodate greater device diversity (increased process flexibility) Fab-to-fab standardization and sharing Increased confidence in alarms Increased ability to redesign products based on tighter process control
1. Increase productivity 2. Eliminate outliers 3. Improve typical distribution • Drive average to target • Reduce variance around target
Reduce variance
Eliminate outliers
Outliers vs. expected typical distribution and ways in which APC results in improvements.
the distribution. The abnormality based methods detect outliers and prevent continued misprocessing. When both methods are used, as in Advanced Process Control, the sensitivity to changes is increased, and the number of outliers is reduced further. The productivity improvement is fortuitous and is due to the automation, applicability of the mathematics, and heavy emphasis on decision-making of APC. As discussed [19,20], it is the productivity improvement that is most needed. We will discuss these benefits again in the Section 23.7.1. As noted in the introduction, different methods perform better for different situations, and applying appropriate statistics is important to achieve the needed benefits [21]. Consequently, a good understanding of the situation in which the methods will be applied is required to understand which method will work satisfactorily and why the benefits listed in Table 23.5 and Figure 23.4 can be achieved. Also some of the productivity benefits are due to the way pilots (non-sellable wafers) and metrology are used in the semiconductor industry. In this section, the reader should consider whether the variation is: † Expected Random Variation † Expected Non-Random Variation † Non-expected Variation As mentioned in Section 23.2, compensation methods are aimed at correcting for expected nonrandom variation and abnormality-based methods are aimed at detecting non-expected variation. For both types of methods, expected random variation is considered natural and should not be classified as a fault, nor should compensation be attempted.
The Four Expected Sources of Variation Requiring Compensation
The variation for which control compensates can be categorized into four sources. Table 23.6 Provides the four categories of expected variation for which control is compensating. The sources of variation in Table 23.6 require compensation, i.e., a different action must be taken, in order for the desired results to be achieved. Note what is not included in Table 23.6. An unstable process is not included. A machine that breaks frequently is not included. Thus, while compensation is a tool that every engineer should have in their toolkit, it is not the only tool. Dynamics can be defined as the non-random behavior of the system over time, i.e., how the output would change with each run if no compensation were used. Disturbances themselves have a particular
Overview of Process Control TABLE 23.6
Four Expected Sources of Variation Requiring Compensation with Explanation and Examples
1. Within-run dynamic process or dynamic target / Strong function of time within a single run 2. Disturbancesa / Equipment aging, such as calibrations, chamber build-up, part wear / Machine maintenance, such as chamber clean, kit replacement / Inherent chamber-to-chamber differences / Wafer state (called "loading" in etch) 3. Change in feedforward valuesb / Incoming wafer state, which are due to results of earlier processes, such as thickness / Machine attributes, such as tube age, sputter target age 4. Change in process or product goal (e.g., set point, target) / Different device / Different step in flow (sidewall oxide etch as opposed to contact oxide etch) Usually not want to compensate for ALL disturbances, feedforward changes, just expected ones. A disturbance which can be measured and whose impact on the controlled output can be modeled can become a feedforward variable. b An unmodeled or unmeasured change in a feedforward variable is a disturbance. a
dynamic behavior which are given in Table 23.7. Feedforwards and Goal changes can be viewed as step changes, i.e., dynamics so fast as to be unmeasurable. Understanding the dynamic behavior is important because the compensation technique is dependent upon the specific dynamics of the system. In other words, what is called the systematic variation by the process engineer is called the dynamic behavior by the control engineer. A technique for step dynamics may not work as well for a disturbance whose dynamics are a moderate ramp. The size of the change is also considered when designing the compensation technique. If the change expected is large, more aggressive action may be required than if small changes are encountered.
Time Scale of Variations
As the same theme as dynamics, is the time constant of the system. In other words, the amount of time it takes before changes are observed. There are actually several different sources of variation within
Equivalent Dynamics (/) and Size of Change ( ) for Disturbances
1. Equipment aging, such as calibrations, chamber build-up, part wear / Slow-to-moderate run-to-run dynamics The faster the dynamics, the greater the changes over 10 lots 2. Machine maintenance, such as chamber clean, kit replacement / Step function Size may range from small to very large, typically large 3. Inherent chamber-to-chamber differences / No dynamics Size may be significant, but can be driven to near zero with considerable work 4. Wafer state (called "loading" in etch) / Step function as switch between products due to differences in topography, open area If exists, size can be considerable / May be step function or slow dynamics if due to previous equipment disturbances If exists, effect is smaller than the effect due to different products 5. Major fault, such as mass flow controller (MFC) fails or rapidly degrades / Step function or within-run dynamics (fast run-to-run dynamics) Size may range from small to very large, typically large A disturbance that can be measured and whose impact on the controlled output can be modeled can become a feedforward variable. Even if the disturbance becomes a feedforward, the dynamics still exist.
a semiconductor process system. Each of these variations and their associated time scale are given in Table 23.8. Table 23.8 assumes a single wafer processor, i.e., that each run consists of a single wafer. Not all systems are single wafer, such as batch furnaces. However, because single wafer systems represent the most complexity, only they will be analyzed. Note that there are continuous changes and discontinuous changes. For example, between each maintenance, there is the continuous slow drift of the order of a fraction of the maintenance cycle, i.e., the changes can only be observed over 100 or more wafers (actually over several lots). However, there are also discontinuous changes which occur approximately every lot (24 wafers). The same continuous and discontinuous variations occur when observing what occurs within a time scale of 24 wafers. Finally, changes occur within a single run itself. Figure 23.5 presents a plot of an example of within run variation. This example is metal etching in a plasma. While there is considerable variation within a single run, the functionality is repeatable. In other words, the mean value or length of a region may increase or decrease from run to run, but that one region has a higher mean value than another region will repeat from run to run. The length of the region may vary due to different incoming or targeted film thicknesses, as well as process drifts over larger time scales (e.g., Within a Maintenance Cycle). The mean value may change due to sensor aging, process aging, or changes in incoming wafer state. The SMALLEST size of variation is typically the within a lot, wafer to wafer, and within a region.
Dynamics of Each Time Scale Variation and Their Causes (Assumes a Single Wafer Processor)
† Maintenance cycle-to-maintenance cycle (every O20,000 wafers) – Discontinuous change (step function) – Repairs, chamber cleans, preventive maintenance kit replacements – Attempts to return in same ideal machine state are rarely successful – Maintenance can produce the largest changes † Within a maintenance cycle (w100–1000 wafers) – Continuous change – Gradual build-up on chamber, machine ear, sensor drift † Lot to lot (every 24 wafers) – Discontinuous change (step function) – Due to incoming wafer state – Due to current process (if plot data from lots of a given type) † Other lots processes run between lots of this process – Undocumented maintenance, changes generally occur between lots † Within a lot [assuming one chamber (1–10 wafers)] – Continuous change – "First wafer effect" (which may last for more than one wafer) † Warm-up effect, de-gassing, different steady-state chamber state – Due to incoming wafer state from previous process which has first wafer effect † Wafer to wafer (every one wafer) – Discontinuous change – Due to incoming wafer state † For example, left/right track effect of upstream lithography step † Different chambers of cluster tool used for upstream processing (1–2–3–1–2–3.) – Due to current process † Randomness caused by process start-up, repeatability of equipment controllers – Undocumented maintenance, changes can also occur wafer to wafer † Within a wafer, further broken down into (Figure 23.5) – Region-to-region † Discontinuous change † Due to different processing conditions (different recipe step) or due to different materials exposed – Within a region † Continuous change † Due to changes in materials exposed and heating effects
Optical emission intensity
Materials exposed
TiN/ Ti
Overetch (Ox)
0 −500 0
Gas pressure stable, plasma ignited
Step # of recipe
Example of within a wafer variation: metal etch.
It is imperative to understand the main sources of variation for both fault detection and control. Many years of observation have shown faults generally occur between lots. Faults are next most likely to occur between wafers. One wants to catch the fault on or before the first wafer after the fault occurred. However, this can be very challenging considering large variations are expected to occur between lots, and the fault may appear small to the measurement technique. Thus, detection between wafers is easiest, but can ONLY occur if measurements are made on every wafer. In-line metrology rarely is done on every wafer. Consequently, only in situ or on-line metrology (metrology mounted on the process equipment or equipment sensors), which can easily be used for every wafer, can be used to detect faults between wafers. An additional challenge is caused by the variety of processes run on a single tool. The difference between processes is usually much larger than the size of a fault. Thus, one might propose to analyze each process separately to increase sensitivity to the fault. However, due to all the expected variations which occurs to the machine and that a given process will not be run in huge volume, the variability across lots of a single process can be huge too. Therefore the concept of global modeling, where a model is used to normalize all processes to each other, is used to allow increased sensitivity. This concept is also used in feedback/ feedforward control and is the predominant source of productivity improvement due to elimination of pilots. Understanding the time scales is important for control because they are a part of the dynamics analysis. As discussed above when introducing dynamics, the compensation technique is selected based upon the dynamics. Thus, if the major source of disturbance is machine variation caused by maintenance a different control scheme will be designed than if the major source of disturbance is the first wafer effect.
Pilots, Look-Aheads, Metrology, and Operational Practices
Twenty to Forty percent of wafers processed are pilots (non-production wafers). Another significant fraction are look-aheads, wafers from a production lot processed and analyzed before the rest of the production lot is processed. Pilots cannot be sold and look-aheads have a huge impact on cycle time and throughput. Thus, both are undesirable. One reason for pilots is that some of the current wafer metrology is contaminating, destructive, or cannot work with topography. Another usage of pilots is for chamber conditioning post maintenance. However, manufacturing flexibility and lack of direct measurement of the equipment/chamber state are the actual reasons for the bulk of pilot and look-ahead
usage. Manufacturing flexibility mandates that a single piece of processing equipment process a variety of wafers. Thus, concern arises about how one process (called "A") will impact the chamber which results in a different result for another process (called "B"). Without any on-tool measurements which indicate the chamber state, a wafer measurement must be used to indicate the chamber state. Therefore, when switching between processes A and B, a pilot or look-ahead will be run first to confirm the chamber state. If there is confidence that process B will most likely be ok or only need small tweaking, a look-ahead is used. If there is less confidence, a pilot is used. The same dilemma arises after maintenance, will the chamber be different and cause different process results? Again, pilots or look-aheads are used. Regardless of process interactions, because processes A and B may be very different, without advanced control, processes A data was analyzed separate from process B data. Thus, if the last 10 lots run were all of process A, a pilot or look-ahead is run before process B. Not because A is suspected to have cross-talk with process B, but because no data are available to predict how process B is run. If a global process model can be created to relate process A data to process B data, then a look-ahead need not be run. It is this ability to create a global model that reduces the number of pilots used in a production fab. In some instances, if process A and B interact, a global model may be developed which predicts this interaction. Modeling and understanding the interaction is much more difficult. Thus, interacting processes are more infrequent in the fab, while non-interacting processes are quite common. While advanced control can reduce the pilot usage for machines which run more than one process, only better on-the-tool metrology can reduce pilot usage after maintenance.
Basic Concepts of All Control Techniques
Before discussing specific techniques, there are several concepts that the reader must comprehend. The first is the Process Qualification and how it pertains to control. The next concept is the Process Capability Indices and how they are used to rank control. The final concept is error rates and their usage in tuning the control algorithm.
Process Qualification
Because this chapter is on process control, to not discuss the role of process qualification would be negligent. Thus, before specific control techniques are presented, a methodology for identifying the right control technique and insuring its ability to control the process satisfactory will be introduced. Included is an over-all semiconductor processing quality system is a methodology for qualifying a process for use in manufacture of production material. The methodology for qualifying a process is commonly known as a qual plan. The most well documented Qual plan in the open literature is the SEMATECH Qual Plan [22,23] Domain Solutions markets software to assist in conducting a qual plan, based on one created at IBM [24]. An important part of a Qual plan is to determine that the associated metrology is capable. Gauge studies, also known as R&R studies, which signify the analysis of repeatability and reproducibility variances, are used to assess the metrology capability. Variance component studies are also done of the process to determine that it will meet specifications with the desired yield and determine the source of variability. This study is done with the desired control system in place. Thus, evaluating the quality of the controller is part of qualifying a process. An adequate control system will guarantee that methods and practices exist which insure the capability values will be maintained in the actual production environment. In the development of the controller, the sources of variation that will be encountered must be considered to design an adequate controller.
Process Capability Indices
Process capability indices are used to assess the process' ability to achieve yield. The two most common over-all metrics to assess the process's capability are Cp and Cpk. These indices were created in the statistical Quality Control field. However, they are a useful metric even when evaluating compensation controllers.
Cp strictly evaluates the process's variability compared to the specification limits on that process:
USLKLSL 6s
Cp Z
where USL is the upper specification limit, LSL the lower specification limit, and s the standard deviation of the process. While Cpk also considers the mean of the process, i.e., how centered the process is within its specification limits:
Cpk Z minimumðCpL ;CpU Þ where
X KUSL 6s X KLSL CpL Z 6s X Z Average of process results CpU Z
The desired values of Cp and Cpk are commonly said to be 2 for a 6s process. Figure 23.6 shows a graphical representation of Cp and Cpk with a value of 2, along with a shift in the mean of 1.5s yielding a Cpk value of 1.5. Note that when the mean shifts and the variance does not, as shown in Figure 23.6, the Cp value remains unchanged, as also shown in the Figure 23.6. A Cpk of 2 means that only 2 parts per billion (ppb) are outside of the specification limits, while a value of 1.5 means that 3.4 parts per million (ppm) will be out of specification. Note that 2 ppb loss translates to a yield of 99.9999998% and 3.4 ppm loss equals an yield of 99.99966%. Because of the many statistical problems exist with Cp and Cpk, such as assuming both an upper and lower specification limit and only one source of random Gaussian variability, there is considerable work in the statistics field developing alternative process capability indices. The greatest issue is the lack of understanding of the large sample size required to obtain a value with good confidence, but this situation
Spec limits Mean –1.5s +1.5s
C p=2.0 C pk=1.5
C p=2.0 C pk=1.5 C p=2.0 C pk=2.0 −6 −5 −4 −3 −2 −1
FIGURE 23.6 Cp and Cpk process capability indices; Cpk considers the average value while Cp does not; Cpk value of 2 is equal to 2 ppb outside of specification; Cpk value of 1.5 is equal to 3.4 ppm out of specification.
would be true for any metric involving variance. Regardless of the statistical issues, Cp and Cpk provide engineers a target for which to aim, and they also convey the importance of centering the process and shrinking its variability. Two alternative metrics for judging a process's performance were developed in the process industries control area, which are independent of the specification limits [4].
MISE Z
MIAE Z
vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi u t uP u error2i t iZ0
t vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi u t uP u jerrori j t iZ0
where errori is the target-Y at time i, Y the controlled output, MISE the mean integral squared error, and MIAE the mean integrated absolute error. These two metrics are influenced by how centered a process is and the variability of the process. MISE is the analog of the standard deviation, but with the average replaced with the target. In other words, MISE can be considered the standard deviation around the target. MIAE is the analog of the Mean Absolute Deviation, and just like Mean Absolute Deviation, is less sensitive to outliers. Thus, process modifications improve MISE greater fraction than MIAE if the modifications remove outliers ("spikes"). These two metrics do not convey information on yield, but they do indicate impact of process and equipment modifications. The goal is to continuously shrink the values of MIAE and MISE.
Types of Errors: False Positives and False Negatives
The following discussion is based upon linear statistics for white gaussian random variation, but these simplified concepts are applicable to any situation. Let's assume that one is attempting to detect a shift in the mean only with no change occurring in the variation level around the mean. As will be discussed later, this situation is the one usually assumed in abnormality control methods. A sample of size N will be used to detect the shift. Consequently, there are two probability distributions of concern, the original distribution and the distribution shifted by an amount D. The two distributions are shown in Figure 23.7. A t-test is used to determine if a shift has occurred [25]. Table 23.9 defines the two types of errors which will occur with the costs associated with each of the errors. As Figure 23.7 shows, the overlap of the two distributions results in the two types of error. It can be seen that as D decreases, b will increase if a is held
m1a Reject H0
b accept H0
FIGURE 23.7 Type I (a) and type II (b) errors from the comparison of mean values of two normal probability distribution functions for sample of size N. Mean values are a distance of D apart. Standard deviation (s) is the same for both distributions.
% of Errors of that Type
Indicates
Costs Due to
Alpha (a)
False positive
Beta (b)
False negative
Detect an abnormality when it has not occurred Not detect an abnormality when it has occurred
Wasted time trying to track down fault that does not exist; unnecessary machine downtime Shipment of bad product, lost of quality, loss of improvement opportunity due to inability to see impact of a factor
constant. In other words, for a given sample size, smaller shifts are more difficult to detect. As the sample size N is increased, the distributions narrow since the standard deviation of the sample mean is the standard deviation of the individuals divided by the square root of N. Thus, as the sample size increases, for a constant shift of size D, b will decrease if a is held constant (or vice versa). In other words, increasing the sample size makes a shift easier to detect. To summarize, Table 23.10 lists the variables which determine the percentage of type I and type II errors, a and b, respectively, for any fault detection method. Which mathematical technique is selected is based upon its appropriateness to the situation and the availability of software and computer hardware. The size of fault that needs to be detected is based upon the necessary quality that must be achieved. However, for the mathematics, it is not the absolute size of the fault that matters, but rather the relative size of the fault compared to the normal variation, usually represented by the standard deviation. The greater the sample size, the lower are the type I and type II errors. However, larger sample sizes may take longer time to gather which may increase the amount of time before a change will be detected. In addition, many times, the sample size is determined by the physics and cost of sampling. Consequently, the remaining choice is between a and b. Once a value for ONE of these variables is selected, the value for the outer variable is also determined. As described in Table 23.9, there are costs associated with both of these errors. Thus, the trade-off between a and b is really an optimization of the economics. The value selection for the error types, for a given relative fault size to detect and sample size, is determined by how the mathematical technique itself is set-up or tuned. In other words, each fault detection technique generally has at least one parameter associated with it. A given value for the parameter(s) determines the values for a and b for a given sample, size, normal variation level, and desired fault size to detect. Many of the methods also include sample size as an explicit parameter in the equations, further highlighting the importance of the sample size. Another way error type information is calculated and explained is with the average run length (ARL). This metric is useful for cases where analytical calculation of error rates is difficult. The ARL is calculated by performing many simulations for a given fault size and standard deviation of the noise ("common cause variation"). The number of runs before a fault is detected, the run length, is recorded for each simulation. The average of these run lengths is then calculated. The ARL for a fault size of zero provides a metric for type I error. The ARL for a given non-zero fault size provides a metric for type II error. Thus, a chart or table of ARL vs. fault size per normal standard deviation is used to compare different fault
TABLE 23.10
Variables Involved in Determining a and b Error Rates
† Mathematical technique used † Size of fault being detected when compared with normal variation † Type I error (a) † Type II error (b) † Sample size of the data
detection methods and/or different values of the method's parameters. While rarely done, the whole distribution of run lengths could also be compared.
Specific Abnormality Detection and Control Methods
We will cover abnormality detection methods used in run-to-run control under compensation methods. Generally, abnormality detection and control methods are part of a total quality management (TQM) program [26]. Due the volume of existing textbook on SPC and TQM, TQM will not be covered here and SPC methods will only be quickly reviewed.
Univariate Statistical Process Control
The most common of the abnormality-detection-based methods in the semiconductor industry is Statistical process control (SPC). There are several books dedicated to the application of SPC [27]. SPC has been practiced in the semiconductor industry for at least 20 years and is very widespread [28]. The SPC is an entire methodology, including addressing what actions to take upon detection of an abnormality and how to inform the operators of these needed actions. In traditional SPC, the expected variation is assumed to be described by a normal (Gaussian) distribution occurring around a mean. In other words, the errors around the mean are assumed to be identically independent distributed (IID) normal. Identically independent distributed means that the value of each error for every measurement comes from the same distribution, and that each value is independent of the previous value, i.e., the errors are uncorrelated. This assumption for the distribution of y is represented as
y Z m C3
3 Z IIDNð0;sÞ
where y is the measurement, m the mean (average) of the distribution for y, 3 the random error in measurement y, IIDN(0,s) the Identically Independently Distributed Normal (Gaussian) distribution with mean of 0 and standard deviation of s. Another common way of representing the distribution of y is
y Z Nðm;sÞ
where y is the measurement, N(m,s) the normal (Gaussian) distribution with mean of m and standard deviation of s. In SPC, an abnormality is assumed to be a shift in the mean of this distribution (m) or a change in the standard variation of the normal distribution (s). In SPC, the abnormality detection technique used is based on the statistics and charting of the data. Different types of statistics have a different associated charting method. Thus, the specific fault detection techniques are usually called XYZ chart, with XYZ denoting the specific statistics used. Note that many times there may be more than one actual chart per a given technique. Different techniques exist because different physical situations require different mathematics and due to efforts to obtain better type I and type II errors. Also, different techniques may be testing different hypothesis. Some are testing whether the mean (m) has shifted, while others are testing whether the standard deviation (s) has changed. Due to the statistics, it requires a much larger sample size to detect a change in the standard deviation than a change in the mean [25]. In addition, some may argue that changes in the mean are more likely to occur, although we will address this suggestion again in the section on using equipment signals. Consequently, charts to detect changes in the mean are much more common. Incidentally, a change in the variance can also cause a test for a change in
the mean to trigger. Thus, although the fault detected is incorrect (a mean change when it is a variance change), an alarm is still generated indicating that something is abnormal. The most common of the SPC charts is a Shewhart chart, also known as an XBar–R (Average–Range) chart [29]. Although XBar–R charts are the must well known, the I-MR (Individuals-Moving Range) is more appropriate. The across sample and run to run variation must be the same for an XBar–R Chart to be appropriate. The variation within a wafer, wafer to wafer, or lot to lot is rarely the same, thus causing the use of a single sample ("individual"). To decrease type II error, "supplementary run rules" are used with the Shewhart Chart. These rules are generally known as the Western Electric (WECO) Rules in recognition of the source of their well known application. While WECO rules decrease Type II errors, they also increase Type I error. Other charts, such as CUSUM, have been developed to provide better Type I and II errors for smaller relative fault sizes. These other charts also lend themselves naturally to single sample size applications. However, these alternative chart types still have not achieved wide application mainly due to software limitations.
Fault Detection by Testing That There Is a Fault
Note that traditional Statistical Process Control Methods look for an abnormality by testing the hypothesis (H0) that the system IS as expected. For example, to test that the current mean equals the expected mean:
H0 :m Z m0
where m is the current mean and m0 the expected mean. On the other hand, one could explicitly test that the system is NOT as expected by testing for a particular fault, for example:
H0 :m Z m0 C D
where D is the fault size testing. For Equation 23.8, only data from when the system is "good" are required to set-up the fault detection method. However, to actually understand the a and b values, a fault size must be assumed. For Equation 23.9, data from when the system is "good" and from when the system is "bad," i.e., experiencing the fault, are required. Thus, if a given fault is known to occur, the methodology corresponding to Equation 23.9 will generally yield better fault detection capabilities. However, if no particular fault is expected, the methodology represented by Equation 23.8 is the only approach available. Even if Equation 23.9 is used, Equation 23.8 should also be used to catch all unexpected faults. While this concept of using "bad" data to create an abnormality detection method is beginning to be presented more frequently in the literature, it still is not encountered in industrial practice.
Other Abnormality Control Methods and Use of Equipment Signals
Table 23.1 includes many methods in addition to univariate SPC, such as multivariate SPC and Real-time SPC. In the semiconductor industry, multivariate methods are predominantly used on equipment signals. Because equipment signals are measured during processing, the term "real time" has been associated with SPC on equipment signals. Because many of the methods used with equipment signals are broader than the univariate SPC, the generic term Fault Detection is also generally used for Abnormality Control applied to equipment signals. The sources of most of the equipment signals are regulatory controllers on the equipment. This application of abnormality control to the regulatory controllers is the layer labeled "Monitor Regulatory Controllers" in Figure 23.3. The regulatory controllers will maintain the controlled output signals close to the setpoints specified in the recipe, even under the influence of moderate faults. However, the actuator values required to maintain the controlled outputs to their setpoints in the face of
faults is usually significantly different than from the situation with no faults. Thus, the actual source of realtime data used in the fault detection technique is the actuator values from the regulatory controllers. The mathematics used in equipment signal monitoring ranges from very simple to quite complex. The reader is referred elsewhere for a discussion of the mathematics [1]. The bibliography at the end is also useful for identifying typical conferences, proceedings, and web sites which also cover this topic more extensively. There is similarity in the methods to those used for monitoring the Run to Run controller (covered in Section 23.8). However, due to the volume of variables and the within run time aspect, real-time controllers are more difficult to monitor.
Definition of the Sensitivity vs. Robustness Challenge
In the section discussing error rates, the concepts of false positive and false negatives were introduced. Let's define sensitivity as the ability to more easily detect errors, i.e., the test is more sensitive to smaller errors. Thus, sensitivity is related to false negatives. The smaller the false negative rate, the more sensitive is the technique. Let's define robustness as the ability for the method to correctly function in a wide variety of expected variation. In other words, robustness is related to the false positive rate. The lower the false positive rate, the more robust is considered the method. Based upon the discussion of error rates, it should now be obvious that sensitivity and robustness are trade-offs. This trade-off is specifically highlighted because of the difficulty in achieving a robust and sensitive method. As already mentioned several times, some methods are more appropriate to a particular situation than other methods and thus will yield better error rates. Consequently, they will provide better sensitivity and robustness.
Specific Compensation Control Methods
When Are Benefits Realizable?
To ensure successful application of a compensation control technique, three items should be considered: 1. Requirements for compensation control to be feasible 2. Definition of goals/improvements to be achieved 3. Probability of success One must understand that certain requirements must be met for compensation control to be possible. The most basic requirement is that the system must NOT be Independently Identically Distributed (IID). IID was discussed in the section on univeriate SPC. Note that the errors (or random error) can be IID, which is actually preferable. This requirement is the same as saying that the mean itself shifts and drifts. Table 23.11 lists the remaining requirements which relates to the concepts of controllability, observability, TABLE 23.11
Requirements for Model-Based Process Control
1. Appropriate situation and predictable / Shifts or long-term drifts affect machine productivity / Typical process variations can be characterized / Changes occur infrequently/slowly enough to get adequate disturbance and process models / Currently need period adjustment 2. Controllable / Adjustments to actuators/settings affect outputs to be controlled / Adjustments to actuators/settings can be made quickly enough / Adjustments to actuators/settings can be made with enough precision 3. Observable / Data collected can be related to output to be controlled / Data are/can be collected frequently enough / Measurement dead time is short enough / Good signal-to-noise ratio
and predictability. In other words, one can predict future changes based upon current and post data, and one can cause alterations in the system to counter-act the changes predicted to occur so that they are never observed in the output. Regardless of the need for productivity or yield improvement, if these basic requirements are not met, then compensation control is not possible. A clear understanding by everyone of which goals are to be achieved is required to ensure the specific controller is selected which is likely to achieve the specific goals. Table 23.5 lists a variety of possible goals. Implementers and their managers should discuss which goals are desired before possible algorithms are ever discussed. One goal not listed in Table 23.5 is which the particular process selected for implementing control will enable implementation at subsequent similar process. For example, while the improvements expected for this process may be small, it allows the development of the infrastructure necessary for more complicated, high visibility processes which are expected to realize large improvements. The probability of success relates to basic systems environment, resource management, and change management. These topics are outside the scope of this chapter. However, their importance in instituting a new methodology which is predicated upon automation and interaction with the current CIM environment cannot be stressed enough.
23.7.2 Controller Goals: Tracking the Target, Rejecting Disturbances, and Ignoring Noise While the final goal of implementing control is usually one of the benefits listed in Table 23.5, the controller itself usually has a particular goal and it is fine-tuned to meet this goal. In other words, particular controller mathematics is used which optimize a particular controller goal in order to achieve an over-all process improvement goal. At first thought, it would seem that tracking the target is the only goal of a controller. However, random noise is also present. The three classic goals of any controller are given in Table 23.12. Trade-offs are required between these goals. Controllers with fast response and which aggressively attempt to remove the influence of disturbances and process dynamics are more susceptible to noise. This susceptibility is due to the amount of data required to distinguish between a real change in the mean caused by a disturbance or process dynamics and a data point in the tails of the normal process variation. Thus, just like for abnormality control methods, Type I and II errors are also of interest in compensation control methods, although rarely discussed in a typical control textbook. In the compensation case, Type I error can be viewed as the controller making an unnecessary action which increases the variance around the target. Type II error can be viewed as the controller not taking a needed action that would have reduced the variance around the target. As the discussion on Type I and II errors mentioned, increasing the sample size requires a greater time for data collection. Thus, a controller with a given algorithm which reduces its type I error, without changing its' Type II error, will be more sluggish to respond. Just as different fault detection algorithms provide better Type I and II errors for a given situational application, so do different compensation algorithms provide better target tracking, disturbance rejection, and noise insusceptibility. We will discuss this concept again in the section on SPC-based compensation control methods. In traditional petrochemical industry control, stability can be a real issue. In fact, in these industries, stability considerations may dominate the design and tuning of the controller. However, in run to run
The Three Classic Goals of a Controller
1. Track the target without lag / The output should immediately go to the new target (set point) when it is changed / The output should remain on target even under the influence of process dynamics 2. Prevent disturbances from influencing the output / The output should remain on target even when disturbances occur 3. Ignore random noise / The controller should not increase product variance by responding to spurious (not real) fluctuations
control, it is rarely a large concern. Thus, this lack of focus on stability concerns has also led to a difference in the approach to control between the semiconductor industry and the petrochemical industry.
Feedback/Feedforward Control
All compensation control techniques can be classified as Feedback or Feedforward. Note that Table 23.2 list Feedback and Feedforward control. Figure 23.8 demonstrates these two types of controllers. Feedback uses measurements about the current process results to decide how to change the process for the next sampling period. Feedforward uses measurements on incoming materials, process, or equipment to decide how to change the process for the current process. Thus, feedback control drives the average value to target (i.e., drives Cpk to equal Cp). Feedforward control, because it accounts for incoming variations, can improve the Cp value, i.e., it turns apparently random variation into non-random variation, which can be compensated for. Based on Table 23.6, feedback control is used to compensate for expected disturbances. Feedforward control is used to compensate for measured disturbances that have been modeled. Target (Setpoint) changes are encountered in both feedback and feedforward control.
23.7.4 Common Compensation Control Methods Used for Run-to-Run Control There are a variety of control methods in the control literature, although many are not currently deployed in the Semiconductor Industry. In this section, how run-to-run (batch-to-batch) control evolved in the semiconductor industry will be covered. Control methods from the petro-chemical industries will be introduced next. Finally, the critical issue of deadtime will be introduced. This section will conclude with an example that illustrates many of the concepts introduced in this section. 23.7.4.1
The Creation of SPC-Based Controllers in the Semiconductor Industry
As mentioned previously, Statistical Process Control, an abnormality detection and control method, has been practiced for many years in semiconductor manufacturing. However, in several cases, traditional SPC just would not, and could not, work [15,30]. The assumption that the expected variation can be described by IID, i.e., that the values were uncorrelated, did not hold. Because of the variety of processes run on a single piece of equipment, a given process produced a small sample size causing statistical problems. In addition, the assumption that the machine was "out-of-control" when an SPC test alarmed was not correct. To many, "out-of-control" meant the machine needed to be repaired, and yet it was not broken. Others interpret the philosophy of using a "knob" to re-turn the process when an alarm is given as compatible with SPC concepts [31,32]. However, the alarm frequency was greater than the traditional
Feedforward
Settings for next run
Settings Thickness metrology
Feedback and feedforward controls.
SPC expectations, i.e., traditional SPC expects alarms to be infrequent and an exception to typical behavior. Thus, because of the frequency of the knob adjustment, ensuring consistency in how different operators used the knobs and documenting what values they used is extremely important. In the mid1980s, the search began for a method to determine: † When to re-adjust the process † How much to re-adjust the process In addition, the emphasis was on: † Ease of implementation due to the frequency of the adjustments † Prevention of over-controlling due to the inventor's SPC background † Ability to use the methodology in an environment of small number of runs per process Thus, the SPC chart gained a new role: to determine when to adjust the process. By allowing the SPC chart to trigger when to adjust the process, over-control could be avoided. It was also believed to be easy to implement since the fab already had SPC charts in place. In addition, the operators and engineers were already used to taking an action when a SPC failure occurred. However, a traditional SPC chart would not be appropriate since a controlled output would be serially correlated, which violates SPC chart assumptions. Thus, a regression control chart is used [33], on which the residuals (Actual value– Predicted value) are plotted. If the predictions are good, then the residuals should be IIDN (0,s) and a SPC chart is appropriate. It is assumed that a model is used for the predictions. When the model is no longer centered the predictions will become poor, causing a fault to trigger on the chart indicating the model needs to be tuned. Of course, in such a case, the residuals may also become autocorrelated, i.e., the residuals will not be independent (the second I in IIDN). Due to the autocorrelation, the error rates (a and b) will not equal the values expected from the SPC chart set-up on truly IIDN(0,s) data. However, in practice, tuning based upon an SPC chart has worked as expected by the engineers who were used to operators manually tuning based on SPC chart on the controlled output. To handle the small run sizes, it was envisioned that models could be used to combine data from different processes into one controller. Thus, if different processes were used for different thicknesses, a model was used for thickness to combine all the data into one model:
y^ Z mx C b
where y^ is the model prediction for output y, e.g., thickness; m the slope of the model (model parameter), model coefficient, gain; x the recipe setting, e.g., time; b the offset and is the tuned model parameter; and y the output being modeled, e.g., thickness. The next question was what data to use to tune the process. An obvious answer was to use the data involved in the WECO failure [30,31]. To show how the process was tuned, b was tuned with the data in the WECO violation set by N W P
bnew Z bold C
ðyi Ky^i Þ NW
where NW is the number of runs involved in WECO test failure, e.g., the 4 or 5 runs involved in a 4/5 WECO run rule failure, called the violation set. Every time the model is tuned, the history is re-set. In other words, the historical data used to calculate the next SPC test does not include any data previous to or including the run for which the last SPC trigger occurred. In addition, the history is re-set after maintenance. If the process is expected to return to a baseline state, the b value is re-set to its original baseline value. However, because the process may act
significantly different after each maintenance, test runs may be used to calculate the b value: L P
ðyi Ky^i Þ
ð23:12Þ L where L is the number of test runs, usually 1, bold the last value of b or the baseline value of b. To calculate the setting (x) to be used in the recipe, the value of x for the next run was found by solving Equation 23.10 by setting the prediction equal to the desired target value T and using the new b value for Equation 23.11 or Equation 23.12: y^ Z T Z mx C b/ x Z
T Kb m
where b is the most up-to-date value of b (from Equation 23.11 or best estimate) and T, the desired target value for output y. The above methodology became known as "model-based process control" in the semiconductor industry because it deployed a process model as part of the controller. A simple graphical representation is shown in Figure 23.9. Table 23.13 lists the algorithm with some generalizations that will be made clear in later sections. Representative equations to use in the algorithm is shown as sub-bullets in Table 23.13. It is the tuning of the model that provides feedback, i.e., the above algorithm is a form of feedback control. Control for setpoint changes occurs when the value for T is changed in Equation 23.13 resulting in new settings values. While Figure 23.9 shows the idealized case of a linear process, no noise, and no model mismatch, experience has proven that the method works even in the presence of these complications. Model mismatch is when the coefficients of the model other than the offset, i.e., the gains are not equal to the true values of the process or when terms, such as a quadratic term, are missing in the model. To use this method, a model needs to be fitted to the process data to obtain a value for m and an initial estimate for b in Equation 23.10. Sometimes the equations used are not of the form above, and it may appear that a model of the form of 10 is missing. However, the same mathematics is implied, i.e., the equations used can be put in the form above. For linear single input-single output systems, Equation 23.10 seems unnecessary because yZ ^ T can usually be substituted in Equation 23.11 and Equation 23.12 and an algebraic solution is possible, as shown in Equation 23.13. However, using an explicit model form is a good practice because such a form is necessary for non-linear, multivariable systems, as will be discussed later.
Output (modeled variable) 18 16 14
Original model
Adapted model
Original recipe
Re-solved
2 3 4 Input (setting on machine)
Graphical representation of model-based process control for case of low error, linear process.
Overview of Process Control TABLE 23.13
Generalized Semiconductor-Model-Based Run-to-Run Control Algorithm
1. Model created to predict output as a function of input (process model) † Equation 23.10 † Equation 23.25 † Others / In Figure 23.9, the lower line is the original (untuned) model 2. Model is solved (optimized, inverted) to determine what value of the settings is predicted to give values for the output equal to target Note: While settings are calculated each run, they are not necessarily different each time † Equation 23.13 † Equation 23.27 † Others / In Figure 23.9, target value of 10, XZ1.8 3. Wafers are run with these settings values in the recipe 4. Measurements are made for run 5. Output metric (actual value) is calculated from measurements † For example, average thicknessZaverage (measured values) / In Figure 23.9, actual output is higher than target 6. Compare actual output to predictions to decide whether the model should be tuned; if not, skip to step 7 † Statistical process control chart † Deadband, Equation 23.24 † Others / In Figure 23.9, is determined the need to tune 7. Tune model (provides feedback) according to disturbance model † Equation 23.11 if production run † Equation 23.12 if qual run † Equation 23.22 or Equation 23.23 with l value for production or qual run † Others / In Figure 23.9, new tuned model shown (adapted model, dotted line) 8. Go to step 2 / In Figure 23.9, new solution results in output on target With example equations and relation to Figure 23.9.
23.7.4.1.1 Process Model and Disturbance Model Equation 23.10 through Equation 23.12 can also be reformulated to highlight two important concepts. † The process model which predicts how a change in the input will cause a change in the output † The disturbance model that predicts how the output changes over time (runs) Using the concept of the process model and the disturbance model, an equivalent equation can be presented.
y^ Z Process model C Disturbance model
Thus, by comparing Equation 23.14 with Equation 23.10, Equation 23.11, and Equation 23.12, it's obvious that:
Z Process model
How b is tuned Z Disturbance model
Z Equation 23:11 and Equation 23:12 It is the formulation of Equation 23.14 that allows expansion into other non-linear and multivariable process models and more advanced disturbance models. It also explicitly highlights that one must effectively capture the inherent behavior of the system to input changes (the process model) AND be able
to predict the way disturbances will impact the system (the disturbance model) to be able to effectively control the process. Thus, Equation 23.14 demonstrates how feedback control is a mechanism for compensating for the disturbance. 23.7.4.1.2 The Biggest Benefits of "Model-Based Process Control" Several major benefits come out of the above methodology and are listed included in the list of Table 23.5. Models were originally used because processing was needed at more than one desired target, due to different products needing different results or due to the same machine being used for two different processes in the flow. Thus, a model-based methodology was created to allow one control strategy for both processes. Once the controller could handle two processes, it could handle infinitely many [30] providing increased process flexibility. In addition, since all the data were related through the model, each product run became the "test run" for the next product run, thereby reducing the need for look-ahead and qualifications runs which decreased pilot usage too. This ability to model more than one process is the "global modeling" concept introduced in the section on Characterizing Control Needs. With the automation of the above methodology, engineering, technician, and operator productivity was improved. By allowing the controller to decide when qualifications were necessary based upon the data and using the controller to perform quals, including those for post-maintenance recovery, qual runs, qual times, and post-maintenance recovery time were reduced. Using the controller data to determine cause of alarms speeds the repair time. The models can be unique per machine chamber and the controller used to drive chamber results to sameness removing the effect of chamber/hardware differences. Other benefits listed in Table 23.5 will be discussed in the section on controller monitoring. The controller described above was applied to the Plasma Enhanced Chemical Vapor Deposition (PECVD) of tetraethyl orthosilicate (TEOS) [15]. The Cpk value was increased from 2.5 to 4.5. The number of quals was reduced from one per day to one every 3 days. Due to one pilot wafer was used for each qual, reducing quals also reduced the associated number of pilots. The time spent doing quals was reduced from 1 h per qual to 15 min per qual. Other examples of improvements are given in Ref. [15]. One item to note is that the SPC based methodology appears to be so simple as to not require automation to achieve the benefits cited. However, in practice, the necessity of automating the calculations to achieve adequate quality and consistency has been demonstrated. On the other hand, it has been found that entering the new settings into the equipment does not necessarily require automation, although increased quality will be achieved with automatic recipe download to the equipment. 23.7.4.1.3 The Biggest Issues with SPC Based Process Control One issue with WECO based tuning is the resulting "bang–bang" nature of the output. Bang–bang control is the simple style of control used for home thermostats. The setting can take on only two values, on or off. The result is the temperature will alternate between above or below the desired target temperature, but rarely at the target temperature [4]. Similarly, with the WECO tuning, the output generally alternates between above and below the target. Contributing to this behavior is the small sample of data used in the tuning. Additionally, lag can sometimes be encountered due to waiting for a SPC failure. The issue of type I and II errors needed to be addressed differently when the response action is an automated control action verses. a manual control action. Table 23.14 compares the cost of type I and II errors for the case of expected variation needing compensation only, i.e., the possibility of the system encountering unexpected variation is ignored for this discussion. As can be seen from this table, the trade-off between Type I and II errors should be different for automated and manual controls. In the case of automated control, minimizing Type II errors has a heavier focus due to the smaller cost associated with Type I errors. Obviously, this trade-off must be within reason or the overall cost will not be favorable due to considerable overcontrolling. Finally as Equation 23.14 highlights, one must have a good disturbance model to effectively compensate for the disturbances. In many cases, the SPC based tuner
TABLE 23.14 Comparison of Error Costs for Manual vs. Automated Control for Case of Expected Variation Needing Compensation Type
Take control action when none is needed
Note take control action when one is needed
Costs in Manual Case
Costs in Automated Case
Wasted time trying to track down fault that does not exist: unnecessary machine downtime; if action finally taken, will result in overcontrol (increased variation around target) and will need to manually undo action in future Loss of quality
Control action easily taken by system: action will result in some increase in variance around target; action will need to be undone, but control system will detect overcontrol within next few runs and undo action itself Loss of quality
does not adequately represent the disturbances dynamic behavior. As noted several times, when the mathematics more adequately represents reality, Type I and II error rates are generally improved. 23.7.4.2
The Creation of EWMA-Based Controllers in the Semiconductor Industry
As the search continued for a method with better Type I and Type II trade-offs, many tried the exponentially weighted moving average (EWMA) to tune the b value of Equation 23.11 [34–39]. The EWMA has the distinction of being known as an EWMA chart to SPC experts [40], as a first older digital filter to control pracitioners [4], and as integrated moving average time series, represented as (1,0,1), to statisticians [41]. It's invention in three different fields attests to its natural applicability to many processes, i.e., it was expected that an EWMA would be a good representation of the disturbance dynamics. The equivalency of the first-order digital low-pass filter to an EWMA can be seen by the EWMA equation
Zt Z l Vt C ð1KlÞ ZtK1
where Zt is the filtered value at time t, Vt the variable to be filtered, l the filter factor, 1/time filter time constant. Note: Whether the filter factor is on the output variable or on the filtered variable varies article to article and software to software. This discrepancy is responsible for many an engineer spending wasted hours trying to track down a math error that is in fact is a misunderstanding in filter factor usage. To use the filter for prediction, the following equivalence is used:
V^ tC1 Z Zt
where V^ tC1 is the prediction of the variable V for the next run (timeZtC1), Zt the filtered value of variable V for the current run (timeZt). Another way to represent the EWMA that more clearly shows how the EWMA corrects itself using a fraction of the prediction error is to rearrange Equation 23.16 and note that Equation 23.17 says the prediction for variable V at time t is the filtered value Z at time tK1
Zt Z ZtK1 C l ðVt KZtK1 Þ Z ZtK1 C l et where et is the error in predicting VtZVtKZtK1.
The EWMA is used for control by filtering the model offset b, i.e., defining
Vt Z b Z yKmx
bnew Z Zt
bold Z ZtK1
bnew Z l ðyKmxÞ C ð1KlÞ bold
and substituting into Equation 23.16
or equivalently, substituting Equation 23.19 through Equation 23.21 into Equation 23.18
^ bnew Z bold C l ðyKyÞ
The value for l is determined by what will result in the best control for the system with its associated control issues. A different value of l may be used for production wafers and qual runs to mimic the concept in Equation 23.11 and Equation 23.12. For many cases, since only one qual is run, l for quals is 1, i.e.,
lproduction Z l lqual Z 1 The EWMA-based controller has found wide applicability in the semiconductor industry [34–39]. In some cases, the tuning is for every run [34,36–39]. In other cases, WHEN to tune is still decided by a SPC chart [35,39] or a deadband. A deadband is used for determining when to tune by
If jbnewKboldj % db; then bnew Z bold Otherwise; bnew Z calculated bnew value
where db is the deadband value. The deadbanding prevents unnecessary control action similar to the SPC chart without suffering from unnecessary lag. It is another way to achieve type I vs. type II trade-off. It can be considered equivalent to the trigger value in an EWMA chart. It is also used to prevent what the engineer considered undesired frequent small control action, especially if the changes are being made manually to the recipe on the machine. The deadbanding may be implemented in other ways, such as checking if the input (x) would change greater than a certain amount. If not, then tuning will not occur. 23.7.4.3 Control
Extension to Multivariable, Non-Linear, Constrained Systems with Feedforward
Equation 23.10 and Equation 23.13 assume linearity and single input-single output, as well as lack constraints on the inputs or outputs. The method above can still be used by changing Equation 23.10 to
^ Cb Y^ Z f ðX; FF;Y;qÞ
where f(x) is the generic equation, including non-linearities; X denotes more than one manipulated variable; FF denotes the feedforward measured variables; Ydenotes more than one output variable (actual value); Y^ denotes prediction for each output variable; q denotes all the parameters involved in equation f; ^ and b the current estimated value of the disturbance, i.e., bZ filteredfY Kf ðX; FF;Y;qÞg.
In reality, Equation 23.25 is actually several equations, one for each output. The effect of a feedforward variable is easily seen since it is included in the model. For example, an incoming thickness value could be used as a feedforward variable for a controller on final thickness using time as the manipulated variable.
Final thickness Z initial thickness C m time C b
Based upon the discussion of Equation 23.14
f ðXÞ Z process model and
HOW b is tuned Z disturbance model: The biggest change due to the non-linearities and the constraints is the need for a numerical solver to replace Equation 23.13. In such a case, there are several cost functions that can be minimized. A common cost function that allows trade-offs between changes in the manipulated variables (size of process adjustment) and reaching the target is
( Minimize X
N X iZ1
Wi ðTi KYi Þ C
k X
) wk ðXk KXk;tK1 Þ
kZ1
with constraints
gj ðXÞR 0 hL ðYÞR 0 Constraints are used because not all values of X are allowable. Constraints on the outputs are used because all outputs generally have upper and/or lower specifications and some outputs may not have targets, but rather just upper or lower constraints with no losses associated with being anywhere inside the specification, only with outside the specification. Additional procedures may be sued to prevent oscillations in the solution [16]. The changes to the linear univariate algorithm can easily be understood by examining Table 23.13. The generalization of the algorithm to use alternative tuning methods, solution methods, and process models is apparent. By the inclusion of feedforward variables, feedforward control in additional to feedback control is achieved. If the model is not tuned, i.e., the desired control output is not measured, then only feedforward control would result. 23.7.4.4
Transformations to Comply with Additive Disturbance Assumption
Equation 23.14 implies the assumption that the disturbance is additive to the modeled output. This assumption puts constraints on the output used for to modeling. However, this assumption has been shown to be valid for a variety of systems. Thus, the output modeled may be different than the output controlled in order to meet the assumption. For example, let thickness be the desired output to control. However, the data shows that the additive disturbance assumption really applies to rate, i.e., it is rate that is changing. In this case, Equation 23.10 is replaced by
R^ate Z b
where rate, the modeled tuned output; r^ate, the prediction of output rate; b, the tuned offset, tuned using SPC-based methods, or EWMA, etc. Instead of solving Equation 23.10, as described in Equation 23.13, a new equation is created which is solved.
^ Thickness Z R^ate Time/ Time Z
R^ate T
^ where thickness, the controlled output; Thickness, the prediction of controlled output; T, the target for controlled output (thickness); time, the setting in recipe used to adjust process, and r^ate the use latest tuned value. 23.7.4.5
Predictor Corrector Control
Sometimes, the EWMA model is not an adequate representation of the disturbance. This situation occurs when the disturbance is a near-constant drift run-to-run. The EWMA controller will result in constant offset. (This situation will be examined further in a later section on control of metal sputter deposition.) Thus, a way to correct the prediction of the EWMA controller was needed [16,42]. The resulting disturbance model was called the predictor corrector control (PCC) and remembering the discussions going with Equation 23.16, Equation 23.17, Equation 23.19 through Equation 23.23, and Equation 23.25
Z l Vt C ð1KlÞ ZtK1
T^ t
Z b Tt C ð1KbÞ T^ tK1
Z Vt KStK1
Z St C T^ t Z FilteredðsmoothedÞ value C Filtered trend
where Zt is the filtered value of variable V at time t, Vt the variable to be filtered (ZyKmx in the simplest case)Zb, Tt the current trend (i.e., the difference between the current value and the previous filtered value), St the current smoothed value, and T^ t the current smoothed trend. As can be seen, Equation 23.30 assumes a constant trend and the purpose is to estimate not only the current value of the model offset, but also the trend (or rate of change) in the model offset. 23.7.4.6
Comparison to Other Methods
To demonstrate that an EWMA controller is equivalent to a pure integral controller, which is frequently found in use as a real-time equipment controller, or that PCC is similar to a double integrator, is beyond the scope of this chapter. However, the reader should note that to facilitate such comparisons, different equation forms derived above (such as Equation 23.22 vs. Equation 23.23) were developed to allow for easier comparison to some modern control methods. See elsewhere for a comparison to modern control techniques and the relationship to stability [16,17,42,43]. The typical semiconductor control technique may also be considered a deadbeat controller in that the set point is not filtered [4]. However, because run-to-run control is not truly a digital controller on a continuous process, the analogy is not quite exact. However, with time some readers may find a discussion of deadbeat controller helpful and they are referred elsewhere [4]. Others may find reading on real-time optimization (RTO; NOT rapid thermal oxidation) in the process industries fascinating [44]. The RTO is very similar to multivariable run-to-run control but is applied to a continuous process. Algorithmic SPC's compensation method [5,6], which was discussed previously, is very similar to the minimum variance control of MacGregor [45]. Minimum variance control (as well as internal model control) are equivalent to the generalized semiconductor multivariable controller presented above. However, Algorithmic SPC adds an additional term in the disturbance model to account for measurement noise, which they call an extrinsic error. The main resulting difference in the controller design will be different values in the correlated noise parameters.
Treatment of Dead Time (Measurement Lag)
Measurement lag is the time between the run and the controller getting the measurement. It can have very detrimental effects on the control performance. There are some existing methods for dealing with lag, although they generally assume CONSTANT lag. One method is discussed in describing the compensation method of algorithmic SPC [5], whereby they alter the best forecast for the model error term. They stress that this alternative equation must be used always should the possibility of deadtime occur since the optimal results will not be obtained otherwise. They also note the difficulty of varying deadtime, even if the deadtime is known. However, in general, while the predictions can be modified to account for the deadtime, the controller performance may be too degraded to be acceptable. Thus, one must consider measurement lag and in some cases, eliminate it, to achieve acceptable controller performance. 23.7.4.8
Summary Example Using Metal Sputter Deposition
To illustrate many of the concepts presented above, especially of the concept of the additive process and disturbance models, metal sputter deposition will be used as an example [46]. The metal to be deposited, titanium, had thickness goals spanning 400 A˚ due to the wide variety of processes used. Before the controller was installed many test runs and monitor pilots were used. The Cpk value was near acceptable, but the technician and processing overhead was too expensive. Note in this example, target means the desired value for the output (thickness), not a sputter target. First, a process model needed to be created which spanned all the processes. Figure 23.10 demonstrates a model where the output was rate, rather than the output that had a goal (thickness), and the input was thickness, rather than time. The "hidden" model is that thicknessZrate!time. The model appears to capture the process data eloquently, but would it allow the assumption of the additive disturbance model? Figure 23.11 shows that over a long time period, the model moved up and down, i.e., the model offset varied, but not the slope. Therefore, the additive disturbance model is correct. Note that what is not shown is the other attempts at process models. Within a short period of time, the control engineer learns that only a couple of functional forms will represent a wide variety of processes from lithography to sputter deposition. Thus, once these forms are known to the engineer, they merely attempt to match the data to one of these forms. Consequently, process model building is faster than one might expect at first glance.
Deposition rate (Å/s)
Normalized thickness
Process model for Ti sputter deposition.
Mature/old Mature/new New/new Mature/old Mature/new Old/mature Old/mature
Disturbance model: if process model in correct space see offset only over large time periods.
Next, the disturbance model must be created. First, an EWMA was attempted. The results are shown in Figure 23.12. An offset appears to be presented, which is more obvious in Figure 23.13. Note how the offset is near constant. Based on Figure 23.12 and Figure 23.13, the PCC model was attempted next. The results are shown in Figure 23.14 and Figure 23.15. Now, the offset is gone, and the offset is centered around 0. The final results were test runs were eliminated, reduced the number of monitor wafers by
Rate actual Rate predicted
5.5 Collimator change 4.5
Target/collimator change
Collimator change
3.5 563 651 690 779 855 89 163 245 317 482 537 596 726 794 860 Sputter target life (KWH)
Incorrect disturbance model.
10 8 6 Thickness error (%)
4 2 0 −2 −4 −6 −8
9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 Run number
Offset easier to see in actual target (thickness is variable with target).
a factor 3, Cpk improved by 10%, and simplified processing for operators and reduced sustaining effort for engineers
Real-Time Compensation Control Methods
Table 23.15 provides a list of new activities in real-time equipment control. This table does NOT mention pressure, MFC, or radio frequency (RF) controllers on etchers. While these are extremely common
Rate predicted Rate actual
Deposition rate (Å / s)
5.5 Collimator change 4.5 Target /Collimator change 3.5 750 829
139 211 284 427 519 582 705 770 837 899 Sputter target life (KWH)
Better disturbance model: linear drift (predictor corrector control).
Thickness error (%)
6 4 2 0 −2 −4 −6 −8 −10
11 13 15 17 19 21 23 25 27 29 31 33 35 Run number
Easier to see improvement in actual target (for thickness variable).
controllers, significant changes have not occurred in their control ability. Mass flow controllers are now becoming digital, but their basic algorithms are not changing. Changes are expected in the RF controller arena, but right now, most changes are due to RF sensor installation rather than RF control. Table 23.15 also does not cover control activities in rapid thermal processing (RTP). Chapter 11 covers RTP. In that chapter, is a section on RTP temperature control systems. The reader is referred to Chapter 11.
23.8 Monitoring the Supervisory Run-to-Run Controller and the Controller System Advanced Process Control As was mentioned when APC was introduced, APC includes abnormality methods for monitoring of the compensation controller. Thus, some concepts of type I and type II errors for a control system will now be introduced. Next algorithms for detecting abnormalities in the control system are introduced. It is amazing how these extremely simple algorithms can prevent horrendous yield loss problems due to the increased sensitivity to faults they provide.
New Activities in Industry in Real-Time Control
† Uniformity control – Rapid thermal process – Lithography bake plate † Model predictive control on furnaces – Cycle time and performance improvement † Endpointing – Small open area † Sensors – Purchased integrated from process vendor, manufactured by sensor vendor
23.8.1 The Other Type I, Type II Errors: Detection of Change in Overall System There is another error situation present in compensation control methods. This situation is when the controller operates on a system with different variances than for which the controller was designed. In other words, the random and/or non-random variances are different than expected. Although the controller may still drive the output to target, the overall quality of the result is suspect since operating in this regime has never been qualified. Thus, unmeasured variables and the metrology itself may be out of specification. The desired behavior would be for the controller to detect the change in behavior and generate an alarm. One can consider Type I error as the controller generating an alarm when the system variance has not changed, and Type II error as the controller not generating an alarm when the variation is different. Note that this situation can also arise in the abnormality based methods when the output appears to be on target, but in reality the system has drifted to a state where the metrology and the system are out of specification. In this case, abnormality based methods have no extra ability to detect the system change. Fortuitously, the compensation behavior provides another way to determine if the system is behaving as expected. In other words, the compensation based controller can monitor not only the output changes, but how the output changes in response to a given change in input as well, to determine if the over-all system has changed behavior resulting in a better overall Type I and II errors. This desire to monitor for abnormalities in the compensation based controller leads to the concept of merging both methods into one, one of the conceepts of Advanced Process Control.
Methods for Monitoring the Supervisory Controller
Monitoring the various aspects of the compensation controller would appear difficult. However, monitoring the feedback amount in a model based control system simplifies the abnormality detection. The simple monitoring algorithms are: † Determine if the adjustment is unusual (single or cumulative adjustment too large, too frequent) † Determine whether the output responds to the adjustment as expected, including random noise level A product called Overseer [30] was created to assist with the automatic checking of the Supervisory Controller. It added some more intricate tests, such as: † Are all equipments of a given type drifting or shifting in unison The main concept to be left with the reader is that no controller should ever be implemented without sufficient monitoring. The monitoring prevents the controller from driving the system past reasonable operation, while the control improves the sensitivity and robustness of the abnormality checking.
Continuous Process Improvement
The description of the various control methods will end with a discussion of the outer control layer in Figure 23.3, continuous process improvement. At all times, engineers are examining their process to determine how best to increase it's productivity and yield. They employ engineering knowledge, statistics, and common sense. However, it is the data coming from the various levels of the controllers, in conjunction with data from specially designed experiments, which provides the most information about how best to improve the process or equipment.
Benefits of Reducing the Effective Noise of the System
As mentioned in the introduction on types of errors, the type I (a) and type II (b) errors are a function of the sample size, the particular size of change (D) to be detected, and the noise level of the system (s). For a fixed sample size, both the type I and type II errors decrease as the noise (s) decreases. Conversely, because b is the probability of not detecting a difference when there is one, decreasing the noise also increases the probability of detecting a difference. The probability of being able to detect a change is called the power and is equal to 1Kb. Having good power is necessary to evaluate process improvement changes and design new products [47]. By using global modeling and feedforward variables (including wafer order), the effective noise of the system is decreased, and, consequently, the power to detect a change is increased. Thus, the procedures outlined in the section on Abnormality Detection Control Methods to enable robust fault detection are also important to continuous process improvement.
Comparing How Different Machines React
Investigations of why different machines of the same model number respond differently to the same inputs provides useful information that can be exploited to improve the machine. Determining that one machine is a rogue tool based upon its response to input changes generally provides increased sensitivity to a machine likely to be the source of yield loss at some point. Thus, controller data provides a great opportunity to identify rogue machines. Driving the machines to respond to inputs in a similar fashion is the greatest assurance that the outputs will be consistently similar for all equipment, a major desire by the fab's customers.
This chapter conveyed the depth that process control in the semiconductor industry has achieved. The reader should now be able to assess the variety of control tools available and select those most appropriate for application in their facility. As part of the references section, several pointers to web pages and further resources are provided.
Acronyms and Glossary
Abnormality control methods: Methods based upon detecting abnormalities and correcting them. Alpha (a): Percentage of false positives (detecting an abnormality when one has not occurred). Advanced process control (APC): A combination of abnormality and compensation control methods. Also equal to FDC plus model-based process control. Beta (b): Percentage of false negative (not detecting an abnormality when one has occurred). CIM: Computer integrated manufacturing (may imply MES). Compensation (target tracking) control methods: Methods based upon actively compensating for expected sources of variation. Cp, Cpk: Most common process capability indices used to assess the process' ability to achieve yield. Cpk considers how centered the process is, while Cp does not. Disturbance model: A model that predicts the way disturbances will impact the process, i.e., describes how the process ages. Dynamics: The non-random behavior of the system over time, i.e., how the output would change with each run if no compensation were used. Error rate: Rate at which a false positive error {alpha (a)} or false negative {beta (b)} occurs. EWMA: Exponentially weighted moving average (filter, type of SPC chart, first-order digital filter).
FDC: Fault detection and control. Feedback control: Uses measurements about the current process results to decide how to change the process for the next sampling period. Thus, feedback control drives the average value to target (i.e., drives Cpk to equal Cp). Used to compensate for expected disturbances. Feedforward: Control uses measurements on incoming materials, process, or equipment to decide how to change the process for the current process. Feedforward control, because it accounts for incoming variations, can improve the Cp value, i.e., it turns apparently random variation into non-random variation, which can be compensated for. Used to compensate for measured disturbances that have been modeled. Gain: The change in the output for a unit change in the input. IIDN(m,s): Identically independently distributed normal means all values belong to the same distribution which is a normal (Gaussian) distribution with mean of m and standard deviation of s. Look-aheads: Wafers from a production lot processed and analyzed before the rest of the production lot is processed. MBPC: Model-based process control. WIP: Work in progress. MES: Manufacturing execution system (used for WIP management, material flow control). Metrology: Measurement science; the act of measuring; the measurement process. Pilot: Non-sellable wafer, may or may not have topography. Power: The probability to detect a particular size of change (Z1Kb). Term encountered in sample size calculations in statistical tests and SPC. Process model: A model that predicts the inherent response of the process to input changes. SPC: Statistical process control. SRC: Semiconductor research company (research consortia that funds universities). Trace: Real-time signal over time. Usually implies signals from processing equipment, but source could also be add-on sensors. Type I error: False positive; to detect an abnormality when one has not occurred. Type II error: False negative; to not detect an abnormality when one has occurred. WECO: Supplementary run rules applied in conjunction with Shewart SPC. These rules are generally known as the Western Electric (WECO) rules in recognition of the source of their well-known applications. These rules simultaneously decrease type II error and increase type I error. PCC: Predictor corrector controller. Filter for continuous drifts. Pilot: Non-sellable wafer. Used when processing or metrology could cause out of specification results, produce contamination, or create defects. Also used for machine recovery and conditioning when the equipment must be operated, since most plasma and deposition machines do not allow nonwafer processing. Qual: Short for qualification. Also, a run, usually using pilot wafers, used to qualify a machine to run a particular process(es) after maintenance or when switching between processes. Qual plan: A methodology to qualify a process for use in the manufacture of production material. Random yield loss: Yield loss due to contamination, particles (as opposed to systematic yield loss) Run: A single processing on a piece of equipment or the processing of all the wafers in the lot, which may consist of several processings on single-wafer equipment. Systematic yield loss: Unintentional and intentional misprocessing (as opposed random yield loss).
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Vicker, K. "Advanced Process Control in the Fab." SEMATECH Advanced Equipment and Process Control Workshop, 338–51. Lake Tahoe, CA: SEMATECH, 1997. Guldi, R. L., C. D. Jenkins, G. M. Damminga, T. A. Baum, and T. A. Foster. "Process Optimization Tweaking Tool (POTT) and Its Applications in Controlling Oxidation Thickness." IEEE Trans. Semicond. Manuf. 2 (1989): 54–9. Wheeler, D. J., and D. S. Chambers. Understanding Statistical Process Control, 2nd Ed. Knoxville, TN: SPC Press, 1992. Mandel, J. "The Regression Control Chart." J. Qual. Technol. 1, no. 1 (1969): 1–9. Sachs, E., A. Hu, and A. Ingolfsson. "Run by Run Process Control: Combining SPC and Feedback Control." IEEE Trans. Semicond. Manuf. 8, no. 1 (1995): 26–43: Boning, D., W. Moyne, T. Smith, J. Moyne, and A. Hurwitz. "Practical Issues in Run by Run Process Control." In Proceedings of IEEE/SEMI Advanced Semiconductor Manufacturing Conference, 201–8, 1995. Mozumder, P. K., and G. G. Barna. "Statistical Feedback Control of a Plasma Etch Process." IEEE Trans. Semicond. Manuf. 7, no. 1 (1994): 1–11. Ling, Z.-M., S. Leang, and C. J. Spanos. In-Line Supervisory Control in a Photolithographic Workcell. SRC publication C91008; also SPIE, 921 (1988):258: Bombay, B. J., and C. J. Spanos. "Application of Adaptive Equipment Models to a Photolithographic Process." SPIE Technical Symposium on Microelectronic Processing Integration, September 1991: Leang, S., S-Y. Ma, J. Thompson, B. J. Bombay, and C. J. Spanos. "A Control System for Photolithographic Sequences." IEEE Trans. Semicond. Manuf. 9, no. 2 (1996): 191–207. Toprac, A. Run-to-Run Control of Poly-Gate Etch SEMATECH Advanced Equipment and Process Control Workshop, 434–40. Lake Tahoe, CA: SEMATECH, 1997. Gerold, D. "Run-to-Run Control Benefits to Photolithography." SEMATECH Advanced Equipment and Process Control Workshop. 104–12. Lake Tahoe, CA: SEMATECH, 1997, suppl. Stefani, J. A. "Practical Issues in the Deployment of a Run-to-Run Control System in a Semiconductor Manufacturing Facility." The 1999 SPIE International Symposium on Microelectronic Manufacturing Technologies. Edinburgh, Scotland, May 1999. Hunter, J. S. "The Exponentially Weighted Moving Average." J. Qual. Technol. 18 (1986): 203–10. Box, G. E. P., G. M. Jenkins, and G. C. Reinsel. Time Series Analysis: Forecasting and Control. Englewood Clifs, NJ: Prentice Hall, 1994. Butler, S. W., and J. Stefani. "Supervisory Run-by-Run Control of Polysilicon Gate Etch Using In Situ Ellipsometry." IEEE Trans. Semicond. Manuf. 7, no. 2 (1994): 193. Butler, S. W., J. Stefani, M. Sullivan, S. Maung, G. Barna, and S. Henck. "An Intelligent Model Based Control System Employing In Situ Ellipsometry." J. Vac. Sci. Tech. A, 12, no. 4 (1994): 1984–91. Marlin, T. E., and A. N. Hrymak. "Real-Time Operations Optimization of Continuous Processes." In Proceedings of the Fifth Conference on Chemical Process Control (CPC V) Assessment and New Directions for Research. AIChE Symposium Series No. 316, Vol. 93, 156–64. CACHE, American Institute of Chemical Engineers, 1997. Harris, T. J., and J. F. MacGregor. "Design of Multivariate Linear-Quadratic Controllers Using Transfer Functions." AIChE J. 33 (1987): 1481–95. Smith, T., D. Boning, J. Stefani, and S. W. Butler. "Run by Run Advanced Process Control of Metal Sputter Deposition." IEEE Trans. Semicond. Manuf. 11, no. 2 (1998): 276. Bohn, R. "The Impact of Process Noise on VLSI Process Improvement." IEEE Trans. Semicond. Manuf. 8, no. 3 (1995): 228–38.
Further Reading Conferences and Supporting Organizations Integrated Metrology Consortia, http://www.integratedmeasurement.com Electrochemical Society, Inc., http://www.electrochem.org American Vacuum Society (AVS) Manufacturing Science and Technology Group (MSTG), http://www. cems.umn.edu/wweaver/mstg/mstgsubway.html International Symposium on Semiconductor Manufacturing (ISSM), http://www.issm.com Advanced Semiconductor Manufacturing Conference (ASMC), http://www.semi.org/Education/asmc/ main.html SPIE Microelectronic Manufacturing, http://www.spie.org/info/mm
SC Control and Control Software University of Michigan Controls Group, http://www.engin.umich.edu/research/controls Berkeley Computer Aided Manufacturing (BCAM), http://bcam.berkeley.edu Maryland University The Institute for Systems Research, http://www.isr.umd.edu SEMATECH and MIT Run by Run Benchmarking, http://www-mtl.mit.edu/rbrBench Triant Technologies Inc., http://www.triant.com Semy, http://www.semyh.com ObjectSpace, http://www.objectspace.com Domain Manufacturing Corp. (formerly, BBN Domain Corp; acquired by Brooks Automation 6/99), Cambridge, MA, http://www.domainmfg.com Umetrics, Winchester, MA, http://www.umetri.se (also good Chemometrics links). Brookside Software, http://www.brooksidesoftware.com Brooks Automation, Richmond, BC, Canada, http://www.brooks.com/bac.htm Fastech (Acquired by Brooks Automation 9/98), http://www.fastech.com Real Time Performance, Sunnyvale, CA, http://www.rp.com (no longer in business, but has code). Adventa (ControlWORKS, ProcessWORKS, WORKS), Dallas, TX, http://www.adventaCT.com Voyan Technology, Santa Clara, CA. PRI Automation, Inc., Billerica, MA, http://www.pria.com Bakshi, V. Fault Detection and Classification (FDC) Software Benchmarking Results, SEMATECH Technology Report 97123433A-TR, 1998. Bakshi, V. Fault Detection and Classification Software for Plasma Etchers: Summary of Commercial Product Information. SEMATECH Technology Report 97083337A-XFR, 1997.
Manufacturing Execution Systems (MES)/Computer Integrated Manufacturing (CIM)/Equipment Integration Automation: Software Used to Run and Track Fab, Perform SPC, etc. Fastech (Acquired by Brooks Automation 9/98), http://www.fastech.com Real Time Performance, Sunnyvale, CA, http://www.rp.com (no longer in business, but has code). Consillium (Acquired by Applied Materials), http://www.consilium.com Promis (Acquired by PRI Automation), http://www.promis.com
Byrd, T. and A. Maggi. "Challenges to Plug and Play CIM." Future Fab Int.: 77–81. Greig, M. and A. Weber. "AMD & ObjectSpace, Inc." Future Fab Int.: 73–74. Data Analysis, Data Warehousing, Data Mining, Bit Mapping, Wafer Tracking, etc. Knight's Technology, Sunnyvale, CA, http://www.knights.com DYM, Bedford, MA, http://www.dym.com LPA Software, South Burlington, VT, (802) 862-2068. Quadrillion, Company Information, http://www.quadrillion.com/quadinfo/htm Device Ware Corporation, http://www.dware.com Maestro, Data Management [JJT Inc.], http://www.jjt.com/data.man.html Sleuthworks, http://www.sleuthworks.com/doc SAS, http://www.sas.com NIST and SEMATECH have created an Engineering Statistics Internet (ESI) Handbook. Check the SEMATECH web page or contact Chelli, [email protected]
General Semiconductor References That May Contain Control References on Occasion SEMATECH, www.sematech.org I300I (dedicated to 300 mm issues), www.i300i.org National Technology Roadmap, http://www.sematech.org/public/roadmap/index.htm Semiconductor Subway, http://www-mtl.mit.edu/semisubway.html Semiconductor Equipment and Materials International (SEMI), http://www.semi.org Semiconductor Research Corporation (SRC), http://www.semi.org Semiconductor International, http://www.semiconductor-intl.com Solid State Technology, http://www.solid-state.com Semiconductor Online, http://www.semiconductoronline.com Semiconductor SuperSite.Net, http://supersite.net/semin2/docs/home.htm FabTech, www.fabtech.org TechWeb, http://www.techweb.com Semiconductor Process Equipment and Materials Network, http://www.smartlink.net/wbmcd/semi/cat. html semiconductor.net–The semiconductor manufacturing industry resource for products, services and information, http://www.semiconductor.net SemiSource, Semiconductor Resource Guide, published annually by Semiconductor International. Solid State Technology Resource Guide, published annually by Solid State Technology. American Vacuum Society (AVS) Buyers Guide, http://www.aip.org/avsguide
Additional Compensation Control and Controller Monitoring Articles C Kraft. U.S. patent 5,528,510, Equipment Performance Apparatus and Method, issued 6.19.96. Harris, T. J. "Assessment of Control Loop Performance." Can. J. Chem. Eng. 67 (1989): 856–61. Scher, G. M. "Wafer Tracking Comes of Age." Semicond. Int. (1991): 126–31. Stefani, J. A. "Practical Issues in the Deployment of a Run-to-Run Control System in a Semiconductor Manufacturing Facility." The 1999 International Symposium on Microelectronic Manufacturing Technologies. Edinburgh, Scotland, May 1999.
In-Line Metrology 24.1 24.2
Measurement Precision to Process Tolerance Ratio vs. Resolution † Manufacturing Sensitivity Analysis
Metrology for Lithography Processes: Critical Dimension Measurement and Overlay Control............. 24-5 Critical Dimension Measurement and Calibration Overlay Process Control
Alain C. Diebold SEMATECH
Metrology for Front End Processes............................... 24-20
Interconnect Process Control ........................................ 24-36
Ellipsometric Measurement of Gate Dielectric Film Thickness † Electrical Measurement of Gate Oxide Thickness † New Methods of Measuring Gate Dielectric Thickness and Nitrogen Concentration † Doping Process Control † Metrology for Measurement of Stress Enhanced Carrier Mobility Interconnect Film Thickness † Ex-Situ Chemical Mechanical Polishing Process Control–Film Flatness and Quality
24.5 In-FAB FIB ...................................................................... 24-49 Acknowledgments ........................................................................ 24-49 References...................................................................................... 24-50
Abstract This chapter on ex-situ metrology covers the in-line and at-line measurements used to control processes in pilot line fabrication or in volume manufacturing of silicon based integrated circuits. Metrology for front end (transistor) processes, lithography, and on-chip interconnect fabrication technologies are all described. As a basis for further discussion, measurement precision and resolution are described, and the measurement precision to process tolerance ratio is used to evaluate metrology capability for statistical process control.
Metrology is an integral part of the development and manufacture of integrated circuits. The International Technology Roadmap for Semiconductors (ITRS) defines metrology as including both the off-line materials characterization and in-line measurement technologies [1]. In-line metrology is discussed in this chapter, while other chapters are devoted to other aspects of metrology. Other chapters of interest include those covering process control, off-line materials characterization, in-situ sensor based metrology, and defect detection and control technology. In-line metrology covers measurement needs for manufacturing control of transistor and on-chip interconnect fabrication including lithography. A high level view of the frequency of metrology 24-1
Transistor-> ∆L eff, ∆Vt, ∆Ioff
Implant dose Gate Ox thickness Poly Si control CD ILD thickness
Interconnect -> circuit delay, resistance
Contact etch control ILD etch control Metal thickness Defect /particle
Overview of the applications of metrology during integrated chip manufacturing.
measurements during manufacture is shown in Figure 24.1. First, the concepts of measurement precision and resolution are reviewed in Section 24.1. Section 24.2 covers critical dimension (CD) and overlay. Section 24.3 discusses gate dielectric thickness measurement and doping process control. Interconnect metrology is covered in Section 24.4, and other measurement tools such as focused ion beam (FIB) and scanning electron microscopy are briefly covered in Section 24.5.
Measurement Precision to Process Tolerance Ratio vs. Resolution
The measurement precision to process tolerance (P/T) ratio is an accepted metric for evaluating the ability of an automated metrology tool to provide data for statistical process control (SPC) [2]. While there is no generally accepted estimator for precision [3] an ideal measure for use in process control would be a function of the total measurement system error variability, s2M . A methodology for estimating P/T in this fashion can be found in SEMI E89, Guide for Measurement System Analysis [4]. Using this or a similar approach, major sources of measurement variability are enumerated and a designed experiment is employed to quantify the variance components associated with each source. s2M is a combination of the short term and the long term sources of variation. Repeatability, sr represents a lower limit to s2M . It is estimated by the sample standard deviation of repeated measurements made under identical conditions, or in the case of a designed experiment, as the square root of the mean squared error [3,4]. Reproducibility, sR, is the variation that results when measurements are made under different conditions such as reloading the wafer on a different day [3,4]. It may include multiple sources of variability and is expressed as the square root of the sum of the variance components for all sources of measurement system variation. Note: SEMI E89 treats repeatability as part of reproducibility, making s2M Z s2R . This approach is not universal. Some treat repeatability and reproducibility as mutually exclusive, in which case s2M Z s2R C s2r . Precision is calculated as CsM, where CZ6 is a common choice for processes with both upper and lower limits and CZ3 for processes with one-sided limits. Contamination limits represent a process with a one-sided (upper) process limit. Process tolerance is the range of allowed values of the process variable: upper process limitKlower process limit (ULKLL) for two-sided processes and (ULKT) or (TKLL), where T is a target value, for one-sided processes. The measurement precision, s, to P/T ratio is either: 6s/(ULKLL), 3s/(ULKT), 6s/(TKLL) [4]. Although P/T should be less than 10%, a value of 30% is often allowed. Unfortunately, the measurement precision used to determine P/T is often an approximation of the true precision. Determination of the true P/T ratio for the process range of interest requires careful
In-Line Metrology
implementation of the P/T methodology. This means that many of the measurement conditions should be varied to determine measurement stability before setting final measurement conditions when determining precision [4]. Varying time between repeated measurement allows one to observe short term issues with repeatability. In addition, reference materials should have identical feature size, shape, and composition to the processed wafer being measured. Often, there are no reference materials that meet this requirement, and P/T ratio and measurement accuracy are determined using best available reference materials. One key example is the lack of an oxide thickness standard for sub 5 nm SiO2 and nitrided oxides. When the reference material has significantly different properties (e.g., thickness), then the precision may not be representative of the precision associated with the product wafer measurement due to nonlinearity. Again, the example of CD or film thickness measurements is useful. The precision associated with measurement of a sub 2 nm gate oxide may be different than that associated with a 10 nm oxide film. If the true precision is large enough, it could mean that the metrology tool has insufficient resolution to distinguish changes over the process range of interest. One way to assure that the metrology tool has adequate resolution to determine the true P/T capability by using a series of standardized, accurate reference materials over the measurement range specified by the ULs and LLs. In Figure 24.2, we depict the difference between precision and bias. In Figure 24.3, we show how the multiple reference materials approach might work. This approach is not used. Instead, in-line metrology uses a reference wafer that is fabricated using the typical process flow. These "golden" wafers have exact materials and dimensions from the process step of interest. Often, only one suitable reference material is used for P/ T determination. The measurement of the thickness of the transistor gate dielectric at the 45 nm technology generation is expected to be difficult in the manufacturing environment. By the 45 nm technology generation, silicon oxynitride will be replaced by a higher dielectric constant material. Dielectric thickness will be written in terms of the thickness that the layer would have if it were silicon dioxide. This is known as the equivalent oxide thickness (EOT). For single layer films, the EOT can be calculated by multiplying the physical film thickness by the ratio of the dielectric constant of silicon dioxide (k(SiO2)Z3.9) to that of the high k material. For high k films with an interfacial layer of silicon dioxide of thickness tint, the EOTZ tintC(3.9/k)thighk. If the gate dielectric EOT is 0.7 nm thick and the process tolerance is 4% for 3s (process variation), then P/TZ10%Z6s/(0.1 nm) which gives a measurement variation 3sZ 0.0028 nm. The size of an atomic step on silicon is w0.15 nm and atomically flat terraces on specially prepared Si (001) are about 100–200 nm wide. The width of terraces after typical processing such as sacrificial oxidation and gate oxide growth is unknown. Thus, some have pointed to the issue of measuring film thickness to less than an atomic width. This is not an issue because the measurement can be considered to be the determination of the average thickness of a perfectly flat layer. This type of measurement precision requires analysis of a large area that averages over atomic steps at the interface
Bias in product wafer measurements X2ave
X2true
Bias and precision change due to non–linearity
Instrument calibration X1ave
Calibration bias
FIGURE 24.2 Measurement non-linearity measurement non-linearities can result in bias (difference between true and measured value) changes between the calibrated value and the range of interest. It is also possible that the bias can change inside the measurement range of interest.
Measurement variation (precision) of experimentally determined values of reference material
FIGURE 24.3 Demonstration of resolution based on precision associated with measurement of a series of reference materials over the process specification range for this example let us assume that the process tolerance (also called process specifications) is from 3.0 to 4.0 nm. The measurement precision at 3s (variation) is shown for reference materials inside the process range. The experimental P/T capability observed using reference materials 4, 5, and 6 indicates that a single measurement of a 3.6 nm is different from one at 3.5 or 3.7 nm. Thus this fictitious metrology tool can resolve those values. According to the precision shown for reference materials 2 and 3, the tool is not able to resolve 3.2 nm from 3.3 nm at 3s.
and other atomic variations. Local variations in thickness of a 2 nm film will be a much larger percentage of total thickness than it would be for a 10 nm film. Therefore, reproducibility of stage location affects the precision of a thickness measurement especially for a small sampling area around 1 mm in diameter. Some metrologists have called for smaller area (!1 mm) measurements. The need for high precision makes this very difficult and high precision with small spot instruments (0.9 mm) are achieved by averaging over a larger area. Even electrical measurements done using capacitors average over larger areas. For contamination measurements and a P/TZ30%, sZ(ULKL)/10. Achieving a measurement variation of (ULKL)/10 requires that the detection limit must be at or below (ULKL)/10 [3]. Chemists have their own definitions of resolution, detection limit, and quantifiable detection limit which must all be considered [5]. For convenience, these topics are illustrated by discussing off-line chemical analysis of trace contaminants in a liquid. Typically, the detection limits for trace amounts of contamination in a liquid vary due to changes in measurement sensitivity. Detection limits are ultimate values for optimum circumstances. When the liquid is analyzed by inductively coupled plasma mass spectrometry (ICP-MS), the detection of one element can be interfered with by the presence of another element. The quantifiable detection limit is the limit at which reliable, repeatable detection is possible [5]. Resolution requirements are not well defined, and thus experience again provides some guidance.
Manufacturing Sensitivity Analysis
Ultimately, the electrical performance of the integrated circuit results from the electrical properties of the transistors and the interconnect structures. The most extensive modeling of how variations in physical properties affect electrical performance has been done for transistors [6]. The effect of small changes in key physical parameters such as gate length, gate dielectric thickness, and doping dose on key electrical parameters such as leakage current and threshold voltage were modeled for a 180 nm transistor [6,7]. Although similar modeling has been done for subsequent generations of transistors, most results are not yet published. The goal was to determine the impact of an increase in the range of a variable on the range of the electrical parameters. Modeling for this purpose is known as manufacturing sensitivity analysis. This type of information is often helpful in prioritizing metrology and understanding the electrical impact of process variation. Another type of model-based sensitivity analysis has been used to relate the electrical test signature to physical defect type for interconnect structures [8,9]. This is sometimes called defect to fault mapping.
It is usually associated with off-line materials characterization and failure analysis laboratories that employ FIB systems, and thus it is not discussed at all in this chapter.
24.2 Metrology for Lithography Processes: Critical Dimension Measurement and Overlay Control Critical dimension and overlay measurements control two of the most important parts of manufacturing: feature delineation and the stacking of layers. In this section, CD and overlay measurement technology and application are reviewed. Detailed chapters on each CD measurement method and on overlay measurement can be found in the Handbook of Silicon Semiconductor Metrology [10]. Control of CD including line edge roughness (LER) across the die and across the wafer starts with control of the range of CDs across the photomask. Since photomasks have glass substrates, they easily charge during scanning electron microscopy based CD measurement. Thus, CD measurements on photomasks requires special considerations which are discussed below. CD metrology is also done on the patterned photoresist structures as well as after the features are etched. Issues associated with these measurement steps are also covered.
Critical Dimension Measurement and Calibration
Today, both critical dimension scanning electron microscopes (CD-SEM) and scatterometry are used during volume manufacture to control the process range for line width and contact via diameter (area). Cross-sectional SEM images and CD-SEM are used to evaluate process conditions after a change in recipe. Electrical measurement of the effective transistor gate length and metal line width are also done using test structures. Electrical measurements support tighter control of electrical transistor parameters that is possible with current physical CD-SEM measurements. Lithography process control using CD-SEM or scatterometry measurements can be done after exposure and development of the resist, thus permitting reprocessing of wafers that have CD values outside of process tolerance limits. CD is also measured after etch of the poly-silicon transistor gate or the trenches and vias used for interconnect. In this section, we will discuss CD-SEM and scatterometry tool and measurement issues, calibration, and electrical CD measurement. 24.2.1.1
CD-SEM Tools and Measurement Issues
A CD-SEM is a scanning electron microscope that has been designed for low voltage (!w1 keV) measurement of line width. In Figure 24.4, we illustrate the operation of a CD-SEM. In Figure 24.5, show a typical CD-SEM design. Conventional wisdom leads one to believe that low voltage operation is the only way to prevent damage to the integrated circuit (IC) chip, and at this time, commercial CD-SEMs operate at voltages between roughly 1 keVand a few 100 eV. Although CD-SEMs differ from in-line and laboratory SEMs in that very short working distances (distance between wafer and SEM electron beam lens) are used to optimize rapid, low voltage imaging, new lens designs are reducing the differences between systems [11]. In order to maintain optimum and reproducible fields over the sample, sample tilt is not used in CD measurement. Recently introduced CD-SEMs have become more capable of measuring sidewall angle. Using the electron lens to tilt the electron beam, sidewall shape and angle can be measured as discussed below. Multiple angles allow determination of sidewall angle through geometric considerations. This increases the rate at which the sample stage can scan the wafer. Precision sample stages that can locate specific wafer coordinates combined with image pattern recognition capability allow automated CD measurement at specific locations on selected die across the wafer. Two components of the SEM hardware are considered key to higher resolution and greater CD precision. First, the final electron beam lens has been designed so the magnetic field extends beyond the lens and around the part of the sample being imaged. This type of lens is referred to as an external extended field lens or snorkel [12]. The second development is the advanced secondary electron detector. The extended field also collects the secondary
FE source
Top down image
Secondary electron detector Scanning coils wafer
Lens Sample stage
FIGURE 24.4 How a critical dimension scanning electron microscope (CD-SEM) works. A line scan is averaged over a length of the measured line using a specially designed SEM. The increase in secondary electron intensity at the line edge is shown. The emitted electron regions are highlighted in green. Emitted electron intensity is the largest at the edge of a line (point 1) and the least at a flat surface (point 2). Sharp features such as the line edge have more surface area for electron emission. More emitted electrons (point 3) will come from sidewalls than from flat areas (point 2).
electrons which are then passed through a Wein filter that results in energy dispersion prior to detection [13]. This allows the ultra rapid collection at 5! to 10! television (TV) scanning rates. A discussion of the origin of the CD-SEM signal and its interpretation as a line width will assist understanding CD-SEM measurements. A recent review of SEM based CD measurement, calibration, and SEM matching is a recommended Ref. [13]. A line trace of detected electron intensity vs. sample position, a SEM image of a line structure and a SEM cross-section of a line structure are shown in Figure 24.4. Both low energy secondary electrons and backscattered (inelastically) scattered electrons can be used separately or in combination to produce an image. Secondary electrons are low energy electrons emitted from the valence band of the sample after excitation by the primary electron beam [14], and they are often labeled as SE-1 electrons [13,14]. The SE-1 yield is a function of the sample material, sample shape, and the energy of the primary electron beam. Sharp features and side walls will be able to emit more secondary electrons than a flat surface. The secondary electron coefficient is a measure of the number of secondary electrons per incident electron from the primary beam. For most materials, the secondary electron coefficient peaks between 1 and 2 keV electron beam energies [13]. Electrons that scatter off sample atoms and out of the sample are known as backscattered electrons [13]. Some of these electrons will have lost energy through typically several collisions inside the sample and are thus inelastically scattered. Some authors [13,14] refer to these electrons as SE-3 secondary electrons, and others seem to prefer not designating these as secondary but as backscattered electrons [13,14]. Other backscattered electrons, known as elastically scattered electrons, hit atoms close to the surface and escape before any energy is lost. These electrons are referred to as SE-2 by some authors [13]. There will be more backscattered electrons from small sharp features and sidewalls than flat surfaces. The emitted electron intensity will be higher at the edge of the line structure as shown in Figure 24.4. In older CD-SEMs, the detected signal is a combination of both the low energy secondary electrons (SE-1) and the backscattered electrons (SE-2 and SE-3). The way in which these contributions are mixed will determine the shape of the signal and how well the line edge algorithm is able to measure line edge. The signal shown in Figure 24.4 demonstrates that one cannot interpret the signal intensity in terms of the sample height. The peak intensity cannot be interpreted as the line edge position [14,15]. Critical dimension measurement is done by averaging over a large number of line scans across a length of line deemed representative. (The SEM image is composed of many line scans with the vertical
Schottky emitter Anode Gun alignment Final aperture Aperture alignment Aperture lens Stigmator
Magnetic lens Electrostatic lens
FIGURE 24.5 Diagram of CD-SEM lens. Applied materials CD-SEM uses a combined electrostatic/magnetic lens and has a through the column emitted electron detector. Figure courtesy Bob Burkhardt of applied materials.
(or horizontal) position of each scan moved by a known increment.) This averages out some of the edge roughness effects and sample variation. At the time of writing this chapter, many different methods of determining edge position exist, and each supplier can chose a method that optimizes the precision of their own instrument. Some of the algorithms are shown in Figure 24.6. It has been shown that the linewidth can vary by 100 nm according to the algorithm selected [12]. Clearly, CD-SEM measurements must be calibrated by a method that is more independent of sample shape and line materials. The above paragraph points to the need for a standardized algorithm so that measurement equipment can be matched. This is critical for manufacturing metrology. The above discussion also points to the need for a fundamental model that relates the true feature shape to the signal inside the CD-SEM [15]. Through Monte Carlo modeling, the secondary electron intensity of a linescan can be related to lineshape. In addition, the effect of the width of the electron beam can be removed. This modeling has also been used to improve the CD precision (nist paper and Schlumberger paper). The use of very low
Fermi fit
Intensity counts
Linear approx
Derivative midpoint
Scan position (nm)
FIGURE 24.6 The algorithm used for determining the line edge impacts the measured value of line width. The red line is the signal from the SEM line scan. Three algorithms are shown: linear approximation, Fermi Fit, and derivative method. Figure 24.6 first appeared in reference 12, and it was used with the authors' permission.
voltages also changes linescan shape as shown in Figure 24.7. Once again, the algorithm that extracts linewidth from linescan information must be altered to allow for changes in linescan shape. Over the past several years, printed linewidth has fallen below 50 nm. These resist features often have rounded tops, and a line scan over this type of feature does not have the same shape as larger rectangular lines. This is shown in Figure 24.8. In order to determine linewidth, new algorithms were developed. These algorithms use the same sort of edge determination approach as that used for measurement of beam width using a sharp edge feature [16].
Pixel position
Plot Intensity
FIGURE 24.7 Line scan shape change during ultra low voltage CD-SEM. Decreasing voltage has a significant change in the linescan intensity vs. position. The high intensity "lobes" normally observed at the line edge disappear at ultra-low voltage. Figure courtesy Neal Sullivan (Schlumberger).
Impact of round topped resist lines on CD-SEM line scan.
Line shape information is critical to further processing and device performance. Formation of transistor source/drain and low dose drain features is done by implantation with the poly-silicon gate acting as a mask, and thus changes in shape can alter the implanted structure thus changing the transistor's electrical performance. Metal line resistivity can be effected by changes in line shape. Although modeling methods exist, the most used methods of controlling lineshape are the tilt beam CD-SEM and scatterometry. In Figure 24.9, we show the determination of line shape from tilt beam CD-SEM [17]. Other approaches include critical dimension atomic force microscope (CD-AFM) and destructive analysis using dual column FIB. Marchman has shown the effect on CD value associated with the density of lines in the measurement area [12]. Additional charging is sometimes observed for dense lines. The effect varied with SEM supplier, and one SEM had a 20 nm change in measurement offset. The variation in offset with SEM model was attributed to different electron beam energies. The effect of line density can be minimized by selecting the appropriate electron beam voltage for each process step [12]. The effect of the electron beam on 193 nm KrF photoresist is well documented. Due to the large variety of photoresist and antireflective coating materials, the amount of shrinkage due to exposure to the electron beam is a function of materials as well as beam energy and dosage. Photoresist shrinkage can be minimized by using measurement recipes (procedures) that reduce exposure of the measured line or via to the electron beam and by optimizing the beam energy. Many different measurement schemes have been proposed for removing the effect of resist shrinkage from the data. These include measuring the feature from twice to several times before taking the final CD measurement. Recent reports indicate that photoresist shrinkage can be reduced or eliminated by using ultra-low (w100 eV) voltage CD-SEM [18]. Measurement and control of LER and line width roughness (LWR) are becoming more critical as the transistor gate length scales. Establishing a single definition of each of these quantities is difficult since standard definitions are under consideration. In that light, the definitions used in the 2003 ITRS were selected as a start. The LWR is 3s of the CD over the spatial frequencies associated with the pitch and the drain extension [1]
1 1 ; % spatial frequences% P 0:5Xj
500 400 300 200 100 0 –50
Side wall reconstructed by stereoscopic analysis
FIGURE 24.9 materials.
Tilt beam CD-SEM allows the reconstruction of lineshape figure courtesy Bob Burkhardt of applied
The goal was to distinguish between line width and CD changes. Although this defines the spatial frequency range used to calculate LWR, it does not define the length of line that must be used to determine these frequencies. Given the highly statistical nature of roughness, sampling of line segments [ than the pitch will be necessary while sampling scan lines !5 nm apart [19]. 24.2.1.2
CD-SEM Focus, Calibration, Tool Matching, and Manufacturability
A unified specification for CD-SEM technology has been developed for the sub 130 nm technology nodes [20]. This reference provides a broad overview of how one can judge the manufacturing compatibility of a CD-SEM. CD-SEM measurements are calibrated using reference materials, CD-AFM, comparison to crosssectioned samples, and correlation to electrical linewidth measurements. We describe each method below. SEM performance criteria include beam diameter, resolution, and sharpness [14]. The Fourier transform of a SEM image is a powerful means of monitoring sharpness [14]. The usefulness of this methodology has been demonstrated in a production environment [21]. CD-SEM magnification is calibrated using a reference material such as the NIST Standard Reference material 2090 [12]. Recently, NIST and Sandia National Laboratory have developed a CD reference material for physical and electrical CD measurement [22]. The test structure is both a microelectromechanical system, and an electrical test structure, and has specially etched, sharp sidewalls so that it can serve as a reference material for CD-SEM or CD-AFM. Since SEM measurements are strongly effected by the material (photoresist vs. poly silicon gate vs. TiN/Al/TiN vs. W/TiN), multiple reference samples
AFM line scan for undercut line ,,
Needle tip
Cylinder tip
Boot tip
FIGURE 24.10 Probe tip shape greatly affects the observed atomic force microscope (AFM) image. There are samples where the cylindrical tips provide superior images. The cylindrical tip shape is expected to be the only mechanically stable tip shape for analysis of dense 100 nm features. Both etched fiber optic tips and carbon nanotubes are being investigated. (See from Dia, et al., Nature, 384, 147, 1996.)
provide optimum process control. A single reference material is considered appropriate for checking SEM drift and CD-AFM precision [22]. Commercialization of this reference material was not complete when this chapter was written. Martin and Wickramasinghe pioneered the application of atomic force microscopy to lithographic metrology needs [23,24]. Griffith [25–27] and Marchman [28,29] have shown the utility of CD-AFM calibration of CD-SEM measurements. Ideally, CD-AFM measurements are independent of sample material. When the CD-AFM is itself well calibrated, it should provide the accuracy and precision required for CD-SEM calibration. An ASTM standard for characterizing probe tip shape is now available [30]. This is a critical part of maintaining measurement reproducibility. The CD-AFM measurement precision has been discussed in the literature [31]. Using "boot tips" (see Figure 24.10), the precision
Isolated lines
10 VNDA MOD1
VNDA MOD2 VNDB ETCH_Ox
DUV_OX
DUV_Poly
DUV_SI
ILIN_SI
0 DECA
SEM-AFM Delta (nm)
–10 Process level
FIGURE 24.11 The effect of materials changes on CD-SEM offset was found to be a function of CD-SEM equipment model. Each SEM uses different primary beam voltages. Taken from reference 2.3 and used with the author's permission. Figure courtesy Hershel Marchman.
360 350 340 330 320 310 300 290 280 270 260 250 240 230 220 210 200 190 180 170 160 150 140 130
X-Section dense KLA8100 Iso X-Section Iso CD=09.137 (KLA8100)–26.012
CD=KLA8100-50
KLA8100 dense
FIGURE 24.12 Calibration of CD-SEM using SEM cross-sectional data. Data for both isolated and dense lines show the same off-set over a broad range of linewidths. Figure courtesy Arnie Ford.
s was found to be 2 nm for the top of the line and 1.5 nm in the middle of the line [31]. Height measurement precision was 0.5 nm and side wall angle was 0.218 for the left wall. In Figure 24.10, we show schematically how probe tip shape effects a line scan across an undercut line. This illustrates the relationship between the AFM image and the sample. The specific relationship will be different for each type of probe tip shape (e.g., sharp pointed tips vs. rounded boot tips). Calibration of CD-SEM requires that the CD-AFM have greater accuracy than the CD-SEM and appropriate precision. The different CD-SEM offsets associated with different materials found at subsequent lithographic process steps are shown in Figure 24.11. Cross-sectional SEM is an effective method of calibrating CD-SEM. CD-SEM calibration is done across a range of linewidths as shown in Figure 24.12. Calibration data for both isolated and dense lines both show a constant offset from 350 to 130 nm linewidths. In an effort to provide greater statistical significance, CD-SEM algorithms now allow for determination of linewidth for several lines in the image field. As the number of lines in this field increases, the average CD in the field provides identical information to scatterometry. Projecting into the future when it may be possible for both methods to sample the same number of lines in a measurement area, there will be one key difference between scatterometry and CD-SEM other than time per analysis area. The CD-SEM will be capable of providing the range and average of the local distribution of CD values. This development will be closely followed by the metrology community. 24.2.1.3
Scatterometry
Scatterometry refers to the use of scattered light to determine lineshape and CD. There are two main approaches to scatterometry, and Raymond's review is recommended [32]. In the single wavelength, multi-angle method, light is scattered from a grating test structure and collected at a series of angles [33]. The intensity maximums of diffracted light occur at angles that depend on the shape and width of the lines making up the grating structure. The polarization dependence of the data is often significant. This method requires specialized equipment for data collection. In the single-angle multi-wavelength method,
the reflected intensity versus wavelength also depends on linewidth and shape [32]. This is schematically shown in Figure 24.13. Commercial spectroscopic ellipsometers (SEs) found on in-line optical metrology systems can record the multi-wavelength single angle data. This method is also known as phase profilometry. This is schematically shown in Figure 24.14. In both methods, intensity of the reflected light is compared to a library of scattering patterns that simulate linewidths and feature shapes. Recently, computational improvements have allowed calculation of feature shape and CD without libraries. In Figure 24.13, we show both approaches to scatterometry. In order to provide an overview of scatterometry, it is useful to start with the scattering or diffraction of light from a regularly spaced grating structure [32]. The intensity of the diffracted light occurs at specific angles given by the well known grating equation:
sin qi C sin qn Z n
l d
where qi is the angle of incidence, qn is the angular location of the nth diffraction order, l is the wavelength of incident light and d is the spatial period (pitch) of the structure [32]. Very careful analysis of the diffraction pattern allows one to directly determine lineshape and width and the thickness of patterned features and the some of the layers below [32]. In order to fully interpret the scattering patterns, a series of scattering patterns are simulated for a range of feature shapes and dimensions using the Rigorous Coupled Wave Approach [32]. The single wavelength, multi angle approach is known as "2-Q" scatterometry [32]. The second method of scatterometry, single angle–multi wavelength, has two major variations. In one variation, an SE is used to measure the usual parameters D (called "Del") and J using a diffraction grating as a target [33]. These parameters are defined below in the section on ellipsometry. The changes in D and J from that expected for an unpatterned film stack allow determination of the average line shape and CD over the measured area. The second method is to use a perpendicular optical path for a reflectometer equipped with polarized light [34]. The second method requires that the parallel and perpendicularly polarized light be oriented relative to the lines in the diffraction grating.
Scanner Variable Qd Variable Qi
Moveable detectors
Scattered light intensity
Diagram of single wavelength–multi angle scatterometry measurement of critical dimension (CD).
Mirror Q in = Qout Multi-wavelength light source
Polarization sensitive detector
Incident polarized white light 0th order
FIGURE 24.14 Diagram of multi wavelength–single angle scatterometry measurement of CD in-line spectroscopic ellipsometers can be used to measure CD.
As shown in Figure 24.14, the average line shape can measured with a great amount of detail with all forms of scatterometry. Since it is an optical method, all forms of scatterometry can be done quickly allowing more rapid throughput when compared to other methods. When comparing scatterometry to CD-SEM, it is important to note that scatterometry measures the average CD while CD-SEM measures one value from the average. Unpublished reports have proposed the need to average from 10 to O50 individual lines (measured by CD-SEM) to determine an average CD that tracks the average measured using scatterometry. There are many difficulties associated with direct comparison of CD-SEM and scatterometry including the need to determine exactly where along the line to compare (top vs. middle vs. bottom) [35]. 24.2.1.4
Application of CD Metrology
CD measurements can be applied at a number of steps during the fabrication of shallow trench isolation, the transistor gate electrode, and interconnect Damascene patterning. For example, CD can be measured in the patterned photoresist, after the resist is trimmed and/or after the poly-silicon is etched. The use of scatterometry combined with advanced process control methods for run to run process control at the etch steps are reported to provide much tighter control of the electrical properties of transistors such as the saturation drive current [36]. Since scatterometry determines film thickness too, the shape and depth of shallow trench isolation can be determined before oxide fill. At this time contact and via CD are done using SEM, and CD-SEM is also used during transistor fabrication. Thus, scatterometry is used to supplement CD-SEM by providing tighter process control at certain key steps. Another function of CD metrology is to determine process tolerance ranges after a change in process recipe. The combination of CD-SEM with cross-sectional CD measurements enable control of sidewall
profile and linewidth. Scatterometry has been applied to control of lines during focus exposure, and dual column FIB has been applied to contact/via control. A recipe change is illustrated by an exposure vs. focus matrix for isolated and dense 250 nm lines respectively in Figure 24.15 [37]. The optimal process range is highlighted for isolated and dense lines. This data was taken after a double post-exposure bake process. In Figure 24.16 the effect of different post exposure bakes for this two bake step process are shown. CD-SEM data is correlated to cross-sectional data from the exposure matrix, and CD-SEM is then used for SPC.
250 nm isolated lines Nominal feature: 225 nm Isolated
UVIIHS double PEB study 125°C/80s PEB#1+140°C/20s PEB#2
Exp (mJ×cm–2)® focus (mm)– –0.1
Feature size +0.1
Feature size
(a) 250 nm nested lines Nominal feature: 225 nm nested Exp (mJ×cm–2)® focus (mm)–
UVIIHS double PEB study 125°C/80s PEB#1+140°C/20s PEB#2 8.775
–0.1 Feature size +0.1 Feature size +0.3
FIGURE 24.15 Cross-sectional CD analysis of a process recipe using (a) isolated and (b) dense lines figure courtesy John Petersen based on a figure from Ref. [37].
Summary table of double PEB test with UVIIHS TEST PAB PEB#1 PEB#2 Nested lines number 90s °C °C#1 s#1 °C#2 s#2
Bias (nm)
FIGURE 24.16 Petersen.
Example of process set-up illustrated using a double bake resist process. Figure courtesy John
Electrical CD Measurement
There are two approaches to electrical measurement of line width. The effective transistor gate length can be determined from the transconductance of the transistor. Another approach is to measure the electrical properties of a test structure such as the cross-bridge resistor test structure, which is shown in Figure 24.17. The electrical line width is determined by first measuring the sheet resistance of the van der Pauw resistor and then measuring the resistance of the bridge resistor. To be more specific, we refer to Figure 24.17 and the description of Ref. [38]. A current I is placed between pads 4 and 3 and the voltage VC 1 is measured is measured. Then the between pads 5 and 2. The polarity of the current is then reversed and voltage VK 1 current I is placed between pads 3 and 2 and the voltage VC is measured between pads 4 and 5. The polarity 2 is again reversed and voltage VK is measured. The sheet resistance is calculated using [38]: 2
Rs Z
K C pðjV1Cj C jVK 1 j C jV2 j C jV2 jÞ 4I ln 2
Cross–bridge resistor test structure
Cross-bridge resistor electrical test structure for CD measurement.
The bridge resistance is calculated from voltage measurements between pads 5 and 6 while a current is placed between pads 1 and 3. VC b is the voltage for current placed between pads 3 and 1, etc., From this the electrical linewidth can be calculated using:
Rb Z
ðjVbCj C jVK R L b jÞ line width W Z b 2Ib Rs
L is the length between pads 5 and 6. In-line electrical CD measurements of test structures on product wafers have been used to control CD during volume manufacture. Automated, in-line electrical probers equipped with camera and pattern recognition are combined with automated electrical measurement systems. A high correlation of CD-SEM and electrical CD measurements has been observed. In one study, correlation coefficients of at least 0.99 were found for both poly-silicon lines and aluminum lines coated with anti-reflective coating (ARC), the slope of both lines indicated that the CD values from the CD-SEM were wider than the electrical measurements [39]. The transconductance, gm, of a transistor provides another measure of electrical gate length, Leff. Transconductance is defined as the derivative of the drain current with respect to the potential difference between the gate and source, VGS, at a constant potential difference between the drain and source [40].
gm Z
dId jV dVGS DS
Plots of the drain current vs. VGS show two different slopes, one at low VGS, and one after the transistor reaches saturation voltage, VSAT. Therefore, an ideal transistor will show two relationships between gm and Leff as follows:
gm Z fbVDS for VDS % VSAT or bVGT for VDS O VSAT g Here, b f1/Leff [40]. This type of CD measurement can be used to separate chips according to expected circuit speed due to line-width-induced gate delay.
Overlay Process Control
Overlay is the term used to describe the registration of the patterned structure in a layer with the patterned structure in the subsequent layer [41,42]. Most overlay metrology is done using an optical system that automatically evaluates how far from center the target pattern in the top layer is from the center of the target pattern in the layer below. Every lithographically patterned layer requires overlay control. Tight control of overlay is a critical part of IC manufacture of the three dimensional structures
Box-in-box overlay structures
(a) Misalligned overlay
Typical overlay patterns. Figure suggested by Chris Nelson.
that form the integrated circuit. Process levels with the smallest IC structures such as the transistor gate drive the metrology tool requirements for overlay. Optical overlay metrology requires test patterns that provide high contrast through the dielectric layer that separates the gate level from the first metal level and subsequently the metal levels from the metal level below. Overlay is used after each lithographic mask step except the first. Typical overlay patterns are shown in Figure 24.18a, and a misaligned box target is shown in Figure 24.18b. A cross-sectional view of an overlay box in box structure and the line structures is shown in Figure 24.19. In Figure 24.20, we show a block diagram of a lithographic stepper and misalignment errors associated with distance between reticle and lens, reticle flatness, and wafer rotation. Overlay must be checked inside each die (intrafield) and from die to die (interfield). Interfield comparisons are done using overlay patterns from the center of the die. In Figure 24.21, we show a wafer with a four point check of interfield errors. The lithographic stepper or step-and-scan tool must correct for translation errors, scaling (different size translation errors across the wafer), orthoginality (centering of overlay pattern), and wafer rotation (see Refs. [35,36]). In practice, a monitor wafer with overlay artifacts is run each day to check inter and intra-field errors. Advanced interconnect processes will challenge overlay process control. Overlay of chemical mechanical polishing (CMP) process steps is made difficult by the fuzzy image observed for the buried box structure. Separating the overlay error due to the stepper from the error in the overlay measurement is often difficult. The origin of the fuzzy image is shown in Figure 24.22. Overlay of Damascene processes is also difficult. The overlay metrology tool consists of a specially designed optical microscope, a camera with a digital detector, and the illumination source [41,42]
Cross-sectional view of box-in-box overlay structures Resist (top box structure) Oxide
Si wafer
Bottom box structure
Cross-sectional view of overlay box and line structures. Figure suggested by Chris Nelson.
Overlay errors Stepper diagram
Stepper diagram
Reticle
Distance error
FIGURE 24.20 Nelson.
Reticle not flat
Reticle not square
Relationship between lithographic stepper and misalignment errors. Figure suggested by Chris
Interfield overlay translation errors scaling is shown (ie., different error magnitude across the wafer)
Four point check of interfield errors. Figure suggested by Chris Nelson.
CMP overlay issues Top down view
Oxide Filled and polished area
FIGURE 24.22 Chemical mechanical polishing (CMP) issues for overlay measurement. Separation of overlay error from measurement error is difficult due to CMP induced edge fuzziness. Figure suggested by Chris Nelson.
Metrology for Front End Processes
Transistors continue to evolve rapidly. New materials will enable current CMOS, and new transistor designs such as the FINFET are expected to extend CMOS beyond the 22 nm node. One critical challenge facing the industry is scaling the properties of transistors such as switching speed. The properties of a CMOS inverter are often used to illustrate the relationship between the transistor's saturation drive current, Idsat, and the gate delay, tZCloadVDD/Idsat. The relationship between transistor characteristics and saturation drive current is a function of gate length. In long channel devices (CDO100 nm), saturation drive current was directly proportional to carrier mobility and inversely proportional to gate length and dielectric thickness. For ultra-short channel devices, the saturation drive current is proportional to the saturation velocity of the carriers, the transistor width, the capacitance, and on voltage. The electrical properties will transition between long and short channel behavior. Thus, 65– 32 nm node transistors will continue to use stress to improve carrier mobility, but the impact on saturation drive current will decrease. Fabrication of transistors requires a number of different processes including formation of isolation structures such as shallow trench isolation, growth of the gate dielectric, doping, and lithographic patterning of gate electrodes. A summary of the metrology steps found in typical from end processing are illustrated in Figure 24.23. In this section, the topics of gate stack film thickness and electrical measurements and dopant dose and junction measurements are discussed. A great variety of process methods are used to induce stress in the transistor channel, and each one requires a different approach to process control. Stress measurement is also reviewed. Gate dielectric thickness is routinely measured on patterned wafers using either multiple angle or SE. A recently introduced in-line x-ray photoelectron spectroscopy (XPS) based method is briefly described along with electron beam induced x-ray fluorescence (XRF). These methods have the advantage of determining nitrogen content. Electrical characterization of gate dielectrics includes non-contact corona based methods and traditional capacitance–voltage (C–V) and current–voltage (I–V) measurements. The ability of the non-contact
Pattern and implant wells
Shallow trench isolation
Pattern and gate dielectric
Pattern poly/metal implant LDD Barrier height gate leakage interfaces contamination Vfb
Sidewall profile
Etch rate selectivity
Silicon interface
Dopant activation Grain structure
Upper interfacial layer
Pattern and implant S/D
High K Dielectric
Lower interfacial layer
DRAIN Metal diffusion
FIGURE 24.23 Typical metrology steps used during transistor fabrication. Control of shallow trench isolation, implants for well formation, gate dielectric formation, low dose drain implants, and source/drain implants all require statistically significant measurements for process control.
methods to measure on patterned wafers is continuously evolving. Dopant dose measurements often require special test wafers, while junction measurements can be done on patterned wafers in special test areas. The use of metal gate electrodes instead of poly-silicon is predicted to occur below the 65 nm technology node, and it is briefly discussed here. The dielectric thickness is determined using a model of the optical properties of the film structure and the observed thickness value can depend on the size of the analysis area and the specifics of interface properties used in the model. Silicon oxynitride thermal films less than 2 nm in thickness and the contribution of the interface to optical and electrical properties is significant. The impact of adsorption of ambient contamination on the dielectric surface has required desorption of these films before optical thickness measurements. Electrical capacitance based measurement of effective dielectric thickness can be done using a fabricated capacitor structure or with equipment that makes the top of the capacitor through corona discharge or with the elastic metal tip approach.
Ellipsometric Measurement of Gate Dielectric Film Thickness
Ellipsometric measurement of film thickness is based on the change in polarization of light after reflection from the dielectric on the wafer surface. If the optical constants of the dielectric are known, the thickness can be determined using a model of the optical structure of the dielectric film on a silicon wafer. The theory of ellipsometric measurement is left to references such as Tompkins [43] and Jellison [44]. In order to better describe ellipsometric data, a brief summary is presented below. 24.3.1.1
The Theory of Ellipsometry
A brief description of elliptically polarized light and the phenomena of reflection and refraction facilitates the discussion of ellipsometry given below [43,44]. In Figure 24.24, a wave of light that is linearly polarized parallel to the plane of incidence to the sample surface is shown reflecting at an angle f. This wave is designated a "p" wave. Light that is polarized perpendicular to the plane of incidence is designated as "s" waves. When "p" and "s" waves are combined slightly out of phase, the light beam is elliptically polarized. If the phase difference is 908, the light is circularly polarized. In Figure 24.25, light is shown reflecting from an infinitely thick sample with complex index of refraction N2ZnKik where k is the extinction coefficient. The extinction coefficient is related to the adsorption coefficient of light, a, through the following relationship:
l a and IðzÞ Z I0 eKaz 4p
P Wave (parallel to plane of incidence)
Reflection of "p" polarized light from a sample surface.
Reflected light
Refracted light
N2 (Complex index of refraction)
Refracted vs. reflected light.
I(z) is the intensity of light at a depth z below the sample surface, and I0 is the initial intensity of light that enters the sample. Since ellipsometric measurement is based on the change in the elliptical polarization after reflection, we must relate the reflection coefficient to the film thickness. The Fresnel reflection coefficients for reflection from an infinitely thick sample for polarizations both parallel and perpendicular to the incident plane are: P r12 Z
N2 cos f1 KN1 cos f2 N2 cos f1 C N1 cos f2
s r12 Z
This leads to the complex, total reflection coefficients for a multi-layer stack:
RP Z
P Ki2b P e C r23 r12 P P Ki2b 1 C r12 r23 e
s Ki2b s e C r23 r12 s s Ki2b 1 C r12 r23 e
In Figure 24.26, we show the multiple reflections described by the Fresnel coefficients used above. The phase thickness b is related to the physical thickness by
d b Z 2p N2 cos f2 l The approximate nature of this model is illustrated by the transmission electron micrograph of a 3 nm thermal oxide film shown in Figure 24.27. The interface between the oxide and silicon substrate is not
N1 N2 N3
Reflection of light from a layered sample.
Gate oxide thickness
Si /SiO2 interface control
FIGURE 24.27 Transmission electron micrograph of a w3 nm silicon dioxide gate dielectric. This image illustrates the lack of a sharp interface between the oxide and substrate. Figure courtesy Bob McDonald.
sharp. A complete model for measurement of gate dielectric thickness includes the optical effect of the interfacial region. In addition, local thickness variations across the area and the size of a sub micron gate will be averaged in typical commercial measurement systems. Averaging over a large area results in sub 0.1 nm precision. Local thickness variations can result in threshold voltage variations. Total reflection coefficients for any model and optical constants of the oxide layer can be programmed into commercial, in-line systems. The ellipsometer actually measures the parameters D (called Del) and J. Del is the phase difference after reflection, D1KD2. Jis defined by the following equation:
tan J Z
jRP j jRs j
The fundamental equation for ellipsometry is:
Rp Z tan JeiD Rs
In Figure 24.28, we show how D and J change with thickness for a SiO2 film. After a thickness of 283.2 nm, the value of D and J will repeat. 24.3.1.2
Multi-Wavelength and Spectroscopic Ellipsometry
Gate dielectric thickness measurement requires exceedingly good precision. This has motivated the use of optical metrology systems that have multiple optical paths. These systems include single wavelength ellipsometers (SWE) for optimum precision for thin films, spectroscopic reflectometers for thicker films, and SEs for complicated films and film stacks. Some commercial ellipsometers use one of 4 single wavelengths for gate dielectric control. The commercial 4-wavelength systems use optics that simultaneously measures over a range of angles. Film thickness is determined in SEs by fitting D and J data taken at many wavelengths to a values calculated from an optical model of the sample.
For the film, n = 1.46
2600Å
240 Film-Free
200Å 400Å
600Å 20
800Å
FIGURE 24.28 Trajectory of Del and psi for silicon dioxide. This figure shows that psi and Del trajectory will repeat after 283.2 nm thus making film thickness determination ambiguous for thicker films. This is one of the reasons that multiple wavelengths are used in many film thickness tools.
Ellipsometric Systems
In Figure 24.29a–c, we show a block diagrams of multiwavelength and SEs. A rotating polarizer type ellipsometer is shown in Figure 24.29a since it is typical of the design used in many commercial systems. There are a variety of system designs, some of which incorporate a focus system that averages over a spread of angles as shown in Figure 24.29b and c. Precision requirements for ultra-thin gate dielectric measurement may drive the use of non-focused systems. Detailed technical descriptions of commercial ellipsometers are available from the technical literature [45–47]. 24.3.1.4
Optical Models for Thin Gate Films
The traditional model of an oxide layer on a silicon substrate is that of a single, flat layer that has a sharp interface with the silicon below. This layer has also been referred to as a slab. Although an interfacial layer with different physical and chemical properties is present after SiO2 or SiOxNy is grown, a comparison of the precision of optical models for SE systems has shown that including the interfacial layer usually results in a larger (worst) precision than modeling the entire film as a single layer (or slab) [48]. Attempts at modeling using an interfacial layer composed of a Bruggerman Effective Medium Approximation (BEMA) model, provides a better Goodness-Of-Fit to the experimental data but a larger precision [48]. These effects are due to too much of correlation between fit variables and usually result in unrealistic values. Alternative single layer models (without an interfacial layer) are used that provide better precision values without sacrificing the Goodness-Of-Fit. Since SWE provides improved (i.e., smaller values) precision for these thin films, the optical constant for a single SiO2 or SiOxNy layer is used. This approach assumes that the nitrogen concentration and depth profile remain uniform across the wafer and from wafer to wafer. The accuracy of oxynitride film thickness depends on the accuracy of the optical constants for that film. According to the ITRS, if the gate dielectric EOT is 1.0 nm thick and the process tolerance is 5% for 3s (process variation), then P/TZ10%Z6s/(0.1 nm) which gives a measurement variation 3sZ 0.004 nm. This precision can be achieved by desorbing the surface contamination layer that adsorbs on the wafer surface prior to measurement. A number of approaches have been made commercially available including use of infra-red laser irradiation and thermal desorption [49]. High-k dielectric materials are being investigated as potential replacements for silicon oxynitride. The optical properties of these films are highly variable according to the method of deposition and the process
conditions. Further, there are no well known tabulated form of optical constants available for films such as hafnium oxide or silicate. Therefore, to accurately model these types of films, a parameterized model is needed that gives the optical properties of the corresponding film for the necessary wavelengths. To date, the Tauc–Lorentz model has proven a suitable choice. This model combines the classical Lorentz oscillator and the Tauc expression for the band gap of amorphous materials to give a parameterized function that models the imaginary part of the dielectric function [49]. However, two problems appear to still exist with this model: (1) no current manufacturing capable SE is capable of implementing this type of optical model. (2) There is too little optical contrast between the hik layer and the interfacial layer, the Tauc–Lorentz model is unable to distinguish the two layers and usually combines the two thicknesses as one. Better models are being developed. 24.3.1.5
Resolution for Ultra Thin SiO2 and Alternate Dielectrics
For an SWE using a laser operating at 632.8 nm, a change in thermal SiO2 thickness of 0.1 nm results in a change in Dw0.258 for films that are between 0 and 10 nm in thickness. The change in J at a single wavelength is not a straight line function between 0 and 4 nm thickness (3.1). A commercial ellipsometer
Spectralaser optical system Four wavelength simultaneous multi-angle ellipsometry with UV reflectometry Fiber optics Shutters Deuterium lamp 458 nm argon lon laser 633 nm helium neon laser 780 nm laser diode 905 nm laser diode Spatial filter/Beam combiner Polarization modulator Video microscope Ellipsometer array detector
UV objective
Grating spectrometer (a)
Auto focus detector Analyzer prism Sample Focusing objectives
UV reflectometer detector
FIGURE 24.29 Block diagrams of several commercial ellipsometer designs. (a) Four wavelength, focusing, multiangle ellipsometer system made by Rudolph Technologies, Inc. Gate oxide thickness measurements can be made using only the 632.8 nm wavelength from the HENe laser. Figure courtesy J. Sullivan, Rudolph Technologies. (b) UV-1280SE spectroscopic ellipsometer system made by KLA-Tencor. The light source is a broad band Xenon lamp, and the ellipsometer is a rotating polarizer type. Figure provided by J.J. Estabil, KLA-Tencor. (c) Thermawave Optiprobe 5240 combined absolute ellipsometer (632.8 nm HeNe laser), spectroscopic ellipsometer (450–840 nm [W halogen lamp], and 210–450 nm [deuterium deep UV source]), beam profile reflectometer, beam profile ellipsometer, deep UV spectrometer (190–840 nm). Figure courtesy W. Lee Smith, Thermawave.
UV-1280SE optics schematic Sample detector
Lamp detector
DBS focus
Grating SE detector Pattern Rec
Xenon lamp SE focus flipper Fiber optic cable
Rotating polarizer
DBS Path UVSE Path
Auto focus detector
BPE
Wave plate
TV camera
Tungsten visible source
Shutter Deuterium DUV source
P polarization array detector
S polarization array detector
Quad cell detector
DUVSE and Spectrometer Array detector
Shutter Grating
675 nm laser
Flip mirror Polarizer
632.8 nm HeNe laser
Analyzer Rotating wave plate
AE detector 0.9 NA lens
Analyzer Rotating wave plate DUVSE path
(continued )
AE path
is capable of measuring changes in D and J of !0.018. Several groups have discussed the sources of measurement error which effect accuracy and precision [49–53]. An error of 0.058 in incident angle near 708 results in a small error in D of !0.028 and in Jof w0.18 when lZ632.8 nm [50]. Multiple wavelengths provide a method of averaging data that helps overcome errors. The Drude approximation predicts a linear change in D vs. thickness for thin (!10 nm), nonadsorbing (imaginary part of refractive index is small or zero) films of different refractive indices. Data for several films such as silicon dioxide and silicon nitride show that the parameter D (at lZ632.8 and 708 incident angle) increases as refractive index increases [43]. The real part of the refractive index of silicon nitride and titanium dioxide is larger than that of SiO2. Therefore, the resolution of ellipsometry to changes in a single layer film of these materials on a silicon substrate would be better than for SiO2. The refractive index of non-isotropic materials such as single crystal TiO2 must be accounted for, and an averaging procedure would provide the needed information for a film having randomly oriented grains. Since grain texture is process dependent, the optical constants of films made using new processes must be checked before using ellipsometry for process control. Thin dielectrics below 100A, Jhas been shown to be almost independent of thickness. Alternatively, D changes almost linearly with thickness. Furthermore, Dw0, for very thin dielectrics. Therefore, the sensitivity for thin dielectrics is with D. The SWE that use a Rotating Compensator has an intensity output proportional to Sin D. Considering the small angle approximation (Sin DwD), any resolution of thickness changes for thin dielectrics, will be detected using SWE with a Rotating Compensator. 24.3.1.6
Poly Si Thickness
The issues associated with single wavelength measurement of poly-crystalline silicon thickness have been discussed in the literature [43]. Optical wavelength ellipsometry is hampered by the fact that silicon is adsorbant in this range, while silicon is transparent in the infra-red region. Recently, in-line ellipsometer systems have been equipped with infra-red wavelength capability. The biggest issue is that the refractive index changes with micro-crystallinity [43]. It is also known that the micro-crystallinity of poly-silicon or a-Si can change across a wafer. Poly-silicon and a-Si thickness measurement is routinely done with commercial systems after careful consideration of the above issues.
Electrical Measurement of Gate Oxide Thickness
This section briefly discusses the measurement of the effective dielectric thickness using capacitors or transistors. Several references which provide details of capacitance measurements are recommended as supplementary reading [54–60]. In addition to these reviews, theoretical corrections have been used to extend capacitance measurements to 2 nm SiO2 [60]. It is useful to discuss capacitance–voltage measurement in order to better compare optical and electrical measurement methods. The effective dielectric thickness refers to the thickness of the region that acts as a dielectric in the capacitor or transistor. The electrically measured thickness can be different from that measured optically when there is depletion of carriers in the poly-silicon above and/or in the silicon below the gate dielectric. In Figure 24.30a, a plot of capacitance vs. voltage (called a C–V curve or plot) for an ideal capacitor illustrates the response of a SiO2 film that is greater than 4 nm on a uniformly doped p-type substrate [54–59]. The assumption is that the poly-silicon gate and the uniformly doped p-type silicon both act as metal plates in a perfect capacitor when the applied voltage on the gate is negative. Band bending causes positive charge accumulation at the surface of the p-type silicon just as one expects positive charge buildup on a metal plate capacitor as illustrated in Figure 24.30b. The capacitance of P-channel metal-oxide semiconductor (PMOS) structure drops as the voltage moves from negative toward zero. In a defect free structure the valence and conduction bands in the substrate are flat at an applied voltage equal to the flat band voltage. The flat band voltage for two "metal" plates having the same work function is zero as discussed in the example shown in Ref. [55]. The equilibration of the Fermi levels (between the doped poly silicon gate and uniformly doped substrate) results in band bending at zero gate voltage and ideal flat band voltage VfbZ(fmKXsKEcCEF)/q. fm is the work function of the
C Total
Cox Low frequency
Metal electrode (Poly-Si gate) EF at Vg
–Vgate
+Vgate
V (volts)
p doped Si
Vg < 0
Flat band voltage for ideal capacitor
Econduction band Einterface states EFermi surface of metal at ground Evalence band
Accumulation of holes (majority carrier)
r Charge density SiO2
High frequency Deep depletion
Accumulation of electrons
(b) Vacuum level qVFB XS Electron affinity of p doped Si
fm Eg
Γ EC EF
C Poly Si gate Resistance due to dielectric leakage
C Gate dielectric
C Bulk Si
C Interface(SiO2–Si)
VFB = ( f m – X S – EC – EF)/q
FIGURE 24.30 Capacitance–voltage measurement of oxide thickness. (a) Typical C–V data is shown. The oxide thickness is determined from the constant capacitance at negative voltage for p-type silicon substrates. (b) The band bending diagram and charge density plot for gate electrode and p-doped substrate show the charge accumulation at the p-substrate–gate oxide interface. (c) The origin of the flat band voltage. The energy band diagram for the polysilicon/gate oxide/p-doped substrate illustrates band bending at zero applied voltage. (d) The equivalent circuit diagram shows the various contributions to the capacitance of the transistor gate.
metal, Xs is the electron affinity of the doped silicon substrate, Ec is the conduction band edge of the doped silicon substrate, EF is the Fermi level, and q is the electric charge. A band diagram of the polysilicon/SiO2/"p" type Si system based on Ref. [60] is shown in Figure 24.30c [60]. The C–V data is obtained by sweeping the voltage at either low or high frequency. This frequency has a large effect on the capacitance observed at positive voltage as shown in Figure 24.30a. Series and parallel capacitors have been used to describe the capacitance of the entire system as shown in Figure 24.30d [59]. The capacitance of the oxide is in series with charge in the semiconductor and in the poly-silicon gate. The charge in the semiconductor is in parallel with the interface charge, and Schroder divides the charge in the semiconductor into the hole accumulation charge "Cp", the space-charge region bulk charge, and the electron inversion charge which is not shown in Figure 24.30d. When the accumulated charge in the p-type silicon is very large, and the Cp is considered to be shorted and thus it acts as a perfect metal plate in an ideal metal-oxide semiconductor (MOS) capacitor. For thicker oxides O4 nm, the gate electrode is considered to be a perfect metal capacitor plate. Using these assumptions, the effective thickness can be calculated using the following relationship, CoxZ3oxA/dox [55–60]. Cox is the maximum capacitance at negative applied gate voltage for PMOS, d is the effective dielectric thickness, A is the area of the capacitor, and 3ox is dielectric constant (real part of dielectric constant). Defects in the oxide layer result
in the trapping of charge in the oxide layer [54–60]. This shifts the flat band voltage from its ideal value, and allows the quality of the gate dielectric to be monitored by the value of the flat band voltage. Several studies have shown an excellent correlation between Cox and ellipsometric oxide thickness. By this we mean that a plot of the uncorrected electrical thickness vs. physical thickness is linear. The electrical and physical measurements will both have contributions from the interface between the gate oxide and silicon substrate. The dielectric constant of the interfacial region is different from bulk SiO2. This is not corrected for in the electrical determination of thickness. For the very thin oxides !2 nm, C–V behavior is not ideal, i.e., the capacitance is not constant in the accumulation or depletion regions of the C–V curve. The present status of correlation between electrical and physical measurements are discussed below. Some production FABs monitor oxide thickness on both uniformly doped substrates and on PMOS and N-channel metal-oxide semiconductor (NMOS) test structures. The growth rate of SiO2 is dependent on doping type (p vs. n) and concentration especially for lightly doped regions. Therefore, the gate oxide (here we refer to O2 nm SiO2) must be measured on test structures that have implants representative of the channel region of a transistor. This means that when tight control of oxide thickness is required the oxide thickness in both the channel in the PMOS and in the NMOS regions must be measured. The assumptions made in the evaluation of the perfect MOS capacitor, such as uniform doping, are no longer valid. The interface between the silicon and the "bulk like" dielectric contributes to the measured capacitance. When this non-bulk oxide capacitance is constant or linearly varies with oxide thickness, correlation with optical (ellipsometric) measurement is possible. Depletion of charge in the poly-silicon gate and quantum states in the bent bands at the interface of the crystalline silicon with the gate dielectric layer alter the C–V behavior described above. In Figure 24.31, we show the C–V data for thermally grown SiO2 ranging in thickness from 2.5 to 1.5 nm [61]. The 2.5 nm oxide has classical C–V behavior while 1.5 and 2 nm oxides show the effect of quantum behavior and poly depletion. A procedure for removing both quantum and depletion effects from C–V data has been described [61,63]. The resulting oxide thickness can be directly compared to ellipsometric measurements. When the oxide is very thin, the voltage applied to the poly-silicon gate drops inside
Capacitance (fF/μm2)
TOX = (2.0 nm) TOX = (2.5 nm)
Al/TiN gate pure RTO
TOX = (1.5 nm) 4×1013 B/cm2 1×1013 As/cm2
C INV = C ACC for TOX = 2.5 nm
Accumulation Inversion
FIGURE 24.31 Capacitance–voltage data for thin oxides using Al/TiN gate electrodes. All data is courtesy George Brown, Texas Instruments. C–V data for 2.5, 2.0, and 1.5 nm oxides made using rapid thermal oxidation show the increased non-ideal capacitance in accumulation and depletion as the oxide becomes thinner.
the poly-silicon gate electrode. This effect is a function of oxide thickness and poly silicon doping. Modeling of the "poly depletion effect" has shown that for a 3.5 nm oxide the ratio of measured gate capacitance to true oxide capacitance is about 0.84 for a poly gate doping level of 2!1020 and w0.75 for 5!1019 [62]. For a 1.5 nm gate oxide the capacitance ratios are 0.7 and w0.55 for these gate doping levels [62]. Band bending at the silicon substrate–gate oxide interface allows the formation of quantum levels. When a negative voltage is applied and electrons are drawn towards the silicon substrate–gate dielectric interface, the accumulated electrons fill these quantum levels. The filled quantum levels increase the amount of band bending, and cause the center of the accumulated charge to shift away from the interface. These effects change capacitance significantly and must be accounted for during electrical measurement of oxide thickness. In Figure 24.32 both corrected and uncorrected theoretical C–V plots for a sub 3 nm SiO2 gate oxide are shown. Measurement of very thin SiO2 with most test equipment requires the use of high frequency (w1 MHz) and transistor structures that have a large width to gate length ratio [62,63]. Direct tunneling through thin oxides distorts the C–V measurement which can be avoided by use of high frequency (nonstatic) C–V. Static C–V measurement have been extended to !w2.5 nm SiO2 by use of special leakage compensation circuitry and numerical correction [63]. C–V metrology should be used for gate thickness on uniformly doped substrates. Simulation of C–V data for channel doped structures is not available at this time. Recently, a new method of obtaining non-contact, C–V like data called the "Quantox" has been introduced. This tool can provide oxide thickness, flat band voltage, and carrier lifetime data [64]. A corona charge, Q, makes the top "gate" for the capacitance measurements, and provides the bias sweep. The Kelvin probe measures the surface voltage at each Q bias point, and the surface photovoltage (SPV) is the transient surface voltage measured at each Q bias point when a light is flashed to photoflatten the bands. This results in a low frequency non-contact Q–V–SPV curve. This is shown in Figure 24.33a and b. The author notes that there are differences between traditional C–V and Quantox measurements. The rate of voltage sweep is different from traditional C–V measurements, and the amount of tunneling of current during Q–V–SPV measurement is considerably less. By pulsing the corona charge to deep deplete
C –V Tox = 2 nm
Vfb = –1
N sub 2×1017/cm3
N poly 6×1019/cm3
With PD&QM
With QM
With PD
Theoretical C–V simulation showing quantum and depletion effects.
.0 –2 .5 –2 .0 –1 .5 –1 .0 –0 .5 0. 0
Corona bias, Q Corona source, CO3–,H3O+ Oxide
Kelvin probe, Surface photovoltage, Vsurf SPV Mechanical Light oscillator Transient Kelvin probe detection electronics SPV Vsurf – +
P Silicon 1.
Apply Qcorona Bias Measure each ∆Q
Measure Vs (=Vox+ψ). Probe vibration drives AC current.
Stop vibration, flash light, and measure SPV. 4. Repeat
(a) MOS
COS Bias Capacitance
Pickup plate
Bias Surface photo voltage (SPV)
Metal dot Oxide SPV
Silicon Capacitance
SPV SPV = 0
C FB
V FB
FIGURE 24.33 (a) Quantox measurement of surface photovoltage (SPV) vs. bias voltage. This figure shows the three components of a Quantox system. A corona charge is used as the gate for a corona-oxide-semiconductor (COS) capacitor measurement. The bias is swept by applying different corona charges. The Kelvin probe measures the transient SPV at each corona (Q) bias point after the bands are flattened by the flashing a light. Figure courtesy Steve Weinzierl, Keithley Instruments. (b) Comparison of traditional capacitance–voltage with quantox Q–V–SPV measurements. Figure courtesy Steve Weinzierl, Keithley instruments.
the silicon from inversion, non-contact measurements of carrier density and generation lifetime to a controlled depth are also provided. The comparison of Quantox data (not corrected for quantum and depletion effects) with ellipsometric data shows a strong correlation. Existing data shows that repeatability is 0.03 nm, 1 s. Some workers believe that Quantox measurements are not effected by hydrocarbon buildup on the oxide surface. In addition, poly depletion corrections are not required. Current–Voltage measurements also show a strong correlation to oxide thickness and may have better resolution to changes in oxide thickness than ellipsometry [60, 61, 63, 64]. Typical current–voltage data is shown for oxide thicknesses between w3 and w1.5 nm in Figure 24.34. Since the I–V data is a strong function of oxide thickness (10 A˚/cm for a 0.04 nm decrease in oxide thickness), measurement resolution
N-Si: Positive bias-Substrate injection
Current density (A/cm2)
1×102 1×101 1
Data: Tox(nom) = 17.6 Å
Simmons Vox model - 17.6 Å
1×10 1×10
Area = 5×10 cm
1×10–8 1×10–9
Applied voltage (V)
FIGURE 24.34 Current–voltage data applied to oxide thickness measurement. At 1 V bias, the current varies over seven orders of magnitude as the oxide thickness changes from w3 to w1.8 nm. Simulated data is also shown. Figure and data courtesy George Brown, Texas Instruments.
appears better than the approximate 0.258 change in D per angstom estimated for ellipsometry at 632.8 nm. On the basis of the measurement procedure reported by Brown and co-workers, the thickness associated with measured current must be calibrated using another measurement. The I–V characteristics should depend on doping characteristics such as channel dose. Unless calibrated to C–V, I–V thickness does not depend on knowledge of the static dielectric constant.
24.3.3 New Methods of Measuring Gate Dielectric Thickness and Nitrogen Concentration X-ray photoelectron spectroscopy is a well known materials characterization method that determines the elemental composition along with their chemical state [65]. The information depth for XPS is roughly the top 5 nm or less. Depth dependent information can be determined using either ion sputtering or by measuring the XPS signal at different angles of x-ray incidence [66]. Recently, a clean room compatible XPS system capable of rapid throughput has been introduced [67]. The first data for the precision of film thickness and nitrogen concentration are promising and worth of mention. This method can also be applied to high k composition and thickness metrology. The spot size of XPS is determined by the size of the area irradiated by the x-rays and the region of this area that generates electrons that enter the detector. This area is 9 mm in diameter which is larger than that analyzed by optical methods. Electron microprobe analysis is another materials characterization method that has been adapted for clean room based metrology. In this technique, x-rays are emitted after irradiation by an electron beam. In one commercial version, low energy x-rays from elements such as nitrogen and oxygen are measured using wavelength dispersive spectrometers. In order to generate enough x-rays to have favorable signal to noise, a relatively large diameter electron beam with a relatively large total current [68] is used. Preliminary evaluation indicates that the precision for nitrogen concentration is w1% of the dose between 0.8 and 5% nitrogen concentration and the precision for thickness is w1% of the thickness for
thin films [65]. The analysis area is between 10 and 100 mm in diameter, and the electron beam energy is from 0.2 to 10 keV. This method can also be applied to dopant dose metrology.
Doping Process Control
The predominant method of dopant processing is implantation of ionized dopants. For the purposes of this chapter, we will refer to three types of implant steps: high energy—medium dose [1013 PC/cm2 at 700 keV, 1013 BC/cm2 at 1.5 MeV] to form retrograde well structures and [BC and PC1012– 1013 ions/cm2 at 100–200 keV] for N and P wells; medium energy—high dose [1015 AsC/cm2 at 10– 2 80 keV; 1015 BC/cm2 at 0.5–40 keV or 1015 BFC 2 =cm at 5–200 keV] to form the source and drain and 13 14 C C C C 2 [10 –10 As , P , B , or BF2 =cm at 0.2–100 keV] to form the lightly doped drain (also called drain 2 extension); and low energy–low dose [1011–1012 AsC, PC, BC, or BFC 2 =cm at 0.2–100 keV] for the threshold voltage implant. Each of these types has a different process tolerance and thus requires a different precision from the metrology tool [69]. Another issue is uniformity across the wafer. Several references have discussed implant process control including SPC and uniformity [70,71]. The three most prevalent methods of dopant dose control are four point probe, optically modulated optical reflection (commercially known as the Thermawave), and secondary ion mass spectrometry (SIMS) depth profiling. Four pt probe is used for high dose plants and Thermawave for medium to low dose process control [69]. SIMS can be applied to junction and dose measurements for all doses. The precision of optical densitometry has recently been improved, and new methods have been proposed. In this section, we discuss all these methods. 24.3.4.1
Four Point Probe
The four point probe method characterizes the active dopant dose by measuring the resistivity and relating this to the active carrier concentration. Two reviews of the fundamentals of four point probe measurements are available [72,73]. The four point probe method of measuring resistivity is based on the use of a linear array of four probes in which two probes carry the current and two probes measure voltage. The resistance of a two probe configuration includes contributions from probe contact and spreading resistance [72]. The two additional probes are used to sense voltage due to the current passing through the sample between the other probes, and current through these probes is minimized and, thus, the spreading resistance and contact terms are minimized. An alternative method involves analysis of the resistance and currents when different pairs of the four point probes are used for injecting current and measuring potential. The effect of the spreading and contact resistance can be mathematically eliminated, and thus this is a second approach to removing these effects. Therefore, the contact and spreading resistance terms cancel out in the four point configuration when the voltage probes are used instead of the two probe approach [72]. Typically, the probes are equally spaced and the current runs through the outer probes [72]. The probe spacing on traditional systems is between 0.5 and 1.5 mm [72], and greatly improved probe tips (larger radius probe tips for improved precision) are required for 180 nm technology generations. The measured resistivity is a function of the sample shape. The equation for the resistivity r is: rZ2psF(V/I), where s is the probe spacing, V is the voltage at the voltage sensing probes, and I is the current through the current carrying probes. F is the correction factor that accounts for sample shape, and it is a function of thickness, lateral dimensions, and wafer edge proximity. Four point probe measurements are done using monitor wafers having special characteristics. After implantion, the monitor wafers must be annealed to restore crystallinity and activate the dopant [69,70]. These monitor wafers must have resistivity characteristics that permit measurement of the implant dose of interest. For example, it would be difficult to measure the change in resisitivity of a low resistivity wafer (e.g., pCwafer) due to a low to medium dose implant. Epi wafers such as "p" epi on pCsubstrate also create problems since the current can pass through the lower resistance substrate which is away from the implant. Implant doses O1014 ion/cm2 are easily measured on wafers having a resistivity R20 U-cm. Doses in the 1011–1012 ions/cm2 range may be measured using high wafers with a high resistivity when
the correct annealing and surface conditions are used. Yarling and Current suggest either "p" or "n" type wafers with a resistivity O100 U-cm for low dose samples [70]. Correct annealing conditions are critical. Due to the processing characteristics of different anneal/dopant combinations, the anneal must be optimized for the parameter being tested. Implant dose alone is often tested by long, high temperature furnace anneals, while implant energy is best tested with a short rapid thermal processing (RTP) anneal or, better yet, with a blocking layer (e.g., oxide layer) which only tests the deeper part of the implant. Similarly, RTP temperature control for implant diffusion is most optimally tested using an implant near the solid solubility. The doping level is most sensitive to the temperature under these conditions. 24.3.4.2
Optically Modulated Optical Reflection
Optically modulated optical reflection is the monitoring of thermal wave propagation in an implanted wafer. The commercial system used for this measurement is often called by the supplier's name, Thermawave. Thermal waves are produced by an argon ion laser modulated at a frequency of 0.1 to 10 MHz [74]. These waves heat the adjacent surface of the wafer changing the volume of the silicon near the surface. The volume change alters the optical properties of the surface, and this is probed by measuring the reflectivity change using light from a second laser. The amount of heat transfer and the volume change per unit heat depend on the implant dose and implanted species because heat transfer is effected by the implant process damages the silicon lattice structure while adding dopant atoms to the lattice. The sample spot size is approximately 1 mm, and measurements of doses between 1011 and 1015 atoms/cm2 have been reported. Optically modulated optical reflection is distinguished by its sensitivity to low dose implants. Each implant ion typically produces 100 to 1000 damage sites so the effect from each ion is multiplied. After a certain dose is reached, there is little change in implant damage, and sensitivity to high dose is hampered. 24.3.4.3
Secondary Ion Mass Spectrometry
Secondary ion mass spectrometry can provide dopant dose, and since SIMS data is in the form of a depth profile, it naturally lends itself to junction measurements. The first dynamic SIMS systems equipped with product wafer capable stages were delivered in 1997. Since SIMS has been described in the chapter on Materials Characterization, only the application to dopant process control is discussed here [75]. SIMS is capable of simultaneously monitoring multiple implant species in the same test structure. Test structures are typically 100 mm!100 mm and larger and have been routinely incorporated in the scribe lines of product wafers. Test structures are also routinely placed in the die of product wafers especially during process and pilot line development. Implant dose is measured by integrating the secondary ion signal of the dopant element from the surface to the depth of the implant. Shallow implants remain a significant challenge for SIMS characterization [75]. The secondary ion signal is strong function of the matrix that the implanted ion resides in (oxide, interface, or bulk silicon). In addition, quantifiable secondary ion signals require that the ion sputtering process reach a steady state. When using energetic primary ion beams such as 5 to C 10 keV OC 2 or 5 to 10 keV Cs , the steady state is not reached until a considerable depth (sometimes up to 50 nm) is sputtered away. Recent studies show that for 300 eV OC 2 primary beam, a steady state is reached for crystalline, oxidized crystalline, or amorphized silicon by the time 0.7 nm has been sputtered away [76,77]. This has driven the use of low energy ion beams for shallow junctions [76–78]. Stable, very low energy ion beams around 100 eV were introduced in 1997. A rule of thumb for depth profiling is that the ion beam energy should be half the implant energy. The optimum conditions for B implant measurement depend on whether or not oxygen gas is used to dose the sample surface along with a primary ion beam of OC 2 . When possible, very low energies (down to 200 eV or less) are used for the primary beam. This can slow down the analysis procedure if the ion beam current is low, and beam energy and current should be selected according to conditions that depend on the lowest concentration of B that one needs to determine [76–78]. The sputter yield decreases below 1 keV primary beam energy and the detection limit is approximately 1017 atoms boron/cm3 for 100 eV OC 2 at normal incidence. When oxygen dosing is used,
low energy primary ions at incidence angles from 45 to 558 have shown satisfactory results. When no oxygen dosing is used, then normal incidence should be used for the primary ion beam. Shallow arsenic implants can be analyzed using CsC at 608 incidence and 500 eV energy. 24.3.4.4
Junction Depth Measurement via Carrier Illumination
Carrier Illumination is a new, non-destructive method of measuring junction depth. Borden has described Carrier Illumination in depth [79]. The junction was considered to be the depth at which carrier concentration drops to 1018/cm3. Due to the increase in channel doping, a value of 1!1019 is becoming more relevant. The method first excites excess carriers using a 2 mm spot laser. The carriers form a quasistatic distribution that piles-up at the edge of the doped layer. The excess carriers are due to the change in the direction of flow of the excess carriers from vertical in the doped layer to a radial horizontal flow in the substrate. The depth of this junction is determined by measuring the reflectivity of a second laser [7,80].
Metrology for Measurement of Stress Enhanced Carrier Mobility
Stress metrology faces the difficult challenge of controlling processes used to increase carrier mobility through stress. As discussed above, greater carrier mobility increases transistor drive current and thus transistor switching speed [81]. Strained silicon substrates are also being investigated for this purpose [82]. First, the diverse set of processes is used to increase mobility as discussed, and then the metrology methods and challenges are reviewed. Stress is the force applied to a material, and it can be compressive or tensil. Stress can also be uni-axial, that is along one crystallographic direction, or bi-axial or along two, perpendicular crystallographic directions. Process induced stress is typically uni-axial, while the lattice mismatch with the substrate induces a biaxially strained silicon surface layer. Stress induced changes in physical properties are typically modeled by as if the silicon is a continuous elastic material. Recent publications indicate that uni-axial stress has some significant advantages over strained silicon layers [83]. The amount of stress required for improving carrier mobility is less for uni-axial stress. In addition, the process based approach allows one to use compressive stress for p-channel devices and tensile stress for n-channel devices while the substrate approach results in only tensile stress [83]. Process based increase in carrier mobility has been used in the manufacture of the 90 and 65 nm technology nodes. Processes induce nearly uni-axial, tensile stress to increase electron mobility and uniaxial, compressive stress to increase hole mobility. Intel uses tensile silicon nitride layers above the NMOS and replaces the source and drain in the PMOS with silicon germanium to compressively stress the channel [84]. Although direct measurement of the stress in the buried channel is impossible, one can surmise how process control is done. Measurement of silicon nitride thickness can provide control of a stable silicon nitride deposition process for the NMOS. It seems likely that a combination of CD and Ge concentration measurement could be used for controlling the PMOS mobility. Recent publications discuss the modeling how the Intel Process induces compressive stress along the h110i direction of silicon increases hole mobility [85]. Texas Instruments has found that use of recessed SiGe source and drain extensions improves PMOS drive current by 35% [86]. Fujitsu has shown that by changing process conditions, the silicon nitride layer can be used to impart both tensile and compressive stress [87]. IBM uses the stress induced by the shallow trench isolation to stress PMOS channels [88]. The amount of stress can be altered by changing the distance between the STI and the edge of the gate electrode. Future approaches to stress induced improvement of carrier mobility include the use of metal gates and strained silicon substrates [89]. Strained silicon substrates are grown on top of silicon germanium layers where the lattice mismatch provides the stress. Strained silicon can either be left on top of the SiGe or transferred to a wafer with a surface oxide layer producing the so-called sSOI. Strain can be measured by a number of different methods such as Raman spectroscopy, x-ray Diffraction, and Photoreflectance. The average stress across a wafer can be measured using the change in wafer curvature. Some of these methods are briefly described below.
Raman spectroscopy measures strain using the shift in the wavelength of the silicon optical phonons. The shift can be related to the stress through the elastic equations. In the future, nano Raman systems based on near field optical microscopes will push the spatial resolution below 200 nm. High resolution– x-ray diffraction measures small changes in lattice constant (strain). Measurement of patterned wafers requires large test areas. Photoreflectance Spectroscopy can measure strain in un-patterned wafers. The electronic transition between energy levels occurs at specific energies that change when the lattice structure is stretched or compressed. Bi-axial stress splits energy levels that degenerate in un-strained silicon or germanium. In particular, the E1 transition energy at 3.392 eV is used to monitor strain. The average stress across a wafer can be calculated from the change in wafer curvature after film deposition. Die level stress can be determined from local wafer curvature using Interferometry. The new Coherent Gradient System uses a referenced interferometer to measure local curvature of the wafer. Using well known algorithms, the local stress changes can be calculated from the local wafer curvature changes when a wafer is measured before and after a process step.
Interconnect Process Control
In this section, we will refer to interconnect processes, as those that begin with the contact between the transistor and the first level of on chip interconnect metal (Metal 1) and end with the passivation layer over the final on chip metal level. In Figure 24.35, we illustrate the typical process steps that are controlled by metrology. The process schemes for interconnect are expected to be a mixture of traditional etched metal/inter level dielectric and Damascene (also known as inlaid metal) processing. Chemical Mechanical Polishing and copper will be used in both types of interconnect processes. The interconnect via and contact (also known as plug) material could be tungsten or aluminum with titanium nitride barrier layers or copper with barrier (possibly Ta) in the future. Routine physical metrology needs for interconnect processes include metal and dielectric film thickness, step coverage, CMP end point and flatness, and particle/defect control. Particle detection and control is covered in the chapter on Contamination Free Manufacturing. When interconnect processes are stable, film stress is not routinely monitored. The CMP processing may replace the need for measurement of B and P in reflow glass inter-layer dielectric (ILD) films. Electrical metrology needs include testing of contact/via resistivity and metal level defects.
High level overview of interconnect metrology.
Process control needs also include the need to measure voids in copper lines and large "killer" pores in porous low k materials. Although porous low k is (at the time of writing) a research material, great progress has been made in the measurement of pore size distribution.
Interconnect Film Thickness
In this section, we discuss film thickness measurement for contacts (e.g., TiSi2), barrier layer (e.g., TiN, TiW, Ti/TiN stacks, or CoSi2), metallic anti-reflective coatings, interconnect dielectric layers, and all metal interconnect films (e.g., Al or Cu). Ideally, film thickness metrology would be done on patterned wafers and include measurement of the liner film thickness inside a via/contact structure. Most film thickness measurements require large, flat sampling areas. A number of commercially available methods have been applied to metal and barrier layer film thickness measurement such as acoustic [90,91], resistivity by Four Point Probe [92], x-ray reflectivity [93], XRF [94], and a new method known as Metal Illumination (MI)e [95]. A newly introduced, in-line method that is very similar to Electron Microprobe uses a relatively large electron beam to excite XRF. This is covered in the section below on determination of metal film thickness using x-ray Methods. Optical reflectivity and ellipsometry are both used for dielectric film thickness [96]. It is useful to note that ellipsometry can measure the thickness of very thin barrier layers. Off-line measurement of patterned metal thickness is possible using scanning electron microscopy and energy dispersive x-ray spectroscopy (EDS) if careful modeling of x-ray emission is done for the film stack and structure that one is analyzing. 24.4.1.1
Interconnect Metal Film Thickness Measurement Using X-Ray Methods
Metal and barrier layer film thickness can be measured in-line by commercially available x-ray reflectivity and XRF. Both methods can determine barrier thickness for barrier films under the seed copper layers. Measurement of barrier layers under the thicker electrochemically deposited copper layers used in the fabrication of metal lines is more difficult, but reports of successful use of XRF exist. Measurement on patterned layers is possible using the electron beam excited, XRF approach embodied in the Matrix 100e [97]. Although x-ray reflectivity may be applied to patterned films, its use is not widely reported at this time. Innovations in x-ray optics make it difficult to know what the true limits of x-ray methods concerning patterned layer measurements. X-ray reflectivity is a very powerful method of characterizing film thickness. x-ray reflectivity is also sometimes referred to as grazing incidence x-ray reflectivity (GI-XRR). In GI-XRR, the angle of incidence of a well collimated, monochromatic x-ray beam is reflected off a flat sample over a range of incident angles [93]. The intensity of the specular reflection is used for film thickness determination. Nonspecular x-ray scattering can also be measured, and film and interface roughness analyzed. Interference patterns in the form of intensity oscillations are formed when GI-XRR is done on single and multi-layer thin film samples. Reflectivity from a homogeneous substrate, a single, and a two layer film is shown in Figure 24.36. The film thickness of a single layer film can be determined from the angular difference between the peaks of subsequent intensity oscillations. Two periods of intensity oscillation are present when analyzing a two layer film. Because the wavelength of a monochromatic x-ray is accurately known, thickness can be accurately determined. Density measurement is more difficult. It is important to note that in-line measurement of x-ray reflectivity is done using an optical path that simultaneously collects reflected x-rays at multiple angles. Specially designed optical paths and detectors allow rapid measurements making it possible to measure multiple wafers per hour inside a clean room. In some sense, x-ray reflectivity and ellipsometry are similar in that both require development of appropriate models to interpret the data. The key to successful modeling is incorporating interfacial characteristics that allow for high precision and appropriate "Goodness of Fit" to the data. Due to the difference in electron density, very thin (0.5 nm) barrier layers have been measured below seed copper films. Due to x-ray absorption, measurement of barrier layers under electroplated copper is usually not considered to be possible.
Monochromator Spatially resolving x-ray sensor
Thin-film sample X-ray tube
Angle (degrees) 0.4 0.6 0.8 1.0
Cu fringes
0.01 0.001 0.0001
Ta fringes
FIGURE 24.36 Diagram of an x-ray fluorescence film thickness tool. The Kevex tool uses collimated probe beam and collimators for the fluoresced x-rays. Figure courtesy David Wherry and Ed Terrell, Kevex.
In-line measurement of metal film thickness has been done using both energy dispersive and wavelength dispersive XRF [94]. Micro-focus tools have a spot size of 50 mm while non-micro-focus systems typically have millimeter size spots. Film thickness can be quantified from 1 nm to 10 mm. Repeatability, which is the short term contribution to precision, is !0.5 nm for 50 nm Ti and TiN films and !1 nm for 1 mm Al films. Using modeling, film stacks can be characterized. This method applies to any barrier layer, TiN type antireflective coating, and both Al and Cu interconnect metal films. Typically, XRF is used to measure the thickness of thin films that are composed of an element or elements different than the silicon or silicon dioxide layer below, e.g., Al or TiN. In addition, the substrate composition must be constant. This greatly simplifies calculation of film thickness from the fluorescent intensity of the element(s) that compose the film. X-ray fluorescence is created by both the incident x-ray beam and fluorescence from surrounding material such as the substrate below the film. The thickness, t, of a film of element (i), Ii, is related to the measured fluorescent intensity of an infinitely thick film of element (I), I fi, the film density, r, and the effective mass attenuation coefficient, mi , by [94]:
t Z ð1=rmI Þlnð1KðIi =Ifi ÞÞ The quantity mi is a function of x-ray wavelength, angle of incidence j 0 , and angle of exit to the detector j 00 :
mi Z mil cscj 0 C mil cscj 00 mil is the mass attenuation coefficient of element I at the wavelength of x-rays used to excite the sample. Daily calibration is required due to the small, day to day variations in x-ray tube intensity and detector efficiency. In Figure 24.37, the x-ray optical paths for one type of XRF systems are shown. The x-ray beam is used as a means of exciting XRF from the film. Since the films are poly-crystalline, x-ray diffraction is difficult to minimize unless the film is highly textured. Although the depth of penetration depends on the angle of incidence and the adsorption of the material, it is of the order of microns. X-ray fluorescence can also be observed from more than a micron below the sample surface [94]. Analysis of XRF is made difficult by
Schematic XRMF spectrometer Evacuable sample champer
Sample XYZ stage
Final collimator Primary filter/collimator
Detector collimator
Preamplifier Lenses Illuminating sources PXS x-ray tube source (side window)
Color CCD camera
Si(Li)
Microprobe viewing system
Crystal detector
LN2 Cold finger Liquid nitrogen crystal
FIGURE 24.37 X-ray reflectivity based film thickness measurement In-line x-ray reflectivity throughput is increased by the use of optics that allow the entire reflectivity vs. angle data to be obtained at one time. X-ray reflectivity data for a copper film on a tantalum barrier layer is shown.
the adsorption of fluoresced x-rays and subsequent re-emission. Therefore, reference materials are critical to the success of this method. In addition, x-ray tube emission and x-ray detectors require daily recalibration. 24.4.1.2 Metal and Interconnect Dielectric Film Thickness Measurement Using Acoustic Methods In this subsection both of these non-destructive methods for measuring metal film thickness are described. Considering the original application of one acoustic method, dielectric film thickness measurement may also be possible. One of these systems is based on impulsive stimulated thermal scattering (ISTS) which is now referred to as laser induced surface acoustic waves. Commercially, the method is now known as SurfaceWave. Detailed descriptions of this method are available in the literature [90]. The acoustic wave travels parallel to the surface of the sample in ISTS, in contrast to picosecond laser ultrasonic sonar where the acoustic wave travels downward. The ISTS is a rapid (!1 s. per data point), small spot (15 mm!30 mm) film thickness method which has outstanding precision when applied to single layer films. The optical path has been designed for a long working distance and with solid state, long life lasers making it suitable for in situ sensor applications. In ISTS, a pair of optical pulses each having a duration of a few hundred picoseconds are overlapped in time and space on a sample's surface. Optical interference between the crossed excitation pulses forms a spatially varying interference or "grating" pattern of alternating light (constructive interference) and dark (destructive interference) regions. Formation of the grating pattern is illustrated schematically in the inset of Figure 24.38a. The grating fringe spacing D (or wave number q) is given
FIGURE 24.38 (a) The time dependent modulation of reflectance due to the acoustic wave produced by impulsive stimulated thermal scattering (ISTS; Surface Wave) from a single copper layer. The three steps in a measurement are: 1. The probe beam strikes the surface, 2. The grating structure is formed from the overlapping parts of the excitation laser pulse and the acoustic wave is formed, 3. The acoustic wave travels away from the excitation area and the traveling surface ripples diffract the probe beam in and out of the detector. Figure courtesy Michael Gostein, Philips Advanced Metrology Systems. (b) Acoustic frequency of Cu film.
24-40 Handbook of Semiconductor Manufacturing Technology
by: qZ4p sin(Q/2)/lZ2p/D. The crossing angle Q of the two excitation pulses. The sample absorbs radiation in the light regions, resulting in a mild heating and thermal expansion that launches coherent acoustic waves whose wavelength and direction match those of the interference pattern with wave vectorGq [90]. The acoustic waves generate a time-dependent "ripple" on the sample's surface. The depth of modulation oscillates at the acoustic frequency, which is determined by the sample's mechanical (e.g., elastic) and physical (e.g., thickness) properties and by the boundary conditions (e.g., adhesion) between the different layers in the sample. At the time that the acoustic waves are propagating outward from the excitation site, heat flows from the heated grating peaks to the unheated grating nulls at a rate determined by the sample's thermal diffusivity. One advantage of this acoustic method is that by changing the angle Q, the wave vector is changed and properties such as sample density can be experimentally determined. Metal film thickness methods, such as XRF Rutherford backscattering, and acoustic, all require knowledge of the sample density. The ISTS can provide experimental density information specific to the metal film fabrication process. Changes in film density can also be monitored. The acoustic response is measured in its entirety by diffracting a probe laser pulse having duration of several hundred microseconds off the surface ripple to form a pair of signal beams (the C1 and K1 diffracted orders). One of the signal beams is detected to generate a light-induced signal waveform [90]. This diffraction mechanism is indicated schematically in the inset of Figure 24.38a. This figure also shows time-dependent data taken from a copper film. These data were collected during a period of one or two seconds. During its first 70 ns, the signal waveform oscillates according to the copper's acoustic frequency and decays primarily due to the travel of the acoustic waves away from the excitation cite into the rest of the sample. Figure 24.38b shows the power spectrum of the copper data in Figure 24.38b to be centered at about 270 MHz. To determine film thickness, the frequency is analyzed as described in the abovementioned references [90]. Figure 24.39 illustrates the accuracy of the ISTS measurements, showing, respectively, the results from a set of copper/oxide/silicon and tantalum/oxide/silicon samples having thicknesses ranging from 20 to 180 nm. These data show the correlation between the center-point film thickness determined using ISTS (y axis) and a conventional four point probe (x axis). Film thicknesses were calculated from the four point probe data using resistivity values that are within 2% of the bulk resistivities for both tantalum and copper. The line in each of the plots has a slope of one and is used as a guide to the eye. For both the 2400 B
ISTS Thickness (Å)
2000 1600 1200 800 400 B 0
B BB B B
B B BB BB
4-Point probe thickness (Å)
FIGURE 24.39 Comparison of ISTS and 4-point probe measurement of film thickness. The data was taken using the InSite 300, and the figure was provided by John Hanselman of Active Impulse Systems. This technology is now provided by Philips AMS.
tantalum and copper samples, the correlation between the ISTS and four point probe thickness measurements is excellent over the entire sample set. On average, these values are within 0.6 and 2.9% of each other, respectively. Deviation between the two measurements may be due to a variety of factors, such as the film's resistivity depending on film thickness of grain structure. Such dependence seems particularly evident in the tantalum data, as the deviation of the data from the solid line systematically increases with film thickness. Impulsive stimulated thermal scattering can measure one or more layers in a multilayer structure. Two different approaches are used based on the thickness of the films [90]. The first method is applicable when both layers are thick (e.g., Ow1000 A˚) and have different acoustic properties. Two acoustic wavelengths are recorded, one short and one long. The two wavelengths probe the sample to different depths. The short wavelength response is relatively more sensitive to the top layer than the bottom one, as compared to the long wavelength response. By analyzing both responses and fitting with a first-principles model, both layer thicknesses can be determined [90]. The second method is applicable when there is a thinner layer underneath the top layer, and both layers have different thermal properties. This method is used for barrier–copper seed applications. In this case, only one acoustic wavelength is used. The frequency response of the signal waveform is sensitive roughly to the total metal mass, while the thermal decay time of the waveform is sensitive to the ratio of the two metals, due to their thermal contrast. Using this information, both metal thicknesses are determined [90]. Presently, a buried layer of down to 5 nm can be measured and controlled. One advantage of ISTS is that it can measure patterned wafer samples. In the case of a sample that consists of metal lines, the acoustic wave travels away from the excitation area along the array of metal lines. The acoustic response of the metal line/insulator array must now be modeled instead of a blanket film. The barrier layer in this type of sample is on both sides and below the metal line. Arrays of lines or vias are treated in the analysis as films with "effective" elastic constants that are a composite of those of the consistuent materials, i.e., metal and dielectric. In many cases the composite elastic constants can be estimated by simple averaging formulas. More complex structures, e.g., those with pitch similar to the acoustic wavelength, for which modeling is complicated, require a calibration to determine the effective elastic constants. In addition, the presence of vias below the metal lines complicates modeling. Due to these complications, the response vs. line thickness is usually calibrated, and routine measurement of film thickness for patterned structures is possible for metal lines, pads, and vias. The CMP process control is a typical application of patterned wafer measurements [90]. Another acoustic film thickness system was commercially introduced in 1997. One system is based on Picosecond Ultrasonic Laser Sonar Technology (PULSE). A detailed description of the physical processes involved making measurements of this type is available [91]. The PULSE technique has a high (a small numerical value) precision, sampling speed (2 to 4 s/pt), spatial resolution (less than a 10 mm diameter spot size), and it can be applied to single and multilayer metal deposition processes. In a PULSE measurement for a sample consisting of a metal film deposited on a substrate (e.g., Si) an acoustic wave is first generated by the thermal expansion caused by sub-picosecond laser light pulse absorbed at the surface of a the metal. The temperature increase (typically 58C–108C) is a function of sample depth which results in a depth dependent isotropic thermal stress [91] which gives rise to a sound wave which propagates normal to the sample surface into the bulk. This wave is partially reflected at the interface between the film and substrate [91]. For an acoustic wave, the reflection coefficient RA depends on the acoustic impedances Z (ZZdensity!sound velocity) of the film and substrate materials, and may be evaluated from the relation RAZ(ZsubKZfilm)/(ZsubCZfilm) [82]. When a reflected wave (or "echo") returns to the free surface after a time t, it causes a small change in the sample optical reflectivity, DR. This change is monitored as a function of time by a second laser probe. Based on the sound velocities of the materials making up the sample (which for most materials are known from bulk measurements) and the echo time, the film thickness dfilm may be evaluated from the simple relation dfilmZvst. As an example, Figure 24.40 shows a PULSE measurement obtained for a sample consisting of a copper film deposited on top of a thin Ta layer (less than 20 nm thick) with a substrate consisting of a thick tetraethoxysilane (TEOS) layer (about 600 nm). The sharp feature observed in a range of time less than
∆R (t )
100 200 300 400 500 600 700 800 900 1000 Time (ps)
FIGURE 24.40 Acoustic measurement of copper film thickness using picosecond ultrasonic laser sonar (PULSE) technology. The time dependent reflectivity observed during PULSE measurement of a copper layer on 20 nm of tantalum on tetraethoxysilane (TEOS) is shown. The ultrasonic wave travels into the copper layer partially reflecting at the Cu/Ta interface and subsequently the Ta/TEOS interface. When the ultrasonic wave returns to the surface, it alters the optical constants of the surface and this is monitored by measuring the change in reflectivity. The transit time is directly related to the speed of sound and the layer thickness. The data taken using a MetaPULSe picosecond laser ultrasonic sonar system, and the figure is courtesy Rob Stoner, Rudolph Technologies.
about 50 ps is associated with relaxation of the electrons in the copper film which initially gain energy from the ultrashort light pulse. This energy is transferred to thermal phonons in the film which gives rise to an increase in its temperature by approximately one degree. The subsequent diffusion of heat out of the film and into the underlying TEOS occurs on a timescale of hundreds of picoseconds, and this is associated with the slowly decaying "background" signal observed in the figure. The sharp feature observed at a time of about 800 ps is the echo caused by sound which has reflected from the bottom of the copper layer and returned to the surface of the sample. To determine the film thickness from these data only the echo component is used; the background is discarded. From the product of the one way travel time for sound through the film (406 ps) and the sound velocity (51.7 A˚/ps), the film thickness is found to be 2.10 mm. The time-dependent reflectivity change DR(t) measured via PULSE depends on the physical mechanisms underlying the sound generation and propagation, and sound-induced changes in optical properties. These may be simulated with very high fidelity even for samples consisting of many layers with thicknesses ranging from less than 50 A˚ to several microns. Using an iterative procedure in which the thicknesses of layers in a model for a sample are adjusted until a best fit to the measured DR(t) is obtained; the commercial PULSE system obtains typical measurement precision for thickness of less than 0.1 nm (1 A˚) with 90% confidence. This modeling methodology also allows other film properties such as density, adhesion, and surface roughness to be obtained along with thickness since these parameters have a predictable influence in the amplitudes and shapes of the optically detected echoes. In Figure 24.40, we show the PULSE signal from a 200 nm thick layer of TiN on top of aluminum. The ability to measure film density has considerable practical significance, especially for WSix, TiN, WN, and other materials whose composition and structure depend on many aspects of the deposition process such as pressure, target composition, temperature or gas mixture. The PULSE has been used to distinguish between TiN films differing in density (or composition) by only a few percent. The PULSE has also been used to detect silicide phase transitions for Ti and Co reacted with silicon at different temperatures based on changes in sound velocity, density, and optical properties [91]. The commercially available MetaPULSe system uses a solid state, compact, ultrafast laser as a source for both the generating and detecting beams, dividing the single beam into two by means of a simple beam splitter. The sensitivity of the technique can be optimized to give improved throughput and sensitivity for specific materials, and a high throughput copper system is one example [91]. The MetaPULSe system is currently available in a highly automated stand alone configuration equipped with
75 100 125 150 175 200 225 Time (ps)
FIGURE 24.41 Simulated time dependent reflectivity of PULSE measurement of a TiN layer on a thick aluminum substrate. This data shows the effect of having a metal substrate instead of the inter-layer dielectric substrate shown in Figure 5.4. Data taken using a MetaPULSe picosecond laser ultrasonic sonar system. Figure courtesy Rob Stoner, Rudolph Technologies.
an optical microscope, pattern recognition software, and precision sample stage so that patterned wafers can be monitored. Because of its long working distance and high throughput, PULSE technology can also be applied to in situ measurements. 24.4.1.3
Resolution and Precision of Acoustic Film Thickness Measurements
The resolution of ISTS determined film thickness is nearly independent of film thickness and composition [90]. The resolution and precision of ISTS are better known for single layer films. Precision values of less than 0.2 nm are typically observed. The precision is sub-angstrom for a wide variety of single layer films. The reason for the small value for precision (greater measurement precisionZsmaller value of precision) is that the general shape of the ISTS data is a damped, high frequency oscillation. This general shape does not change with film thickness, only the frequency and damping characteristics change with thickness and composition. Since the oscillations can be averaged over many periods on every sample, precision values are always small. The precision of PULSE measurements is related to the precision with which the echo times within a sample may be determined [91]. For a hypothetical measurement in which a single echo is analyzed, the precision is equal to the product of the sound velocity in the film (typically about 50 A˚/ps) and the uncertainty in determining the centroid (time) of the echo Dt. The two most important factors which influence Dt are the system noise (from mechanical, electrical, and optical fluctuations) and the linearity and precision of the mechanism used to establish the time base (i.e., the delay in time between the generating and measuring laser pulses). The latter is a mechanical delay line consisting of a retroreflector mounted on a linear stage, so that the time base linearity and precision are determined by the linear stage characteristics. In practice, a Dt of about 0.006 ps can be achieved using readily available components over a range of echo times extending from 0 to over 2 ns. This gives a precision for thickness of order 0.3– 0.6 A˚ for measurements based on a single echo, and this is typical of observed static measurement repeatability for films thicker than a few thousand Angstroms, giving a precision of order 0.1%, or better. For thinner films it is generally possible to observe several echoes within the finite delay range of the measuring system, and this gives a corresponding improvement in precision by a factor which is proportional to the number of echoes observed. Thus the precision in dimensions of length remains approximately constant for thicknesses ranging from a few hundred Angstroms to several microns. For very thin films the signal to noise ratio tends to degrade due to the increasing transparency of the films and the increasing overlap between successive echoes so that measurements become impractical for films thinner than about 25 A˚ (depending on the material). Therefore for films up to a few hundred Angstroms the measurement precision may vary from between 0.1 and 1% depending on the specific combination of optical properties and film thickness.
For multilayer films, the measurement precision is layer specific and also dependent on the proximity of each layer to the free surface as well as the ideality of the interfaces between layers. For multilayer samples with perfect interfaces between all layers, the measurement uncertainty (in dimensions of length) for any single layer increases relative to the equivalent single film case by an amount proportional to the number of films between it and the free surface. This increase in uncertainty is usually negligible since, in general, more than one echo is observed within a buried layer less than about 1000 A˚ thick. 24.4.1.4
Optical Measurement of Interconnect Dielectric and Metal Film Thickness
Ellipsometry can measure the thickness of very thin metal and metal-like films [98]. The depth of penetration of light is directly related to the imaginary part of the refractive index, k, of a material. The intensity of light at a depth, z, is given by: IZI0 eK(4pkz/l). One way to estimate the maximum thickness of a metal film that ellipsometry can measure, presuming that the top layer is the only one being measured is to use the expression dwl/pk (5.16). Therefore, at lZ632.8, the following thicknesses can be measured: TiNw18 nm; Tiw17 nm; amorphous Siw107 nm; and Co 12 nm [98]. Since the requirements are for thicker films, ellipsometry is not in wide spread use for control of Ti and TiN deposition. As mentioned in Section 24.3.2, SWE must be supplemented in order to measure film thickness for SiO2 films thicker than w283 nm. The values of Del and Psi repeat themselves after 283 nm making the measurement interpretation ambiguous. This problem has been overcome by use of multiple wavelengths, multi-angle, and SEs make the measurement unambiguous. The correct optical constants must be used for non-thermal SiO2 films such as boron and phosphorous doped silica glass (BPSG) and boron and phosphorous doped TEOS. Thickness measurements for low k dielectrics also require knowledge of the correct optical constants. Manufacturing process control for low k dielectrics can be done even on some complicated film stacks [96]. Some of the proposed new dielectrics have different in-plane, hTE, and out-of-plane, hTM, refractive indices. These materials are characterized by a birefringence which is hTEKhTM. Some polyimide thin films show thickness dependence to their optical (and thermal, mechanical, and electrical) properties due to preferential orientation of the molecular chains in the plane of the film [99]. Ho and co-workers have published the dielectric constants (%1 MHz) and the in-plane and out -of- plane refractive indices at lZ632.8 nm [99]. As discussed in Section 24.3 of this chapter, the complex refractive index is the square root of the complex dielectric constant. At optical frequencies, the dielectric behavior is due to electric polarization while below 10 MHz the dielectric constant has contributions from electric and lattice polarization (Figure 24.41). 24.4.1.5
Metal Line Thickness and Copper Void Detection by Metal Illumination
The thickness of patterned metal lines can be measured in-line using Metal Illumination [95,100]. Borden has described this method which determines line resistance by measuring the thermal conductivity [95,100]. One can calibrate system response for un-patterned metal layers, as well as, measure the thickness of patterned metal lines. Resistance is a function of the line cross-section. The system used to measure metal line thickness as well as voids in patterned structures uses an 830 nm laser to inject heat into one or more metal lines [100]. The measurement is illustrated in Figure 24.42. Visualizing the measurement process is useful for understanding its application to void determination. Borden describes the process in detail in Ref. [100]. Absorption of light from an 830 nm laser heats the metal lines within the spot diameter of 2 mm. The heating laser is modulated at kHz frequency. The heat flows away from this spot along the un-pattered film or along the lines away from the heated spot. This results in a temperature distribution. Under the laser spot used to heat the metal, the temperature is inversely proportional to the line cross-sectional area A and thermal conductivity K (Tw1/(AK)). Because the thermal and electrical conductivities of pure metals are related by the Wiedemann-Franz law, one can determine electrical conductivity and thus resistance if one measures the temperature of the metal lines [95]. The peak temperature varies as the resistance per unit length (Tw1/(As)Zr/A), with s the electrical conductivity and r the resistivity. A 980 nm laser is used to measure the reflectance of
Pump laser Probe laser
Measurement spot
Temperature probe laser spot Heating laser spot
Metal lines Temperature
Thin line Insulator Thick line Distance
FIGURE 24.42 Metal illumination. Metal illumination can measure metal film and metal line thickness as well as detect voids in copper metal lines. The pump laser heats the metal film or metal lines, and the reflectivity of the probe laser light measures the resistivity of the metal. The resistivity value determines film or metal line thickness. Figure courtesy Peter Borden of Applied Materials.
copper as a function of temperature. The signal intensity will oscillate at the kHz frequency of the heating laser. Detection of voids in copper metal lines and contact/via structures is a difficult task. Many of the proposed methods rely on the small change in volume of copper due to the presence of voiding. The challenge is to observe these volume changes when across wafer uniformity varies due to changes in metal line thickness. Variation in metal line thickness is a result of the different polishing rates of thick lines vs. dense lines vs. isolated lines. Metal illumination and ISTS have been applied to detection of voids in patterned copper metal structures. In metal illumination, copper voids in metal lines are detected by the temperature change from the void induced reduction in the line cross-section. This effect has been experimentally verified using SEM cross-sections [100]. Voiding measurements are conducted by measuring a series of closely spaced sites (typically with site spacing smaller than the beam diameter) along a structure such as an isolated line or a via chain. This approximates a continuous scan along the line. In Reference [100], it is reported that metal illumination can detect a 1% voiding volume for voids that are 15% of the line cross-section down to 65 nm wide copper lines. At these dimensions, the void diameter is 52 nm with a density NVoidZ1.9 per microns for 90 nm wide lines and 37 nm diameter voids with a density of 2.7 per micron for 65 nm wide lines [100]. This density of voids per unit length is about equal one void in the measurement spot size of 2 mm. Ref. [100] also reports that the issues associated with CMP induced non-uniformity can be minimized by selecting the appropriate method of scanning. Voids in contacts and vias can also be detected by the change in thermal conductivity that the void induces. When a good metal line or lines are scanned with metal illumination, the heat can be conducted away from the metal lines by the presence of a good via connection to the next metal level. Thus, the
temperature drops as one scans across the via. When the via has a void or is not connected to the metal line below, the temperature does not drop as much as it does for the good via [100]. In via measurements this method has an advantage over volume-based measurements. Structures such as via chains are designed with fat links and small vias in order to minimize the effect of a variation of link resistance. The MI method passes a current of heat through the via, and is thus predominantly sensitive to the via resistance change. Volume-based measurements will be equally sensitive to changes in link and via volume [100]. 24.4.1.6
Pore Size Distribution in Porous Low k
Characterization of the distribution of pore sizes is a critical part of the analysis of porous films. Above, we described the use of x-ray reflectivity for measurement of film thickness. This method uses the specularly reflected x-rays (angle inZangle out), and it is an excellent method of measuring low k film thickness even for complicated stacks. As the x-rays transverse the low k film, the pores scatter x-rays away from the specular angle. This is also called diffuse scattering of x-rays by pores. Analysis of the intensity of the non-specularly scattered x-rays vs. the angle of incidence of the x-ray beam provides information on the pore size and the distribution of the pore size within the porous material [101]. The diffusely scattered x-rays need to be separated from the specularly reflected x-rays. There are a number of means of separating these signals. Moving the sample slightly away from the alignment used for x-ray reflectivity (XRR) allows use of existing XRR systems. Some suppliers have developed special detectors that capture diffuse scattering from a greater range of angles. The pore size distribution and average pore size is calculated from the scattering intensity vs. angle using well established x-ray theory and a model for the pore size distribution [101].
24.4.2 Ex-Situ Chemical Mechanical Polishing Process Control–Film Flatness and Quality The purpose of CMP is to produce a flat surface over device topology for lithographic patterning. The CMP is used in both traditional metallization and Damascene (inlaid metal) processing. In traditional metallization processes, metal is deposited, patterned, etched, and overcoated with oxide which is polished flat. In Damascene (inlaid metal) processes, oxide (or low k dielectric) is deposited, patterned, and etched, and metal fill is deposited and then polished back to oxide. The CMP must be monitored for
Recess Erosion
Sheet resistance (ohm/cm)
"A"
Line width (a) 0.475,0.8,5,10
Line space (a) 0.35,0.6,3.75,12.55
Bus width (a) 0,10,40
FIGURE 24.43 Defects in inlaid metal CMP processes. Figure from Farkas, J., and M. Freedman, In Proceedings of the Fourth Workshop on Industrial Applications of Scanned Probe Microscopy, NIST, May, 1997. With permission.
Step height (Å)
Bus lines (10 – 40 mm)
Min. pitch snake (0.25– 0.8 mm)
Condition"A"
Condition"B"
Condition"C"
400 500 600 700 800 Distance (μm)
FIGURE 24.44 Comparison of CMP process conditions using high resolution profilometry. Figure from Farkas, J., and M. Freedman, In Proceedings of the Fourth Workshop on Industrial Applications of Scanned Probe Microscopy, NIST, May, 1997. With permission.
both local flatness within a die and across the wafer. The CMP can generate some radial variation in removal across the wafer. Both traditional and Damascene process are adversely effected by this radial variation in removal rate. Over etching of contact and via structures at the edge of the wafer can result when an oxide layer over metal is over thinned toward the wafer edge. In this case, optical film thickness is used to monitor oxide CMP for traditional metallization processes to ensure that differences in thickness of the oxide layer do not result in over etching during fabrication of contact/via openings. Stylus profilometry or scanned probe microscopy are used to determine film flatness after CMP. The local topography across a die is known to induce non-uniform polishing, and particles in the slurry used during CMP can either be left on the surface or produce scratches that can result in yield loss. Scratches, pits, and residual particles have been referred to as localized irregularities [102]. Dishing, erosion, and recess result in insufficient planarity [103]. In Figure 24.43 we show some of the types of polishing defects that result in insufficient planarity. Process development requires careful monitoring of test structures. In Figure 24.44, we show an example of the recess of a CMP processed test structure under 3 different polishing conditions [103]. The test structure has several different types of metal lines: bus lines, bond pads, and minimum feature size metal lines. The CMP of layers containing contact and via
FIGURE 24.45 (KLA-Tencor).
Profilometry characterization of CMP of via and contact structures. Figure courtesy Jason Schneir
CMP of traditional metal processes Expanded view of Local surface topography
Global oxide surface
Pattern below Oxide Wafer
CMPof damascene (inlaid metal) Expanded view of Local surface topography Global surface
FIGURE 24.46 Process monitoring requirements for CMP of tradition metal and damascene (inlaid metal) processes. The local topography must be monitored over the area of lithographic exposure, while the radial variation of thickness must also be monitored. Optical thickness measurements can be used to determine the local variation of oxide thickness in traditional CMP to insure that via/contact etch processes do not "over etch".
structures must also be monitored during process development. Local scans are used to characterize the recess of tungsten plugs after CMP as shown in Figure 24.45. Issues associated with local flatness and global over-polishing is shown in Figure 24.46 for both traditional and Damascene processes. Stylus profilometers and the new, high resolution profilometers provide information on planarity both locally and globally. The lithographic exposure tool images the reticle mask over the distance of a die (w25 mm!25 mm) with a limited depth of focus (!600 nm using 248 nm exposure tools for 180 nm technology generations). The KLA-Tencor HRP-200 uses a diamond probe tip with a tip radius of 0.05 mm and a scan length of up to 205 mm. A lateral resolution of 1 nm is possible when local areas are analyzed [102]. The step height repeatability is 0.8 nm for features that are 1 mm in height. Maps from wafer flatness tools (such as profilometers) may become part of the lot by lot database of metrology data management systems. In-line process control for CMP is done using test structures which are processed after a change in recipe or polishing pads on the CMP tool.
In-FAB FIB
Focused ion beam systems are now available in two versions, with dual electron beam and ion beam columns and as ion beam systems only [104]. FIB can be supplemented with a SIMS and the dual column systems can also be equipped with EDS. FIB has been used in-FAB for control of trench capacitor and contact/via structures. FIB cross-sections of these structures allow detailed imaging of critical titanium nitride
Acknowledgments I thank and acknowledge Jimmy Price, P.Y. Hung, Ben Bunday, and Hugo Celio for their assistance with revising this chapter. I gratefully acknowledge the review and figures from Peter Borden (Carrier and Metal Illumination) and discussion and review by Michael Gostein (ISTS). I also acknowledge those that helped with the chapter that appeared in the first addition of this volume: Arnie Ford, Dan Holladay,
Hershel Marchman, Kevin Monahan, Chris Nelson, Paul Tobias, Harland Tompkins, George Collins, George Brown, Steve Weinzeirl, John Hauser, Jimmy Wortman, Mathew Banet, John Hanselman, Gary Schwartz, and Randy Goodall.
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In-Situ Metrology 25.1 25.2 25.3
Gabriel G. Barna Texas Instruments, Inc.
Brad VanEck SEMATECH
Introduction ...................................................................... 25-1 Process State Sensors ........................................................ 25-4
Temperature † Gas Phase Reactant Concentration Properties † Wall Deposition Sensor
Wafer-State Sensors ........................................................ 25-31
Film Thickness and Uniformity
Feature Profile
Measurement Techniques for Potential Sensors........... 25-47
Software for In-Situ Metrology ..................................... 25-53
Ellipsometry
Epi Resistivity and Thickness
Data Collection Software † FDC Analysis Software Model-Based Process Control Software
Use of In-Situ Metrology in SC Manufacturing .......... 25-55
Fault Detection and Classification † Fault Interdiction Fault Prognosis † Model-Based Process Control
References .................................................................................... 25-57
Since the early 1960s, semiconductor manufacturing has historically relied on statistical process control (SPC) for maintaining processes within prescribed specification limits. This is fundamentally a passive activity based on the principle that the process parameters—the hardware settings—be held invariant over long periods of time. The SPC then tracks certain unique, individual metrics of this process— typically some wafer-state parameter—and declares the process to be out-of-control when the established control limits are exceeded with a specified statistical significance. While this approach has established benefits, it suffers from (a) its myopic view of the processing domain—looking at one, or only a few parameters and (b) its delayed recognition of a problem situation—looking at metrics generated only once in a while or with a significant time delay relative to the rate of processing of wafers. In the late 1990s, while semiconductor manufacturing continues to pursue the ever-tightening specifications due to the well-known problems associated with the decreasing feature size and increased wafer size, it became clear that both these constraints have to be removed in order to stay competitive in the field. Specific requirements are that † processing anomalies be determined by examining a much wider domain of parameters; † processing anomalies be detected in shorter timeframes; within-wafer or at least wafer-to-wafer; † processing emphasis be focused on decreasing the variance of the wafer-state parameters instead of controlling the variance of the set points. Advanced process control (APC) is the current paradigm that attempts to solve these three specific problems. Under this methodology, the fault detection and classification (FDC) component addresses 25-1
the first two requirements, model-based process control (MBPC) addresses the last one. In contrast to the SPC methodology, APC is a closed-loop, interactive method where the processing of every wafer is closely monitored in a time scale that is much more relevant (within-wafer or wafer-to-wafer) to the manufacturing process. When a problem is detected, the controller can determine whether to adjust the process parameters (for small deviations from the normal operating conditions) or to stop the misprocessing of subsequent wafers (for major deviations from the standard operating conditions). The APC paradigm is a major shift in operational methods and requires a complex, flexible architecture to be in place to execute the above requirements. A schematic representation of this architecture is provided in Figure 25.1. Briefly, this system starts with the processing tool and sets of in-situ sensors and ex-situ metrology tools to provide data on the performance of the tool. When the performance exceeds some pre-defined specifications, actions can be taken to either terminate the processing or reoptimize the settings of the equipment parameters via the model tuner and the pertinent process models. The purpose of this brief APC overview was to provide the context for this chapter on in-situ metrology. In-situ sensors are becoming more widespread, as they are one of the key components of this APC paradigm. The goal of this chapter is to detail the fundamentals of in-situ process and wafer-state sensors in original equipment manufacturer (OEM) tools, and their use in APC, as this is the path that semiconductor manufacturing now has to aggressively pursue. This message is clearly articulated in the 1997 version of the National technology roadmap for semiconductors (NTRS), which states: "To enable this mode of operation (APC), key sensors are required for critical equipment, process, and wafer-state parameters. It is essential that these sensors have excellent stability, reliability, reproducibility, and ease of use to provide high quality data with the statistical significance needed to support integrated manufacturing" [1]. Hence, this chapter will provide information for the in-situ sensors that are commercially available (i.e., not test-bed prototypes) and are currently, or soon will be, used in OEM tools for the measurement and control of process state and wafer-state properties. In-situ sensors are those that monitor the process state of the tool or the state of the wafer during the processing of each wafer. For the sake of completeness, in-line sensors will also be included, as some of the sensor technologies are only applicable in this format. In-line sensors measure wafer state in some location close to the processing, such as a cool-down station in a deposition reactor or a metrology module on a lithography track system. Metrology tools that are currently used off-line, but are seen to be moving towards a simpler in-situ or in-line sensor embodiment CONTROLLER Adaptation strategy Model tuner
SPC Methods
Ex situ Metrology
Process models Solution strategy Targets Feedforward
Solver (Optimize) Out of bounds
Diagnosis and maintenance
Predicted outputs Optimal settings
Data reduction
In-situ Sensor
Architecture for advanced process control.
(e.g., ellipsometer, Fourier transform infrared (FTIR) film thickness) will be included. Sensors used for tool development (e.g., intrusive RF probes, spatially resolved spectroscopy) are not included. Sensors used for gas flow and pressure control are also omitted, as these are well-established technologies; while in-situ particle sensors are covered in the chapter on contamination free manufacturing. For each sensor described, the following information will be included based on input from the sensor manufacturer: † the fundamental operating principle behind each sensor, with greater detail for the less-common ones; † practical issues in the use and interfacing of these sensors. When a number of manufacturers exist for a given sensor, references will be provided to several manufacturers; although there is no claim that this list will be totally inclusive. The sensors included in this chapter are ones that provide most of the features of an ideal in-situ sensor. These features are low TABLE 25.1
Web Links to Major Companies Manufacturing Sensors for Semiconductor Manufacturing
Sensor Company
Nanometrics
http://www.nanometrics.com
Advanced Energy Digital Instruments
http://www.advanced-energy.com http://www.di.com
ENI Ferran Scientific Ircon KLA-Tencor
http://www.enipower.com http://www.ferran.com/main.html http://www.designinfo.com/ircon/ html http://www.kla-tencor.com
Leybold Inficon, Inc.
http://www.inficon.com
Lucas Labs Luxtron Ocean Optics Nova Measuring Instruments
http://www.LucasLabs.com http://www.luxtron.com http://www.oceanoptics.com/ homepage.asp http://www.nova.co.il
On-Line Technologies, Inc.
http://www.online-ftir.com
Panametrics
http://www.industry.net/ panametrics http://www.prinst.com http://www.quantumlogic.com http://www.rudolphtech.com/ home http://www.semitest.com http://www.scientificsystems. physics.dcu.ie http://www.sctec.com/sctinfo.htm http://www.sig-inst.com http://www.microphotonics.com/ sofie.html http://www.sopra-sa.com http://spectra-rga.com http://www.specinst.com http://www.thermawave.com http://www.thermionics.com http://www.verityinst.com
Princeton Instruments Quantum Logic Corporation Rudolph Technologies, Inc. SemiTest Scientific Systems SC Technology Sigma Instruments Sofie Instruments Sopra Spectra International Spectral Instruments Therma-Wave Thermionics Verity Instruments
Product Scatterometer, Fourier transform infrared (FTIR) RF systems, sensors AFM for chemical–mechanical polishing (CMP) (offline) RF probes Residual gas analysis (RGA) Noncontact IR thermometers Stress, thin film measurement, wafer inspection, metrology Residual gas analyzer (RGA), leak detectors, full wafer interferometry, quartz crystal microbalance (QCM) Plasma diagnostics Endpoint for plasma and CMP Spectrometer-on-a-card Spectrophotometric integrated thickness monitors for CMP FTIR spectrometer for wafer state and gas analysis Moisture, O2 analyzers Imaging, spectroscopy Pyrometry Ellipsometer Epi layer resistivity Langmuir probe, plasma impedance Reflectometry for coaters QCM Interferometer, optical emission spectroscopy (OES), ellipsometer Spectroscopic ellipsometry RGA Spectrophotometers, CCD cameras Thin film and implant metrology Diffuse reflectance spectroscopy OES, spectral ellipsometer
cost, reliability, ease of integration into the processing tool, with sensitivity to equipment, and process variations over a broad range of processing conditions. The highest level sorting will be by the major process state (temperature, gas phase composition, plasma properties, etc.) and wafer-state (film thickness, thickness uniformity, resist thickness and profile, etc.) sensors. The major focus is on the technology behind each sensor. Applications will be described only when they are not necessarily obvious from the nature of the sensor. Any particular application example is not intended to promote that particular brand of sensor, but (1) it may be the only available sensor based on that technology or (2) the specifics may be required to provide a proper explanation for the use of that type of sensor. Links to the major companies selling sensors are in Table 25.1.
Process State Sensors
Sensors exist for monitoring both the process state of a particular tool and the wafer state of the processed wafer. The wafer state is of course, the critical parameter to be controlled, hence measurement of the appropriate wafer-state property is clearly the most effective means for monitoring and controlling a manufacturing process. However, this is not always possible due to † lack of an appropriate sensor (technology limitation); † lack of integration of appropriate sensors into processing tools (cost, reliability limitations). In the above cases, the alternative is to monitor the process state of the manufacturing tool. In many cases, this is an easier task achieved with less expensive sensors. Nonintrusive RF sensors can be connected to the RF input lines, or the tuner, of a RF-powered processing tool. A range of optical techniques exists which require only an optical access to the processing chamber. Historically, the most predominant use of such process state sensors has been for endpoint determination. This is generally performed by the continuous measurement of an appropriate signal (e.g., intensity at a specific wavelength) during the processing of a wafer, looking for a change in the magnitude of the signal. Aside from endpoint determination, the availability of process state sensors in OEM processing tools is generally paced by integration issues (electrical, optical, cost, reliability). In addition, there is generally a lack of the necessary models that relate these process state measurements to the critical wafer-state properties. Especially due to this limitation, many of the process state sensors are typically employed for fault detection. This is the simplest use of such sensors, where the output is monitored in a univariate or multivariate statistical method, to determine deviations from the "normal" processing conditions. This methodology has a significant payback to manufacturing yield by an early determination of operational anomalies and hence the decreased misprocessing of wafers. Using process state sensors for process control requires much more rigorous models between the sensor signal(s) and the wafer-state parameter. The following is a description of the sensors that have, or soon will be, integrated into OEM processing tools for use in FDC or MBPC.
The measurement and control of wafer temperature and its uniformity across the wafer are critical in a number of processing tools, such as rapid thermal processing (RTP), chemical rapor deposition (CVD), physical rapor deposition (PVD), and epitaxial (EPI) used for film growth and annealing. Historically, the most commonly used temperature measurement techniques are thermocouples and infrared pyrometry. Infrared pyrometry is based on analysis of the optical emission from a hot surface. It is dependent on two main variables: field of view of the detector and the optical properties of the material, such as refractive indices and emissivity. While useful only above 4508C due to the low emissivity of semiconductors in infrared, pyrometry has been commercialized and is widely utilized in semi conductor (SC) manufacturing tools. A newer technique is diffuse reflection spectroscopy (DRS), which provides noncontact, in-situ optical method for determining the temperature of semiconducting
In-Situ Metrology TABLE 25.2
Pro and Con for Four Temperature Measurement Techniques
Easy to use Low cost
Pyrometer
All-optical, noninvasive Requires a single optical port
Diffuse reflectance spectroscopy
Optical, noninvasive Directly measures substrate temperature Insensitive to background radiation Can be applied to a wide range of optical access geometries Wafer temperature mapping capability Sample emissivity not a factor Wide temperature range
Acoustic thermometry
Disadvantages Cannot be used in hostile environment Requires mechanical contact with sample Sensitivity depends on placement Unknown or variable wafer backside emissivity Limited temperature range Sensitive to all sources of light in environment Requires two optical ports Relatively weak signal level
Intrusive to the reaction chamber Physical contact required
Source: Adapted from input by Booth, J., Thermionics Northwest, Port Townsend, WA. http://www.thermionics.com
substrates. The technique is based on the optical properties of semiconductors; specifically that the absorption coefficient rapidly increases for photon energies near the band gap of the material. Hence, a semiconducting wafer goes from being opaque to transparent in a spectral region corresponding to its band gap energy. A temperature change of the semiconductor is accompanied by a change in the band gap, which is then reflected as a shift of this absorption edge. Recently, an acoustic technology has been developed. The advantages and disadvantages of these four techniques are presented in Table 25.2. Thermocouples are sometimes used for temperature measurement in processing tools. Since they have to be located remotely from the wafer, temperature errors of more than 1008C are possible; with no means for monitoring the temperature distribution across the wafer. Hence, this sensor is not widely used in SC manufacturing tools, so it will be omitted from this discussion. 25.2.1.1
Pyrometry
Precise wafer temperature measurement and tight temperature control during processing continue to be required because temperature is the most important process parameter for most deposition and annealing processes performed at elevated temperature [2]. As device features become smaller, tighter control of thermal conditions is required for successful device fabrication. Optical temperature measurement is historically the primary method for in-situ wafer temperature sensing. Known as pyrometry, optical fiber thermometry, or radiation thermometry, it uses the wafer's thermal emission to determine the temperature. The optical fibers (sapphire and quartz), or a lens, are mounted on an optically transparent window on the processing tool and collects the emitted light from, in most cases, the backside of the wafer. The collected light is then directed to a photo detector where the light is converted into an electrical signal. 25.2.1.1.1 Theory of Operation All pyrometric measurements are based on the Planck equation written in 1900, which describes a blackbody emitter. This equation basically expresses the fact that if the amount of light emitted is known and measured at a given wavelength, then the temperature can be calculated. As a consequence of this phenomenon, all pyrometers are made of the following four basic components: † collection optics for the emitted radiation; † light detector;
† amplifiers; † signal processing. There are thousands of pyrometer designs and patents. A thorough description of the theory and the many designs, as well as the most recent changes in this field are well summarized in recent books and publications [3–6]. The two largest problems and limitations with most pyrometric measurements are the unknown emissivity of the sample—which must be known to account for the deviations from black-body behavior, and stray background light. In addition, the measurement suffers from a number of potential errors from a variety of sources. While the errors are often small, they are interactive and vary with time. The following is a summary of these sources of error, roughly in order of importance: 1. 2. 3. 4. 5.
Wafer emissivity: worst case is coated backsides with the wafer supported on pins. Background light: worst case is RTP and high energy plasma reactors. Wafer transmission: worst at low temperatures and longer wavelengths. Calibration: it has to be done reproducibly and to a traceable standard. Access to the wafer: retrofits are difficult for integrating the sensor into the chamber.
The following problems will become much more important as the previous problems are minimized by chamber and pyrometer design. 6. Pyrometer detector drift: electronics (amplifiers) and photo detectors drift over time. 7. Dirt on collection optics: deposition and outgassing coat the fiber or lens. 8. Changes in alignment: moving the sensor slightly can cause an error by looking at a different place on the wafer or by changing the effective emissivity of the environment. 9. Changes in the view angle: changes the effective emissivity and hence the measured temperature. 10. Changes in wavelength selective filters: oxidation over years will change the filters. Careful design of the entire pyrometer environment, not just the pyrometer itself, can serve to minimize these problems. Nearly all single-wafer equipment manufactures now have pyrometry options for their tools. Properly designed sensor systems in single-wafer tools can accurately measure wafers quickly (onetenth of a second) from about 250 to 12008C with resolution to 0.058C. The continually increasing process requirements will continue to push the pyrometric measurement limits to lower temperatures for plasma assisted CVD, cobalt silicide RTP, and plasma etch. The need for lower temperatures will mandate more efficient fiber optics. There will be a continued improvement in real-time emissivity measurement. Physical properties other than thermal radiance will also be used for measuring wafer temperatures. Repeatability will have to improve. The problem of unknown or changing emissivity is being addressed with the implementation of the ripple technique [7], which takes advantage of the modulation in background light to measure real-time wafer emissivity. This method can measure emissivity to G0.001 at a rate of 20 times per second. 25.2.1.2
25.2.1.2.1 Theory of Operation Semiconductor physics provides a method for the direct measurement of substrate temperature, based on the principle that the band gap in semiconductors is temperature dependent [8]. This dependence can be described by a Varshni equation [9]
Eg ðTÞ Z Eg ðT Z 0ÞK
aT 2 ðb C TÞ
where a and b are empirically determined constants. The behavior of the band gap is reflected in the absorption properties of the material. If a wafer is illuminated with a broadband light source, photons with energy greater than the band gap energy are absorbed as they pass through the material. The wafer is transparent to lower energy (longer wavelength) photons. The transition region where the material goes
GaAs (semi-insulating) spectrum
Signal (arb.)
Absorption edge
Transparent region
Opaque region
Wavelength (nm)
FIGURE 25.2 Spectrum of 350-mm thick gallium arsenide (GaAs) wafer showing the absorption edge where the wafer goes from being opaque to transparent. (Adapted from input by Booth, J., Thermionics Northwest, Port Townsend, WA. http://www.thermionics.com)
from being transparent to opaque occurs over a relatively narrow energy (or wavelength) range. Thus, a plot of light signal level passing through the material as a function of wavelength or energy (its spectrum) yields a step-like absorption edge, as shown in Figure 25.2. The position of the absorption edge shifts in energy or wavelength as the substrate temperature changes. The magnitude of the shift is material dependent. 25.2.1.2.2 Band Edge Measurement Techniques There are several different techniques for measuring the optical absorption of semiconductors in-situ: transmission, specular reflection, and diffuse reflection. Transmission measurements observe light that passes through the substrate. This technique has the advantage of providing a high signal-to-noise ratio (SNR). The main drawbacks are that to implement this approach one must have optical access to both sides of the sample and one is limited to single point temperature monitoring. Reflection measurements from a sample can be separated into two components: specular reflection and diffuse reflection. Specularly reflected light is the familiar "angle of incidence equals angle of reflection" component. The diffusely scattered portion is light that is reflected from the sample over 2p steradians and carries with it color and texture information about the sample. The main differences between diffuse and specular reflection are: 1. Diffuse reflection can be seen over a wide range of angles, while specular reflection can only be observed from a narrow region in space. 2. Diffuse reflection is much weaker than specular reflection. 3. Both diffuse and specular reflections carry with them color and texture information. However, it is much easier to read this information from diffuse reflection because it is not buried under a large background signal level. 25.2.1.2.3 Band Edge Thermometry Limitations There are two limitations to band-edge temperature measurement techniques: (1) free carrier absorption in the material and (2) coating the substrates with opaque material.
In semiconductors, there are a number of different phenomena that contribute to light absorption in the material. One of these is the so-called free carrier absorption. This absorption term is related to the number of carriers excited into the conduction band from the valence band. Free carriers are thermally excited and the free carrier absorption increases with sample temperature. This absorption occurs over a broad wavelength range and the material becomes more opaque as the temperature rises. The substrate band edge feature decreases in intensity until, above a material dependent threshold temperature, it can no longer be seen. In general, the smaller the band gap, the lower the temperature at which the substrate will become opaque. For silicon, the upper temperature limit for DRS temperature measurement is approximately 6008C, while for gallium arsenide the upper limit is estimated to be above 8008C. The second limitation arises when the substrate is covered with an opaque material such as a metal. In this situation, light cannot penetrate the metal layer and consequently no band edge spectra can be recovered. Two remedies for this situation are: leaving an open area on the substrate for temperature monitoring purposes and viewing the substrate from the nonmetallized side. 25.2.1.2.4 Temperature Measurement: Practice and Applications The initial application of band edge thermometry [10] measured the heater radiation that passed through a substrate to deduce the sample temperature. This approach suffered from a decreasing SNR as the heater temperature dropped. As in pyrometry, it was susceptible to contamination from other light sources present in the processing environment. Later on [11–13], two key innovations were introduced to the original transmission technique: (1) the use of an external modulated light source to illuminate the sample and (2) collection of the diffusely reflected source light to measure the band edge. The DRS technique is shown schematically in Figure 25.3. Part of the light is specularly reflected, while the other is transmitted through the sample. At the back surface, some of the transmitted light is diffusely scattered back towards the front of the sample. The collection optics are placed in a nonspecular position and the captured diffusely scattered light is then analyzed. The net result is a transmission-type measurement from only one side of the wafer. A DRS temperature monitor [14] is shown schematically in Figure 25.4. The system consists of a main DRS module housing the monochromator, power supplies, and lock-in amplifier electronics. The light source and collection optics attach to the exterior of the processing chamber. Data collection and analysis are controlled by a stand-alone computer. The system can output analog voltages for direct substrate temperature control and can communicate with other devices using an RS-232 interface. The device is capable of 1 s updates with point to point temperature reproducibility of G0.28C. The system can read
Specular refelection Diffuse refelection
Wafer Wafer mount
FIGURE 25.3 Schematic showing the diffuse reflection spectroscopy measurement technique. (Adapted from input by Booth, J., Thermionics Northwest, Port Townsend, WA. http://www.thermionics.com)
Light collection module
DRS-1000 Unit
Light input module Substrate material
FIGURE 25.4 Diffuse reflection spectroscopy 1000e temperature monitoring system schematic. (Adapted from input by Booth, J., Thermionics Northwest, Port Townsend, WA. http://www.thermionics.com)
silicon, gallium arsenide, and indium phosphide substrates from below room temperature to 600, O800, O7008C, respectively. The DRS technology has been applied to both compound semiconductor and silicon processing. In molecular beam epitaxy and its related technologies, such as chemical beam epitaxy (CBE), material is grown layer by layer by opening shutters to molecular sources. The quality of the layers depends, in part, on the temperature and temperature uniformity of the substrate. In typical growth environments, the wafer temperature is controlled by a combination of thermocouple readings and pyrometer readings. The DRS can monitor and control the temperature of a gallium arsenide (GaAs) wafer in a CBE tool to well within G18C [15]. Even though band edge thermometry has a fixed upper temperature limit of w6008C for silicon, this technique is still applicable to several silicon processing steps, such as silicon etching [16], wafer cleaning, and wafer ashing. 25.2.1.3
Acoustic Wafer Temperature Sensor
Recently, a new technology has been developed for real-time wafer temperature measurement in semiconductor processing tools [17]. This product [18] is based on state-of-the-art acoustic thermometry technologies developed at Stanford University. This sensor fills the need for real-time wafer temperature measurement independent of wafer emissivity, especially in the sub-6008C process regime. It is compatible with plasma processes and mechanical or electrostatic wafer clamping arrangements. 25.2.1.3.1 Theory of Operation The velocity of acoustic waves in silicon is a very linear function of temperature. Acoustic thermometry accurately measures velocity of an acoustic wave on the silicon wafer to determine the temperature of the wafer. The acoustic thermometer determines the velocity by very accurately measuring a delay between two points at a known distance. In its simplest implementation, the acoustic thermometer contacts the wafer with two pins, as shown in Figure 25.5. One pin is a transmitter, and the other a receiver. Both pins have a piezoelectric transducer mounted to their lower end. Both piezoelectric transducers can turn an electrical excitation into an acoustic excitation, or vice versa. The tops of the two pins touch the wafer, to allow the transfer of acoustic energy between the wafer and the pins. The pins can be of any inert, relatively stiff material, such as quartz (fused silica) or alumina. An electrical excitation pulse excites the transmitter pin's transducer to initiate the measurement. This excites an acoustic wave that propagates up the transmitter pin. When the wave reaches the top
Transmitter signal
Acoustic wave propagation Transmitter pin with transducer
Excitation pluse
Receiver pin with transducer
Echo signal
Receiver signal
Signal transmitted through Si wafer Acoustic wave time of flight through Si wafer
FIGURE 25.5 Geometry and electrical signal for acoustic thermometry. (Adapted from input by Sensys Instruments, Sunnyvale, CA.)
of the pin, two things happen to the acoustic energy. Most of the energy reflects back down the pin. The reflected energy gives rise to an electrical echo signal at the transmitter's transducer. A small amount of the acoustic energy enters the silicon as an acoustic wave, which propagates out from the transmitter pin. When the acoustic wave reaches the receiver pin, a small portion of its energy excites an acoustic wave that propagates down that pin. That wave produces the electrical signal at the receiver pin's transducer. The echo signal corresponds to propagation up a pin and down a pin. The received signal corresponds to propagation up a pin, across the wafer, and down a pin. If the pins are identical, the delay between the received and the echo signals corresponds to propagation on the wafer over the known distance between the transmitter and the receiver pins. The ratio of the distance to the delay is the velocity of the acoustic wave in the wafer, and is thus an indicator of the wafer temperature. The temperature sensor is the wafer itself. Since the acoustic thermometer measures the velocity of propagation between the two pins, it measures an average temperature of the wafer along the propagation path between the pins, and not just the temperatures at the pins. Additional pins can yield average temperatures over multiple zones on the wafer. The acoustic wave extends across the whole thickness of the wafer. Thus, the measured temperature is an average over the thickness of the wafer as well. It is not particularly sensitive to the lower surface of the wafer, even though the pins only touch the lower surface. This sensor can be designed to operate as the lift pin mechanism in single-wafer processing tools. The sensor does not influence or contaminate the wafer environment. The pin assembly has to be integrated into the OEM tool for the successful deployment of this technology.
Gas Phase Reactant Concentration
Most semiconductor manufacturing processes are chemical in nature. Typically, there is a chemical reaction between a gas phase chemical species (or mixture) with the surface layer of the silicon wafer. These reactions can be kinetically controlled, hence the interest in the wafer temperature. But they can also be controlled by the composition and concentration of the gas phase reactants. These parameters therefore have to be monitored and controlled in order to provide consistent, reproducible reactions, and wafer-state properties. Processing tools always control the primary components of these gas phase mixtures (flow rate of the gases, pressure). However, there is still a clear need for measuring the composition and/or the concentration of individual species to detect:
† changes in the chemistry as a function of the chemical reaction with the wafer, i.e., endpoint for etch; † changes in the chemistry due to spurious conditions or faults (e.g., leaks, wrong gas); † rapid changes or a slow drift in the gas phase chemical composition due to reactor chamber effects, such as cleaning, residue formation on the walls, wear of consumable parts within the reactor. A large group of in-situ sensors for gas phase monitoring are spectroscopic in nature, as these are truly nonintrusive sensors. They require optical access through a single (sometimes opposing) windows, which are made of materials that can provide a vacuum seal and are transparent to the wavelengths being employed. The sensors analyze the composition of the gas phase via absorption or emission methods, as appropriate for a given process. The spectral range is from the UV through the IR, depending upon the nature of the information required. Mass spectroscopy, in the commonly used residual gas analysis (RGA) mode, provides another class of in-situ sensors used for monitoring gas composition. These are based on the analysis of the masses of the species (specifically, m/e) entrained in the gas flow. Sampling can be performed via a pin-hole orifice to the processing chamber, or by sampling the effluent from the reactor. A typical installation requires differential pumping of the RGA, although some of the recent systems do not have this requirement in selected low-pressure applications. 25.2.2.1
Optical Emission Spectroscopy
Optical emission spectroscopy (OES) is based on [19] monitoring the light emitted from a plasma during wafer processing and is used to gain information about the state of the tool and the process. It exploits the fact that an excited plasma emits light at discrete wavelengths which are characteristic of the chemical species present in the plasma. The intensity of the light at a particular wavelength is generally proportional to both the concentration of the associated chemical species and the degree of plasma excitation. An OES system consists of a viewport to the plasma chamber, an optical coupling system, an optical detector incorporating some means of isolating the wavelength of interest, and a computer or processor to acquire