I hope you've had a chance to try my last recipe for cheese, olive and onion bread. It's a great variation of the original, but that doesn't mean the original isn't still useful. Today's recipe will show you one of the things you can make using it.
I love this Breakfast Casserole for Sunday mornings, and especially when I have company for Brunch. Since those of you following either Paleo and Keto plans don't eat a lot of fruit, this is a great way to indulge in some of those super healthy berries without overdoing it.
If you're looking for more Brunch recipes, see my Brunch post here.
By the way, don't be surprised that this serves six. It really does. Unlike normal breakfast casseroles that are mainly bread ( which doesn't fill you up at all ) this Paleo bread has lots of almonds and eggs in it already before the extra eggs that are added to it, so you will find a sixth of this casserole is more than filling, even for the biggest eaters.
Serve this with a side of bacon or sausage and it will be hours before you're hungry again.
Put the cut up bread and the frozen blueberries into your baking dish.
Add the vanilla, cream, sweetener and spices.
Pour the egg mixture over the bread cubes and blueberries.
Bake for 40 to 50 minutes, or until the eggs are set.
Remove the casserole from the oven, put on a cooling rack or trivet, and let it stand for at least 15 minutes so it can set.
Divide into 6 and serve. I like to offer a variety of toppings - blueberry puree, sugar-free syrup, and/or more whipping cream or coconut milk.
This is a great weekend breakfast dish. You can either serve it right away or cut it into portions, put in freezer bags, and freeze for later. To serve, eat either cold or heated for a few minutes in your microwave or oven.
Blueberries are such a healthy fruit in so many ways, and splurging once a week on this delicious Blueberry Breakfast Casserole is a great way to make sure you get all the benefits while still sticking to your food plan.


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Jeremy Schwartz joins Kantar as Practice Chairman for Sustainable Transformation
Kantar, the world's leading data, insights and consulting company, today announce the addition of Jeremy Schwartz, former CEO of The Body Shop and Pandora, to the leadership team of Kantar's Sustainable Transformation Practice. Mr Schwartz joins Kantar in the role of Practice Chairman, with a broad remit focused on increasing marketplace visibility for the practice, alongside C-suite engagement.
Jeremy Schwartz was the CEO for The Body Shop, Pandora and Conival PLC and Managing Director for L'Oréal UK. Previously, he held senior marketing roles as CMO for News International, European Innovation and Marketing Director for Coca-Cola and Brand Director for Sainsbury's supermarkets. He adds his role with the Kantar Sustainable Transformation Practice to his advisory position with McKinsey's Business Transformation Practice.
As Chairman and CEO of The Body Shop – which operates in 66 countries – he spearheaded a new company purpose and with it a commitment to innovate in sustainability, biodiversity and business models. His leadership style and global experience has promoted employee and community inclusion in all aspects of business.
Throughout Jeremy's career he has been the architect of a number of business, channel and brand transformations which are all highly relevant to the process of creating, planning and delivering new sustainability and diversity agendas with clients.
Kantar's Sustainable Transformation Practice launched in March 2020 and in October released the publication of Realising the Value of Good Intentions. The report identified the need for traditional competitors to recognize the power and momentum in collaboration, evaluate how their business models can transition to circularity and how to take responsibility for the usage phase of the product lifecycle. More recently the practice held a one-day conference outlining how to address sustainability risks and get ahead of emergent opportunity.
Commenting on his new responsibilities, Jeremy said, "I look forward to supporting c-suite clients and the practice team with delivery of sustainability and inclusion initiatives at pace to support the planet, the business and societal needs: the triple bottom line."
Jonathan Hall, Sustainable Transformation Practice Managing Partner, added: "Jeremy is known as a purpose-driven leader who has had a proven impact on many organizations. He brings an expertise and passion around the intersection between sustainability and commerciality, together with a deep CEO- and CMO-level understanding in operationalizing sustainability. Jeremy's experience and stature will significantly enhance the capabilities and visibility of our Sustainable Transformation Practice."

redpajama_set_name: RedPajamaCommonCrawl


text:
+Account Login
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Firland Line Card 2021
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Grants FAQ
Past Research Grants
This area of funding addresses our mission of support for medically underserved individuals with chronic respiratory problems. Research studies are usually conducted by fellows and faculty of the Division of Pulmonary and Critical Care Medicine and the Division of Pediatric Pulmonary Medicine at the University of Washington in Seattle. Grants range, on average, from $5,000 to $20,000. Results of these studies are often presented at international meetings such as the American Thoracic Society and published in refereed journals. The following list of selected studies illustrates the typical scope of funded studies.
A Pilot Study of Nutritional Supplementation for Malnourished HIV-TB Co-Infected Adults in Senegal. University of Washington (PI: Noelle Benzekri). $22,000
Autophagy, ULK-1, and Pediatric TB. University of Washington (PI: Andrew Graustein). $20,000
TB Needs Assessment among Tribal Communities throughout Washington, Oregon, Idaho, and Alaska. Firland Northwest TB Center (PI: David Horne). $25,000
The Effect of Maternal Antibodies on Infant BCG Vaccine Immunogenicity. University of Washington (PI: Lisa Cranmer). $20,000
Seattle Pilot Project for Video Observed Therapy. Public Health Seattle & King County, TB Control Program (PI: Lisa Skow). $74,220
Tuberculosis and HIV Transmission in the African Population in the U.S. Public Health-Seattle and King County/University of Washington (PI: Roxanne Kerani). $14,475
Assessing Effectiveness of Tuberculosis DOTS Program among Public and Public Private Mix Facilities in Karachi: A Cross Sectional Survey. The Aga Khan University (PI: Amin Pethani). $1,953
Mincle and the Human Immune Responses to Tuberculosis. University of Washington (PI: Javeed Shah). $19,000
The Frequency and Mortality Associated with Mycobacterium tuberculosis Genotypes Causing Bacteremia within Hospitalized HIV-Infected Ugandan Patients. University of Washington (PI: Shevin Jacob). $20,187
TB Diagnostics in HIV-Infected Pregnant Women: A Pilot Study. University of Washington (PI: Sylvia LaCourse). ($20,000)
Tuberculosis Infection and Genetic Variation. University of Washington (PI: David Horne). $14,640
Role of CD1 in Protecting Against Tuberculosis in Infants. University of Washington. (PI: Chetan Seshadri). $20,000
Pilot Study: TB (IGRAs) in HIV-1 Infected Women of Kenya. University of Washington. (PI: Grace John-Stewart) $19,875
Chronic Lung Diseases
Development of a Low Cost Ultrasonic Spirometer. CitizenMedical. (PI: Chris Hallberg). $23,910
Childhood Interstitial Lung Disease at Seattle Children's Hospital: A Retrospective and Prospective Study of Diagnosis, Treatment and Outcomes. University of Washington/Seattle Children's Hospital. (PI: Jennifer Soares). $20,000
The Role of TGF Beta Signaling in Hyperoxia-Induced Lung Injury and Fibrosis. University of Washington/Seattle Children's Hospital. (PI: Laurie Eldredge). $19,986
Pro-inflammatory, Pro-remodeling, and Oxidative Stress Profiles of Bronchial Epithelial Cells Obtained from Asthmatic and Non-Asthmatic Children to Urban Particulate Matter Exposure. Seattle Children's Hospital/University of Washington (PI: Kensho Iwanaga). $19,009
Yoga as a Therapy for Adolescents and Young Adults with Cystic Fibrosis: A Pilot Study. Seattle Children's Hospital, University of Washington. (PI: Jennifer Ruddy) $19,970
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The curator has been working hard preparing an exhibit which will open tomorrow. The exhibit is entitled The Mission Makers and features Albert Lacombe, OMI and Alexandre Taché, OMI, two oblates who began the mission in St. Albert. We've included in this blog post some photos of the exhibit set-up. The exhibit opens Saturday June 11 and will be up until November 2011.


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Oculus Rift demo puts you in the Battle of Endor
By Andy Chalk
Have you ever found yourself with an Oculus Rift strapped to your face, and no real idea what to do with it next? Allow me to make a suggestion: Hop into the cockpit of an X-Wing starfighter and enjoy a front-row seat for the Battle of Endor.
The video is taken from an Oculus Rift X-Wing simulator being developed by James Clement, who wrote on YouTube that it "still needs a lot of polish" but made it available for download for those who want to try it anyway. Unfortunately, it hasn't been updated since September; the most recent related video, a demonstration of a technical issue with flickering shadows, went up at the end of September.
The video starts off fairly slowly, but the intensity jumps up dramatically when the order to engage the capital ships at point-blank range comes in. Twisting around the massive Mon Calamari cruiser and then strafing the Star Destroyer provides a scale and sense of speed that the opening minutes lack, although it loses momentum again once the fighter dives into the exhaust port: There's no sense of anything at all happening beyond a pleasant, traffic-free cruise through a four-lane tunnel.
This kind of first-person, in-cockpit experience is exactly what the Oculus Rift is surely made for, and somewhat surprisingly, it doesn't take a whole lot of hardware to make it happen: According to the Oculus page, the Battle of Endor sim was tested on a 2.4 GHz dual-core AMD CPU with 6GB RAM, and a laptop with an unspecified 2.4 GHz CPU and 16GB of RAM. It's clearly not as polished as, say, Elite: Dangerous, but it's free. And it's Star Wars! Get the details at Oculus.com (opens in new tab).
Andy Chalk
Andy has been gaming on PCs from the very beginning, starting as a youngster with text adventures and primitive action games on a cassette-based TRS80. From there he graduated to the glory days of Sierra Online adventures and Microprose sims, ran a local BBS, learned how to build PCs, and developed a longstanding love of RPGs, immersive sims, and shooters. He began writing videogame news in 2007 for The Escapist and somehow managed to avoid getting fired until 2014, when he joined the storied ranks of PC Gamer. He covers all aspects of the industry, from new game announcements and patch notes to legal disputes, Twitch beefs, esports, and Henry Cavill. Lots of Henry Cavill.


Although touted as a documentary on what's going on behind making a Hollywood feature film, it really is more of a reality TV series. Executive produced by Ben Affleck and Matt Damon, it was thoroughly engaging and entertaining to watch. Just don't believe everything that was being shown. The following article by Slash Film explains how certain scenes were manipulated by editing, just as all reality TV shows do to make their shows more entertaining.
The main conflict in the show is set between Jason Mann, the Project Greenlight winner given US$3 million to make his first feature film under HBO Films, and the producer Effie Brown. Their differences were apparent from the beginning and their spats simply got worsen till the final episode. Again, it makes for very good TV as both Jason and Effie are relatable characters that divided the audience into two camps, each rooting for their preferred personality.
Nevertheless, whether completely true or not, Project Greenlight is one of the best TV shows that can give movie buffs and aspiring filmmakers glimpses into the 'glamorous' industry which in truth is one of the hardest to work in.
I remembered a filmmaking masterclass I have attended years ago. The speaker started his class by discouraging the audience to stay away from the industry and refrain from ever becoming a director. He declared the director job as the most difficult job in the world. Still, many aspiring filmmakers are mesmerised by great movies and dream of making their own films one day.
Project Greenlight offers us one of the closest and most comprehensive look at what goes on behind the process today. It shows the reality of how difficult the jobs of director and producer really are, but I think that will hardly deter anyone from their determination to enter the industry. That's the magic of films.


Color mixing is done at the LED level, and each optic projects the same color as neighbouring optics.
LEDs project different colors with color mixing being achieved outside the fixture when the beams blend with each other.
Ideal for applications where powerful color changing light is necessary.
36 monochromatic LEDs delivering powerful light.
Many color choices available along with specialty colors Blue and Amber.


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Workplace NeuroDiversity Rising – Start Making Immediate Changes to the World Around You
January 16, 2023 January 16, 2023 Lyric Holmans
Workplace NeuroDiversity Rising is intended to be a tool that can help ANYONE who wants to make the world, or the spaces around them more inclusive for NeuroDivergent (and all) People, in organizations, communities, schools, and beyond. Continue reading Workplace NeuroDiversity Rising – Start Making Immediate Changes to the World Around You
UpdatesLeave a comment
January 1, 2023 January 1, 2023 Lyric Holmans
If you would have told me at the beginning of 2022, that by the end of the year I would be the author of a best-selling business ethics book (Workplace NeuroDiversity Rising) that would be praised in Forbes as "an excellent 'how to manual' based on lived experience and professional competence" I'm not sure I would have believed it. Continue reading 2022 Was Amazing and I am EXCITED about 2023


Set the position and angle of the body.
Note that the position may not be the center of mass of the body. An angle of 0 radians will mean "looking to the right". Although radians increase counter-clockwise, the y axis points down so it becomes clockwise from our point of view.
The x component of the position.
The y component of the position.


The skull on the left has the distinctive characteristics of a Polynesian person. A Polynesian skull, when viewed from behind, forms the shape of a pentagon. These skulls were in the basement of the Humboldt museum in Winnemucca Nevada some forty years ago and have since disappeared. The angle that the photo below was taken clearly show the double rows of teeth of this Polynesian giant. What was a Polynesian skull doing in Northern Nevada?
The photo below has a Polynesian skull that has been mounted for display. Notice the Pentagonal shape of the skull.
The Original Photos of a Giant's Skull From Lovelock Cave.
These photos are original prints taken some forty years ago in the basement of the Humboldt museum in Winnemucca Nevada by Don Monroe. The Museum now denies the existence of this and other skulls. Why???
Notice what appears to be "double rows" of teeth.


text:
China to Give $150 million in Aid to El Salvador as Relationship Deepens
Nov 08, 2018 Politics Comments Off on China to Give $150 million in Aid to El Salvador as Relationship Deepens
SAN SALVADOR China will give El Salvador $150 million to spur development of social and technological projects, the Salvadoran president said on Wednesday, the latest sign of deepening ties between the countries that has alarmed the United States.
Salvadoran President Salvador Sanchez Ceren is returning from his first trip to China since the countries established diplomatic ties in August. Speaking on local television, Ceren said he met with Chinese President Xi Jinping during the visit and agreed to 13 joint projects, without providing details.
The donation marks China's latest gambit to make inroads in Central America, a campaign that has drawn the ire of the United States. Earlier this year, El Salvador cut diplomatic ties with Taiwan in favor of China, following the Dominican Republic and Panama. The United States promptly recalled its ambassadors in the region.
"This historic meeting between the governments of the People's Republic of China and the Republic of El Salvador has produced excellent results," Ceren said. "This confirms that the establishment of diplomatic relations with China is my government's most important decision in foreign policy."
Representatives for the Chinese government were not immediately available for comment.
The date when the funds will be received has not been set, a spokesman for the Salvadoran government said. China will also donate three thousand tons of rice to support Salvadorans who are reeling from a drought in July and floods in October, Ceren said.
The White House warned in August that China was luring countries with incentives that "facilitate economic dependence and domination, not partnership. Self-ruled Taiwan has formal relations with a dwindling number of countries, almost all of them small and less developed nations in Central America and the Pacific.
Acuva UV LED…รูปแบบการทำลายเชื้อโรคที่มีความกะทัดรัด ประหยัดพลังงาน และมีกำลังการทำลายเชื้อโรคมากที่สุดในโลกสำหรับอุปกรณ์ OEM แบบบูรณาการ StackPath Joins Cybersecurity Tech Accord


New vehicle. Sold in 2008.
Patented model. All-purpose European tráiler-truck suitable for ´´C´´ and ´´C+E´´ license according to the Spanish regulations, RD 818/2009. Doble Cab. ABS. Three pedal Dual Control. Roof Spoiler. Visor. Work lamps. Pneumatic horn. Instructor's seat with pneumatic suspension. Radio-CD. Air conditioning.


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UFC to crown women's featherweight champion at February's UFC 208
The UFC is introducing a new title with one well-known fighter notably missing out of the first match for the gold.
On ESPN Tuesday night, it was revealed that former UFC women's bantamweight champion Holly Holm will battle fellow bantamweight fighter Germaine de Randamie to become the inaugural UFC women's featherweight champion.
The fight will headline UFC 208 at the Barclays Center in Brooklyn, NY, on February 11th.
Surprisingly, Cris 'Cyborg' Justino is not involved as during media interviews last week, Dana White said Justino turned down two opportunities to fight for the title. Justino cited needing recovery time from the hard weight cut she endured before her September beatdown of Lina Lansberg.
Justino was the final Strikeforce women's featherweight champion and is the current Invicta women's featherweight champion.
Holm has been quiet since losing to Valentina Shevchenko in July, her second straight defeat. The 35-year-old rose to prominence with her November 2015 knockout of Ronda Rousey, but lost to Miesha Tate in dramatic fashion in her first defense of the gold.
The 32-year-old de Randamie has finished two straight opponents, but has fought just twice in the last three years.
UFC needed a main event for the show, given they just postponed their January PPV and were running out of time to start the promotional plan for February. That would lead one to believe that the men's featherweight championship unification bout between Jose Aldo and Max Holloway will not be on that February 11th show as Aldo alluded to Monday.
As of now, Holm vs. de Randamie is the only fight announced for the show.
icymiUFC 208holly holmheadlinesufc


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AP Exams (Nationwide)
All high school level students are eligible to take Advanced Placement (AP) exams. Accommodations can be made for students with disabilities, home-schooled students, and students whose schools do not offer AP courses. For more information, see the College Board's AP Program Guide.
AP exams are usually administered in the first two-weeks of May every year.
For the full exam schedules, visit the AP College Calendar.
Test Structure
Each of the 38 exams has its own unique requirements; however, almost all of the exams have several things in common:
- Most exams are two to three hours long.
- The first part of the exam usually consists of multiple-choice questions.
- Students will choose one of four or five answer choices for each question.
- Multiple-choice section: Students will not receive or lose points for incorrect answers or unanswered questions.
- The second part of the exam usually consists of free-response questions that require students to generate their own responses.
- Depending on the exam, responses could be in the form of an essay, a solution to a problem, or a spoken response.
- In most cases, students will write their response in pen in the free-response exam booklet.
There are 38 types of AP exams offered in Arts, English, History and Social Sciences, Math and Computer Science, Sciences, World Languages and Cultures as well Interdisciplinary.
The content for all can be found here.
Most exams are two to three hours long and are given in the first two-weeks of May every year.
The AP Exam score is a weighted combination of scores on the multiple-choice section and the free-response section. AP Exam scores are reported on a 5-point scale that indicates how qualified students are to receive college credit and placement.
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When something goes wrong it is human to look for someone to blame. In weight issues as well, especially because weight in our view is connected to beauty, rather than health. I mean aesthetics come first, health comes second.
Nowadays, after so much mentioning even our children finally started looking obese, even to our loving eyes, and who is to be blamed? Some groups claim it is all Ronald McDonald's fault because we all trusted him and wanted to eat more for his sake. So, McDonald's Corporation first of all, it is being mentioned most of the time, and there are movies made about it, then Burger King, I guess they are also kind of frequently mentioned. Then Coca Cola, corn syrups, sugars, you name it.
And given a chance to become healthier, they still are not.
Ok, imagine we can ban McDonald's and the rest of the gang, since they are not going to correct anyways. Let's imagine it's a done deal. Now what? Can you imagine your fridge without coke? Can you see yourself as a veggie lover, brown rice, small portion eater, only green tea-no-sugar drinker, walker, biker, runner and dancer?
When your child wants some ice cream, are you going to say no? Or think that he will be unhappy without it, because all other children have it. And they sure will yell and ask for sweets because they watch tv commercials about "immune boosting", sugar loaded cereals and other sweets and you cannot do anything about that. If you can stand him and restrict him from all those temptations, do you know what are you going to feed him instead?
Now the news claim that our pets are obese. They sure watch commercials too.
BTW, the yogurt which is advertised as healthy is not healthy at all, if you want healthy stuff, mix some plain yogurt with fresh-cut fruit, and no sugar at all.


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package com.sonoport.freesound.response.mapping;

import static org.junit.Assert.assertEquals;

import org.json.JSONObject;
import org.junit.Test;

import com.sonoport.freesound.response.BookmarkCategory;

/**
 * Unit tests to ensure the correct operation of {@link BookmarkCategoryMapper}.
 */
public class BookmarkCategoryMapperTest extends MapperTest {

	/** URL to use in tests. */
	private static final String URL = "http://www.freesound.org/people/frederic.font/bookmarks/category/23840/";

	/** Name of category. */
	private static final String NAME = "Rooms";

	/** Number of sounds in category. */
	private static final int NUMBER_OF_SOUNDS = 1;

	/** URL to list of sounds in category. */
	private static final String SOUNDS_URL =
			"http://www.freesound.org/apiv2/users/frederic.font/bookmark_categories/23840/sounds/";

	/** Instance of {@link BookmarkCategoryMapper} to use in tests. */
	private final BookmarkCategoryMapper mapper = new BookmarkCategoryMapper();

	/**
	 * Ensure that a properly formatted JSON representation of a bookmark category is correctly converted into a
	 * {@link BookmarkCategory} object.
	 *
	 * @throws Exception Any exceptions thrown in test
	 */
	@Test
	public void parseBookmarkCategory() throws Exception {
		final JSONObject bookmarkCategoryJSON = readJSONFile("/bookmark-category.json");

		final BookmarkCategory bookmarkCategory = mapper.map(bookmarkCategoryJSON);

		assertEquals(URL, bookmarkCategory.getUrl());
		assertEquals(NAME, bookmarkCategory.getName());
		assertEquals(NUMBER_OF_SOUNDS, bookmarkCategory.getNumberOfSounds());
		assertEquals(SOUNDS_URL, bookmarkCategory.getSoundsURL());
	}
}

redpajama_set_name: RedPajamaGithub


1999-04-19 Assigned to NEOMAGIC CORPORATION reassignment NEOMAGIC CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MATHUR, HARISH N.
A search engine for a network switch reads a routing table for an entry with a matching MAC or IP address. The routing table is contained in an embedded DRAM. The search engine and the embedded-DRAM routing table are integrated together on the same integrated circuit chip, allowing a very wide data path between the search engine and the routing table. A free-running sequencer outputs addresses to the routing table so that each entry is read in a continuous-loop sequence. The same entry is sent to comparators for all active searches. Destination addresses for different input ports are compared to the entry read from the table. A match ends the search for a port while searches for other ports continue. Since ports can begin and end searches at any point in the continuous-loop sequence, a same low latency is provided for all input ports, even when other searches are in progress. The wide data path from the embedded-DRAM allows several entries to be read and compared for each cycle and for each port. Thus multiple entries are compared in parallel for each port, and ports are searched in parallel.
This invention relates to computer networks, and more particularly to searching a routing table to configure a network switch.
Computer networks such as local-area networks (LANs) and larger wide-area networks (WANs) route data packets from one station to another often through intermediate nodes. Recently network switches making switching decisions based on multiple OSI Layers have become favored for connecting different stations on a LAN or different LANs on a corporate backbone network. These network switches have a higher throughput than earlier hubs or repeaters since multiple connections may be dynamically made and broken between different pairs of network nodes as needed, and they significantly reduce network congestion experienced in the shared media.
FIG. 1 is a diagram of a prior-art system that configures a network switch based on a search of a routing table using a microprocessor. Routing table 20 contains entries for different network addresses. These entries may be for lower-level media-access-controller (MAC) addresses on a LAN or higher-level Internet-Protocol (IP) addresses for a WAN. Each entry contains a MAC or IP address and a port number. Incoming packets to network switch 22 contain a destination address, such as a MAC and/or IP address. For some switches capable of performing multi-layered switching, the IP address may only be searched if the MAC address matches. The traditional routers are networked devices, and they only do IP-address searches. This destination address from the incoming packet is compared to the addresses in the entries in routing table 20 until a match is found. Then the port number for the matching entry is used to configure network switch 22, so that the data from the incoming port is forwarded to the output port identified by the port number from the matching entry in routing table 22.
Central processing unit (CPU) 10 monitors the input ports of network switch 22 for incoming packets. When an incoming packet is detected, CPU 10 reads the destination address of the new packet. Then CPU 10 executes a search routine to look for a matching entry in routing table 20. Once a matching entry is found, CPU 10 sends instructions to network switch 22 over bus 16 to establish a connection between the input port receiving the new input packet and the output port identified by the port number from the matching entry in routing table 20.
When CPU 10 is a general-purpose processor, CPU instructions are read from memory 12 over bus 16 before CPU 10 executes each instruction. The search routine is a series of such instructions contained in code block 18 in memory 12. For each entry in routing table 20, several instructions are fetched from code block 18, and the entry itself is read from routing table 20 in memory 12. Thus several accesses of memory 12 over bus 16 are required. Caching of instructions in CPU 10 can reduced traffic on bus 16, but usually caches are not large enough to contain routing table 20.
For each entry in routing table 20, the entry must be read from routine table 20 and compared to the destination address, which is stored in a register in CPU 10. Within CPU 10, arithmetic-logic-unit (ALU) 14 compares the destination address to the address in the entry read from routing table 20. This compare is repeated for each entry read from routing table 20 until a match is found.
Thus many accesses of memory 12 by CPU 10 are required to search routing table 20. Other incoming packets for other input ports may be detected before the search is complete. The search for these other incoming packets may need to be delayed until the first search is completed. Thus the delay or latency for these subsequent packets is increased. System throughput may be decreased, or a faster, more expensive CPU is needed to reduce delay and latency. However, the search must still be performed serially resulting in ports waiting in long queues while waiting for the CPU to finish the on-going search.
Some hardware-assisted search chips (integrated circuits) are being developed. For example, a dedicated search engine may be used rather than ALU 14 in CPU 10. This dedicated search engine can be directly coupled to the memory containing routing table 20. While this hardware improves the efficiency of the search engine compared to using the CPU, it does not solve the problem of serial search. Furthermore, the speed of the search is limited by the bandwidth (number of pins allocated to the table memory).
The assignee has recognized the problem of bottlenecks to external dynamic-random-access memory (DRAM) in graphics display systems, and has pioneered embedded DRAM for graphics controllers. See for example: Puar et al., "Graphics Controller Integrated Circuit Without Memory Interface", U.S. Pat. Nos. 5,650,955 and 5,703,806. These embedded-DRAM graphics controllers have been used predominantly for portable PC's such as laptop and notebook PCs.
Although graphics controllers are in a different technical field hand network switches, the inventor has realized that such embedded DRAM technology could solve performance and cost problems for network switches. While many view embedded DRAM technology as useful only for portable systems, the inventor realizes that computer-network routers could benefit from the performance and cost improvement of embedded DRAM.
What is desired is a search engine for a network switch. It is desired to have a dedicated search engine search a network routing table for an entry with a matching MAC or IP address. It is further desired to use an embedded DRAM containing the routing table. It is desired to locate the search engine and the embedded DRAM on the same integrated circuit chip, allowing a very wide data path between the search engine and the routing table. It is further desired to increase the speed of the search engine by using an ultra-wide data path to the routing table. A parallel architecture for the search engine is also desired to allow searches for different input ports to occur at the same time, increasing throughput and decreasing latency. It is desired to provide a same low latency for all input ports even when other searches are in progress. A highly-parallel multiple-port search engine is desired.
A parallel-search integrated circuit has a free-running sequencer that repeatedly outputs a sequence of addresses in a loop. A table stores a plurality of entries. The table outputs an entry in response to an address from the free-running sequencer.
A plurality of search engines are included. Each search engine receives the entry from the table. A first search engine compares at least a portion of the entry to a first input and generates a first match signal when the first input matches the at least a portion of the entry. A second search engine compares the at least a portion of the entry to a second input and generates a second match signal when the second input matches the at least a portion of the entry. A third search engine compares the at least a portion of the entry to a third input and generates a third match signal when the third input matches the at least a portion of the entry.
The free-running sequencer repeats the sequence of addresses once all entries have been read from the table. The first search engine begins a search once the first input is received, beginning the search at any address in the sequence of addresses and continuing until all entries have been compared by the first search engine or until the first match signal is generated. The second search engine begins a search once the second input is received, beginning the search at any address in the sequence of addresses and continuing until all entries have been compared by the second search engine or until the second match signal is generated. Likewise, the third search engine begins a search once the third input is received, beginning the search at any address in the sequence of addresses and continuing until all entries have been compared by the third search engine or until the third match signal is generated.
The first, second, and third search engines perform overlapping searches that begin and end at different times and at different addresses in the sequence. Thus parallel searches are performed.
In further aspects of the invention, the table is contained in an embedded dynamic-random-access memory (DRAM) integrated on a same silicon chip as the free-running sequencer and plurality of search engines. Thus the table is in the embedded DRAM. An internal bus is coupled between the table and the plurality of search engines. The internal bus transfers the entry from the table to the plurality of search engines.
In still further aspects, the internal bus is a wide bus having a width sufficient to transfer a group of multiple entries to each search engine in the plurality of search engines for each memory access cycle of the embedded DRAM. The first search engine compares at least a portion of each of the multiple entries to the first input and generates a first match signal when the first input matches the at least a portion of any of the multiple entries. Likewise, the second search engine and the third search engines each compare at least a portion of each of the multiple entries to the second or third input and generates a second or third match signal when the second or third input matches the at least a portion of any of the multiple entries. Thus multiple entries are compared for each memory access cycle from the embedded DRAM.
In still further aspects the table is a network routing table. Each entry contains a network address that is compared by the first search engine to a first destination address applied to the first input. It is also compared by the second search engine to a second destination address applied to the second input, and it is compared by the third search engine to a third destination address applied to the third input. Thus the network routing table is searched for an entry that matches a destination address.
FIG. 1 is a diagram of a prior-art system that configures a network switch based on a search of a routing table using a microprocessor.
FIG. 2 is a diagram of a network-switch router that uses a search engine with an embedded-DRAM routing table.
FIG. 3 shows a search chip with an embedded-DRAM routing table that searches up to four input ports in parallel.
FIG. 4 shows a search chip with an embedded DRAM table for searching 4 entries and 4 ports in parallel.
FIG. 5 shows a search chip with an internal 1024-bit bus connecting an embedded-DRAM routing table with a search array.
FIG. 6 illustrates a parallel search chip with a variable-width entry compare.
FIG. 7 highlights search timing, showing that searches can begin and end at any time.
FIG. 8 highlights parallel-entry search timing, showing that searches can begin and end at any time.
FIG. 9 is a diagram of a comparator for a 48-bit MAC address.
FIG. 10 is a diagram of a comparator for a 32-bit address.
FIG. 11 highlights a search engine with an embedded-DRAM routing table that cascades entry registers to reduce loading on the DRAM bus.
The present invention relates to an improvement in network route-table searching. The following description is presented to enable one of ordinary skill in the art to make and use the invention as provided in the context of a particular application and its requirements. Various modifications to the preferred embodiment will be apparent to those with skill in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.
The inventor has realized that embedded DRAM technology could solve performance and cost problems for a search of a network routing table. While many view embedded DRAM technology as useful only for portable-computer graphics-display systems, the inventor realizes that a routing table search engine could benefit from the performance and cost improvement of embedded DRAM.
The inventor also realizes that unusually wide data paths are feasible with embedded DRAM. These wider data paths allow more table entries to be retrieved in a cycle, increasing bandwidth. Different, highly-parallel architectures are then possible for the search engine.
FIG. 2 is a diagram of a network-switch that uses a search engine with an embedded-DRAM routing table. Search chip 30 is an integrated circuit (IC) that contains an embedded dynamic-random-access memory (DRAM). Routing table 20 is contained in the embedded DRAM. Using DRAM rather than faster external static RAM (SRAM) allows for a much larger memory size, allowing for more entries in routing table 20.
Since each output port may connect to other routers, hubs, repeaters, or network connections, each output port may require many entries since many addresses are routed through the output port. As many as 8K or more entries in routing table 20 are required for a network switch. For 64-bit entries, a memory size of 512 Kbits is needed for the 8K entries when the bus width is 1024 bits.
When a new incoming packet to an input port of network switch 22 is detected, the packet's destination address captured by the media-access-controller (MAC) is loaded into port register 26 on search chip 30. Entries from routing table 20 are read and sent to comparator 24, which compares the MAC address from port register 26 to the MAC address in the selected entry from routing table 20. When no match is detected by comparator 24, the next entry in routing table 20 is read and compared.
Once a matching MAC address is detected by comparator 24, the port number from that match entry is sent to network switch 22 along with a match signal. The match signal causes network switch 22 to make a connection from the input port to the output port identified by the port number from the matching entry. The incoming packet is then forwarded across the connection to the output port toward its final destination. Once the packets are transmitted, the connection in the switching fabric of network switch 22 can be broken.
CPU 10 may still be used for oversight functions, executing code 18′ from memory 12. However, code 18′ does not search the routing table but merely performs higher-level functions such as initializing network switch 22, performing error recovery, and accumulating network statistics. ALU 14 in CPU 10 is not used for the compare function when routing table 20 is searched. Thus the many instructions for searching each entry in routing table 20 are not executed by CPU 10 and are not fetched from memory 12. Entries from routing table 20 are not sent over bus 16. Bandwidth requirement on bus 16 is greatly reduced, allowing a slower CPU 10 to be used. CPU 10 and memory 12 may even be eliminated in some systems.
Since routing table 20 and comparator 24 are integrated onto the same search chip 30, external pins are not needed for transferring the entries. A very wide internal bus from routing table 20 to comparator 24 may be used. For example, a 256-bit internal bus can transfer 4 entries in a single access cycle. This would require a 300-pin chip if an embedded DRAM was not used.
In another example, a 1024-bit internal bus allows 16 entries of routing table 20 to be sent to comparator 24 for each memory access cycle. Such a transfer rate would require perhaps a 1200-pin chip, or multiple chips, making the cost prohibitive. Thus putting routing table 20 in an embedded DRAM allows 4 to 16 or more entries to be searched in parallel by search chip 30 thus reducing the latency by the same factor.
FIG. 3 shows a search chip with an embedded-DRAM routing table that searches up to four input ports in parallel. Sequencer 38 generates a sequence of 8K addresses, and can be implemented as a 13-bit binary or gray-code counter. When the number of entries in routing table 20 is less than 8K, a smaller counter can be used, or the terminal count can be programmed and the counter reset at the terminal count. Each address in the sequence is for a different entry in routing table 20. Sequencer 38 is driven by a free-running clock, although the clock may be stopped or disabled for power-savings or test modes when no incoming packets are received.
Routing table 20 outputs a different entry for each address received from sequencer 38. This entry is latched into all four entry registers 32. When an incoming packet is detected, its destination address is latched into one of port registers 34. As other incoming packets are detected on other ports, their destination addresses are also loaded into other port registers 34. Up to four different destination addresses for four different input ports can be stored in port registers 34. This allows up to four searches for different input ports to be performed simultaneously.
Comparators 36 compare each of the four destination addresses in port registers 34 to the same entry address in each of the four entry registers 32. If any of comparators 36 detects a match, than the output-port number from the entry for that port is output to the network switch and a connection is made. The search for that port ends, but the searches for the other ports continue. Sequencer 38 causes search chip 30 to continuously circulate through all entries in routing table 20.
Each entry read from routing table 20 is thus compared to four destination addresses at the same time. As new packets are detected, new searches can begin immediately. The searches continue as the address from sequencer 38 wraps around from the last table entry to the first entry. A search ends once a matching entry is found. Since a search can begin at any point in the table, the length of time until a match is found is indeterminate. However, the maximum time is 8K cycles, the time to read all entries. There is no initial delay while a previous search completes.
Such a parallel-port search chip 30 uses just a 64-bit bus between routing table 20 and entry registers 32, since each entry is 64 bits. However, much wider internal busses are contemplated, greatly increasing search bandwidth.
FIG. 4 shows a search chip with an embedded DRAM table for searching 4 entries and 4 ports in parallel. The internal bus from the embedded-DRAM routing table 20 to entry registers 32 is increased to 256 bits. This allows four 64-bit entries to be read and transferred from routing table 20 during each memory access cycle.
For 8K table entries, sequencer 38 is modified to count to 2K, with each address outputting four table entries. An 11-bit counter can be used. Sequencer 38 moves ahead by four table entries for each clock pulse.
The four entries read from routing table 20 are loaded into the four entry registers 32 for port A, and the four entry registers 32 for each of the other three ports. The first entry is loaded into the right-most of the four registers, the second entry into the second of the four registers, the third entry to the third of each port's group of four registers, and the fourth entry of the 256-bit read from routing table 20 is loaded into the left-most of the four entry registers 32 for each port.
When a new incoming packet is detected, its destination addresses is loaded into each of the four port registers 34 for that port. Four comparators 36 compare this single destination address to four different entry addresses in entry registers 32. When one of the four comparators 36 detects a match, the search for that port ends. The port number from the entry register 32 for the comparator 36 detecting the match is sent to the network switch to establish the connection. A policy, such as not allowing data from an unauthorized source, may be applied by performing a similar search on the incoming source address.
Search latency is reduced by a factor of four, since four entries are compared for each memory-access cycle. Up to four different ports may be searched simultaneously.
FIG. 5 shows a search chip with an internal 1024-bit bus connecting an embedded-DRAM routing table with a search array. The internal bus from routing table 20 is increased to 1024 bits, enough to simultaneously transfer 16 64-bit entries in a memory access cycle. Such a wide DRAM interface is not practical for external busses as the pin cost and IC package cost is high.
Sequencer 38 effectively increments by 16 table entries for each clock, so that successive addresses point to a next group of 16 table entries. The maximum latency is reduced to 0.5 K memory-access cycles for a table with 8K entries, since 16 entries are read for each cycle.
The sixteen different 64-bit entries are loaded into the sixteen entry registers 32 for a port. Since there are four search ports (A,B,C,D), each entry is loaded into four entry registers 32, one for each search port.
When a new search begins, the destination address from the incoming packet is loaded into all 16 port registers 34 for an unused search port. The 16 comparators 36 for that search port compare the single destination address to all 16 entries read from routing table 20 in a cycle. Alternately, a single port register could drive all 16 comparators 36 for a search port.
When a match is detected in any one of the 16 comparators 36 for a search port, the output-port number in the matching entry is sent to the network switch, along with the input-port number. The network switch establishes a connection between the input and output ports, allowing the packet to be sent along the next link toward its destination.
While a large number of comparators and registers (64) are required for four search ports, individual registers and compare cells (XOR gates) are small. For a 48-bit MAC address, 48 XOR gates are needed for each comparator 36, or a total of 3072 XOR gates. This is about 10K 2-input NAND equivalent gates.
FIG. 6 illustrates a parallel search chip with a variable-width entry compare. Sequencer 38 is programmable for the address terminal count, allowing the counter to be adjusted to match the number of entries in routing table 20 during each memory circulation.
Entry registers 42 are each loaded with the current group of entries read from routing table 20 for each clock cycle. Destination addresses for up to four input ports are loaded into port registers 44 at the beginning of a search. Exclusive-OR (XOR) blocks 46 compare address bits in entry registers 42 with address bits from port registers 44. When a match occurs, the search ends and the port number for the matching entry is sent to the network switch to establish the connection.
The lower-level MAC address is 48 bits, while the higher-level IP address is 64 bits, with 32 bits for source and 32 bits for destination. When MAC addresses are stored in routing table 20, only 48 bits are compared for each entry by XOR blocks 46. However, when IP addresses are stored in routing table 20, all 32 destination bits are compared for each entry by XOR blocks 46. All 48 bits in a MAC address must match for a MAC match, while all 32 bits in an entry must match for an IP match. Control logic in XOR blocks 46 disables or re-routes some XOR-gate outputs to summing logic as needed for MAC or IP address matching.
Each entry register 42 contains several entries, while the destination address is replicated in port register 44 or routed to the corresponding XOR gates in XOR block 46. The output-port number from the entry may be loaded into entry registers 42, or may not be latched from routing table 20 until a match is found. A separate set of 16 output-port registers may be connected to the 1024-bit internal bus from routing table 20 to act as pipeline registers to hold the output-port numbers. These registers can be read later if a match is detected. Control logic in the comparators allows matching of variable length entries such as 48-bit MAC address or 32-bit IP address.
FIG. 7 highlights search timing, showing that searches can begin and end at any time. Such a timing could be applied to the search chip of FIG. 3. During clock cycle or time slot 1, entry 1 is read from the routing table. Entries 2-7 are read during time slots 2-7. Since the table in this simplified example has only 7 entries, the sequencer wraps back to entry 1, which is read again during time slot 8. Entries 2-7 are read again during time slots 9-14.
A new packet is detected on one of the input ports and assigned to search port A before time slot 1. During time slot 1, entry 1 is read from the routing table and compared to destination address A. During time slot 2, entry 2 is read and compared to destination address A. This continues until a match is found. In the worst case, the match occurs during time slot 7 for entry 7.
Another new packet is detected and assigned to search port C during time slot 2. The first entry read and compared for port C is entry 3, since that is the entry read during time slot 3. Entries 4, 5, 6, 7 are read and compared to destination address C during times 4, 5, 6, 7. Then entries 1 and 2 are compared during times 8, 9. The worst case occurs when entry 2 matches the destination address for port C.
Incoming packets are detected during times 3 and 4 for two other input ports. These are assigned to search ports B and D. Searching for port B begins with entry 4 in time 4 and concludes with entry 3 at time 10, or until an earlier match is detected. Searching for port D begins with entry 5 in time 5 and in the worst-case concludes with entry 4 at time 11. However, an earlier match is found with entry 2 at time 9, so the port-D search ends early. On average, searches should take only half of the maximum search time if the entries are randomly mapped.
At any time, up to four destination addresses can be compared to the same entry address. For example, during time 6, entry 6 from the routing table is compared to destination addresses for ports A, B, C, D. During time 7, entry 7 is compared to destination addresses for all ports A, B, C, D.
FIG. 8 highlights parallel-entry search timing, showing that searches can begin and end at any time. Such a timing could be applied to a search chip such as for FIG. 4 but having only 3 comparators per port rather than 4.
During clock cycle or time 1, entries 1, 2, and 3 are read from the routing table. Entries 4, 5, 6 are read during time 2, while entries 7, 8, 9 are read during time 3. Since the table in this simplified example has only 9 entries, the sequencer wraps back to entry 1, which is read again during time 4. Entries 1-9 are read again during the next three cycle times 4-6.
Since 3 entries are read for each cycle time period, the entire 9-entry table is read in just 3 cycles. Latency is reduced from a maximum of 9 periods to just 3 periods.
A new packet is detected on one of the input ports and assigned to search port B before time 1. During time 1, entries 1, 2, 3 are read from the routing table and compared to destination address B. During time 2, entries 4, 5, 6 are read and compared to destination address B. This continues with entries 6, 7, 8 in time 3 unless a match is found. In the worst case, the match occurs during time 3 for entry 7, 8, or 9.
Another new packet is detected and assigned to search port A during time 1. The first group of entries read and compared for port A is entries 4, 5, 6, since those are the entries read during time 2. Entries 7, 8, 9 are read and compared to destination address A during time 3. Then entries 1, 2, 3 are compared during time 4. The worst case occurs when entry 1, 2, or 3 matches the destination address for port A.
Incoming packets are detected during times 4 and 5 for two other input ports. These are assigned to search ports C and D. Searching for port C begins with entries 4, 5, 6 in time 5 and concludes with entries 1, 2, 3 at time 7, or until an earlier match is detected. Searching for port D begins with entries 7, 8, 9 in time 6 and in the worst-case concludes with entries 4, 5, 6 at time 8. However, an earlier match is found with entry 2 at time 7, so the port-D search ends early.
At any time, up to four destination addresses can be compared to the same 3 entry addresses. For example, during time 6, entries 7, 8, 9 from the routing table are compared to destination addresses for ports C, D.
FIG. 9 is a diagram of a comparator for a 48-bit MAC address. One such comparator is needed for each entry and each search port compared in parallel and thus corresponds to comparators 36 in FIGS. 3, 4, 5.
Each 64-bit routing-table entry has a 48-bit MAC address and a 16-bit output. A new entry is loaded into entry register 32 for each MEM_CLK cycle. The 48-bit MAC address is loaded into sub-register 64, while the 16-bit output is loaded into sub-register 62.
When a new incoming packet is detected, its destination MAC address is loaded into port register 34 by START_SEARCH, which is activated only at the start of a new search, not every memory-clock cycle. XOR gates 66 compare each of the 48 address bits from sub-register 64 to port register 34. This search is repeated each cycle of MEM_CLK. Signal START_SEARCH is synchronized to MEM_CLK to avoid glitches.
When all 48 address bits match, all 48 XOR gates 66 output a low to OR gate 52. OR gate 52 then outputs a low to OR gate 54, signaling a match. OR gate 54 sends a pulse to output register 56 on the next MEM_CLK low, causing the 16-bit port number from sub-register 62 to be latched into output register 56. The port number can then be sent to the network switch.
The 16-bit output may include policy bits and other bits besides a port identifier. These policy bits can be used by hardware to determine a priority for the connection. A route may be selected from among various possibilities using such policy bits or packets may be blocked or unblocked. The actual port identifier may be only 4 bits, depending on the number of ports supported.
FIG. 10 is a diagram of a comparator for a 32-bit IP address. One such comparator is needed for each entry and each search port compared in parallel and thus corresponds to comparators 36 in FIGS. 3, 4, 5.
Each 32-bit routing-table entry has a single 32-bit IP address. A new entry is loaded into entry register 32 for each MEM_CLK cycle. The 32-bit destination IP address is loaded into all of register 32.
When a new incoming packet is detected, its 32-bit destination IP address is loaded into port register 34 by START_SEARCH, which is activated only at the start of a new search, not every memory-clock cycle. XOR gates 66 compare each of the 32 address bits from register 32 to port register 34. This search is repeated each cycle of MEM_CLK.
When all 32 address bits match, all 32XOR gates 66 output a low to OR gate 52. OR gate 52 then signals a match. The port number can then be sent to the network switch.
Control logic that converts the 48-bit matching logic of FIG. 9 to 32-bit matching logic as shown in FIG. 10 can be implemented with widely-available logic synthesis tools rather than explicitly adding muxes and control gates. Thus a variable-width comparator can be implemented with these design tools.
FIG. 11 highlights a search engine with an embedded-DRAM routing table that cascades entry registers to reduce loading on the DRAM bus. The search engines for the search ports may be cascaded so that entries from routing table 20 are passed from one search engine to the next rather than sent to all search engines at the same time.
Sequencer 38 generates a series of addresses to access entries in routing table 20. Each entry read from routing table 20 is sent to first entry register 72. When multiple entries are read from routing table 20 for each clock cycle, first entry register 72 contains all the entries read in parallel. Comparator 70 compares the addresses from the entries in first entry register 72 to the destination address in port register 74 and outputs a match signal when one of the entries matches the destination address. The search for port A then ends and a new search for another incoming packet can be performed using port A.
As the address from the entries in first entry register 72 is being compared by comparator 70, the entries are also passed to second entry register 76 in the second search engine for search port B. During the following clock cycle, comparator 79 compares the second destination address in port B register 78 with the entry in second entry register 76. When a match occurs, port B finishes.
Likewise, as the address from the entries in second entry register 76 is being compared by comparator 79, the entries are also passed to third entry register 82 in the third search engine for search port C. During the following clock cycle, comparator 80 compares the third destination address in port C register 84 with the entry in third entry register 82. When a match occurs, port C finishes.
Each entry or group of entries read from routing table 20 during a first memory-clock cycle are first loaded into first entry register 72, then loaded from first entry register to second entry register 76 during the second clock cycle, and finally transferred from second entry register 76 to third entry register 82 in the third clock cycle, and so on. Thus the compare for comparator 79 is always one entry behind the compare by comparator 70. The compare for comparator 82 is always two entries behind the compare by comparator 70.
Such pipelining of entries reduces the loading of the internal bus from routing table 20, since only one register is loaded. Other registers are loaded in later clock cycles from the other entry registers. Other search ports may be cascaded on to third entry register 82, allowing more than 3 ports to be searched in parallel.
The maximum search time is not increased, since sequencer 38 is free-running and the location of the starting entry is merely changed by the register pipelining. The maximum search time is always the memory-access-cycle multiplied by the number of entries in routing table 20, then divided by the number of entries fetched together from routing table 20.
A search engine for a network switch reads a routing table for an entry with a matching MAC or IP address. An embedded DRAM contains the routing table. The search engine and the embedded DRAM are integrated together on the same integrated circuit chip, allowing a very wide data path between the search engine and the routing table. The speed of the search engine is increased by using an ultra-wide data path to the routing table. A parallel architecture for the search engine allows searches for different input ports to occur at the same time, increasing throughput and decreasing latency. A same low latency for all input ports is provided, even when other searches are in progress. A highly-parallel multiple-port search engine is achieved.
For a 4-entry parallel search engine, a 300-pin chip is needed to achieve the same throughput if an embedded DRAM was not used. In another example, a 1024-bit internal bus allows 16 entries of the routing table to be sent to the comparator for each memory access cycle. Such a transfer rate would require at a minimum a 1200-pin chip, or multiple chips, making the cost prohibitive. Thus putting the routing table in an embedded DRAM allows 4 to 16 entries to be searched in parallel by the search chip. Pin-count and power consumption are reduced by integrating the DRAM with the search engine.
The architecture is scalable such that size of the table, the bus width, the degree of parallelism of the hardware, and the clock speed can be adjusted to meet the requirement of the application. Additionally, this facilitates further integration of the network switch, including physical drivers and the media-access controller (MAC) on the same chip. For example, the bus width can be higher than 1024 and the memory depth can be greater than 8K, depending on the technology used to implement the chip. With the free running sequencer, the maximum search time is predictable regardless of the number of ports and the amount of data passing through the device. The invention allows easy updating of the table, because the entries can be randomly located. An address can be loaded in the table at any available location. Higher clock rates and wide buses enable larger table searches for gigabit data rates at wire speed.
Multiple entries made possible by the wide data bus can also be used to match the source and destination address for both MAC and IP address at the same time, provided the data structure in the table is created to make this possible.
Several other embodiments are contemplated by the inventor. For example dynamic registers or latches may be used for entry registers. FIFO buffers or pipeline latches can be inserted into the circuitry at many points, such as to and from the embedded memory. Multiple tables or banks of embedded DRAM with different contents can be used to simultaneously perform different types of searches with the invention. The embedded DRAM is integrated on a same silicon substrate with the parallel search engines. Other kinds of substrates may be substituted.
Arithmetic comparators may replace the logical comparators for implementing filters in the network hardware. The invention can also be used for searching strings of alpha-numeric characters received on multiple ports. More than one register may be loaded during first clock cycle depending on the drive capability of the table.
Incoming packets on input ports can be dynamically assigned to an available search ports, or input ports can statically share a search port with other input ports. Comparators can be constructed in many ways, using inverting logic such as XNOR gates rather than XOR gates. Depending on the application and the number of ports required, the network switch and the search engine may be integrated on the same semiconductor chip along with MAC and Physical interface drivers.
In order to further enhance the search process and provide some priority scheme, the sequencer may be loaded with a terminal count where there is maximum likelihood of finding a match. The decision to load the terminal count is made elsewhere. Additionally, the routing table shall then be organized with such a data structure.
whereby parallel searches are performed.
whereby the table is in the embedded DRAM.
an internal bus, coupled between the table and the plurality of search engines, the internal bus for transferring the entry from the table to the plurality of search engines.
whereby multiple entries are compared for each memory access cycle from the embedded DRAM.
5. The parallel-search integrated circuit of claim 4 wherein the internal bus comprises at least 256 data bits.
6. The parallel-search integrated circuit of claim 4 wherein the internal bus comprises at least 1024 data bits.
wherein the network routing table is searched for an entry that matches a destination address.
whereby destination addresses are extracted from incoming packets to a network switch.
9. The parallel-search integrated circuit of claim 8 wherein the destination address is a media-access-controller (MAC) addresses or an Internet Protocol (IP) address.
10. The parallel-search integrated circuit of claim 8 wherein each entry further comprises a port identifier, the port identifier indicating which of a plurality of output ports of the network switch should be connected to an input port of the network switch that received a network packet having a destination address that matches the network address from the entry.
whereby parallel searches are performed using same entries read from the routing table means.
whereby multiple entries are read from the routing table means and compared.
13. The switch-based network router of claim 12 wherein the sequencer means increments by multiple entries.
a main memory, coupled to the central processing unit, for storing the control program.
whereby simultaneous temporary connections are made by the network switch.
16. The switch-based network router of claim 12 wherein the routing table means is an embedded dynamic-random-access memory (DRAM) contained within the parallel search chip on a same semiconductor substrate.
whereby a same sequence of entries are read from the routing table and compared by different search engines that begin and end searches at different times.
18. The parallel-search method of claim 17 wherein a same maximum latency until a match is found is obtained for the first, second, and third packets.
ending a search by the third search engine when a match is detected and allowing another search for another input port to use the third search engine.
configuring a network switch to transfer the third packet from the third input port to a third output port identified by the third port identifier.
"A Day in the Life of an LS Packet" Application note, I-Cube, 10/97, pp. 1-19.
ACD80800 Address Resolution Logic Data Sheet.


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text:
DIANA GABALDON'S 2005 LETTER 'IN DEFENSE OF FRANK RANDALL': Frank's Mom Dishes It Out
This is a letter and reply that was posted on Compu-serve in November of 2005. The reply is by Diana Gabaldon and I am posting it here in FULL, without edits, for those who would like to read it, as it is hard to find on that site. Diana is often asked about Frank's 'cheating' and I think she wanted to put things into perspective and like me, she is baffled on why there is so much Frank hate. As a die-hard/full-blown/bitten n' smitten member of #TeamFrank, I was terribly happy to read this! Those who dislike or hate the character and do NOT wish to hear any Truths and Facts by the person who created him, then maybe it's time to go walk the dog or go shopping.... or wash your hair. *wink*
Nov. 12, 2005:
I'm writing because I was asked by ——(nameless individual)——to
intervene in a Huge Argument being debated. (We are trying to avoid
Internet bloodshed and hurt feelings!) Oddly enough, it has nothing to
do with ABOSAA or rather, very little.
The very "heated" discussion is surrounding Frank's role in his
relationship with Claire upon her return from the eighteenth century.
1) WHY did Frank stay with Claire if he wasn't getting the love he
desired/needed? (evidenced by the affairs that he thought Claire knew
nothing about) Why didn't he just leave?
2) Was Claire "cheating" on Frank during this period because her heart
still belonged to Jamie, even though she believed him dead?
(Your/Claire's perspective)
3) IS Frank the "pathetic slime-ball" a couple of people have labeled
him? (Not my opinion or my words, by the way–just relating the
questions). <G>" — Thanks, Susan.
Nov. 13, 2005 Diana's reply:
"As to L'Affaire Frank…<g>
Geez Louise. You guys. <rolling eye>
Of course Frank isn't "a pathetic slimeball." Where do they come up
with these ideas? (My personal guess would be that the people holding
this particular opinion are possibly not that fond of their own SO,
and would trade him in for Jamie in a heartbeat. Ergo, they project
things onto Frank. But that's only a guess.)
Look. In the books, we see Claire and Frank's relationship only from
Claire's point of view. Which is understandably a trifle biased,
following her return through the stones.
What we see prior to her disappearance is an awkward but affectionate
relationship between two people who are married, but who are
effectively strangers-they've barely seen each other in six years, and
have been back together for only a few days. They're feeling each
other out, trying to reestablish the connection they once had, and
struggling to overcome the fact that they are now quite different
people than who they once were.
Frank asks her diffidently at one point whether she had ever been
tempted to stray during the war-assuring her that he would understand
if she had. Claire-and the reader-think that his reason for doing this
may well be that he had strayed, and would feel better about
confessing his own transgression if she had suffered similar temptations.
Well, maybe he did, and maybe he didn't. It's actually not an abnormal
question to ask a mate you haven't seen in six years, and one whom you
know has been working closely with hundreds of wounded (and thus
possibly emotionally appealing) men, in conditions that you know are
stressful, dangerous, and highly conducive to passionate, if
short-lived, physical attractions.
He's trying to ask it tactfully, but-they're strangers. She takes
offense, and he hastily drops the question. He doesn't bring it up
again, in the time they're together-which is fairly short. So you have
to draw your own conclusion there:
1) he hasn't been having affairs himself, but can't help a certain
male feeling of curiosity/jealousy about what Claire might have been
doing,
2) perhaps he had a brief fling, which he regrets, and wants to
confess this to Claire, so their marriage can resume without his
feeling constant guilt, or
3) he's been screwing every woman who crossed his path, but would like
to find out that Claire's had her own affairs, so he can throw it back
at her in case she ever finds out.
OK. There is NO evidence favoring any one of these three alternatives.
None. Any one of them is as likely as another. The reader's
conclusions depend on the reader-and each reader brings his or her own
experiences and background to the act of reading.
Now, Claire disappears. No warning, no trace, no nothing. What do you
reckon happened, when she didn't come back? A police search, no
leads-and probably deep suspicion of the husband, who is the Most
Likely Suspect. So Frank's left panicked, then grief-stricken, while
probably being interrogated and threatened about his wife's
disappearance. But this must obviously have all died down in the next
three years, and Frank begins to rebuild his life.
Does the rebuilding involve any kind of relationship with women, or a
woman? Quite possibly; he's a handsome, personable man, with friends
who would think it their duty to introduce him to women.
Claire comes back. Filthy, malnourished, and hysterical, if not
outright demented. And, of course, pregnant. She tells him an
unbelievable story, presumably the product of a disordered mind, the
result of whatever horrible abduction/captivity/rape has resulted in
her present condition. She tells him to leave her.
Does he leave her? No. Does he produce another woman and explain that
actually, dear, while you were gone, Mary and I. No. He replies
shortly that no one but a cad would leave a woman in her condition.
So, OK. HE doesn't think he's a cad. Why on earth should anybody else?
He does stay with Claire, not only while she's recovering, but
thereafter. There's no hint that he's pursuing a love affair started
while she was gone; in fact, he takes her to Boston, so that no hint
of scandal will attend Bree's birth. If he did have some relationship
while she was gone, plainly he's broken it off (and perhaps the
removal to Boston is to make such a break more definite-we don't know,
because we don't know what he was doing during those three years).
All right. From this point on, Claire's view of Frank is definitely
suspect, because her own state of mind makes it impossible for her to
connect fully with him, save for brief interludes of tenderness, when
they're able to reach one another physically (like the night he makes
love to her on the floor of the nursery). Yes, their relationship is
strained-we know that, because we see it. But the relationship of any
new parents is strained (believe me on this <g>), even if the two
parties aren't on difficult terms to start with. And these two parties
definitely are.
Claire thinks he may be having affairs, but she doesn't ever have
evidence of it. Either the guy is very dang good at hiding this stuff
(and unfaithful spouses almost always give themselves away)-or he
isn't having affairs. He may well be seeking companionship, sympathy,
and ego-reinforcement from other women (he ain't gettin' a lot of
those things at home-but note that he isn't leaving, either), but it's
at least possible that he isn't crossing the line into actual physical
infidelity. Note that Claire says that now and then she forces her
sexual attentions on him, trying to prove that he's been with someone
else (and thus unable to respond to her)-but that every time, he does
respond to her, even if with mutual rage.
On the other hand, Frank knows beyond the shadow of a doubt that
Claire's been unfaithful to him. At first, he most likely thinks she's
been raped, but she goes on insisting on her absurd story. If it's
true in any way-then she did it on purpose. This can't do his feelings
any good. But he stays, because only a cad would abandon a pregnant
woman with no resources-and he isn't a cad.
See, all these red-eyed readers are identifying with Claire (for the
excellent reason that she's telling the story)-but they'd do better to
watch Frank. He clearly has a code of honor, and by God, he's sticking
to it, dearly though it may cost him. Would a man with this kind of
code then proceed to have promiscuous affairs?
Maybe-but maybe not. His own image of himself as an honorable man is
probably as valuable to him as Claire is, at this point; if he won't
abandon her, he won't abandon that image, either.
Now, their relationship is definitely a difficult one. On Claire's
side, there's grief, resentment (over being parted from Jamie), the
fractured feelings of giving birth to Jamie's baby, and the struggle
to build a career (which is probably not something Frank ever expected
her to want to do, and wasn't prepared for). You note that she
apologizes to Frank only once, in their initial conversation after her
return-at which point, she's completely hysterical. She makes it clear
that she loves Jamie more than him, even if Jamie is dead-this is Not
All That Good for a marriage.
Mind, divorce was simply Not Done at this time, in either the UK or
the US. A divorced woman was stigmatized, as was the child of divorced
Frank-honorable man that he sees himself as-isn't going to expose
either Claire or Bree to that stigma. Besides, he's in love with
Brianna, and doesn't want to be parted from her. To not only divorce
Claire but also get custody of Bree would mean a huge, ugly, public
court-case, in which he would have to accuse Claire of moral
depravity, alcoholism, and anything else he could think of-and prove
it. No-fault divorce hadn't been invented; a divorce had to be
approved by a judge, on the basis of strong evidence. (For the same
reasons, Claire wouldn't seek to divorce Frank.
A) She wouldn't deprive Brianna of a father who plainly loved her,
B) she wouldn't expose Bree to the trauma of an ugly divorce case, and
C) she'd have to prove that Frank was guilty of various horrible things.
And we do see evidence that he still does love Claire. He's angry at
her, confused by what's happened, and obviously having a hard time
with everything-but he does love her. Enough to help her with her
medical career, even though he doesn't like her having it and
objective enough to admire the sense of destiny that drives her to it,
even though he's somewhat jealous that he doesn't possess that drive
Frank a pathetic slimeball? Good grief. He's the major tragic figure
of the books, unsung though he is. He is-on the evidence to hand-a
stand-up guy, who's taken a horrible set of circumstances (which he
didn't cause and had nothing to do with) and done the best he could to
build a family, do right by his daughter, and treasure what strands of
occasional tenderness form between himself and his guilt-ridden,
emotionally-distant wife."
That help?
On Nov. 14, 2005:
Diana wrote:
"P.S. Forgot to note in the above that Frank, Claire, and Brianna are
all Catholics. Catholics _really_ didn't get divorced in the
'50's–they still don't do it all that often, since it means
excommunication.
I don't at all understand why the anti-Frank contingent thinks Claire
should have left the marriage, though. Why? Frank wasn't beating
her, or mentally torturing her, or otherwise behaving badly (with, of
course, the _possible_ exception that he was being unfaithful. And
that, we don't know). The only overwhelming reason she might have had
would be to go back to Jamie–which is something that Frank obviously
knows, which is why he doesn't tell her when he finds evidence that
Jamie didn't die at Culloden. (And while I'm sure that the anti-Frank
people view this as more evidence that he's a Bad Person, consider
what he himself says in his letter to the Reverend. True, he _didn't_
want to lose her (i.e., he loved her), but he also didn't want to
cause her and/or Brianna additional grief and suffering by giving her
an impossible choice. She was by that time reconciled to her live in
the present, doing well as a doctor, and if their marriage wasn't
great, it mostly wasn't bad.
If she knew Jamie was alive, though…either she'd choose to try to
return to him, leaving her young daughter (more horrible guilt), or
she'd stay for Bree's sake, but be constantly torn by yearning for
Jamie. So Frank didn't tell her. He clearly had mixed motives for
that, but they weren't necessarily evil ones, at all."
**-**
Now...I am NOT saying Diana gives Frank Haters a spanking here....I am just saying...ummm...never mind. *grin* And yes, I know DG doesn't exactly exonerate him...but she sure in the Hell makes it clear that Frank shouldn't be vilified! THAT much is clear.
Here...to make the anti-Frank squad feel better, I will buy them ice-cream, ok? That always helps...
...ummm...again...never mind.
Posted by DeniseSF at 4:45 PM 9 comments: Links to this post
Labels: Claire Randall Fraser, compu-serve, Diana Gabaldon, Frank Randall, ice cream comfort, Outlander
DIANA GABALDON'S 2005 LETTER 'IN DEFENSE OF FRANK ...


text:
Community Cancer Center Ownership Change
Cancer Center news release FINAL 8-19-20
Shelli Dankoff
Media Relations Supervisor
shelli.j.dankoff@osfhealthcare.org
Bloomington, Ill.,
Ownership of the Community Cancer Center in Normal will change, effective September 1, 2020 when Carle Health will lead the Community Cancer Center in accordance with its newly established ownership of Carle BroMenn Medical Center in Normal.
Advocate Aurora Health and OSF HealthCare had jointly owned the stand-alone Community Cancer Center, which opened in 1999 after leaders from OSF St. Joseph Medical Center in Bloomington and BroMenn Medical Center in Normal came together to provide cancer care to the Bloomington-Normal community. In January 2020, Advocate Aurora announced it was selling BroMenn Medical Center to Urbana-based Carle health system. That action activated a review of the joint venture agreement for the Community Cancer Center.
"OSF HealthCare greatly appreciates the more than 20-year partnership with BroMenn in providing cancer services in Bloomington-Normal. We are proud of the cancer care that the Community Cancer Center has provided," said Lynn Fulton, president of OSF St. Joseph Medical Center. "OSF HealthCare spent a great deal of time, consideration and discernment in the decision to move away from ownership of the center, but ultimately decided the timing was right to make the change. We welcome Carle to the community and will continue to work collaboratively with their team."
"We have appreciated our partnership with OSF over the years and we are so pleased to carry forward the legacy of the Community Cancer Center that was established many years ago to ensure patients receive the care they needed locally. We look forward to continuing to advance cancer care in central Illinois in the future," said Colleen Kannaday, president, Carle BroMenn Medical Center.
OSF HealthCare leaders plan to coordinate with Carle and health care providers at the Community Cancer Center to ensure that patients continue to receive high-quality care during the ownership transition, with no disruption.
About OSF HealthCare:
OSF HealthCare is an integrated health system owned and operated by The Sisters of the Third Order of St. Francis, headquartered in Peoria, Illinois. OSF HealthCare employs more than 23,600 Mission Partners (employees) in 147 locations, including 14 hospitals – 10 acute care, four critical access – and two colleges of nursing. Its physician network employs more than 1,500 primary care, specialist physicians, and advanced practice providers.
About Carle Health:
Based in Urbana, IL, The Carle Foundation is a vertically integrated system with more than 9,500 employees in its five hospitals, multi-specialty physician groups, health plan and associated healthcare businesses including the Carle Illinois College of Medicine, the world's first engineering-based medical school. Carle is proud to be named a Great Place to Work®. Carle Foundation Hospital and Carle BroMenn Medical Center hold Magnet® designation, the nation's highest honor for nursing care and Carle Foundation Hospital (CFH) ranks as one of America's 50 Best HospitalsTM by Healthgrades®.


Rosie Sherry interviews Richard Bradshaw to talk about automation in testing. Richard is an independent tester, very active in the testing community, a conference junky and more well known as the Friendly Tester.
Where on should testers start when thinking about automation in testing?
What are the different types of tools testers could be consider?
How should a tester decide what to test? And where should they start?


text:
Minnesota Vikings Cheerleader auditions to heat up the Rotunda at Mall of America®
Tara Niebeling
Tara.Niebeling@moa.net
WHAT: The excitement usually reserved for the sidelines of Minnesota Vikings games will fill the Rotunda at Mall of America® for the MN Vikings Cheerleader auditions on Tuesday, April 28.
Dozens of enthusiastic candidates will dance and cheer their way though a crucial round of auditions, competing for a spot on the 2015 2016 Minnesota Vikings Cheerleading Squad.
For more information on the Vikings Cheerleading auditions, click here.
VISUALS: Dozens of candidates dancing on stage in the Rotunda
Cheerleaders interacting with fans of all ages
6:30 8:30 p.m.
WHERE: Mall of America Rotunda
About Mall of America®
Mall of America is the nations largest retail and entertainment complex. At 4.87 million square feet, the Mall is home to more than 520 world-class shops; Nickelodeon Universe, the nations largest indoor family theme park; EMS Entertainment Exhibit Center; SEA LIFE Minnesota Aquarium, a 1.2 million gallon walk-through aquarium; Hard Rock Café; Moose Mountain Adventure Golf; Theatres at Mall of America, a 14-screen movie theater with digital projection including 4K, digital sound and 3D capabilities; Radisson Blu Mall of America, a 500-room hotel connected by skyway to Mall of America The Mall opened in August of 1992 and is located in Bloomington, Minn., just minutes from downtown Minneapolis and St. Paul. The Mall is currently undergoing an expansion project on all three levels on the north side. The expansion will include a 342-room JW Marriott hotel, office tower, high-end retailers, new dining options, a tourist welcome center and large event space. Follow Mall of America on Facebook and Twitter.


text:
static char THIS_FILE[] = __FILE__;
#endif

/////////////////////////////////////////////////////////////////////////////
// CResultsParticipantForSeriesSet

IMPLEMENT_DYNAMIC(CResultsParticipantForSeriesSet, CRecordsetEx)

CResultsParticipantForSeriesSet::CResultsParticipantForSeriesSet(CDatabase* pdb)
	: CRecordsetEx(pdb)
{
	//{{AFX_FIELD_INIT(CResultsParticipantForSeriesSet)
	m_SeriesID = 0;
	m_EventID = 0;
	m_PersonID = 0;
//	m_DivisionActual = 0;
//	m_AgeGroup = 0;
//	m_GroupIDActual = 0;
//	m_GroupStartActual = 0.0f;
	m_NewGroupID = 0;
	m_NewGroupMessage = _T("");
//	m_GrossPerformanceHOUR = 0;
//	m_GrossPerformanceMIN = 0;
//	m_GrossPerformanceSEC = 0.0f;
//	m_NetPerformanceHOUR = 0;
//	m_NetPerformanceMIN = 0;
//	m_NetPerformanceSEC = 0.0f;
//	m_Place = 0;
//	m_OverallPlace = 0;
//	m_Percentile = 0;
//	m_Points = 0;
//	m_Eligible = _T("");
//	m_EventRate = 0.0f;
//	m_GroupRateActual = 0.0f;
//	m_ChestNumber = _T("");
//	m_WorldStandard = 0.0f;
	m_GroupIDSupposedTo = 0;
//	m_DivisionSupposedTo = 0;
//	m_OrgID = 0;

//	m_PFS_SeriesID = 0;
//	m_PFS_PersonID = 0;
	m_PFS_GroupIDSupposedTo = 0;
//	m_PFS_DivisionSupposedTo = 0;
//	m_PFS_ConsistencyAgeGroup = 0;
//	m_PFS_ConsistencyEventsCurrent = 0;
//	m_PFS_ConsistencyEventsOlder = 0;
//	m_PFS_ConsistencyEventsRate = 0.0f;
//	m_PFS_EventsForSeason = 0;
//	m_PFS_GrossPoints = 0;
//	m_PFS_LowPoints = 0;
//	m_PFS_NetPoints = 0;
//	m_PFS_EligibilityForEvent = _T("");
//	m_PFS_OrgID = 0;
//	m_PFS_EventsForSeries = 0;

//	m_nFields = 42;
	m_nFields = 7;
	//}}AFX_FIELD_INIT
	m_nDefaultType = dynaset;
}

CString CResultsParticipantForSeriesSet::GetDefaultConnect()
{
	return _T("");
}

CString CResultsParticipantForSeriesSet::GetDefaultSQL()
{
	return _T("[Results],[ParticipantForSeries]");
}

void CResultsParticipantForSeriesSet::DoFieldExchange(CFieldExchange* pFX)
{
	//{{AFX_FIELD_MAP(CResultsParticipantForSeriesSet)
	pFX->SetFieldType(CFieldExchange::outputColumn);
	RFX_Long(pFX, _T("[Results].[SeriesID]"), m_SeriesID);
	RFX_Long(pFX, _T("[Results].[EventID]"), m_EventID);
	RFX_Long(pFX, _T("[Results].[PersonID]"), m_PersonID);
//	RFX_Long(pFX, _T("[Results].[DivisionActual]"), m_DivisionActual);
//	RFX_Long(pFX, _T("[Results].[AgeGroup]"), m_AgeGroup);
//	RFX_Long(pFX, _T("[Results].[GroupIDActual]"), m_GroupIDActual);
//	RFX_Double(pFX, _T("[Results].[GroupStartActual]"), m_GroupStartActual);
	RFX_Long(pFX, _T("[Results].[NewGroupID]"), m_NewGroupID);
	RFX_Text(pFX, _T("[Results].[NewGroupMessage]"), m_NewGroupMessage);
//	RFX_Long(pFX, _T("[Results].[GrossPerformanceHOUR]"), m_GrossPerformanceHOUR);
//	RFX_Long(pFX, _T("[Results].[GrossPerformanceMIN]"), m_GrossPerformanceMIN);
//	RFX_Double(pFX, _T("[Results].[GrossPerformanceSEC]"), m_GrossPerformanceSEC);
//	RFX_Long(pFX, _T("[Results].[NetPerformanceHOUR]"), m_NetPerformanceHOUR);
//	RFX_Long(pFX, _T("[Results].[NetPerformanceMIN]"), m_NetPerformanceMIN);
//	RFX_Double(pFX, _T("[Results].[NetPerformanceSEC]"), m_NetPerformanceSEC);
//	RFX_Long(pFX, _T("[Results].[Place]"), m_Place);
//	RFX_Long(pFX, _T("[Results].[OverallPlace]"), m_OverallPlace);
//	RFX_Long(pFX, _T("[Results].[Percentile]"), m_Percentile);
//	RFX_Long(pFX, _T("[Results].[Points]"), m_Points);
//	RFX_Text(pFX, _T("[Results].[Eligible]"), m_Eligible);
//	RFX_Double(pFX, _T("[Results].[EventRate]"), m_EventRate);
//	RFX_Double(pFX, _T("[Results].[GroupRateActual]"), m_GroupRateActual);
//	RFX_Text(pFX, _T("[Results].[ChestNumber]"), m_ChestNumber);
//	RFX_Double(pFX, _T("[Results].[WorldStandard]"), m_WorldStandard);
	RFX_Long(pFX, _T("[Results].[GroupIDSupposedTo]"), m_GroupIDSupposedTo);
//	RFX_Long(pFX, _T("[Results].[DivisionSupposedTo]"), m_DivisionSupposedTo);
//	RFX_Long(pFX, _T("[Results].[OrgID]"), m_OrgID);

//	RFX_Long(pFX, _T("[ParticipantForSeries].[SeriesID]"), m_PFS_SeriesID);
//	RFX_Long(pFX, _T("[ParticipantForSeries].[PersonID]"), m_PFS_PersonID);
	RFX_Long(pFX, _T("[ParticipantForSeries].[GroupIDSupposedTo]"), m_PFS_GroupIDSupposedTo);
//	RFX_Long(pFX, _T("[ParticipantForSeries].[DivisionSupposedTo]"), m_PFS_DivisionSupposedTo);
//	RFX_Long(pFX, _T("[ParticipantForSeries].[ConsistencyAgeGroup]"), m_PFS_ConsistencyAgeGroup);
//	RFX_Long(pFX, _T("[ParticipantForSeries].[ConsistencyEventsCurrent]"), m_PFS_ConsistencyEventsCurrent);
//	RFX_Long(pFX, _T("[ParticipantForSeries].[ConsistencyEventsOlder]"), m_PFS_ConsistencyEventsOlder);
//	RFX_Double(pFX, _T("[ParticipantForSeries].[ConsistencyEventsRate]"), m_PFS_ConsistencyEventsRate);
//	RFX_Long(pFX, _T("[ParticipantForSeries].[EventsForSeason]"), m_PFS_EventsForSeason);
//	RFX_Long(pFX, _T("[ParticipantForSeries].[GrossPoints]"), m_PFS_GrossPoints);
//	RFX_Long(pFX, _T("[ParticipantForSeries].[LowPoints]"), m_PFS_LowPoints);
//	RFX_Long(pFX, _T("[ParticipantForSeries].[NetPoints]"), m_PFS_NetPoints);
//	RFX_Text(pFX, _T("[ParticipantForSeries].[EligibilityForEvent]"), m_PFS_EligibilityForEvent);
//	RFX_Long(pFX, _T("[ParticipantForSeries].[OrgID]"), m_PFS_OrgID);
//	RFX_Long(pFX, _T("[ParticipantForSeries].[EventsForSeries]"), m_PFS_EventsForSeries);
	//}}AFX_FIELD_MAP
}

/////////////////////////////////////////////////////////////////////////////
// CResultsParticipantForSeriesSet diagnostics

#ifdef _DEBUG
void CResultsParticipantForSeriesSet::AssertValid() const
{
	CRecordsetEx::AssertValid();
}

void CResultsParticipantForSeriesSet::Dump(CDumpContext& dc) const
{
	CRecordsetEx::Dump(dc);
}
#endif //_DEBUG