2016-05-31 Assigned to INTEGRATED MEMORY LOGIC, INC. reassignment INTEGRATED MEMORY LOGIC, INC. DOCUMENT ID: 503849762 - CORRECTION BY DECLARATION: TO CORRECT ASSIGNEE NAME IN PREVIOUSLY RECORDED (REEL/FRAME 11810/583). ASSIGNOR HEREBY CONFIRMS THE ASSIGNMENT OF ASSIGNOR INTEREST. Assignors: INTEGRATED MEMORY LOGIC, INC.
A flash memory controller with a volatile program and data memory is disclosed. The controller loads microcode and data into the program and data memory from a flash memory array upon powerup of the controller. If an error occurs during the download or the microcode does not exist in the flash memory array, then the controller loads microcode and data into the program and data memory from the host computer. In some embodiments of the invention, an initial code is downloaded to the controller so that an evaluation of the configuration of the controller and the flash memory can be communicated to a host computer. The host computer then downloads for storage into the flash memory a tailored microcode and restarts the controller so that the tailored microcode is loaded from the flash memory and executed. In some embodiments, a protection circuit is provided to protect the microcode from accidentally being erased from the flash memory. Additionally, in some embodiments, an interleaved data structure is utilized to minimize wait times during read and write operations to the flash memory.
CD-ROM Appendix A, which is a part of the present disclosure, is a CD-ROM appendix consisting of 57 text files. CD-ROM Appendix A includes Verilog code (in a directory labeled VERILOG) for producing a controller chip as described below, initial code (in a directory labeled INITIAL) for controlling a microcontroller, and host computer code (in a directory labeled HDIAG) to create downloadable microcode and data as described below. The total number of compact disks including duplicates is two. Appendix B, which is also part of the present specification, contains a list of the files contained on the compact disk. The attached CD-ROM Appendix A is formatted for an IBM-PC operating a Windows operating system.
These and other embodiments are further discussed below.
This invention relates to controllers and interfaces for flash memory controllers and, more particularly, to a flash memory controller with volatile program and data memory.
Flash memory is increasingly being utilized in small electronic devices as non-volatile data storage medium. Flash memory is also increasingly utilized as a replacement for conventional magnetic memory such as hard disks, floppy disks, and other non-volatile data storage media. Flash memory is a non-volatile semiconductor memory in which power consumption is small and data can be electronically rewritten. Further, flash memory stores data in the absence of power, is shock proof, and is light-weight and compact, thereby lending itself to many uses in the data storage area.
Flash memory stores data as charge on floating gates. Presence of charge on the floating gate represents one logic level while the absence of charge on the floating gate represents the opposite logic level. The state of a bit in flash memory, however, can not be simply changed. The bit must be erased and then rewritten. Because of the necessity of erasing bits in flash memory before a write to the flash memory can occur, data transfers to and from flash memory are handled differently than those in conventional magnetic memory which do not require an erase function before a new write can occur.
Flash memory utilized for data storage is usually arranged in blocks. Each block includes a plurality of addressable sectors, with each sector being within a physical block address PBA. In a conventional system, if the data or program stored within an address in a block is to be changed, the data in that source address is first read out of the flash memory and stored in a buffer latch. An erased block in the same flash device is identified as a destination block. Data, including the data to be retained from the source block, is then written into the destination block and the source block can be erased. In some systems, unchanged sectors can be transferred directly to the destination block without being buffered.
Conventionally, a computer system employs a dedicated controller for a flash memory drive. The host computer gives the controller read and write commands and the controller directly controls the reading from and writing to the flash memory itself. Furthermore, the controller performs memory management such as block erase, block reads, and block writes to the flash memory.
The controller, then, keeps track of blocks in use, blocks that have been erased, or blocks that have been damaged (or worn out). Therefore, the controller usually includes an address conversion table stored in memory separately from the flash memory in order to track data within the flash memory. Microcode executed by a microcontroller of the flash controller is typically stored in a non-volatile, non-erasable memory. The program memory, then, can not be easily modified. Furthermore, microcode appropriate for all configurations of the controller card needs to be stored on the controller card, leading to the need for a large amount of expensive storage capacity on the controller card.
Therefore, there is a need for memory controllers where the firmware for controlling the transfer of data between a host computer and a flash memory bank can be loaded into the memory controller from the host computer, increasing the versatility and decreasing the memory costs for the controller.
In accordance with the present invention, a Flash Disk controller that can download microcode is disclosed. The Flash Disk Controller interfaces between a host computer and a flash memory bank. The Flash Disk controller according to the present invention includes volatile memory banks for storing microcode and data where microcode can be downloaded from a host computer.
On controller startup, the controller proceeds to shadow code and attempts to load the microcode from the flash memory bank itself. If the microcode is not present in the memory bank or there is an error in downloading the microcode from the flash memory (i.e. shadowing), then the flash memory controller expects download of microcode from the host computer. In some embodiments, the host computer can independently initiate download of microcode from the host computer in order to replace microcode already stored in the controller.
In some embodiments, the host computer can download an initial code into the program memory. In some embodiments, during download of the initial code the microprocessor of the controller is suspended. When the initial code is executed by the microprocessor of the controller (i.e., by releasing the microprocessor), diagnostics are performed on the controller and the flash memory coupled to the controller to determine, for example, the flash memory configurations, defects in the flash memory, and other information. In some embodiments, the initial code executed by the microprocessor operates in response to commands from the host computer. The information obtained in the diagnostics routine is uploaded to the host computer so that the host computer can construct microcode tailored for that particular controller with that flash memory configuration. The newly constructed microcode is downloaded through the controller and stored in the flash memory. During the download process, the new microcode can be treated as regular data to be written into flash memory. In this fashion, the new microcode tailored by the host computer for the particular configuration can be loaded directly into the flash memory and the controller card reset to execute the new microcode. The controller card therefore requires much less memory space to hold the tailored microcode than would be needed if the microcode for all configurations were required to be stored.
In some embodiments, on startup, the controller reads the microcode from the flash memory and loads it into volatile memory. The controller, then, includes a microprocessor that executes the microcode from the volatile memory. In some embodiments, an error check can be performed on the microcode as it is loaded from flash memory into volatile memory. If an error is detected, the controller can switch to download mode in order to load new microcode into the volatile memory from the host computer. In some embodiments of the controller, the microprocessor is held in a hold mode until microcode is available in the volatile memory. In some embodiments, when the controller switches to download mode all commands from the host processor but the download command are either ignored or responded to with an error code. When the download is completed, the microprocessor is released to execute the code downloaded into volatile memory.
In some embodiments, the area of flash memory utilized for storage of the microcode is protected against accidental erasure. The protection can be performed by comparing a password stored in a password register with a stored password before the area of flash memory is written. If the passwords do not match, the controller can issue an error message. Therefore, in order to download the new microcode into the appropriate area of the flash, the appropriate password is loaded into the password register. Then the new microcode can be loaded into the appropriate area of the flash memory.
In some embodiments, the controller executes an interleaved storage system. The flash memory includes several flash memory chips which, in some embodiments, can be separated into multiple banks of flash memory chips. In some embodiments, data is written alternatively into sectors of different chips. In that fashion, during a read operation during the time that a first flash memory chip is loading data from a requested sector into a buffer of the first flash memory chip, the controller is asking a second flash memory chip for the sector corresponding to the next data in the requested data. Therefore, the read time can be shortened.
In some embodiments, the controller is programmed once during its operational lifetime. It can, for example, be programmed at the factory before shipping. In other embodiments, the controller can be reprogrammed multiple times during its operational lifetime.
The major advantages of downloadable microcode include the requirement of less memory in the controller and the versatility of downloading updated versions of the software. The lowered memory requirements lead to lowered cost of the controller and the ability to reload microcode leads to higher versatility of the controller. These and other embodiments are further discussed below with respect to the following figures.
FIG. 1 shows a block diagram of an embodiment of a flash memory controller according to the present invention.
FIG. 2a shows a block diagram of the start-up algorithm for the flash memory controller according to the present invention.
FIG. 2b shows a block diagram of a download algorithm of the start-up algorithm of FIG. 2a.
FIG. 3 shows a block diagram illustrating a protection system according to aspects of the present invention for insuring that the portion of the flash memory storing the microcode is not accidentally erased.
FIGS. 4a, 4 b, and 4 c show a block diagram illustrating interleaved reading and writing to flash memory according to the present invention.
In the figures, elements having the same identifier have the same function.
FIG. 1 shows a block diagram of an embodiment of a flash memory controller 100 according to the present invention. Controller 100 includes a host interface 101, a volatile memory 108, a microprocessor 104, an error correction block 109, a flash interface 10, and a card initialization block 150. Flash interface 110 is coupled to flash memory bank 140. Host interface 101 is coupled to host computer 130.
In general, flash memory bank 140 is divided into blocks 141. Whole ones of blocks 141 are erased at a time. After erasing a block 141, individual sections in the block can then be written. Since each section of a block 141 are linked so that whole blocks are erased at once, out of date information can not be erased unless all information in block 141 is erased. Furthermore, data can not be rewritten into each of blocks 141 until the entire block has been erased. As a result, valid data may be moved into different ones of blocks 141 of flash memory 140 periodically so that invalid data can be overwritten. Therefore, controller 100 controls the reading of data from flash memory 140 and the erasure and rewriting of data into blocks 141 of flash memory 140.
FIG. 4a shows an example of flash memory chips 410 and 420. Chip 410 includes block 411 with sectors 412-0 through 412-N. Chip 420 includes block 421 having sectors 422-0 through 422-M. If, for example, sector 412-1 is to be rewritten, and block 421 has been erased, then sectors 412-0 and 412-2 through 412-N can be transferred to block 421. A new sector 412-1 can then be written into block 421 and block 411 can be erased.
In most embodiments, at least a portion of the flash memory management system of controller 100 is encoded in microcode that is executed by microcontroller 104. Some of the flash memory management system of controller 100 is embedded in the firmware operation of, for example, flash interface 110 and error correction block 109.
Data read from flash memory 140 through interface 110 is received by error correction block 109. Error correction block 109 checks errors on the fly as data is received from flash memory 140 and attempts to correct error problems. The functions of error correction block 109 are well known in the art. In some error correction schemes, for example, 6 bytes of redundancy can be appended to a 512 byte block, which can detect up to 31 bits of error and, once the errors are found, can proceed with error correction routines. Data can then be transferred from error correction block 109 to buffer region 107 of memory block 108.
Memory block 108 also includes program memory 105, which holds microcode that can be executed by microcontroller 104 to control the transfer between host computer 130 and flash memory 140, and data memory 106, which includes, for example, reference tables for monitoring bad data blocks in flash memory 140. Since flash memory tends to decay with time, in most embodiments flash memory 140 is monitored by controller 100 and the reference tables of data memory 106 are often updated. In some embodiments, memory 105 can be 8 KB of SRAM, memory 106 can be 2 KB of SRAM for storing defect mapping tables, and memory 107 can be 4 KB of data as a data buffer. Other examples can include any combination of sizes for memory 105, 106 and 107. The microcode and the defect mapping table can be loaded into program memory 105 and defect memory 106, respectively, from flash memory 140 itself or, if it is not present in flash memory 140 or corrupted in flash memory 140, may be downloaded from host computer 130.
Interface 101 interfaces between flash controller 100 and host computer 130. Interface 101 receives control signals from host computer, transmits status and error codes to host computer 130, and transfers data between controller 100 and host computer 130. Attribute memory 102 stores registers for controlling the operation of controller 100. Attribute memory 102, for example, includes information regarding the interface types and serial numbers for the controller. The card information structure (CIS) can include, for example, the following registers: CISTPL_DEVICE, which is a function specific memory address range; CISTPL_DEVICE_OC, which is another function specific memory address range; CISTPL_JEDEC_C, which is PC Card ATA register; CISTPL_MANFID, which is the card manufacture code; CISTPL_VERS_1, which is the manufacturer version number for controller 100; CISTPL_FUNCID, which identifies the function of controller 100 (for example fixed disk); CISTPL_FUNCE, which identifies interface 101 (for example PC Card ATA, device types, serial numbers, low power modes); CISTPL_CONFIG, identifying the locations of the function configuration registers; CISTPL_CFTABLE_ENTRY, which includes information regarding default systems, memory mapping, and power management requirements; and CISTPL_NOLINK registers. The information in these registers can be downloaded into flash memory 140 and shadowed in the SRAM of attribute memory 102. Other registers are permanently fixed and stored in non-volatile memory of attribute memory 102.
ICC, the Interface Configuration Control Register, which includes a MDRV (Master Drive Selection) flag, a SShadow (Slave Shadow Feature Enable) and a DisShadR (Disable Shadow Auto Response) flags.
FIM, the Flash Interrupt Mask Register, which is used to control Flash Memory interrupts.
HGC, the Host General Control Register, including an SAbort (Start to Abort Host Related Operation), SFRST (Start Firmware Reset), and SARAC (Stop Auto-Read After Current Transfer) flags.
FGCR, the Flash General Control Register, including AFOE (Automation Flash Operation Disabled), PIKE (Program 1K Command Enabled), PIE (Page Interleave Enable), EDCE (EDC Engine Enabled), and ECCE (ECC Engine Enable).
GD#, which is several General Data Register.
Power manager 103 supplies the power requirements, including voltages and clock signals, required for operation of controller 100. As discussed above, aspects of power manager 103 are controlled by various control registers. The voltages and clock signals, in some embodiments, can be set by values stored in CIS registers of attribute memory 102 or system control registers 115.
In some embodiments, controller 100 is compatible with PCMCIA Specification release 6.1, however other embodiments may be compatible with other specifications. Some embodiments, as shown in FIG. 1, can support PC Card ATA interface protocols, may include an automatic power saving standby and power down mode, can be produced with low-power CMOS technology with a 3.3V power supply, and can include on-the-fly error detection (EDC) and error correction code (ECC) capability (in error correction 109). Flash memory 140 may include any flash memory system, including 32 Mb, 64 Mb, 128 Mb, 256 Mb, and 512 Mb NAND type flash interface. In some embodiments, controller 100 can be included on a single integrated circuit chip. Embodiments of the invention can include any system clock speed.
In some embodiments, host computer 130 controls embedded Attribute Memory 102 for CIS (card information structure) and Configuration Control registers; controls dual data registers; controls error and features register supporting 8, 16, or other size bit data transfers; supports high transfers rates (for example 16.6 MB rates); supports memory mapping, IO mapping and true IDE mode; supports automatic protocol control on block transfers for ATA read or write commands; and supports multiple read and write.
In some embodiments, flash memory 140 can be any number of pieces (for example from 1 to 16) of any size or type of flash memory (for example 32 Mb, 64 Mb, 128 Mb, 256 Mb, 512 Mb or 2 Gb NAND type Flash). In some embodiments, interface 110 can support any total size of flash memory 140 (for example, between 4 MB to 512 MB). In some embodiments, error correction 109 can perform ECC functions to correct 2 random bits for each 512 bytes. Additionally, on-the-fly EDC can detect 4 random bits up to 31 bits in 512 bytes. In some embodiments, interface 110 can perform two-way interleaved read/write capability to reduce Flash access latency and supports program, erase, sector read and status report functions. Further, interface 110 can support flash programming to reduce flash program time.
The microcode operated by microcontroller 104 can include algorithms for defect management to extend the life of flash memory 140 as well as algorithms for accessing flash memory 140 and transferring data between flash memory 140 through buffer memory 107 to host computer 130. Microcontroller 140, in some embodiments, can be an 80C32 microprocessor.
Several functions, including the functions of error correction 109, are controlled in hardware. In accordance with the present invention, hardware in interface 101, error correction 109, and interface 110 control downloading of microcode from host computer 130 and transfer of microcode from flash memory 140 into program memory 105 before microprocessor 104 is started. Further, the hardware functions in microcode shadowing during normal operation mode of controller 100.
In some embodiments, controller 100 operates in one of four modes: Power-on mode, shadowing mode, download mode or normal mode. FIG. 2a shows a power-on mode algorithm 200 according to the present invention. In block 201 of algorithm 200, chip 100 is powered up or reset. In block 202, firmware in chip 100 sets the PC-card busy flags so that no commands from host 130 are executed. In memory mapping mode, a PC card busy signal can be set. In non-memory mapping mode, a PC card busy signal can be set in the ATA Status Register.
In block 203, controller 100 initiates flash memory interface 110 by, in CPB format (chip, block, page addressing), setting an address for initial access into a starting address register. In some embodiments, the CPB address (registers FCNA, EBAL, EBAH, and PNG of flash memory interface 114) is set to [0,0,0] (chip 0, block 0, page 0). Additionally, a flash transfer count register (FTTC of flash memory register 114) can be set to an initial size (for example, 10 h), and a flash buffer pointer register (FBP of flash memory registers 114) can be initialized with an initial value (for example, 40 h). At this point, chip 100 can start buffering data from flash memory 140 into memory 108. In some embodiments, the flash buffer pointer register is set to buffer data into program memory 105. The flash transfer count register is initialized with the size of the microcode program stored in flash memory at the address stored in the CPB address register.
During the loading of data from flash memory 140 into memory 108 at the flash buffer pointer position indicated by the flash buffer pointer register, error checking is performed by error check 109. If any errors are found or are uncorrectable, then shadow mode is terminated and chip 100 switches to download mode. In FIG. 2a, if an error code is detected in block 204, then download block 205 is executed.
In some embodiments, after each page of microcode is transferred from flash memory 140 into memory 108, the flash transfer count register is decremented and the flash buffer pointer register is incremented by one. In some embodiments, once the flash transfer count register reaches a particular value, for example 2, then the flash buffer pointer register can be reset to memory 106 from memory 107 in order to load the data files corresponding to bad memory areas into the data memory portion 106 of memory 108. In some embodiments, the data memory area 104 can be loaded with data stored in attribute memory 102. Attribute memory, including data memory mappings, can be stored in flash memory 140.
In block 204, if no errors have been detected during transfer of microcode and data files into program memory 105 and data memory 106, respectively, then firmware algorithm 200 proceeds to block 206 where card 100 is switched to ready mode. In block 207, microprocessor 104 is released to begin execution of the microcode that has been loaded into program memory 105. After microprocessor 104 has been started to execute the microcode in program memory 105, then algorithm 200 switches to a normal mode of operation.
If, however, algorithm 200 detects an error in downloading the microcode from flash memory 140 or, as in the initial power up of chip 100, flash memory 140 does not contain the expected microcode, then algorithm 200 switches to download mode in block 205. The download mode of block 205 is utilized when the microcode is not in flash memory 140.
FIG. 2b shows an embodiment of download block 205 according to the present invention. In block 210, an initial code is downloaded into program memory 105. Controller 100 sets the PC Card ready and a signal is transmitted to host computer 130 indicating that the microcode is not stored in flash memory 140. For example, in some embodiments, in memory mapping mode, controller 100 will transmit to host computer 130 a signal indicating that no CIS data is available. The firmware in controller 100 then initializes controller 100 by setting an ATA task file register, for example a status register, to a value indicating a download status (for example, a 50 h). After receiving an ATA command from host 130, controller 100 will process the command automatically. If the command is other than a Firmware Download Command, then controller 100 sets the ATA Status Register such that the DRDY flag and the ERR flag are set, indicating an error and drive ready condition to host 130, and generates an interrupt to host 130 if host interrupts are enabled.
If the ATA command is a Firmware Download Command, then controller 100 initializes the Host Transfer Pointer Register (HTPR) of buffer manager registers 113 with the starting address of program memory 105, the Host Total Transfer Count Register (HTLR) of buffer manager registers 113 with the length of the microcode program, and initializes performance of an Auto-Write Operation to transfer data from host 130 to memory 108. After the initial microcode as been downloaded into program memory 105, the Host Transfer Pointer Register (HTPR) of buffer manager registers 113 is reset to the starting address of data area 106, Host Transfer Length Register HTLR is reset to the size of the CIS data, and the CIS data is downloaded from host 130 to data memory 106.
Once the initial microcode is loaded into program memory 105 and the CIS data is loaded into data memory 106, controller 100 releases microcontroller 104 to execute the microcode in block 211. In most embodiments, the initial code transferred into memory 108 determines the configuration of controller 100 and FLASH memory 140 and transmits that data back to host computer 130 in block 212. In block 213, host computer 130 tailors a microcode for the particular configuration (e.g., how much flash memory is in flash memory 140) of controller 100. In this fashion, the microcode for all configurations do not need to be resident in controller 100 or stored in flash memory 140, significantly reducing the on-board memory requirements of controller 100. Furthermore, memory mapping tables, file allocation tables, and CIS data is created by host computer 130.
In block 214, while still operating controller 100 with the initial microcode, the tailored microcode is downloaded into the microcode storage areas of FLASH memory 140 as regular data. Memory mapping tables, file allocation tables, and CIS data can be downloaded into FLASH memory 140 along with the tailored microcode. Once the tailored microcode and data is stored in FLASH memory 140, controller 100 can be reset in block 215. As shown in FIG. 2a, once controller 100 is reset, then algorithm 200 is restarted so that the busy flag for card 100 can be set and firmware shadowing 203 can be executed, thereby loading the tailored code into memory 108.
FIG. 3 shows a protection circuit 300 for protecting the microcode storage locations in FLASH memory 140 from being accidentally cleared and rewritten. When an erase block address is received by flash interface 110, the erase block address is stored in an erase block address register 302. A compare circuit 305 compares the address stored in the erase block address register 302 with a range of addresses stored in address range register 301. The range of addresses stored in address range register 301 corresponds to the range of addresses in FLASH memory 140 where the microcode and data are stored. The output signal from compare 305, which can be denoted TRUE if the erase address is within the range of addresses for storing the microcode and FALSE if the erase address is not within the range of addresses for storing the microcode, is input to NAND gate 307.
A password is stored in password register 303. If the microcode stored in FLASH memory 140 is to be erased in preparation for writing new microcode, then the password is loaded into password register 304. Compare 306 compares the contents of register 303 with that of register 304 and outputs a TRUE signal if those addresses are not equal and a FALSE signal if they are equal. The output signal from compare 306 is input to NAND gate 307. NAND gate 307 outputs a TRUE signal (indicating that it is allowable to erase the indicated block) if the erase address stored in register 302 is outside of the range indicated in register 301 or if the erase address stored in register 302 is within the range indicated in register 301 and the password stored in register 303 matches the password stored in register 304. Otherwise, NAND gate 307 outputs a FALSE signal, indicating an error has occurred and no erase operation should take place.
In normal operation, the password stored in register 304 is not the password stored in register 303 so that an error message is generated if a block containing microcode is attempted to be erased. Additionally, if the microcode stored in FLASH memory 140 is to be replaced, password register 304 can be loaded with the password stored in password 303, the new microcode can be written, and register 304 can be reloaded with anything but the password stored in register 303.
In some embodiments, an interleaved memory write algorithm is utilized. In NAND type FLASH memory, there is a limitation regarding the process time, especially erase time. The FLASH memory performance, especially in write operations, can be markedly increased by interleaving. In a read operation, the flash memory chip is sent the block address and sector address and the flash memory chip loads the flash memory cell data into an internal buffer. FIG. 4a shows a block diagram of two flash memory chips 410 and 420. Flash memory chips 410 and 420 include data blocks 411 and 421, respectively. Data blocks 411 and 421 each denote an arbitrary one of the data blocks in chips 410 and 420, respectively. Data block 411 is segregated into sectors 412-0 through 412-N and data block 421 is segregated into sectors 422-0 through 422-M, where N and M are integers denoting the number of sectors in a block in chip 410 and 420, respectively. Chip 410 includes buffer 413 and chip 420 includes buffer 423. Chip 410 receives read and write commands and data transfers through port 414 on line A. Chip 420 receives read and write commands and data transfers through port 424 on line B.
In general, a read to chip 410, for example, involves providing a read command along with a block address and sector address to port 414 on line A. Chip 410, then, loads the data from the indicated block and sector into buffer 413. Finally, the data is transferred from buffer 413 to controller 100 (FIG. 1). For example, if a read command indicates block 414 and sector 412-1, then the data in sector 412-1 is transferred to buffer 413 for transfer through port 414 to controller 100. In a typical FLASH memory cell, the loading time, i.e. the time required to transfer data from sector 412-1 to buffer 413, is about 10 microseconds. The time required to transfer data from buffer 413 to controller 100 is typically about 30 microseconds.
In a write operation to chip 410, for example to sector 412-1 of block 411, a write command specifying the block address and sector address (in this case the address of sector 412-1 of block 411) is presented to port 414 on line A immediately followed by data to be written into that sector. The data is stored in buffer 413 and may take about 30 microseconds to transfer from controller 100 to buffer 413. Chip 410, then, internally transfers the data from buffer 413 to sector 412-1 of block 411. In the write operation, block 411 must have been previously erased, which can take about 2 milliseconds in a typical FLASH memory chip, before the actual writing of data to sector 412-1 so that sector 412-1 of block 411 is completely blank. The internal write of data from buffer 413 to sector 412-1 can take about 200 microseconds, therefore a wait of about 200 microseconds must be made between transfers of data for subsequent writes.
The access speed of the memory system of FLASH memory 140 can be greatly increased if the data is interleaved between chips. In that case, both in a write or a read operation, while data is being transferred internally to one flash memory chip, a second flash memory chip is communicating with controller 100 and wait times can be minimized. In general, any level of interleave can be obtained. In one example, data can be alternately split between block 411 of chip 410 and block 421 of chip 420. In that case, a first sector H1 is written into sector 412-0 of block 411, a second sector H2 is written into sector 422-0 of block 421, and so forth until all of the data is stored between chips 410 and 420. In an embodiment with a three level interleave, three chips are involved so that first sector H1 is written into a 0th sector of a block in a first chip; second sector H2 is written into a 0th sector of a block in a second chip; third sector H3 is written into a 0th sector of a block in a third chip; fourth sector H4 is written into a 1st sector of the block in the first chip, and so forth in a round-robin fashion until the data is written between the three chips. In general, any number of chips can be utilized.
FIG. 4b shows an example of a read operation in a two-chip interleave system, as shown in FIG. 4a. Chip 410 receives a read command to H1 (including a block address and sector, for example block 411 and sector 412-0). While chip 410 is loading data from sector 412-0 to buffer 413, chip 420 is receiving a read address for the next sector of data H2 (block 421 and sector 422-0). When chip 410 is ready to download data, controller 100 receives data from buffer 413 and chip 410 proceeds to load buffer 413 with data H3 (buffer 411 and sector 412-1). At that time, data H2 is ready to transfer from buffer 423 to controller 100. Once data H2 is transferred, then chip 420 proceeds to transfer the next sector data H4. This process is repeated until all of the desired data is transferred sequentially from chips 410 and 420. Since, in many embodiments, there is only one error correction block 109, a single stream of data is received from FLASH memory 140. In general, parallel streams of data can be utilized. If the first read in a sequence is H4, for example, then a read command is presented to chip 420 first instead of chip 410 as illustrated.
FIG. 4c illustrates a write operation for a sequence of data H1, H2, H3, H4, H5 . . . into FLASH memory 140. Chip 410 is presented with a write command and data H1, which is transferred into buffer 413. While data H1 is written into chip 410, for example at block 411 and sector 412-0 as indicated in the example, chip 420 is presented with a write command and data H2. When chip 410 is once again ready, data H3 is transferred to buffer 413 and chip 410 proceeds to write data H3 into the next sequential sector, in this case block 411 and sector 412-1. When chip 420 is once again ready, data H4 is transferred to buffer 423 and chip 420 proceeds to write data H4 into the next sequential sector, in this case block 421, sector 422-1. In that way, all of the data is written in a round-robin fashion between blocks 411 and 421 of chips 410 and 420, respectively.
Attached CD-ROM Appendix A, which is herein incorporated by reference in its entirety, includes Verilog code (in directory VERILOG) for producing an embodiment of controller 100 on an integrated circuit chip. CD-ROM Appendix A also includes an embodiment of software for operation of host computer 130 for creating microcode for downloading into controller 100 from host 130 (in directory HDIAG) and an embodiment of initial microcode for operating microprocessor 104 during the analysis and download process (in directory INITIAL), as was described above. A directory of text files included in CD-ROM Appendix A is included here as Appendix B, also hereby incorporated by reference in its entirety.
The above embodiments of the invention are exemplary only and are not intended to be limiting. One skilled in the art may recognize several variations of the invention which are intended to be within the scope of this disclosure. As such, the invention is limited only by the following claims.
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wherein tailored microcode and data can be loaded into the flash memory from the host computer if the microcode and data are not correctly loaded into the volatile memory area from the flash memory.
2. The controller of claim 1, wherein new microcode is loaded into the flash memory from the host computer if a portion of the microcode is blank in the flash memory.
3. The controller of claim 1, wherein data is loaded into the volatile memory area through the flash memory interface and wherein data can be loaded into the flash memory from the host computer before the data is loaded into the volatile memory area from the flash memory.
4. The controller of claim 3, wherein data and microcode are both loaded into the flash memory from the flash controller together.
5. The controller of claim 4, wherein new microcode and data are loaded into the flash memory from the host computer if a portion of either the microcode or the data is blank in the flash memory.
6. The controller of claim 3, wherein the data includes card information structure (CIS) data.
7. The controller of claim 3, wherein the data includes a memory mapping table.
8. The controller of claim 7, wherein the memory mapping table includes a mapping of logical addresses to physical addresses that maps out bad blocks in the flash memory.
9. The controller of claim 3, wherein the data includes a file allocation table.
10. The controller of claim 1, further including an error correction circuit for detecting errors in microcode loaded from the flash memory.
11. The controller of claim 10, wherein new microcode is loaded into the flash memory if the error correction circuit detects an error in the microcode loaded from the flash memory.
12. The controller of claim 3, further including an error correction circuit for detecting errors in microcode and data loaded from the flash memory.
13. The controller of claim 12, wherein new microcode and data are loaded into the flash memory if the error correction circuit detects an error in the microcode loaded from the flash memory.
14. The controller of claim 1, further including a protection circuit that prevents accidental erasure of a portion of flash memory that stores the microcode.
15. The controller of claim 14, wherein the protection circuit compares an erase address with a range of addresses where the microcode is stored and outputs an error message if a password loaded into a password register does not match a stored password.
16. The controller of claim 1, further including a memory management system having an interleaved data structure.
17. The controller of claim 16, wherein the interleaved data structure is a two-chip interleave where sectors of data are alternately stored between a first block in a first chip and a second block in a second chip.
18. The controller of claim 16, wherein the interleaved data structure is multi-chip interleave where data is stored in a round-robin fashion between a block in each of a plurality of chips.
if the state is not successful, executing a download algorithm to receive microcode from a host computer interface.
wherein indicating the state includes indicating the state of loading of the data to the volatile memory area.
21. The method of claim 20, wherein the data includes card information structure data.
22. The method of claim 20, wherein the data includes memory mapping data.
23. The method of claim 22, wherein the memory mapping data maps logical addresses to physical addresses such that bad blocks of the flash memory bank are mapped out.
24. The method of claim 20, wherein the data includes file attribute data.
restarting the power up algorithm to load the tailored microcode from the flash memory bank into the volatile memory area.
sending information regarding the flash memory bank and the controller to the host computer interface.
27. The method of claim 25, wherein a host computer coupled to the host computer interface constructs the tailored microcode and data to be transmitted to the host computer interface.
transferring the tailored microcode from volatile memory area into the flash memory bank.
means for receiving tailored microcode and data from a host computer if the microcode and data was not correctly loaded into the volatile memory from the flash memory.
means for transferring information to the host computer.
means for determining if a portion of the microcode or data in the flash memory is blank.
means for transferring the microcode and data as data from the host computer into the flash memory.
means for interleaved reading and writing data into the flash memory.
means of protecting a portion of the flash memory from accidental overwrite, the portion of the flash memory being the portion utilized to store microcode and data utilized by the microcode.
wherein tailored microcode and data can be loaded into the flash memory from the host computer before the microcode is loaded into the volatile memory area from the flash memory.
36. The controller of claim 35, wherein the microcontroller executes an initial microcode received from the host computer to receive the tailored microcode from the host computer.
37. The controller of claim 36, wherein information is provided to the host computer by the controller when the initial microcode is executed.
38. The controller of claim 37, wherein the tailored microcode and data and written into the flash memory by the controller when the initial microcode is executed.


text:
Medwatch: January is National Blood Donor Month
By Haley Wilson
Published: Jan. 12, 2023 at 11:15 AM CST
LAWTON, Okla. (KSWO) - Every two seconds, someone needs blood, that's according to Our Blood Institute.
Once blood is donated, it's then distributed to hospitals like Comanche County Memorial Hospital. Prakriti Adhikari, the Blood Bank Supervisor at CCMH, said once it arrives, they do testing on the blood and crossmatch testing to make sure that it's safe for the patient to receive the transfusion.
"And there are a lot of checks in place that we have in our system and personal checks at the bedside so that the patient can have it safely," she said."
Adhikari said it's important to have the blood at the hospital so it's available when it's needed.
"So we use the blood not just for trauma or surgery," she said, "but we use it for our neonatal population. If they need blood, we give blood to them, and every month we have a baby that's getting a blood transfusion."
Adhikari said while they've always experienced seasonal blood shortages because of weather or the holidays, they've noticed changes over the past few years.
"Due to the pandemic, it is getting harder to recover, and sometimes we have to call around to have those products available for our patients, and sometimes it's ok," Adhikari said. "We are still managing here."
Because of that, she said they had to cut down their supply at the hospital. She encourages people to donate blood if they can because you never know when an emergency might happen.
"We need to make sure that we have enough blood on our shelf to treat our patients immediately because it could be a trauma patient that could need a lot of blood, so we need to have it prepared and given to the patient," she said.
Donating blood is easy, safe and can save up to three lives.
"It's not a scary thing to do," Adhikari said. "Blood donation is an act of kindness that you can show to others in need. We really appreciate whoever goes out there and donates."
If you'd like to donate, you can go to Our Blood Institute in Lawton. If you've never donated before, why not give for the first time this month which is National Blood Donor Month.
FDA issuing a proposal guidance to ease restrictions on blood donations for gay and bisexual men
Medwatch: CCMH holds active shooter training for staff
Hospital staff undergo active shooter simulation
Comanche County Memorial Hospital hosts active shooter training classes

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text:
Jensplaining
Sterilization camp in India kills 11 women – a government funded slaughterhouse
Posted byDr. Jen Gunter	 November 12, 2014 November 13, 2014 16 Comments on Sterilization camp in India kills 11 women – a government funded slaughterhouse
The reports from India read more like the review of a horror movie rather than a detailing of a government funded surgical program – 83 women receiving a surgical sterilization leaving 11 dead and another 50 hospitalized, 20 of whom (as of this posting) are seriously ill. And all of this happened in six hours with one surgeon at a government sponsored sterilization camp.
As an OB/GYN I want to tell you how bad this actually is…
The most common method of tubal ligation is by laparoscopy, which is major surgery. An operating telescope is placed into the belly and a clip is placed across the Fallopian tubes to clamp them shut. Sometimes doctors remove the Fallopian tubes or burn them. The biggest risk from the surgery is inadvertently injuring the bowel (spilling stool leading to potentially catastrophic infection, bleeding, and even death), cutting a blood vessel (resulting in uncontrollable bleeding), and infection (from non bowel injury causes). There is also risk from the anesthesia. Patients are counselled about warning signs of these complications so they can get care sooner rather than later should a problem arise.
With competent surgeons, anesthesiologists, and nurses and clean hospitals the risks of laparoscopic tubal ligation are low. In one study of over 9,000 tubal ligations in the United States there was one serious complication and no deaths. Using a more liberal definition of serious complication the rate rose to 1%. A Swiss study indicates no deaths in a review of more than 27,000 procedures. Overall, the estimate is that 1-2 women will die for every 100,000 laparoscopic tubal ligation with most deaths anesthetic related. Basically, 99% of healthy women should expect to have no major issues beyond a day or two of recovery and for the women who do have major complications most involve getting a larger surgical incision and immediate repair of the damage with no long-term issues.
The other method of tubal ligation is done through the uterus and called a hysteroscopic tubal ligation. This can be done in the office (and takes about 20 minutes start to finish versus 40 minutes for a laparoscopic tubal ligation), saving the risk of the anesthesia. It is also less expensive. The risk of injuring blood vessels and bowel is still there (if the device is inserted incorrectly it can puncture the uterus and potentially cause bleeding/bowel injury/and infection), but studies tell us that the complication rate is likely lower than a laparoscopic tubal ligation.
It is likely the women in India had laparoscopic tubal ligations as the procedures are described in the press as "tubectomies" (impossible to do through the uterus).
That is why 11 deaths and 50 women hospitalized with 20 seriously ill is so appalling. A mortality rate of 13% for a procedure that should have a mortality rate of 0.001-2%.
83 tubal ligations in 6 hours and reportedly one surgeon and one or perhaps two assistants is nothing short of a horror show. It takes an average of 40 minutes to give a women an anesthetic, clean her belly, insert the instruments, clip the tubes, make sure nothing is injured, remove the scope, sew or glue the incisions, reverse the anesthetic, and get her off the operating table. It is possible, if everything is going smoothly and there are no complications, to sometimes have this done in 20-30 minutes. Even if there were 3 surgeons, 83 women in 6 hours is impossible unless of course hands were not cleaned and dirty intruments were just stabbed into bellies. The thought that the women may not have had adequate (or even any) anesthesia makes it even more horrifying. How could they given what has been described?
That the government funded this horror show is terrible. That a doctor was involved with this makes it even worse. Agreeing to such a perversion of health care is an abomination – 83 women simply can not have tubal ligations in 6 hours even with 3 competent surgeons and 3 anesthesiologists in a modern hospital never mind in a field. Understanding that doesn't require a medical degree, just common sense and compassion. Money was offered to the women increasing an element of coercion. How many were forced by their families to go?
Government quotas for sterilization don't empower women to make better decisions for themsleves and their families they only treat women like livestock. Or worse.
***November 13, 2014 update***
The BBC is reporting that the surgeon, Dr. RK Gupta, has been arrested. Sadly, the death toll has climbed to 15 women. 14 women died at the first camp (mentioned above) and 1 from another sterilization "camp" that was held two days later. Apparently 130 women were operated on over two day by just Dr. Gupta and an assistant.
Posted byDr. Jen Gunter November 12, 2014 November 13, 2014 Posted inContraception, Patient safety, war on womenTags: contraception, patient safety, war on women
Why women voting matters today more than ever
A letter to Dr. Oz for his In Box
Jessica A Bruno (waybeyondfedup) says:
Reblogged this on Jessica A Bruno (waybeyondfedup).
korhomme says:
I'm not an Ob/Gyn but was a general surgeon, and I do understand the procedures.
The reports speak of "tubectomy" rather than tubal ligation. Even so, to do such a procedure in five minutes or less, which is what the figures imply is impossible. Even under local anaesthesia, it is impossible.
Dr M de Bakey used to lots of heart valve replacements; but he had five or so operating theatres, and five teams. Each team would prepare the patient, including any necessary heart by-pass; Dr De Bakey only replaced the valve, the team completed the operation.
Even if this was how so many patients were "managed", it still allows only a few minutes for the surgeon to clip the tubes after the anaesthesia (if any) has been given and the pneumoperitoneum to be established. Even so, I cannot see how so many women were operated on by one surgeon and an assistant in such a short time; it is just not credible.
enaffaaffane13 says:
What does that mean ….!!!!
ErinBliss says:
Even with all the problems this country this has, I am feeling blessed.
This is just sickening.
bethhavey says:
With the rapes in India and now this, women are obviously not honored. It is shameful in 2014 to read of this kind of slaughter–that's really what it is.
Tom Yokohama says:
Unlicensed (and even those with licenses) medical professionals can and do make horrible decisions that lead to unnecessary suffering by patients and their loved ones whether in India, Japan, or the United States. The profit motive for both doctors and patients, poor regulation, public health policy concerns, and a whole host of other issues created an environment where this happened.
Unfortunately, Americans have a habit of cherry picking news like this to support their unsophisticated opinions about other nations (look up confirmation bias). Does India have a problem with rape? Yes. The United States has problems with rape, gender pay equality, domestic violence, age discrimination disproportionately aimed at women, body image shaming of women who do not fit pop culture ideals, and racism just to name a few but none of us condemn your nation. We call this bigotry.
Perhaps your shame and scorn extends to the events occurring in the United States but I don't know. I do know doctors like Jennifer Gunter bring valuable experience to explain the news. There needs to be a discussion on solving the problems in India but discourse such as yours does nothing to advance any useful cause.
It may be that there is a caste problem; all the women came from the poorest, most disadvantaged caste.
Lyla Michaels says:
Reblogged this on Conversations I Wish I Had.
Canee says:
Dr Jen. Please advise about reading of HSV IgG positive (33) in first test and unequivocal in the second test after 15 days. Does it suggest virus has become dormant?
evmaroon says:
And just to throw a little more insult into the horror show, part of the money the women received for this had to be given back immediately to the van driver who took them to the surgeon. Sick.
Loren Pechtel says:
The local paper here had an article about this, contaminated drugs are suspect. On the other hand it said he had performed 50,000 such operations, from what you say that seems pretty unreasonable.
I've seen that about the contaminated drugs too. It sounds more like blame shifting.
It's also reported that the scalpel was sterilised by dipping it in spirit between cases, and being discarded after 10 or so. The towel clips were similarly sterilised. Anyone with any understanding of the sterilisation of surgical instruments would see this as about as useful as dipping instruments in holy water.
I have yet to see an explanation of how it is possible to do a "tubectomy" in two to four minutes.
It looks like there's something to the contamination claim:
Barbara O' Donnell says:
This is what happens (sickeningly) when women's rights. education and access to contraception are slim or non-existent. And I agree that mistakes/problems/issues are not limited to first world countries. All of these things, no matter where they occur, need to be discussed openly in society.
Those instruments cannot have been sterilised in any meaningful way. No operating theatre, even in the West has 83 sets/scopes on hand. Even 40. A mini autoclave cycle would be 30 mins generally in between cases. And we have stopped using mini autoclaves in main operating theatres in the UK due to increasingly stringent traceability requirements.
I find it incredibly difficult that this doctor will have been attended by other healthcare professionals, all of whom were knowingly carrying out these procedures in worse than substandard conditions. Dr. Gupta's assertions that he was "morally obligated" to operate on these women because the administration rounded up 83 of them is another load of absolute rubbish for which I don't have words,
It's also about poverty, the women operated on came from the lowest and most impoverished caste.
And the place of men and women in society; a vasectomy is quicker and less invasive than a tubal ligation, but apparently not so acceptable to men. India did have a vasectomy policy some years ago, this seems to have been curtailed.
The "Little Sister" and similar types of small autoclaves were useful when someone accidentally contaminated an instrument; it didn't take long to autoclave it. However, doubts were raised about how effective it was.
Pingback: Claims of poisoning in India sterilization deaths seem unlikely | Dr. Jen Gunter
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The external connector is only necessary for CRM On-premise. The external connector license is already included in partner hosted CRM (SPLA) and CRM Online. The license is not a CAL license, it is a server license. You license your CRM server for external access. You purchase one external connector for every CRM server you have licensed. Another thing to consider is that an external connector will not give any users any rights to use the UI or outlook client - you will have to build your own portal to access the data. It is only for external people in your organization. In your case, both of those seem to be true. I hope you are building your external portal using the portal framework - if you need more information, please feel free to contact me.
Thank you for sharing more details on External Connector License. Yes, I am building a separate website and planning to use "CRM 2011 ASP.NET Membership Provider".
Hello Ankit, External Connector License is to give access to any of the Non-Employee. (Dealers, Partners, Distributors, Consultants & Others). They can access MS CRM data through the API or Custom Portal. You can also give access of crm data to employee via portal, but u need to buy ESS CAL for the Employee.
Am going to use CRM External connector License, to allow access to external user.
1) Do we add external connector user to CRM System use entity.
2) IF yes then what is the access type/ license type to set to user.
The external connector licence is a trust license. It has nothing to do with the implementation. No need to attach it in CRM system user entity.


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The End of Tangier
Shoshi Parks
Portraits of a Vanished Army
Wesley Morgan
Erhan Kahveci is a Milan-based documentary photographer driven by a desire to see people and the hidden parts of the world, and capture society through his images.
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Erhan Kahveci is a Milan-based documentary photographer who has traveled to more than 40 countries, mostly solo, driven by a desire to see people and hidden parts of the world, and capture society through his images. He grew up in Turkey, where East meets West, and moved to Italy in 2012.
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Q: Merging dataframes with all.equal on numeric(float) keys? I have two data frames I want to merge based on a numeric value, however I am having trouble with floating point accuracy. Example:
> df1 <- data.frame(number = 0.1 + seq(0.01,0.1,0.01), letters = letters[1:10])
> df2 <- data.frame(number = seq(0.11,0.2,0.01), LETTERS = LETTERS[1:10])
> (merged <- merge(df1, df2, by = "number", all = TRUE))
   number letters LETTERS
1    0.11       a       A
2    0.12    <NA>       B
3    0.12       b    <NA>
4    0.13       c       C
5    0.14       d       D
6    0.15    <NA>       E
7    0.15       e    <NA>
8    0.16       f       F
9    0.17       g       G
10   0.18       h       H
11   0.19       i       I
12   0.20       j       J

Some of the values (0.12 and 0.15) don't match up due to floating point accuracy issues as discussed in this post.  The solution for finding equality there was the use of the all.equal function to remove floating point artifacts, however I don't believe there is a way to do this within the merge function.
Currently I get around it by forcing one of the the number columns to a character and then back to a number after merge, but this is a little clunky; does anyone have a better solution for this problem?
> df1c <- df1
> df1c[["number"]] <- as.character(df1c[["number"]])
> merged2 <- merge(df1c, df2, by = "number", all = TRUE)
> merged2[["number"]] <- as.numeric(merged2[["number"]])
> merged2
   number letters LETTERS
1    0.11       a       A
2    0.12       b       B
3    0.13       c       C
4    0.14       d       D
5    0.15       e       E
6    0.16       f       F
7    0.17       g       G
8    0.18       h       H
9    0.19       i       I
10   0.20       j       J

EDIT: A little more about the data

*

*I wanted to keep my question general to make it more applicable to other people's problems, but it seems I may need to be more specific to get an answer.

*It is likely that all of the issues with merging with be due to floating point inaccuracy, but it may be a little hard to be sure.  The data comes in as a series of time series values, a start time, and a frequency.  These are then turned into a time series (ts) object and a number of functions are called to extract features from the time series (one of which is the time value), which is returned as a data frame.  Meanwhile another set of functions is being called to get other features from the time series as targets.  There are also potentially other series getting features generated to complement the original series.  These values then have to be reunited using the time value.

*Can't store as POSIXct: Each of these processes (feature extraction, target computation, merging) has to be able to occur independently and be stored in a CSV type format so it can be passed to other platforms.  Storing as a POSIXct value would be difficult since the series aren't necessarily stored in calendar times.

A: Round to the level of precision that will allow the number to be equal.
> df1$number=round(df1$number,2)
> df2$number=round(df2$number,2)
>
>  (merged <- merge(df1, df2, by = "number", all = TRUE))
   number letters LETTERS
1    0.11       a       A
2    0.12       b       B
3    0.13       c       C
4    0.14       d       D
5    0.15       e       E
6    0.16       f       F
7    0.17       g       G
8    0.18       h       H
9    0.19       i       I
10   0.20       j       J

If you need to choose the level of precision programmatically then you should tell us more about the data and whether we can perhaps assume that it will always be due to floating point inaccuracy. If so, then rounding to 10 decimal places should be fine. The all.equal function uses sqrt(.Machine$double.eps) which in usually practice should be similar to round( ..., 16).

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Next message: [mythtv] SEGV attempting to use ThreadedFileWriter after deletion.
> unless an underdosage of major tranquilizers was involved.
> of wasting *your* time?
(for *a valid engineering reason*, no less).
> I seem to have wandered into the last reel of The Cable Guy.
> in my opinion you should state it.
I did.  Try reading the bug logs before making baseless accusations.


This issue occurs when you run the ServerProtect for Microsoft Windows/Novell Netware setup on the server to install only the NS component.
On the IS, go to the \Program Files\trend\Sprotect folder and back up the TMRPC.ini file.
Open and edit the TMRPC.ini file.
Look for the entry of the NS that you want to add. This may be the server name or IP address. If it does not exist, add the entry and give it the value "2".
Save and close the TMRPC.ini file.
Restart the Trend ServerProtect Agent service.
On the Normal Server that could not be added to IS, go to the \Program Files\trend\Sprotect folder.
Back up and edit the TMRPC.ini file.
Look for the entry of the IS that you want to add. This may be the server name or IP address. If it does not exist, add the entry and give it the value "2".
Restart the Trend Server Protect service.
Log on to the ServerProtect management console and retry adding the NS.
If there is no entry for Client Protocols in the registry, then recreate the whole key.
In the Registry Editor, create the HKEY_LOCAL_MACHINE\SOFTWARE\Microsoft\Rpc\ClientProtocols subkey.
If you have another working Normal Server, then export the same registry key and then import it on the target server.
Restart the server and try again.


text:
Home > Criminal Defense > Searches and Seizures
Fourth Amendment Rights
The Fourth Amendment of the U.S. Constitution provides that the right of the people to be secure in their persons, houses, papers, and effects, against unreasonable searches and seizures, shall not be violated, and no Warrants shall issue, but upon probable cause, supported by Oath or affirmation, and particularly describing the place to be searched, and the persons or things to be seized. aclu.org
If law enforcement believes a crime has been committed, based on information and belief, a search warrant must be obtained from a judge before a search can be conducted. The judge will only issue a warrant if he/she is convinced that the search will lead to evidence in support of the alleged crime. Furthermore, the warrant must set forth specifically who, what, and where with regard to a search. For example, a judge issued a warrant for the lawful search of your home office only. However, evidence was seized from a locked box in your bedroom during the search. The evidence confiscated from the locked box would be inadmissible at trial under the exclusionary rule doctrine because it is considered fruit of the poisonous tree. Silverthorne Lumbar Co. v. United States, 251 U.S. 385 (1920). In other words, anything taken from a tainted source is tainted.
Weeks v. United States, 232 U.S. 383 (1914) was a Supreme Court case in which, by a unanimous decision, the Court held that the warrantless seizure of items from Weeks' private home was in violation of his Fourth Amendment rights. Weeks was a federal prosecution, and the exclusionary rule only applied to federal prosecutions at that time. It was not until Mapp v. Ohio, 367 U.S. 643 (1961), more than 46 years later, that the exclusionary rule applied to state prosecutions as well.
It is fascinating that the original 10 amendments of the U.S. Constitution has remained steadfast throughout the evolution of our modern society. Do you think our forefathers could have anticipated what society would be like more than 200 years later? Do you think they could have foreseen the types of assault weapons we have today when they adopted the Second Amendment (Right to Bear Arms)?
Secure in Their Persons, Houses, Papers, and Effects Defined
Warrantless searches and seizures are unconstitutional; however, there are exceptions in which the Fourth Amendment would not be violated:
You may have heard of the term "Terry Stop." A Terry Stop gives law enforcement the authority to briefly stop and search a suspicious person and make reasonable inquiries with regard to those suspicions when an officer observes unusual conduct which leads him/her to reasonably conclude that criminal activity may be afoot. Terry v. Ohio, 392 U.S. 1 (1968)
Houses, Papers, & Effects
If a police officer reasonably believes that the person granting consent to a search has the authority to do so, then a warrant is not required. The issue is not whether the person has actual authority, but whether the police officer reasonably believes the party consenting has the authority.
Evidence is in plain sight of law enforcement officers; however, they must legally be in the location wherein the evidence can be seen in plain view.
Stop & Frisk
As mentioned above in Terry, the police are permitted to stop, and briefly search (frisk), a person provided they have a reasonable suspicion that a criminal act is, or is about to, occur. The law enforcement officer can arrest a suspect with probable cause.
Search Incident to Lawful Arrest
A limited search of a person and their immediate surroundings is permitted for the purpose of locating dangerous weapons or a means to escape, or preventing evidence from being destroyed. Law enforcement must show an actual and continuing threat to his/her safety and/or a need to preserve evidence.
Exigent circumstances exists when a situation requires immediate action, with probable cause, to act because the emergency situation outweighs the needed for a warrant. Instances when a life is in danger, or evidence is compromised, would outweigh the need for a warrant.
The hot pursuit exception permits law enforcement officers to follow suspects on, or in, private property when being pursued without a search warrant, even when the suspect has no connection whatsoever to the property. This exception is also permitted when evidence can be destroyed or moved before a warrant can be issued.
Automobile Exception
The motor vehicle exception allows law enforcement to search a vehicle, upon probable cause, without a search warrant as long as he/she believes contraband is located in the vehicle. The rationale of this exception is based on the premise that there is a lower expectation of privacy in motor vehicles. The mobility of an automobile presents an urgent need to prevent the removal of evidence.
The law is not black and white, but many complicated shades of gray. Take note of the underlined words in the above exceptions. What does probable cause or reasonable suspicion mean? I ask this rhetorically to demonstrate that one case may set a legal precedent or standard, but the Court may narrow, or broaden, the interpretation of the law when later presented with another case as noted above in Silverthorne, Weeks, and Mapp. It was more than 46 years later when the Court expanded the exclusionary rule to also include state criminal prosecutions.
The Court of Last Resort
If you are displeased with your state's appellate court ruling, you can ask (petition) the U.S. Supreme Court to hear your case. However, the Supreme Court is not obligated to do so. The Court hears cases when there are conflicting decisions in the federal circuit courts, where there is precedential value, and cases which have been decided in either a U.S. Court of Appeals or the highest state court in matters of constitutional issues. The Court generally accepts 100-150 of the 7,000 cases it is asked to review each year. uscourts.gov
One of the roles of the U.S. Supreme Court is to protect the constitutional rights of its citizens, as well as the government's interest, all while preserving the fundamental rights adopted in the Bill of Rights (Amendments 1-10) in 1791. Over the years, the Court has had to interpret the authors' intent behind the amendment, and set forth the legal standard when questions of law are presented, such as when issues of probable cause and reasonable suspicion must be defined within the context of the amendments and laws.
As you can see, the law and its application is quite complicated. If you have been arrested, consult with one of our attorneys immediately to protect and preserve your constitutional rights and to ensure you are given the due process our Constitution affords. You may call us at (704) 714-1450 for a free case evaluation and consultation.
Retrograde Extrapolation and Expert Testimony
Contributory Negligence in Car Accidents in North Carolina
Dog Bites In North Carolina
Jury Selection Process in North Carolina Criminal Trials


text:
Haunted Inns in Gettysburg, Pennsylvania
Haunted Hotels on Staten Island, New York
Candlelight Ghost Tours of Gettysburg
Susan Miller, Leaf Group
Monument at Gettysburg National Military Park (Photo: GETTYSBURG image by brelsbil from Fotolia.com )
Halloween Activities and Haunted Houses in Colonial Williamsburg, VA
Salem Graveyard Tours
It's alleged that ghosts still inhabit Gettysburg, the town where the horrific Civil War battle took place on July 1, 2 and 3 of 1863. More than 51,000 soldiers and 5,000 horses died, prompting President Abraham Lincoln to establish a national cemetery there; he memorialized the dead in the Gettysburg Address. Several tour guides have put together different walking tours conducted by candlelight. The tours are not for the squeamish; some even say they've felt ghostly hands tap them from behind. Keep in mind that no paranormal activity has been proven, and a healthy dose of skepticism should be in mind while enjoying the entertainment value of these tours.
Farnsworth House Inn Tours
The Farnsworth House Inn has been called "one of the most haunted inns in America" by the Travel Channel. The Inn was a single family home during the Battle of Gettysburg, but it sustained more than 100 bullet holes as the war raged around it, which can still be seen. The Inn hosts four candlelight ghost tours, which all begin at the Farnsworth House. Guests can take the East Cemetery Hill Walk and the Confederate Hospital Ghost Walk nightly. Two additional tours are offered on Fridays and Saturdays only: the College Tour and the "Mature Tour," which is only for those over the age of 12 due to its graphic content.
Farnsworth House Inn
401 Baltimore St.
gettysburgshauntedaddress.com
Ghosts of Gettysburg Candlelight Tours
The Ghosts of Gettysburg Candlelight Tours hosts tours based on the books by Mark Nesbitt. The three-quarter mile tours include the Baltimore Street, Carlisle Street, Seminary Ridge and Steinwehr Avenue walking tours, which each last about one hour, 15 minutes. The Baltimore Street tour takes guests to the county courthouse and a church that both served as a makeshift hospital for wounded soldiers. The Steinwehr Avenue tour visits the Gettysburg National Cemetery. A bus tour, offered from Memorial Day weekend through Halloween, encompasses sites not included in the walking tours.
Ghosts of Gettysburg
ghostsofgettysburg.com
Sleepy Hollow of Gettysburg Tours
The primary focus of the three tours offered by Sleepy Hollow of Gettysburg are the tales told by the storytelling guides. The Towne Tour covers three to five blocks of Gettysburg's historic district and lasts about 90 minutes. The Psychic Medium Tour is led by a psychic who uses dowsing rods and other tools to share insights with guests. The more comprehensive Seminary Ridge Tour takes guests directly to the battlefield itself.
Sleepy Hollow of Gettysburg Candlelight Ghost Tours
61 Steinwehr Ave.
sleepyhollowofgettysburg.com
Gettysburg Ghost Tours
Gettysburg Ghost Tours offers three candlelight walking tours. The Black Cat Tour takes guests down dark alleys where fighting occurred, and to sites that once served as shallow makeshift graves. The Battlecry Tour covers cemeteries, battlegrounds and haunted hotels. The Scare on the Square Tour visits Seminary Ridge, historic buildings and the hotel where President Abraham Lincoln stayed the night before he gave the Gettysburg Address. A motor coach tour called the Haunted Coach Tour is also offered.
gettysburgghosttours.com
Ghosts of Gettysburg Tours
Susan Miller has been a professional journalist since 1990. She edited two weeklies for a chain of suburban newspapers and has written for the "Indianapolis Star," the "Indianapolis Business Journal" and several magazines, among other publications and websites. Miller studied design, photography and technology at Purdue University and Central Piedmont Community College.
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It's not surprising that veteran NFL player Donald Lee is passionate about football. What may come as a surprise to some, however, is that Lee is equally passionate about the town that set him on the path to play in the National Football League.
The Maben native and former standout tight end at Mississippi State University is a 10-year NFL veteran. A fifth-round pick in the 2003 NFL Draft, Lee currently plays for the Cincinnati Bengals, his third team. He also has a Super Bowl ring after helping the Green Bay Packers to the title in 2011.
Two days before reporting to training camp with the Bengals, Lee reclines in ease in one of the overstuffed chairs at the Bookmart in Starkville. Although he is nonchalant about his status as an NFL player, when he speaks of his love for the game and the college that gave him his start, a glint appears in his eye and a smile flashes across his face. He leans forward in his chair and excitedly reflects on his time spent at MSU and his dedication to the town that supported him. Now, Lee says he wants to give back to the community that has given so much to him.
Lee and his childhood best friend Lamar Ware are partnering to bring national restaurant chain Beef 'O' Brady's to Starkville. The restaurant will be located on the now vacant lot in front off the Malco Cinema off of Hwy. 12.
Ware, who will act as the general manager for the eatery, says he and Lee want the new franchise to be "a restaurant for the community, not just a restaurant in the community."
Lee and Ware met as teens years when Ware's mother, Gwendolyn Ware, was Lee's teacher at Maben High School. The two became fast friends and kept touch throughout the years as Lee headed to Mississippi State and Ware went to Moore College in Birmingham. When Lee headed to Florida to begin his NFL career, Ware moved to Texas to pursue a career in the medical field. However, both men say that Mississippi will always be home. That sense of community is why the two decided to open up a restaurant in Starkville.
"We're about family," said Ware. "We're about community. We feel that's what Beef O' Brady's is about, too."
While Lee's presence in town will be limited as he is bound for the Bengals' training camp followed by a 16-game NFL season -- followed by the playoffs, hopefully. Ware will remain in Starkville and manage the project from the ground up. Ware, a Starkville resident, says he plans to get involved with local youth. He said that once the restaurant is up and running, he and Lee would like to sponsor various youth sports teams as well as host music venues in the area. Ware and Lee both repeatedly stated their desire to show local youths "hand work and dedication pays off."
Both Lee and Ware credit their determination and belief in hard work to their experience on the football field.
Lee said football can teach you a lot about life and reflected back on a speech his high school football coach gave during one of his first days on the field. Lee said the coach told him and his fellow teammates that everything is a habit, adding that while football is hard, those who stuck it out and worked hard to succeed on the field would inevitably work hard and succeed off the field. Those who chose to quit football because it required hard work would either end up dead or in jail.
He applied that lesson early on in life and he says it has carried him for the past 15 years. Lee, 31, said he has accomplished everything he set out to achieve all those years ago on his high school football field.
"I always said I wanted to play 10 years in the NFL. I've done that and it's a dream come true," Lee said.
Lee frequently returns home to Starkville to spend time with his two children and he says misses home while he is away playing football. Opening a restaurant close to his alma mater is just another reason for the football icon to return home.
Both Lee and Ware are looking forward to the restaurant's opening, which, according to a press release from Beef 'O' Brady's, will be sometime in November.
The Starkville location will be the launch of the "new Beef's 2.0 prototype" which is set to include large screen TV's, small televisions throughout the restaurant and video games for both children and adults to enjoy. Lee and Ware attribute the chain's "kid-friendly" atmosphere as the main reason the two choose to join the expanding franchise.
The restaurant's location at 1205 Stark Road, should attract movie-goers from the nearby Malco Cinema.
"You can take your family to dinner then a movie,'' Lee said. "It's the American Dream."
Sarah Fowler covered crime, education and community related events for The Dispatch.