A power management circuit for an SRAM system including one or more isolated memory arrays and implementing a power source including a local power supply associated with each memory array and an external power supply connected to local supplies during an active mode of operation. The power management circuit comprises: a switch mechanism for disconnecting the external power supply to each of local power supply during a low power mode of operation; and, a refresh timing circuit implementing memory array refresh operation by selectively connecting the external power supply to a respective local power supply during the low power mode. During the low power mode, the refresh circuit intentionally enables the local power supply to float and allow it to drift to a lower predetermined voltage level prior to the memory array refresh operation.
This invention relates generally to memory systems, and more specifically, a low power static random access memory (SRAM) system including a power management scheme implementing a novel, robust refresh control circuit for enabling significantly reduced low power operation.
SRAM, or static random access memory, due to its high-performance nature, is widely used in computer systems. As the density of the SRAM is further improved along with the scaling of the technology, the SRAM memory chips, or embedded macros are also widely adopted in the hand-held systems, such as cell phone, personal digital assistants (PDA), global positioning systems (GPS), especially for L1 or L2 cache. The design of SRAM is simpler than that of dynamic random access memory (DRAM) systems in that the data stored in the array are latched in the cells and no refresh is required. SRAM is additionally faster than DRAM, since all the read operations are nondestructive, no write back or bit-line pre-charge period is required. Recently, a 4-T SRAM cell has been proposed by NEC to further reduce the SRAM size. Normally, SRAM cell efficiency (i.e., the area ratio of array to the whole chip) is higher than that of DRAM. Area overhead such as on-chip generator system, refresh unit, redundancy and complex BIST are absent from SRAM circuits.
However, the biggest concern for SRAMs to be used for low-power systems is the stand-by current from the arrays when they are idle. The power supply to the SRAM array must be maintained during the low-power modes, e.g., sleep and stand-by modes, or otherwise, the data stored in the array will be lost. Some prior art systems have addressed this problem by shutting off the portion of the array that is not in use. This method relies on the system to decide which part of the array is in use, and to switch off the array that is not needed in the low-power mode. This also requires a large area for placing the switch device, since every row needs a switch to selectively turn it off. As proposed by M. Powell, from Purdue University in the digest paper entitled "Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep Sub-Micron Cache Memory" published by the International Symposium on Low-Power Electronic Design (ILPED 2000 pages 90-95), a switch to shut off the row may degrade the SRAM performance if it is not properly sized. Additionally, a complex decoding and switch circuit to shut off the rows is required. This approach is especially not effective when a small SRAM is used, and when most of the array is needed for data storage during the low-power mode, e.g., when SRAMs are to be used for cache applications.
The concept of low-power SRAM using a refreshable array scheme has been proposed. The power saving of the refreshable SRAM array during stand-by is significant, especially when the array is large and stand-by period is long. Use of a conventional DRAM-like refresh circuit that is able to perform the refreshing of local supplies, and SRAM cells, is not very desirable in that such a solution is typically (1) bulky in size, (2) consumes a larger power overhead, and (3) requires an initial test to set the refresh timing.
It would be highly desirable to provide a power management circuit to minimize the power consumption of SRAM arrays especially during the low-power modes of operation.
It would be further highly desirable to provide a new and robust refresh circuit that is relatively smaller than those implemented in DRAM circuits, and that obviates the need of conventional clock generator for the refresh timing.
It would be further highly desirable to provide a new and robust refresh circuit that where the refresh timing is generated directly from the internal or local voltage supply.
It is an object of the present invention to provide a power management circuit to minimize the power consumption of SRAM arrays especially during the low-power mode.
It is a further object of the present invention to implement a refresh timing circuit similar to that of DRAMs to conduct refresh to the internal (local) voltage supply of the SRAM arrays, however implements a novel refresh timing mechanism that is generated directly from the local voltage supply.
According to the principles of the invention, there is provided a power management circuit for an SRAM system including one or more memory arrays and implementing a power source including a local power supply associated with each memory array and an external power supply connected to each local power supply during active mode of operation, the power management circuit comprising: a switch mechanism for disconnecting the external power supply to each of local power supply during a low power mode of operation; and, a refresh timing circuit implementing memory cell refresh operation by selectively connecting the external power supply to a respective local power supply during the low power mode, wherein, during the low power mode, the refresh circuit intentionally enables the local power supply to float and drift to a lower predetermined voltage level prior to the memory cell refresh operation.
In a further embodiment, there is implemented a refresh timing circuit similar to that provided in DRAM circuits to conduct refresh to the local power supply of the SRAM arrays. Particularly, in accomplishing improved low power operation, a soft-refresh to the SRAM arrays and the local power supply is implemented. The SRAM arrays are further partitioned into multiple of sub-arrays with ground buses used to isolate the sub-arrays. To optimize the power saving, a test algorithm is proposed to determine the optimum SRAM array refresh cycle time which is programmable by fuse elements in the power management circuit.
Advantageously, detrimental noise coupling effects are avoided while SRAM arrays are in the low-power mode to prevent the possibility of lost data.
FIG. 1 is a circuit diagram illustrating the low-power SRAM block 100 with dynamic array refresh scheme according to the invention.
FIG. 2 illustrates a circuit schematic of the power management circuit for the SRAM circuit of the invention.
FIG. 3 depicts the layout of the power management circuit 200 for an SRAM sub-array circuit of the invention.
FIG. 4 is a diagram illustrating an example SRAM refresh control circuit 400 according to the invention.
FIG. 5 is a schematic diagram illustrating a conventional 6-T SRAM cell.
FIGS. 6(a)-6(c) illustrates voltage waveform diagrams relating to the dynamic array precharge in accordance with the principles of the invention.
FIG. 7 illustrates a circuit schematic of a refresh control circuit 600 according to a preferred embodiment of the invention.
FIGS. 8(a)-8(d) illustrate various voltage waveforms corresponding to the refresh circuit of FIG. 7.
FIG. 9 illustrates in greater detail a J-K flip-flop provided with a sleep control input for use in the refresh control circuit of the invention.
FIG. 10 illustrates a circuit schematic of a refresh control circuit 200′ implementing a voltage clamp technique according to another preferred embodiment of the invention.
FIG. 11(a) illustrates voltage waveforms of the refresh control circuit 200′ implementing the voltage clamp technique and FIG. 11(b) illustrates a corresponding voltage supply current waveform for the voltage clamp refresh circuit.
According to the invention, there is provided an exemplary depiction of a low-power SRAM circuit 100 with dynamic array refresh scheme according to the principles of the invention. As shown in FIG. 1, the SRAM circuit 100 comprises four sub-arrays 10, 20, 30 and 40, with each sub-array including a respective power management unit, 91, 92, 93 and 94 which decides and controls when each respective sub-array is to be connected to a major power supply, i.e., Vdd 15. The SRAM circuit 100 further includes row decoder and word-line drivers 50, pre-decoder, and control block circuitry 70, and, sense-amplifiers, column switches, column decoders, and I/O drivers 60. A novel refresh control circuit 80 that generates refresh cycle time for the power management unit is additionally provided as will be discussed in greater detail herein. Further included is the major Vdd power supply 15 that powers each array, and ground buses 11,12,13,14 and 16 that isolate each of the arrays from each. As will be described in greater detail, the SRAM sub-arrays may be refreshed simultaneously or, one at a time. The provision of the ground busses acts to minimize any coupling from the neighboring array during refresh.
FIG. 2 illustrates a circuit schematic of the power management circuit for the SRAM circuit of the invention. As shown in FIG. 2, the power management circuit 300 supplies power from a major power supply source 210 to each sub-array, i.e., labeled sub-army (1), (2) (3) and (4). Preferably, the power management component for each of the sub-arrays comprises two sets of switches: a first set of switches 220 which are large size MOS devices that are used to connect to four sub-arrays and are fully turned on during the active mode operation (i.e., not in sleep mode), and 2) a second set of smaller switch devices 260 are used to refresh each of the internal supplies 240 to each of the sub-array (1), (2) (3) and (4) during the non-active mode (or sleep mode). The switches 260, 220 for a respective sub-array is referred to as a switch unit 201 such as the one shown corresponding to memory sub-array (1) an example layout of which is illustrated in FIG. 3. To avoid a threshold voltage drop, it is desirable that pMOS devices are used for each first switch device 220. To avoid a power surge, one internal supply maybe refreshed for a sub-array individually one at a time. However, for the soft-refresh, power surge is not a concern, and all sub-arrays may be refreshed simultaneously. As will be described in greater detail hereinbelow, a refresh control circuit, like a DRAM system, implements a refresh clock generator to provide the controls to each refresh switch. As shown in FIG. 2, the refresh control circuit generates respective switch control signals 231, 232,233 and 234, for controlling second set transistors 260 of each respective sub-array (1), (2), (3) and (4). Further, the power management circuit of FIG. 2 includes a respective reservoir capacitor 270 attached to the internal power supplies 240. These capacitors 270 are used to temporarily supply a charge for replenishing any leaky arrays so that a refresh period may be reasonably long. This acts to further facilitate power savings. The switches 220, 260 for a respective sub-array are referred to as a switch unit 201 as shown corresponding to memory sub-array (1) with an example layout illustrated in FIG. 3.
Particularly, FIG. 3 illustrates the layout of the power management circuit 200 for an SRAM sub-array circuit of the invention. As shown in FIG. 3, a major power supply that feeds the SRAM array is a wide metal bus 110 which connects to the source of a pMOS device 150 via a group of conductors 180. The drain of the pMOS device is connected to the internal supply bus 140 via another group of metal conductors 190. This pMOS switch with a gate 120 (corresponding to switch 220 in FIG. 2) is a very wide device to ensure that the "on"-resistance will be low. During the active mode, the switch is activated by a control "not-sleep" or "sleep-bar" signal applied to gate 120. During the active mode, the power supply to the array should have as lowest resistance as possible so not to degrade the SRAM's performance. As further shown in FIG. 3, the second switch for this sub-array 160 (corresponding to switch 260 in FIG. 2) may also be a pMOS device, however, preferably, is a very small device, with device width ranging from about 1.0 μm to 5.0 μm. The reason that a small device is used is to ensure a "soft" switch, and thus "soft-refresh" during SRAM array refresh, as will be described in greater detail herein. Soft-refresh is understood to mean bringing of the internal supply voltage back to a predetermined high-level at a low-rate to avoid coupling noise. The gate of the smaller switch 160 is controlled by a control signal 130 from the refresh control circuit. During the sleep mode, the supply to each sub-array will be refreshed simultaneously, or sequentially. Similarly, the source of the switch pMOS device 160 is connected to the external supply via a group of conductors 196, and the drain of the switch pMOS device 160 is connected to the local supply via conductors 195. The reservoir capacitor 170 as laid out in FIG. 3, is preferably a gate oxide capacitor, trench capacitor or any other on-chip, low-cost capacitor.
FIG. 4 is a block diagram of an example of SRAM refresh control circuit 400 (or 80 in FIG. 1) according to a first embodiment of the invention. As shown in FIG. 4, the SRAM refresh control circuit 400 comprises a refresh clock generator 340, a refresh address counter 350, an address decoder 360, a pulse generator 370, and a clock timing adjustment unit 380. In general, these components function as those used for generating refresh pulse for a DRAM array circuit. For instance, the refresh clock generator 340 may comprise an RC timer circuit for producing a coarse timing signal to refresh the internal supply with the understanding that the refresh timing is dependent upon the resistor and capacitor sizes of the RC timer. Depending on the technology, and the selected array size, the SRAM refresh period may range anywhere between about 1 μs to 100 μs. The clock timing adjust unit 380 provides a timing adjustment by enabling programming of fuses during a test mode. Once the timing is set, the counter 350 and decoder 360 circuits function to refresh the array, or indicate which local supply needs to be refreshed. While refreshing the local supply, the true and complement nodes of cells in the corresponding array are differentiated. The pulse generator circuit 370 functions to generate a refresh pulse 371 having a pulse width, for example, ranging anywhere from about 1 ns to 100 ns. If the whole array is refreshed at once, then the counter and decoder are not needed. The output signals 331, 332, 333 and 334 of the SRAM refresh control circuit 400 are input as the four switch control signals 231, 232, 233 and 234, and are generated in the sleep mode to sequentially switch transistor devices 260 of each respective sub-array (1), (2), (3) and (4) (as shown in FIG. 2). The SRAM refresh control circuit 400 additionally generates a control signal 320 which functions to switch on/off each of the first switch devices 220 which connect the major supply to the local supplies during the active mode. As shown in FIG. 4, the refresh control circuit 400 receives a 2-bit input control signal 310 that is decoded to determine which of the sub-arrays, e.g., sub-arrays (1)-(4), are to receive the respective control signal 331-334 used to activate the refresh operation during sleep mode. A "sleep" control signal 330 is used to activate the whole refresh control circuit.
As known, it is imperative that the data stored in the SRAM array experience minimum coupling from the environment during an SRAM refresh operation is that, i.e., the differential data bits stored in the internal nodes of a SRAM cell be correctly restored when a refresh operation is finished. FIG. 5 is a schematic diagram illustrating a conventional 6-T SRAM cell 500 which is formed by two back-to-back inverters 510, 520 and two transfer gates N1 and N2, with a first inverter 510 formed by pMOS transistor P1 and nMOS transistor N3, and a second inverter 520 formed by pMOS transistor P2 and nMOS transistor N4. The gates of the transfer devices N1 and N2 are connected to a word-line. The source of the transfer gate N1 is connected to a bit-line BL, and the transfer gate N2 is connected to a complimentary bit-line bBL. The power supply to the cell is coming from Vdd line via the sources of each pull-up pMOS device of the inverters 510, 520. The sources of the NMOS devices of the inverters are connected to ground. As shown in FIG. 5, in operation, when the internal node of the inverter 510 is a high or logic "1" state, e.g., 1.2V, the inverter 520 is a "Low" state, e.g. 0V. If power is suddenly removed from the supply, the "high" node will drift lower due to the channel leakage of the pull-down N3 devices. If bit-lines are pre-charged to a high voltage level, then channel leakage via the transfer device N2 will also occur. Furthermore, the voltage "low" state will become higher due to charge leakage from bBL. When the voltage level of the high state drifts lower than certain value, and the voltage level of the low state drifts higher than a certain value, the latched data is no longer valid. Therefore, for such refresh operation, it must be decided at which low voltage level the internal supply must be refreshed.
As known from the DRAM read operation, as long as a delta signal, i.e., the differential voltage maintained at the internal nodes of the cell is maintained above 100 mV, it is safe to differentiate the high and low data using the latch-type sense amplifier. For a more conservative approach, the Low-Vdd level may be set to achieve a delta higher than 100 mV minimum delta and ranging anywhere from about 100 mV to 300 mV minimum delta. Furthermore, it is advantageous to intentionally provide a built-in capacitor (Ch1) linking between two-internal nodes of SRAM cells so that noise margin may be significantly improved due to coupling effect.
FIGS. 6(a)-6(c) illustrates voltage waveform diagrams relating to the dynamic array precharge operation in accordance with the principles of the invention. It is desirable that the ramp up rate of the internal Vdd refresh is not too rapid, i.e., soft, in order to avoid the noise coupling effect. As shown in FIG. 6(a), the internal Vdd node of a static SRAM cell is first pre-charged to a level High-Vdd, at 550 and after reaching this voltage level, is left floating until it hits the Low-Vdd level, at 560. During a test mode, the SRAM array is written with all high data, and the time period for the Vdd to drift to the lowest Low-Vdd level is measured. This time is then programmed in the refresh timer circuit for the periodic internal power supply low power mode refresh operation. When the sleep mode is over, the internal Vdd level is restored to the full High-Vdd level.
It should be understood that by changing the size of the switch, the ramp up rate of the internal voltage supply level during a "refresh period" 565 is controlled. In one example, a 10.0 ns to 100.0 ns period refresh pulse-width may be used for each 1000 ns to 1500 ns refresh period. As small as a 1.0 μm wide of MOS switch may be needed to perform the "soft refresh". It is determined that a 1.0 μm wide MOS switch device is sufficient for a 250 k of sub-array, since during a refresh period, the Low-Vdd level may be at 200 mV-300 mV and still achieve a conservative delta. The stand-by power comparison between this refresh scheme and a no-refresh conventional one is 3.2 μA versus 26 μA, for a 250 K array. This doesn't include the power used to perform the refresh, which is about 20 μA. Therefore, for a larger array, using 4M as an example (i.e., equal to sixteen 250 K sub-arrays), by implementing this method, the SRAM array stand-by current may be reduced from 416 μA to 71.2 μA (51.2 μA+20 μA) or about an 83% saving of leakage current for a 4M SRAM. When combined with a mechanism for disengaging the unused SRAM portion, the saving will be even more significant. Further power savings will result by preventing refresh operation to those sub-array portions known to be not in use during a low-power mode.
According to the preferred embodiment, a new and robust refresh circuit is provided which obviates the need for a conventional clock generator, and thus, is simpler and relatively smaller in size. Rather, in the preferred refresh circuit, the timing is generated directly from the internal voltage supply. The principle of operation is as follows: during the sleep mode, the switch connecting the major supply to the local supplies is turned off. The local supply level floats and the voltage gradually falls as millions of the cells are simultaneously leaked. When a predetermined low voltage on the local supply is detected, the switches that join the internal supply to the external supply (Vdd) are activated to increase the voltage level of the internal supply (a refresh period). When the predetermined high level is detected, the switch is turned off, and the local supplies become floating again. The waveforms of the local supply voltages during sleep mode are as shown in FIG. 6(a). FIG. 6(b) depicts the sleep mode control signal 320′ and the FIG. 6(c) depicts the pulsed refresh waveform 330 having a typical floating period of about 1 μs, for example, and a refresh period of about 10 ns, for example. Depending upon the desirable high and low level, the refresh timing may be different.
A simple circuit schematic of a refresh control circuit 600 according to a preferred embodiment is shown in FIG. 7. As shown, refresh control circuit 600 comprises a voltage divider component 620, first and second low-power differential amplifiers 630, 635 connected at respective different nodes of the voltage divider component 620, and a flip-flop device such as J-K flip-flop 640. In order to keep the power overhead of the control circuit to be less than 10 uA, the voltage divider circuit is comprised of high value resistors (e.g., in the range of Mohm). In an example embodiment depicted in FIG. 7, the voltage divider component 620 includes three resistors R1-R3 connected in serial with resistance values of 0.12 Mohm, 0.06 Mohm and 0.06 Mohm, respectively. The first node of the first resistor is connected to an internal power supply 240. The second node of the first resistor R1 is connected to the first node of the second resistor R2 and the first input of the first differential amplifier 630. The second node of the second resistor R2 is connected to the first node of the third resistor R3, and the first input of the second differential amplifier 635. A reference voltage, Vref, of approximately 0.6 V, for example, is connected to the second inputs of each of the first and the second differential amplifiers. The second node of the third resistor R3 is connected to the drain of a nMOS device 650 with the source of the NMOS device 650 connected with ground. The output of the first differential amplifier 630 is input to the "J" input of a J-K flip-flop 640 and the output of the second differential amplifier 635 is input to the "K" input of the J-K flip-flop. The inverted output of the J-K flip-flop is connected with the switch 260 connected between the major power supply Vdd 210 to the internal (local) power supply 240.
The resistors R1-R3 are used to set the high-voltage level (Vh) and low- voltage level (Vl) of the local supply. For example, values of Vdd=1.2V with the high level being set at Vh=0.6V and low-level being set at Vl=0.3V may be used. The local supply may be set at such a low range is to ensure that array leakage is minimal, since I=V/R. If V is small, the DC leakage current "I" will also be small, accordingly. However, it is understood that the low level may not be too low, or the data stored in the cells may be lost due to noise. As further shown in FIG. 7, it is noted that a sleep control signal 320 is presented to activate the refresh circuit 600. When the sleep is over, all the refresh components are disabled.
FIGS. 8(a)-8(d) illustrate various voltage waveforms corresponding to the refresh circuit of FIG. 7. As shown in FIG. 8(a), when the internal voltage supply voltage 662 is lower than 0.3V, the second differential amplifier 635 will activate to reset the J input (FIG. 8(b)) causing the output switch to 260 to turn on (FIG. 8(d)) and enabling the internal Vdd voltage to rise. More specifically, as shown in FIG. 8(a), when the low level is reached, some over-shooting 663 occurs due to the relatively slow response time of the low-power differential amplifier and low-power voltage divider. At this moment, the second differential amplifier will swing, creating the "J" pulse which forces the negative output of the J-K flip-flop to engage the switch. The falling edge of the J pulse is caused by the detection of the low-level has reached, and has no effect on the J-K flip-flop. Consequently, the switch is maintained on as shown in FIG. 8(d). Similarly, when the internal voltage supply voltage 662 reaches the Vh level of about 0.6V at 664, the first differential amplifier 630 is activated to reset the K input (FIG. 8(c)) causing the output switch to 260 to turn off (FIG. 8(d)) and enabling the internal Vdd voltage to float. Thus, after a certain overshooting 664, the local supply is reduced to below the high level since the switch is shut off. More specifically, as shown in FIG. 8(a), the second differential amplifier first is turned on when the high-level is reached which creates the rising edge of the "K" pulse which, in turn, forces the negative output of the J-K flip-flop to disengage the switch 260 (FIG. 7). When the switch is off, the voltage will drop from an overshot level back to below the high level, which will trigger the second differential amplifier off. This has no effect on the J-K flip-flop and the switch is maintained off until the voltage falls below the low level at which time the cycle again will start.
FIG. 9 illustrates in greater detail the J-K flip-flop 640 which is shown as provided with a sleep control input 645 that functions to disable the flip-flop. Particularly, as shown in FIG. 9, the J-K flip-flop 640 comprises two AND gates, i.e. AND-1 and AND-2, and two NOR gates, i.e. NOR-1 and NOR-2 in the configuration shown, as known in the art, with the negative output of the flip-flop 649 being used to switch the pMOS device, according to the invention.
In an example implementation, wherein the dynamic refresh scheme according to the preferred embodiment (FIG. 7) is used in a 4M SRAM implementation, the array leakage was measured to be about 51.2 uA when the Vh level of the internal supply was set at 0.7V and Vl level was set at 0.35V. With the power consumption from the refresh control circuit being about 12 uA, the total average stand-by power is about 63.2 μA comparing to that of the conventional array of 416 μA, enabling even more significant power reduction savings.
It is desirable to further simplify operation of the power management control circuit to achieve even further power saving and reduce semiconductor real estate. Thus, in a second embodiment, the power management circuit 300′ is implemented with a static clamp mechanism for clamping the low level of the internal supply at a desirable low level, e.g., to about 0.3Vdd. The control circuit 300′ as shown in FIG. 10 corresponds to the circuit of FIG. 2, however, implements a small, high-threshold voltage nMOS device 260′ having Vth in the range from about 0.6V to about 0.8 V as the switch during sleep mode. In the active mode, these nMOS switches 260′ are turned off, and, the larger pMOS transistor switches 220′ are turned on to reduce the on resistance to the power supply line 210. While in the sleep mode, the nMOS switch 260′ is on so that the internal voltage level is clamped roughly at a voltage corresponding to Vdd−Vthn, where Vthn is the threshold voltage of the nMOS device 260′. Assuming a large SRAM array, several nMOS switches may be needed in order to evenly feed the current to the array. When implementing the circuit of FIG. 10 in a SRAM array, the "high" node voltage of the SRAM cell is first dropped from Vdd to Vdd−Vthn, or about 0.36V, when entering the sleep mode as shown in FIG. 11(a). This level is recovered back to Vdd when the sleep mode is over. As shown in FIG. 11(b), during the simulation, the average current from power supply after switching from low-resistance pMOS switch to the high-resistance high-Vt NMOS switch caused by array leakage is about 6.1 μA. The voltage is maintained at a low level 0.36V clamped by the NMOS device during the period of sleep. When the sleep is over, a 500 ns "soft-recover" period is provided to allow the cells to be restored to the full level. This soft recovery period is important in order to avoid any disturbance to the array. The average stand-by current for a 4M SRAM including the recovery current is about 97.6 uA, however no complex control circuit is needed for this approach.
This invention has great potential to be used to save power in many products using SRAM/logic technologies. The products can range from high performance servers, PC's such as the IBM PowerPC, workstations as well as portable system for pervasive and wireless applications.
a refresh control device for independently controlling each said second switch device for selectively connecting and disconnecting said external power source to said local power source associated with a respective memory array for refreshing said associated local power source during said low power mode of operation, whereby power consumption in said SRAM device is reduced during said low power mode.
2. The SRAM system as claimed in claim 1, wherein said first and second switch devices are MOS devices, said second switch device being smaller than said first switch device for slow switching during said low power mode.
3. The SRAM system as claimed in claim 1, wherein said refresh control device generates a periodic pulsed refresh control signal for periodically switching said external power source to a respective local power supply.
4. The SRAM system as claimed in claim 1, wherein said refresh control device simultaneously generates one or more pulse control signals fir enabling simultaneous switching of each second switch device for connecting said external power source to each said local power source for powering each memory array during the low-power mode.
5. The SRAM system as claimed in claim 1, wherein said refresh control device sequentially generates one or more pulse control signals for connecting said external power source to a respective local power supply of a memory array in a sequential manner during the low-power mode.
6. The SRAM system as claimed in claim 1, wherein said refresh control device includes a mechanism for sensing a voltage of said local power supply during the low-power mode, wherein upon sensing of a local supply voltage level lower than a predetermined low-level voltage, said refresh control device activating said second switch to connect the external power supply to a respective local supply to thereby increase its voltage level.
7. The SRAM system as claimed in claim 6, wherein upon sensing of the local supply voltage level at a level higher than a predetermined high-level, said refresh control device de-activating said second switch to disconnect the external power supply from the local supply to thereby decrease its voltage level due to sub-array memory cell charge leakage.
8. The SRAM system as claimed in claim 7, further comprising a reservoir capacitor connected to a respective local power supply for replenishing any the leakage charge to the SRAM arrays.
9. The SRAM system as claimed in claim 7, wherein said generated pulsed refresh control signal has a pulse width ranging from 1 nsec to 100 nsec.
10. The SRAM system as claimed in claim 7, wherein said refresh control device comprises a timer circuit for generating said pulsed refresh control signal.
11. The SRAM system as claimed in claim 3, wherein said refresh control device further comprises a decoder device responsive to a control signals for indicating a specific memory array to be refreshed.
12. The SRAM system as claimed in claim 2, wherein said first switch device is a low resistance switch for operation during said active mode, and said second switch device is a high resistance switch to ensure a soft-refresh during said low power mode.
13. The SRAM system as claimed in claim 12, wherein said first switch device is a wide channel MOS transistor device having a channel width ranging anywhere from about 100 μm-5000 μm.
14. The SRAM system as claimed in claim 12, wherein said second switch device is a narrow channel MOS transistor device having a channel width ranging anywhere from about 1 μm-5 μm.
15. The SRAM system as claimed in claim 12, wherein said second switch device is a high-threshold voltage nMOS device having a threshold voltage ranging anywhere from about 0.6 V to 1V, wherein during said low-power mode, said second switch device functions to clamp said local supply level.
16. The SRAM system as claimed in claim 12, wherein said first switch device is a low-threshold voltage pMOS device having a threshold voltage ranging anywhere from about 0.3 to 0.6V.
17. The SRAM system as claimed in claim 7, wherein a refresh cycle time period for a memory array ranges from about 1 μsec to 5 μsec.
18. The SRAM system as claimed in claim 7, wherein said predetermined high-level of the local power supply voltage ranges anywhere between 0.6 V to 1 V and said predetermined low-level of the local power supply voltage ranges from 0.2 V to 0.4 V.
means responsive to said first and second comparing devices for one of: respectively deactivate and activate said second switch device for respectively disconnecting said external power supply from said local supply or connecting said external power supply to said local supply.
20. The SRAM system as claimed in claim 19, wherein said means responsive to said first and second comparing devices includes a flip-flop device.
21. The SRAM system as claimed in claim 1, further comprising ground wiring provided to shield noise among said one or more memory arrays.
a refresh timing circuit implementing memory cell refresh operation by selectively connecting the external power supply to a respective local power supply during said low power mode, wherein, during said low power mode, said refresh circuit intentionally enables said local power supply to float and drift to a lower predetermined voltage level prior to said memory array refresh operation.
a refresh timing circuit implementing a voltage clamp device for clamping said each respective local power supply at a predetermined voltage during said low power mode, said predetermined voltage being lower than said external supply voltage.
24. The power management circuit for an SRAM device as claimed in claim 23, wherein said first switch mechanism and said voltage clamp device are responsive to a low power mode control signal for initiating said lower power mode.
25. The power management circuit for an SRAM device as claimed in claim 23, wherein said voltage clamp device includes a high-threshold voltage MOS transistor device having a threshold voltage ranging anywhere from about 0.6 V to 1 V.
26. The power management circuit for an SRAM device as claimed in claim 23, wherein said first switch device is a low-threshold voltage MOS transistor device having a threshold voltage ranging anywhere from about 0.3 to 0.6V.


text:
2 area men killed in I-495 accident
TELEGRAM & GAZETTE STAFF
Aug 26, 2009 at 12:23 PM Aug 26, 2009 at 5:31 PM
Two men were killed and two were injured this morning in a multi-vehicle crash that tied up traffic on Interstate 495 for several hours.
The crash occurred about 6:30 a.m. in the northbound lanes of I-495, near the Boston Road interchange.
Four vehicles were involved in the accident.
Preliminary investigation by state police indicates that a Honda CRV driven by Henry X. O'Brien III, 40, of Templeton, was traveling south when it was rear-ended by a Chevrolet Malibu driven by John J. Cousineau, 21, of Worcester. The Honda veered to the left, crossed the median, and collided with a northbound Dodge Caravan driven by Joseph P. Dainis Sr., 40, of Leicester.
The Honda was then hit by a northbound tractor-trailer driven by Joseph Poirier, 48, of Hopedale.
The Honda rolled over and came to a rest in the median.
Mr. O'Brien and his passenger in the Honda, Gregory E. Butler, 46, of Fitchburg, were killed in the accident.
Mr. Cousineau and Mr. Dainis were taken by ambulance to area hospitals, where they were treated for minor injuries, police said. Both men wore seat belts. It is not known if the other victims were wearing seat belts.
All three lanes of I-495 north and the left lane of I-495 south were closed for three hours.

redpajama_set_name: RedPajamaCommonCrawl


text:
Healthy and confident, jock Alex Cintron riding hot streak
by Doug McCoy | Jun 20, 2019 | Breaking, DE Racing, Delaware, Features, Top Stories
Alex Cintron and Please Flatter Me won the Alma North Stakes. Photo by Laurie Asseo.
Jockey Alex Cintron's career has been one full of ups, downs, and unexpected turns.
His talent has never been in question. But throughout his career Cintron has had the misfortune to go down in spills just when he was riding at peak form. Six times over the past 11 years the rider has been forced to the sidelines to recover from injuries that have ranged from a broken shoulder to multiple fractures of his facial bones. Often the recovery period was long and painful, but time and time again Cintron, with strong support from his family, has managed to come back and return to the saddle.
He returned to riding in late May last season and had a respectable season once back, registering over $2.3 million in purse earnings, but he won only 14 percent of his starts.
So some six weeks ago, after starting 2019 somewhat slowly, Cintron split with his long time agent, Mark Mace, and retained veteran Tom Stift handle his engagements. Stift, who also handles former Eclipse Award winner as top apprentice Victor Carrasco, got Cintron into some new barns for new trainers and his business took off.
Cintron has won 30 races since the beginning of May – giving him 41 victories thus far in '19 — including a pair of stakes, and he has ridden multiple winners for top trainers like Michael Trombetta, Claudio Gonzales, Tom Ianotti, and Gary Capuano. He's winning at a sizzling 26.5 percent clip since May 1.
In short, Cintron is in the zone.
"Mark [Mace] and I had been together for more than 8 years and we had a good run," the rider said. "He (Mace) had stuck with me through the periods when I was injured and on the sideline, which I appreciated, but this year I was healthy and wanted very badly to show people that Alex was back, that I still had what it takes to win races and be successful. Business had not been that good early in the year, and things just weren't clicking."
His last half-dozen stakes mounts have come for six different trainers. That includes wins in the Alma North Stakes aboard Please Flatter Me for conditioner Mark Reid and in the Get Serious Stakes on Wet Your Whistle for Mike Trombetta.
"You know, every agent has certain trainers and stables they have relationships with, and I just felt moving to another agent I would get a chance to ride for some new outfits and outfits with horses that were capable of competing and winning," Cintron said. "I had watched how Tom handled his business and was impressed."
Cintron said he'd known Stift for some time, and, after checking in with Carrasco to be sure there would be no friction between the riders, Cintron made the move.
"I wish Mark all the best, but I feel like this is my second chance to make my mark and make a statement about my riding," the rider said. "I want to show everyone that I'm back, I'm healthy and I'm ready and able to compete with anybody."
With the change has come a new kind of energy, the confidence begat by success.
"Right now I'm riding with so much confidence, I'm so relaxed and self-assured when I go to the gate, and I feel like I have a chance to win with every horse I ride," Cintron revealed. "And the horses sense this, they feel it in your hands and in your actions and they respond by giving you all they've got. It's a great feeling, I hope it lasts a long time."
Cintron currently leads all Delaware Park by Thoroughbred wins and is tied for third in limited action at Laurel Park.
One of the things Cintron was committed to doing this year was concentrating his riding at Delaware Park. He lives less than five minutes from the track with his wife Carmen Reyes and four children, Alana, age five, Mikaela, age six, Yalexa, age 14 and his godson Yatniel, age 17.
The rider says being just minutes from home makes a big difference in keeping fresh and rested.
"It's nice not to spend half of every day driving to and from tracks," he said. "Now I can be home with the family, enjoy the time together and be sharp and ready to go the next morning. And the kids love to come out and watch me ride."
Speaking of the kids, Cintron's next mission will be teaching Yatniel to be a jockey.
"He wants to follow in my footsteps," the rider said. "He's seen the good parts of riding and the bad parts, like the injuries, but he's committed to being a rider, so it's up to me to do all I can to teach him the ropes, show him how to be a professional, and most importantly, how to ride safe and stay away from situations where he's going to get hurt."
PreviousDelaware Park 2019 horses to watch: June 20
NextBigger Picture hopes to frame 2nd U.N. victory
Doug McCoy has been a racing writer and chartcaller since 1972. He retired in late 2013 after 23 years (and 150 Grade 1 charts called) with Equibase and continues to write for the The Racing Biz and The Blood-Horse.
Chromatic Lass on the ascent


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Callers are for the most part creatures of habit, and many do not make use of relationship type boxes to their full potential. I call them GROUP-TYPE Boxes, and by the term "box," I mean the 8-Chain Thru Formation. A call that naturally goes with the Standard 8 Chain Thru formation is curiously enough, 8-Chain Thru or 8-Chain <N>. There's a Get-out in that call for ANY GROUP-TYPE Box. Let's take a look.
To see the complete article, click on the icon below.


Join us for a 'Easter Special' Children's Film Club screening of The Lego Movie 2 with children's party specialists, Sharky & George.
Parents can choose to leave their children with the expert team and enjoy a leisurely Sunday brunch in Refuel Restaurant. Meanwhile the team at Sharky & George will keep children entertained with Easter activities.
After the activities, a buffet brunch and drinks will be provided followed by a special children's screening of The Lego Movie 2 starring Chris Pratt and Elizabeth Banks. Parents can choose to join their children for the movie or come to pick them up following the film as it will be supervised by the team.
Please note that £10 film tickets are only available for accompanied children.
** Please also note that children under four must be accompanied by an adult for the entire duration.


From 2010 to 2013 Tom worked on the staff of the Dutch Delta Commissioner. This special high-level government official had been appointed in 2010 to help guard progress and coherence of the Netherlands National Delta Programme (www.deltacommissaris.nl).
The Delta Programme has two objectives: to keep the Netherlands safe from flooding (both from the sea and from rivers) and keep it supplied with fresh water of sufficient quality, now and towards the end of the century, taking climate change into account. The Programme operates on the basis of a special law and has a dedicated budget of around €1B/yr.
At first Tom acted as the Commissioner's liaison officer with three of the sub programmes (coastal, Wadden Sea, and spatial adaptation) and later he worked on international contacts and innovation.
The Delta Programme focuses on increasing resilience over the long-term, avoidance of lock-in, incremental steps along adaptive pathways as essential aspects to deal with the inherent uncertainty of climate change impacts. It also introduced a water safety system based on an assessment of individuals' risk, group risk and cost-benefits to calculate the investments needed in order to maintain appropriate safety levels for the country.
From 2013 onwards, Tom has been working with the Vietnamese Government on the application of similar concepts to the Vietnamese Mekong Delta.
John Church is a Professor in the Climate Change Research Centre, University of New South Wales.
He has published across a broad range of topics in oceanography. His area of expertise is the role of the ocean in climate, particularly anthropogenic climate change. He is an expert in estimating and understanding global and regional sea-level rise.
He is the author of over 150 refereed publications, over 100 other reports and co-edited three books. He was co-convening lead author for the Chapter on Sea Level in the IPCC Third and Fifth Assessment Reports. He was awarded the 2006 Roger Revelle Medal by the Intergovernmental Oceanographic Commission, a CSIRO Medal for Research Achievement in 2006, the 2007 Eureka Prize for Scientific Research, the 2008 AMOS R.H. Clarke Lecture and the AMOS Morton Medal in 2017.
He is a Fellow of the Australian Academy of Science, the Australian Academy of Technological Sciences and Engineering and the American Meteorological Society.
Dr. Nathan Quadros completed his PhD at The University of Melbourne in 2008 investigating the use of 3D laser scanning (LiDAR) in the coastal zone.
For the next few years he managed the acquisition, delivery and quality assurance of large LiDAR projects for the Victorian Government, including the topographic and bathymetric acquisition for the Future Coasts team.
In 2011 Nathan moved to the Cooperative Research Centre for Spatial Information (CRCSI) where he now manages the Rapid Spatial Analytics research program. Nathan is an expert in LiDAR acquisition and its applications, having led research projects in quality assurance, feature extraction and web tool development.
In the past year Nathan has been involved in developing the publicly available Coastal Risk websites for Australia, Vanuatu and Tonga. These websites dynamically present maps on sea level rise using Google Earth Engine.
Recently, Nathan spoke at COP21 in Paris after winning a United Nations award for sea level rise planning in the Pacific Islands.
As General Manager for the Policy, Risk and Disaster Planning Directorate, Karl is responsible for the facilitation of industry policy and initiatives regarding emerging risks as well as coordinating the industries response and partnership with government following a significant disaster event.
Karl brings with him significant experience in the disaster planning and risk management field. Prior to joining the Insurance Council, Karl was responsible for global Disaster Planning, Response and Mitigation for the Qantas Group of Companies. In conjunction with that role, Karl was active in international and domestic forums focused on a wide range of disaster events and emerging risks.
Prior to Qantas, Karl enjoyed a career in the Royal Australian Air Force, including several operational flying tours and appointments responsible for consequence management and disaster planning.


Our new clinical trials database will help you look for a clinical trial that might be suitable for you. We hope this helps you to make informed decisions and choices about your lymphoma treatment and care.
Questions about Lymphoma TrialsLink and how to use it? Read more about Lymphoma TrialsLink or if you can't find the answer please contact us at trialslink@lymphoma-action.org.uk.


If the situation didn't already look dire enough after their atrocious appearance at the World Cup, England will probably consider quitting cricket after Australia's 17 man squad for this year's Ashes series was named this week.
The England Cricket Board appeared to have built a team capable of competing as recently as 18 months ago but after the humiliation of backing themselves for a 5-0 whitewash only to have that prediction turned around and firmly thrust upon them over the 2013/14 summer, the Pommies have receded back to what I like to call "Classic England" – poor bowling, even worse batting and more in-fighting than the One Direction fan club.
Peter Siddle has been Australia's go-to in lean periods of late but even he looks like missing out on a first XI spot to the likes of Mitchell Johnson, Ryan Harris and the World Cup's best player Mitchell Starc; all named in the Ashes squad along with spinners Nathan Lyon and Fawad Ahmed.
So who do the soap dodgers pick to face such a potent pace attack?
There's been a lot made of Kevin Pietersen's exile from the national team over the last 12 months and many are calling for his reinstatement ahead of the Ashes. Several times this part-time South African has been brought into the fold only to be dumped again and nothing ever changes. If Pietersen was even half as good at holding his wicket as he is at picking twitter fights from the safety of a keyboard, then maybe the Aussies would face some resistance.
How about Gary Ballance? He was brought in to help save England the last time they faced Australia, and that went well! So poor has his form been, the 'Yorkshireman' who is actually from Zimbabwe would be hard pressed getting a run for the Harare Mugabes.
Ian Bell. Now there's a batsman you can set your watch to. Even as an Australian it's hard not to appreciate the grace of Ed Sheeran's doppelganger with a big piece of willow in hand but it would not surprise me if he finishes every English innings not out on 20 as the other ten blokes get out around him.
Michael Clarke retired from 50 over cricket after the World Cup win to extend his test career, as injuries have been more frequent and severe in recent seasons.
Pup is sure to lead from the front an impressive Australian batting line-up boasting firepower from the likes of David Warner and Brad Haddin, calm stroke play from Chris Rogers and creativity from Steve Smith.
The once fearsome bowling of James Anderson and Stuart Broad has diminished, the lack of a world-class spinner is apparent and Australia could probably pick players from the Don's last tour and post a defendable score as a result.
If I had it my way, we'd play the Kiwis at Lords, Old Trafford, the Oval and Trent Bridge and say it was England. That way, a five day match might be completed.


The girl from the Netherlands with those eyebrows we're forever coveting – meet this week's model muse.
From Christian Dior's navy dream to No.21's subtle embroidery – AW 17 kept cool with sheer overlay dresses. I see you.


text:
namespace impala {

class BufferedTupleStream;
template <typename K, typename V> class FixedSizeHashTable;
class MemTracker;
class RowBatchSerializeTest;
class TRowBatch;
class Tuple;
class TupleRow;
class TupleDescriptor;

/// A RowBatch encapsulates a batch of rows, each composed of a number of tuples.
/// The maximum number of rows is fixed at the time of construction.
/// The row batch reference a few different sources of memory.
///   1. TupleRow ptrs - may be malloc'd and owned by the RowBatch or allocated from
///      the tuple pool, depending on whether legacy joins and aggs are enabled.
///      See the comment on tuple_ptrs_ for more details.
///   2. Tuple memory - this is allocated (or transferred to) the row batches tuple pool.
///   3. Auxiliary tuple memory (e.g. string data) - this can either be stored externally
///      (don't copy strings) or from the tuple pool (strings are copied).  If external,
///      the data is in an io buffer that may not be attached to this row batch.  The
///      creator of that row batch has to make sure that the io buffer is not recycled
///      until all batches that reference the memory have been consumed.
/// In order to minimize memory allocations, RowBatches and TRowBatches that have been
/// serialized and sent over the wire should be reused (this prevents compression_scratch_
/// from being needlessly reallocated).
//
/// Row batches and memory usage: We attempt to stream row batches through the plan
/// tree without copying the data. This means that row batches are often not-compact
/// and reference memory outside of the row batch. This results in most row batches
/// having a very small memory footprint and in some row batches having a very large
/// one (it contains all the memory that other row batches are referencing). An example
/// is IoBuffers which are only attached to one row batch. Only when the row batch reaches
/// a blocking operator or the root of the fragment is the row batch memory freed.
/// This means that in some cases (e.g. very selective queries), we still need to
/// pass the row batch through the exec nodes (even if they have no rows) to trigger
/// memory deletion. AtCapacity() encapsulates the check that we are not accumulating
/// excessive memory.
//
/// A row batch is considered at capacity if all the rows are full or it has accumulated
/// auxiliary memory up to a soft cap. (See at_capacity_mem_usage_ comment).
class RowBatch {
 public:
  /// Create RowBatch for a maximum of 'capacity' rows of tuples specified
  /// by 'row_desc'.
  /// tracker cannot be NULL.
  RowBatch(const RowDescriptor& row_desc, int capacity, MemTracker* tracker);

  /// Populate a row batch from input_batch by copying input_batch's
  /// tuple_data into the row batch's mempool and converting all offsets
  /// in the data back into pointers.
  /// TODO: figure out how to transfer the data from input_batch to this RowBatch
  /// (so that we don't need to make yet another copy)
  RowBatch(const RowDescriptor& row_desc, const TRowBatch& input_batch,
      MemTracker* tracker);

  /// Releases all resources accumulated at this row batch.  This includes
  ///  - tuple_ptrs
  ///  - tuple mem pool data
  ///  - buffer handles from the io mgr
  ~RowBatch();

  static const int INVALID_ROW_INDEX = -1;

  /// Add n rows of tuple pointers after the last committed row and return its index.
  /// The rows are uninitialized and each tuple of the row must be set.
  /// Returns INVALID_ROW_INDEX if the row batch cannot fit n rows.
  /// Two consecutive AddRow() calls without a CommitLastRow() between them
  /// have the same effect as a single call.
  int AddRows(int n) {
    if (num_rows_ + n > capacity_) return INVALID_ROW_INDEX;
    has_in_flight_row_ = true;
    return num_rows_;
  }

  int AddRow() { return AddRows(1); }

  void CommitRows(int n) {
    DCHECK_GE(n, 0);
    DCHECK_LE(num_rows_ + n, capacity_);
    num_rows_ += n;
    has_in_flight_row_ = false;
  }

  void CommitLastRow() { CommitRows(1); }

  /// Set function can be used to reduce the number of rows in the batch.  This is only
  /// used in the limit case where more rows were added than necessary.
  void set_num_rows(int num_rows) {
    DCHECK_LE(num_rows, num_rows_);
    DCHECK_GE(num_rows, 0);
    num_rows_ = num_rows;
  }

  /// Returns true if the row batch has filled all the rows or has accumulated
  /// enough memory.
  bool AtCapacity() {
    return num_rows_ == capacity_ || auxiliary_mem_usage_ >= AT_CAPACITY_MEM_USAGE ||
      num_tuple_streams() > 0 || need_to_return_;
  }

  /// Returns true if the row batch has filled all the rows or has accumulated
  /// enough memory. tuple_pool is an intermediate memory pool containing tuple data
  /// that will eventually be attached to this row batch. We need to make sure
  /// the tuple pool does not accumulate excessive memory.
  bool AtCapacity(MemPool* tuple_pool) {
    DCHECK(tuple_pool != NULL);
    return AtCapacity() ||
        (tuple_pool->total_allocated_bytes() > AT_CAPACITY_MEM_USAGE && num_rows_ > 0);
  }

  TupleRow* GetRow(int row_idx) {
    DCHECK(tuple_ptrs_ != NULL);
    DCHECK_GE(row_idx, 0);
    DCHECK_LT(row_idx, num_rows_ + (has_in_flight_row_ ? 1 : 0));
    return reinterpret_cast<TupleRow*>(tuple_ptrs_ + row_idx * num_tuples_per_row_);
  }

  int row_byte_size() { return num_tuples_per_row_ * sizeof(Tuple*); }
  MemPool* tuple_data_pool() { return tuple_data_pool_.get(); }
  int num_io_buffers() const { return io_buffers_.size(); }
  int num_tuple_streams() const { return tuple_streams_.size(); }

  /// Resets the row batch, returning all resources it has accumulated.
  void Reset();

  /// Add io buffer to this row batch.
  void AddIoBuffer(DiskIoMgr::BufferDescriptor* buffer);

  /// Add tuple stream to this row batch. The row batch must call Close() on the stream
  /// when freeing resources.
  void AddTupleStream(BufferedTupleStream* stream);

  /// Returns true if 'stream' has been added to with batch, false otherwise.
  bool ContainsTupleStream(BufferedTupleStream* stream) const;

  /// Adds a block to this row batch. The block must be pinned. The blocks must be
  /// deleted when freeing resources.
  void AddBlock(BufferedBlockMgr::Block* block);

  /// Called to indicate this row batch must be returned up the operator tree.
  /// This is used to control memory management for streaming rows.
  /// TODO: consider using this mechanism instead of AddIoBuffer/AddTupleStream. This is
  /// the property we need rather than meticulously passing resources up so the operator
  /// tree.
  void MarkNeedToReturn() { need_to_return_ = true; }

  bool need_to_return() { return need_to_return_; }

  /// Transfer ownership of resources to dest.  This includes tuple data in mem
  /// pool and io buffers.
  void TransferResourceOwnership(RowBatch* dest);

  void CopyRow(TupleRow* src, TupleRow* dest) {
    memcpy(dest, src, num_tuples_per_row_ * sizeof(Tuple*));
  }

  /// Copy 'num_rows' rows from 'src' to 'dest' within the batch. Useful for exec
  /// nodes that skip an offset and copied more than necessary.
  void CopyRows(int dest, int src, int num_rows) {
    DCHECK_LE(dest, src);
    DCHECK_LE(src + num_rows, capacity_);
    memmove(tuple_ptrs_ + num_tuples_per_row_ * dest,
        tuple_ptrs_ + num_tuples_per_row_ * src,
        num_rows * num_tuples_per_row_ * sizeof(Tuple*));
  }

  void ClearRow(TupleRow* row) {
    memset(row, 0, num_tuples_per_row_ * sizeof(Tuple*));
  }

  /// Acquires state from the 'src' row batch into this row batch. This includes all IO
  /// buffers and tuple data.
  /// This row batch must be empty and have the same row descriptor as the src batch.
  /// This is used for scan nodes which produce RowBatches asynchronously.  Typically,
  /// an ExecNode is handed a row batch to populate (pull model) but ScanNodes have
  /// multiple threads which push row batches.
  /// TODO: this is wasteful and makes a copy that's unnecessary.  Think about cleaning
  /// this up.
  /// TOOD: rename this or unify with TransferResourceOwnership()
  void AcquireState(RowBatch* src);

  /// Deep copy all rows this row batch into dst, using memory allocated from
  /// dst's tuple_data_pool_. Only valid when dst is empty.
  /// TODO: the current implementation of deep copy can produce an oversized
  /// row batch if there are duplicate tuples in this row batch.
  void DeepCopyTo(RowBatch* dst);

  /// Create a serialized version of this row batch in output_batch, attaching all of the
  /// data it references to output_batch.tuple_data. This function attempts to
  /// detect duplicate tuples in the row batch to reduce the serialized size.
  /// output_batch.tuple_data will be snappy-compressed unless the compressed data is
  /// larger than the uncompressed data. Use output_batch.is_compressed to determine
  /// whether tuple_data is compressed. If an in-flight row is present in this row batch,
  /// it is ignored. This function does not Reset().
  Status Serialize(TRowBatch* output_batch);

  /// Utility function: returns total size of batch.
  static int GetBatchSize(const TRowBatch& batch);

  int num_rows() const { return num_rows_; }
  int capacity() const { return capacity_; }

  const RowDescriptor& row_desc() const { return row_desc_; }

  /// Max memory that this row batch can accumulate in tuple_data_pool_ before it
  /// is considered at capacity.
  static const int AT_CAPACITY_MEM_USAGE;

  /// Computes the maximum size needed to store tuple data for this row batch.
  int MaxTupleBufferSize();

 private:
  friend class RowBatchSerializeBaseline;
  friend class RowBatchSerializeBenchmark;
  friend class RowBatchSerializeTest;

  /// Decide whether to do full tuple deduplication based on row composition. Full
  /// deduplication is enabled only when there is risk of the serialized size being
  /// much larger than in-memory size due to non-adjacent duplicate tuples.
  bool UseFullDedup();

  /// Overload for testing that allows the test to force the deduplication level.
  Status Serialize(TRowBatch* output_batch, bool full_dedup);

  typedef FixedSizeHashTable<Tuple*, int> DedupMap;

  /// The total size of all data represented in this row batch (tuples and referenced
  /// string and collection data). This is the size of the row batch after removing all
  /// gaps in the auxiliary and deduplicated tuples (i.e. the smallest footprint for the
  /// row batch). If the distinct_tuples argument is non-null, full deduplication is
  /// enabled. The distinct_tuples map must be empty.
  int64_t TotalByteSize(DedupMap* distinct_tuples);

  void SerializeInternal(int64_t size, DedupMap* distinct_tuples,
      TRowBatch* output_batch);

  MemTracker* mem_tracker_;  // not owned

  /// All members below need to be handled in RowBatch::AcquireState()

  bool has_in_flight_row_;  // if true, last row hasn't been committed yet
  int num_rows_;  // # of committed rows
  int capacity_;  // maximum # of rows

  int num_tuples_per_row_;
  RowDescriptor row_desc_;

  /// Array of pointers with capacity_ * num_tuples_per_row_ elements.
  /// The memory ownership depends on whether legacy joins and aggs are enabled.
  ///
  /// Memory is malloc'd and owned by RowBatch:
  /// If enable_partitioned_hash_join=true and enable_partitioned_aggregation=true
  /// then the memory is owned by this RowBatch and is freed upon its destruction.
  /// This mode is more performant especially with SubplanNodes in the ExecNode tree
  /// because the tuple pointers are not transferred and do not have to be re-created
  /// in every Reset().
  ///
  /// Memory is allocated from MemPool:
  /// Otherwise, the memory is allocated from tuple_data_pool_. As a result, the
  /// pointer memory is transferred just like tuple data, and must be re-created
  /// in Reset(). This mode is required for the legacy join and agg which rely on
  /// the tuple pointers being allocated from the tuple_data_pool_, so they can
  /// acquire ownership of the tuple pointers.
  Tuple** tuple_ptrs_;
  int tuple_ptrs_size_;

  /// Sum of all auxiliary bytes. This includes IoBuffers and memory from
  /// TransferResourceOwnership().
  int64_t auxiliary_mem_usage_;

  /// If true, this batch is considered at capacity. This is explicitly set by streaming
  /// components that return rows via row batches.
  bool need_to_return_;

  /// holding (some of the) data referenced by rows
  boost::scoped_ptr<MemPool> tuple_data_pool_;

  /// IO buffers current owned by this row batch. Ownership of IO buffers transfer
  /// between row batches. Any IO buffer will be owned by at most one row batch
  /// (i.e. they are not ref counted) so most row batches don't own any.
  std::vector<DiskIoMgr::BufferDescriptor*> io_buffers_;

  /// Tuple streams currently owned by this row batch.
  std::vector<BufferedTupleStream*> tuple_streams_;

  /// Blocks attached to this row batch. The underlying memory and block manager client
  /// are owned by the BufferedBlockMgr.
  std::vector<BufferedBlockMgr::Block*> blocks_;

  /// String to write compressed tuple data to in Serialize().
  /// This is a string so we can swap() with the string in the TRowBatch we're serializing
  /// to (we don't compress directly into the TRowBatch in case the compressed data is
  /// longer than the uncompressed data). Swapping avoids copying data to the TRowBatch and
  /// avoids excess memory allocations: since we reuse RowBatchs and TRowBatchs, and
  /// assuming all row batches are roughly the same size, all strings will eventually be
  /// allocated to the right size.
  std::string compression_scratch_;
};

}

#endif

redpajama_set_name: RedPajamaGithub


Cloud Computing – What Happens When your Favored Services is Acquired Out?
Cloud computing may be the idea of employing web applications to Savannah Computer Service work with and store facts. It is straightforward determined by the concept you can obtain your information and programs from any browser owning your data files readily available any where you need them to become. You can find massive ease, but what takes place in the event your assistance is purchased out by an additional firm?
Regardless that this is a reasonably new plan, cloud computing products and services have by now been purchased out by greater corporations. 3 points are going on with obtain outs. You would like to be aware of what can take place to the solutions that you are currently working with.
The primary is the fact the assistance is acquired out then discontinued. This transpires when a business contains a competing product or service and purchases out their competitor. In essence, every thing you have can get locked out and be erased.
The second is the corporation buys out the services to incorporate it as element in their latest solutions. Firms like Google have completed this and also social sites like Facebook. A thing is well-liked over the internet so these massive companies obtain them up and make them available for their people.
The 3rd is often a transitional type of a invest in out. This means that your data will probably be offered as is for a specific variety of weeks and following that will probably be migrated for the new services should you wish.
In all these instances you require to concentrate on two matters.
Initially, if it is about the cloud, back again it up. You never really know what will happen in your services. If it can be with your machine, you don't need to worry about it.
Second, be aware of migration sort companies that could enable you to alter from one particular company to another. Make this happen currently to ensure that if an announcement of the purchase out is built tomorrow, you already know who to drop by.
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Below you may find the In the movie 2001 Dr. Dave Bowman asks this character to Open the pod bay doors which is part of the Jeopardy Archive. In case the question or answer is wrong or something is missing do not hesitate to contact us and we will be glad to help you out. If you are looking for our Jeopardy Finder you can access it here.


Shared Responsibility: Is it in the Children's Best Interest?
Shared parental responsibility — not to be confused with shared custody — means that, after a divorce, both parents retain the right to make decisions regarding the children. This includes decisions about everything from after-school activities to what orthodontist the children go to. Shared child custody is a different issue, referring to the time children spend with each parent. Shared custody is not necessary to have shared parenting.
At the law firm of Anne E. Raduns, PA, we can help you determine if shared parental responsibility makes sense for you and your children, or if sole parental responsibility is necessary.
In most situations, we encourage shared parental responsibility. We feel that divorce can do too much damage to children on its own. That damage would only be increased if one parent were to disappear from the children's lives. Both parents need to have a positive relationship with the children, and that can be achieved through shared parental responsibility.
Even if one parent ends up being the primary residential parent, spending more time with the children, the non-custodial parent can still have equal decision-making powers.
Unfortunately, shared parental responsibility doesn't make sense in every situation. If one parent has a history of violence, drug use, crime, neglect or anything else that could put children at risk, that parent should not necessarily have any say in making decisions for the children. Our goal is to see that shared parental responsibility is only used when it will benefit the children.
Contact our attorneys today for a free low cost case evaluation!


I agree 100% Cardassians are cool because they are so thoroughly awesome.
Someone's into spoonheads. =p Federation-Cardassian war could be used to make a movie, I guess. Altough, Maquis and their fight against the Cardassian oppressors would work too.
I agree, they're such great and interesting characters. Romulans are too, but they've been used too much recently.
A DS9 film, or rather, one done by the same writers (dosen't have to be DS9 set, but, Cardassians and stuff?) would be awesome.
Considering the alternate universe canon we now have, the Cardassians can become whatever they want.
Honestly, I wouldn't mind seeing a Star Trek: Cardassia film - an entire film seen from a Cardassian point of view. Show the traditional Starfleet guys as the 'baddies' while the brave Cardassians fight gloriously for the union.
That would be great because you could go way over the top with the script because the Cardies are so caricature-like. Much funny awesomeness.
I think that would be a fresh view on the Star Trek universe and, actually, Cardassians are multi-layered and they've never been straight "bad" or "good" guys, they have their own weird sense of right and wrong and justice. You could even argue that in many ways Gul Dukat had qualities of a decent person.
I'd very much like to see a feature film which involves Cardassians, though I don't see that happening if I were honest with you.
I think the whole 'typical' Trek timeline is finished with, so any hope of working on something during the Cardassian-Federation war, or anything revolving DS9 just wouldn't work anymore. Nobody is going to be interested enough for them to warrant such a film, especially as that area of Trek has practically finished up now. From what I'm aware, whatever lose ends they've got, they're taking into STO.
The only think I think they can do, is introduce them in the JJverse, though I'm not sure they'll belong in a Kirk-based era. I'm not even sure if they're known by then, though I suppose anything is possible with the AR, but again, a little too early? I don't know.
If they do use them (in a JJ film) I think they should be a sub-plot, there should be a ship full, or small group, and Kirk (etc) wouldn't know whether to trust them until right at the end of the movie or something.
Give them that edge, never knowing whether they're good or bad. Could be interesting.
Uhura ordered a Cardassian Sunrise in the last film, so, they're there. They could turn up, I think, as something new but still Cardassian. Anything is now possible?
FileTrekker;5385609Uhura ordered a Cardassian Sunrise in the last film, so, they're there. They could turn up, I think, as something new but still Cardassian. Anything is now possible?[/quote]Whilst possible, it is more likely the ingredients were purchased from another bar, on another planet, where the Cardassians had been. You're probably right though, they'd have probably been introduced in the new Kirk era. Kirk and co didn't think too much of the Romulans being around, taking into account that the TOS Kirk and crew did.
[QUOTE=FileTrekker;5385609]If they had any sense about them, they'd see their potential as characters and give them a sequel.
They could make a movie in two parts.. Like clint eastwood did with iwo jima.
You take a huge battle like the one we saw in sacrifice of angels? First movie is on board of a federation ship (no familiar one, just one of the backgrounds) And you see the crew fighting their way through the cardassian fleet. They describe the cardassians as dogs, cardies, spoonheads etc. The movie ends that the persons you get to know on the fed ship, you have a connection with, almost all die and only or two persons survive on the bridge or of the group. You see them looking at the screen or a window and the cardassian fleet is in huge shambles and the remaining forces are hunting them down.Actually like a war movie.
While the second part is on the cardassian side. You see them drinking at quarks, quite shivering from the fact that the federation is leaving with only 600 ships to fight at them. That they realize that humans are actually dangerous and aggressive. Not the propaganda that they hear from the leaders. Later they are in the fleet, also somewhere in the background, and the same thing happens. And you realize that both factions are actually the same and don't want war, only the big called leaders. It would be even cool that you see their ship getting phaser strikes from the fed ship in the other part..


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Exploring the joys and challenges of raising boys
Parenting	by Michael Grose October 11. 2016
How to raise a 'giver'
Young children are egocentric by nature. As any 3-year old knows only too well the world revolves around them. "I want…" "Give me…" "It's mine!" and other variations are the mantras for this age group. This self-centredness is developmental, which means it's something they grow out of… or they're supposed to.
But some kids never bridge the gap from self-centredness to generosity. They become takers with an inflated sense of entitlement rather than givers who do all they can to accommodate the needs of others. While it can be argued that some children are maybe self-centred by temperament I'm not convinced that we can blame Mother Nature entirely. There is no doubt that parenting impacts enormously on a child's propensity to give rather than take.
In the eagerness to get kids off to a good start in life, a spirit of generosity is one quality that parents can easily overlook. Developing children's personal competencies tend to be higher on most parents' wish lists for their kids than developing a generous spirit.
But developing a sense of sharing in kids has plenty of positives. Children who are able to share their time, their space and themselves generally have more friends and experience more success than those who are self-centred and mean-spirited. Quite simply, they are leadership material!
Like most facets of child rearing developing a community ethos in kids' can be a frustrating task but perseverance, modeling and expectations are parents' greatest allies when it comes to things that really matter.
Here are 5 practical ways to develop a sense of generosity in kids:
Expect kids to help
With families shrinking, kids get fewer opportunities to help at home than before. With this in mind expect your kids to help without being paid. Regular chores and activities that benefit others such as setting the meal table or helping a younger sibling get dressed teaches them that their contribution is valuable and very much required.
Think 'gang'
It's a quirk of modern life that parenting is an individual endeavour. "What's in the best interest of my child?" has replaced "What's in the best interest of the family?" as a key parenting principle. Encourage children to make allowances for each other which may mean everyone watches a sibling's special concert rather than some children missing it because 'it's boring!' 'We put ourselves out for each other' is a wonderful family strength that often needs to be reinforced by parents.
Don't let them get away with meanness
Children wear L-plates when it comes to behaving generously. They don't always get it right, which means that parents as the wise adults need to remind children when their words and actions are intolerant or mean-spirited, or when they need to put their own needs behind the needs of others.
Develop a sense of other
Children and teenagers don't live in a bubble. The socialisation process demands that kids be accountable for their poor behaviours. "What does this social situation reasonably require of my child at his or her age and stage of development?" is a great question to ask yourself to develop a sense of other, rather than entitlement in kids.
Encourage giving
During the Victorian bushfires a few years ago I heard the story of a 9-year old whose mum went into his bedroom to growl at him for being up too late. She found him busy emptying his moneybox into little plastic bags, ready to donate at the school bushfire appeal next day. There were plenty of stories like this showing the generosity of Australian kids, we just need to encourage them in everyday life, rather than wait for a tragedy, to give their generosity a kick start. You can begin by encouraging them to give toys, books and clothes away when they have finished with them, or doing a good deed by a neighbour or friend.
The skills that kids need for future success are changing as technology, greater flexibility and mobility, and new economic forces are transforming workplaces at an astonishingly rapid rate. But the basic attitudes and character traits needed to succeed such as teamwork, initiative and generosity haven't changed too much over time. Ask any employer and I'm sure they'd say they'd hire a giver over a taker any day as they are just so valuable to have on a team. Hopefully they are not becoming a rarity as well!
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Michael Grose is an Australian parenting educator, father, author, speaker and founder of www.parentingideas.com.au	This article is about Parenting
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Hawks Ultimate Club
Info on our (typical) Spring Program
Player Status
Teams - Spring 2015
Spring Reign 2015
Fall 2015 - Welcome
About Our Fall Program >
Hawks Ultimate at Hamilton International Middle School
Fall Leagues Postponed for 2020/2021 Season
DiscNW has partnered with Seattle Public Schools and other league coordinators to adapt our normal Fall School League calendar to the realities of COVID-19 and to ensure that teams get the support from schools and parks departments as much as possible. Use the link below to see the proposed dates for DiscNW Middle School Ultimate programs for the upcoming 2020 / 2021 school year. These dates are subject to change depending on the status of King County public health conditions or input from WIAA and Seattle Public Schools.
Find out more here at DiscNW: Fall Public Middle School League
General Hawks Info for Typical Season:
Welcome to Hamilton Hawks Ultimate!
This website will be your primary source of information about the ultimate program at Hamilton International Middle School (HIMS). Please bookmark this site, come back often, and use it as a reference for information regarding ultimate at HIMS.
Fall Ultimate at HIMS is a sanctioned sport run by the Seattle Public Schools and governed by the policies of the Seattle Public Schools, Hamilton International Middle School, DiscNW, and the Hawks Ultimate Club. The fall league is administered and scheduled by DiscNW.
Acceptance into Hawks Program
We are all very excited about the Ultimate program here at HIMS. It's been a great success! But we are overwhelmed by its popularity. It's heartbreaking to exclude any kids, but we don't have enough practice field space or coaches to accommodate everyone. We've come to understand that a team with too many players creates a difficult and frustrating environment. Play time becomes very limited, in practices and especially in games, and it can be a very frustrating experience for players and coaches. Because of this we have instituted a program size cap in order to improve the experience of participating players. We do everything we can to accommodate as many players as possible
with our limited resources.
Team Numbers Cap
We will have a target of 21 players per team.
All teams will be co-ed and will balance genders so as to adhere to the standard established by DiscNW for all youth leagues:
DiscNW's gender maximum rule requires each team to play each point with no more than four players who identify as the same gender. If you cannot do so, you will have to play down unless otherwise discussed with your opponent according to the Captain's Clause.
The gender a player identifies with is considered that player's gender. Please refer to DiscNW's Gender Inclusion Policy for more information.
We intend to field five teams this season. With more coaches and practice field space, we may be able to field six teams.
Acceptance Criteria
Ultimate prides itself on its focus on community and "Spirit of the Game". We will always put our greatest emphasis on sportsmanship, inclusion, community, and a commitment to learning the game and becoming a better player and teammate while adhering to these principles. We will accept players into the program based on their commitment to the sport and their teammates, their citizenship and contribution to the "Spirit of the Game". Game and disc skills will also be a contributing factor in acceptance into the program. We will rank players based on basic disc skills, quickness and speed, field awareness, experience, and knowledge of the game.
Below is our list of Acceptance Criteria. This list is in our primary order of preference.
Commitment to "Spirit of the Game", our ultimate community, and being a good citizen and teammate.
Participation and Availability
All players are expected to participate in all practices and all games, though a very limited number of excused absences is acceptable.
If you think your child may need to miss practices because of other commitments, then please consider withdrawing your registration for the Fall and try again in the Spring, or explore some of the other options listed below.
We will attempt to accommodate players/family schedules regarding team placement, but not at the expense of other players who meet or exceed the above criteria. While we will ask parents for a preferred day to practice, we offer no guarantee that we can place your child on a team on your preferred day.
Skills and Knowledge of the Game. Players will be rated based on:
Willingness to learn and accept instruction.
Field awareness and player safety.
Disc skills.
Speed, quickness, and general athletic ability or aptitude.
Knowledge of the game, including rules, terms, and offensive and defensive strategy.
Experience with the game of ultimate or other field sports
and... WE NEED MORE GIRLS!
More Information about the Fall Ultimate Program
From the HIMS website: Player eligibility will be based on a 2.0 average for all classes with no more than one core subject (math, reading, writing, social studies, or science) having a sub-2.0 grade at any time.
HIMS automatically assesses player eligibility on a weekly basis. The school athletic director will notify any players who are not meeting criteria and their coaches. Students who are not academically eligible cannot play in games that week, but can still participate in practice. Hamilton school staff will work with those students to set up an academic plan to get back on track.
For the most part, we are very lucky to have a crew of dedicated and respectful players, but sometimes middle schoolers will be middle schoolers. When those actions are repeatedly causing disruptions that prevent their teammates from participating and improving, coaches have to take action beyond the typical corrections (e.g., pay attention, extra laps).
Hamilton Ultimate follows a two warning policy. Repeated interruptions will be followed by a one-on-one discussion with coaches and the player, where we will explain specifically what the player needs to improve. That is their first warning. If the behavior continues, a discussion between coaches and the player's parents is the second warning. Finally if the behavior persists, the player will be cut from the team. Players were told about this at their first practice, but wanted to make sure parents are aware of policy. It is rare that we get to even the second warning.
PE Waivers
Students who do not enroll in a PE class at HIMS are required to complete at least 60 hours of organized athletic activity during the school year. Students are required to submit a PE Waiver to the HIMS Office, stating their plan for organized athletic activity.
More info about the PE Waiver at HIMS (will update when the 2019 page is out)
PE Waiver forms are obtained from and submitted to the HIMS Office.
Do not to submit PE Waiver forms to athletic coaches.
All families who need a PE Waiver are required to submit the PE Waiver form.
For students participating in school sports, a separate cover letter from the coach/team is not required. Each school athletic program will submit the entire roster, along with verification of participation and number of hours.
Estimated PE Waiver hours: 50 hours.
Players are responsible for getting themselves to and from practice. For practices at Green Lake playfields, players can take the public bus or bike – more information will be provided prior to the first practice...
Players must have their own transportation to games.
If we can, we will enlist a parent to organize a game-day carpool system.
If you would like to be our Carpool Coordinator, please email us at hamiltonhawksultimate@gmail.com.
Fall Drizzle: This is a one-day middle school tournament held in early Nov. More details as they are announced.
Equipment / Jerseys
Footwear: Soccer or football cleats are highly recommended.
Clothing: Shorts or athletic pants, a synthetic athletic shirt, and warm/rain layers.
Jerseys: Players will be provided a Hamilton Ultimate jersey. These are the property of HIMS and must be returned at the end of the season.
Players who own a Hamilton Ultimate jersey from a previous season may use that jersey.
Remember: Players may not participate in tryouts, practices, or games until all SPS Athletic Registration requirements are submitted to the HIMS Office and approved!
If you have any questions, please email us at hamiltonhawksultimate@gmail.com


Around a quarter to a third of schoolchildren are overweight or obese according to a House of Commons report. These alarming figures have led governments to introduce policies to get children fitter and healthier, such as a sugar tax on soft drinks and restrictions on the promotion of sugary, fatty foods.
This may be great on a national basis but what should you do if your own child is overweight? Is it best to raise the topic and risk hurting their feelings, or should you ignore your child's expanding waistline but worry in silence about their future health and well-being?
What do we mean by overweight?
Children are not little adults because they are still growing and developing. This means that their weight, shape and size can change drastically by the time they leave school. Because of this, we measure 'weight for height' as an age-dependent percentile (a way of comparing individual children to a healthy national average). You can check out your child's percentile in the growth chart book you received when your child was born. Otherwise, you can find charts on the internet.
Children are at risk of being overweight if their body mass index (a ratio of weight for height) is on or above the 85th percentile for their age. Being on the 85th percentile means they're bigger than 85% of the children they're being compared to. They are at risk of becoming obese (one stage on from overweight) if their body mass index is on or above the 95th percentile.
Why should we be concerned about weight?
While some children will simply grow out of chubbiness or 'puppy fat', many don't and this can lead to problems later on.
Overweight and obese children may feel breathless, have difficulty taking part in sport and games, and experience bullying or teasing due to their size. Obese girls can reach puberty earlier and have to deal with periods at as young as 8 or 9 years of age.
Overweight and obese children are more likely to stay overweight into young adulthood. This can increase their risk of type 2 diabetes and limit their ability to stay fit and healthy. No one wants this for their child, so what can parents do?
It can be very difficult to start a conversation at home about body weight but if you are concerned about your child, it's worth the effort.
"If your children's weight is not an issue, either to them or you, the less parents talk about weight the better," says Tam Fry from the National Obesity Forum.
However, if your child's weight does start to impact on their life and well-being, he suggests that parents start by expressing their own fears about how excess weight might affect their child's health and happiness, rather than calling out their size or eating habits. Fry adds: "There are no guidelines which every family can follow except that the conversation should always be loving and honest. Tough love it may be but parents would be failing if they didn't deliver it."
Starting a conversation can be more challenging when parents are conscious that their own weight, eating habits and fitness are not an ideal example for their children to follow.
Parenting coach, Lorraine Thomas, says: "As a parent, look at the food you have in the house. Your child may be old enough to open the fridge ... but you buy what goes in there! Talk to your children about family health so that they are not singled out and show them that you are working on yours too. Set some goals, have some fun, do exercise together and spend quality time cooking together."
Avoiding negativity is vital, says psychologist, Emma Kenny. She continues: "Being body positive is essential. If your children hear you being negative about your own body, then expect them to follow with opinions of their own. I remind my kids constantly of how unbelievably blessed they are to have arms and legs and fingers and toes and taste and sight, etc. I think family activities such as nature trails, or even a brisk walk around the block every day can help increase activity levels and fitness and also doing some exercise at home together can make fitness fun."
Elaine Wyllie, a former headteacher of St Ninian's Primary school in Stirling, knows that even a short burst of regular exercise can be a great way for children to take charge of their own physical and emotional health. She was instrumental in introducing a campaign called the Daily Mile. This is a daily 15-minute run or walk which includes all children in the school, even those who are disabled or unfit.
She explains: "We are trying to promote self-care in children so a Daily Mile was a great way of getting the children to take charge of their own health. It was aimed at improving fitness but it actually ended up helping to prevent obesity as well as getting children in the right frame of mind to learn. It is definitely a positive health promotion tool."
The MEND foundation is another excellent place to find information about appropriate interventions for overweight and obese children. Parents can refer their child directly or ask a health professional to do this.
Check out your child's weight for height on the percentile chart or ask your health professional to help you do this.
Explore with your child whether their weight is causing any issues. Can they take part in all the activities they want to, do they have happy and stable friendships, and is there any evidence of teasing or bullying?
If your child's weight for height is above the 95th percentile or if you think their weight is causing issues for them, consider having a sensitive conversation about their health and fitness. Children should never be put on a diet unless your health professional has suggested it.
Focus your discussion on your own fears and hopes and suggest positive steps for making changes, such as taking more exercise as a family and eating healthier foods and drinks.
Avoid making negative comments about your child's weight or size, even in jest, as this can be counterproductive. Emma Kenny says: "Siblings often use 'fat' as a loaded insult as so many children know how hurtful such a term can be. As a parent it is important to communicate how unacceptable these types of comments are within sibling relationships."
Children are more successful at managing their weight when the whole family makes healthy changes to their diet and exercise habits.