Shrinking design rules and reduced process tolerances require tight control of CD linewidth, feature shape, and profile of the printed geometry. The Holistic Metrology approach consists of utilizing all available information from different sources like data from other toolsets, multiple optical channels, multiple targets, etc. to optimize metrology recipe and improve measurement performance. Various in-line critical dimension (CD) metrology toolsets like Scatterometry OCD (Optical CD), CD-SEM (CD Scanning Electron Microscope) and CD-AFM (CD Atomic Force Microscope) are typically utilized individually in fabs. Each of these toolsets has its own set of limitations that are intrinsic to specific measurement technique and algorithm. Here we define "Hybrid Metrology" to be the use of any two or more metrology toolsets in combination to measure the same dataset. We demonstrate the benefits of the Hybrid Metrology on two test structures: 22nm node Gate Develop Inspect (DI) & 32nm node FinFET Gate Final Inspect (FI). We will cover measurement results obtained using typical BKM as well as those obtained by utilizing the Hybrid Metrology approach. Measurement performance will be compared using standard metrology metrics for example accuracy and precision.
In keeping up with the tightening overall budget in lithography, metrology requirements have reached a deep subnanometer level . This drives the need for clean metrology (resolution and precision). Results have been published of a thorough investigation of a scatterometry-based platform from ASML , showing promising results on resolution, precision, and tool matching for overlay, CD and focus [2 - 6]. But overall requirements are so extreme that all measures must be taken in order to meet them. In light of this, in addition to above-mentioned need for resolution and precision, the speed and sophistication in communication between litho and metrology (feedback control) are also becoming increasingly crucial. An effective sampling strategy for metrology plays a big role in order to achieve this. This study discusses results from above mentioned scatterometry-based platform in light of sampling optimization. For overlay, various sampling schemes (dense / sparse combinations as well as inter and intra field schemes) were used on many production lots. The effectiveness of such sample schemes were studied to reveal an ideal sampling scheme that can result in 0.5nm to 1nm gain in overlay control (compare to today's practice). Moreover, cycle time contribution of metrology (at litho) in overall cycle time of a full process flow was investigated and quantified with the concept of integrated metrology. Results indicate a cycle time reduction per layer (if an integrated concept is used) of 3 to 5 hours, which can easily add up to several days of total cycle time reduction for a fab.
Improved overlay performance is one of the critical elements in enabling the continuing advancement of the semiconductor integrated circuit (IC) industry. With each advancing process node, additional sources of overlay error and new methods of reducing those errors need to be taken into account. We consider the impact of mask registration or pattern placement errors on intra-field on-wafer overlay performance. Mask registration data is typically minimally sampled and not well incorporated into the wafer fab overlay systems. In this work we consider mask-to-mask overlay and point out the importance of high density sampling as well as the potential for improved mask qualification and disposition.
Temporal drift in the mask manufacturing process has been observed in CD measurements collected at different times. Most of this is corrected through global sizing and dose adjustments resulting in small mean-to-target (MTT) residual errors. However, this procedure does not account for a detectable change in the proximity behavior of the mask process. This paper discusses a procedure for detecting and monitoring the proximity behavior of a process using an targeted sampling plan. It also proposes a procedure to correct for drifts in proximity behavior if it is predictable and systematic.
The novel method of sub-nanometer accuracy (uncertainty) for the line width and line profile measurement using STEM (Scanning Transmission Electron Microscope) images is proposed to calibrate CD-SEM line width measurement. In accordance with the proposed method, the traceability and reference metrology of line width measurements are established using Si lattice structures. First, we define two interfaces of Si-SiO2 and Si-Air. The interface of Si-SiO2 is defined as the end of Si lattice structure, and the interface of SiO2-Air is defined using image intensity of STEM image after metal coating. Second, an image magnification is calculated using 2D Fourier analysis of a STEM image. Third, the edge positions of the line are detected by Si lattice patterns and image intensity. Using the proposed method, the estimated accuracy less than 0.5 nm for the line width of 50 nm is established.
Semiconductor technology is advancing below 50 nm critical dimensions bringing unprecedented challenges to process engineering, control and metrology. Traditionally, interconnect metrology is put behind high-priority gate metrology; however, considering metrology, process and yield control challenges this decision is not always justified. Optical scatterometry is working its way to interconnect manufacturing process control, but scanning electron microscopy (SEM) remains the number one critical dimension (CD) metrology for interconnect process engineering and optical proximity correction (OPC) modeling. Recently, several publications have described secondary electron (SE) trapping within narrow high-aspect ratio interconnect structures. In these papers, pre-dosing of the sample helped to extract SE from the bottom of the hole and measure its diameter. Based on current understanding of the phenomenon, one should expect that high-aspect ratio interconnect structures (holes and trenches) with critical dimensions below 100 nm may show signs of SE trapping of various degree. As a result, there may be an uncontrolled effect on SE waveform and, therefore, bias of CDSEM measurement. CD atomic force microscopy (AFM) was employed in this work as a reference metrology for evaluation of uncertainty of trench and hole measurements by CDSEM. As the data indicates, CDSEM bias shows a strong dependence on pitch of periodic interconnect structure starting from drawn CD of 50 nm. CDSEM bias variation for the evaluated set of samples is about 19 nm. A typical OPC sample consists of both photoresist and etched interlayer materials. As the AFM data for photoresist material indicates, the hole diameter changes quite significantly with depth and the hole profile varies from one OPC structure to another. Abe et al.  have used a clever way to correlate physical bottom diameter of holes with CDSEM measurements and demonstrated that for their process and dimensions the SEM "top" diameter and physical bottom diameter correlate well. Unfortunately, this conclusion can't be generalized and measurement uncertainty of CDSEM must be evaluated on an individual technology/process basis. A more general approach to improve CDSEM accuracy is necessary which is based upon SI-traceable CDSEM bias measurements, modeling and correction.
Photoresist shrinkage is an important systematic uncertainty source in critical dimension-scanning electron microscope (CD-SEM) metrology of lithographic features. In terms of metrology gauge metrics, it influences both the precision and the accuracy of CD-SEM measurements, while locally damaging the sample. Minimization or elimination of shrinkage is desirable, yet elusive. Because this error source will furthermore be a factor in CD-SEM metrology on polymer materials, learning to work around this issue is necessary. Tool-to-tool matching is another important component of measurement uncertainty that metrologists must control in high volume manufacturing, and photoresist samples are a most difficult case due to shrinkage effects, as tool-to-tool biases can vary based on the sample or other parameters. In this work, we explore different shrinkage effects and their influence on matching. This will include an investigation of how the photoresist shrinkage rate varies with time from the chemical development of the photoresists, which necessitates that measurements on different tools within a group be performed in rapid succession to avoid additional error. The differences in shrinkage rates between static and dynamic load/unload cases will also be addressed, as these effects also influence matching. The results of these dynamic effect experiments will be shown to have far-reaching implications for the shrinkage phenomenon in general. Finally, various sampling schemes for matching will be explored, through both simulation and experiment, for use with shrinking materials. Included is a method whereby various fleet tools measure different locations, once per tool, within a uniform line/space grating. Finally, we will assess how well matching can be achieved using these techniques.
Influence of the prominent charging effect on the precision of measuring EUV mask features using CD-SEM was studied. The dimensions of EUV mask features continuously measured by CD-SEM gradually varied because of the charging. The charging effect on the measured CD variation mainly consists of three factors: 1) shift of the incident points of primary electrons deflected by the surface charge, 2) distortions of the profiles of secondary electron signal intensity caused by the deflection of the secondary electrons, 3) deviation of the maximum slope points of the secondary electron signal intensity due to the variation of the image contrast. For those three factors described above, how the material constant affect the CD variation measured by CD-SEM is discussed.
Rapidly decreasing critical dimensions (CD) for semiconductor devices drive the study of improved methods for the detection of defects within patterned areas. As reduced CDs are being achieved through directional patterning, additional constraints and opportunities present themselves in defect metrology. This simulation and experimental study assesses potential improvements in patterned defect inspection that may be achieved by engineering the light incident to the sample within a high-magnification imaging platform. Simulation variables include the incident angle, polarization, and wavelength for defect types common to directional device layouts. Detectability is determined through differential images between no-defect- and defect-containing images. Alternative metrologies such as interference microscopy are also investigated through modeling. The measurement of a 20 nm defect is demonstrated experimentally using 193 nm light. The complex interplay of unidirectional patterning and highly directional defects is explored using structured off-axis illumination and polarization.
The ability to simulate patterned wafer inspection microscopy is important to guide equipment development, with defect signal-to-noise being the key output metric. With the ongoing introduction of aggressively low k1 lithography, the contribution of wafer noise is becoming one of the dominant noise elements. Quantitative noise models which accurately represent wafer noise are required. The present work develops structural models for line edge roughness and surface roughness. Aerial image FDTD simulations are performed on the model structures and the relationships between the model parameters and defect signal-to-wafer-noise are explored, with conclusions being drawn regarding the wafer inspection sensitivity process window.
An in-line inspection method for estimating defect resistances from the grayscale of voltage contrast in SEM images of manufactured patterns was developed. This method applies a circuit simulator to calculate the intensity of the secondary electrons according to an equivalent-circuit model considering the charge-up voltage on the patterns. To accurately estimate the resistance of defects formed in a device, first, the simulator was improved by taking the variation of defect resistance into account, which strongly depends on the differential voltage between the plug surfaces and the backside wafer. The defect resistances were obtained from the measured I-V characteristics of the deliberately formed defect on the standard calibration wafers, in which some incomplete-contact defects were systematically formed. Next, to consider the effect of the electronic characteristics of the pattern under the normal plugs on the grayscale, the I-V characteristics of the normal plugs were measured. The equivalent circuit of the simulator was improved by taking into account the measured I-V characteristics. The calibration curve for the inspected patterns was calculated from the improved circuit simulator. Finally, the inspection method was applied to estimate the resistance of defects formed on an SRAM pattern. The calculated calibration curve was used to accurately estimate the defect resistance (with an accuracy of about an order of magnitude) from the voltage contrast formed on the defects in the inspected SRAM patterns.
Extreme ultraviolet (EUV) lithography is considered as the leading patterning technology beyond the ArF-based optical lithography, addressing the need for transistor densification to meet Moore's Law. Theoretically, EUV lithography at 13.5nm wavelength meets the resolution requirements for 1xnm technology nodes. However, there are several major challenges in the development of EUV lithography for mass production of advanced CMOS devices. These include the development of high power EUV light sources, EUV optics, EUV masks, EUV resists, overlay accuracy, and metrology and inspection capabilities. In particular, it is necessary to ensure that effective defect control schemes will be made available to reduce the EUV lithography defectivity to acceptable levels. This paper presents a study on the wafer defectivity and characterization of patterned EUV resists, with the objective of providing a quantitative comparison between the defectivity of different resist materials and different stacks. Patterned wafers were printed using the ASML® EUV full-field Alpha-Demo Tool (ADT 0.25 NA) at imec. The EUV resist patterns were 32nm line/spaces. Several advanced resist types were screened experimentally. The different resist types and stacks were inspected using a DUV laser based brightfield inspection tool, followed by a SEM defect review and CD metrology measurements. The patterns were characterized in terms of defect types and defect density. We identified the major defect types and discuss factors that affect the defectivity level and pattern quality, such as resist type, exposure dose and focus. Defect scattering analysis of DUV polarized light at different polarizations was performed, to indicate on the inspection performance trends for a variety of defect types and sizes of the different resists and stacks. The scattering analysis shows that higher defect scattering is induced using polarized light.
As the design rule shrinks down, various techniques such as RET, DFM have been continuously developed and applied to lithography field. And we have struggled not only to obtain sufficient process window with those techniques but also to feedback hot spots to OPC process for yield improvement in mass production. OPC verification procedure which iterates its processes from OPC to wafer verification until the CD targets are met and hot spots are cleared is becoming more important to ensure robust and accurate patterning and tight hot spot management. Generally, wafer verification results which demonstrate how well OPC corrections are made need to be fed back to OPC engineer in effective and accurate way. First of all, however, it is not possible to cover all transistors in full-chip with some OPC monitoring points which have been used for wafer verification. Secondly, the hot spots which are extracted by OPC simulator are not always reliable enough to represent defective information for full-chip. Finally, it takes much TAT and labor to do this with CD SEM measurement. These difficulties on wafer verification would be improved by design based analysis. The optimal OPC monitoring points are created by classifying all transistors in full chip layout and Hotspot set is selected by pattern matching process using the NanoScopeTM, which is known as a fast design based analysis tool, with a very small amount of hotspots extracted by OPC simulator in full chip layout. Then, each set is used for wafer verification using design based inspection tool, NGR2150TM. In this paper, new verification methodology based on design based analysis will be introduced as an alternative method for effective control of OPC accuracy and hot spot management.
A new methodology for inspection of TSV (Through Silicon Via) process wafers is developed by utilizing an optical diffraction signal from the wafers. The optical system uses telecentric illumination and has a two-dimensional sensor in order to capture the diffraction light from TSV arrays. The diffraction signal modulates the intensity of the wafer image. Furthermore, the optical configuration itself is optimized. The diffraction signal is sensitive to via-shape variations, and an abnormal via area is analyzed using the signal. Using the test wafers with deep hole patterns on silicon wafers, the performance is evaluated and the sensitivities for various pattern profile changes were confirmed. This new methodology is available for high-volume manufacturing of the future TSV-3D CMOS devices.
We formerly developed the "assembly method" for analyzing the line-edge and line-width roughness (LER/LWR) that has a long-range correlation beyond the conventional analysis limit. In the method, we repeatedly assembled virtual long lines by gathering line segments, which were arbitrarily disposed on actual long lines and by randomly changing their combination and order, permitting the assembled lines to share the same line segments. Then, we obtained the PSD of the LER/LWR of the assembled lines considering the lines as seamless. We also derived an analytic formula of the assembled-line PSDs. This formula excellently agreed with experimental PSDs. In this report, we propose guidelines for suppressing the statistical-noise effect on the assembly method for the purpose of accurately analyzing the long-range- correlated LER/LWR. The guidelines will greatly help shed light on the long-range correlation, which causes the variability even in large devices but has long been veiled due to the lack of metrology.
As the design rule of Integrated Circuits(IC) becomes smaller, the precise measurement of Critical Dimension (CD) of features and minimization of deviation in CD measured becomes a vital issue. In this paper, a simple frequency analysis method to extract the noise from SEM images was used to evaluate the contribution of SEM noise in CD Uniformity. Multiple SEM images of simple Line and Space (L/S) patterns were analyzed and a model of frequency profile (Power Spectrum Density (PSD) model) was made using an offline analyzing tool based on Matlab®. From this profile, white noise and 1/f profile were separated. Noises are eliminated to generate a noise reduced PSD profile to make CD results. The contribution of white noise on CD measurement can be assessed using Line Width Roughness (LWR) measurement. Furthermore, CD uniformity can be also predicted from the model. This prediction is based on an assumption that CD uniformity is equal to LWR if the inspection area is extended to infinity and appropriate sampling method is applied. The results showed that the contribution of white noise on LWR can be up to around 70% (in power) without any noise reduction measures (sum line averaging) after imaging in photo resist image. For experimental validation, CD uniformity is predicted from the model for different measurement conditions and compared with real measurement. For a result, CD uniformity prediction (3sigma) from the model shows within 20% in accuracy with real CD uniformity value measured from the photo resist image.
We have improved both the spatial resolution and precision of three-dimensional (3D) electron microscopy, which is based on conventional scanning transmission electron microscopy (STEM), by using a micro-pillar specimen together with a 3D analysis holder, and by introducing marker-assisted image alignment prior to 3D reconstruction. Our 3D STEM measurement of aggressively scaled metal-oxide-semiconductor (MOS) gate structures not only successfully showed the z-axis positional dependence of gate-edge profiles and edge-roughness profiles such as line edge roughness (LER) and line width roughness (LWR), but also revealed uniformity of each layer of which the gate structure was composed. Such observations are very important in controlling future device characteristics, but are difficult to obtain using other measurement techniques.
We used azimuthally-resolved spectroscopic Mueller matrix ellipsometry to study a periodic silicon line structure with and without artificially-generated line edge roughness (LER). The unperturbed, reference grating profile was determined from multiple azimuthal configurations using a generalized ellipsometer, focusing the incident beam into a 60 μm spot. We used rigorous numerical modeling, taking into account the finite numerical aperture, introducing significant depolarization effects, and determining the profile shape using a four trapezoid model for the line profile. Data obtained from the artificially perturbed grating were then fit using the same model, and the resulting root-mean-square error (RMSE) values for both targets were compared. The comparison shows an increase in RMSE values for the perturbed grating that can be attributed to the effects of LER.
Recently, optical proximity correction model calibration techniques that use SEM contours have enabled possibly significant improvements in complex mask design. However, compared to conventional CD-based calibration, contour-based calibration results in increased errors in 1D features. In fact, our research shows that there is a ~1-nm gap, which we call "CD-gap," between CD measurements directly calculated from a SEM image and CD measurements calculated from SEM contours. To achieve accurate calibration, SEM contours must match the corresponding CD measurements. We have developed a CD-gap-free contour extraction technique in response to this problem. In our technique, a mask edge is classified into shape structures and an optimized SEM contour extraction method is prepared for each shape structure to reduce the CD-gap. Experimental results show that the CD-gap can be decreased to sub-nm, which clearly demonstrates the potential of our proposed technique to play a vital role in the lithography process.
A data-set comprising of lines and spaces was collected by inline scanning electron microscope at a single measurement threshold. Input data included measurements from features of several sizes at a range of pitch values as well as the entire Bossung curve for certain critical features. Models were calibrated with and without scaling of cost weight. Weights were scaled using inverse weight algorithm based on the differential sensitivity to focus for various feature types to a given lithography system. The imaging and the resist empirical parameters were extracted by regression over the entire data-set and a truncated version of the same data-set. The through-focus fitting error reduced by over 50% from +/- 5% to 2% with the cost weights scaled using the inverse weight algorithm. The quickness combined with the ability to extract fitting parameters precisely using this technique has enabled implementation on various digital and analog layers ranging from 180nm to 65nm nodes.
In this paper, we present a methodology for the characterization of Contact Edge Roughness (CER) using top-down SEM images and an algorithm for the generation of model contact edges with controlled roughness as well as synthesized SEM images with CER. The characterization methodology is applied to the determination of the effects of exposure dose on the amplitude and frequency parameters of the CER of an EUV resist, while the model edges are used for understanding the results and connecting RMS to CD variation. Experiments show us that the RMS value of CER decreases as dose decreases contrary to what happens to LER/LWR. Modeling shows that RMS decreases and CD variation increases as the sampled edge length is decreased, in agreement with LER/LWR. Thus, modelling may offer an explanation of the RMS reduction with reduced dose: Indeed, decrease of dose causes reduction of Critical Dimension (CD) (i.e. diameter) of the hole and therefore reduction of its circumference (i.e. measurement edge length), which in turn causes reduction of RMS and increase in CD variation.
The measurement uncertainty is becoming one of the major components that have to be controlled in order to guarantee sufficient production yield. Already at the R&D level, we have to cope up with the accurate measurements of sub-40nm dense trenches and contact holes coming from 193 immersion lithography or E-Beam lithography. Current production CD metrology techniques such as CD-SEM and OCD are limited in relative accuracy for various reasons (i.e electron proximity effect, outputs parameters correlation, stack influence, electron interaction with materials...). Therefore, time for R&D is increasing, process windows degrade and finally production yield can decrease because you can not manufactured correctly if you are unable to measure correctly. A new high volume manufacturing (HVM) CD metrology solution has to be found in order to improve the relative accuracy of production environment otherwise current CD Metrology solution will very soon get out of steam. In this paper, we will present a potential Hybrid CD metrology solution that smartly tuned 3D-AFM and CD-SEM data in order to add accuracy both in R&D and production. The final goal for "chip makers" is to improve yield and save R&D and production costs through real-time feedback loop implement on CD metrology routines. Such solution can be implemented and extended to any kind of CD metrology solution. In a 2nd part we will discuss and present results regarding a new AFM3D probes breakthrough with the introduction of full carbon tips made will E-Beam Deposition process. The goal is to overcome the current limitations of conventional flared silicon tips which are definitely not suitable for sub-32nm nodes production.
Through-focus scanning optical microscopy (TSOM) is a new metrology method that achieves 3D nanoscale measurement sensitivity using conventional optical microscopes; measurement sensitivities are comparable to what is typical when using scatterometry, scanning electron microscopy (SEM), and atomic force microscopy (AFM). TSOM can be used in both reflection and transmission modes and is applicable to a variety of target materials and shapes. Nanometrology applications that have been demonstrated by experiments or simulations include defect analysis, inspection and process control; critical dimension, photomask, overlay, nanoparticle, thin film, and 3D interconnect metrologies; line-edge roughness measurements; and nanoscale movements of parts in MEMS/NEMS. Industries that could benefit include semiconductor, data storage, photonics, biotechnology, and nanomanufacturing. TSOM is relatively simple and inexpensive, has a high throughput, and provides nanoscale sensitivity for 3D measurements with potentially significant savings and yield improvements in manufacturing.
Mask inspection review of pattern features and defects is normally carried out using a secondary electron microscopy (SEM) technique. Ideally, such mask inspections reviews should be non-destructive; nonetheless, as reported in this paper, high-dose exposures of EUVL mask surfaces have resulted in significant topographical changes, which were revealed by topographical mapping of reviewed masks using atomic force microscopy (AFM). Exposures with current densities of 1 mA/cm2 and higher resulted in the formation of topographical features in and around the scanned region on mask surfaces. On the Ru-capped multilayer blanks, the topographies consisted of small or absent depressions surrounded by ridges, which were attributed to secondary-electron-emission induced hydrocarbon deposition. On the chromium-nitride backsides, the topographies were usually simple depressions - although sometimes ridges were observed. The depressions were attributed to volume compaction in the substrate. The depressions were attributed to volume compaction in the substrate, and were observed for all for mask surfaces studied - substrate compaction took place with both quartz and LTEM substrates. The height range of the topography extended up to 25 nm, whereas the lateral dimensions often exceeded the scanned area by about a micron. While these lateral extensions could not be explained by either beam-induced heating or stress relief, Monte-Carlo simulations showed that it could be explained qualitatively by the size of the region within which the energy deposition had taken place. This interpretation suggests that the current understanding as described by Hau- Riege qualitatively describe our observations related to depression topography.
In order to achieve pattern shape measurement with CD-SEM, the Model Based Library (MBL) technique is in the process of development. In this study, several libraries which consisted by double trapezoid model placed in optimum layout, were used to measure the various layout patterns. In order to verify the accuracy of the MBL photoresist pattern shape measurement, CDAFM measurements were carried out as a reference metrology. Both results were compared to each other, and we confirmed that there is a linear correlation between them. After that, to expand the application field of the MBL technique, it was applied to end-of-line (EOL) shape measurement to show the capability. Finally, we confirmed the possibility that the MBL could be applied to more local area shape measurement like hot-spot analysis.
A method for improving the resolution of a scanning electron microscope (SEM) designed for inspection of nanodevices was developed. The trade-off between the resolution and depth of focus of the SEM was quantitatively evaluated by a method based on "information passing capacity". It was theoretically and experimentally shown that depth of focus is enhanced under observation conditions with increased pixel size. Furthermore, increasing depth of focus is effective in obtaining high-resolution images because increasing the pixel size of the formed SEM image maintained the focal plane of the electron beam. The maximum axial magnetic field and the focal length of the objective lens in the SEM optics needed to obtain a resolution of 0.9 nm were determined theoretically. The maximum axial magnetic field can be strengthened by improving the immersion lens in the SEM optics in terms of geometry and material composition. The focal length was reduced by adopting the immersion lens and by dynamically controlling the electron beam by deflectors as well as optical correctors. This method will be applied in developing apparatuses for R&D purposes as well as for improving the yield of the production process for integrated circuits.
Spacer defined double patterning processes consists of multiple deposition, post strips and etch steps and is inherently susceptible to the cumulative effects of defects from each process step leading to higher rate of defect detection. CD distortions and CD non-uniformity leads to DPT overlay errors. This demands improved critical dimension uniformity (CDU) and overlay control. Scatterometry technique enables the characterization and control the CD uniformity and provision to monitor stepper and scanner characteristics such as focus and dose control. While CDSEM is capable of characterizing CD and sidewall angle, is not adequate to resolve shape variations, such as footing and top rounding and spacers with leaning angles, during the intermediate process steps. We will characterize direct low temperature oxide deposition on resist spacer with fewer core films and reduced number of processing and metrology control steps. Metrology characterization of SADP and resist core transferred spacers at various process steps will be performed by scatterometry using spectroscopic ellipsometry and reflectometry. We will present CD distribution (CDU) and profile characterization for core formation, spacer deposition and etch by advanced optical scatterometry and also validate against CDSEM.
With device size reduction, variability induced by local micro roughness is becoming less and less negligible in terms of statistical control of critical dimensions (CD). We applied a recent approach developed at Fresnel Institute for the determination of micro roughness on periodic structures through optical far field characterization using an angle resolved scatterometer. Structure periodicity affects the diffraction orders, while roughness signature is mainly found between diffraction orders. Theoretical simulation was performed using two in-house computer codes based on differential method and on first order approximation. We will review the theoretical approach and show roughness data derived from measurement on glass gratings as well as poly silicon gate type structures.
Improvement in metrology performance when using a combination of multiple optical channels vs. standard single optical channel is studied. Two standard applications (gate etch 4x and STI etch 2x) are investigated theoretically and experimentally. The results show that while individual channels might have increased performance for few individual parameters each - it is the combination of channels that provides the best overall performance for all parameters.
In recent years, numerous authors have reported the advantages of Diffraction Based Overlay (DBO) over Image Based Overlay (IBO), mainly by comparison of metrology figures of merit such as TIS and TMU. Some have even gone as far as to say that DBO is the only viable overlay metrology technique for advanced technology nodes; 22nm and beyond. Typically the only reported drawback of DBO is the size of the required targets. This severely limits its effective use, when all critical layers of a product, including double patterned layers need to be measured, and in-die overlay measurements are required. In this paper we ask whether target size is the only limitation to the adoption of DBO for overlay characterization and control, or are there other metrics, which need to be considered. For example, overlay accuracy with respect to scanner baseline or on-product process overlay control? In this work, we critically re-assess the strengths and weaknesses of DBO for the applications of scanner baseline and on-product process layer overlay control. A comprehensive comparison is made to IBO. For on product process layer control we compare the performance on critical process layers; Gate, Contact and Metal. In particularly we focus on the response of the scanner to the corrections determined by each metrology technique for each process layer, as a measure of the accuracy. Our results show that to characterize an overlay metrology technique that is suitable for use in advanced technology nodes requires much more than just evaluating the conventional metrology metrics of TIS and TMU.
Angle resolved Mueller polarimetry implemented as polarimetric imaging of the back focal plane of a high NA microscope objective has already demonstrated a good potential for CD metrology1. In this paper we present the experimental and numerical results which indicate that this technique may also be competitive for measurements of the overlay error δ between two gratings at different levels. Series of samples of superimposed gratings with well controlled overlay errors have been manufactured and measured with the angle resolved Mueller polarimeter. The overlay targets were 20 μm wide. When overlay error δ = 0 the absolute value of Mueller matrix elements is invariant by matrix transposition. This symmetry breaks down when δ ≠ 0. As a result, we can define the following overlay estimator matrix: Ε = |Μ | - |Μ |t. The simulations show that matrix element E14 is the most sensitive to the overlay error. In the experiments the scalar estimator of E14 was defined by averaging the pixel values over specifically chosen mask. The scalar estimator is found to vary essentially linearly with δ for the overlay values up to 50 nm. Our technique allows entering quite small overlay marks (down to 5 μm wide). The only one target measurement is needed for each overlay direction. The actual overlay value can be determined without detailed simulation of the structure provided the two calibrated overlay structures are available for each direction.
In this paper we present a method to combine measurement techniques that reduce uncertainties and improve measurement throughput. The approach has immediate utility when performing model-based optical critical dimension (OCD) measurements. When modeling optical measurements, a library of curves is assembled through the simulation of a multi-dimensional parameter space. Parametric correlation and measurement noise lead to measurement uncertainty in the fitting process resulting in fundamental limitations due to parametric correlations. We provide a strategy to decouple parametric correlation and reduce measurement uncertainties. We also develop the rigorous underlying Bayesian statistical model to apply this methodology to OCD metrology. These statistical methods use a priori information rigorously to reduce measurement uncertainty, improve throughput and develop an improved foundation for comprehensive reference metrology.
CD-AFM can report CD measurements to several nanometer differences when different probing techniques including probe types, scan methods, or data analyses are employed on the same sample despite using standard calibration techniques. This potentially weakens the assertion that this instrument is inherently accurate. It is particularly important to resolve these discrepancies given the measurement challenges where multiple probing techniques need to be employed to get complete CD information. Probe type refers to tip construction methods that can significantly affect geometrical aspects of probe such as effective length, width, and edge height as well as material composition and coating. Scan code refers to CD or DT mode of tool operation. Analysis includes probe geometry deconvolution and measurement algorithms. These challenges in measurement accuracy are especially significant for the foot or bottom CD metrology of 3D structures. This paper explores the impact of these different probing techniques on the measurement accuracy. In one series of experiments, measurements for different probing techniques are compared when the test and the referencing structures are composed of similar material and possess smooth vertical profiles. The investigation is then extended to explore the accuracy of bottom CD measurement of non vertical profiles encountered in actual process development. A hybrid method using CD and DT modes has been tested to measure the bottom CD of challenging pitch structures. The limited space for the probe is particularly problematic for CD mode but the accuracy of DT mode for CD measurement is a concern. Other challenges will also be discussed along with possible solutions. CD-AFM has increased uncertainty when it comes to measuring within 15 nm of the bottom of a structure. In this regime details of the shape of the probe and the method by which this shape is extracted from the raw data become important. Measured CDs can vary by a few nanometers depending upon the algorithm employed for data analysis. These algorithms apply approximate methods for probe shape deconvolution from the raw data. Given all these sources of variation in CD determination it important to understand their impact on the accuracy of measurement in order to properly estimate uncertainty and drive improvement. Overall this paper provides a practical guideline in pursuit of accurate CD metrology and scope for improvements for upcoming technology nodes.
As the feature size in the lithography process continuously shrinks, accurate critical dimension (CD) measurement becomes more important. A new 3-dimensional (3D) metrology atomic force microscope (AFM) has been designed on a decoupled XY and Z scanner platform for CD and sidewall characterization. In this decoupled scanner configuration, the sample XY scanner moves the sample and is independent from the Z scanner which only moves the tip. The independent Z scanner allows the tip to be intentionally tilted to easily access the sidewall. This technique has been used to measure photoresist line patterns. The tilted scanner design allows CD measurement at the top, middle, and bottom of lines as well as roughness measurement along the sidewall. The method builds upon the standard AFM tip design resulting in a technique that a) maintains the same resolution as traditional AFM, b) can be used with sharpened tips for increased image resolution, and c) does not suffer from corner inaccessibility from large radius of curvature tips.
The aggressive device scaling imposed by the International Technology Roadmap for Semiconductors (ITRS) is introducing additional and more demanding challenges to current in-line monitoring tools. In this paper we present a new probe microscopy based technology, the Rapid Probe Microscope (RPM), which produces nano-scale images using a height contrast mechanism in a non-vacuum environment. The system offers the possibility to address metrology challenges in alternative ways to existing review and inspection tools. This paper presents applications of the RPM process which cater to the requirements of the semiconductor industry. Results on several standard semiconductor wafer layers have been used to demonstrate the capabilities of the RPM process, including nano-scale surface imaging at high image capture rates.
Image of the atomic force microscopy (AFM) is the convolution of probe shape and specimen geometry. However, probe shape for AFM imaging is not equivalent to the actual probe shape. Gap distance was controlled with the interaction between probe and specimen. Imaging parameters for controlling gap distance between probe and specimen surface is one of the origins of image artifacts. Artifacts of the AFM image were analyzed as a function of set-point in dynamic mode, using well defined reference specimen. Two kinds of typical objects, such as single protrusion and narrow gap were used for the analysis of artifacts in the AFM image.
Forbidden pitch which is introduced under a dipole illumination condition has extremely narrow DOF (Depth Of Focus). Therefore when a lithographic pattern is transferred on a wafer the forbidden pitch should be removed from the layout. However this narrow DOF behavior can be utilized to monitor a focus of scanner systems due to its sensitiveness to focus changes. In this paper, a newly developed focus monitoring method utilizing a forbidden pitch pattern will be introduced and the benefits and sensitivity of this method will be discussed in details.
To keep pace with the overall dimensional shrink in the industry, overlay capability must also shrink proportionally. Unsurprisingly, overlay capability < 10 nm is already required for currently nodes in development, and the need for multi-patterned levels has accelerated the overlay roadmap requirements to the order of 5 nm. To achieve this, many improvements need to be implemented in all aspects of overlay measurement, control, and disposition. Given this difficult task, even improvements involving fractions of a nanometer need to be considered. These contributors can be divided into 5 categories: scanner, process, reticle, metrology, and APC. In terms of overlay metrology, the purpose is two-fold: To measure what the actual overlay error is on wafer, and to provide appropriate APC feedback to reduce overlay error for future incoming hardware. We show that with optimized field selection plan, as well as appropriate within-field sampling, both objectives can be met. For metrology field selection, an optimization algorithm has been employed to proportionately sample fields of different scan direction, as well as proportional spatial placement. In addition, intrafield sampling has been chosen to accurately represent overlay inside each field, rather than just at field corners. Regardless, the industry-wide use of multi-exposure patterning schemes has pushed scanner overlay capabilities to their limits. However, it is now clear that scanner contributions may no longer be the majority component in total overlay performance. The ability to control correctable overlay components is paramount to achieving desired performance. In addition, process (non-scanner) contributions to on-product overlay error need to be aggressively tackled, though we show that there also opportunities available in active scanner alignment schemes, where appropriate scanner alignment metrology and correction can reduce residuals on product. In tandem, all these elements need to be in place to achieve the necessary overlay roadmap capability for current development efforts.
There is no overlay standard in the world. For critical dimension (CD), we may use the VLSI standard or programmed pitch offsets to determine the CD accuracy or CD sensitivity. Programmed overlay offsets can provide relatively accurate sub-nanometer level overlay splits but it is only on a single layer and does not contain layer-to-layer process variations. The splits of scanner magnification can check the trend of overlay sensitivity but it cannot provide the exact value of overlay offsets. Transmission electron microscopes (TEM) can be used as a final overly error verification tool. However, TEM sample preparation for after-development-inspection (ADI) will introduce even more sample distortion errors. Therefore, unlike CD metrology, there is no clean and systematic way to verify the accuracy of overlay metrology. These technical barriers necessitate matching diffraction-based overlay and image-based overlay, especially for sub-nanometer point-to-point matching requirement. In this paper, we compare the correlation of ADI to after-etch-inspection (AEI) by using image-based box-in-box overlay measurement and diffraction-based overlay measurement on the same wafer. The ADI-to-AEI overlay data consistency plays a key role for lithography overlay APC success and AEI overlay should be treated as the final standard for overlay accuracy. We found that process-induced asymmetric profiles of overlay marks will lead to ADI-to-AEI overlay bias. This bias is proportional to the degree of profile asymmetry and different color/wavelength have different sensitivity to this ADI-to-AEI bias. Our experimental results show that the ADI-to-AEI overlay data bias can indeed be significantly improved by selecting the color/wavelength with minimum sensitivity to the asymmetry profile. These results make us believe that overlay metrology recipe setup is quite critical no matter for image-based overlay or diffraction-based overlay. Otherwise, problematic overlay data will be taken into APC feedback loop and lead to wrong overlay correction.
The shrinkage of design rule necessitated corresponding tighter overlay control. However, in advanced applications, the extension of current technology may not be able to meet the control requirement, consequently, additional breakthroughs are required. In this study, we investigated methods to enhance the overlay control, approaches by extraction of real overlay error out of overlay measurement. So far, only the destructive inspections like vertical SEM have enabled us to measure real misalignment. But, a concept of non-destructive method is proposed in this paper, extracting vertical information from the results of multiple measurements with various measurement conditions, keys or recipes. With this proposed method, the measurement accuracy can be improved and we can enable a new knob for overlay control.
Overlay control is one of the most critical areas in advanced semiconductor processing. Maintaining optimal product disposition and control requires high quality data as an input. Outliers can contaminate lot statistics and negatively impact lot disposition and feedback control. Advanced outlier removal methods have been developed to minimize their impact on overlay data processing. Rejection methods in use today are generally based on metrology quality metrics, raw data statistics and/or residual data statistics. Shortcomings of typical methods include the inability to detect multiple outliers as well as the unnecessary rejection of valid data. As the semiconductor industry adopts high-order overlay modeling techniques, outlier rejection becomes more important than for linear modeling. In this paper we discuss the use of robust regression methods in order to more accurately eliminate outliers. We show the results of an extensive simulation study, as well as a case study with data from a semiconductor manufacturer.
Scribe Line Marks (SLM) printed on substrates are a standard method used by modern scanners for wafer alignment. Light reflected from the SLM forms a diffraction pattern which is used to determine the exact position of the wafer. The signal strength of the diffraction order needs to reach a certain threshold for the scanner to detect it. The marks are changed as the wafers go through various processes and are buried underneath complex film stacks. These processes and stacks can severely reduce wafer quality (WQ). Equipment manufactures recommend several variations of the SLM to improve WQ but these variations are not effective for certain advanced processes. This paper discusses theoretical analysis of how SLM designs affect wafer quality, addresses the challenge of self-aligned double patterning (SADP) on SLMs and experimentally verifies results using various structures.
For the 28 nm node lithographic production steps, the process window for both overlay and CD are becoming increasingly tight. The overlay stability of lithography tools must be at a level of 1-2 nm within the product cycle time, while focus needs to be stable within 5 nm. Well-matched tools are crucial to improve the flexibility of tool usage and the pressure for higher tool availability is allowing less time for periodic maintenance and tool recovery. Here, we describe the way of working and results obtained with a long-term stability control application, containing a scanner performance control system with a correction feedback loop deploying scatterometry. In this study the overlay performance for immersion scanners was stabilized and the point-to-point difference to a reference is maintained at less than 4 nm. The capability of tool recovery handling after interventions is demonstrated. Results of overlay matching between machines are shown. The tool stability for focus was controlled in a range of less than 5 nm while improving the total focus uniformity.
In order to ensure long-term profitability, driving the operational costs down and improving the yield of a DRAM manufacturing process are continuous efforts. This includes optimal utilization of the capital equipment. The costs of metrology needed to ensure yield are contributing to the overall costs. As the shrinking of device dimensions continues, the costs of metrology are increasing because of the associated tightening of the on-product specifications requiring more metrology effort. The cost-of-ownership reduction is tackled by increasing the throughput and availability of metrology systems. However, this is not the only way to reduce metrology effort. In this paper, we discuss how the costs of metrology can be improved by optimizing the recipes in terms of the sampling layout, thereby eliminating metrology that does not contribute to yield. We discuss results of sampling scheme optimization for on-product overlay control of two DRAM manufacturing processes at Nanya Technology Corporation. For a 6x DRAM production process, we show that the reduction of metrology waste can be as high as 27% and overlay can be improved by 36%, comparing with a baseline sampling scheme. For a 4x DRAM process, having tighter overlay specs, a gain of ca. 0.5nm on-product overlay could be achieved, without increasing the metrology effort relative to the original sampling plan.
LWR and CD linearity are both a major concern in the interpretation of drawn devices to actual structures on Si, and even more when translating to expected currents (both driven current and leakage current). Both of them have long ago been shown to be sensitive to process (especially lithographic) conditions, but usually not comparatively and, even more seldom are the final (etched) results thus related to the lithography process. Following our previous work on the sensitivities of LER and LWR to layout, we set out to research whether these sensitivities are themselves sensitive to process changes which tend to affect LER and LWR. As a logical conclusion, we expected that process changes which tend to worsen roughness will increase the dependence of the roughness on layout effects - that the outcome will be addible. Measurements were done in Active Area (a.k.a. STI definition) layer. Results show very interesting dependence of roughness and CD linearity (dependence of measured CDs on drawn CDs) of long dense resistors. Process changes that tended to make roughness worse, also had significant impact on the linearity, making it surprisingly more accurate at the low CD regime, but with significantly more variance.
It was reported that the ArF excimer laser mainly used in the process of lithography for semiconductor devices cause pollutants on a photo-mask by various photochemical reactions, which is called by the haze. Therefore, the real time detection system on the lithography process is needed in order to inspect the generation of defects containing the haze on the mass production system before and/or after the generation of defects. We proposed and experimentally confirmed the concept of the new real time detection system to detect automatically and visually many defects with several hundred nanometer size generating on a photo-mask by using interference fringes generated by interfering between the light wave scattered by small defects of a photo-mask and the reflected light wave from the rest area of the front surface. In order to balance the contrast ration of two interference light waves, we utilized the incident beam with the nearly Brewster angle on the photo-mask and a linear polarizer aligned in front of the CCD camera. For all of the Cr defects from the size of 0.6 μm to that of 10 μm we succeeded to detect the interference fringes between the scattered beam and the reference beam.
In order to accurately measure narrow space patterns, we propose an improved secondary-electron extraction efficiency model for the model-based library (MBL) method. In the conventional model, the same extraction efficiency is applied to all electrons, regardless of where they are emitted from. This is a simplified model assuming a uniform extraction electric field strength. In the improved model, the extraction efficiency is calculated as a function of the pattern shape and the emission position of the electrons. The function is based on simulation results for the electric field strength of critical-dimension scanning electron microscopy (CD-SEM) optics. We verify the effectiveness of the improved extraction model by applying it to actual patterns with space widths in the range 20 to 30 nm. The measurement bias of the sidewall angle (SWA) is evaluated through comparison with cross-sectional SEM measurements. We show that the average SWA bias is improved from 0.8° for the conventional model to 0.04° for the improved model.
The deposition of residually stressed films in semiconductor manufacturing processes introduces elastic distortions in the wafer that can contribute to overlay errors in lithographic patterning. The distortion induced by film deposition causes out-of-plane distortion (i.e. wafer shape) that can be measured with commercial metrology tools as well as in-plane distortion that leads to overlay errors. In the present work, overlay errors and out-of-plane distortion of wafers resulting from residual stresses that are non-uniform over the area of wafer are examined using computational mechanics modeling. The results of these simulations are used to examine the correlations between wafer shape features and overlay errors. Specifically, connections between overlay errors and metrics based on the slope of the wafer shape are assessed.
The stage synchronization (vibration) performance highly impacts image quality, especially for ArF immersion tool due to high NA and high scan speed is used. But it is very difficult to judge scanner stage vibration effect by measuring CD impact since different factors such as energy, focus, PEB temperature may cause CD variation and cannot be decoupled. This problem can be solved by using a focus-energy regression model based Scatterometry CD measurement. Exposed wafers by ArF immersion scanner with different scan speed are measured by Scatterometry with 12X13 intra field measurement points. Then the data is regressed by the focus-energy model to separate the factors of energy, focus (z direction), and fitting error (other factors include x, y direction). Based on the regression result, stripes can be clearly seen in the focus and fitting error map which indicates the vibration distribution. By reducing the stage scan speed, the fitting error can be significantly reduced.
As the dimensions of integrated circuit continue to shrink, diffraction based overlay (DBO) technologies have been developed to address the tighter overlay control challenges. Previously data of high accuracy and high precision were reported for litho-etch-litho-etch double patterning (DP) process using normal incidence spectroscopic reflectometry on specially designed targets composed of 1D gratings in x and y directions. Two measurement methods, empirical algorithm (eDBO) using four pads per direction (2x4 target) and modeling based algorithm (mDBO) using two pads per direction (2x2 target) were performed. In this work, we apply DBO techniques to measure overlay errors for a different DP process, litho-freeze-litho-etch process. We explore the possibility of further reducing number of pads in a DBO target using mDBO. For standard targets composed of 1D gratings, we reported results for eDBO 2x4 targets, mDBO 2x2 targets, and mDBO 2x1 target. The results of all three types of targets are comparable in terms of accuracy, dynamic precision, and TIS. TMU (not including tool matching) is less than 0.1nm. In addition, we investigated the possibility of measuring overlay with one single pad that contains 2D gratings. We achieved good correlation to blossom measurements. TMU (not including tool matching) is ~ 0.2nm. To our best knowledge, this is the first time that DBO results are reported on a single pad. eDBO allows quick recipe setup but takes more space and measurement time. Although mDBO needs details of optical properties and modeling, it offers smaller total target size and much faster throughput, which is important in high volume manufacturing environment.
Moore's Law continues to drive improvements to lithographic resolution to increase integrated circuit transistor density, improve performance, and reduce cost. For the 22 nm node and beyond, extreme ultraviolet lithography (EUVL) is a promising technology with λ=13.5 nm, a larger k1 value and lower cost of ownership than other available technologies. For small feature sizes, process control will be increasingly challenging, as small features will create measurement uncertainties, yet with tighter specifications. Optical scatterometry is a primary candidate metrology for EUV lithography process control. Using simulation and experimental data, this work will explore scatterometry's application to a typical lithography process being used for EUV development, which should be representative of lithography processes that will be utilized for EUV High Volume manufacturing (HVM). EUV lithography will be performed using much thinner photoresist thicknesses than were used at the 248nm or 193nm lithography generations, and will probably include underlayers for adhesion improvement; these new processes conditions were investigated in this metrological study.
The Multiple Detector CD-SEM acquires the secondary electron from pattern surface at each detector. The 3D shape and height of mask patterns are generated by adding or subtracting signal profile of each detector. In signal profile of the differential image formed in difference between left and right detector signal, including concavo-convex information of mask patterns. Therefore, the 3D shape of mask patterns can be obtained by integrating differential signal profile. This time, we found that proportional relation between pattern height and shadow length on one side of pattern edge. In this paper, we will report experimental results of pattern height measurement. The accuracy of measurement and side wall angle dependency are studied. The proposal method is applied to OMOG masks.
The earliest semiconductor device manufacturing employed optical microscopes for measurement and control of the manufacturing process. The introduction of the Critical Dimension Scanning Electron Microscope (CD-SEM) in 1984 provided a tremendous increase in capability for process monitoring and has been the standard for in-line metrology for over 25 years. The advantages of the CD-SEM are highly accurate and stable measurement reproducibility at very specific locations throughout the device. The evolution of the CD-SEM in Metrology has included improved resolution, development of advanced measurement and pattern recognition algorithms, all required by performance improvement demands from the market. Current conventional metrology using the in-line CD-SEM involves measuring about ten points per wafer (one point per one chip). at a magnification of over x150k(Field of View is about 1μm2). In contrast, the area of measurement pattern on chip is much larger than the area of CD-SEM measurement (mm2 : (on chip) versus μm2 : (CD-SEM measurement)). This would mean that the result of the CD-SEM measurement is influenced by local pattern variation. The very stringent requirements placed on in-line Metrology for the last couple of technology nodes has produced an additional metrology methodology, beyond the CD-SEM, that involves large area measurements with very high precision for the most critical levels. We will refer to this methodology as "Macro Area Measurements". We investigated the applicability of using a CD-SEM Macro Area Measurement methodology in this paper. The areas investigated focused on the following points: 1) Determining the optimum CD-SEM sampling plan for a macro area measurement. 2) Optimization of the measurement parameters. 3) Optimization of the measurement condition. 4) Verification of Macro Area Measurement with an FEM (Focus Exposure Matrix) wafer. In the results, we are able to validate a new methodology that we called "Macro Area Measurement" which is demonstrated to successfully detect small process variations with the same throughput and reduced damage to the pattern.
EUV mask metrology and inspection challenges as well as EUV patterned wafer metrology and inspection strategies must be addressed to enable EUV patterning for pilot and high volume production. In this work we present a defectivity analysis of defects from post EUV lithography and etch and the correlation between them on 40nm and 28nm half pitch (HP) line/space structures. The objective of the work was to study the lithography and etch process window vs. pitch as well as to characterize the performance of a DUV brightfield wafer inspection system on EUV stacks in order to detect EUV related DOI's. In addition to defect characterization for the lithography and etch layers, we present the results of scattering simulation from these layers, with polarized 266nm DUV illumination, to provide insight on the light-pattern interaction and on the critical detection parameters.
In recent years, layer-to-layer overlay methods moved from the linear regime into non-linear high-order methods in order to meet the shrinking overlay requirements. In this study we investigate a large number of metrology structures in the overlapped scribe-line between adjacent scanner fields and the opportunity for improved overlay performance. Sampling and modeling considerations are discussed. In this investigation we consider the opportunities for high-order stitching analysis in process control and scanner monitoring. The goal of this work is to establish a systematic methodology for high order stitching to characterize and reduce overlay errors for advanced IC manufacturing.
The fabrication of semiconductor devices can be complicated by various defectivity issues with respect to fabrication process steps, their interactions, the used materials and tool settings. In this paper we will focus on a defect type, called spire or cone defect. This conducting defect type is very common in the shallow trench isolation (STI) process. The presence of a single defect can be responsible for a device breakdown or reliability problems, which will result in a serious impact on the competitive edge for a product qualification. Spire defects, which can only be detected after etch, are observed on all our technology nodes using 248nm or 193nm exposure techniques. Bottom Anti-Reflection Coatings (BARC) impurities are considered to be the main root cause for the formation of spire defects. Therefore we focused our efforts on chemical filtration of the BARC material and related solvents, the usage of different BARC materials and the influence of the subsequent etch steps in order to reduce or overcome the spire defect problem. In this paper we will discuss the effectiveness of different filter materials, pore sizes and different BARC materials (organic and dielectric BARC) with respect to defect analysis and lithographic performance.
We fabricated sub-50-nm pitch reference grating with positional identification mark for specifying the location. The address mark of silicon groove was fabricated by EB lithography and dry etching processes. The sub-50-nm pitch multilayer substrate was bonded with the address mark silicon substrate and polished as a flat chip. Next the fine pitch grating reference pattern was fabricated by SiO2 selective chemical etching. Finally the sub-50-nm pitch grating pattern was set on the flat surface for CD-SEM due to retarding bias system for low voltage inspection. As a result of the fundamental characteristics evaluation using CD-SEM, the uniformity of the pitch size in the reference chip was smaller than 1 nm in 3σ. The positional identification marks are useful for obtaining accurate calibrations by specifying the location of the grating and the number of calibrations. Also, the pitch-size was obtained by diffraction angle measurements with a high-accuracy grazing incidence small-angle x-ray scattering (GI-SAXS). The traceability of calibration is under vertification.
Mask manufacturers will be impacted by two significant technology requirements at 22nm and below: The first is more extensive use of resolution enhancement technologies (RET), such as OPC or Inverse Lithography Technology (ILT), and Source Mask Optimization (SMO); the second is EUV technology. Both will create difficulties for mask inspection, defect disposition, metrology, review, and repair. For example, the use of ILT and SMO significantly increases mask complexity, making mask defect disposition more challenging than ever. EUV actinic inspection and AIMSTM will not be available for at least a few years, which makes EUV defect inspection and disposition more difficult, particularly regarding multilayer defects. Computational Lithography and Inspection (CLI), which has broad applications in mask inspection, metrology, review, and repair, has become essential to fill this technology gap. In this paper, several such CLI applications are presented and discussed.
It is known that different overlay mark designs will have different responses to process setup conditions. An overlay mark optimized for the 45nm technology node might not be suitable for wafers using 30nm or 20nm process technologies due to changes in lithography and process conditions. As overlay control specifications become tighter and tighter, the process engineer requires metrics beyond precision, tool-induced shift (TIS) and TIS variability to determine the optimal target design. In this paper, the authors demonstrate a novel, comprehensive methodology which employs source of variance (SOV) to help engineers select the best overlay marks to meet overlay control requirements.
Reticle Pattern Placement Error (PPE) has been identified as one of the key challenges of Double-Patterning Lithography (DPL) as the overlay of the circuit patterns between two masks is a critical achievement for successful implementation of the process. According to the 2009 ITRS roadmap, double-patterning lithography is expected to extend 193nm immersion lithography to the 23nm node by 2016 and the corresponding PPE requirements is 1.9nm. PPE between the two masks comprising a DPL mask pair affects the resulting critical dimensions of the circuit pattern and the final device performance. In this paper, we study how the reticle PPE can be affected by the pellicle. The pellicle can induce a mechanical stress on the reticle such that the actual placement of the circuit patterns on wafer will be distorted after the lithography process. This distortion effect is known as Pellicle-Induced Distortion (PID). We conducted experiments by using different combinations of pellicle frames and frame adhesives on a DPL mask pair to study how reticle PPE can change with each combination. We used the KLA-Tencor LMS IPRO4 mask registration metrology tool to measure the PPE before and after the mount/un-mount of each experiment combination. The analysis is done using the KLA-Tencor DEVA software to quantify how the pellicle can affect the individual reticle PPE and also the relative errors between the DPL mask pair.
Metrology on 3D features like contact holes (CH) is more challenging than on lines and spaces (L/S) structures especially if one wants to have profile information. Scatterometry has been widely used on L/S structures and has enabled characterization of lithographic features providing with critical dimensions (CD) as well as feature height and side wall angle. In this paper, we will present the application of scatterometry to the measurement of 3D structures using an angle resolved polarized scatterometer: ASML YieldStar S-100. Contact hole measurements will be presented and correlation to standard metrology tools will be shown. Measurement capability will be discussed in terms of reproducibility, calculation time, sensitivity of the parameters of interest and correlation between them leading to a proper model choice. Finally initial results on more complex 3D features (line ends, brick walls,...) will be presented.
We have been developing a resist loss measurement function which is based on quantified pattern top roughness. In order to use practically the resist loss detection function, the PTR index must be calibrated to amount of resist loss. Furthermore, the evaluation of different chemical formulation and different film thicknesses of the resist is also required. In this study, we explore the calibration technique of resist loss detection. In order to convert measured PTR index into amount of resist loss, a reference measurement to pattern height is required. Techniques that can measure local pattern height are limited to off-line techniques such as AFM or cross-sectional SEM with current technology. These techniques have a very long Turnaround Time (TAT), and also highly skilled engineer is required, it cannot be used for in-line processing. Then, we examined the reasonable calibration method by short TAT. At first, the calibration wafer with changed resist film thickness is exposed using an "open frame" condition. It is measured by an optical film thickness metrology (FTM) tool and CD-SEM, a conversion factor is determined and converted PTR index of measured target patterns into resist loss amount. The validity of converted resist loss amount by this method has been proven by comparing to the resist height obtained by AFM and cross-sectional SEM images. The calibration technique using PTR index of un-patterned resist allowed us to understand the relationship between un-patterned resist thickness and resist surface roughness. We have demonstrated a simple and easy way to calibrate pattern resist loss using CD-SEM top-down images.
Airborne molecular contamination (AMC) assessment approaches can vary greatly between different fabs and even between different divisions within a given company. Some companies have very rigorous testing schedules (such as those needed to maintain tool warranties) while others feel AMC testing is only necessary when they are having a problem. While choosing to only test for AMC when a trouble arises may be cost effective in the short term it can have significant impacts on tools, in particular tool optics, and product losses due to defects which can cost significantly more in the long term than the AMC testing would have. Another critical issue in assessing AMC is what species you should be testing for. Some volatile species may not cause an issue in your process while part-per-trillion volume (pptv) amounts of others can do serious damage to your tools and/or products. Knowledge of which volatile compounds can cause problems in your applications and at what levels is crucial in deciding what type of AMC assessment to perform and at what frequency. Typically four classes of AMC are routinely monitored in clean rooms and tool environments: acids, bases, hydrocarbons, and refractory compounds. Real world examples will be presented using the solely solid-state trap collection methods utilized by SAES Pure Gas.
As DRAM design rules scale below 4Xnm, controlling the micro-step height caused by the etching process after patterning becomes more critical because it affects the post Chemical Mechanical Planarization (CMP) process window and furthermore affects yield. In this study, the latest Multi-Azimuth angle capability of Scatterometry Critical Dimension (SCD) was used to analyze the model of the micro-step height of nitride. SCD results were verified with Atomic Force Microscope (AFM) measurements.
With reduction of design rules, a number of corresponding new technologies, such as i-HOPC, HOWA and DBO have been proposed and applied to eliminate overlay error. When these technologies are in use, any high-order error distribution needs to be clearly distinguished in order to remove the underlying causes. Lens aberrations are normally thought to mainly impact the Matching Machine Overlay (MMO). However, when using Image-Based overlay (IBO) measurement tools, aberrations become the dominant influence on single machine overlay (SMO) and even on stage repeatability performance. In this paper, several measurements of the error distributions of the lens of SMEE SSB600/10 prototype exposure tool are presented. Models that characterize the primary influence from lens magnification, high order distortion, coma aberration and telecentricity are shown. The contribution to stage repeatability (as measured with IBO tools) from the above errors was predicted with simulator and compared to experiments. Finally, the drift of every lens distortion that impact to SMO over several days was monitored and matched with the result of measurements.
As the semiconductor feature size continues to shrink, the thickness of photo resist needs to be thinner and thinner to prevent resist features from collapse. Coupling with the need of high NA lithography for small feature patterning, both the reflectance control and the etch budget on resist thickness are becoming major challenges for lithographers. One way to simultaneously satisfy the needs of superior low reflectance, sufficient etch resistance and minimizing the resist feature collapse is adopting tri-layer lithography scheme. The tri-layer scheme has been successfully implemented in our manufacturing flow for FEOL (Front-End-of-Line) application. This work investigated the application of tri-layer scheme to BEOL (Back-End-of-Line) AlCu patterning. One critical problem met in this application is the defect that majorly originates from wafer edge after AlCu patterning. The defects were finally ascribed to the hump formation of Si-rich hard-mask by EBR (Edge Bead Removal) process. The hump of Si-rich hard-mask yields etch masking behavior during AlCu etch accordingly leads to pattern bridging or peeling of inorganic hard-mask after AlCu patterning. To reduce the defect, several evaluations were made to suppress the hump formation, including the EBR optimization, bake condition of Si-rich hard-mask, film stacking architecture of tri-layer by EBR rinse and surfactant additive added Si-rich hard-mask. A synergy effect among process factors has been proposed to effectively fix the defect problem around wafer edge.
As semiconductor process design rules continue to shrink, the ability of optical inspection tools to separate between true defects and nuisance becomes more and more difficult. Therefore, monitoring Defect of Interest (DOI) become a real challenge (Figure 1). This phenomenon occurs due to the lower signal received from real defects while noise levels remain almost the same, resulting in inspection high nuisance rate, which jeopardizes the ability to provide a meaningful, true defect Pareto. A non-representative defect Pareto creates a real challenge to a reliable process monitoring (Figure 4). Traditionally, inspection tool recipes were optimized to keep data load at a manageable level and provide defect maps with ~10% nuisance rate, but as defects of interest get smaller with design rule shrinkage, this requirement results in a painful compromise in detection sensitivity. The inspection is usually followed by defect review and classification using scanning electron microscope (SEM), the classification done manually and it is performed on a small sample of the inspection defect map due to time and manual resources limitations. Sample is usually 50~60 randomly selected locations, review is performed manually most of the times, and manual classification is performed for all the reviewed locations. In the approach described in this paper, the inspection tool recipe is optimized for sensitivity rather than low nuisance rate (i.e. detect all DOI with compromising on a higher nuisance rate). Inspection results with high nuisance rate introduce new challenges for SEM review methodology & tools. This paper describe a new approach which enhances process monitoring quality and the results of collaborative work of the Process Diagnostic & Control Business Unit of Applied Materials® and GLOBALFOUNDRIES® utilizing Applied Materials ADRTrueTM & SEMVisionTM capabilities. The study shows that the new approach reveals new defect types in the Pareto, and improves the ability to monitor the process and identify excursion for low magnitude defect of interest.
Lithographic tool performance is the main contributor to CDU. The tool designers and users require an accurate method to measure the tool's error factors on the wafer side in order to improve CDU. Engineers typically use the FEM method to estimate DOF and EL, and then predict the CDU. However, based on the exposure data, it is often difficult to separate systematic level physical errors, such as DOSE repeatability, focus repeatability, dynamic errors and all the other tool's imperfections. In this paper, we introduce a wafer data based method to diagnose tool's performance for CDU improvement. As the systematic errors have a specific signature, they generate a fingerprint in the exposure data. Based on the knowledge of the exposure process and process flow, multiple dimensions exposure matrix is designed to analyze and diagnose the tool's systematic error from wafer data fingerprint. For SMEE's scanner tool (SSA600/10), we use this method to diagnose tool's systematic error and improve the CDU. Some typical result is represented in this paper.
This paper discusses the scatterometry-based metrology measurement of 28nm high k metal gate after-develop inspection (ADI) and after-etch inspection (AEI) layer structures. For these structures, the critical measurement parameters include side wall angle (SWA) and critical dimension (CD). For production process control of these structures, a metrology tool must utilize a non-destructive measurement technique, and have high sensitivity, precision and throughput. Spectroscopic critical dimension (SCD) metrology tools have been implemented in production for process control of traditional poly gate structures. For today's complex metal gate devices, extended SCD technologies are required. KLA-Tencor's new SpectraShape 8810 uses multi-azimuth angles and multi-channel optics to produce the high sensitivity and precision required for measurement of critical parameters on metal gate structures. Data from process of record (POR), focus-exposure matrix (FEM) and design of experiment (DOE) wafers are presented showing the performance of this new SCD tool on metal gate ADI and AEI process structures. Metal gate AEI scatterometry measurement results are also compared to transmission electron microscopy (TEM) reference measurements. These data suggest that the SpectraShape 8810 has the required sensitivity and precision to serve as a production process monitor for 28nm and beyond complex metal gate structures.
Information is 'key'. Timely information in a fab environment provides substantial insight into the Mask quality, process health, steps needed to improve yield and throughout time. Ideal for mask and wafer fabs, the RS-Mini central server brings the inspection tool's terminal to the end user via a desktop application. Hundreds of users can simultaneously classify (with automation capability), annotate repair history, query and summarize year's worth of inspection results with images from tens of tools, as well as establish defect and process health trends in a matter of seconds. The RS-Mini, a low cost, state of the art mask defect management framework delivering a highly integrated rich user experience, fits in a compact rack mountable server blade less than 2 inches in thickness.
Accurate wavefront aberration measurement are essential for next-generation Extreme Ultraviolet (EUV) Lithography. During the past years several accurate interferometric techniques have been developed, but these techniques have limitation. In this work we discuss a different technique based on the Hartmann Wavefront Sensor that requires no interferometry. We present a mathematical model of this system and describe our experimental setup which demonstrates the feasibility and advantages in terms of dynamic range and accuracy compared to interferometric techniques.
Overlay performance will be increasingly important for Spacer Patterning Technology (SPT) and Double Patterning Technology (DPT) as various Resolution Enhancement Techniques are employed to extend the resolution limits of lithography. Continuous shrinkage of devices makes overlay accuracy one of the most critical issues while overlay performance is completely dependent on exposure tool. Image Based Overlay (IBO) has been used as the mainstream metrology for overlay by the main memory IC companies, but IBO is not suitable for some critical layers due to the poor Tool Induced Shift (TIS) values. Hence new overlay metrology is required to improve the overlay measurement accuracy. Diffraction Based Overlay (DBO) is regarded to be an alternative metrology to IBO for more accurate measurements and reduction of reading errors. Good overlay performances of DBO have been reported in many articles. However applying DBO for SPT and DPT layers poses extra challenges for target design. New vernier designs are considered for different DPT and SPT schemes to meet overlay target in DBO system. In this paper, we optimize the design of the DBO target and the performance of DBO to meet the overlay specification of sub-3x nm devices which are using SPT and DPT processes. We show that the appropriate vernier design yields excellent overlay performance in residual and TIS. The paper also demonstrated the effects of vernier structure on overlay accuracy from SEM analysis.
Critical Dimension Scanning Electron Microscope (CD-SEM) recipe creation needs sample preparation necessary for matching pattern registration, and recipe creation on CD-SEM using the sample, which hinders the reduction in test production cost and time in semiconductor manufacturing factories. From the perspective of cost reduction and improvement of the test production efficiency, automated CD-SEM recipe creation without the sample preparation and the manual operation has been important in the production lines. For the automated CD-SEM recipe creation, we have introduced RecipeDirector (RD) that enables the recipe creation by using Computer-Aided Design (CAD) data and text data that includes measurement information. We have developed a system that automatically creates the CAD data and the text data necessary for the recipe creation on RD; and, for the elimination of the manual operation, we have enhanced RD so that all measurement information can be specified in the text data. As a result, we have established an automated CD-SEM recipe creation system without the sample preparation and the manual operation. For the introduction of the CD-SEM recipe creation system using RD to the production lines, the accuracy of the pattern matching was an issue. The shape of design templates for the matching created from the CAD data was different from that of SEM images in vision. Thus, a development of robust pattern matching algorithm that considers the shape difference was needed. The addition of image processing of the templates for the matching and shape processing of the CAD patterns in the lower layer has enabled the robust pattern matching. This paper describes the automated CD-SEM recipe creation technology for the production lines without the sample preparation and the manual operation using RD applied in Sony Semiconductor Kyusyu Corporation Kumamoto Technology Center (SCK Corporation Kumamoto TEC).


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text:
Acer Will Use Moblin Linux Across Its Products
By Dan Nystedt
The world's third-largest PC vendor plans to roll out the Moblin Linux operating system, championed by Intel, in its products, a top executive said Wednesday.
"Acer is in the process of putting Moblin in the range of its products," said R.C. Chang, chief technology officer at Acer, at a news conference in Taipei. Acer products that will soon run with Moblin Linux include Aspire One nettops, as well as regular laptop and desktop PCs, he said.
Aspire One netbooks already running Moblin were on display at the news conference. Moblin was developed for netbooks, which are mini-laptops built for mobility with low-power microprocessors, 10-inch screens and six-cell batteries for long run times. An updated version of the operating system, Moblin 2.0, was released last month, and it has proven popular at Computex Taipei 2009.
A number of netbooks were on display at the news conference, running several different versions of Moblin on various netbooks, including Suse Moblin, Xandros Moblin, Linpus Moblin, Red Flag Moblin and Ubuntu Moblin running on netbooks from Hewlett-Packard, Asustek Computer, Micro-Star International and Hasee Computer.
There were also a few handheld computers, which Intel calls mobile Internet devices, running Moblin 2.0. BenQ displayed its new S6 MID running on Moblin, while Compal Electronics showed off an MID with a slide-out QWERTY keypad.
Ellis Wang, software product marketing director at Asustek Computer, showed off an Eee Keyboard, which is a keyboard with a built-in LCD screen and computer, with a Moblin OS at the conference.
Moblin 2.0 has met with some controversy since its launch. The easy use and nice look of the software has prompted several reports to call chip giant Intel an OS company, and Moblin 2.0 a rival to Windows in netbooks. Moblin 2.0 offers a number of improvements over the previous version, including an improved user interface, quick boot-up and easy connections to messaging and social networking sites such as Facebook.
Doug Fisher, vice president of the software and services group at Intel, said his team is aiming for a 5-second bootup for Moblin because mobile users are accustomed to quick boot-up times. The company also continues to optimize Moblin to squeeze the most power savings possible out of its Atom microprocessors, he said.

redpajama_set_name: RedPajamaCommonCrawl