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Jennifer Trimble
Associate Professor of Classics
Jennifer Trimble works on the visual and material culture of the Roman Empire, with interests in portraits and replication, the visual culture of Roman slavery, comparative urbanism, and ancient mapping. Her book on Women and Visual Replication in Roman Imperial Art and Culture (Cambridge University Press, 2011) explores the role of visual sameness in constructing public identity and articulating empire and place. Trimble was co-director of the IRC-Oxford-Stanford excavations in the Roman Forum (now being prepared for publication), focused on the interactions of commercial, religious and monumental space. She also co-directed Stanford's Digital Forma Urbis Romae Project, a collaboration between computer scientists and archaeologists to help reassemble a fragmentary ancient map of the city of Rome.
Associate Professor, Classics
Associate Professor, Department of Classics, Stanford University (2008 - Present)
Associate Professor, Dept. of Classics, Stanford University (2005 - 2008)
Assistant Professor, Department of Classics, Stanford University (2001 - 2008)
Acting Assistant Professor, Department of Classics, Stanford University (1999 - 2001)
Ellen Andrews Wright Fellow, Stanford Humanities Center (2012 - 2013)
Hellman Faculty Scholar, Stanford University (2005 - 2006)
Dean's Fellow in the Humanities, Stanford University (2005 - 2006)
Visiting Scholar, Corpus Christi College, University of Oxford (2004 - 2004)
Mellon Postdoctoral Fellowship, Humanities, Stanford (1999 - 2001)
Predoctoral Fellowship, Institute for the Humanities, Michigan (1998 - 1999)
Mellon Predoctoral Fellowship, University of Michigan (1998 - 1999)
Predoctoral Fellowship, American Research Institute in Turkey (1997 - 1997)
Travel Fellowship, History of Art, Samuel H. Kress Foundation (1997 - 1997)
Mellon Candidacy Fellowship, University of Michigan (1996 - 1996)
Regents Rackham Fellowship, University of Michigan (1993 - 1996)
Dean's Award for Distinguished Teaching, Stanford University (2005)
Distinguished Dissertation Award, University of Michigan (2000)
Rome Prize, American Academy in Rome (1997-1998)
Co-director, IRC-Oxford-Stanford Excavations in the Roman Forum (2003 - 2005)
Co-director, Stanford Digital Forma Urbis Romae Project (2000 - 2004)
Director, magnetometry survey, Monte Polizzo, Sicily (2001 - 2001)
Director, magn. survey, Statonia, Etruria (1998 - 1999)
Trench supervisor; field survey team member, Leptiminus, Tunisia (1995 - 1996)
Archaeological Investigator, Psalmodi, France (1995 - 1995)
Supervisor, numismatics, Sardis, Turkey (1992 - 1993)
Student excavator, Kelheim, Germany (1990 - 1990)
Member, Curriculum committee, Stanford Archaeology Center, Stanford University (2013 - 2014)
Member, Archaeology advisory committee, American Academy in Rome, Stanford University (2012 - Present)
Member, Fellowships committee, Archaeological Institute of America, Stanford University (2012 - Present)
Stanford representative, Intercollegiate Center for Classical Studies in Rome, Stanford University (2001 - 2004)
Head of search committee, Department of Classics, Stanford University (2011 - 2012)
Interim director, Stanford Archaeology Center, Stanford University (2009 - 2010)
Director of graduate studies, Department of Classics, Stanford University (2008 - 2011)
Member, Graduate committee, Department of Classics, Stanford University (2007 - 2008)
Director of undergraduate studies, Department of Classics, Stanford University (2003 - 2004)
Member, Undergraduate committee, Department of Classics, Stanford University (2005 - 2007)
Member, Finance committee, Stanford Archaeology Center, Stanford University (2007 - 2008)
Advisory Board, Berliner Studien zum antiken Rom (2012 - Present)
Editorial Board, Classical Antiquity (2000 - 2008)
Article referee, Journal of Roman Archaeology
Article referee, American Antiquity
Article referee, American Journal of Archaeology
Article referee, Journal of Social Archaeology
Article referee, Papers of the British School at Rome
Article referee, Classical Antiquity
Grant referee, National Geographic- Committee for Research and Exploration
B.A., Bryn Mawr College, English (1986)
M.A., Harvard University, Classical Art and Archaeology (1994)
M.A., University of Michigan, Latin (1999)
Ph.D., University of Michigan, Classical Art and Archaeology (1999)
trimble@stanford.edu
University - Faculty Department:&nbspClassics Position: Assoc Professor
450 JANE STANFORD WAY, BLDG. 110
Directed Reading in Classics (Graduate Students)
CLASSICS 298 (Aut, Win, Spr)
Directed Readings (Undergraduate)
Dissertation Proposal Preparation
Senior Honors Thesis
URBANST 199 (Win)
Undergraduate Thesis: Senior Research
Roman Gladiators
CLASSICS 164 (Spr)
Space and Mapping
CLASSICS 354 (Win)
Developing a Classics Dissertation Prospectus
Topics in Roman Art and Visual Culture
Archaeology of Roman Slavery
Gender and Power in Ancient Rome
CLASSICS 36 (Spr)
Doctoral Dissertation Reader (AC)
Thomas Leibundgut
Doctoral Dissertation Advisor (AC)
Serena Crosson, Kevin Ennis, Paula Gaither, Guoshi Li, Catherine Teitz
Sinead Brennan-McMahon, Guoshi Li, Matthew Previto
Welcome from the new editors JOURNAL OF ROMAN ARCHAEOLOGY Trimble, J., Ben Russell, Van Oyen, A., Leidwanger, J. 2021; 34 (1): 1-2
View details for DOI 10.1017/S1047759421000398
Women, Art, Power, and Work in the House of the Chaste Lovers at Pompeii WOMEN'S LIVES, WOMEN'S VOICES Trimble, J., Longfellow, B., SwetnamBurland, M. 2021: 199-215
GENDER AND BODY LANGUAGE IN ROMAN ART (Book Review) JOURNAL OF ROMAN ARCHAEOLOGY Book Review Authored by: Trimble, J. 2019; 32: 605–11
GENDER, IDENTITY AND THE BODY IN GREEK AND ROMAN SCULPTURE (Book Review) JOURNAL OF ROMAN ARCHAEOLOGY Book Review Authored by: Trimble, J. 2019; 32: 605–11
Figure and ornament, death and transformation in the Tomb of the Haterii Trimble, J., Dietrich, N., Squire, M. WALTER DE GRUYTER GMBH. 2018: 327–52
The Zoninus Collar and the Archaeology of Roman Slavery AMERICAN JOURNAL OF ARCHAEOLOGY Trimble, J. 2016; 120 (3): 447-472
View details for DOI 10.3764/aja.120.3.0447
Urban Spaces New book series Trible, J., de Gruyter, W. edited by Trimble, J., Muth, S., Wulf-Rhcidt, U. URBS. Berlin. 2012
Women and Visual Replication in Roman Imperial Art and Culture Series: Greek Culture in the Roman World Trimble, J. edited by Alcock, S., Elsner, J., Goldhill, S. Cambridge University Press. 2011
The Herculaneum Woman statue types and their ongoing history Journal of Roman Archaeology Trimble, J. 2009; 22: 592-600
Process and Transformation on the Severan Marble Plan Cartography in Antiquity and the Middle Ages: Fresh Perspectives, New Methods Trimble, J. edited by Richard, J. A., Unger, R. W. Brill. 2008: 67–97
Pharaonic Egypt and the Ara Pacis in Augustan Rome Princeton-Stanford Working Papers in Classics Trimble, J. 2007
Visibility and Viewing on The Severan Marble Plan Severan Culture Trimble, J. edited by Swain, S., Harrison, S., Elsner, J. Cambridge University Press. 2007: 368–84
Statues in Roman society: Representation and response (Book Review) JOURNAL OF ROMAN STUDIES Book Review Authored by: Trimble, J. 2007; 97: 338-340
Art and Replication: Greece, Rome and Beyond. Special issue of Art History Trimble, J. edited by Trimble, J., Elsner, J. 2006; 29 (2)
Introduction: If You Need an Actual Statue Art and Replication: Greece, Rome and Beyond. Art Histmy Trimble, J., Elsner, J. edited by Trimble, J., Elsner, J. 2006: 201–212
Rome as Souvenir: the Septizodium and the Severan Marble Plan Proceedings of the XVI International Congress of Classical Archaeology Trimble, J. edited by Mattusch, C., Donohue, A. A., Brauer, A. 2006: 106–9
Rome the Cosmopolis Bryn Mawr Classical Reviews Trimble, J. 2004
Ancient maps and mapping in and around Rome Journal of Roman Archaeology Trimble, J. 2004; 17: 577-583
Magnetometry Survey at Monte Polizzo, Sicily Memoirs of the American Academy in Rome Trimble, J., Platt, D. 2003; 48: 317-333
Understanding Muse and Philosopher Imagery Journal of Roman Archaeology Trimble, J. 2002; 15: 507-510
Greek Myth, Gender, and Social Structure in a Roman House: Two Paintings of Achilles at Pompeii The Ancient Art of Emulation: Studies in Artistic Originality and Traditionfi·om the Present to Classical Antiquity. Memoirs of the American Academy in Rome, Supp. 1 Trimble, J. edited by Gazda, E. K. University of Michigan. 2002: 225–248
Oltre Ia Grecia: Aile origini delfilellenismo di Adriano Gnomon Trimble, J. 2001; 73: 236-241
Rethinking 'Romanization' in Early Imperial Greece: Butrint, Corinth and Nicopolis Journal of Roman Archaeology Trimble, J. 2001; 14: 625-628
Antiquarian delights - Rome unveils three splendid museums ARCHAEOLOGY DYSON, S. L., Trimble, J. 2000; 53 (1): 34-35
Replicating the Body Politic: the Herculaneum Women Statue Types in Early Imperial Italy Journal of Roman Archaeology Trimble, J. 2000; 13: 41-68
Untersuchungen zu den kaiserzeitlichen Togastatuen Griechischer Provenienz American Journal of Archaeology Trimble, J. 2000; 104: 145-146
Fayum Portraits in the Kelsey Museum of Archaeology: Representing Gender and Status in Roman Egypt Women and Gender in Ancient Egypt From Prehislmy to Late Antiquity Trimble, J. edited by Wilfong, T. G. Ann Arbor. 1997: 58–64
Preserving Life: A Fertility Statue Preserving Eternity: Modern Goals, Ancient Intentions. Egyptian Funerary Art(facts in the Kelsey Museum of Archaeology Trimble, J. edited by Richards, J. E., Wilfong, T. G. Ann Arbor. 1995: 20–21


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Kaj Sierhuis (born 27 April 1998) is a Dutch professional footballer who plays as a forward for Ligue 1 club Reims.

Club career

Ajax
Sierhuis was born in Athens, Greece, on 27 April 1998, when his father, Cock Sierhuis, was president of AEK Athens. The family returned to the Netherlands when Kaj was four years old, and he grew up in Jisp, North Holland.

He had started playing football with WSV '30 in Wormer in the province of North Holland as a five-year-old before moving the to Ajax Youth Academy at age 11. In August 2016, he signed his first professional contract and made his first appearances for Jong Ajax on 25 November 2016 in an Eerste Divisie match against Telstar. That season he also continued to play for the under-19 team in the league and in the UEFA Youth League. In the 2016–17 season, he was top goalscorer in the UEFA Youth League alongside Jordi Mboula of Barcelona. In the 2017–18 season, Sierhuis, who had outgrown the youth teams, was not always part of the regular lineup, but scored 14 goals in 20 appearances and became second-tier Eerste Divisie champion with Ajax's second team, which could however not win promotion due to Dutch league rules. Sierhuis made his first competitive appearance for the Ajax first team on 25 July 2018 in a 2–0 win in the UEFA Champions League second qualifying round against Sturm Graz.

After making just two appearances in the Eredivisie, Sierhuis agreed to a loan move to Groningen until the end of the season with an option to buy. He quickly earned a starting place as Groningen qualified for play-offs for a place in the UEFA Europa League third qualifying round. There, the Groningen side was eliminated in the first round by Vitesse.

Reims
On 1 February 2020, Sierhuis signed with Ligue 1 club Reims on a long-term contract. He made his debut for the club on 5 February 2020, starting in a league game against Nice, but had to be replaced by Nathanaël Mbuku in the 13th minute after falling out with a hamstring injury. Due to the COVID-19 pandemic, this remained Sierhuis' only appearance for Reims in the 2019–20 season.

In the 2020–21 season, he made regular appearances for Reims, but his playing time decreased from the beginning of 2021 and he was sent on a one-season loan to Eredivisie club Heracles Almelo in August 2021. After 19 total appearances in which he scored one goal, he tore his anterior cruciate ligament on 11 February 2022 against Utrecht and was sidelined for the rest of the season.

He rejoined the Reims squad for the 2022–23 season.

Honours
Jong Ajax
 Eerste Divisie: 2017–18

References

External links

Living people
1998 births
Footballers from Athens
Association football forwards
Dutch footballers
Netherlands under-21 international footballers
Netherlands youth international footballers
Dutch expatriate footballers
AFC Ajax players
Jong Ajax players
FC Groningen players
Stade de Reims players
Heracles Almelo players
Eredivisie players
Eerste Divisie players
Ligue 1 players
Championnat National 2 players
Expatriate footballers in France
Dutch expatriate sportspeople in France

redpajama_set_name: RedPajamaWikipedia


THARG (Toponymy, History and Archaeology of the Kingdom of Granada) is an interdisciplinary research group based in the University of Granada. The main interest of our group is the study of the Middle Ages in all its complexity. A growing interest has born in the last decades about landscape. It has become one of the major fields of study within the group from a wide range of perspectives from that of archaeology to history, geography or geology.
The research group was created in 1989 with the aim of studying the Islamic presence on the land that would later be occupied by the Nasrid kingdom (basically the present provinces of Granada, Malaga and Almeria) and of the transformations that took place after the Castilian conquest (1492).
Within toponymy: publication of Arab documents and studies of major and minor toponymy.
Within medieval archaeology: the settlement, the ceramics, urban development and specific elements within them, such as castles and the Nasrid palace par excellence, the Alhambra, as well as the organisation of the spaces for economic exploitation (agricultural, pastoral, etc.).
Within medieval history: social structures and Nasrid and Castilian economics from the analysis of productive spaces (distribution of ownership of the land, social sharing of water, Christian re-settlement and formation of Castilian estates).
Study of Al-Andalus material culture.
Social organisation of the space.
Landscape archaeology and Cultural Landscapes.
Another publication that appears almost every year is the proceedings of a meeting held annually as well. The issues are related to Medieval archaeology in one way or another. Previous numbers dealt with landscape, archaeometry, rural and urban settlements among many other topics.
The transition between Late Antiquity and the Early Middle Ages. Excavation in the ancient city of Madinat Ilbira.
The relationship between salt and livestock, especially in the Late Middle Ages.
The end of the middle Ages and the beginning of the Modern period.


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Q: Counting license plates I would like to know how to find the total number of vehicles of a city using Number Plates in following conditions:
Number plate has following format:
AA 9999 (2 Alphabets followed by 4 numbers)
Each alphabet can combine with any of the alphabet (including self) and form the first part of the number plate.
Each combination (e.g. AA) can have numbers from 0000 to 9999 to it.
Based on this, can you please let me know max. number of vehicles that can be registered without changing numbering system?
Thanks!

A: Last year, there was a news article that spoke of the 'gross overspending' of a particular football team on new clothing. They said that the team bought enough clothing for a total of 32 different combinations. Why so many?
I was not impressed, nor mortified (except by the media). Looking into it, the team had 2 colors of helmet, jersey, pants, socks, and arm-covers (whatever they're called). So they had 2 complete uniforms. But when choosing what to wear, they had 2 choices of helmet, 2 choices of jersey, 2 of pants, 2 of socks, and 2 for their arms. In total, they had $2 \cdot 2 \cdot 2 \cdot 2 \cdot 2 = 2^5 = 32$ different choices.
What a gross overstatement.
Also, this is called the multiplication principle, and it's how you do this problem.

A: It is 26^2 * 10^4 = 6760000.  26 is the number of possible letters, 2 is the number of letters on the plate, 10 is the number of possible digits, 4 is the number of digits on the plate.  Now consider what if there are still 2 letters and 4 digits but the letters and numbers can be mixed together, for example "A11B59"?

redpajama_set_name: RedPajamaStackExchange


Meet up with fellow bands & artists, plan your projects, work on your tracks or simply just daydream at Rocklab's co-working space. Equipped with computers featuring digital audio software (Ableton Live, Logic) and useful online resources (tutorials, workshops) and a specialized media library as well as a relaxed lounge area, this space is dedicated to those who need an environment to get their work done or inspiration triggered. And with Rocklab's offices right around the corner, there's always a helping hand waiting with counsel and information.


St Benedict (AD 480-550) was the first recorded saint to create a garden at his monastery, as a place for prayer and contemplation. His was a rose garden or 'rosary'. It was St Fiacre (an Irish Saint) in 670, however, who became the first to plant a garden in honour of Our Lady, using those flowers which bore her name.
This idea quickly spread throughout Ireland and England, with many "Mary Gardens" being created to honour our Lady. These were places often close to a church, where people could go to spend quiet time in prayer with our Lady. They were often enclosed gardens with a simple statue of the Blessed Virgin, surrounded by the shrubs and flowers which had been named after her.
In Britain, so many plants originally had Marian names and meanings, that it was actually possible to have themed "Mary Gardens" based around particular attributes of Our Lady and her life – a garden specifically devoted to her virtues, or her earthly life, or her joys and sorrows for example. Mary Gardens flourished right up to the time of the Reformation.
The Marian names and symbolism of the flowers of pre-Reformation England were largely omitted from English herbals and gardening books produced in the 16th century. In a short space of time, 800 years of floral Marian connections and symbolism had disappeared from our gardens and countryside along with the monasteries and shrines.
In 1932, St Joseph's Church, Woods Hole, Massachusetts, decided to redress the balance, becoming the first church in the United States to plant a Mary Garden. For their inspiration, they took the plants of old Catholic England. From this small beginning, the movement spread across the States and an association was set-up to specifically promote Mary Gardens.
Today the Marian Garden is a bold statement of Catholic Faith in a secular world. It expresses our pride in our Catholic roots and our love of our ancient heritage.
Here is an exquisitely illustrated guide to creating a Mary Garden in the home, parish, school or monastery, with an extensive guide to traditional English plant names dedicated to Our Lady, their legends, use in art and in prayer and meditation.


2010-08-31 First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=29398416&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=KR100458288(B1) "Global patent litigation dataset" by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
PURPOSE: A dual gate FinFET device and a fabricating method thereof are provided to reduce fabricating cost and parasitic resistance by using a bulk wafer and forming an epitaxial layer on a source/drain. CONSTITUTION: A dual gate FinFET device includes a bulk silicon substrate(2b), a Fin active region(4), the second oxide layer(10), a gate oxide layer, the first oxide layer(6), a gate(16), a source/drain, a contact region, and a metal layer. The Fin active region is formed on the center portion of an upper portion of the bulk silicon substrate. The second oxide layer is formed on the surface of the bulk silicon substrate. The gate oxide layer is formed at both sidewalls of the Fin region of the second oxide layer. The first oxide layer is formed on an upper surface of the Fin active region. The gate is formed on the first and the second oxide layers. The source/drain is formed at both sides of the Fin active region except for an overlapped part between the gate and the Fin active region. The contact region and the metal layer are formed on the contact part of the source, the drain, and the gate.
본 발명은 이중-게이트 FinFET 소자 및 그 제조방법에 관한 것으로서, 더 상세하게는 벌크(bulk) 실리콘기판을 이용하되, 채널이 형성되는 바디(body)가 될 실리콘의 Fin액티브 영역이 나노 크기의 폭을 갖도록 하고 기판에 연결되도록 하며, 전류가 흐르는 길이 방향으로 담장처럼 형성되게 함으로써 전기적으로 안정된 이중-게이트 FinFET 소자 및 그 제조방법에 관한 것이다. The present invention is a double-gate FinFET devices and as it relates to a process for the preparation, and more specifically to the bulk (bulk), but using a silicon substrate, the width of the Fin active area nano-size of the silicone is a body (body) in which the channel is formed and to have, and to be connected to a substrate, and electrically stable duplex by causing current to flow in the longitudinal direction as the fence-gate FinFET relates to a device and a method of manufacturing the same.
나노 CMOS 소자 기술은 CPU와 같은 로직 회로와 메모리 기술에 적용되어 엄청난 부가가치를 창출할 수 있는 특성을 갖고 있어 현재 전 세계적으로 연구가 매우 활발하게 진행되고 있다. Nano-CMOS device technology, it has a property that can create a tremendous value added is applied to a logic circuit and memory technology, such as a CPU may be a current study worldwide proceeds very actively.
실리콘 반도체 기술을 이용한 시스템의 크기가 작아지고 낮은 전력소모를 필요로 하면서 소자 크기가 그에 따라 작아져야 한다. The size of the system using a silicon semiconductor technology is reduced and the device size should be smaller accordingly, requiring a low power consumption.
이에 부응할 수 있는 가장 경쟁력이 있는 소자 기술이 CMOS 소자 기술이다. This is a CMOS device technology, device technology is the most competitive to meet.
이들 소자의 게이트 크기는 현재 계속 스케일링 다운되고 있는데, 그에 따른 문제가 계속 발생하고 있다. Gate size of these devices there is still scaled down current, and hence the problem still occurs.
가장 큰 문제는 소위 짧은 채널효과(Short Channel Effect)이다. The main problem is a so-called short-channel effect (Short Channel Effect).
종래의 CMOS 기술은 주로 벌크(bulk) 실리콘기판에서 제작되어 왔다. Conventional CMOS technology has been mainly produced in the bulk (bulk) silicon substrate.
벌크 실리콘에서 만들어진 MOS 소자는 50 nm 이하의 게이트 길이로 스케일링다운되면서 공정조건이 매우 민감하게 소자의 특성에 영향을 미치고, 또한 채널 길이가 30 nm 근처에서는 소자의 성능이 실제 회로에 적용되기에는 아직 충분하지 않다. MOS devices made from bulk silicon affects the characteristics of the scaled-down process conditions are very sensitive element as a gate length of less than 50 nm, also in the vicinity of a 30 nm channel length still has doegie the performance of the device applied to the physical circuit Not full yet.
인텔(Intel)에서 개발한 30 nm CMOS 소자는 게이트 길이는 30 nm인데, IV 특성이 종래의 것에 비해 우수하지 않다. Intel (Intel) a 30 nm CMOS devices is the development in the 30 nm gate length, IV characteristics are not better than those of the prior art.
또한 실제 하나의 소자가 점유하는 면적은 스케일링 다운되지 않는 게이트 옆에 형성된 스페이서 영역 때문에 종래에 비해 줄어들지 않았기 때문에 집적도를 개선할 여지가 적다. In addition, an area that is one of the actual element is occupied is room for improving the degree of integration because it did not decrease compared to the conventional low because the spacer region formed next to the gate is not scaled down.
이들 벌크 실리콘 기판을 근간으로 하는 MOS 소자 기술에 한계가 생기면서 30 nm 이하의 채널 길이를 갖는 소자를 구현하기 위해 SOI(Silicon On Insulator) 실리콘기판을 근간으로 하는 소자에 대한 연구가 활발하게 진행되고 있다. The bulk is a limit to the MOS device technology that stems from the silicon substrate animation while research on the device as the foundation of the silicon substrate SOI (Silicon On Insulator) to implement a device having a channel length of no more than 30 nm been actively have.
종래의 벌크 실리콘기판에서 제작한 소자 구조를 그대로 SOI 실리콘기판에서 제작하여 그 특성을 분석한 연구가 많이 진행되었으나, 실리콘 필름 두께가 얇은 관계로 기생 소스/드레인 저항이 크게 증가하여 소스/드레인 영역에 선택적으로 에피층을 성장해야 한다. But by directly produced in SOI silicon substrate for a device structure manufactured by the conventional bulk silicon substrate advances a lot of research was analyzed and its properties, and the silicone film thickness increases significantly the parasitic source / drain resistance in thin relation to the source / drain region Alternatively it must grow the epitaxial layer.
또한 소자의 바디가 SOI 소자의 특성상 기판과 연결되어 있지 않기 때문에 플로팅(floating) 바디 효과와 열전도가 잘 되지 않아 소자의 성능이 떨어지는 문제가 있다. In addition, because it does not have the body of the device is associated with the nature of the substrate SOI devices do not work in a floating (floating) the body effect and heat transfer have poor device performance problems.
이와 같이 종래의 구조를 SOI 기판에 구현한 것은 벌크에서 구현한 소자에 비해 스케일링 다운 특성이 크게 개선되지 않아, CMOS 소자의 채널길이를 25 nm 또는 그 이하까지 줄이기 위한 가장 적합한 소자구조로 이중-게이트 소자 구조가 등장했다. Thus, it is an implementation of a prior art structure on the SOI substrate does not improve the scaling-down characteristic compared to a device implemented in bulk significantly, the most suitable device structure to reduce the channel length of a CMOS device to 25 nm or less, a dual-gate the device structure has emerged.
이중-게이트 소자는 전류가 흐르는 채널의 상하(아래와 위)나 좌우(왼쪽과 오른쪽)에 게이트 전극이 존재하여 게이트 전극에 의한 채널의 제어 특성을 크게 개선할 수 있다. A double-gate device can be to a gate electrode present above and below the channel in which a current flows (below above), or right and left (right and left) significantly improve the control characteristics of the channel by the gate electrode.
게이트에 의한 채널의 제어 특성이 큰 경우, 소스와 드레인 사이의 누설전류를 종래의 단일 게이트 소자에 비해 크게 개선할 수 있어 결국 DIBL(Drain Induced Barrier Lowering) 특성을 크게 개선할 수 있다. If the control characteristics of the channel by the gate is large, can be greatly improved compared with the leakage current between the source and the drain in the conventional single-gate device's end may significantly improve the DIBL (Drain Induced Barrier Lowering) characteristics.
또한 채널 양쪽에 게이트가 존재하여 소자의 문턱전압을 동적(dynamically)으로 변화시킬 수 있어 채널의 on-off 특성이 종래의 단일 게이트 구조에 비해 크게 개선되고 짧은 채널효과를 억제할 수 있다. In addition, it is possible to present to the gate it is possible to change the threshold voltage of the device in a dynamic (dynamically) the on-off nature of the channel is greatly improved compared to a conventional single-gate structure for suppressing the short channel effect in both channels.
도 1은 종래의 이중-게이트 구조에서 전류가 흐르는 채널의 방향을 100 웨이퍼 표면을 기준으로 해서 간단하게 도식적으로 표현한 도면이다. Figure 1 is a conventional dual-a view to the direction of the channel in which a current flows from the gate structure simple, based on the wafer 100 surface diagrammatic representation.
게이트(32)는 바디(채널,34)의 좌우 또는 상하에 형성된다. Gate 32 are formed on left and right or above and below the body (channel 34).
도 1a는 방향 100 웨이퍼에 수직으로 형성되어 소스/드레인이 상하로 형성되는 일종의 3차원(3-D) 소자로 전류는 상하로 흐른다. Figure 1a is a three-dimensional (3-D) that is a kind of device as the source / drain is formed in a direction perpendicular to the wafer 100 formed with the upper and lower current flows in the vertical direction.
도 1b는 방향 100 웨이퍼에서 웨이퍼와 같은 면에 채널(34)이 형성되고 그 채널의 아래 위에 게이트(32)가 형성되는 표준 이중-게이트 MOS 소자 구조로 전류는 결정방향 100 면으로 흐른다. Figure 1b is a standard double that gate 32 on the bottom of the channel 34 on the surface is formed the channel, such as a wafer in the direction 100 to form the wafer-to-gate MOS device structure, a current flows in the crystal orientation 100 side.
도 1c는 방향 100 웨이퍼 면과 수직되게 형성된 면에 채널(34)이 형성되어도 1a와는 달리 소스/드레인 영역이 상하로 형성되지 않고 100 웨이퍼 면과 같은 나란한 방향으로 전류가 흐른다. Figure 1c is a current flows in parallel, such as the wafer 100 if the direction 100 perpendicular to the wafer surface and may be presented channel 34 formed on the surface 1a is formed, unlike the source / drain region is not formed in the vertical direction.
도 2는 종래 FinFET 구조를 보이고 있는 것으로, 배선을 위한 금속층은 생략하고 주요 부분만 표시한 것이다. Figure 2 shows that a conventional FinFET structure, a metal layer for wiring is omitted, and only show the main part.
도 2a와 도 2b는 같은 구조로 도 2a는 반투명으로 도 2b는 해칭을 넣어 표시한다. Figure 2a and Figure 2b Figure 2a to Figure 2b, such structure is a semi-transparent display is put in a hatching.
도 1c에 해당하는 구조와 전류 방향을 갖고 있다. It has the structure as the current direction in Figure 1c.
채널의 양쪽(또는 상하)에 게이트 전극(16)을 두어 소위 짧은 채널효과를 크게 개선할 수 있다. Placing the gate electrode 16 on either side of the channel (or top and bottom) can be increased to improve the so-called short-channel effect.
미설명 부호 2a는 SOI 실리콘기판, 6, 10은 산화막, 12는 게이트 산화막이다. Reference numeral 2a is a SOI silicon substrate, 6, 10 oxide film, 12 is a gate oxide film.
상기 도 1b와 도 1c의 특징을 가진 이중-게이트 소자를 구현하기 위한 방법을 자세히 설명하면 다음과 같다. Double with the features of FIG. 1c and FIG. 1b - A detailed description how to implement the gate device as follows.
먼저 그 구현방법은 크게 2가지가 있다. First, its implementation is largely twofold.
첫째, 도 1b에서와 같이 전류가 웨이퍼의 표면방향과 같은 방향인 수평으로 흐르는 구조이다. First, the structure of the current flows in the same direction with the surface direction of the wafer level, as shown in Figure 1b.
이 구조에서는 종래의 경우와 같이 채널(34)이 실리콘의 결정방향 100에서 형성되어 종래의 구조에 비해 Si-SiO 2 계면 특성이 저하되지 않는다. In this structure, the channel 34 as in the case of the prior art is formed from crystal orientation of the silicon 100 not the Si-SiO 2 interface properties are not lowered as compared with the conventional structure.
도 1b의 이중-게이트 소자는 채널(34)의 아래와 위에 게이트(32)가 존재한다. Dual of Figure 1b - the gate element is a gate (32) present on the below of the channel 34.
이 소자 구조는 바디 실리콘 영역의 필름 두께를 얇고 균일하게 제어하여 제작하는 것이 가능하다. The device structures can be fabricated by thin and uniform control of the film thickness of the silicon body region.
채널(34)의 아래와 위에 게이트(32)를 형성하기 위해서는 MEMS(Micro Electro-Mechamical System) 기술을 이용한 웨이퍼 본딩(bonding)과 etch-back 공정을 수행해야 하기 때문에 다소 공정이 복잡해진다. In order to form the gate 32 follows over the channel 34 becomes a little complicated process because the need to perform wafer bonding (bonding) and etch-back process using the (Micro Electro-Mechamical System) MEMS technology.
이중-게이트 MOS 소자에서 아주 중요한 요건 중에 하나는 2개의 게이트(32)가 자기정렬되어야 하는데 그렇지 않으면 소자의 특성이 크게 저하된다. A double-gate MOS devices in the very important requirement is one of two or else to gate 32 is to be self-aligning properties of the device is significantly reduced.
채널(34)의 아래와 위에 게이트(32)를 갖는 도 1b의 소자에서 자기정렬형으로 게이트(32)를 구성하기 위한 연구가 많이 진행되고 있으며, 이들은 재료 및 공정상에서 복잡성을 유발한다. The progress much research to configure the gate 32 in a self-aligned in the device of Figure 1b has a gate 32 over below the channel 34, and these results in a complexity on the material and process.
소자의 스케일링 다운 특성을 개선하기 위해서는 채널 실리콘 필름의 두께를 20 nm 또는 그 이하로 줄여야 한다. In order to improve the scaling-down characteristic of the device to reduce the thickness of the channel in the silicon film 20 nm or less.
이와 같이 20 nm 이하의 두께를 갖는 실리콘 필름을 채널 및 소스/드레인 영역으로 그대로 사용하면 소자의 짧은 채널효과를 개선할 수 있지만 소스/드레인 기생저항을 크게 증가시켜 소자의 특성을 저하시키게 된다. According to this as using the silicon film has a thickness of 20 nm as a channel and a source / drain region, thereby to improve the short channel effect of the device, but the degradation characteristics of the device greatly increases the source / drain parasitic resistance.
결국 자기정렬형을 구현하고 소스/드레인 저항을 줄이기 위해 공정의 복잡성을 감수해야 한다. Finally implement the self-aligned and should take steps to reduce the complexity of the source / drain resistance.
둘째, 이중-게이트 MOS를 구현하기 위한 다른 방법은, 도 1c에서와 같이 채널(34)의 양쪽(왼쪽과 오른쪽)에 게이트(32)를 형성하여 소자를 제작하는 방법이다. Second, the double-another way to implement the MOS gate is a method of manufacturing the device by forming a gate 32 on both sides (left and right) of the channel 34, as shown in Figure 1c.
상기 도 1c의 MOS 소자를 'FinFET'라고 부른다. Wherein the MOS device of Figure 1c is referred to as 'FinFET'.
도 1c의 이중-게이트 소자는 SOI 소자 기술에서 채널이 되는 영역(34)의 폭을 나노미터 크기(대개 50 nm 이하)로 패턴을 형성하고 식각하여 게이트 물질을 증착하면 식각된 채널 패턴의 양쪽 측벽이 주 채널영역이 되는 것을 이용하는 것이다. Of Figure 1c the double-gate device is nanometer size the width of the region 34 is a channel in the SOI device technology (typically 50 nm or less) when a to form a pattern and etch depositing a gate material on both sides of the etched channel pattern side wall the use to which this main channel region.
상기 구조에서는 전류가 흐르는 채널(34)이 웨이퍼 표면 방향과 수직으로 형성되어 전류가 흐른다. The structure in the channel 34 in which a current flows is formed in the direction perpendicular to the wafer surface and current flows.
상기 구조를 구현하는 공정은 게이트(32)가 아래/위에 있는 구조에 비해 공정이 크게 단순화 되는 특징이 있다. Process for implementing the above structure is characterized in that the process is greatly simplified compared to the structure above / below the gate 32.
그러나 표면이 100인 실리콘 기판에 수직으로 형성된 필름의 측면에 전류가 흐르는 채널(34)이 형성되기 때문에 채널의 결정방향은 통상 110이 되어 종래의 100 계면에 비해 계면 특성이 나쁘다. However, since the surface 100 of the channel 34 in which a current flows on the side of the film that is formed perpendicularly to the silicon substrate is formed in the crystal direction of the channel is the normal 110 is poor interfacial characteristics as compared with the conventional 100 interface.
이를 해결하기 위해서 웨이퍼의 일차 평탄 지역(primary flat zone)과 45도 방향으로 채널을 형성하면 결정방향 100 실리콘 면에 채널을 형성할 수 있다. When the primary 45 and the flat area (primary flat zone) of the wafer is also formed in the channel in the direction to solve this problem, it is possible to form a channel 100 in the silicon crystal plane orientation.
채널의 실리콘 영역은 나노 패터닝 기술에 의해 정의되기 때문에 아래/위에 게이트가 있는 이중-게이트 소자(도 1b)에 비해 채널이 형성되는 바디 폭의 변화가 상대적으로 커서 소자 특성의 편차가 상대적으로 크게 생겨날 수 있고, 기본적으로 게이트(32)가 채널(34)의 양쪽면에서 자기정렬형으로 형성되는 특징이 있다. Arise largely with variation in the change in the body width relative to the cursor device characteristics in which the channel is formed relative to the gate element (Fig. 1b) relative-silicon area of the channel is a double with gate on / down because they are defined by the nano-patterning technique number, and is characterized in that by default, the gate 32 is formed in a self-aligned at both sides of the channel 34.
그러나 소스/드레인은 바디 영역과 같은 나노 폭을 갖기 때문에 기생 소스/드레인 저항이 증가하여 소자의 전류구동능력이 저하된다. However, the source / drain is owing to the nano range, the parasitic source / drain resistance to increase the current driving capability of the device, such as a body region is reduced.
이를 해결하기 위해 소스/드레인이 될 영역에 자기정렬이 아닌 형태로 다결정 실리콘이나 SiGe 층을 증착하고 패터닝하는 공정을 추가하여 기생 저항을 줄이려는 시도가 발표되었지만 그 효과가 크지 않고, 제조 공정의 변화나 공정의 추가가 있더라도 결국 얇은 폭을 갖는 채널과 소스/드레인 영역 사이의 기생저항을 줄이지는 못하였다. Although an attempt is made to reduce a parasitic resistance presented by adding the step of depositing and patterning the poly-Si or SiGe layer in the form a non-self-aligned to the regions to be source / drain in order to solve this problem is not greater that effect, the change in the manufacturing process even if the addition of the process or did eventually reduce the parasitic resistance between the thin width of the channel and source / drain regions having.
즉, 종래의 SOI 실리콘기판(2a)에 형성된 이중-게이트 MOS 소자는 웨이퍼의 가격이 벌크 웨이퍼에 비해 훨씬 비싸고 기생 소스/드레인 저항이 증가하는 문제가 있었다. That is, the double-formed on a conventional SOI silicon substrate (2a) - gate MOS devices there has been a problem that the price of the wafer is more expensive, parasitic source / drain resistance is increased compared to the bulk wafers.
또한 도 2에서 소자의 채널이 형성되는 바디(34)가 SOI 소자의 특성상 SOI 실리콘기판(2a)과 연결되어 있지 않기 때문에 플로팅 바디 문제를 가지고 있고 SOI 실리콘기판(2a)에 형성된 산화막(10)이, 소자에서 발생한 열이 SOI 실리콘기판(2a)으로 전도되는 것을 차단하여 소자의 성능이 떨어진다. In addition, the oxide film 10 formed in the SOI silicon substrate (2a) and has a floating body problem because even not in the second no body 34, a channel is formed in the element is associated with the nature of SOI silicon substrate (2a) of the SOI device , blocks the heat generated by the element is conducted to the SOI silicon substrate (2a) to the inferior performance of the device.
본 발명은 상술한 문제점을 해결하기 위하여 안출된 것으로서, 벌크 웨이퍼를 사용하여 가격이 싸고 게이트와 자기정렬되게 소스/드레인에 에피층을 성장하여 기생 저항성분을 줄일 수 있으며 실리콘 구조물인 Fin액티브 영역은 채널이 형성되는 바디이고 벌크 실리콘기판과 연결되어 플로팅 바디 문제를 해결할 수 있을 뿐만 아니라 열전도가 잘 되어 소자의 특성을 향상시킬 수 있는 이중-게이트 FinFET 소자 및 그 제조방법을 제공하는데 그 목적이 있는 것이다. The present invention been made in view of solving the above problems, using a bulk wafer cheap price gate and self-aligned to be to reduce the parasitic resistance component by growing the epitaxial layer on the source / drain and silicon structure of Fin active region body and is connected to the bulk silicon substrate in which the channel is formed, as well as to fix the floating body problem are well heat conductive double to improve the properties of the device - to provide a gate FinFET device and a method of manufacturing it with its object .
상술한 목적을 달성하기 위하여 본 발명은, 벌크 실리콘기판과, 상기 벌크 실리콘기판에 연결되고 벌크 실리콘기판 상부 가운데에 단결정 실리콘으로 형성된 담장 모양의 Fin액티브 영역과, 상기 벌크 실리콘기판 표면에서 Fin액티브 영역의 일정 높이까지 형성된 제2산화막과, 상기 제2산화막 위의 Fin액티브 영역 양쪽 측벽에 형성된 게이트 산화막과, 상기 Fin액티브 영역의 위쪽 표면에 게이트 산화막과 같거나 두껍게 형성된 제1산화막과, 상기 제1,2산화막 위에 형성된 게이트와, 상기 게이트와 겹치는 Fin액티브 영역을 제외한 Fin액티브 영역 양쪽에 형성된 소스/드레인과, 상기 소스, 드레인, 게이트의 콘택 부분에 형성된 콘택영역 및 금속층을 포함하는 이중-게이트 FinFET 소자를 제공하고자 한다. The present invention to achieve the above object, a bulk silicon substrate, and coupled to the bulk silicon substrate is a bulk silicon substrate top of the single crystal silicon as formed Fin active region of the wall shape in, Fin active region in the bulk silicon substrate surface, first and second oxide film formed to a predetermined height, wherein the first oxide film formed the same as a gate oxide film on the top surface of the gate oxide film and the Fin active regions formed on both side walls Fin active area above the second oxide film, or thick, the first 2 with a gate formed on the oxide film, the gate and the overlapping Fin source / drain formed on either side Fin active region except for the active region and a double including the source, drain, and contact region and a metal layer formed on the contact portion of the gate-to-gate FinFET and to provide a device.
상술한 목적을 달성하기 위하여 본 발명은, 벌크 실리콘기판에 단결정 실리콘으로 담장 모양의 Fin액티브 영역을 형성하는 공정과, 상기 벌크 실리콘기판 표면에서 Fin액티브 영역의 일정 높이까지 제2산화막을 형성하는 공정과, 상기 제2산화막 위로 형성된 Fin액티브 영역 양쪽 측벽에 게이트 산화막을 형성하는 공정과, 상기 Fin액티브 영역의 위쪽 표면에 게이트 산화막과 같거나 두껍게 제1산화막을 형성하는 공정과, 상기 제1,2산화막 위에 게이트를 형성하는 공정과, 상기 게이트와 겹치는 Fin액티브 영역을 제외한 Fin액티브 영역 양쪽에 소스/드레인을 형성하는 공정과, 상기 소스, 드레인, 게이트의 콘택 부분에 콘택영역 및 금속층을 형성하는 공정을 포함하는 이중-게이트 FinFET 소자 제조방법을 제공하고자 한다. The present invention to achieve the above object, the step of forming the Fin active region of the fence-shaped single-crystal silicon on bulk silicon substrate, a step of forming a second oxide film in the bulk silicon substrate surface to a certain height of the Fin active region and, the step of forming the gate oxide film and the like on the upper surface of the step, the Fin active region to form a gate oxide film on each side wall Fin active region formed over the second oxide film, or thick first oxide, the first and second a step of forming a gate on the oxide film, a step of forming other than the overlapping Fin active region and the gate and the step of forming the source / drain on both sides Fin active region, said source, drain, a contact region and a metal layer on the contact portion of the gate to provide a gate FinFET device manufacturing method-double comprising a.
도 1a 내지 도 1c는 종래 이중-게이트 구조에서 전류가 흐르는 채널의 방향을 웨이퍼 표면을 기준으로 해서 간단하게 나타낸 사시도이다. Figure 1a to 1c, prior art dual-a perspective view of the direction of the channel in which a current flows from the gate structure shown simply by, based on the wafer surface.
도 2a 및 도 2b는 종래 FinFET 소자의 구조로서 반투명과 해칭을 넣어 표시한 사시도이다. Figure 2a and Figure 2b is a perspective view of a structure of a conventional FinFET device into the semi-transparent display and hatching.
도 3a 및 도 3b는 본 발명에 따른 FinFET 소자의 구조로서 반투명과 해칭을 넣어 표시한 사시도이다. 3a and 3b show a perspective view and into the semi-hatching as the structure of the FinFET device in accordance with the present invention.
도 4a와 도 4b는 도 3a의 일반적인 사시도와 그 패턴을 보여주는 평면도이다. Figure 4a and Figure 4b is a plan view showing a general perspective view with the pattern of Figure 3a.
도 5a와 도 5b는 본 발명의 다른 실시예에 따른 FinFET 구조를 보여주는 사시도와 그 패턴을 보여주는 평면도이다. Figure 5a and Figure 5b is a perspective view and a plan view showing a pattern that shows a FinFET structure in accordance with another embodiment of the present invention.
도 6a 내지 도 6d는 도 4를 구현하기 위한 각 마스크 단계를 보여주는 평면도이다. Figure 6a to Figure 6d is a plan view showing a mask for each step for implementing the FIG.
도 7은 도 4의 사시도를 채널을 중심으로 해서 수평과 수직 방향으로 자른 단면도이다. 7 is a sectional view taken in the horizontal and vertical directions by the perspective view of Figure 4 around the channel.
도 8은 도 5의 사시도를 채널을 중심으로 해서 수평과 수직 방향으로 자른 단면도이다. Figure 8 is a sectional view taken in the horizontal and vertical directions by the perspective view of Figure 5 around the channel.
도 9a 내지 도 9d는 본 발명의 제1실시예에 따라 FinFET 소자의 바디 구조를 구현하는 공정을 보여주는 예시도이다. Figure 9a through 9d is a view illustrating a process for implementing the body structure of the FinFET device in accordance with a first embodiment of the present invention.
도 10a 내지 도 10d는 본 발명의 제2실시예에 따라 FinFET 소자의 바디 구조를 구현하는 공정을 보여주는 예시도이다. Figure 10a to Figure 10d is a view illustrating a process for implementing the body structure of the FinFET device in accordance with a second embodiment of the present invention.
도 11a 내지 도 11d는 본 발명의 제3실시예에 따라 FinFET 소자의 바디 구조를 구현하는 공정을 보여주는 예시도이다. Figure 11a to Figure 11d is a view illustrating a process for implementing the body structure of the FinFET device in accordance with a third embodiment of the present invention.
도 12a 내지 도 12d는 본 발명의 제4실시예에 따라 FinFET 소자의 바디 구조를 구현하는 공정을 보여주는 예시도이다. Figure 12a to Figure 12d is a view illustrating a process for implementing the body structure of the FinFET device in accordance with a fourth embodiment of the present invention.
도 13a 내지 도 13d는 본 발명의 제5실시예에 따라 FinFET 소자의 바디 구조를 구현하는 공정을 보여주는 예시도이다. Figure 13a to Figure 13d is a view illustrating a process for implementing the body structure of the FinFET device in accordance with a fifth embodiment of the present invention.
이하 본 발명을 첨부된 도면을 참고로하여 설명하면 다음과 같다. Referring to the accompanying drawings, the present invention below with reference to as follows.
상기 소스, 드레인, 게이트(16)의 콘택 부분에 형성된 콘택영역(46) 및 금속층(48)으로 이루어진다. It comprises a contact region 46 and the metal layer 48 formed on the contact portions of the source, drain, and gate 16.
상술한 구성에서, 제2산화막(10)의 두께를 20 nm ∼ 800 nm로하여 게이트(16)와 벌크 실리콘기판(2b) 사이의 기생용량 성분을 줄일 수 있다. In the above-described configuration, it is possible by the thickness of the second oxide film 10 to 20 nm ~ 800 nm to reduce the parasitic capacitance component between the gate 16 and the bulk silicon substrate (2b).
상술한 구성에서, 상기 금속층(48)과 접촉하는 콘택영역(46)을 Fin액티브 영역(4)의 폭이나 게이트(16) 길이보다 크게 하여 소자의 집적도를 개선하고 콘택 저항을 줄일 수 있다. In the above-described configuration, it is possible for the contact area 46 in contact with the metal layer 48 significantly improves the degree of integration of the element than the width of Fin or gate 16 in the active region 4, the length and reduce the contact resistance.
상술한 구성에서, 상기 Fin액티브 영역(4)의 폭을 일정하게 하지 않고 벌크 실리콘기판(2b)에 가까와짐에 따라 제2산화막(10) 내에서 넓어지도록 하여 Fin액티브 영역(4)의 저항을 줄일 수 있다. In the above-described configuration, the resistance of the Fin active region 4, the second oxide film 10 and so wide in the Fin active region 4 rather than a constant width in accordance with the load closer to the bulk silicon substrate (2b) of It can be reduced.
상술한 구성에서, 상기 Fin액티브 영역(4)이 상부 폭은 좁고, 하부 폭이 넓은 사다리꼴 모양으로 할 수 있다. In the above-described configuration, the Fin active region 4 is top width can be as narrow trapezoidal shape, a lower wide.
상술한 구성에서, 상기 Fin액티브 영역(4)의 두 상부 모서리를 900℃ 이상의 산화공정, 식각공정 또는 수소 분위기에서의 어닐링을 통해 둥글게 형성하여 소자의 내구성을 향상시킬 수 있다. In the above-described configuration, by forming round through the annealing in the Fin active region (4) two or more of the upper edge 900 ℃ oxidation process, an etching process or a hydrogen atmosphere, it is possible to improve the durability of the device.
상술한 구성에서, 상기 게이트(16)를 구성하는 물질은 폴리실리콘, 폴리 SiGe, 금속을 사용할 수 있다. In the above-described configuration, the material constituting the gate 16 can be polysilicon, poly-SiGe, metals.
도 3은 본 발명에서 제안한 소자의 구조를 보인다. Figure 3 shows the structure of the proposed device in this invention.
배선을 위한 금속층은 제외하고 주요 부분만 보인 것으로, 같은 구조를 도 3a는 반투명으로 도 3b는 해칭을 넣어 표시하였다. And that the major part only shown, Figure 3a Figure 3b with the same structure except for a translucent metal layer for wiring are expressed into the hatching.
도 2와 다른 점은 Fin액티브 영역(4)이 플로팅(flaoting)되어 있지 않고 벌크 실리콘기판(2b)에 연결되어 있으며, 이것에 의해 특성이 크게 개선된다. Figure 2 differs from the Fin and the active region 4 is not without floating (flaoting) connected to the bulk silicon substrate (2b), the characteristic is greatly improved by this.
즉, 채널이 형성되는 바디가 벌크 실리콘기판(2b)에 연결되어 기존의 SOI 실리콘기판(2a)에 형성된 소자가 갖는 플로팅 바디 문제가 없고, 또한 소자의 채널에서 생성되는 열이 기존의 구조에 비해 훨씬 쉽게 벌크 실리콘기판(2b)으로 빠져 나갈 수 있다. That is, the body in which the channel is formed is connected to the bulk silicon substrate (2b) there is no floating body problem element having formed on conventional SOI silicon substrate (2a), also the heat generated in the device channel compared to the conventional structure more easily can pass through the bulk silicon substrate (2b).
또한 SOI 웨이퍼 대신 벌크 웨이퍼를 사용하여 제작하므로 가격면에서도 유리하다. Also be manufactured using a bulk wafer instead of an SOI wafer is advantageous in terms of price.
도 4a는 본 발명에서 제안한 구조로서, 도 3a와 같은 구조로 비교를 위해 첨가한 것이고, 도 5a는 도 4a의 구조에서 기생 소스/드레인 저항을 줄이기 위한 선택적 에피층(18) 첨가를 추가로 보인 것이다. Figure 4a is a proposed structure of the present invention, as a structure, such as 3a will added for comparison, Figure 5a is shown an additional selective epitaxial layer 18 is added to reduce the parasitic source / drain resistance in the structure of Figure 4a will be.
도 4a와 도 5a는 배선을 위한 금속층은 제외하고 주요 부분만 도시한 것이고, 도 4b와 도 5b는 각각의 도면에 대한 평면도를 보이고 있다. Figure 4a and Figure 5a will, except the metal layer for wiring and showing only the main part, and Fig. 4b is a top view and Figure 5b shows for each of the drawing.
도 4b에서 게이트(16)가 겹치지 않는 Fin액티브 영역(4)에 소스/드레인 영역이 형성된다. In Figure 4b the gate 16 does not overlap the active region Fin (4) source / drain regions to be formed.
상기 Fin액티브 영역(4)에서 소스/드레인이 형성되는 곳에 콘택(contact)이 형성되어 금속선이 연결되는 부분은 채널과 같은 폭의 Fin 구조이기 때문에, 기생 소스/드레인 저항을 크게 증가시키는 단점이 있어 도 5b와 같이 하여 기생 저항 성분을 줄인다. The Fin active region 4, a contact (contact) where it is the source / drain is formed in the formed part is a metal wire is connected is it a disadvantage that since the Fin structure, such as the channel width, parasitic source / significant increase in drain resistance as it is shown in Figure 5b, reducing the parasitic resistance component.
여기서 FinFET 소자의 소스/드레인 영역에만 선택적 에피층(18)을 성장하는 과정을 살펴본다. Here looks at the process of growing selective epitaxial layer 18 only on the source / drain regions of the FinFET device.
먼저 소자의 구조가 게이트(16) 형성까지 되어 있다고 가정한다. First, it assumes that the structure of the device is up to the gate 16 is formed.
채널의 도우핑(~10 18 cm -3 )에 비해 게이트(16)가 10 20 cm -3 이상으로 도우핑되어 있는 상태에서 5 nm에서 20 nm 정도 이내로 습식으로 산화를 시키면 게이트(16)에는 3 내지 5배 정도 도우핑에 의해 훨씬 두껍게 산화막이 성장한다. Compared to doping (~ 10 18 cm -3) of the gate channel (16) when the wet oxidation while it is doped with more than 10 20 cm -3 in the 5 nm to within about 20 nm, the gate 16 3 to five times to help grow much thicker oxide film by Ping.
상기 성장된 산화막을 채널에 형성된 산화막 두께를 기준으로 다시 식각하면 Fin액티브 영역의 측벽에 형성된 산화막이 없어지고 Fin액티브 영역(4)의 실리콘이 드러나게 된다. Referring back etching the grown oxide film, based on the thickness of the oxide film formed in the channel do not have the oxide film formed on the side wall of the Fin becomes active areas are revealed a silicon active region of the Fin (4).
이때 상대적으로 두껍게 산화막이 성장된 게이트(16)는 여전히 산화막에 덮혀있게 된다. At this time, a relatively thick oxide film is grown gate 16 is still covered with the oxide film is possible.
소스/드레인의 Fin액티브 영역(4)의 측벽에 드러난 실리콘을 씨앗(seed)으로 하여 선택적 에피층(18)을 성장시킨다. Using the silicon exposed in the side wall of the Fin active region 4 of the source / drain to the seed (seed) is grown by selective epitaxial layer 18.
경우에 따라서는 Fin액티브 영역(4)의 측벽 및 상부에도 실리콘이 드러나게 하고 그것을 씨앗으로 하여 선택적 에피층(18)을 성장할 수 있다. In some cases, may be grown to a side wall and an optional epitaxial layer 18 to expose the silicon, and that the seed in the upper part of the Fin active region (4).
이때 성장되는 선택적 에피층(18)으로는 단결정 실리콘, 단결정 SiGe, 단결정 Ge, 폴리실리콘, 폴리 SiGe이 가능하다. The selective epitaxial layer 18 is grown as is capable of single crystal silicon, single crystal SiGe, Ge single crystal, polysilicon, poly-SiGe.
도 4a와 도 5a에서 Fin액티브 영역(4)에 일점쇄선으로 표시된 것은 소스/드레인 접합깊이를 나타낸다. Figure 4a and Figure 5a is at one point in Fin active area 4 indicated by the chain line indicates the source / drain junction depth.
여기서는 접합깊이가 제2산화막(10) 표면 위쪽 면보다 더 위에 위치하고 있음을 알 수 있고, 이는 접합깊이를 조절하여 짧은 채널효과를 제어하기 위함이다. Here, the junction depth and found that located further on the second oxide film 10, the upper surface than cotton, which is to control the short channel effect by adjusting the junction depth.
상기 제2산화막(10)의 위쪽 면을 기준(0 nm)으로 했을 때 소스/드레인 접합깊이가 위쪽으로, 즉, 0 nm 보다 크고 50 nm 이내로 하면 짧은 채널효과를 억제할 수 있다. The second oxide film 10, source / drain junction depth, when the reference (0 nm), the top surface is upward, that is, it is possible to suppress the short-channel effect when greater than 0 nm to within 50 nm.
반대로 접합깊이를 아래 쪽으로, 즉, 0 nm 보다 작고 -50 nm 보다 크면 짧은 채널효과보다는 전류 구동능력을 증가시키는 효과를 가져 온다. In contrast the downward depth of the junction, that is, comes to have the effect that less than 0 nm is greater than -50 nm, rather than a short channel effect increases the current driving capacity.
도 5a에서 선택적 에피층(18)을 성장하는 다른 일예를 소개한다. It presents another example of the selective epitaxial growth layer 18 in Figure 5a.
공정 순서에서 게이트(16) 형성까지 완료한 다음 절연막을 5 nm에서 100 nm 사이의 두께로 증착하고, 증착한 두께와 제2산화막(10) 위로 돌출된 Fin액티브 영역(4)의 높이에 해당하는 두께만큼 비등방 식각하면 게이트(16)와 소스/드레인 Fin액티브 영역(4)이 만나는 근처에만 절연막이 형성되고 다른 곳은 드러나게 된다. In a process sequence that corresponds to the height of the gate 16 is complete up to the formation of the next dielectric film deposition from 5 nm to a thickness of between 100 nm and protrude above the deposition thickness and a second oxide film (10) Fin active region 4 When anisotropic etching by a thickness gate 16 and the source / drain active regions Fin only the insulating film near 4 is formed to meet a different place is revealed.
드러난 Fin액티브 영역(4)의 실리콘 영역과 게이트(16)의 폴리실리콘 영역을 씨앗으로 하여 선택적 에피층(18)을 5 nm에서 100 nm 사이의 한 값으로 성장시킨다. To a silicon region and a polysilicon gate region 16 of the active region exposed Fin (4) as a seed to grow a selective epitaxial layer 18 to a value between 100 nm at 5 nm.
그러면 선택적 에피층(18)이 소스/드레인 영역에도 성장되고 드러난 폴리실리콘 또는 SiGe 게이트(16)에도 성장되어 저항을 줄일 수 있게 된다. This growth is selective to the epi layer 18. The source / drain region are exposed to growth of polysilicon or SiGe gate 16 it is possible to reduce the resistance.
물론 게이트(16)와 소스/드레인은 전기적으로 절연되어 있다. Of course, the gate 16 and the source / drain thereof is electrically isolated.
도 6은 도 4a에 보여진 구조를 구현하기 위한 마스크 순서를 보이고 있다. Figure 6 shows the mask in order to implement the structure shown in Figure 4a.
도 6a에서는 Fin액티브 영역(4)을 구현하기 위한 것이고, 도 6b에서는 게이트(16)을 구현하기 위한 것이다. In Figure 6a is for implementing the Fin active region 4, in the Figure 6b is to implement the gate 16.
도 6c는 소스/드레인 콘택을 위한 콘택영역(46)를 보이고 있으며, 도 6d 배선을 위한 금속층(48)의 연결을 보이고 있다. Figure 6c is showing the connection of the metal layer 48 for the source / drain, and showing a contact region 46 for the contacts, wiring Figure 6d.
도 7은 본 발명에서 제안한 도 4의 구조를 채널을 중심으로 해서 수평과 수직 방향으로 자른 단면을 보이고 있다. Figure 7 is showing a cross section cut in the horizontal and vertical directions by the proposed architecture of Figure 4 in the present invention around the channel.
소스/드레인 영역은 폭이 좁은 Fin액티브 영역(4)와 같은 폭을 가지고 있어 저항이 크다. Source / drain regions there is greater resistance has the same width as the narrow Fin active region (4) width.
중앙 상단에 표시된 콘택영역(46)은 금속층(48)과 Fin액티브 영역(4)에 형성된 소스/드레인을 전기적으로 연결할 때 사용된다. Contact region 46 is displayed in the top center is used to electrically connect the source / drain formed on the metal layer 48 and the active region Fin (4).
도 8은 본 발명에서 제안한 도 5의 구조에서 소스/드레인 Fin액티브 영역(4)에 선택적 에피층(18)을 성장한 구조에 대해 채널을 중심으로 해서 수평과 수직 방향으로 자른 단면을 보이고 있다. Figure 8 shows the proposed also a selective epitaxial layer 18 on the source / drain active regions Fin (4) In the structure of 5 to around the channel for a structure grown cut in the horizontal and vertical cross-section in the present invention.
추가로 보인 좌측 하단의 단면(BB' 단면)을 보면 Fin액티브 영역(4)의 드러난 양쪽 측벽에 선택적 에피층(18)이 형성되어 있음을 알 수 있다. In an additional section (BB 'cross-section) of the lower left corner as shown it can be seen that the selective epitaxial layer 18 on either side of the side wall of the Fin exposed active region 4 is formed.
상기 선택적 에피층(18)은 Fin액티브 영역(4)의 양쪽 측벽은 물론이고 윗면에도 성장될 수 있다. The selective epitaxial layer 18 can be grown in both side walls of the Fin top active region 4, as well as.
소스/드레인 영역은 선택적 에피층(18) 형성 공정을 통하여 Fin액티브 영역(4)과 다르게 폭이 넓어 기생 소스/드레인 저항이 작다. Source / drain regions are selectively epitaxial layer 18 through the active region forming step Fin (4) Unlike the parasitic source / drain resistance is small, the increasing width.
중앙 상단에 표시된 콘택영역(46)은 금속 패턴(48)과 Fin액티브 영역(4)에 형성된 소스/드레인을 전기적으로 연결할 때 사용된다. Contact region 46 is displayed in the top center is used to electrically connect the source / drain formed on the metal patterns 48 and the Fin active region (4).
이하의 설명에서는 제안된 구조의 채널이 형성되는 바디를 보이기 위해 3 차원 그림을 사용하지 않고 주요 부분인 채널과 게이트(16)가 만나는 곳의 2차원 단면으로 표시한다. In the following description, the two-dimensional display with cross section of where the major part of the channel and the gate 16 meet without the use of a three-dimensional figure to show the channel body of the proposed structure to be formed.
도 9는 본 발명에서 제안한 FinFET 소자를 구현하기 위한 하나의 예로서, CMP(Chemical Mechanical Polishing)를 도입하여 구현하는 주요 공정단계를 2 차원 단면으로 보인다. 9 is as an example for implementing the proposed FinFET device in the present invention, showing a main process for implementing the introduction of CMP (Chemical Mechanical Polishing) in a two-dimensional cross section.
도 9a에서 벌크 실리콘기판(2b)에 제1산화막(6)을 형성하고 나노 패터닝을수행한 뒤, 제1산화막(6)과 벌크 실리콘기판(2b)의 실리콘을 식각한 것을 나타낸다. Forming a first oxide film (6) on a bulk silicon substrate (2b) in Fig. 9a and shows that a rear one, of etching the silicon of the first oxide film 6 and the bulk silicon substrate (2b) performing a nano-patterning.
나중에 벌크 실리콘기판(2b)에 연결되는 채널 Fin이 Fin액티브 영역(4)과 같이 형성된다. Later, the channel Fin connected to the bulk silicon substrate (2b) is formed as Fin active region (4).
이때 상기 제1산화막(6)의 두께는 0.5 nm에서 200 nm 사이의 두께를 사용하고, Fin액티브 영역(4)의 높이는 10 nm에서 1000 nm 사이의 값을, 그 폭은 4 nm에서 100 nm 사이의 값을 사용한다. At this time, between a value of said first oxide film 6 thickness is from 0.5 nm using a thickness of 200 nm, and the height of the Fin active region 4 in the 10 nm 1000 nm of, its width is in the 4 nm 100 nm the value is used.
도 9b에서는 도 9a에서 형성된 구조에 제2산화막(10)을 20 nm에서 1000 nm 사이의 두께로 바람직하게는, 20 nm에서 800 nm 사이의 두께로 형성하고 CMP를 통하여 식각한 단면을 나타낸다. In Figure 9b formed to a thickness between the structure formed in Figure 9a the second oxide film 10 in the 20 nm to a thickness of between 1000 nm and preferably, from 20 nm 800 nm and shows a cross section etched by a CMP.
도 9c에서는 도 9b에서 형성된 제2산화막(10)을 10 nm에서 300 nm 사이의 두께로 식각한 단면을 나타낸다. In Figure 9c shows a cross section etched by a thickness of between a second oxide film 10 formed in FIG. 9b from 10 nm 300 nm.
결국 제2산화막(10) 위로 돌출된 Fin액티브 영역(4)의 높이는 5 nm에서 300 nm 사이가 된다. After the height of the second oxide film 10 is Fin active region (4) projecting upwardly is between 300 nm at 5 nm.
도 9d에서는 형성된 Fin액티브 영역(4)에 게이트 산화막(12)을 0.5 nm에서 10 nm 사이의 두께로 성장한 단면을 나타낸다. A gate oxide film 12 to the Fin active regions 4 formed in the Fig 9d shows a cross-sectional grown at 0.5 nm at a thickness of between 10 nm.
상기 게이트 산화막(12)을 형성하기 전에 돌출된 Fin액티브 영역(4)의 측벽을 깨끗이 하고 이전 공정에 의한 데미지(damage)를 제거하기 위해 희생 산화막을 성장하였다가 제거한 후, 질소나 아르곤 분위기에서 어닐링을 수행함이 바람직하다. After removal of the sacrifice oxide film in order to remove the damage (damage) by refreshing the side wall of the overhanging Fin active region (4) and before the process before forming the gate oxide film 12 is grown, annealing in nitrogen or argon atmosphere. the carrying out preferred.
이후의 후속 공정으로 게이트 물질로 폴리실리콘(p + 나 n + 도우핑)이나 SiGe(p + 나 n + 도우핑) 또는 금속으로 층을 형성하고 사진전사(photolithography)를 통해 게이트(16)를 구현한다. To the next step after the gate material to form a polysilicon (p + or n + doping) or a SiGe layer (p + or n + doping) or metal, through the photo transfer (photolithography) implement the gate 16 do.
산화막을 형성하고 적절한 열처리 공정을 수행하며, 필요에 따라 산화막을 증착한다. Forming an oxide film, and perform the proper heat treatment step, and to deposit the oxide film, if necessary.
그리고 콘택영역(46)을 위한 사진전사(photolithography)를 수행한다. And it performs the picture transfer (photolithography) for the contact region (46).
소스/드레인과 전기적으로 연결이 될 금속층(48)을 증착하고 사진전사를 통해 금속 배선을 형성한다. Source / drain and depositing a metal layer electrically (48) to be connected and forming a metal wiring by the photo transfer.
도 10은 본 발명에서 제안한 FinFET 소자의 채널이 형성되는 바디를 구현하기 위한 하나의 예로서, CMP(Chemical Mechanical Polishing)를 도입하여 구현하는 주요 공정단계를 보인다. Figure 10 as an example for implementing the channel body of the proposed FinFET devices formed in the present invention, showing a main process for implementing the introduction of CMP (Chemical Mechanical Polishing).
도 10a에서 벌크 실리콘기판(2b)과 Fin액티브 영역(4)에 제1산화막(6)과 질화막(14)을 형성하고 나노 패터닝을 수행한 뒤 제1산화막(6)과 질화막(14), 그리고 실리콘을 식각한 것을 나타낸다. FIG one behind the first oxide film 6 and the nitride film (14) performing a first oxide film 6 and the nitride film 14 is formed and the nano-patterning on a bulk silicon substrate (2b) and Fin active region 4 at 10a, and and indicates that the etching of the silicon.
상기 질화막(14)은 CMP의 etch stopper로 사용되며, 그 두께는 10 nm에서 200 nm 사이의 값을 사용한다. The nitride film 14 is used as a CMP etch stopper, the thickness is from 10 nm using a value of 200 nm.
이때 상기 제1산화막(6)의 두께는 0.5 nm에서 200 nm 사이의 두께를 사용하고, Fin액티브 영역(4)의 높이는 10 nm에서 1000 nm 사이의 값을 사용한다. At this time, the first using a thickness between the thickness of the first oxide film (6) is in the 0.5 nm 200 nm, and the height of the Fin active region (4) using a value of 1000 nm at 10 nm.
도 10b에서는 도 10a에서 형성된 구조에 제2산화막(10)을 20 nm에서 1000 nm 사이의 두께로 바람직하게는, 20 nm에서 800 nm 사이의 두께로 형성하고 CMP를 통하여 식각한 단면을 나타낸다. In Figure 10b formed to a thickness between the structure formed in Figure 10a the second oxide film 10 in the 20 nm to a thickness of between 1000 nm and preferably, from 20 nm 800 nm and shows a cross section etched by a CMP.
도 10c에서는 도 10b에서 형성된 제2산화막(10)을 10 nm에서 300 nm 사이의 두께로 식각한 단면을 나타낸다. In Figure 10c shows a cross-section etched in the thickness between the second oxide film 10 formed in FIG. 10b from 10 nm 300 nm.
도 10d에서는 형성된 Fin액티브 영역(4)에 게이트 산화막(12)을 0.5 nm에서 10 nm 사이의 두께로 성장한 단면을 나타낸다. A gate oxide film 12 to the Fin active regions 4 formed in the FIG 10d shows a cross-sectional grown at 0.5 nm at a thickness of between 10 nm.
여기서 게이트 산화막(12)은 질화막(14)을 제거한 후 성장할 수도 있다. The gate oxide film 12 may grow after removing the nitride film 14.
산화막을 형성하고 적절한 열처리 공정을 수행하며, 필요에 따라 산화막을증착한다. Forming an oxide film, and perform the proper heat treatment step, and to deposit the oxide film, if necessary.
도 11은 본 발명에서 제안한 FinFET 소자의 채널이 형성되는 바디를 구현하기 위한 하나의 예로서, 선택적 에피 성장 방법으로 Fin 채널을 형성하여 구현하는 주요 공정단계를 보인다. Figure 11 as an example for implementing the channel body of the proposed FinFET devices formed in the present invention, showing a major processing step implemented by forming the Fin channel selective epitaxial growth method.
도 11a에서 벌크 실리콘기판(2b)에 두께가 20 nm에서 1000 nm 사이의 제2산화막(10)을 형성하고 나노 패터닝을 수행한 뒤 제2산화막(10)을 식각한 단면을 나타낸다. In Figure 11a after the formation of the second oxide film 10 between the bulk silicon substrate (2b) having a thickness of from 20 nm to 1000 nm and performing patterning nano shows a cross-sectional etching the second oxide film (10).
여기서 식각된 제2산화막(10)의 폭은 4 nm에서 100 nm 사이이고 깊이는 10 nm에서 1000 nm 사이의 값을 갖는다. The width of the second oxide film 10 is etched here in 4 nm between 100 nm and 10 nm in depth has a value between 1000 nm.
일종의 식각된 산화막 트랜치 바닥에 드러난 벌크 실리콘기판(2b)의 실리콘 영역을 씨앗으로 하여, 선택적 에피 성장 방법으로 적당한 높이의 선택적 에피층을 성장하여 Fin액티브 영역(4)을 형성한다. The silicon area of the bulk silicon substrate (2b) exposed on the floor kind of the etched trench oxide film as a seed, growing a selective epitaxial layer of appropriate height by selective epitaxial growth method to form a Fin active region (4).
상기 Fin액티브 영역(4) 위에 0.5 nm에서 200 nm 사이의 제1산화막(6)을 형성하고 그 위에 10 nm에서 200 nm 사이의 질화막(14)을 형성한다. To form the nitride film 14 between the Fin active region (4) forming a first oxide film (6) between 200 nm at 0.5 nm over and above that from 10 nm 200 nm.
CMP나 건식 식각을 통하여 증착한 두께 만큼 질화막(14)과 제1산화막(6)을 식각하면 도 11b와 같은 단면을 보이게 된다. When deposited as a thickness through the CMP or dry etching process of etching the nitride film 14 and the first oxide film 6 is shown the cross-section as shown in Fig. 11b.
도 11c에서는 제2산화막(10)을 10 nm에서 300 nm 사이의 두께로 식각한 단면을 보인다. Figure 11c shows a cross-section in the etching the second oxide film 10 in the 10 nm to a thickness of between 300 nm.
도 11d에서는 형성된 Fin액티브 영역(4)에 게이트 산화막(12)을 성장한 단면을 나타낸다. Also in Fin active regions 4 formed in the end surface 11d shows the growth of the gate oxide film 12.
이후의 후속 공정은 도 9d나 도 10d의 후속 공정과 같다. Since the subsequent processing is the same as the subsequent steps in FIG. 9d and FIG. 10d.
도 12는 본 발명에서 제안한 FinFET 소자의 채널이 형성되는 바디를 구현하기 위한 하나의 예로서, CMP를 사용하지 않고 대신 필드 산화막(28)을 성장하여 원하는 최종 구조를 구현하기 위한 주요 공정단계를 보인다. Figure 12 shows a main process step for the growth of the field oxide film 28, instead, without the use of CMP as an example for implementing the body channel of the proposed FinFET devices formed by the present invention to achieve the final structure desired .
여기서는 스페이서 산화막(26) 형성과 필드(field) 산화막(28) 성장기술을 도입하여 구현하는 방법의 주요 공정단계를 보이고 있다. This section shows the major process steps of a method implemented by introducing a spacer oxide film 26 is formed and a field (field) oxide film 28 is grown technology.
도 12a에서는 나노 사진전사를 수행하여 Fin액티브 영역(4)을 형성한 후, 0.5 nm에서 200 nm 사이 두께의 제1산화막(6)을 형성하고 그 위에 10 nm에서 200 nm 사이의 두께를 갖는 질화막(14)을 형성하며, 다시 그 위에 5 nm에서 500 nm 사이의 두께를 갖는 제3산화막(20)을 형성한다. After Figure 12a in by performing the nano-picture transfer form the Fin active region 4, from 0.5 nm to form a first oxide film (6) between a thickness of 200 nm and a nitride film having a thickness of 200 nm at 10 nm thereon forming the 14, and to form a third oxide layer 20 having a thickness of 500 nm in 5 nm thereon again.
상기 제3산화막(20), 질화막(14), 제1산화막(6) 및 벌크 실리콘기판(2b)의 실리콘을 식각하면 도 12a의 단면 구조를 얻게 된다. When etching the silicon of the third oxide layer 20, nitride layer 14, a first oxide film 6 and the bulk silicon substrate (2b) it is obtained a cross-sectional structure of Fig. 12a.
형성된 Fin액티브(4) 영역의 높이는 10 nm에서 1000 nm 사이의 값이 되게 한다. Fin formed active (4) the height of the area should be a value between 1000 nm at 10 nm.
이 상태에서 얇은 버퍼 산화막(22)을 1 nm에서 50 nm 사이의 두께로 형성하고 그 위에 산화방지용 질화막(24)을 5 nm에서 100 nm 사이의 두께로 형성한다. In this state, forming a thin buffer oxide film 22 from 1 nm to a thickness of between 50 nm and forms an oxidation resistant nitride film 24 thereon from 5 nm to a thickness of between 100 nm.
그 위에 다시 스페이서 산화막(26)을 5 nm에서 500 nm 사이의 두께로 형성하고 비등방 건식식각을 수행하면 스페이스 형태로 산화막(26)이 형성된다. When the spacer oxide film 26 is again formed over a thickness of between 5 nm 500 nm and performing anisotropic dry etching is formed in the oxide film 26 to form the space.
상기 Fin액티브 영역(4)의 양쪽 면과 윗면은 산화막(6,20,22,26)과 질화막(14,24)으로 싸여 있고, 다른 곳은 벌크 실리콘기판(2b)의 실리콘이 드러나 있게 된다. Each side surface and the upper surface of the Fin active region (4) which are wrapped with an oxide film (6,20,22,26) and the nitride layer (14,24), so that change is the silicon of the bulk silicon substrate (2b) exposed.
벌크 실리콘기판(2b)의 실리콘을 30 nm에서 300 nm 사이의 두께로 등방 식각하면 도 12b의 단면 구조가 된다. If isotropic etching the silicon of the bulk silicon substrate (2b) from 30 nm to a thickness of between 300 nm is a cross-sectional view of Fig 12b.
여기서 산화막(20,22,26)을 선택적으로 식각하면 도 12c와 같이 된다. Wherein selectively etching the oxide film (20,22,26) is as shown in Figure 12c.
이 상태에서 필드 산화막(28)을 30 nm에서 500 nm 사이 두께로 성장하고 질화막(14,24)을 제거하면 도 12d와 같은 단면을 갖게 된다. When in this state, the growth of the field oxide film 28 to 30 nm in thickness between 500 nm and removing the nitride layer (14,24) will have a cross section as shown in Fig. 12d.
결국 필드 산화막(28) 위로 돌출된 영역 Fin액티브 영역(4)의 높이는 5 nm에서 300 nm 사이가 된다. After the height of the active area region Fin (4) projecting over the field oxide film 28 is between 300 nm at 5 nm.
도 12d에서는 형성된 Fin액티브 영역(4)에 게이트 산화막(12)을 성장한 단면을 나타낸다. Also in Fin active regions 4 formed in the end surface 12d shows the growth of the gate oxide film 12.
이후의 후속 공정은 도 9d, 도 10d, 도 11d의 후속 공정과 같다. Subsequent processes are the same as after the subsequent steps of Fig 9d, Fig. 10d, FIG. 11d.
도 13은 본 발명에서 제안한 FinFET 소자의 채널이 형성되는 바디를 구현하기 위한 하나의 다른 예로서, 스페이서(30) 형성과 필드(field) 산화막(28) 성장기술을 도입하여 구현하는 방법의 주요 공정단계를 보인다. Figure 13 is the main process of the method for implementing the introduction of as a further example for implementing the body channel of the proposed FinFET devices formed in the present invention, the spacer 30 is formed with a field (field) oxide film 28 is grown Technology it seems a step.
도 12에 비해 스페이서(30)를 구성하는 물질만 다르다. Fig than 120,000 different from a material constituting the spacer 30.
도 13a에서는 나노 사진전사를 수행하여 Fin액티브 영역(4)을 형성한 후 0.5 nm에서 200 nm 사이 두께의 제1산화막(6)을 형성하고 그 위에 10 nm에서 200 nm 사이의 두께를 갖는 질화막(14)을 형성하며, 다시 그 위에 5 nm에서 500 nm 사이의 두께를 갖는 제3산화막(20)을 형성한다. Figure 13a In performing the nano-picture transfer to form a first oxide film (6) after the formation of the Fin active region (4) between at 0.5 nm 200 nm thick and a nitride film having a thickness of 200 nm in 10 nm on the ( 14) is formed, and to form a third oxide layer 20 having a thickness of 500 nm in 5 nm thereon again.
제3산화막(20), 질화막(14), 제1산화막(6) 및 벌크 실리콘기판(2b)의 실리콘을 식각하면 도 13a의 단면 구조를 얻게 된다. A third oxide layer 20, nitride layer 14, when etching the silicon of the first oxide film 6 and the bulk silicon substrate (2b) is obtained a cross-sectional structure of Fig. 13a.
이 상태에서 얇은 버퍼 산화막(22)을 1 nm에서 20 nm 사이의 두께로 형성하고 그 위에 산화방지용 질화막(24)을 5 nm에서 50 nm 사이의 두께로 형성한다. Formed to a thickness between the thin buffer oxide film 22 in this state from 1 nm to 20 nm is formed over the anti-oxy-nitride film (24) in the 5 nm to a thickness of between 50 nm.
그 위에 다시 스페이서(30) 물질로 폴리실리콘이나 아몰퍼스 실리콘으로 5nm에서 500 nm 사이의 두께로 형성하고 비등방 건식식각을 수행하면 스페이서(30)가 형성된다. When the above formed to a thickness between the back spacer 30 material is polysilicon or amorphous silicon to 500 nm at 5nm and performing anisotropic dry etching to form the spacer 30.
이 구조는 도 13b에서 보여주고, 도 13b의 스페이서(30)와 도 12b의 스페이서 산화막(26)은 그 물질이 다르다. This structure is shown in Fig 13b, the spacer 30 and the spacer oxide film 26 of Fig. 12b in Fig. 13b is different from the substance.
도 13b에서는 스페이서(30) 물질로 폴리실리콘이나 아몰퍼스 실리콘을 사용하는 데, 이는 도 12b에서 스페이서 산화막(26)을 식각할 때 산화방지용 질화막(24) 아래에 있는 버퍼 산화막(22)이 식각되어 이후의 필드 산화막(28) 성장에 나쁜 영향을 줄 수 있기 때문이다. Figure 13b in for using polysilicon or amorphous silicon as a spacer 30 material, which buffer oxide film 22 at the bottom of the oxidation resistant nitride film 24 when etching the spacer oxide layer 26. In Figure 12b since the etching a field oxide layer (28), because it can have a negative impact on growth.
또한 상기 폴리실리콘이나 아몰퍼스 실리콘은 높은 농도로 도우핑 되는 것도 가능하다. In addition, the polysilicon or amorphous silicon, it is also possible to be doped in high concentration.
도 13b에서 드러난 스페이서(30)와 벌크 실리콘기판(2b)을 식각하기 위해 실리콘을 30 nm에서 300 nm 사이의 두께로 등방 식각하면 도 13c의 단면 구조가 된다. There is shown a silicon to etch the exposed spacer 30 and the bulk silicon substrate (2b) from 30 nm 13b to a thickness of between 300 nm isotropic etching is a cross-sectional structure of FIG. 13c.
이 상태에서 필드 산화막(28)을 30 nm에서 500 nm 사이 두께로 성장하고 질화막(14,24)을 제거하면 도 13d와 같은 단면을 갖게 된다. When in this state, the growth of the field oxide film 28 to 30 nm in thickness between 500 nm and removing the nitride layer (14,24) will have a cross section as shown in Fig. 13d.
도 13d에서는 형성된 Fin액티브 영역(4)에 게이트 산화막(12)을 성장한 단면을 나타낸다. Also in Fin active regions 4 formed in the end surface 13d shows the growth of the gate oxide film 12.
이후의 후속 공정은 도 9d, 도 10d, 도 11d, 도 12d의 후속 공정과 같다. Subsequent processes after Fig. 9d, Fig. 10d, FIG. 11d, as a subsequent process of FIG. 12d.
이상에서 살펴본 바와 같이 본 발명에 의하면, 벌크 웨이퍼를 사용하여 가격이 싸고 게이트와 자기정렬되게 소스/드레인에 에피층을 형성하여 기생 저항성분을 줄일 수 있으며, 실리콘 구조물인 Fin액티브 영역은 채널이 형성되는 바디이고 벌크 웨이퍼와 연결되어 플로팅 바디 문제를 해결할 수 있을 뿐만 아니라 열전도가 잘 되어 소자의 특성을 향상시킬 수 있다. According to the present invention As described above, by using a bulk wafer cheap price can be the gate and self-aligned to form an epitaxial layer on the source / drain to reduce the parasitic resistance component, the silicon structure of Fin active region channel is formed a body connected to the bulk wafers, as well as to fix the floating body problem that the thermal conductivity can be well improve the properties of the device.
포함하는 이중-게이트 FinFET 소자. Dual containing-gate FinFET devices.
청구항 1에 있어서, 상기 Fin액티브 영역의 폭이 4 nm ∼ 100 nm인 것을 특징으로 하는 이중-게이트 FinFET 소자. The method according to claim 1, characterized in that the double width of the Fin active area of 4 nm ~ 100 nm - gate FinFET devices.
청구항 1 또는 청구항 2에 있어서, 상기 Fin액티브 영역의 높이가 벌크 실리콘기판 표면으로부터 10 nm ∼ 1000 nm인 것을 특징으로 하는 이중-게이트 FinFET 소자. The method according to claim 1 or claim 2, characterized in that the double height of the Fin active area of 10 nm ~ 1000 nm from a bulk silicon substrate surface-gate FinFET devices.
청구항 3에 있어서, 상기 Fin액티브 영역의 높이가 제2산화막 표면으로부터 5 nm ∼ 300 nm인 것을 특징으로 하는 이중-게이트 FinFET 소자. The method according to claim 3, characterized in that the double height of the active area of Fin 5 nm ~ 300 nm from the second oxide film surface-gate FinFET devices.
청구항 1에 있어서, 상기 게이트 산화막의 두께는 0.5 nm ∼ 10 nm이고, 제1산화막의 두께는 0.5 nm ∼ 200 nm인 것을 특징으로 하는 이중-게이트 FinFET 소자. The method according to claim 1, characterized in that the double of the thickness is 0.5 nm ~ 200 nm of the thickness of the gate oxide film is 0.5 nm ~ 10 nm, the first oxide film-gate FinFET devices.
청구항 1에 있어서, 상기 제2산화막의 두께를 20 nm ∼ 800 nm로 하여 게이트와 벌크 실리콘기판 사이의 기생용량 성분을 줄인 것을 특징으로 하는 이중-게이트 FinFET 소자. The method according to claim 1, characterized in that the double thickness of the second oxide film with 20 nm ~ 800 nm with reduced parasitic capacitance component between the gate and the bulk silicon substrate, a gate FinFET devices.
청구항 1에 있어서, 상기 금속층과 접촉하는 콘택영역을 Fin액티브 영역의 폭이나 게이트 길이보다 크게 하여 콘택 저항을 줄인 것을 특징으로 하는 이중-게이트 FinFET 소자. The method according to claim 1, for the double contact region in contact with said metal layer characterized in that to reduce the contact resistance significantly less than the width or the gate length of the active region Fin-gate FinFET devices.
청구항 1에 있어서, 상기 소스/드레인은 게이트와 겹치는 Fin액티브 영역을 제외한 Fin액티브 영역 양쪽에, 게이트와 자기정렬 형태로 기생저항을 줄이기 위해형성된 선택적 에피층을 성장한 것임을 특징으로 하는 이중-게이트 FinFET 소자. The method according to claim 1, wherein the source / drain, characterized in both Fin active region except the overlapping Fin active region and gate, that the growth of the gate with selective epitaxial layer is formed to reduce a parasitic resistance to the self-alignment type double-gate FinFET device .
상기 게이트가 10 20 cm -3 이상으로 도우핑 된 상태에서 습식으로 산화시켜, 게이트의 산화비가 Fin액티브 영역보다 큰 것을 이용하여, 성장한 산화막을 일부 식각하고, Fin액티브 영역의 측벽에 드러난 실리콘을 씨앗으로 한 것임을 특징으로 하는 이중-게이트 FinFET 소자. By oxidation in the above gate is doped with more than 10 20 cm -3 in a wet state, by the gate oxide Fin ratio is greater than the active area, and some etching the grown oxide film, a silicon seed exposed to the side wall of the Fin active region double, characterized in that a by-gate FinFET devices.
상기 게이트에 절연막을 증착하고 이 절연막 두께와 상기 제2산화막 위로 돌출된 Fin액티브 영역의 높이만큼 비등방 식각하여 Fin액티브 영역과 게이트가 만나는 근처를 제외한 드러난 Fin액티브 영역의 실리콘과 게이트의 폴리실리콘을 씨앗으로 한 것임을 특징으로 하는 이중-게이트 FinFET 소자. The depositing an insulating film on the gate insulating film thickness and said second oxide layer over the protruding Fin active region of a height by anisotropic etching to Fin active region and the gate of the silicon and the gate polysilicon of exposed Fin active areas except near the meeting seeds double, characterized in that a by-gate FinFET devices.
청구항 8 내지 청구항 10중 어느 한 항에 있어서, 상기 선택적 에피층의 물질은 단결정 실리콘, 단결정 SiGe, 단결정 Ge, 폴리실리콘, 폴리 SiGe 중에서 하나 이상인 것을 특징으로 하는 이중-게이트 FinFET 소자. Gate FinFET device-according to any one of claim 8 to claim 10, the material of the selective epitaxial layer is double, characterized in that at least one of single crystal silicon, single crystal SiGe, Ge single crystal, polysilicon, poly-SiGe.
청구항 1에 있어서, 상기 Fin액티브 영역에 형성되는 소스/드레인을 위한 도우핑의 접합 깊이가, 제2산화막 위쪽 표면을 기준(0 nm)으로 할 때, 위쪽으로 0 nm ∼ 50 nm인 것을 특징으로 하는 이중-게이트 FinFET 소자. The method according to claim 1, as to the Fin dough junction depth of mapping for the source / drain formed on an active region that, in the second oxide upper surface of the reference (0 nm), characterized in that the top of the 0 nm ~ 50 nm dual-gate FinFET devices.
청구항 1에 있어서, 상기 Fin액티브 영역에 형성되는 소스/드레인을 위한 도우핑의 접합 깊이가 제2산화막 위쪽 표면을 기준(0 nm)으로 할 때, 아래쪽으로 0 nm ∼ -50 nm인 것을 특징으로 하는 이중-게이트 FinFET 소자. The method according to claim 1, wherein, when the Fin junction depth of doping for the source / drain formed on an active region is to be a reference (0 nm) to a second oxide upper surface, characterized in that the bottom of the 0 ~ nm -50 nm dual-gate FinFET devices.
청구항 1에 있어서, 상기 Fin액티브 영역의 폭이 벌크 실리콘기판에 가까워지면서 산화막 내에서 넓어져 상기 Fin액티브 영역의 저항이 줄어듬을 특징으로 하는 이중-게이트 FinFET 소자. The method according to claim 1, which is double the width of the Fin active region as it nears the bulk silicon substrate spreads in the oxide film characterized in that the resistance of the active region juleodeum Fin-gate FinFET devices.
청구항 1에 있어서, 상기 Fin액티브 영역이 상부 폭은 좁고, 하부 폭이 넓은 사다리꼴 모양인 것을 특징으로 하는 이중-게이트 FinFET 소자. Gate FinFET device - according to claim 1, wherein the double-Fin active region is characterized in that the top width is narrow, the bottom width of a wide trapezoidal shape.
청구항 1에 있어서, 상기 Fin액티브 영역의 두 상부 모서리가 산화공정, 식각공정 또는 수소 분위기에서의 어닐링에 의해 둥글게 형성됨을 특징으로 하는 이중-게이트 FinFET 소자. The method according to claim 1, double the two upper corners of the Fin active area features a rounded formed by annealing in the oxidation process, an etching process or a hydrogen atmosphere-gate FinFET devices.
포함하는 이중-게이트 FinFET 소자 제조방법. Dual containing-gate FinFET device manufacturing method.
상기 Fin액티브 영역을 제외한 벌크 실리콘기판의 나머지 표면에 제2산화막을 덮고, 상기 제2산화막을 CMP(Chemical Mechanical Polishing)를 이용하여 평탄화한 뒤, Fin액티브 영역의 표면에서 아래로 적정 두께만큼 식각하는 공정인 것을특징으로 하는 이중-게이트 FinFET 소자 제조방법. The Fin cover the second oxide film to the remaining surface of the bulk silicon substrate other than the active region, the second oxide film to then planarized using a CMP (Chemical Mechanical Polishing), to etching by an appropriate thickness down from the surface of the Fin active region double characterized in that the step-gate FinFET device manufacturing method.
상기 제2산화막을 적정한 두께만큼 식각하는 공정인 것을 특징으로 하는 특징으로 하는 이중-게이트 FinFET 소자 제조방법. Gate FinFET device manufacturing method-double, characterized in that characterized in that the step of etching the second oxide film by a proper thickness.
상기 필드 산화막 형성 공정은, 상기 벌크 실리콘기판과 Fin액티브 영역에 버퍼 산화막/산화방지용 질화막/스페이서를 형성하여 식각을 수행하고 이때 드러난 상기 벌크 실리콘기판의 실리콘을 식각하며, 상기 스페이서를 제거한 상태에서 벌크 실리콘기판을 열산화시켜 필드 산화막을 성장한 후 버퍼 산화막과 산화방지용 질화막을 제거하는 공정인 것을 특징으로 하는 이중-게이트 FinFET 소자 제조방법. The field oxide film forming step is to form the bulk silicon substrate and Fin buffer oxide film on the active region / oxidation proof nitride film / spacer perform the etching, and wherein exposed etching the silicon of the bulk silicon substrate, and the bulk while removing the spacers gate FinFET device manufacturing method, heating by the double, characterized in that after the step of removing the buffer oxide film and oxidation resistant nitride film grown the field oxide film oxidizing the silicon substrate.
청구항 20에 있어서, 상기 스페이서의 물질은 폴리실리콘이나 아몰퍼스 실리콘인 것을 특징으로 하는 이중-게이트 FinFET 소자 제조방법. The method according to claim 20, the material of the spacer is a double, characterized in that polysilicon or amorphous silicon a-gate FinFET device manufacturing method.
청구항 17에 있어서, 상기 게이트 산화막을 형성하기 전에 돌출된 Fin액티브 영역의 측벽을 깨끗이 하고 이전 공정에 의한 데미지(damage)를 제거하기 위해 희생 산화막을 성장하였다가 제거한 후, 질소나 아르곤 분위기에서 어닐링을 수행함을 특징으로 하는 이중-게이트 FinFET 소자 제조방법. After according to claim 17, the sacrifice oxide film in order to remove the damage (damage) by refreshing the side wall of the protruding Fin active region and before the step prior to forming said gate oxide film grown removed, the annealing in a nitrogen or argon atmosphere. double, characterized by carrying out-gate FinFET device manufacturing method.
폴리실리콘, 폴리 SiGe, 금속중에서 어느 하나로 층을 형성하고 이 층에 대해 사진전사를 수행하는 공정인 것을 특징으로 하는 것을 이중-게이트 FinFET 소자 제조방법. The method gate FinFET device-polysilicon, poly-SiGe, to form a double layer by any one from the group consisting of metals, and characterized in that the step of performing a transfer for a picture layer.


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Aortic prosthetic size predictor in aortic valve replacement
Anh Tuan Vo ORCID: orcid.org/0000-0001-8273-681X1,
Tomomi Nakajima2,
Trang Thi Thu Nguyen1,
Nguyen Thoi Hai Nguyen3,
Nga Bich Le3,
Tri Huu Cao4 &
Dinh Hoang Nguyen1,3
Patient-prosthesis mismatch (PPM) is a major concern in aortic valve replacement (AVR) and leads to perioperative morbidity and rehospitalization. Predicting aortic annulus diameter pre-procedurally is crucial to managing patients with high-risk of PPM.
To compare preoperative measurements of aortic annulus from echocardiography and CT scan with surgical sizing and develop an imaging-based algorithm to predict PPM.
From January 2017 to December 2020, patients underwent AVR at a teaching hospital were examined. The relationship between imaging measurements with operative values was assesed using scatter plots and Pearson's correlation coefficient. Univariable linear regression was then used to build the predictive model.
A total of 144 patients underwent AVR during the study period. Suture types and surgical approaches were not significantly associated with prosthesis size. CT scan-based measurements showed strong correlation with prosthesis size: mean diameter (R = 0.79), perimeter-derived diameter (R = 0.76), and area-derived diameter (R = 0.75). Mechanical valve and tissue valve shared similar correlation coefficients. Prosthesis size predictive models based on CT scan were 12.89 + 0.335 × d for mean diameter, 13.275 + 0.315 × d for perimeter-derived diameter and 13.626 + 0.309 × d for area-derived diameter.
Preoperative CT scan measurements are a reliable predictor of aortic prosthesis size. Transthoracic echocardiography is a possible alternative, though it is highly performer-dependent and unable to represent the aortic annulus fully. Together, these two imaging modalities can be used to quantitatively anticipate PPM preoperatively.
Aortic valve replacement (AVR) remains the gold standard for patients with valvular lesions like aortic stenosis. A major complication following AVR is patient-prosthesis mismatch (PPM), a nonstructural dysfunction. First described in 1978 [1], PPM occurs when excessive pressure gradient is generated across a normally functioning prosthetic valve. Its severity is determined by the indexed effective orifice area (EOAi) as follows: not clinically significant (none or mild) when > 0.85 cm2/m2, moderate when between 0.65 and 0.85 cm2/m2, and severe when ≤ 0.65 cm2/m2.
While the negative impact of PPM in the early recovery period is controversial, it generally increases perioperative morbidity and rehospitalization due to heart failure and lack of left ventricular mass regression, and eventually long-term mortality [2, 3]. Several factors were found to increase the likelihood of PPM, including female sex, younger age, high body surface area (BSA), left ventricular end systolic diameter, aortic root dimension [4], hypertension, diabetes, renal failure, and utilization of bioprothesis [5]. Among these, calculating BSA from a patient's height and weight has been suggested as the first in a simple three-step algorithm to determine the type and size of prosthesis according to EOAi's reference values [6]. The aforementioned risk factors can easily be recognized clinically and preoperatively; however, their qualitative nature prevents surgeons from knowing whether further operative considerations, such as aortic root enlargement (ARE), are warranted.
With the above limitations in mind, multimodality imaging has been proposed as a powerful and comprehensive approach to identify and quantitate PPM [7]. 2D/3D transthoracic (TTE) and multidetector computed tomography (CT) remain the most widely used tools to measure the aortic annulus dimensions pre-procedurally [3]. Previous studies have documented the superiority of CT measurements as compared to echocardiographic values and recommended the former to be routinely included in prosthesis sizing [8]. In practice, however, some inconsistencies still exist between calculated values and actual manufacturers' prothesis size. Hence, a more direct and robust imaging-based algorithm would significantly improve the ability to predict PPM before implantation.
Herein, we examined AVR cases from our institution and assessed the correlation between the aortic valve diameter as measured by echocardiography and CT scan preoperatively versus the true size of implanted valve. Our aim is to develop an imaging-based algorithm to predict the prosthesis valve size prior to AVR.
This retrospective cohort study included patients who underwent AVR at the Department of Cardiovascular Surgery, University Medical Center at Ho Chi Minh City from January 2017 to December 2020. All patients had 128-slice CT scan and TTE and both were used to calculate the aortic annulus.
The aortic annulus is a crown-shaped structure that serves as the insertion point for the aortic cusps. Its highest and lowest points are located at each of the three commissures and between any two of them, respectively. The annulus, which lacks a planar structure, is compressed to the round-shaped prosthesis after conventional AVR. We therefore assumed that prothesis size is correlated with the plane passing all three nadirs of the aortic valve.
Using TTE, the diameters of aortic annulus and left ventricular outflow tract (LVOT), as well as the sinus of Valsalva, sinotubular junction (STJ) and ascending aorta, were measured on the parasternal long axis view (PLAX) (Fig. 1). While reproducible, the results were greatly dependent on echocardiographers.
Measurement of aortic annulus diameters on TTE
On CT scan, we employed multiplanar reconstruction (OsiriX™ software, Bernex, Switzerland) to map out the plane that passes through three nadirs of the aortic valve. The largest, smallest, average, perimeter-derived and area-derived diameters were then calculated (Fig. 2).
Measurement of aortic annulus diameters on CT scan
All diameters were measured at end-systole.
We performed AVR via three approaches: conventional full sternotomy, upper ministernotomy or second intercostal minithoracotomy. For the minimally invasive procedures, peripheral cardiopulmonary bypass (CPB) was established with femoral vessels. Custodiol® HTK Solution was delivered antegradely into the aortic root or the coronary ostia in patients with severe aortic regurgitation and was repeated every 120 min if necessary. We used single annular sutures for intra-annular valve replacement and ventricular-side pledgeted sutures for supra-annular valve replacement. Pledgeted sutures (supra-annular fashion) were utilized when severe calcifications were found on the valve leaflets and annulus. Finally, transesophageal echocardiography (TEE) was used to assess the surgery results.
For mechanical valve, we used SJM™ Masters Series Mechanical Heart Valve (Abbott Laboratories, Chicago, Illinois, USA). For tissue valve, we used Carpentier-Edwards PERIMOUNT Magna Ease (Edwards Lifesciences, Irvine, California, USA).
Data analysis was performed using MedCalc version 19 (Medcalc Software Ltd, Ostend, Belgium). The associations between imaging measurements and valve size were evaluated using scatter plots and Pearson's correlation coefficients. Linear regression model was used to predict the surgical sizing from imaging-based values. As strong correlations between parameters were found, we performed univariable linear regression and selected the highest correlated measurements to build the prediction model (outcome = a + b × measurement; a: intercept; b: slope). The 95% confidence interval (CI) of the slope and intercept are reported. We analyzed the whole dataset and then performed subgroup analyses for tissue valve and mechanical valve. Statistically significant p value was set to equal or less then 0.05.
A total of 144 patients were included in our study. Baseline and operative characteristics are presented in Tables 1 and 2, respectively. Overall, we found no significant differences in the durations of cardiopulmonary bypass, cross-clamp, mechanical ventilation and ICU stay among three surgical techniques. Interestingly, patients undergoing second intercostal minithoracotomy had longer CPB and cross-clamp time but shorter mechanical ventilation length and ICU stay. Regarding adverse outcome, one death occured at postoperative day five due to cerebral hemorrhage. No aortic dissection was recorded. Nine patients required reoperation due to bleeding, including five cases of full sternotomy, three upper ministernotomies and one second intercostal minithoracotomy. Operative approach was changed to full sternotomy in two patients due to uncontrolled bleeding (upper ministernotomy, one case) and poor exposure (second intercostal minithoracotomy, one case).
Table 1 Baseline characteristics
Table 2 Intraoperative details
Table 3 illustrates prosthesis size as according to two suture techniques, namely intra-annular single suture and supra-annular pledgeted suture, and three surgical approaches. Neither parameters significantly affect the prosthesis size.
Table 3 Prosthesis size according to different suture techniques and surgical approaches
The relationship between diameters calculated by imaging modalities and the implanted prothesis size was computed using Pearson correlation coefficients (Table 4) and graphed as scatterplots (Fig. 3). TTE-measured diameters showed the weakest correlation, whereas those calculated from CT scan were strongly correlated with surgical prosthesis sizing (coefficients were greater than 0.70 for all diameters and for both mechanical and tissue valve). Hence, CT-based predictive model of aortic prothesis size were developed using univariable linear regression (Table 5).
Table 4 Pearson correlation coefficients between imaging-measured diameters and intraoperative prothesis size
Scatterplots for the correlation of each calculated diameters with prosthesis size
Table 5 CT scan-based prediction model of aortic prosthesis size
The major finding of this study is that CT-calculated aortic annulus diameter is more reliable than TTE preoperatively and hence could be used to develop a predictive model of prosthesis size, eventually preventing PPM.
Several preventive strategies can be considered when PPM following AVR is likely [3]. A newly developed generation of prosthesis, the stentless bioprosthesis, is a valve designed for supra-annular implantation [9]. The new era of transcatheter AVR (TAVR) also promised to lower the prevalence of PPM, with supporting data from Asian population [10, 11]. Nevertheless, these valves might not be commercially available or too costly for patients in developing countries. Under these circumstances, aortic root enlargement (ARE) is commonly indicated to place a larger valve and has been performed for many years. However, not only does this practice add to operation time and complexity, but could also negatively affect morbidity and mortality in the field of minimally invasive surgical AVR, such as mini-thoracotomy and upper ministernotomy [12]. In addition, ARE is associated with several complications, such as mitral valve prolapse and aorto-left atrial fistula [13]. Therefore, recognizing the need for ARE and adequately determining a patient's risk of PPM are crucial prior to AVR.
This study compared preoperative CT scan and TTE measurements of aortic annulus diameter to intraoperative annular sizing. Our results agree with previous literature, which indicated that CT-based calculations were better correlated with operative values. In particular, Kempert et al. demonstrated that utilizing the "effective" diameter on CT scan is preferable to TTE values in patients with oval-shaped annulus [14]. Likewise, Daskevish et al. found that the calculated annular measurements with CT are closer to operative sizing with a Hegar dilator [8]. While suggesting that imaging modalities (CT and TTE) could be fairly accurate in predicting the aortic annulus size, both studies shared similar limitations, i.e. small sample size (26–33 patients) and did not establish predictive models. A recent review by Pibarot et al. proposed an algorithm to predict and prevent PPM by using multidetector CT or 3D TEE but still did not provide an estimated prothesis size preoperatively [3]. This could lead to unplanned ARE during AVR and pose major challenges to inexperienced surgeons.
The superiority of CT scan over echocardiography can be explained as follows. TTE is echocardiographer-dependent, and a single dimension on PLAX cannot represent the whole aortic annulus. On the other hand, CT scan provides three different diameters (mean, perimeter-derived and area-derived diameter) that are fairly comparable when calculating the prosthesis size preoperatively. In practice, however, echocardiography is non-invasive and presents as the only option when CT scan is contraindicated or unavailable. Hence, measurements predicted from TTE alone could still be considered while bearing in mind that they might not be as accurate as CT scan-based. Our study showed that CT-calculated algorithms for mechanical and tissue valve shared similar coefficients, thus proving CT-based predictor as applicable for both prothesis types. Overall, we recommend combining all three diameters on CT scan to minimize possible errors during measurements.
To our knowledge, this is the first study to propose a quantitative, imaging-based model to predict PPM prior to AVR. Knowing each patient's predictive prosthesis size, surgeons can anticipate and develop suitable strategies (eg using valves with larger EOAi, preparing for ARE or performing TAVR in lieu of surgical AVR) before incision. This would in turn help decrease morbidity caused by unintended procedures and lead to better patient outcome.
The main limitations of this study are its retrospective nature, small sample size and that few types of prostheses were used to establish the predictors. As different manufacturers produce protheses with similar size but largely inconsistent dimensions, the two most popular prostheses in our center were chosen to increase the model accuracy (SJM™ Masters Series for mechanical valve and Carpentier-Edwards PERIMOUNT Magna Ease for bioprosthesis). As a result, the suggested algorithm might only apply to these two and further studies using a wider variety of prothesis types are needed.
Preoperative CT scan measurements is efficient in predicting the size of aortic prosthesis. If CT is contraindicated or unavailable, TTE is an alternative imaging method, though its dependence on echocardiographers and inability to represent the full aortic annulus limit its accuracy. Together, these two imaging modalities can be incorporated into a quantitative and straightforward algorithm to predict PPM preoperatively.
AVR:
Aortic valve replacement
Aortic root enlargement
PPM:
Patient-prosthesis mismatch
Cadiopulmonary bypass
TAVR:
Transcatheter aortic valve replacement
TTE:
Transthoracic echocardiography
TEE:
Transeophageal echocardiography
PLAX:
Parasternal long axis
LVOT:
EOA:
Effective orifice area
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Pibarot P, Magne J, Leipsic J, et al. Imaging for predicting and assessing prosthesis-patient mismatch after aortic valve replacement. JACC Cardiovasc Imaging. 2019;12(1):149–62.
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The authors received no specific funding for this work.
Department of Cardiovascular Surgery, University Medical Center, University of Medicine and Pharmacy at Ho Chi Minh City, 215 Hong Bang Street, District 5, Ho Chi Minh City, Vietnam
Anh Tuan Vo, Trang Thi Thu Nguyen & Dinh Hoang Nguyen
Department of Cardiovascular Surgery, Faculty of Medicine, University of Tsukuba, Tsukuba, Japan
Tomomi Nakajima
Department of Thoracic and Cardiovascular Surgery, Faculty of Medicine, University of Medicine and Pharmacy at Ho Chi Minh City, Ho Chi Minh City, Vietnam
Nguyen Thoi Hai Nguyen, Nga Bich Le & Dinh Hoang Nguyen
Department of Surgery, Nguyen Tri Phuong Hospital, Ho Chi Minh City, Vietnam
Tri Huu Cao
Anh Tuan Vo
Trang Thi Thu Nguyen
Nguyen Thoi Hai Nguyen
Nga Bich Le
Dinh Hoang Nguyen
Conceptualize: ATV, DHN. Design: ATV, TTTN. Carry out analyses: TN, TTTN, NTHN, NBL, THC. Intepret study results: ATV, TTTN, TN, NTHN. Draft manuscript: ATV, TN. Revise: DHN. Approve final manuscript: ATV, TN, TTTN, NTHN, NBL, THC, DHN. All authors read and approved the final manuscript.
Correspondence to Dinh Hoang Nguyen.
The research was approved by the ethical board of the University of Medicine and Pharmacy at Ho Chi Minh City, number 146/HDDD-DHYD, on February 22nd 2021.
All authors of this paper have read and approved the final version submitted.
Vo, A.T., Nakajima, T., Nguyen, T.T.T. et al. Aortic prosthetic size predictor in aortic valve replacement. J Cardiothorac Surg 16, 221 (2021). https://doi.org/10.1186/s13019-021-01601-z
DOI: https://doi.org/10.1186/s13019-021-01601-z
Prosthetic size predictor
Patient-prothesis mismatch

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Share this Story: Austria's Kurz says stepping down as chancellor
Austria's Kurz says stepping down as chancellor
Oct 09, 2021 • October 9, 2021 • < 1 minute read • Join the conversation
VIENNA — Austrian Chancellor Sebastian Kurz said on Saturday he is stepping down after being placed under investigation on suspicion of corruption offenses.
Kurz said in a statement to the media that he was proposing Foreign Minister Alexander Schallenberg, a career diplomat, as his successor. Kurz plans to remain leader of his conservative party and take over as its leader in parliament, he added. (Reporting by Francois Murphy, Editing by William Maclean)
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