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Year created
Supersedes
PCI-X
Width in bits
1 per lane; 1-32 bonded lanes
No. of devices
One device each on each endpoint of each connection. PCI Express switches can create multiple endpoints out of one endpoint to allow sharing one endpoint with multiple devices.
For single-lane (×1) and 16-lane (×16) links, in each direction:
v. 1.x (2.5 GT/s):
250 MB/s (×1)
4 GB/s (×16)
v. 2.x (5 GT/s):
15.75 GB/s (×16)
v. 4.x (16 GT/s):
1.969 GB/s (×1)
8 GB/s (×1)
128 GB/s (×16)
Hotplugging interface
Yes, if ExpressCard, Mobile PCI Express Module, XQD card or Thunderbolt
External interface
Yes, with PCI Express OCuLink and External Cabling, such as Thunderbolt
pcisig.com
Various slots on a computer motherboard, from top to bottom:
PCI Express ×4
PCI Express ×16
Conventional PCI (32-bit, 5 V)
PCI Express (Peripheral Component Interconnect Express), officially abbreviated as PCIe or PCI-e,[1] is a high-speed serial computer expansion bus standard, designed to replace the older PCI, PCI-X and AGP bus standards. It is the common motherboard interface for personal computers' graphics cards, hard drives, SSDs, Wi-Fi and Ethernet hardware connections.[2] PCIe has numerous improvements over the older standards, including higher maximum system bus throughput, lower I/O pin count and smaller physical footprint, better performance scaling for bus devices, a more detailed error detection and reporting mechanism (Advanced Error Reporting, AER[3]), and native hot-swap functionality. More recent revisions of the PCIe standard provide hardware support for I/O virtualization.
Defined by its number of lanes,[4] the PCI Express electrical interface is also used in a variety of other standards, most notably the laptop expansion card interface ExpressCard and computer storage interfaces SATA Express, U.2 (SFF-8639) and M.2.
Format specifications are maintained and developed by the PCI-SIG (PCI Special Interest Group), a group of more than 900 companies that also maintain the conventional PCI specifications.
An example of the PCI Express topology; white "junction boxes" represent PCI Express device downstream ports, while the gray ones represent upstream ports.[5]:7
A PCI Express ×1 card containing a PCI Express switch (covered by a small heat sink), which creates multiple endpoints out of one endpoint and allows it to be shared by multiple devices
Conceptually, the PCI Express bus is a high-speed serial replacement of the older PCI/PCI-X bus.[6] One of the key differences between the PCI Express bus and the older PCI is the bus topology; PCI uses a shared parallel bus architecture, in which the PCI host and all devices share a common set of address, data and control lines. In contrast, PCI Express is based on point-to-point topology, with separate serial links connecting every device to the root complex (host). Because of its shared bus topology, access to the older PCI bus is arbitrated (in the case of multiple masters), and limited to one master at a time, in a single direction. Furthermore, the older PCI clocking scheme limits the bus clock to the slowest peripheral on the bus (regardless of the devices involved in the bus transaction). In contrast, a PCI Express bus link supports full-duplex communication between any two endpoints, with no inherent limitation on concurrent access across multiple endpoints.
In terms of bus protocol, PCI Express communication is encapsulated in packets. The work of packetizing and de-packetizing data and status-message traffic is handled by the transaction layer of the PCI Express port (described later). Radical differences in electrical signaling and bus protocol require the use of a different mechanical form factor and expansion connectors (and thus, new motherboards and new adapter boards); PCI slots and PCI Express slots are not interchangeable. At the software level, PCI Express preserves backward compatibility with PCI; legacy PCI system software can detect and configure newer PCI Express devices without explicit support for the PCI Express standard, though new PCI Express features are inaccessible.
The PCI Express link between two devices can vary in size from one to 32 lanes. In a multi-lane link, the packet data is striped across lanes, and peak data throughput scales with the overall link width. The lane count is automatically negotiated during device initialization, and can be restricted by either endpoint. For example, a single-lane PCI Express (×1) card can be inserted into a multi-lane slot (×4, ×8, etc.), and the initialization cycle auto-negotiates the highest mutually supported lane count. The link can dynamically down-configure itself to use fewer lanes, providing a failure tolerance in case bad or unreliable lanes are present. The PCI Express standard defines link widths of ×1, ×2, ×4, ×8, ×12, ×16 and ×32.[5]:4,5 This allows the PCI Express bus to serve both cost-sensitive applications where high throughput is not needed, and performance-critical applications such as 3D graphics, networking (10 Gigabit Ethernet or multiport Gigabit Ethernet), and enterprise storage (SAS or Fibre Channel). Slots and connectors are only defined for a subset of these widths, with link widths in between using the next larger physical slot size.
As a point of reference, a PCI-X (133 MHz 64-bit) device and a PCI Express 1.0 device using four lanes (×4) have roughly the same peak single-direction transfer rate of 1064 MB/s. The PCI Express bus has the potential to perform better than the PCI-X bus in cases where multiple devices are transferring data simultaneously, or if communication with the PCI Express peripheral is bidirectional.
A PCI Express link between two devices consists of one or more lanes, which are dual simplex channels using two differential signaling pairs.[5]:3
PCI Express devices communicate via a logical connection called an interconnect[7] or link. A link is a point-to-point communication channel between two PCI Express ports allowing both of them to send and receive ordinary PCI requests (configuration, I/O or memory read/write) and interrupts (INTx, MSI or MSI-X). At the physical level, a link is composed of one or more lanes.[7] Low-speed peripherals (such as an 802.11 Wi-Fi card) use a single-lane (×1) link, while a graphics adapter typically uses a much wider and therefore faster 16-lane (×16) link.
A lane is composed of two differential signaling pairs, with one pair for receiving data and the other for transmitting. Thus, each lane is composed of four wires or signal traces. Conceptually, each lane is used as a full-duplex byte stream, transporting data packets in eight-bit "byte" format simultaneously in both directions between endpoints of a link.[8] Physical PCI Express links may contain from one to 32 lanes, more precisely 1, 2, 4, 8, 12, 16 or 32 lanes.[5]:4,5[7] Lane counts are written with an "×" prefix (for example, "×8" represents an eight-lane card or slot), with ×16 being the largest size in common use.[9] Lane sizes are also referred to via the terms "width" or "by" e.g., an eight-lane slot could be referred to as a "by 8" or as "8 lanes wide."
For mechanical card sizes, see below.
Serial bus
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The bonded serial bus architecture was chosen over the traditional parallel bus because of inherent limitations of the latter, including half-duplex operation, excess signal count, and inherently lower bandwidth due to timing skew. Timing skew results from separate electrical signals within a parallel interface traveling through conductors of different lengths, on potentially different printed circuit board (PCB) layers, and at possibly different signal velocities. Despite being transmitted simultaneously as a single word, signals on a parallel interface have different travel duration and arrive at their destinations at different times. When the interface clock period is shorter than the largest time difference between signal arrivals, recovery of the transmitted word is no longer possible. Since timing skew over a parallel bus can amount to a few nanoseconds, the resulting bandwidth limitation is in the range of hundreds of megahertz.
A serial interface does not exhibit timing skew because there is only one differential signal in each direction within each lane, and there is no external clock signal since clocking information is embedded within the serial signal itself. As such, typical bandwidth limitations on serial signals are in the multi-gigahertz range. PCI Express is one example of the general trend toward replacing parallel buses with serial interconnects; other examples include Serial ATA (SATA), USB, Serial Attached SCSI (SAS), FireWire (IEEE 1394), and RapidIO. In digital video, examples in common use are DVI, HDMI and DisplayPort.
Multichannel serial design increases flexibility with its ability to allocate fewer lanes for slower devices.
PCI Express (standard)
Intel P3608 NVMe flash SSD, PCI-E add-in card
A PCI Express card fits into a slot of its physical size or larger (with ×16 as the largest used), but may not fit into a smaller PCI Express slot; for example, a ×16 card may not fit into a ×4 or ×8 slot. Some slots use open-ended sockets to permit physically longer cards and negotiate the best available electrical and logical connection.
The number of lanes actually connected to a slot may also be fewer than the number supported by the physical slot size. An example is a ×16 slot that runs at ×4, which will accept any ×1, ×2, ×4, ×8 or ×16 card, but provides only four lanes. Its specification may read as "×16 (×4 mode)", while "×size @ ×speed" notation ("×16 @ ×4") is also common. The advantage is that such slots can accommodate a larger range of PCI Express cards without requiring motherboard hardware to support the full transfer rate. Standard mechanical sizes are ×1, ×4, ×8, and ×16. Cards with a differing number of lanes need to use the next larger mechanical size (ie. a ×2 card uses the ×4 size, or a ×12 card uses the ×16 size).
The cards themselves are designed and manufactured in various sizes. For example, solid-state drives (SSDs) that come in the form of PCI Express cards often use HHHL (half height, half length) and FHHL (full height, half length) to describe the physical dimensions of the card.[10][11]
PCI Type
Dimensions (in)
Full-Length PCI Card 107mm (height) × 312mm (long) 4.21in (height) × 12.28in (long)
Half-Length PCI Card 106.68mm (height) × 175.26mm (long) 4.2in (height) × 6.9in (long)
Low-Profile/ Slim PCI Card 64.41mm (height) × 119.91-167.64mm (long) 2.54in (height) × 4.72-6.59in (long)
Pinout
The following table identifies the conductors on each side of the edge connector on a PCI Express card. The solder side of the printed circuit board (PCB) is the A side, and the component side is the B side.[12] PRSNT1# and PRSNT2# pins must be slightly shorter than the rest, to ensure that a hot-plugged card is fully inserted. The WAKE# pin uses full voltage to wake the computer, but must be pulled high from the standby power to indicate that the card is wake capable.[13]
PCI Express connector pinout (×1, ×4, ×8 and ×16 variants)
+12 V PRSNT1# Must connect to farthest PRSNT2# pin
HSOp(8) Reserved Lane 8 transmit data, + and -
+12 V +12 V Main power pins
HSOn(8) Ground
+12 V +12 V
Ground HSIp(8) Lane 8 receive data, + and -
Ground Ground
Ground HSIn(8)
SMCLK TCK SMBus and JTAG port pins
HSOp(9) Ground Lane 9 transmit data, + and -
SMDAT TDI
Ground TDO
+3.3 V TMS
TRST# +3.3 V
HSOp(10) Ground Lane 10 transmit data, + and -
+3.3 V aux +3.3 V Standby power
HSOn(10) Ground
WAKE# PERST# Link reactivation; fundamental reset
Ground HSIp(10) Lane 10 receive data, + and -
Key notch
Ground HSIn(10)
CLKREQ#[14] Ground Clock Request Signal
Ground REFCLK+ Reference clock differential pair
HSOp(0) REFCLK- Lane 0 transmit data, + and -
PRSNT2# HSIn(0)
PCI Express ×1 cards end at pin 18
PWRBRK#[15] HSIn(3)
PRSNT2# HSIn(15)
PRSNT2# Ground
Reserved Ground
Ground Reserved
Ground pin
Zero volt reference
Power pin
Supplies power to the PCIe card
Card-to-host pin
Signal from the card to the motherboard
Host-to-card pin
Signal from the motherboard to the card
Open drain
May be pulled low or sensed by multiple cards
Sense pin
Tied together on card
Not presently used, do not connect
8-pin (left) and 6-pin (right) power connectors used on PCI Express cards
All PCI express cards may consume up to at . The amount of +12 V and total power they may consume depends on the type of card:[16]:35-36[17]
×1 cards are limited to 0.5 A at +12V (6 W) and 10 W combined.
×4 and wider cards are limited to 2.1 A at +12V (25 W) and 25 W combined.
A full-sized ×1 card may draw up to the 25 W limits after initialization and software configuration as a "high power device".
A full-sized ×16 graphics card[13] may draw up to 5.5 A at +12V (66 W) and 75 W combined after initialization and software configuration as a "high power device".
Optional connectors add 75 W (6-pin) or 150 W (8-pin) of +12 V power for up to 300 W total (2×75 W + 1×150 W).
Sense0 pin is connected to ground by the cable or power supply, or float on board if cable is not connected.
There are cards that use two 8-pin connectors, but this has not been standardized yet as of 2018[update], therefore such cards must not carry the official PCI Express logo. This configuration allows 375 W total (1×75 W + 2×150 W) and will likely be standardized by PCI-SIG with the PCI Express 4.0 standard. The 8-pin PCI Express connector could be confused with the EPS12V connector, which is mainly used for powering SMP and multi-core systems.
6-pin power connector (75 W)[18]
8-pin power connector (150 W)[19][20][21]
6 pin power connector pin map
1 +12 V 1 +12 V
2 Not connected (usually +12 V as well) 2 +12 V
4 Sense1 (8-pin connected[a])
4 Ground 5 Ground
5 Sense 6 Sense0 (6-pin or 8-pin connected)
^ When a 6-pin connector is plugged into an 8-pin receptacle the card is notified by a missing Sense1 that it may only use up to 75 W.
PCI Express Mini Card
A WLAN PCI Express Mini Card and its connector
MiniPCI and MiniPCI Express cards in comparison
PCI Express Mini Card (also known as Mini PCI Express, Mini PCIe, Mini PCI-E, mPCIe, and PEM), based on PCI Express, is a replacement for the Mini PCI form factor. It is developed by the PCI-SIG. The host device supports both PCI Express and USB 2.0 connectivity, and each card may use either standard. Most laptop computers built after 2005 use PCI Express for expansion cards; however, as of 2015[update], many vendors are moving toward using the newer M.2 form factor for this purpose.
Due to different dimensions, PCI Express Mini Cards are not physically compatible with standard full-size PCI Express slots; however, passive adapters exist that allow them to be used in full-size slots.[22]
Physical dimensions
Dimensions of PCI Express Mini Cards are 30 × 50.95 mm (width × length) for a Full Mini Card. There is a 52-pin edge connector, consisting of two staggered rows on a 0.8 mm pitch. Each row has eight contacts, a gap equivalent to four contacts, then a further 18 contacts. Boards have a thickness of 1.0 mm, excluding the components. A "Half Mini Card" (sometimes abbreviated as HMC) is also specified, having approximately half the physical length of 26.8 mm.
Electrical interface
PCI Express Mini Card edge connectors provide multiple connections and buses:
PCI Express ×1 (with SMBus)
Wires to diagnostics LEDs for wireless network (i.e., Wi-Fi) status on computer's chassis
SIM card for GSM and WCDMA applications (UIM signals on spec.).
Future extension for another PCIe lane
1.5 V and 3.3 V power
Mini-SATA (mSATA) variant
Despite sharing the Mini PCI Express form factor, an mSATA slot is not necessarily electrically compatible with Mini PCI Express. For this reason, only certain notebooks are compatible with mSATA drives. Most compatible systems are based on Intel's Sandy Bridge processor architecture, using the Huron River platform. Notebooks such as Lenovo's ThinkPad T, W and X series, released in March-April 2011, have support for an mSATA SSD card in their WWAN card slot. The ThinkPad Edge E220s/E420s, and the Lenovo IdeaPad Y460/Y560/Y570/Y580 also support mSATA.[23]
Some notebooks (notably the Asus Eee PC, the Apple MacBook Air, and the Dell mini9 and mini10) use a variant of the PCI Express Mini Card as an SSD. This variant uses the reserved and several non-reserved pins to implement SATA and IDE interface passthrough, keeping only USB, ground lines, and sometimes the core PCIe ×1 bus intact.[24] This makes the "miniPCIe" flash and solid-state drives sold for netbooks largely incompatible with true PCI Express Mini implementations.
Also, the typical Asus miniPCIe SSD is 71 mm long, causing the Dell 51 mm model to often be (incorrectly) referred to as half length. A true 51 mm Mini PCIe SSD was announced in 2009, with two stacked PCB layers that allow for higher storage capacity. The announced design preserves the PCIe interface, making it compatible with the standard mini PCIe slot. No working product has yet been developed.
Intel has numerous desktop boards with the PCIe ×1 Mini-Card slot which typically do not support mSATA SSD. A list of desktop boards that natively support mSATA in the PCIe ×1 Mini-Card slot (typically multiplexed with a SATA port) is provided on the Intel Support site.[25]
PCI Express M.2 (Mini PCIe v2)
The new version of Mini PCI express, M.2 replaces the mSATA standard. Computer bus interfaces provided through the M.2 connector are PCI Express 3.0 (up to four lanes), Serial ATA 3.0, and USB 3.0 (a single logical port for each of the latter two). It is up to the manufacturer of the M.2 host or device to select which interfaces are to be supported, depending on the desired level of host support and device type.
PCI Express External Cabling
PCI Express External Cabling (also known as External PCI Express, Cabled PCI Express, or ePCIe) specifications were released by the PCI-SIG in February 2007.[26][27]
Standard cables and connectors have been defined for ×1, ×4, ×8, and ×16 link widths, with a transfer rate of 250 MB/s per lane. The PCI-SIG also expects the norm will evolve to reach 500 MB/s, as in PCI Express 2.0. An example of the uses of Cabled PCI Express is a metal enclosure, containing a number of PCIe slots and PCIe-to-ePCIe adapter circuitry. This device would not be possible had it not been for the ePCIe spec.
PCI Express OCuLink
OCuLink (standing for "optical-copper link", since Cu is the chemical symbol for Copper) is an extension for the "cable version of PCI Express", acting as a competitor to version 3 of the Thunderbolt interface. Version 1.0 of OCuLink, released in Oct 2015, supports up to PCIe 3.0 ×4 lanes (8 GT/s, 3.9 GB/s) over copper cabling; a fiber optic version may appear in the future.[28][29]
OCuLink in last version will have up to 16 GT/s (8 GB/s total for ×4 lanes),[30] while the maximum bandwidth of a Thunderbolt 3 connector is 5 GB/s.
Several other types of expansion card are derived from PCIe; these include:
Low-height card
ExpressCard: Successor to the PC Card form factor (with ×1 PCIe and USB 2.0; hot-pluggable)
PCI Express ExpressModule: A hot-pluggable modular form factor defined for servers and workstations
XQD card: A PCI Express-based flash card standard by the CompactFlash Association
XMC: Similar to the CMC/PMC form factor (VITA 42.3)
AdvancedTCA: A complement to CompactPCI for larger applications; supports serial based backplane topologies
AMC: A complement to the AdvancedTCA specification; supports processor and I/O modules on ATCA boards (×1, ×2, ×4 or ×8 PCIe).
FeaturePak: A tiny expansion card format (43 × 65 mm) for embedded and small-form-factor applications which implements two ×1 PCIe links on a high-density connector along with USB, I2C, and up to 100 points of I/O
Universal IO: A variant from Super Micro Computer Inc designed for use in low-profile rack-mounted chassis.[31] It has the connector bracket reversed so it cannot fit in a normal PCI Express socket, but it is pin-compatible and may be inserted if the bracket is removed.
Thunderbolt: A variant from Intel that combines DisplayPort and PCIe protocols in a form factor compatible with Mini DisplayPort. Thunderbolt 3.0 also combines USB 3.1 and uses the USB-C form factor as opposed to Mini DisplayPort.
Serial Digital Video Out: Some 9xx series Intel chipsets allow for adding another output for the integrated video into a PCIe slot (mostly dedicated and 16 lanes).
M.2 (formerly known as NGFF)
M-PCIe brings PCIe 3.0 to mobile devices (such as tablets and smartphones), over the M-PHY physical layer.[32][28]
U.2 (formerly known as SFF-8639)
History and revisions
While in early development, PCIe was initially referred to as HSI (for High Speed Interconnect), and underwent a name change to 3GIO (for 3rd Generation I/O) before finally settling on its PCI-SIG name PCI Express. A technical working group named the Arapaho Work Group (AWG) drew up the standard. For initial drafts, the AWG consisted only of Intel engineers; subsequently, the AWG expanded to include industry partners.
Since, PCIe has undergone several large and smaller revisions, improving on performance and other features.
PCI Express link performance[33][34]
rate[i]
Throughput[i]
×16
1.0 2003 8b/10b 2.5 GT/s 250 MB/s 0.50 GB/s 1.0 GB/s 2.0 GB/s 4.0 GB/s
2.0 2007 8b/10b 5.0 GT/s 500 MB/s 1.0 GB/s 2.0 GB/s 4.0 GB/s 8.0 GB/s
3.0 2010 128b/130b 8.0 GT/s 984.6 MB/s 1.97 GB/s 3.94 GB/s 7.88 GB/s 15.75 GB/s
4.0 2017 128b/130b 16.0 GT/s 1969 MB/s 3.94 GB/s 7.88 GB/s 15.75 GB/s 31.51 GB/s
5.0 2019 128b/130b 32.0 GT/s[ii] 3938 MB/s 7.88 GB/s 15.75 GB/s 31.51 GB/s 63.02 GB/s
6.0 (planned) 2021 128b/130b 64.0 GT/s 7877 MB/s 15.75 GB/s 31.51 GB/s 63.02 GB/s 126.03 GB/s
^ a b In each direction (each lane is a dual simplex channel).
^ Initially, 25.0 GT/s was also considered for technical feasibility.
PCI Express 1.0a
In 2003, PCI-SIG introduced PCIe 1.0a, with a per-lane data rate of 250 MB/s and a transfer rate of 2.5 gigatransfers per second (GT/s). Transfer rate is expressed in transfers per second instead of bits per second because the number of transfers includes the overhead bits, which do not provide additional throughput;[35] PCIe 1.x uses an 8b/10b encoding scheme, resulting in a 20% (= 2/10) overhead on the raw channel bandwidth.[36]
PCI Express 1.1
In 2005, PCI-SIG[37] introduced PCIe 1.1. This updated specification includes clarifications and several improvements, but is fully compatible with PCI Express 1.0a. No changes were made to the data rate.
A PCI Express 2.0 expansion card that provides USB 3.0 connectivity.[a]
PCI-SIG announced the availability of the PCI Express Base 2.0 specification on 15 January 2007.[38] The PCIe 2.0 standard doubles the transfer rate compared with PCIe 1.0 to 5 GT/s and the per-lane throughput rises from 250 MB/s to 500 MB/s. Consequently, a 32-lane PCIe connector (×32) can support an aggregate throughput of up to 16 GB/s.
PCIe 2.0 motherboard slots are fully backward compatible with PCIe v1.x cards. PCIe 2.0 cards are also generally backward compatible with PCIe 1.x motherboards, using the available bandwidth of PCI Express 1.1. Overall, graphic cards or motherboards designed for v2.0 will work with the other being v1.1 or v1.0a.
The PCI-SIG also said that PCIe 2.0 features improvements to the point-to-point data transfer protocol and its software architecture.[39]
Intel's first PCIe 2.0 capable chipset was the X38 and boards began to ship from various vendors (Abit, Asus, Gigabyte) as of October 21, 2007.[40] AMD started supporting PCIe 2.0 with its AMD 700 chipset series and nVidia started with the MCP72.[41] All of Intel's prior chipsets, including the Intel P35 chipset, supported PCIe 1.1 or 1.0a.[42]
Like 1.x, PCIe 2.0 uses an 8b/10b encoding scheme, therefore delivering, per-lane, an effective 4 Gbit/s max transfer rate from its 5 GT/s raw data rate.
PCI Express 2.1 (with its specification dated March 4, 2009) supports a large proportion of the management, support, and troubleshooting systems planned for full implementation in PCI Express 3.0. However, the speed is the same as PCI Express 2.0. The increase in power from the slot breaks backward compatibility between PCI Express 2.1 cards and some older motherboards with 1.0/1.0a, but most motherboards with PCI Express 1.1 connectors are provided with a BIOS update by their manufacturers through utilities to support backward compatibility of cards with PCIe 2.1.
PCI Express 3.0 Base specification revision 3.0 was made available in November 2010, after multiple delays. In August 2007, PCI-SIG announced that PCI Express 3.0 would carry a bit rate of 8 gigatransfers per second (GT/s), and that it would be backward compatible with existing PCI Express implementations. At that time, it was also announced that the final specification for PCI Express 3.0 would be delayed until Q2 2010.[43] New features for the PCI Express 3.0 specification include a number of optimizations for enhanced signaling and data integrity, including transmitter and receiver equalization, PLL improvements, clock data recovery, and channel enhancements for currently supported topologies.[44]
Following a six-month technical analysis of the feasibility of scaling the PCI Express interconnect bandwidth, PCI-SIG's analysis found that 8 gigatransfers per second can be manufactured in mainstream silicon process technology, and can be deployed with existing low-cost materials and infrastructure, while maintaining full compatibility (with negligible impact) to the PCI Express protocol stack.
PCI Express 3.0 upgrades the encoding scheme to 128b/130b from the previous 8b/10b encoding, reducing the bandwidth overhead from 20% of PCI Express 2.0 to approximately 1.54% (= 2/130). A desirable balance of 0 and 1 bits in the data stream is achieved by XORing a known binary polynomial as a "scrambler" to the data stream in a feedback topology. Because the scrambling polynomial is known, the data can be recovered by applying the XOR a second time. Both the scrambling and descrambling steps are carried out in hardware. PCI Express 3.0's 8 GT/s bit rate effectively delivers 985 MB/s per lane, nearly doubling the lane bandwidth relative to PCI Express 2.0.[34]
On November 18, 2010, the PCI Special Interest Group officially published the finalized PCI Express 3.0 specification to its members to build devices based on this new version of PCI Express.[45]
In September 2013, PCI Express 3.1 specification was announced to be released in late 2013 or early 2014, consolidating various improvements to the published PCI Express 3.0 specification in three areas: power management, performance and functionality.[28][46] It was released in November 2014.[47]
On November 29, 2011, PCI-SIG preliminarily announced PCI Express 4.0,[48] providing a 16 GT/s bit rate that doubles the bandwidth provided by PCI Express 3.0, while maintaining backward and forward compatibility in both software support and used mechanical interface.[49] PCI Express 4.0 specs will also bring OCuLink-2, an alternative to Thunderbolt connector. OCuLink version 2 will have up to 16 GT/s (8 GB/s total for ×4 lanes),[30] while the maximum bandwidth of a Thunderbolt 3 connector is 5 GB/s. Additionally, active and idle power optimizations are to be investigated.
In August 2016, Synopsys presented a test machine running PCIe 4.0 at the Intel Developer Forum. Their IP has been licensed to several firms planning to present their chips and products at the end of 2016.[50][51]
PCI-SIG officially announced the release of the final PCI Express 4.0 specification on June 8, 2017.[52] The spec includes improvements in flexibility, scalability, and lower-power.
NETINT Technologies introduced the first NVMe SSD based on PCIe 4.0 on July 17, 2018, ahead of Flash Memory Summit 2018[53]
Broadcom announced on 12 September 2018 the first 200 Gbit Ethernet Controller with PCIe 4.0.[54]
AMD announced on 9 January 2019 their upcoming X570 chipset will support PCIe 4.0.[55] AMD planned to enable partial support for older chipsets, but they retracted that promise because of the instability caused by PCIe 4.0.[56][57]
In June 2017, PCI-SIG announced the PCI Express 5.0 preliminary specification.[52] Bandwidth was expected to increase to 32 GT/s, yielding 63 GB/s in each direction in a 16 lane configuration. The draft spec was expected to be standardized in 2019.[] PLDA announced the availability of their XpressRICH5 PCIe 5.0 Controller IP based on draft 0.7 of the PCIe 5.0 specification on the same day.[58][59]
On 10 December 2018, the PCI SIG released version 0.9 of the PCIe 5.0 specification to its members,[60] and on 17 January 2019, PCI SIG announced the version 0.9 had been ratified, with version 1.0 targeted for release in the first quarter of 2019.[61]
On 29 May 2019, PCI-SIG officially announced the release of the final PCI-Express 5.0 specification.[62][clarification needed]
On June 18 2019, PCI-SIG announced the development of PCI Express 6.0 specification that will double the data rate to 64 GT/s, yielding 128 GB/s in each direction in a 16 lane configuration, with a target release date of 2021.[63] The new standard uses 4-level pulse-amplitude modulation (PAM-4) with a low-latency forward error correction (FEC) in place of non-return-to-zero (NRZ) modulation.[64]
Extensions and future directions
Some vendors offer PCIe over fiber products,[65][66][67] but these generally find use only in specific cases where transparent PCIe bridging is preferable to using a more mainstream standard (such as InfiniBand or Ethernet) that may require additional software to support it; current implementations focus on distance rather than raw bandwidth and typically do not implement a full ×16 link.
Thunderbolt was co-developed by Intel and Apple as a general-purpose high speed interface combining a ×4 PCIe link with DisplayPort and was originally intended to be an all-fiber interface, but due to early difficulties in creating a consumer-friendly fiber interconnect, nearly all implementations are copper systems. A notable exception, the Sony VAIO Z VPC-Z2, uses a nonstandard USB port with an optical component to connect to an outboard PCIe display adapter. Apple has been the primary driver of Thunderbolt adoption through 2011, though several other vendors[68] have announced new products and systems featuring Thunderbolt. Thunderbolt 3 will become part of USB 4 standard.
Mobile PCIe specification (abbreviated to M-PCIe) allows PCI Express architecture to operate over the MIPI Alliance's M-PHY physical layer technology. Building on top of already existing widespread adoption of M-PHY and its low-power design, Mobile PCIe allows PCI Express to be used in tablets and smartphones.[69]
Draft process
There are 5 primary releases/checkpoints in a PCI-SIG specification:[70]
Draft 0.3 (Concept): this release may have few details, but outlines the general approach and goals.
Draft 0.5 (First draft): this release has a complete set of architectural requirements and must fully address the goals set out in the 0.3 draft.
Draft 0.7 (Complete draft): this release must have a complete set of functional requirements and methods defined, and no new functionality may be added to the specification after this release. Before the release of this draft, electrical specifications must have been validated via test silicon.
Draft 0.9 (Final draft): this release allows PCI-SIG member companies to perform an internal review for intellectual property, and no functional changes are permitted after this draft.
1.0 (Final release): this is the final and definitive specification, and any changes or enhancements will be through Errata documentation and Engineering Change Notices (ECNs) respectively.
Historically, the earliest adopters of a new PCIe specification generally begin designing with the Draft 0.5 as they can confidently build up their application logic around the new bandwidth definition and often even start developing for any new protocol features. At the Draft 0.5 stage, however, there is still a strong likelihood of changes in the actual PCIe protocol layer implementation, so designers responsible for developing these blocks internally may be more hesitant to begin work than those using interface IP from external sources.
Hardware protocol summary
The PCIe link is built around dedicated unidirectional couples of serial (1-bit), point-to-point connections known as lanes. This is in sharp contrast to the earlier PCI connection, which is a bus-based system where all the devices share the same bidirectional, 32-bit or 64-bit parallel bus.
PCI Express is a layered protocol, consisting of a transaction layer, a data link layer, and a physical layer. The Data Link Layer is subdivided to include a media access control (MAC) sublayer. The Physical Layer is subdivided into logical and electrical sublayers. The Physical logical-sublayer contains a physical coding sublayer (PCS). The terms are borrowed from the IEEE 802 networking protocol model.
Connector pins and lengths
×1 2×18 = 36[71] 2×7 = 14 25 mm 7.65 mm
×4 2×32 = 64 2×21 = 42 39 mm 21.65 mm
×16 2×82 = 164 2×71 = 142 89 mm 71.65 mm
An open-end PCI Express ×1 connector, allowing longer cards capable of using more lanes to be plugged while operating at ×1 speeds
The PCIe Physical Layer (PHY, PCIEPHY, PCI Express PHY, or PCIe PHY) specification is divided into two sub-layers, corresponding to electrical and logical specifications. The logical sublayer is sometimes further divided into a MAC sublayer and a PCS, although this division is not formally part of the PCIe specification. A specification published by Intel, the PHY Interface for PCI Express (PIPE),[72] defines the MAC/PCS functional partitioning and the interface between these two sub-layers. The PIPE specification also identifies the physical media attachment (PMA) layer, which includes the serializer/deserializer (SerDes) and other analog circuitry; however, since SerDes implementations vary greatly among ASIC vendors, PIPE does not specify an interface between the PCS and PMA.
At the electrical level, each lane consists of two unidirectional differential pairs operating at 2.5, 5, 8 or 16 Gbit/s, depending on the negotiated capabilities. Transmit and receive are separate differential pairs, for a total of four data wires per lane.
A connection between any two PCIe devices is known as a link, and is built up from a collection of one or more lanes. All devices must minimally support single-lane (×1) link. Devices may optionally support wider links composed of 2, 4, 8, 12, 16, or 32 lanes. This allows for very good compatibility in two ways:
A PCIe card physically fits (and works correctly) in any slot that is at least as large as it is (e.g., an ×1 sized card will work in any sized slot);
A slot of a large physical size (e.g., ×16) can be wired electrically with fewer lanes (e.g., ×1, ×4, ×8, or ×12) as long as it provides the ground connections required by the larger physical slot size.
In both cases, PCIe negotiates the highest mutually supported number of lanes. Many graphics cards, motherboards and BIOS versions are verified to support ×1, ×4, ×8 and ×16 connectivity on the same connection.
Even though the two would be signal-compatible, it is not usually possible to place a physically larger PCIe card (e.g., a ×16 sized card) into a smaller slot – though if the PCIe slots are altered or a riser is used most motherboards will allow this. The width of a PCIe connector is 8.8 mm, while the height is 11.25 mm, and the length is variable. The fixed section of the connector is 11.65 mm in length and contains two rows of 11 (22 pins total), while the length of the other section is variable depending on the number of lanes. The pins are spaced at 1 mm intervals, and the thickness of the card going into the connector is 1.6 mm.[73][74]
PCIe sends all control messages, including interrupts, over the same links used for data. The serial protocol can never be blocked, so latency is still comparable to conventional PCI, which has dedicated interrupt lines.
Data transmitted on multiple-lane links is interleaved, meaning that each successive byte is sent down successive lanes. The PCIe specification refers to this interleaving as data striping. While requiring significant hardware complexity to synchronize (or deskew) the incoming striped data, striping can significantly reduce the latency of the nth byte on a link. While the lanes are not tightly synchronized, there is a limit to the lane to lane skew of 20/8/6 ns for 2.5/5/8 GT/s so the hardware buffers can re-align the striped data.[75] Due to padding requirements, striping may not necessarily reduce the latency of small data packets on a link.
As with other high data rate serial transmission protocols, the clock is embedded in the signal. At the physical level, PCI Express 2.0 utilizes the 8b/10b encoding scheme[34] to ensure that strings of consecutive identical digits (zeros or ones) are limited in length. This coding was used to prevent the receiver from losing track of where the bit edges are. In this coding scheme every eight (uncoded) payload bits of data are replaced with 10 (encoded) bits of transmit data, causing a 20% overhead in the electrical bandwidth. To improve the available bandwidth, PCI Express version 3.0 instead uses 128b/130b encoding with scrambling. 128b/130b encoding relies on the scrambling to limit the run length of identical-digit strings in data streams and ensure the receiver stays synchronised to the transmitter. It also reduces electromagnetic interference (EMI) by preventing repeating data patterns in the transmitted data stream.
Data link layer
The data link layer performs three vital services for the PCIe express link:
sequence the transaction layer packets (TLPs) that are generated by the transaction layer,
ensure reliable delivery of TLPs between two endpoints via an acknowledgement protocol (ACK and NAK signaling) that explicitly requires replay of unacknowledged/bad TLPs,
initialize and manage flow control credits
On the transmit side, the data link layer generates an incrementing sequence number for each outgoing TLP. It serves as a unique identification tag for each transmitted TLP, and is inserted into the header of the outgoing TLP. A 32-bit cyclic redundancy check code (known in this context as Link CRC or LCRC) is also appended to the end of each outgoing TLP.
On the receive side, the received TLP's LCRC and sequence number are both validated in the link layer. If either the LCRC check fails (indicating a data error), or the sequence-number is out of range (non-consecutive from the last valid received TLP), then the bad TLP, as well as any TLPs received after the bad TLP, are considered invalid and discarded. The receiver sends a negative acknowledgement message (NAK) with the sequence-number of the invalid TLP, requesting re-transmission of all TLPs forward of that sequence-number. If the received TLP passes the LCRC check and has the correct sequence number, it is treated as valid. The link receiver increments the sequence-number (which tracks the last received good TLP), and forwards the valid TLP to the receiver's transaction layer. An ACK message is sent to remote transmitter, indicating the TLP was successfully received (and by extension, all TLPs with past sequence-numbers.)
If the transmitter receives a NAK message, or no acknowledgement (NAK or ACK) is received until a timeout period expires, the transmitter must retransmit all TLPs that lack a positive acknowledgement (ACK). Barring a persistent malfunction of the device or transmission medium, the link-layer presents a reliable connection to the transaction layer, since the transmission protocol ensures delivery of TLPs over an unreliable medium.
In addition to sending and receiving TLPs generated by the transaction layer, the data-link layer also generates and consumes DLLPs, data link layer packets. ACK and NAK signals are communicated via DLLPs, as are some power management messages and flow control credit information (on behalf of the transaction layer).
In practice, the number of in-flight, unacknowledged TLPs on the link is limited by two factors: the size of the transmitter's replay buffer (which must store a copy of all transmitted TLPs until the remote receiver ACKs them), and the flow control credits issued by the receiver to a transmitter. PCI Express requires all receivers to issue a minimum number of credits, to guarantee a link allows sending PCIConfig TLPs and message TLPs.
Transaction layer
PCI Express implements split transactions (transactions with request and response separated by time), allowing the link to carry other traffic while the target device gathers data for the response.
PCI Express uses credit-based flow control. In this scheme, a device advertises an initial amount of credit for each received buffer in its transaction layer. The device at the opposite end of the link, when sending transactions to this device, counts the number of credits each TLP consumes from its account. The sending device may only transmit a TLP when doing so does not make its consumed credit count exceed its credit limit. When the receiving device finishes processing the TLP from its buffer, it signals a return of credits to the sending device, which increases the credit limit by the restored amount. The credit counters are modular counters, and the comparison of consumed credits to credit limit requires modular arithmetic. The advantage of this scheme (compared to other methods such as wait states or handshake-based transfer protocols) is that the latency of credit return does not affect performance, provided that the credit limit is not encountered. This assumption is generally met if each device is designed with adequate buffer sizes.
PCIe 1.x is often quoted to support a data rate of 250 MB/s in each direction, per lane. This figure is a calculation from the physical signaling rate (2.5 gigabaud) divided by the encoding overhead (10 bits per byte). This means a sixteen lane (×16) PCIe card would then be theoretically capable of 16×250 MB/s = 4 GB/s in each direction. While this is correct in terms of data bytes, more meaningful calculations are based on the usable data payload rate, which depends on the profile of the traffic, which is a function of the high-level (software) application and intermediate protocol levels.
Like other high data rate serial interconnect systems, PCIe has a protocol and processing overhead due to the additional transfer robustness (CRC and acknowledgements). Long continuous unidirectional transfers (such as those typical in high-performance storage controllers) can approach >95% of PCIe's raw (lane) data rate. These transfers also benefit the most from increased number of lanes (×2, ×4, etc.) But in more typical applications (such as a USB or Ethernet controller), the traffic profile is characterized as short data packets with frequent enforced acknowledgements.[76] This type of traffic reduces the efficiency of the link, due to overhead from packet parsing and forced interrupts (either in the device's host interface or the PC's CPU). Being a protocol for devices connected to the same printed circuit board, it does not require the same tolerance for transmission errors as a protocol for communication over longer distances, and thus, this loss of efficiency is not particular to PCIe.
Asus Nvidia GeForce GTX 650 Ti, a PCI Express 3.0 ×16 graphics card
The NVIDIA GeForce GTX 1070, a PCI Express 3.0 x16 Graphics card.
Intel 82574L Gigabit Ethernet NIC, a PCI Express ×1 card
A Marvell-based SATA 3.0 controller, as a PCI Express ×1 card
PCI Express operates in consumer, server, and industrial applications, as a motherboard-level interconnect (to link motherboard-mounted peripherals), a passive backplane interconnect and as an expansion card interface for add-in boards.
In virtually all modern (as of 2012[update]) PCs, from consumer laptops and desktops to enterprise data servers, the PCIe bus serves as the primary motherboard-level interconnect, connecting the host system-processor with both integrated-peripherals (surface-mounted ICs) and add-on peripherals (expansion cards). In most of these systems, the PCIe bus co-exists with one or more legacy PCI buses, for backward compatibility with the large body of legacy PCI peripherals.
As of 2013[update] PCI Express has replaced AGP as the default interface for graphics cards on new systems. Almost all models of graphics cards released since 2010 by AMD (ATI) and Nvidia use PCI Express. Nvidia uses the high-bandwidth data transfer of PCIe for its Scalable Link Interface (SLI) technology, which allows multiple graphics cards of the same chipset and model number to run in tandem, allowing increased performance. AMD has also developed a multi-GPU system based on PCIe called CrossFire. AMD, Nvidia, and Intel have released motherboard chipsets that support as many as four PCIe ×16 slots, allowing tri-GPU and quad-GPU card configurations.
Note that there are special power cables called PCI-e power cables which are required for high-end graphics cards[77].
External GPUs
Theoretically, external PCIe could give a notebook the graphics power of a desktop, by connecting a notebook with any PCIe desktop video card (enclosed in its own external housing, with a power supply and cooling); this is possible with an ExpressCard interface or a Thunderbolt interface. The ExpressCard interface provides bit rates of 5 Gbit/s (0.5 GB/s throughput), whereas the Thunderbolt interface provides bit rates of up to 40 Gbit/s (5 GB/s throughput).
In 2006, Nvidia developed the Quadro Plex external PCIe family of GPUs that can be used for advanced graphic applications for the professional market.[78] These video cards require a PCI Express ×8 or ×16 slot for the host-side card which connects to the Plex via a VHDCI carrying eight PCIe lanes.[79]
In 2008, AMD announced the ATI XGP technology, based on a proprietary cabling system that is compatible with PCIe ×8 signal transmissions.[80] This connector is available on the Fujitsu Amilo and the Acer Ferrari One notebooks. Fujitsu launched their AMILO GraphicBooster enclosure for XGP soon thereafter.[81] Around 2010 Acer launched the Dynavivid graphics dock for XGP.[82]
In 2010 external card hubs were introduced that can connect to a laptop or desktop through a PCI ExpressCard slot. These hubs can accept full-sized graphics cards. Examples include MSI GUS,[83] Village Instrument's ViDock,[84] the Asus XG Station, Bplus PE4H V3.2 adapter,[85] as well as more improvised DIY devices.[86] However such solutions are limited by the size (often only ×1) and version of the available PCIe slot on a laptop.
Intel Thunderbolt interface has given opportunity to new and faster products to connect with a PCIe card externally. Magma has released the ExpressBox 3T, which can hold up to three PCIe cards (two at ×8 and one at ×4).[87] MSI also released the Thunderbolt GUS II, a PCIe chassis dedicated for video cards.[88] Other products such as the Sonnet's Echo Express[89] and mLogic's mLink are Thunderbolt PCIe chassis in a smaller form factor.[90] However, all these products require a computer with a Thunderbolt port (i.e., Thunderbolt devices), such as Apple's MacBook Pro models released in late 2013.
In 2017, more fully featured external card hubs were introduced, such as the Razer Core, which has a full-length PCIe ×16 interface.[91]
An OCZ RevoDrive SSD, a full-height ×4 PCI Express card
PCI Express protocol can be used as data interface to flash memory devices, such as memory cards and solid-state drives (SSDs).
XQD card is a memory card format utilizing PCI Express, developed by the CompactFlash Association, with transfer rates of up to 500 MB/s.[92]
Many high-performance, enterprise-class SSDs are designed as PCI Express RAID controller cards with flash memory chips placed directly on the circuit board, utilizing proprietary interfaces and custom drivers to communicate with the operating system; this allows much higher transfer rates (over 1 GB/s) and IOPS (over one million I/O operations per second) when compared to Serial ATA or SAS drives.[93][94] For example, in 2011 OCZ and Marvell co-developed a native PCI Express solid-state drive controller for a PCI Express 3.0 ×16 slot with maximum capacity of 12 TB and a performance of to 7.2 GB/s sequential transfers and up to 2.52 million IOPS in random transfers.[95]
SATA Express is an interface for connecting SSDs, by providing multiple PCI Express lanes as a pure PCI Express connection to the attached storage device.[96]M.2 is a specification for internally mounted computer expansion cards and associated connectors, which also uses multiple PCI Express lanes.[97]
PCI Express storage devices can implement both AHCI logical interface for backward compatibility, and NVM Express logical interface for much faster I/O operations provided by utilizing internal parallelism offered by such devices. Enterprise-class SSDs can also implement SCSI over PCI Express.[98]
Cluster interconnect
Certain data-center applications (such as large computer clusters) require the use of fiber-optic interconnects due to the distance limitations inherent in copper cabling. Typically, a network-oriented standard such as Ethernet or Fibre Channel suffices for these applications, but in some cases the overhead introduced by routable protocols is undesirable and a lower-level interconnect, such as InfiniBand, RapidIO, or NUMAlink is needed. Local-bus standards such as PCIe and HyperTransport can in principle be used for this purpose,[99] but as of 2015[update] solutions are only available from niche vendors such as Dolphin ICS.
Competing protocols
Other communications standards based on high bandwidth serial architectures include InfiniBand, RapidIO, HyperTransport, Intel QuickPath Interconnect, and the Mobile Industry Processor Interface (MIPI). The differences are based on the trade-offs between flexibility and extensibility vs latency and overhead. For example, making the system hot-pluggable, as with Infiniband but not PCI Express, requires that software track network topology changes.
Another example is making the packets shorter to decrease latency (as is required if a bus must operate as a memory interface). Smaller packets mean packet headers consume a higher percentage of the packet, thus decreasing the effective bandwidth. Examples of bus protocols designed for this purpose are RapidIO and HyperTransport.
PCI Express falls somewhere in the middle, targeted by design as a system interconnect (local bus) rather than a device interconnect or routed network protocol. Additionally, its design goal of software transparency constrains the protocol and raises its latency somewhat.
Delays in PCIe 4.0 implementations led to the Gen-Z consortium, the CCIX[100] effort and an open Coherent Accelerator Processor Interface (CAPI) all being announced by the end of 2016.[101]
In March 2019, Intel presented Compute Express Link (CXL),[102] a new interconnect bus, based on the PCI Express 5.0 physical layer infrastructure.
Integrators List
Integrators List is the Compliance Program power by PCI-SIG, This list includes all products that have successfully completed the rigorous testing procedures of the Compliance Workshop. Inclusion on the list is only available to PCI-SIG member companies and cannot be used for individual marketing programs. The list include Switches/Bridges, NIC, SSD etc. However, many companies do refer to the list when making company-to-company purchases.[103]
Electronics portal
Active State Power Management (ASPM)
Conventional PCI
PCI configuration space
PCI/104-Express
PCIe/104
Root complex
Serial Digital Video Out (SDVO)
List of device bit rates § Main buses
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^ Evan Koblentz (February 3, 2017). "New PCI Express 4.0 delay may empower next-gen alternatives". Tech Republic. Archived from the original on April 1, 2017. Retrieved 2017.
^ Compute Express Link (CXL) site
^ "Integrators List | PCI-SIG". pcisig.com. Retrieved .
Budruk, Ravi; Anderson, Don; Shanley, Tom (2003), Winkles, Joseph 'Joe' (ed.), PCI Express System Architecture, Mind share PC system architecture, Addison-Wesley, ISBN 978-0-321-15630-3 1120 pp.
Solari, Edward; Congdon, Brad (2003), Complete PCI Express Reference: Design Implications for Hardware and Software Developers, Intel, ISBN 978-0-9717861-9-6 , 1056 pp.
Wilen, Adam; Schade, Justin P; Thornburg, Ron (Apr 2003), Introduction to PCI Express: A Hardware and Software Developer's Guide, Intel, ISBN 978-0-9702846-9-3 , 325 pp.
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3rdchair was established for young adults to have a place to come when life becomes overwhelming, regardless of their financial situation. Many of our young adults and families that come here lack resources and/or insurance to cover mental health counseling sessions. We find that very sad, and that the very reason we set up 3rdchair as a 501(c)3 non profit so others can give to help others. That is what the world is truly about at the end of the day: helping others.
We have set up separate funds established to help cover the cost of the counseling session. Your donation will go directly to helping a young adult who is struggling, and the funds will only be used to cover if we see a client, never to cover our fixed costs. Nothing else. You can help fund our efforts by making a tax-deductible contribution.
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Vindy.com
Blitz Live
Blitz Scoreboard
AP Podcasts
Brady White Antonio Gibson Kedarian Jones Patrick Taylor Jr. Mike Norvell Damonte Coxie Kenneth Gainwell Jordan Cronkrite Charlie Strong Kelley Joiner David Small Sports College football Football College sports
South Florida The American Memphis Florida
White throws 2 TD passes, No. 18 Memphis blasts USF 49-10
By FRED GOODALL - Nov. 23, 2019 09:02 PM EST
Memphis wide receiver Antonio Gibson (14) gets between South Florida defensive back Devin Studstill (8) and linebacker Andrew Mims (59) to score during the second half of an NCAA college football game Saturday, Nov. 23, 2019, in Tampa, Fla. (AP Photo/Chris O'Meara)
TAMPA, Fla. (AP) — One more win and No. 18 Memphis will get another crack at playing for the American Athletic Conference championship.
The Tigers shrugged off a slow start to beat South Florida 49-10 Saturday and move a step closer to another AAC West division crown and a third consecutive berth in the league title game.
Memphis (10-1, 6-1), which has won five straight since their only loss at Temple, retained a share of first place with Navy and will win the West with a home win over No. 17 Cincinnati next week.
"I have yet to use the word championship at all this year, not since January," coach Mike Norvell said. "I got to say it in that locker room because we put ourselves in a position now if we can go to take care of our business next week, which is going to be an unbelievable challenge.''
Brady White threw for 222 yards and two touchdowns, and the Tigers shrugged off two early turnovers to score 42 consecutive points to finish the blowout before an announced crowd of 25,136 that included a gray cat that ran onto the field after Antonio Gibson scored on an 18-yard run to make it 35-10 with just under seven minutes left in the third quarter.
The ensuing kickoff was delayed less than a minute while the cat darted around, searching for an escape route. It finally took off through an open area behind the USF bench.
White was intercepted twice in the first half when USF (4-7, 2-5) led 10-7. The graduate transfer settled in and took control of the game with help from a bevy of playmakers.
Memphis rushed for 325 yards, with Patrick Taylor gaining 95 on 17 attempts and scoring on runs of 3, 5 and 10 yards. Leading rusher Kenneth Gainwell averaged 9 yards a carry and finished with 128, with most of his production coming while the Tigers were building a 28-10 halftime lead.
White completed 18 of 22 passes, including second-quarter TDs of 50 yards to Kedarian Jones and 23 yards to Damonte Coxie. He only threw once after halftime, leaving the game late in the third quarter after Gibson and Taylor ran for scores that increased the lead to 42-10.
"Obviously, we all aspire to want to be able to lift a trophy, but you've got to put yourself in that position," Norvell said. "These guys have done that, but we have one more huge step we to have to take, and it's going to be an unbelievable challenge against a great opponent.''
USF, playing without injured running back Jordan Cronkrite, sputtered offensively after rushing for 67 yards on its first drive to take a 7-0 lead. Dave Small scored on a 1-yard run. Kelley Joiner led the Bulls with 115 yards rushing on 13 attempts.
With the loss, USF's streak of four consecutive bowl appearances comes to an end.
"You got to give their team credit. We didn't play well," USF coach Charlie Strong said. "When you go out there and we play a good team like Memphis, we knew that all three phases had to play together, just knowing who they are, what they've done and how they've played the whole season.''
Memphis: The offense outgained USF 560 yards to 170, including a 325-126 edge on the ground. The defense was dominating, too, after yielding a 75-yard TD drive to begin the game. USF managed just 44 yards the rest of the first half, with 22 of that coming on the last play. The Tigers cruised after minimizing the damage after White interceptions, holding the Bulls to three points off the turnovers.
South Florida: The Bulls have lost three straight after playing their way into a position to become bowl eligible following a 1-3 start. They fell to 11-27 against teams ranked in the Top 25, including 0-6 under Strong, who is 21-15 in three seasons at USF.
The Tigers are 18th in the latest CFP rankings. Saturday's victory leaves them in a position to overtake Cincinnati (No. 17 CFP) as the highest rated Group of Five team if they can beat the Bearcats next week. Of course, that would also ensure a rematch between the teams in the AAC championship game the following week. Memphis remained tied with Navy for first in the AAC West. The Tigers hold the tiebreaker because they beat the Midshipmen 35-23 on Sept. 26.
Memphis: Host No. 17 Cincinnati next Friday.
South Florida: Close the season at UCF on Friday night.
More AP college football: https://apnews.com/Collegefootball and https://twitter.com/AP_Top25

redpajama_set_name: RedPajamaCommonCrawl


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James Beard Foundation Will Not Name Winners for 2020/2021
By PDX Food Dude Last Update August 20, 2020 Leave a Comment
The James Beard Foundation has announced the 2020/2021 event will celebrate previously announced honorees and nominees.
This is after the foundation had already released its list of 2020 semi-finalists.
James Beard. Photo by Dan Wynn. Courtesy JamesBeard.org
At first, the foundation announced the award finalists and scheduled the announcement of winners to May, coinciding with the 30th anniversary of the awards. When the pandemic prevented an in-person event, it was changed to a virtual ceremony in Chicago for May 4th, which was then replaced with an online program to be held in late September. The list of semi-finalists from Oregon included Gado Gado, Eem for Best New Restaurant, Kim Boyce of Bakeshop for Outstanding Baker, Expatriate for Outstanding Bar Program, Gabe Rucker of Le Pigeon/Cannard for Outstanding Chef and Outstanding Wine Program, Pete Cho of Han Oak, Gregory Gourdet of Departure, Kristen Murrary of Måurice, and Katy Millard of Coquine for Best Chef NW.
Foundation to Also Begin Year-Long Initiative to Audit and Overhaul Awards Processes with Intent to Remove Any Systemic Bias.
NEW YORK, NY (August 20, 2020) – Today the James Beard Foundation announced that its annual Awards program will not present winners in the remaining categories at the upcoming ceremony on Friday, September 25, an unprecedented decision in the Awards' 30-year history. The choice comes as restaurants continue to suffer the grave negative effects of COVID-19, and as substantial and sustained upheaval in the community has created an environment in which the Foundation believes the assignment of Awards will do little to further the industry in its current uphill battle. The Awards' usual positive impact on restaurants and chefs' businesses will likely not be fully realized due to the current state of the industry, with many restaurants closed permanently or temporarily or operating at minimal capacity. These factors helped to inform the decision not to assign winners during a time of such turmoil.
The resulting ceremony, which will be broadcast live via Twitter from the host city of Chicago, will instead celebrate previously announced honorees in categories such as America's Classics, Lifetime Achievement, Humanitarian of the Year, Design Icon, and Leadership Awards. The broadcast will also shine a spotlight on many of the nominees and be a night of storytelling surrounding the historic challenges this community faces and how we can work together to rebuild a stronger and more equitable restaurant industry.
The decision comes after serious deliberation and consultation with members of the industry, Award committees, JBF staff, and partners. "We did not come to this decision lightly," said James Beard Foundation CEO Clare Reichenbach. "The uncertainty of this time for our industry is already a hard reality and considering anyone to have won or lost within the current tumultuous hospitality ecosystem does not in fact feel like the right thing to do. In short, an honor which we know is held in high regard, at the moment, feels minor when compared to the dire situation we are in. As we strive to provide an Awards program with the highest ethical standards, one that is fair, equitable, and reflective of the industry which we serve, we know that the right move is to step back and take stock of the nominees and honorees achievements. We hope to focus our collective energy on helping our community get through this crisis and on addressing the inequities in the industry going forward. We look forward to bringing the Awards back when the industry is once again ready for them."
The Foundation recognizes the leadership role that it plays in the restaurant industry through the James Beard Awards and other programs. Thus, it is conducting a comprehensive internal and external review to address any bias and align the Awards with the Foundation's mission of promoting sustainability, equity, and diversity in the restaurant industry. By definition, "honoring excellence" is an important act that requires care, judgment and openness. The Foundation is taking stock of how the Awards are administered, communicated, and presented to assure the Awards are open to all and that these judgments are made in a manner that promotes and preserves the Foundation's mission without bias.
The Foundation has also made the decision to forgo its traditional Awards presentations in 2021. The Awards recognize work done during the previous calendar year, so any intent to hold a ceremony in 2021 based on 2020 work would be unfair and misguided, taking into account the unprecedented hardships which restau rants and potential nominees faced this year. Instead, the 2021 ceremony will be a celebration of the independent restaurant community who have shown leadership during this crisis and honoring those who have made a significant impact on the industry and in their communities. This celebration will be held in Chicago and broadcast nationwide in May 2021. The Foundation will take this time to continue the analysis of Awards-related programs with the goal of a transparent and equitable process in 2022 and beyond.
You can read the entire press release here.
Category: Portland Food and Restaurant News and Discussion.
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I was glad that I came down here for a second morning in a row. I would not have been able to get this shot the morning before due to people being in the picture. Plus the water was calmer and the sun wasn't partially blocked by clouds.


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La Guerra de la Lingüística es un término coloquial que se emplea en discusiones prolongadas dentro la gramática generativa estadounidense. Se trata de un término proveniente de una disputa entre Noam Chomsky y algunos de sus primeros estudiantes y compañeros de trabajo, la cual tuvo lugar especialmente en los años sesenta y los setenta.

Lingüistas como Paul Postal, "Haj" Ross, George Lakoff y James McCawley la denominaron "Los Cuatro Jinetes del Apocalipsis" y —propusieron una teoría alternativa a la gramática generativa, que básicamente tiró por los suelos la teoría de Chomsky al centrarse en la semántica lingüística antes que en la gramática como la base del concepto de Chomsky a cerca de la estructura profunda. Mientras que Chomsky y otros "generative grammarians" discutieron que el significado provenía del orden subyacente de las palabras que eran usadas. La semántica generativa menciona el significado de las palabras dando lugar a su orden.
Finalmente, la gramática generativa produjo un paradigma alternativo y lingüístico conocido como la lingüística cognitiva, que intenta correlacionar el entendimiento del lenguaje con función biológica de estructuras neutrales y específicas. Mientras que la narrativa semántica se basa en la premisa de que la mente tiene un módulo único e independiente para el desarrollo del lenguaje, los lingüistas cognitivos niegan esto. Sin embargo, aseguran que el proceso de lingüística está fundado por profundas estructuras conceptuales y aún más importante es que las habilidades cognitivas que se usan para procesar está información son parecidas a aquellas que se emplean en otras tareas no lingüísticas. La mayor parte de este trabajo ha sido publicado a día de hoy bajo el nombre neurolingüística.

Gramática Generativa
La gramática generativa trata de predecir mediante una serie de reglas la combinación de palabras que forman una frase.
Hay diferentes tipos de gramática generativa, entre ellos la gramática generativa transformacional desarrollada por Noam Chomsky a mitad de los años 50. Sin embargo los lingüistas siguen en desacuerdo respecto al tipo de gramática generativa que podría ser usada como mejor modelo para la descripción del lenguaje natural.
Este término no solo distingue las estructuras gramaticales de un idioma mediante las secuencias de palabras del mismo. Además, proporcionan una descripción estructural y un análisis sintáctico de cada estructura gramatical.

Noam Chomsky es considerado el padre de la lingüística moderna - también llamada analítica lingüística. En 2008 cumplió 80 años y fue emérito de lingüística en el Instituto Tecnológico de Massachusetts. Además combinó su trabajo con sus intereses en filosofía, política y ética aparte de añadir en su criterio analístico las disciplinas de psicología, antropología y neurociencia.

George Lakoff es descrito como alguien que cree en el pensamiento no-metafísico pero únicamente cuando las personas describen realidades físicas auténticas. Además George Lakoff abarcó la conexión entre razón y emoción. De esta forma observó que sin la emoción una persona no puede motivarse puesto que sin la emoción "no podemos hacer nada" ya que no sabremos lo que estamos buscando. Los biólogos interpretan las emociones como algo químico que puede producir emociones que podrían llegar a ser contraproductivas. George Lakoff demostró que la razón se encuentra la mayor parte de las veces por debajo de la propia consciencia y que el proceso de razonamiento es más complejo que lo vivido en el pasado.
Él afirma que las emociones varían intensamente y por ello las personas se encuentran desprovistas de auto-control. Él también tiene en cuenta el rol emotivo que se opone a la política retórica. Varias personas han criticado su trabajo entre ellos el ilustre profesor de Harvard.

Libro
La Guerra de la Lingüística es también el título de un libro escrito en 1993 por Randy Allen Harris sobre este tema (ISBN 978-0-19-509834-1).
Trata el tema de la polémica involucrando a Chomsky y a otros personajes importantes (George Lakoff, Steve Pinker, etc..) y también destacando como ciertas teorías han evolucionado con características importantes e influenciando teorías lingüísticas actuales.

Referencias

Enlaces externos
 http://www.fsmitha.com/h2/ch37cog.htm
 http://www.britannica.com/topic/generative-grammar
 http://www.translationdirectory.com/articles/article1796.php

Gramática generativa
Lingüística generativa
Libros de 1995
Noam Chomsky
Rivalidad ideológica
Historia de la lingüística

redpajama_set_name: RedPajamaWikipedia


Executions, forced and arbitrary detentions, beatings, whipping, incarceration and hard labor — This is a common face of drug policy in many Asian nations, and one that is looking ever more archaic.
Half a million drug users are held annually in compulsory detention centers in China and Southeast Asia, according to estimates from the United Nations Office on Drugs and Crime (UNODC). Arduous physical exercises and military drills are often routine there, as is violence – former detainees described shocks with electric batons and whipping with electric wires to Human Rights Watch.
Roughly 50 to 70 percent of prisoners in Indonesia, Malaysia, Myanmar, the Philippines, and Thailand are in jail for drug-related crimes. In extreme cases, prisoners pay with their lives. Indonesia is currently preparing executions for drug trafficking.
The harsh, punitive approach to drug use in Asia stands in stark contrast with the health approach in many Western countries, where programs for "harm reduction" of drug use– such as access to clean needles and methadone substitution treatment– are the norm.
Since Portugal successfully decriminalized drugs in 2001, whereby getting caught with drugs may result in a small fine and a referral to treatment, other countries have followed suit.
This dichotomy of approaches was evident at the United Nations General Assembly special session on drugs (UNGASS) last month. While Indonesia defended the use of the death penalty amid jeers, Canada and Mexico declared they would go their own way to legalize cannabis.
A public letter to the UN urging reform was signed by 1,000 prominent global leaders and activists, including many former world leaders, as well as Hillary Clinton, Bernie Sanders, and Richard Branson. Leading global public health bodies also urged reform in a report, arguing prevailing policies have had "serious detrimental effects" on health and human rights.
A "drug-free world" was the 2015 goal of the Association of Southeast Asian Nations (ASEAN), a hopeless irony given the region's flourishing drug trade. Between 2006 and 2013, opium poppy cultivation in the region's "Golden Triangle" tripled, according to UNODC. Methamphetamine seizures in the region almost quadrupled from 2008 to 2013, to about 42 tons.
Governments have battled the rising trade by taking a hard stance on drugs, often directed at drug users, with police raids, forced urine testing and, in 11 countries, drug detention centers.
Drug users "face very serious human rights abuses" in these centers, Human Rights Watch associate director of health and human rights Diederik Lohman said, adding these centers violated international and often national law.
"Asia remains strongly invested in traditional law enforcement and justice approaches," said Jeremy Douglas, UNODC's Regional Representative for Southeast Asia and the Pacific. He called for a balance with these approaches and access to adequate health and social services. "I often comment that good public health equals good public security, but there is a distance to go before the balance is there [in Asia]," he said.
There is, however, "a significant move to align drug and public health policy," he said. Skyrocketing HIV epidemics among injecting drug users – who number 3 to 5 million in Asia – have forced governments to change.
Take Malaysia. In the 1990s, drug users were all sent to prison or drug rehabilitation centers run by former army personnel, who enforced daily military drills and marching. More than 75 percent of reported HIV infections cases were among drug users.
It was a shocking situation for Dr. Adeeba Kamarulzaman who returned to Malaysia in 1997, after training and working in Melbourne, where it was rare to see injecting drug users acquiring HIV. "After seeing one patient after another with advanced HIV who was a drug user, I felt that something really needed to be done," she said.
She put together a report with the help of Australian colleagues. "With that we went knocking on doors of agencies that had to do with either drug use or HIV… Ultimately we went to the highest political leadership who gave us the go ahead to pilot a methadone program in 2005. The nod to do a needle exchange program came as a complete surprise," said Adeeba, now the dean of University of Malaya's Faculty of Medicine.
The scientific evidence helped make a case for harm reduction and maintain it. "We took great pains to ensure that we had a good monitoring and evaluation system in place," she said.
The Cure and Care clinics which provide free, confidential, voluntary treatment such as methadone, have impressive results. One study found less than 40 percent of drug users attending the clinics relapse after a year – yet for compulsory detention centers, 50 percent relapse within a month, and 100 percent by a year. The clinics have been described as a model and have drawn visitors from across the region.
A recent return on investment study, done with World Bank support, found harm reduction had averted 12,600 new HIV infections. "Hopefully this has gone some way in ensuring that the programs are continued," Adeeba said.
Asia's hard line on drugs is softening elsewhere too. Most countries now have some harm reduction programs, although not enough to meet needs, said Gloria Lai, senior policy officer for the International Drug Policy Consortium. Changes in Singapore and Vietnam may help limit the death penalty while public debate on drug decriminalisation has emerged in a few countries, she added.
Last year, representatives of nine Asian countries met in Manila with UNODC and other UN bodies and agreed to a transition towards voluntary, community-based services for drug users. "The discussion now needs to be taken up to the policy level with government ministers," Douglas of the UNODC said.
Overall though, progress is still slow and piecemeal. In Malaysia, despite the success of harm reduction there, the country still maintains 28 drug rehabilitation centers and imprisons many drug users – 13,500 in 2014.
"Reform will be slow to come in the region because of the portrayal of drugs and any related activities as a security issue, in the minds of both government and the public, and the limited space for challenging those perspectives and policies," said Lai.
She added some countries "will stay entrenched" in the tough, punitive approach "for a while to come," in particular Singapore, Pakistan, Indonesia and China.
Mangai Balasegaram is a regular columnist with The Star, a national, English-language daily in Malaysia. She has been writing on drug use for 25 years, and previously won the international journalist of the year award from the International Harm Reduction Association, which promotes a public health approach to drug use.


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Mount Pleasant is special to woman following daughter's death from it in October 2012
Jeff Barron
Lancaster Eagle-Gazette
LANCASTER - Despite a horrific personal tragedy that occurred there, Kelly Fuller finds Mount Pleasant a peaceful place, particularly during the annual sunrise Easter service.
In October 2012, her 11-year-old daughter, Drew, died when she fell from the mountain. Fuller said she feels connected to her daughter while at the service.
"It just has come to represent reconciliation, resurrection and new hope," she said. "We've made friends there that we wouldn't have made had we not gone that we've stayed in touch with and proven to be incredible supporters in our lives."
Fuller has gone to every sunrise service on Easter there since 2013 before the COVID-19 pandemic forced its cancellation last year. Fuller, a Bexley resident and former Lancaster resident who works for the Columbus Chamber of Commerce, plans on going to Sunday's 7:15 a.m. service.
"I was terrified the first time up," she said of the 2013 visit. "In fact, I wasn't quite sure how I would react when we got to the top of the mountain. But just seeing all those people and watching the sun come up and being a part of it. We're not particularly overly religious people. I can't overstate that, I guess. But there's just something about that community of faith that drew us in and continues to draw us back every year."
By the time Easter came around in 2013, Fuller said she and her family, including husband Bob Thomas and daughter Caroline, were still grieving and could not bring themselves to go to church. But she said she had an overwhelming urge to visit Rising Park and Mount Pleasant for the first time since the tragedy.
"We found an incredible community of people that were worshipping and feeling close to their own faith," Fuller said. "It began to happen to me that I began to feel an incredible awakening of my faith."
Fuller said she went through some confusion and anger following Drew's death and didn't want to accept it.
"As anyone can imagine who's been through the loss of a child, it's traumatic for all involved," Fuller said. "Parents, siblings, grandparents, friends. We did struggle and all these years later, I guess, continue to do so around significant events like birthdays, holidays."
In order to deal with the grief, the family has dedicated itself to causes and organizations to help others and to keep Drew's spirit alive. Additionally, Fuller goes to art therapy which she said has been helpful in channeling her grief into something creative.
Going back to the awful day in 2012, Fuller said she got a call from Nationwide Children's Hospital in Columbus saying her child had been airlifted there after going to Rising Park to play. Caroline was Drew's twin sister, so Fuller didn't know which child was injured. But she was told the injury was just a broken leg, which was not true, of course.
"Once we arrived at Children's, we realized the injuries were much more catastrophic," Fuller said. "She had indeed broken her leg, but she had suffered a massive head injury. She did succumb to her injuries after 24 hours on life support."
Fuller said she doesn't know if the grieving process ever ends and that she belongs to several online support groups for grieving parents.
"It's always there," she said. "It just becomes less jagged and that just becomes part of who you are."
But while Drew is no longer with her, Fuller still has her memories.
"She was a very peace-loving person," she said. "She was a very joyous person. We were surprised at how many people came to the funeral (in Circleville). And as each child filed by me, almost to a person they said that she was my best friend.
"And I thought what a lovely legacy to leave, that you make every person in the world feel like they're so important that you are their best friend and they are your best friend."
As someone who has lost a child, Fuller is well-versed on advising others in her situation.
"Go easy on yourself," she said. "Everyone's grief journey is different. Give yourself time and space to heal the best you can. And if you are able to find counseling and support groups, there are those types of organizations available even at low or no cost to many people."
jbarron@gannett.com
Twitter: @JeffDBarron


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Home » Boris Johnson will hold Downing Street press conference today on Omicron variant
Boris Johnson will hold Downing Street press conference today on Omicron variant
November 30, 2021politics
The Prime Minister is expected to update the UK on new Covid rules which came into force at 4am today and discuss the booster vaccine rollout in a briefing in No10
Omicron: Boris Johnson announces tightening of coronavirus rules
Boris Johnson will give a Downing Street press conference this afternoon after new measures took force to tackle the Omicron variant.
The Prime Minister will speak after a flurry of announcements over the weekend as scientists found 11 cases of the strain with more than 30 mutations in the UK – with more cases expected to follow.
He is expected to speak about the new compulsory face mask rules which took effect in England from 4am today.
Mr Johnson will urge people to get their booster vaccines after the rollout was extended to all over-18s and the gap between second and third doses halved to three months.
According to reports, he will set a new target of 500,000 boosters a day – up from around 350,000 – and spell out when age groups can come forward. Health Minister Gillian Keegan said: "We be trying to increase the rate from the current rate."
He will also likely speak about new travel rules which force all arrivals to take a Day 2 PCR test and isolate until it comes back negative.
But Scotland and Wales' governments have demanded Mr Johnson go further and keep all arrivals in isolation until a Day 8 test.
Boris Johnson giving a previous No10 press conference
PA)
The Prime Minister has also not yet enacted all of England's 'Plan B' measures, leaving vaccine passports for nightclubs and stadiums in reserve.
And the government has not advised people in England to work from home where possible, despite advice of that kind in Scotland.
Asked if the Government might tighten up England's rules even further in the next three weeks, minister Edward Argar said: "It's not something I'm anticipating."
But the PM's spokesman did not rule out tighter travel rules, or tighter rules after the new restrictions are reviewed in three weeks' time.
No10 said Boris Johnson was not "planning" to adopt the plea for eight days' isolation, but did not rule it out, saying the response would be kept under review.
Straight after today's press conference, MPs will vote on an SNP motion to censure the PM for "frequently violating" ethics rules and more than halve his ministerial pay, cutting it by £41,567.
Critics suggest the Prime Minister is not going far enough
POOL/AFP via Getty Images)
Mr Johnson could also face a revolt from some Tory backbenchers at around 4pm when the new Covid measures go to a vote. They are concerned about what will happen when the measures expire on December 20 – with Parliament in recess.
In quotes released overnight by No10, the Prime Minister said: "The measures taking effect today are proportionate and responsible, and will buy us time in the face of this new variant.
"Based on everything we know, our vaccines and boosters remain our best line of defence, so it is more important than ever that people come forward when eligible to get boosted.
"Not only will today's steps help us slow down the variant's spread, but they will help us protect each other and the gains we have all worked so hard for."
The NHS is expected to set out more details of when people can book their boosters after tens of millions of Brits became eligible overnight.
Health Minister Gillian Keegan said the booking system would be up and running "in the next couple of days", urging people to "wait to be contacted for now".
Asked if Christmas will be ruined, she replied: "Hopefully not".
She added: "Let's be proportional and balanced, as we're trying to be. We have five cases today. That will go up I'm pretty sure, but what we're trying to do is really clamp down on that as much as possible."
All the new Covid rule changes from today – what you can and can't do
Covid face mask rules: Full list of places to cover up in from Tuesday to avoid £200 fine
Pupils in London schools where vaccination rates are low urged to keep masks
Ministers attempting to blackmail colleagues who might oppose PM, alleges Tory MP