text:
\section{Introduction}
\label{sec:introduction}

Expensive, large-scale supercomputers consisting of thousands of nodes make performance
a major issue for efficient resource utilization. A lot of research in this area concentrates on massive scalability, but there is just as much potential for optimization at the core and chip levels.
If performance fails to be acceptable at small scales, scaling up will waste resources even if the parallel efficiency is good. Therefore, performance engineering should always start with solid insight at the smallest scale: the core. Using this approach will give the performance engineer a profound understanding of performance behavior, guide optimization attempts and, finally, drive scaling at the relevant hardware bottlenecks.

Modeling techniques are essential to understand performance on a single core due to the complexities hidden in modern CPU and node architectures. Without a model it is hardly possible to navigate through the multitude of potential performance bottlenecks such as memory bandwidth, execution unit throughput, decoder throughput, cache latency, TLB misses or even OS jitter, which may or may not be relevant to the specific application at hand. Analytic models, if applied correctly, help us focus on the most relevant factors and allow validation of the gained insights. With ``analytic'' we mean models that were derived not by automated fitting of parameters of a highly generic predictor function, but by consciously selecting key factors that can be explained and understood by experts and then constructing a simplified machine and execution model from them.

We understand that the application of analytic performance modeling techniques often poses challenges or tends to be tedious, even for experienced software developers with a deep understanding of computer architecture and performance engineering. Kerncraft \cite{hammer15kerncraft}, our tool for automatic performance modeling, addresses these issues. Since its first publication, Kerncraft has been throughly extended with the layer condition model, an independent and more versatile cache simulation, as well as more flexible support for data accesses and kernel codes. These enhancements will be detailed in the following sections. Kerncraft is available for download under GPLv3 \cite{kerncraft-github}.

\subsection{Related Work}
\label{subsec:related}

Out of the many performance modeling tools that rely on hardware
metrics, statistical methods, curve fitting, and machine learning,
there are only four projects in the area of automatic and
analytic modeling that we know of: PBound, ExaSAT, Roof\/line Model
Toolkit and MAQAO.

Narayanan et al.\ \cite{pbounds2010} describe a tool (PBound) for
automatically extracting relevant information about execution
resources (arithmetic operations, loads and stores) from source
code. They do not, however, consider cache effects and parallel
execution, and their machine model is rather idealized.  Unat et
al.\ \cite{Unat01052015} introduce the ExaSAT tool, which uses
compiler technology for source code analysis and also employs ``layer
conditions'' \cite{stengel14} to assess the real data traffic for
every memory hierarchy level based on cache and problem sizes. They
use an abstract simplified machine model, whereas our Kerncraft tool
employs Intel IACA  to generate more
accurate in-core predictions. On the one hand this (currently)
restricts Kerncraft's in-core predictions to Intel CPUs, but on the
other hand provides predictions from the actual machine code
containing all compiler optimizationsr. Furthermore, ExaSAT is restricted to the Roof\/line model
for performance prediction. Being compiler-based,
ExaSAT supports full-application modeling and code optimizations,
which is work in progress for Kerncraft. It can
also incorporate communication (i.e., message passing) overhead,
which is not the scope of our research.  Lo et al.~\cite{rmt15} introduced in 2014 the ``Empirical Roof\/line
Toolkit,'' (ERT) which aims at automatically generating hardware
descriptions for Roof\/line analysis. They do not support automatic
topology detection and their use of compiler-generated loops
introduces an element of uncertainty.  Djoudi et
al.~\cite{djoudi2005maqao} started the MAQAO Project in 2005, which
uses static analysis to predict in-core execution time and combines it
with dynamic analysis to assess the overall code quality. It was
originally developed for the Itanium~2 processor but has since been adapted for
recent Intel64 architectures and the Xeon Phi. As with Kerncraft, MAQAO
currently supports only Intel architectures. The memory access analysis is based on
dynamic run-time data, i.e., it requires the code to be run on
the target architecture.

\subsection{Performance Models}
\label{subsec:perfmodels}

Performance modeling, historically done by pen, paper and brain, has a long tradition in computer science. For instance, the well-known Roof{}line model has its origins in the 1980s \cite{hockney89}. In this paper, we make use of the Roof{}line and the Execution-Cache-Memory (ECM) models, both of which are based on a bottleneck analysis under a throughput assumption. Detailed explanations of the models can be found in previous publications; we will limit ourselves to a short overview.

\subsubsection{Roof{}line}
\label{subsec:roofline}
The Roof\/line model yields an absolute upper performance bound for a loop. It is based on the assumption that either the data transfers to and from a single level in the memory hierarchy or the computational work dictates the runtime. This implies that all data transfers to all memory hierarchy levels perfectly overlap with each other and with the execution of instructions in the core, which is too optimistic in the general case. The Roof{}line model in the current form was popularized and named by Williams et al.\ in 2009 \cite{roofline:2009}.

For the types of analysis Kerncraft supports it is useful to reformulate the Roof\/line model in terms of execution time instead of performance, and to use a basic unit of work that spans the length of a cache line (typically eight iterations): $T_\mathrm{roof}=\max_k\left(T_\mathrm{core},T_k\right)$. The ratio $T_k=\beta_k/B_k$, with the achievable peak bandwidth $B_k$ and data transfer volume $\beta_k$, is the data transfer time for memory hierarchy level $k$. $T_\mathrm{core}=\phi/P_\mathrm{max}$ is the in-core execution time for computations with the amount of work $\phi$. The latter is usually given in \mbox{flops}, but any other well-defined metric will do. $P_\mathrm{max}$ is the applicable computational peak
performance (in \mbox{flops}\ per \mbox{cy}) of the code at hand. It may be smaller than the
absolute peak performance because of unbalanced multiply and add operations, because SIMD cannot be applied, etc.

Applying the Roof\/line model to a loop kernel which loads 448~\mbox{bytes}\ from the first level cache (L1), 6 cache lines (CL) from the second level cache (L2), 4 CLs from the last level cache (L3), and two CLs from main memory, to produce one cache line of results (8 iterations), gives us the data volumes in Table~\ref{tbl:roofline}. This is what we would expect with a 3D seven-point stencil (see Listing~\ref{lst:3d-7pt}) for a certain problem size that leads to a 3D-layer condition fulfilled in L3 and a 2D-layer condition fulfilled in L2 (see below for more on layer conditions). For the computational work, we assume 5 additions and 7 multiplications per iteration, thus 96 FLOPs for eight iterations, i.e.,
$\phi = 96\,\mbox{flop}$.
Combining this with measured bandwidths from a STREAM \cite{STREAM} copy kernel on an Ivy Bridge EP processor in all memory hierarchy levels, we can derive the throughput time per eight iterations shown in the last column of Table~\ref{tbl:roofline}. The achievable peak bandwidth $B_k$ is obtained via a streaming benchmark since theoretical bandwidths published by vendors cannot be obtained in practice.
The ECM model provides a partial explanation for this effect, so it requires less measured input data (see below).
\begin{table}[tbp]
    \caption{\label{tbl:roofline}Overview of data transfers and bandwidths necessary to model a 3D seven-point stencil kernel using the Roof{}line model.}
\centering\renewcommand{\arraystretch}{1.1}
\begin{tabular}{r||r|r|r}
    Level & Data Volume per 8 It. & STREAM copy Bandwidth & Time for 8 It. \\
    $k$ & $\beta_k$ & $B_k$ & $T_k$ \\
    \hline
    \hline
    L1 & $448\,\mbox{B}$ (only LOAD) & $137.1\,\mbox{GB/s}$ & $9.8\,\mbox{cy}$ \\

    L2 & $7\,\mbox{CL}$ or $384\,\mbox{B}$ & $68.4\,\mbox{GB/s}$ & $16.6\,\mbox{cy}$ \\

    L3 & $5\,\mbox{CL}$ or $256\,\mbox{B}$ & $38.8\,\mbox{GB/s}$ & $24.7\,\mbox{cy}$ \\

    MEM & $3\,\mbox{CL}$ or $128\,\mbox{B}$ & $17.9\,\mbox{GB/s}$ & $32.2\,\mbox{cy}$ \\

\end{tabular}
\end{table}

The double precision maximum applicable performance of a code with $5/7$ addition-multiplication ratio on an Ivy Bridge core  is
$$P_{\mathrm{max}} = \frac{40\,\mbox{flop}}{7\,\mbox{cy}}$$
which yields an in-core prediction of
$$T_\mathrm{core}={96\,\mbox{flop} \over 40\,\mbox{flop} / 7\,\mbox{cy}} = 16.8 \,\mbox{cy}$$
The dominating bottleneck is therefore the transfer from main memory $T_\mathrm{MEM}$ with $32.2\,\mbox{cy}$ for eight iterations or updates, which corresponds to a maximum expected (``lightspeed'') performance of $8.94\,\mbox{Gflop/s}$.

Predicting the L1 time and performance with the measured bandwidth can only be precise if the microbenchmark mimics exactly the load/store ratio as found in the modeled code. To circumvent this issue it is advisable to use a static analyzer with knowledge of the architecture, like the Intel Architecture Core Analyzer (IACA) \cite{iacaweb}. It also allows a more accurate prediction of $T_{\mathrm{core}}$.

\subsubsection{Execution-Cache-Memory}
\label{subsec:ecm}

The Execution-Memory-Cache (ECM) model is based on the same fundamental idea as the Roof\/line model, i.e., that data transfer time or execution of instructions, whichever takes longer, determine the runtime of a loop.  Unlike in the Roof\/line model, all memory hierarchy levels contribute to a single bottleneck. Depending on the microarchitecture, data transfer times to different memory hierarchy levels may overlap (as in the Roof{}line model) or they may add up. This latter assumption was shown to fit measurements quite well on x86-based processors~\cite{stengel14,Wittmann:2016}; on Power8, for instance, the cache hierarchy shows considerable overlap~\cite{Hofmann:2016-Kahan}. In the following we will concentrate on Intel architectures, since the current version of Kerncraft implements a strict non-overlapping ECM model.

We also need to know the data volumes transferred to and from each memory hierarchy level and the amount of work performed in the core. To calculate the time contributions per cache level we use documented inter-cache throughputs (e.g., two cycles per cache line from L3 to L2 on Intel Ivy Bridge). The ECM prediction on an Intel core for data in memory is then given by
$$
T_\mathrm{ECM,Mem} = \max\left(T_\mathrm{OL},T_\mathrm{nOL}+T_\mathrm{L1-L2}+
T_\mathrm{L2-L3}+T_\mathrm{L3-MEM}\right)~.
$$
$T_\mathrm{OL}$ is the overlapping time for computations and stores, $T_\mathrm{nOL}$ is the time for the loads from registers into L1, $T_\mathrm{L1L2}$ the loads from L2 into L1, and so on. The model is  written in the following compact notation:
$$
\ecm{T_\mathrm{OL}}{T_\mathrm{nOL}}{T_\mathrm{L1-L2}}{T_\mathrm{L2-L3}}{T_\mathrm{L3-MEM}}{}~.
$$
See \cite{stengel14} for more details on the model and the notation.

Applying the ECM model to the 3D seven-point stencil (see Listing~\ref{lst:3d-7pt}) on an Ivy Bridge EP processor, we get the in-core contributions from IACA:
$$T_\mathrm{OL}= 13.2\,\mbox{cy}\quad\mbox{and}\quad
T_\mathrm{nOL} = \beta_\mathrm{L1} \cdot 1 \frac{\mbox{cy}}{64\,\mbox{B}}=7\,\mbox{cy}~~.
$$
The data transfers through the memory hierarchy are obtained from cache simulation in combination with hardware performance characteristics:
$$T_\mathrm{L1-L2} = \beta_\mathrm{L2} \cdot 2\frac{\mbox{cy}}{\mbox{CL}}=14\,\mbox{cy}$$
$$T_\mathrm{L2-L3} = \beta_\mathrm{L3} \cdot 2\frac{\mbox{cy}}{\mbox{CL}}=10\,\mbox{cy}$$
$$T_\mathrm{L3-MEM} = \frac{\beta_\mathrm{MEM} \cdot 3.0\frac{\mbox{Gcy}}{\mbox{s}} \cdot 64\frac{\mbox{B}}{\mbox{CL}}}{63.4 \frac{\mbox{GB}}{\mbox{s}}} = 9.1\,\mbox{cy}$$
The ECM notation for eight iterations of the 3D seven-point stencil code is then:
$$
\ecm{13.2}{7}{14}{10}{9.1}{\mbox{cy}}~.
$$

A comparison of the data that goes into the ECM and Roof{}line analysis (manual and automatic) is shown in Figure~\ref{fig:ECMvsRoofline}. It also illustrates the fundamental differences in the bottleneck assumption.

\begin{figure}[tbp]
\sidecaption
\includegraphics[scale=.78]{ECMvsRoofline}
\caption{Side-by-side comparison of the (x86) ECM model and the Roof{}line model, including the origin of information needed as input for both, such as bandwidth and execution bottlenecks.}
\label{fig:ECMvsRoofline}
\end{figure}

\section{Kerncraft}
\label{sec:kerncraft}
In this section we give an overview of the architecture and analysis modes available in Kerncraft. The recent additions, which have not been covered in our 2015 publication \cite{hammer15kerncraft}, will be explained in due detail.

The core of Kerncraft is responsible for parsing and extracting information from a given kernel code, abstracting information about the machine, and providing a homogenous user interface. The modules responsible for the modeling  will be described in Section~\ref{subsec:models}. A visualization of the overall structure is shown in Figure~\ref{fig:overview}. The user has to provide a kernel code (described in Sec.~\ref{subsec:code}) and a machine description (described in Sec.~\ref{subsec:machine_description}), and they have to select a performance model to apply (options are described in Sec.\ref{subsec:models}). Optionally, parameters can be passed to the kernel code, similar to constants defined by macros or \verb.-D. compiler flags. For models that rely on prediction of caching, either the layer condition prediction or the cache simulation (using the pycachesim module) can be employed. Both predictors will be described in Section~\ref{subsec:cacheprediction}.
\begin{figure}[t]
\sidecaption
\includegraphics[width=\textwidth]{overview}
\caption{Overview of the Kerncraft pipeline. The user provides kernel code, constants, and a machine description. IACA, pycachesim, and a compiler are employed to build the ECM, Roof\/line, and layer condition models.}
\label{fig:overview}
\end{figure}

\subsection{Kernel Code}
\label{subsec:code}

Kerncraft is based on the analysis of standard-compliant C99 \cite{ISO:C99} code, which must be provided as shown in Listing~\ref{lst:3d-7pt}. Example files for several stencils are distributed with the Kerncraft repository\footnote{\url{https://github.com/RRZE-HPC/kerncraft/tree/master/examples/kernels}}. The first lines are dedicated to variable and array definitions. While large arrays would in practice be allocated on the heap, Kerncraft requires arrays to be declared as local varaibles. The multidimensional syntax (e.g., \texttt{a[M][N]} and \texttt{a[j][i]}) is optional, since Kerncraft now also supports flattened indices (e.g., \texttt{a[M*N]} and \texttt{a[j*N+i]}).

\texttt{N} and \texttt{M} in Listing~\ref{lst:3d-7pt}, are constants which can be passed to the code through the command line. During analysis they are treated as symbols, which may be replaced by constant positive integers.
\begin{lstlisting}[language=C,float=tbp,label={lst:3d-7pt},caption={Input kernel code for a three-dimensional 7-point star stencil (3D-7pt).}]
double a[M][N][N];
double b[M][N][N];
double coeffs_N, coeffs_S, coeffs_W, coeffs_E,
       coeffs_F, coeffs_B, s;

for(int k=1; k<M-1; ++k)
    for(int j=1; j<N-1; ++j)
        for(int i=1; i<N-1; ++i)
            b[k][j][i] = ( coeffs_W*a[k][j][i-1]
                         + coeffs_E*a[k][j][i+1]
                         + coeffs_N*a[k][j-1][i]
                         + coeffs_S*a[k][j+1][i]
                         + coeffs_B*a[k-1][j][i]
                         + coeffs_F*a[k+1][j][i]) * s;
\end{lstlisting}

Following the variable definitions is the loop nest, which may only contain one loop per level and only the innermost loop may contain variable assignments and arithmetic operations.
The loop indices must be local to that loop and the bounds may only depend on constant integers and simple arithmetic operations (addition, subtraction, and multiplication) of constant integers. The step size can be any constant length; in Listing~\ref{lst:3d-7pt} we have a step size of one, but \texttt{k+=2} would for instance also work.

Any number of statements are allowed in the loop body, as long as they are assignments and arithmetic operations based on constants, integers, variables, and array references. Array references may contain arithmetic expressions in their indices (e.g., \texttt{a[j*N+i+1]}). Such an expression may only be composed of constants, integers, and loop index variables (\texttt{i}, \texttt{j}, and \texttt{k} in Listing~\ref{lst:3d-7pt}).

Function calls, \texttt{if}s, pointer arithmetic, and irregular data accesses are not allowed, since they could not be analyzed with the algorithms used in the current version of Kerncraft. Moreover, the underlying models do not yet have a canonical way of dealing with the effects arising in such cases.

\subsection{Machine Description}
\label{subsec:machine_description}
To select the targeted machine architecture, Kerncraft needs a machine description file in the YAML file format \cite{yaml}. Example machines description files are distributed through the Kerncraft repository\footnote{\url{https://github.com/RRZE-HPC/kerncraft/tree/master/examples/machine-files}}. A machine description file always consists of three parts: the execution architecture description, the cache and memory hierarchy description, and benchmark results of typical streaming kernels. In the following, we will go into some settings found in Listing~\ref{lst:machinefile} that are not self-explanatory.

\begin{lstlisting}[float=tbp,language=yaml,label={lst:machinefile},caption={Shortened machine description for Haswell (skipped sections are marked by \texttt{...}).}]
# Execution Architecture:
model name: Intel(R) Xeon(R) CPU E5-2695 v3 @ 2.30GHz
micro-architecture: HSW
non-overlapping ports: [2D, 3D]
overlapping ports: ['0', 0DV, '1', '2', '3', '4', '5', '6', '7']
FLOPs per cycle:
  DP: {ADD: 8, FMA: 8, MUL: 8, total: 16}
  SP: {ADD: 16, FMA: 16, MUL: 16, total: 32}
compiler: icc
compiler flags: [-O3, -xAVX, -fno-alias]
...
# Memory and Cache Hierarchy:
memory hierarchy:
    - level: L1
      cache per group: {
         'sets': 64, 'ways': 8, 'cl_size': 64, # 32 kB
         'replacement_policy': 'LRU',
         'write_allocate': True, 'write_back': True,
         'load_from': 'L2', 'store_to': 'L2'}
      cores per group: 1
      threads per group: 2
      groups: 28
      cycles per cacheline transfer: 2
    ...
# Benchmark Description and Results:
benchmarks:
  kernels:
    copy:
      FLOPs per iteration: 0
      read streams: {bytes: 8.00 B, streams: 1}
      read+write streams: {bytes: 0.00 B, streams: 0}
      write streams: {bytes: 8.00 B, streams: 1}
    ...
  measurements:
    L1:
      1:
        cores: [1, 2, 3, ...]
        results:
          copy: [36.15 GB/s, 72.32 GB/s, 108.48 GB/s, ...]
          ...
        size per core: [21.12 kB, 21.12 kB, 21.12 kB, ...]
        size per thread: [21.12 kB, 21.12 kB, 21.12 kB, ...]
        threads: [1, 2, 3, ...]
        threads per core: 1
        total size: [21.12 kB, 42.24 kB, 63.36 kB, ...]
    ...

\end{lstlisting}

\paragraph{Compute Architecture}
The first section is the execution architecture description (the actual order of elements does not matter in the YAML file format). This section describes the compute capabilities of the machine, such as clock speed, number of cores, or compiler flags to use for benchmarks. \texttt{micro-architecture} is the abbreviation for the Intel microarchitecture codename as used by IACA (e.g., \texttt{HSW} for Haswell), \texttt{overlapping-ports} are the execution ports corresponding to the overlapping portion in the ECM model as reported by IACA, \texttt{non-overlapping-ports} are all other ports as reported by IACA.

The machine description file with the benchmark section and partial information about the memory hierarchy and compute architecture can be generated automatically by the script \texttt{likwid\_bench\_auto.py}, which comes with Kerncraft. It employs \texttt{likwid-topology} and \texttt{likwid-bench} \cite{likwid}  to gather accurate information about the machine it is executed on.

\paragraph{Memory Hierarchy}
Each level of the memory hierarchy has an entry in the \texttt{memory hierarchy} section. \texttt{cores per group} is the number of physical cores that share one resource on this level (e.g., if every core has its own private cache, \texttt{cores per group} is 1). \texttt{threads per group} is the number of virtual threads that share one resource on this level. \texttt{groups} is the total number of resources of this type (e.g., an L1 cache) that exist on all sockets. \texttt{cycles per cacheline transfer} is only needed for caches, except for the last level cache (LLC). It denotes the number of cycles it takes to load one cache line from the adjacent ``lower'' (closer to main memory) cache. For the last level cache this number is calculated from the measured saturated memory bandwidth.

The \texttt{cache per group} dictionary contains the cache description as required by pycachesim \cite{pycachesim}. \texttt{write\_back} makes sure that a modified cache line is transferred to the \texttt{store\_to} cache in case of its replacement. \texttt{write\_allocate} enforces a load of the cache line if some part of it is updated. The product of \texttt{sets}, \texttt{ways}, and \texttt{cl\_size} is the size of one cache resource in bytes.

\paragraph{Benchmarks}
Streaming benchmark results are required input for the Roof{}line model with all core counts and in all memory hierarchy levels. The ECM model only needs the measured saturated main memory bandwidth. In order to cover the whole memory hierarchy and typical effects and configurations, many tests are performed and their results stored in the machine description file. First, all benchmark kernels need to be specified in the \texttt{kernels} dictionary. For each kernel, \texttt{FLOPs per iteration} is the number of floating-point operations per iteration of the underlying kernel. \texttt{read streams} is the number of bytes and different streams read at each iteration. The ratio $\mathrm{\texttt{bytes}}/\mathrm{\texttt{streams}}$ is the size of one element in the processed array. \texttt{read+write streams} are accesses that are both read and written to (e.g., \texttt{a} in \texttt{a[i] = a[i] + 1}). \texttt{write streams} complements \texttt{read streams}. The differentiation into these three metrics is important to handle write-allocate transfers correctly.

The benchmark results are then grouped into memory hierarchy levels and SMT threads. Each such block has the configuration per physical core, with measured bandwidth (without write-allocate), used memory size (total, per thread and per core), and the number of cores and threads used.

\subsection{Models}
\label{subsec:models}
The models offered in Kerncraft are: \texttt{Roof{}line}, \texttt{ECM}, \texttt{Layer Conditions}, and \texttt{Benchmark}. Although not all are, strictly speaking, performance models, each one allows some unique and valuable insight into the performance, or some aspect of expected behavior, of the kernel at hand.

\paragraph{Roofline}
The Roof{}line model is implemented in the two variants \texttt{Roofline} and \texttt{Roof\-line\-IACA}. The former counts \mbox{flops}\ in the high level code and matches them to the \texttt{FLOPs per cycle} configuration in the machine description file. It also models the first level cache to register transfers using the corresponding measured bandwidth result. \texttt{RooflineIACA}, on the other hand, uses the IACA analysis to predict in-core or compute performance and first level cache to register throughput. This analysis will be explained in detail in the ECM section below.

Apart from the differences in the in-core and first level cache to registers bottlenecks, both variants use the same approach for analysis throughout the rest of the memory hierarchy: take the cache miss prediction (explained in Section~\ref{subsec:cacheprediction}) and predict the required data volume ($\beta_k$) coming out of each memory hierarchy level per iteration. Take these volumes and divide them by the measured achievable bandwidths ($B_k$) out of the corresponding hierarchy level, which yields a throughput time for that data amount ($T_k={\beta_k}/{B_k}$).
Out of the numerous benchmarks (as described in Section~\ref{subsec:machine_description}), Kerncraft tries to find the one matching the kernel under examination as closely as possible with regard to the number of read and write streams into memory.

If IACA is available and a supported Intel architecture is analyzed, the \texttt{Roof\-line\-IACA} model is to be preferred over the regular \texttt{Roofline} model, as it will yield a much better accuracy.

\paragraph{ECM}

Three versions of the Execution-Cache-Memory (ECM) model are supported: \texttt{ECM\-Data} (modeling only the first level cache to main memory data transfers), \texttt{ECMCPU} (modeling only the in-core performance and first level cache to registers) and \texttt{ECM} (combining the data and in-core predictions). \texttt{ECMPCPU} relies on a suitable compiler and IACA to be available, which is why the rest of the ECM model can be run separately.

\texttt{ECMData} uses either the layer conditions or cache simulation (both explained in Section~\ref{subsec:machine_description}) to predict the data volumes out of each memory hierarchy level. Then it applies the documented bandwidths for inter-cache transfers and the measured full-socket main memory bandwidth for the memory to LLC transfers. By taking the ratio of data volume and bandwidth, $T_\mathrm{L1L2}$, $T_\mathrm{L2L3}$, and $T_\mathrm{L3Mem}$ are calculated (on machines with three cache levels). The benchmark kernel used for the main memory bandwidth is chosen according to the read and write stream counts best matching the analyzed kernel.

\texttt{ECMCPU} requires that the kernel is analyzed by IACA, which in turn requires a compilable version of the kernel. The kernel code is therefore wrapped in a \verb.main. function that takes care of initializing all arrays and variables. Dummy function calls are inserted to prevent the compiler from removing seemingly useless data accesses. Once compiled to assembly language using appropriate optimizing flags, the innermost kernel loop is extracted and the unrolling factor is determined from it. Both are done using heuristics and may fail; if they do, interaction by the user is requested. Using the unrolling factor, the IACA predictions can be scaled to iterations in the high-level kernel code. IACA reports throughput cycle counts per port, which are then accumulated into $T_\mathrm{nOL}$ and $T_\mathrm{OL}$ based on the machine description configuration.

\paragraph{Layer Conditions}

To predict optimal blocking sizes, layer conditions can be formulated in an algebraic way and solved for block sizes. The details are explained in \cite{lc-web}, while the concept of layer conditions and our generic formulation is described in Section~\ref{subsec:layer-conditions}.

\paragraph{Benchmark}

To allow validation of the previously explained models, the benchmark model compiles and runs the code and measures performance. The code is prepared in basically the same way as for an IACA analysis, but arrays are initialized and LIKWID marker calls are inserted to enable precise measurements using hardware performance counters. The output of \verb.likwid-perfctr. is used to derive familiar metrics (\mbox{Gflop/s}, \mbox{MLUP/s}, etc.), which in turn are used for validations. It is important to note that this model must be executed on the same machine as the one in the machine description file passed to Kerncraft, otherwise results will not be conclusive.

\subsection{Cache Miss Prediction}
\label{subsec:cacheprediction}

One of the core capabilities of Kerncraft is the prediction of the origin of data within the memory hierarchy, which can currently be done via two methods: a partial cache simulation using pycachesim, or a layer condition analysis. Both prediction methods have their strong points and drawbacks. Cache simulation can capture some irregularities arising from the cache structure and implementation in hardware (such as associativity conflicts) and at the same time is more generic and versatile in terms of architectural features and the kernels it can be used for. Layer conditions, on the other hand, yield very clean and stable results without disturbance from hardware-specific issues. They can be evaluated very quickly and almost independently of the code and domain size, but they only work for least-recently-used (LRU) replacement policies and currently only handle sequential traversal patterns.

In summary, if the layer condition prediction can be applied to the kernel and architecture of interest, it is usually the better choice.

\subsubsection{Cache Simulation with pycachesim}
\label{subsec:pycachesim}

The open source pycachesim library is a spin-off from Kerncraft. It is designed to efficiently model all the common cache architectures found in Intel, AMD, and Nvidia products.\footnote{Kerncraft currently only supports Intel Xeon and Core architectures, but pycachesim has been developed with other architectures in mind.} The cache architecture is described in the machine description file and then modeled in pycachesim. It supports inclusive and exclusive caching, multiple replacement policies (LRU, RR, Random and FIFO) as well as victim caches. For the Intel architectures covered in this paper, inclusive write-back caches with LRU are assumed. The simulator, once initialized with the cache structure, gets passed accessed data locations (loads and stores), which are followed through the simulated memory hierarchy. It also keeps a statistic about accumulated load, store, hit, and miss counts. After a warm-up phase, the statistic is reset, data accesses from a precise number of loop iterations are passed to the simulator, and the updated statistic is read out. The gained information reflects the steady state behavior.

It is very important to align the end of the warm-up period with cache line boundaries, as well as with edges of the arrays to skip over boundary handling (e.g., loops that go from $2$ to $N-3$). If these cases are not considered, imprecise and oscillating performance predictions are likely.

\subsubsection{Layer Conditions}
\label{subsec:layer-conditions}

Another approach to predicting the cache traffic are the Layer Conditions \cite{Rivera:2000,stengel14}. In order to utilize them for our purposes, we have generalized and reformulated them to allow symbolic evaluation. The symbolic evaluation heavily relies on sympy \cite{sympy}, a computer algebra system for python.

The basis of layer conditions is the least-recently-used replacement policy, which (although typically not perfectly implemented in large, real caches) mimics observed behavior quite well. By taking the relative data access offsets and assuming sequential increments during the subsequent iterations, we can predict very precisely which access will hit or miss depending on given cache sizes.

For demonstration we assume a double precision 2D 5-point stencil on $\mathrm{M}\times\mathrm{N}$ arrays \texttt{a[M][N]} and \texttt{b[M][N]}, with accesses in the $j$th and $i$th iteration to  \texttt{a[j-1][i]},  \texttt{a[j][i-1]} \texttt{a[j][i+1]}, \texttt{a[j+1][i]} and \texttt{b[j][i]}. The inner loop index is \texttt{i}. Now we compute the offsets between all accesses after sorting them in increasing order (as already shown), e.g., \texttt{\&a[j][i-1] - \&a[j-1][i]} or $(N-1)$ elements. We store them in the list $L$ and insert, per array, another $\infty$, since we do not know the offsets between the arrays:
$$L=\{\underbrace{\infty}_{\text{first access}\atop\text{to \texttt{a}}}, \underbrace{N-1}_{\text{\texttt{\&a[j][i-1]}}\atop\text{\texttt{- \&a[j-1][i]}}}, \underbrace{2}_{\text{\texttt{\&a[j][i+1]}}\atop\text{\texttt{- \&a[j][i-1]}}}, \underbrace{N-1}_{\text{\texttt{\&a[j+1][i]}}\atop\text{\texttt{- \&a[j][i+1]}}}, \underbrace{\infty}_{\text{first access}\atop\text{to \texttt{b}}}\}$$
For each reuse distance $t$ in $L$ we can derive the required cache size $C_\mathrm{req}$, hits $C_\mathrm{hits}$, and misses $C_\mathrm{misses}$:
\begin{eqnarray*}
C_\mathrm{req} & =  & \sum(L_{\leq t}) + t*\mathrm{count}(L_{>t})\\
C_\mathrm{hits} & =  & \mathrm{count}(L_{\leq t})\\
C_\mathrm{misses} & = & \mathrm{count}(L_{>t})~~.
\end{eqnarray*}
Here, $L_\mathrm{condition}$ is a sublist of $L$ that contains only entries that fulfill the given condition (e.g., $L_{<t}$ contains all elements out of $L$ which are smaller than $t$).
Applying this method to the described kernel, we have the interesting case $t=N-1$, for which we get $C_\mathrm{req} = 2(N-1)+2+2(N-1) = 4N-2$ elements, or $32N-16$\,bytes, $C_\mathrm{hits} = 3$, and $C_\mathrm{misses} = 2$.

This means that if an LRU-based cache can hold more than  $32N-16\,\mathrm{bytes}$, three hits will be observed in each iteration and two misses will need to be passed to the next level in the memory hierarchy, which is to leading order exactly the result from a manual LC analysis (where the 16\,bytes are typically neglected so that four layers, i.e., rows, must fit into the cache). Since caches in modern CPUs do not operate on bytes but on cache lines, the computed hits and misses are averaged. Once a cache line was loaded due to a miss, subsequent accesses will be hits, which averages out to the misses and hits per iteration yielded by the layer condition analysis.

\subsection{Underlying In-Core Execution Prediction}
\label{subsec:in-core}

To predict the in-core execution behavior, we employ the Intel Architecture Core Analyzer (IACA) \cite{iacaweb}, which predicts the throughput and latency for a sequence of assembly instructions under the assumption that all loads can be served by the first level cache. IACA presupposes steady-state execution, i.e., the loop body is assumed to be executed often enough to amortize any start-up effects.

Kerncraft operates on high level C code, which can not be analyzed by IACA directly. Therefore it first needs to be transformed into a compilable version by wrapping the kernel in a \verb.main. function. It is then passed through a compiler and converted to assembly. The assembly sequence of the inner loop body needs to be marked to be recognized by IACA. The marked assembly is then fed into the assembler to produce an object file as input to IACA. IACA reports the throughput and latency analysis itemized by execution ports.
We are interested in the overall and load-related throughput and latency. Which execution ports are associated with loads is defined in the machine description file (see Section~\ref{subsec:machine_description} above).
The compiler might have unrolled the inner-most loop a number of times (e.g., to allow vectorization), so this factor needs to be extracted from the assembly to scale the IACA results to a single high-level kernel code loop iteration. The IACA output is parsed and the data is presented by Kerncraft as part of the analysis.

\section{Kerncraft Usage}
\label{sec:validation}

Kerncraft guides performance engineering efforts by allowing developers to predict and validate performance. In the following sections we will use an instructive example to demonstrate the single-core performance prediction, the scaling from single-core to the full socket, and the analytic layer conditions.
The analysis will be based on the long-range 3D kernel (3d-long-range) in Listing~\ref{lst:3d-long-range}.
Predictions and measurements will be done for the Intel Ivy Bridge EP (IVY) microarchitecture. The details of the machine are described in Table~\ref{tbl:machines}.

\begin{lstlisting}[language=C,float=tbp,label={lst:3d-long-range},caption={Kernel code for a three dimensional long-range star stencil with constant coefficients.}]
double U[M][N][N];
double V[M][N][N];
double ROC[M][N][N];
double c0, c1, c2, c3, c4, lap;

for(int k=4; k < M-4; k++) {
    for(int j=4; j < N-4; j++) {
        for(int i=4; i < N-4; i++) {
            lap = c0 * V[k][j][i]
                + c1 * ( V[ k ][ j ][i+1] + V[ k ][ j ][i-1])
                + c1 * ( V[ k ][j+1][ i ] + V[ k ][j-1][ i ])
                + c1 * ( V[k+1][ j ][ i ] + V[k-1][ j ][ i ])
                + c2 * ( V[ k ][ j ][i+2] + V[ k ][ j ][i-2])
                + c2 * ( V[ k ][j+2][ i ] + V[ k ][j-2][ i ])
                + c2 * ( V[k+2][ j ][ i ] + V[k-2][ j ][ i ])
                + c3 * ( V[ k ][ j ][i+3] + V[ k ][ j ][i-3])
                + c3 * ( V[ k ][j+3][ i ] + V[ k ][j-3][ i ])
                + c3 * ( V[k+3][ j ][ i ] + V[k-3][ j ][ i ])
                + c4 * ( V[ k ][ j ][i+4] + V[ k ][ j ][i-4])
                + c4 * ( V[ k ][j+4][ i ] + V[ k ][j-4][ i ])
                + c4 * ( V[k+4][ j ][ i ] + V[k-4][ j ][ i ]);
            U[k][j][i] = 2.f * V[k][j][i] - U[k][j][i]
                       + ROC[k][j][i] * lap;
}}}
\end{lstlisting}

\begin{table}[tbp]
    \centering\renewcommand{\arraystretch}{1.1}
    \label{tbl:machines}
    \caption{Technical data of the Ivy Bridge-based node used for the long-range stencil case study.}
\begin{tabular}{r||c}
    Microarchitecture & Ivy Bridge EP \\
    \hline
    Abbreviation      & IVY           \\

    \hline
    \hline
    Model Name & E5-2690v2 \\
    \hline
    Clock (fixed, no turbo) & 3.0 GHz\\
    \hline
    Cores per socket & 10 \\
    \hline\hline
    Cacheline size & $64\,\mathrm{B}$ \\
    \hline
    Theoretical L1-L2 bandwidth & $0.5\,\mathrm{CL/cy}$ \\
    \hline
    Theoretical L2-L3 bandwidth per core & $0.5\,\mathrm{CL/cy}$ \\
    \hline
    Achievable single-socket memory &  \multirow{2}{*}{$47.2\,\mathrm{GB/s}$ (7 cores)}\\
    bandwidth (copy kernel) &  \\
    \hline
    \hline
    Compiler version & Intel ICC 16.0.3 \\
    \hline
    IACA version & 2.1 \\
    \hline
    Kerncraft version & 0.4.3 \\
\end{tabular}
\end{table}

\subsection{Single-Core Performance}
\label{subsec:single-core}
Using Kerncraft for a single-core performance analysis involves choosing an overall prediction model (ECM or Roof{}line) and a cache predictor model (pycachesim simulation [SIM] or layer conditions [LC]). An example using \verb.RooflineIACA., \verb.ECM., and \verb.SIM. is shown in Listing~\ref{lst:output_ecm_rl}.
It is easy to do parameter studies via simple scripting, and scanning a range of problem sizes often leads to valuable insights. Running this analysis from $N=100$ to $N=2000$, we can see the effect of the inner dimension increasing and visualize it in Figure~\ref{fig:single-core}.
\begin{lstlisting}[float=tbp,language=shell,label={lst:output_ecm_rl},caption={Excerpt from the kerncraft CLI (reformatted for brevity) for the analysis of the long-range stencil}]
$ kerncraft -p ECM -p RooflineIACA --cache-predictor=SIM \
            3d-long-range.c -m IVY.yaml -D M 130 -D N 1015;
=========================== kerncraft ===========================
3d-long-range-stencil.c                               -m IVY.yaml
-D M 130 -D N 1015
----------------------------- ECM -------------------------------
{ 52.0 || 54.0 | 40.0 | 24.0 | 48.5 } cy/CL
{ 54.0 \ 94.0 \ 118.0 \ 166.5 } cy/CL
saturating at 4 cores

------------------------- RooflineIACA --------------------------
Bottlenecks:
 level | a. intensity | performance   | bandwidth  | bw kernel
-------+--------------+---------------+------------+----------
   CPU |              | 18.22 GFLOP/s |            |
    L2 |  0.26 FLOP/B | 17.52 GFLOP/s | 68.37 GB/s | copy
    L3 |  0.43 FLOP/B | 16.57 GFLOP/s | 38.79 GB/s | copy
   MEM |  0.43 FLOP/B |  7.65 GFLOP/s | 17.91 GB/s | copy

Cache or mem bound with 1 core(s)
7.65 GFLOP/s due to MEM bottleneck (bw with from copy benchmark)
Arithmetic Intensity: 0.43 FLOP/B
\end{lstlisting}

\begin{figure}[tbp]
\sidecaption
\includegraphics[width=\textwidth]{3d-long-range}
\caption{Single-core parameter sweep of the long-range stencil for $N=100$ to $N=2000$ with $M$ chosen such that the working set will never fit into any cache and needs to be loaded from main memory.}
\label{fig:single-core}
\end{figure}

The ECM prediction (stacked areas from $T_\mathrm{nOL} + T_\mathrm{L1-L2} + T_\mathrm{L2-L3} + T_\mathrm{L3-MEM}$) follows the trend of the measured throughput (black plus signs). The Roof{}line prediction (green dashed line) is generally too optimistic due to the evenly distributed runtime contribution from multiple memory hierarchy levels, which is not correctly modeled in this particular case. The cache simulator, taking the associativity of all cache levels into account, correctly identifies L1 thrashing and a corresponding runtime increase near $N=1792=7\cdot 256$. The corresponding increase in traffic between L1 and L2 of more than 50\% can be shown using performance counter measurements.
Many more such ``pathological'' sizes exist, of course, but the size range was not scanned with a step size of one.
In Figure~\ref{fig:single-core_LC} the same parameter study was done with the LC predictor. Since it knows nothing about cache organization, the prediction is much smoother.

\begin{figure}[!h]
\sidecaption
\includegraphics[width=\textwidth]{3d-long-range-LC}
\caption{Single-core parameter sweep, with layer condition cache prediction, of the long-rang stencil for $N=100$ to $N=2000$ with $M$ chosen such that the data will never fit into any cache and needs to be loaded from main memory.}
\label{fig:single-core_LC}
\end{figure}

\subsection{Single-Socket Scaling and Saturation Point}
\label{subsec:scaling}

For multi-core scaling the ECM model assumes perfect scalability until a shared
bandwidth bottleneck (usually the main memory bandwidth) is hit. It
thus predicts the number of cores where the loop performance ceases to
scale:
$$
n_\mathrm s=\frac{T_\mathrm{ECM,Mem}}{T_\mathrm{L3-Mem}}~~.
$$
By default, Kerncraft reports the saturation point in the ECM model, as seen in Listing~\ref{lst:output_ecm_rl}. The default report assumes that the total cache size and cache bandwidth scales with the number of cores. This is mostly true on current Intel microarchitectures, but not for the last level cache (L3) size, which is shared among all cores in a socket. To also take that change of cache sizes into account, Kerncraft can be run with the {\tt--cores} argument.
In the case presented in Listing~\ref{lst:output_ecm_rl}, a reduction of the L3 cache size by a factor of four (for 4 cores) does not change the predicted results, since no layer condition changes.

To perform the single-socket scaling  we added OpenMP pragmas to the outer loop in the code and ran with the same problem size as seen in Listing~\ref{lst:output_ecm_rl} (strong scaling). The result can be seen in Figure~\ref{fig:single-socket}: By increasing the number of cores up to the predicted saturation point (four cores), we expect perfect scaling (dashed gray line), and constant performance beyond (dotted line). The scaling model fits the observations very well except right before the saturation point, which is a known weakness of the ECM model with data-bound kernels \cite{stengel14}.
\begin{figure}[bp]
\sidecaption
\includegraphics[width=\textwidth]{3d-long-range-scaling}
\caption{Single-socket strong scaling of the long-range stencil for $N=1015$ and $M=132$ with all cores on same socket. The vertical line denotes the predicted saturation point. The horizontal line is the minumum runtime as given by the saturated memory bandwidth.}
\label{fig:single-socket}
\end{figure}

\subsection{Layer Conditions}
\label{subsec:loop-tiling}

Layer conditions enable a much more efficient cache behavior prediction without extensive parameter studies through the simulator or benchmarks. As explained in Section~\ref{subsec:layer-conditions}, they are evaluated analytically and yield a prediction for transition points from one cache state to another. Kerncraft generally employs analytic LCs when using the option {\tt--cache-predictor=LC}, but it can also output the derived transition points as shown in Listing~\ref{lst:kerncraft_lc}. The predicted transition in L3 from the 3D to the 2D layer condition at $N = 546$ is also clearly visible in Figures~\ref{fig:single-core} and \ref{fig:single-core_LC}.

\begin{lstlisting}[float=tbp,language=shell,label={lst:kerncraft_lc},caption={Excerpt from the kerncraft CLI (reformatted for brevity) showing LC transition points from the analysis of the long-range stencil}]
$ kerncraft -p LC 3d-long-range.c -m IVY.yaml -D M 130 -D N 1015;
=========================== kerncraft ===========================
3d-long-range-stencil.c                               -m IVY.yaml
-D M 130 -D N 1015
------------------------------ LC -------------------------------
2D Layer-Condition:
L1: N <= 216
L2: N <= 1725
L3: N <= 172463
3D Layer-Condition:
L1: N <= 19
L2: N <= 55
L3: N <= 546
\end{lstlisting}

\section{Future Work}
\label{sec:future}
Development on Kerncraft will continue and strive to enhance usability and portability and to allow support of a broader range of kernels and architectures.
One of the major obstacles to supporting  non-Intel CPUs is IACA, which is closed-source and only supports Intel microarchitectures. It is our goal to develop a model and tool which will be suitable for predictions on other architectures.
In the near future we will also integrate our layer condition model with the LLVM-Polly project \cite{polly:2012}.
This will allow the Polyhedral model to automatically choose cache-efficient tiling sizes without user interaction.

As with all of our tools and libraries (Kerncraft, LIKWID \cite{likwid}, GHOST \cite{ghost}, and the soon-to-be-published fault-tolerance package CRAFT), future work will be released under open source licenses and we will support and encourage other projects to build upon them.

\begin{acknowledgement}
This work was in part funded by the German Academic Exchange Service's (DAAD) FITweltweit program and the Federal Ministry of Education and Research (BMBF) SKAMPY grant.
\end{acknowledgement}

\bibliographystyle{spmpsci}

redpajama_set_name: RedPajamaArXiv


The EAWOP 2019's Program and Local Organizing Committees want to thank all authors who have sent abstract proposals. We have registered a high participation; particularly, we have received 147 contributions as symposia, 7 as panel discussions, 966 as oral presentations, 363 as posters and interactive posters, plus more than 15 invited symposia, with a total of over 2200 abstract proposals.
The review process is underway thanks to about 240 reviewers; we are very grateful to all of them for their contribution to the success of the Congress.
Notification of acceptance will be communicated to all authors by January 15th, 2019.
Keep in touch in the coming weeks with many other updates on the Congress!


text:
Government warns Ford owners about recalled…
Government warns Ford owners about recalled vehicles
The government on Thursday warned owners of about 4.6 million recalled Ford vehicles to bring their cars and trucks immediately to dealerships to disconnect cruise control switch systems that have been linked to engine fires.
The National Highway Traffic Safety Administration issued the consumer advisory to the owners of certain unrepaired Ford, Lincoln and Mercury sport utility vehicles, pickup trucks, vans and passenger cars who have not yet responded to past recalls.
The recalls have vexed the Dearborn, Mich.-based automaker, affecting its popular F-Series pickup trucks, prompting hundreds of complaints and dozens of lawsuits over engine fires. Three deaths have been tied to the fires and Ford has struggled to produce enough parts to fix the problem.
About 9.6 million Ford vehicles have been recalled since 1999 and about 5 million have been fixed, raising concerns about the remaining vehicles on the road. NHTSA said they have received about 60 complaints of engine fires in the Ford vehicles since August 2007.
Ford said they supported the action and dealers would soon offer a more permanent fix.
"We absolutely want everybody to come in as soon as they can because we can eliminate the risk of fire for anyone with a vehicle in this recall," said Ford Motor Co. spokesman Wes Sherwood. He said the company would have an "ample supply" of the replacement parts by June.
NHTSA said many dealers will disconnect the cruise control switches as a "drive through" service so owners do not have to leave their vehicles at the dealership or schedule an appointment.
Dealers have installed a fused wiring harness into the speed control electrical system as part of the recall, but replacement parts have not been widely available. Owners can take their vehicle to a dealer to have the cruise control deactivated until the parts arrive.
NHTSA issued a lengthy list of older vehicles covered by the consumer advisory, including 1993-2004 Ford F150 trucks, 1994-2002 F250 through F550 Super Duty trucks with gasoline engines, and 1998-2001 Ford Explorer and Mercury Mountaineer SUVs, all of which were among the best-selling vehicles in the nation during those years.
A complete list was available at http://www.nhtsa.dot.gov/.
The Ford recalls have run into problems. Earlier this month, the automaker recalled about 225,000 vehicles that had already been repaired because some wiring harnesses appeared to be defective.
Ford also faces more than 100 lawsuits nationwide because of fires linked to the cruise control deactivation switch. Many owners have alleged the fires began after the vehicles were turned off and there have been three deaths attributed to that problem in Iowa, Georgia and Arkansas.
Last week, Ford was able to consolidate 77 lawsuits filed in Texas so a single judge can handle pretrial discovery.
Ford has said its internal investigations have found the fires did not cause deaths and injuries.
"In the cases where there was that allegation, we found that the source of the fire was unrelated to the vehicle," said Ford spokeswoman Kristen Kinley.
For additional details, owners can call Ford at (888) 222-2751.
On the Net: Ford Motor Co.

redpajama_set_name: RedPajamaCommonCrawl


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text:
Q: Smart pointers with PythonQt My app uses QSharedPointers throughout the C++ API, where instead of returning an object, it usually returns a smart pointer to it and every class has an accompanying typedef for convenience.
class SomeClass
{
 SomeClassP getInstance() { return SomeClassP(new SomeClass()); }
}
typedef QSharedPointer<SomeClass> SomeClassP;

This has worked well, but I'm wondering how/if my design needs to be altered to handle PythonQt integration.  For example, in a PythonQtWrapper what should I return from pointers?  If I'm dealing with pointers in python, how can I call other functions that take a smart pointer and not a normal pointer?  Do I need to expose the smart pointer to PythonQt?  It seems that in boost::python a lot of the smart pointer stuff was taken care of automatically.  What needs to be done in my case?  Should I add additional functions in C++ that accept non-smart-pointers that simply wrap the pointer in a smart pointer and send it on to the smart-pointer-accepting function?  It seems the python API has some fairly complex rules regarding pointer ownership.
class PythonQtWrapper_SomeClass : public QObject
{
   Q_OBJECT
public slots:
   SomeClass* new_SomeClass() { return new SomeClass(); }
   void delete_Mesh(SomeClass* obj) { delete obj; }
   SomeClass* static_SomeClass_build(int foo) {
       SomeClassP ack = SomeFactory::build(foo);
       return ?
   }
};

A: We are having this exact same problem, and don't have a great solution yet.
Earlier resorted to adding variants of funcs that returned raw pointers instead. Then we got rid of those, and am now decorating smart pointers in PythonQt so that py code can call .get() on them to get the raw pointer. This is how I just made a first experimental switch to that style: (from https://github.com/realXtend/naali/commit/e72cb827c7fcbaee27b8258e616ee7bd2835fbd7 )
//Ptr conversions, not automatic but with an explicit call
int scenePtr_id = qRegisterMetaType<ScenePtr>("ScenePtr");
QObject* TundraDecorator::get(ScenePtr* self)
{
    return self->get();
}

Am not sure if that is safe even but seems to work. Am very interested if there are better solutions.

redpajama_set_name: RedPajamaStackExchange


Between 12 and 16 September, 2017, SCRC Director Gan Rongxing and Ruan Liangliang, Director of Shanghai Engineering Research Center of Biobank, under the invitation of BBMRI-ERIC (The Biobanking and Bimolecular Resources Research Infrastructure-European Research Infrastructure Consortium), attended Global Biobank Week 2017 (GBW 2017) held in Swede, and gave a key-note speech. At the conference, the delegates discussed about issues that were commonly concerned and interested, and basically realized the intended goal.
The conference, initiated by BBMRI-ERIC, welcomed about one thousand delegates outstanding in biobanking. They shared their practical experience in biobanking in the past, and discussed together about the future developmental direction for biobanking. Moreover, at the meeting, delegated exchanged ideas about quality control before and after making sample analysis, ethics, data and sample share mechanism, and sustainable development, and paid close attention to future development of biobanking, quality control of genomics, and the success stories in their biobanking practice.
During the conference, Director Gan Rongxing and Director Ruan Liangliang proactively communicated with local delegates on the issue of biobank. On the one hand, they learned a lot about the advanced technological experience; and on the other, they introduced biobanking in Shanghai to the international community. It drove forward international communication and cooperation, and further enhanced mutual understanding, leading to the consensus on some cooperative fields. Due to the active exchanges, SCRC delegates got a deeper understanding of the potential to cooperate with European countries in construction of biobank and development of translational medicine, thus obtaining the aim to communicate, enlarge influence, deepen friendship and achieve win-win collaborations. Meanwhile, by comparison, SCRC got clearer awareness of the gap between the self and the other, and deeper sense of responsibility and urgency, which would necessarily impel its development.
In a word, SCRC paid constant attention to the cooperation with international biobanking institutions and would deepen the cooperation with BBMRI-ERIC in the future, and further enhance SCRC's international influence in biobanking, thus largely promoting development of biobanking in China.


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The bright red envelope with the "all is calm, all is bright" holiday stamp gives no hint of the heartache inside.
"It is with deep sadness and grief that I share the news that our sweet and beautiful Dominique has died," reads the year-in-review letter from Nancy Swabb, the Chicago mom who welcomed the toddler from the West African nation of Ivory Coast into her home before and after a successful life-changing surgery in 2017 at Advocate Children's Hospital in Park Ridge. "It's hard to believe, I know. Dominique was love."
The relationship between Swabb and Dominque was celebrated last Mother's Day, which was Dominique's second and final birthday, with a feel-good Daily Herald column explaining the bond between Swabb and the happy and healthy active kid with a smile that spanned two continents.
"I just fell in love with her," Swabb said of Dominique then. "I feel we will have a bond forever."
Expected to have a long life after her successful surgery, Dominque developed a high fever in her Ivory Coast home and died a few days later on Oct. 29, 2018. The Swabb family sent Dominque home with mosquito netting, but Swabb says, "We suspect that malaria took her life." The mosquito-borne illness killed 435,000 people worldwide in 2017, most of them children younger than 5, according to the World Health Organization.
"We want to keep her story alive, her spirit," Swabb says of Dominque. "She really made us all feel so good."
Borrowing a concept and a hashtag used last year by her friend Jen Kramer, the director of university events at DePaul, Swabb is using #yearoflove and #dominiqueislove to highlight kindhearted and inspiring people on her Facebook page throughout 2019.
Swabb says she, her husband, Tim, and their daughters Lena, 16, and Mara, 11, got so much joy from their relationship with Dominique and the girl's family members, who still keep in touch online. "I will always consider you my sister and we will be connected forever," Dominque's father told Swabb.
Swabb, a marketing expert and event planner who served as an infant-care volunteer for a decade at a Chicago hospital, first saw Dominique's story on the website for Children's Medical Mission West, which arranged Dominique's medical care in the United States. Swabb and her family hosted the girl before and after her groundbreaking "miracle" surgery.
Born with an extremely rare condition in which a twin stops developing during gestation but fails to separate from the other body, Dominque endured a six-hour surgery to remove the bottom half of the twin's body -- the waist, spine, bladder, two moving legs and feet -- protruding from Dominique's neck and back.
"It's why we go into medicine," Dr. John Ruge, the pediatric neurosurgeon who led the Advocate Children's Hospital team that cared for Dominique, said at the time. "I'm just really proud of our team. I have a lot of rewarding cases, but this one is unique. She's a happy little girl, walking around and normal."
After Dominique's death, the hospital issued a statement. "Our hearts are broken at Advocate Children's Hospital," began the notice. "Our thoughts and prayers are with Dominique's family and the Swabb family of Chicago, who served as Dominique's host family during her surgery and recovery. Dominique touched all of our hearts."
Posting good news daily in Dominique's memory is the way Swabb keeps the girl in those hearts. "I want to have that little moment of happiness every day," Swabb says. "I'm doing it because there was so much good and so much love that came out of it."


Casa Calvet was erected between 1898 and 1900 for the Calvets, a family of textile industrialists. It was built with offices on the ground floor, though the space now hosts a restaurant. Gaudí's most conventional work, it received the Barcelona City Council Award in 1900 for the best building finished in that year which exhibited major artistic merits.
The building was constructed by Gaudí along the strictly codified lines of houses in the Eixample district although there were problems along the way. At first Gaudí's plans were rejected by the municipal architect of the City on the grounds that the building's height would exceed the maximum permitted for the street on which it was to be built. However after Gaudi threatened to build it to the allowed height and then end it abruptly, the objection was dropped.
The stone facade with its bay windows and sculptural decoration as well as the vestibule, stairway, and elevator reflect baroque influences. The shape of the balconies can be seen as a forerunner to shapes used at Casa Batlló where Gaudi turned much more to the inspiration of nature. The roof is topped with two pediments, each supporting a wrought iron cross, and are surrounded by various pieces of stone ornamentation as well as statues of San Ginés and Saint Peter, patron saints of the Calvet home town of Vilasar de Mar.


text:
Q: Ajax Bootstrap Popover: Object # has no method 'popover' I'm trying to build an Ajax Bootstrap Popover to display a page that contains a rating star system.
The javascript here work nice the first time.
Then I have this error:

Uncaught TypeError: Object # has no method 'popover'

I'm not really good in jQuery, but I guess it seems to be due to the ajax call, but I can't find where the problem is.
$(".myRate")
        .popover({
            offset: 10,
            trigger: 'manual',
            animate: false,
            html: true,
            placement: 'top',
            template: '

'

        });
$('.myRate').mouseenter(popoverDisplay);

popoverDisplay = function() {
var el = $(this);
var _data = el.attr('alt');
$.ajax({
     type: 'GET',
     url: 'notes.php',
     data: _data,
     cache: false,
     dataType: 'html',
     success: function(data) {
        el.attr('data-content', data);
        el.popover('show');
     }
  });
}

I don't get what I am doing wrong...
Any idea ?
EDIT:
After searching, it seems that, it's the loaded pages which causes this error.
Exactly this part:
It seems that loading jquery-1.7.2.js make the bug because if I remove it, the error disapear. Problem: I can't delete it because without it jRating doesn't work anymore :/

A: I had this problem because i was trying to use the jQuery from bootstrap while also importing jQuery from googleapis
(like it says in http://railscasts.com/episodes/205-unobtrusive-javascript)
if you're using bootstrap, you'll have jquery

A: I had this problem after running the rails twitter bootstrap generator, then switching to bootstrap-sass.
It was caused by a filename collision because boostrap-sass references bootstrap.js instead of twitter/bootstrap, which clashes with the generated file.
Just rename the generated app/assets/javascripts/bootstrap.js.coffee to something else, eg app/assets/javascripts/bootstrap_and_overrides.js.coffee, and you're good to go.

A: i had the same problem .
you might be loading jquery AFTER loading bootstrap.js . for some reason the sequence is important

loading jquery before bootstrap did the job for me . hope that helps

A: I had the same problem. I was loading jQuery.js twice... Narf...

A: You can either use boostrap.js or (bootstrap-popover.js and bootstrap-tooltip.js)
But not both because if you use both. You get Uncaught TypeError: Object # has no method 'popover'

A: I guess you're using rails, so it might come that assets/vendor/jquery is loaded after assets/vendor/bootstrap, because the load order is alphabetical. So you might rename the bootstrap file to fit the right loading order. I experienced that problem and it did the trick


text:
For those interested in publishing articles that concern a broad range of topics in French and Francophone literature, film, culture, and theory from the medieval period to the twenty-first century. However, articles on French literature in the nineteenth and twentieth century predominate ("Francophone" literature is lightly represented, with perhaps one article a year).
Articles from all periods are selected for publication; articles on material from the nineteenth to the twentieth century have a slightly higher representation with a little over 40% for the past five years, while ones covering the eighteenth century make up less than 20% of articles. Medieval and early modern make up approximately 10% each.
Submissions are accepted in both English and French. The journal does not seem to be concerned with the ratio of English-French articles, although there are fewer French articles: some issues only contain articles in English, others include more French articles than the English, or vice versa. That is to say, their concern is not the language but the quality of the articles.
As they claim on their website, the journal is " the most comprehensive source…in French studies," it covers a wide breadth of subject from film to critical theories. However, in each issue, literature is the dominant subject, followed by philosophy/critical inquiries, linguistics and films. Philosophical subjects tend to overlap with literary genres or subjects, as opposed to being a pure conceptual inquiry.
Few literary figures/philosophers/film makers are discussed repeatedly; except for Marcel Proust (7 articles in the past five years). Montaigne and Corneille are the only other authors with more than one article in the past five years.
The subjects vary as well, but some recurring topics are: gender, hetero/homo-sexuality, sexual politics, aesthetics, body, and (urban) space. Among other topics, it may be worth mentioning that the question of "Frenchness" recurs, which is unique to this journal. The focus is on the canon.
About 1 out of 5 articles analyzes a literary text through the lens of a theorist such as Derrida, Foucault, Barthes, or Deleuze.
The journal occasionally has a special issue, however, there was only one special issue over the past 5 years, which was on "The Medieval Library" (Vol. Issue 2, 2016).
Reviewed by TS
Useful for Submission
Word Count: Articles should not, as a rule, exceed 6,000-8,000 words in length, including notes.
Issues per year: Quarterly (January, April, July, and October)
Current volume number: Volume 71, Issue 1, January 2017
Articles per year: 20
Citation style: MHRA style
Abstract length (if required): N/A
Upcoming special issues (if available): N/A
Relevant Editors: Timothy Unwin (University of Bristol), Russell Goulbourne, and Emma Cayley
https://wp.me/p6aNXL-7e


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text:
Home / News & Sport / Boxing – McCloskey to Return To Letterkenny
Boxing – McCloskey to Return To Letterkenny
Paul McCloskey will enjoy home comforts for the second defence of his European Light Welterweight title against Barry "The Bizness" Morrison on the Hunky Dorys Fight Night at The Aura in Letterkenny on Saturday, October 2nd. The unbeaten Dungiven southpaw will be returning to the scene of his victory over former World Champ Cesar Bazan in 2008 as European Championship Boxing comes to Donegal for the very first time. McCloskey is currently rated number 4 in the World by the WBC and he will be looking to press his claims for a shot at the World's elite with the likes of Amir Khan and undefeated Americans Tim Bradley and Devon Alexander considered the marquee names in the Light Welterweight division.
Paul is looking forward to his return to Letterkenny.
https://highlandradio.com/wp-content/uploads/2010/08/BOX-Paul.mp3
In the chief supporting contest in Letterkenny unbeaten Cavan star Andy Murray faces a major step up in class in an International ten round contest and Donegal's own Michael Mc Laughlin will make his pro debut on the night.
https://dev.highlandradio.com/wp-content/uploads/2010/08/BOX-Paul.mp3


text:
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How Pierre Hardy Accidentally Became a Shoe Designer
The Parisian shoe designer behind Hermès and his namesake line has a refreshingly irreverent view of the fashion industry.
By: Emily Ramshaw
Styling: Stephanie Mark
Photography: Jake Rosenberg
Only Pierre Hardy could accidentally fall into shoe design and get his first real gig at Dior in the '80s when "it was the biggest name in fashion," meanwhile holding on to his teaching job at a fashion school. Hardy only gave up the teaching job six years ago—despite the fact that he's been designing his own label since 1999 and has been in charge of shoes and jewelry at Hermès for more than 15 years—as we learned when we chatted up the designer at his showroom and studio. According to him, it meant that it was never really about the money, a pretty rare position to be in, and a perspective that has led him to creating Fashion Week collections that are more about sharing his conceptual ideas than selling shoes. In turn, that same point of view is probably what's led us to covet his label (and Hermès'), and it's distinct intellectual aesthetic more than most. Here, the irreverent designer on how he stumbled into shoe design and then jewelry design, why Hermès is the purest brand in the industry, and why disillusion caused him to launch his own label.
His circuitous route to becoming a full-time designer:
"It has been very organic. The one thing I've always loved since I was a kid was drawing—day and night, on the holidays and during school time. It was the only thing I wanted to do. It happened that it became shoes because I was studying fine art and I met a friend who was into fashion—they asked me to do some illustration for them and illustrations for a fashion magazine. Someone in fashion told me, 'Ah! Apparently you love to draw, maybe you could draw a collection.' I thought, 'Why not?!' At that time I didn't know what that was exactly. It was just for fun and expressing myself. They asked me for a shoe collection. If someone had asked me to draw clothes, I would be doing clothes today. There wasn't a strategy or a career. I had a lot of passion, but distance, too. First of all, I had another job. I was teacher. I wasn't desperate to earn money. It was just for fun."
"I stopped teaching [six] years ago. I was teaching at a fashion school, one of the best in Paris. I didn't really teach fashion, more creative methodology. My students used to come from many different fields like architecture, advertising, illustration, fashion, textile, whatever. The purpose was to make them work together and to make them really creative people.
"The first shoe I designed was a pair for my collection. The first collection was a turning point for me. It's the moment when you use your own voice. You say, 'Okay, I'm not talking for someone else.' That makes a big difference."
Collaborating with major fashion houses is an art:
"My first real collaboration was at Dior. Once again I went in like a child [laughs]. This was in '87. [Dior] was the biggest name in fashion, but it was still handcrafted. I was doing the boutique collection, the ready-to-wear collection, the couture collection, and the license collection. That's when I learned how not to separate, but articulate the different levels within a collection and treat it as an image. With a brand as famous as Dior with its heritage and DNA, I had to analyze it and transform it into something modern.
"Hermès was very different because Hermès is not totally a fashion brand. It is more about quality and depth and your knowledge of what a beautiful product is. Now everybody is trying to do this, but the first house to treat the fashion product this way—not the image, not the communication, not the people, but really the product—[was Hermès]. The collection, at the beginning, was nothing. There was no real shoe collection. I improved myself a lot because I really had to build it, collection after collection, to make people understand that it was a shoe collection; that was not totally linked with the ready-to-wear, but things you could buy separately. It is very interesting still because it's growing and progressing."
How he wound up taking on jewelry at Hermès as well:
"The president, Jean-Louis Dumas, asked me, 'Would you, by the way, be interested in doing jewelry?' I said, 'Not specifically, actually, to tell you the truth!' I had never thought about it! He said, 'Well, you should try it.' So I said, 'Okay!' And then it was done. That was fifteen years ago."
Why he launched his own label:
"Disillusion [laughs]. At one point, you believe that you know all the things… Like, 'I'm a big guy, I'm going to do it by myself.' Wroooongg [laughs]! It is much more complicated when you are by yourself—it's easy to do a collection for someone else. Especially for Hermès because they give you freedom and support. But then you have to build a little car by yourself and drive it. There's no protection, there's no screen. There is no team and no name to protect you. You have to do everything. I discovered, step-by-step, that it would be okay. I [want my own line because] I noticed when I was drawing and designing there were some ideas that I couldn't explore and express for other brands. I said, 'Okay, let's build a space to make this happen.' That's what I did!"
On the subject of his definitive aesthetic:
"You can't explain why you prefer red and not blue, or why you like darkness. I try to express what I like season after season in different ways. I think and I hope that there is an identity that you can recognize. I must say that when I look back at the first collection, there is a center—there is a sun and there are some planets around it. Every collection is a planet, building a world, a dream world because it is a fantasy of your own. That's what I am trying to do."
How he's dealing with the speed of the fashion cycle:
"Everyone knows the rhythm of fashion is absurd. It doesn't correspond to any reality! Not the reality of creation, the manufacturer, the distributor, the customer—and not the reality of the press! Everyone is misfit! I don't make a main collection. It's now too late for the customer because they see it now and in six months they don't care—and they may want something different in between. Now I'm presenting only creative experimental collections, where I go push the aesthetic. Then we do two full collections for resort [and pre-fall]."
His not-so-average day:
"First, it is never the same. [The only thing that is the same] is that I wake up quite early at seven and go to the gym! Then I arrive at the office. I go to Hermès if there is a collection meeting or a prototype check. Basically my time is shared between here and Hermès, but more here."
Want more stories like this?
An Afternoon with Isabel Marant
A Walk Around the Block with Christian Louboutin
Catching Up with Elena Doukas—the Woman Behind Your Favorite Sunglasses
Part of the series:
Them's Whembley Sewell on Shaking Up the Media Industry
8 Unisex Fragrances You Need on Your Vanity
Inside NYC's Most Luxurious Watch and Jewelry Boutique
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Venture Financings
IP & Tech Transactions
Blockchain & Digital Currency
Lawtalk Blog
The Balancing Test Between Data Privacy and Public Health in a Pandemic
Steve Masur
By: Steven Masur and Maria Samson
The 2019 novel coronavirus "COVID" has disrupted seemingly every facet of daily life. From closing schools to altering the 9-to-5 workday, the pandemic has made us question constructs that have long been established as "the way it is," and created a new construct; the way it is now, or "the new normal." Organizations of all kinds have had to come up with unprecedented new solutions, such as imposing mandatory quarantines and creating contract tracing methods to flatten the curve. Unsurprisingly, governments have increased surveillance to control the spread of COVID, and have instituted tracking measures that make many people uncomfortable. How far should such surveillance go? Is your privacy at risk?
Pandemic outbreaks like COVID will likely occur again, and perhaps with more frequency. Contact tracing practices and surveillance technology created in reaction to the current pandemic threaten individual privacy and may have long-term privacy implications. As we shift to a new version of normal, we must find a balance between individual privacy and public health.
Companies, such as Apple and Google, are offering technology-assisted contact tracing solutions to help battle COVID. The Apple-Google solution is voluntary and allegedly anonymous, which aims to help control the spread of the virus by using Bluetooth technology. The Apple-Google solution records a user's whereabouts, relationships, and activities. It is a good idea in theory, but in practice, such tracing technology is in its infancy and its efficacy is still in question. For instance, Norway temporarily suspended its nationwide contact tracing app due to security concerns. The app was gathering more data than was necessary to track the virus. As a result, Norway decided to delete all data collected by the app because keeping it constituted a disproportionate intrusion in citizens' privacy. Ultimately, because contact tracing gathers so much information about an individual's day-to-day activities, critics say that its use at scale could roll back years of privacy protection efforts that were meant to protect sensitive location data and keep people safe from governmental as well as criminal and other potential threats.
Contact tracing apps are not narrowly tailored to only track one's contact with COVID. They record an individual's location and movement, making it difficult to keep the data anonymous. The surveillance technology is more intrusive than necessary to achieve the narrow purpose of tracking the spread of COVID "hot spots". While it may seem important to share this information now, proceeding down this slippery slope implicitly gives the government the actual data and could lead to unauthorized mass surveillance. In addition, the data is stored in centralized and mirrored databases that are susceptible to security breaches and make it likely that the data could be obtained and used not only by the government but by criminals as well.
In time, contact tracing methods can be developed to both serve public health and protect individual privacy. While governments and institutions have yet to find a solution that successfully balances these interests, we must safeguard individual privacy and not turn a blind eye to the rise of inappropriate or illegal forms of surveillance.
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Donate to Connect now!
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You or your company can become a Friend of Connect and earn a spot in the hall of fame on our website home page, or donate any amount to support our youngsters.
Connect is a registered non-profit company and can provide a Section 18(A) certificate for South African donations.
Donations from the UK even come with a Gift Aid tax break thanks to our partners, the Atlas Foundation.
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Sweet, smoky and entirely irresistible, this recipe combines baked and black beans and smothers them with a barbecue sauce full of cubed pork loin, onion, garlic, chili powder and ground cumin.
Heat oil over medium heat in large skillet or saucepan. Sauté onion and garlic 3 minutes. Stir in remaining ingredients, except pork.
Bring to boil, reduce heat and cover; simmer 15 minutes.
Stir in chopped pork, cover and simmer 5 minutes more or until pork is heated through. Serve with coleslaw and cornbread.


A special Thank You goes out to Adam and Christa Kalcic for setting this site up for me; it is a wonderful Christmas present.
Adam's amazing talent at website design and development is responsible for all the marvelous pages you going to find here on this site. He even taught me how to do a few things here which was a miracle in itself.
This is going to be an invaluable tool to help promote the novel, it's a true treasure for any up and coming author.
www.Facebook.com/GreyGhostNovel to the new website!
And as a special treat on this, the official opening of the Nicholas Cara website, I am giving you all an exclusive sneak peek at two significant items from The Grey Ghost: The Shadow That Walks.
Remember these two leaks from the pages are TOP SECRET!


For use with the M18 Multi-Tool, the Dust Extraction Kit is designed to help keep your work area clean during sanding applications and reduce clean up time. The dust extractor fits onto a 1-1/4 in. vacuum hose for easy dust collection.