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Patent application title: STRUCTURE AND METHOD TO MAKE REPLACEMENT METAL GATE AND CONTACT METAL
Inventors: Zhengwen Li (Wappingers Falls, NY, US) Michael P. Chudzik (Danbury, CT, US) Unoh Kwon (Fishkill, NY, US) Unoh Kwon (Fishkill, NY, US) Filippos Papadatos (Wappingers Falls, NY, US) Andrew H. Simon (Fishkill, NY, US) Keith Kwong Hon Wong (Wappingers Falls, NY, US)
Assignees: International Business Machines Corporation
IPC8 Class: AH01L2916FI
Class name: Active solid-state devices (e.g., transistors, solid-state diodes) specified wide band gap (1.5ev) semiconductor material other than gaasp or gaalas diamond or silicon carbide
An electrical device is provided that in one embodiment includes a p-type semiconductor device having a first gate structure that includes a gate dielectric that is present on the semiconductor substrate, a p-type work function metal layer, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An n-type semiconductor device is also present on the semiconductor substrate that includes a second gate structure that includes a gate dielectric, a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. An interlevel dielectric is present over the semiconductor substrate. The interlevel dielectric includes interconnects to the source and drain regions of the p-type and n-type semiconductor devices. The interconnects are composed of a metal layer composed of titanium and aluminum, and a metal fill composed of aluminum. The present disclosure also provides a method of forming the aforementioned structure.
1. An electrical device comprising: an n-type semiconductor device comprising a first gate structure in a first device region of a semiconductor substrate that is between a first source region and a first drain region, wherein the first gate structure includes a gate dielectric that is present on the semiconductor substrate, a metal layer comprising titanium and aluminum, and a metal fill comprised of aluminum; a p-type semiconductor device comprising a second gate structure in a second device region of the semiconductor substrate that is between a second source region and a second drain region, wherein the second gate structure includes the gate dielectric that is present on the semiconductor substrate, a p-type work function metal layer, the metal layer comprising titanium and aluminum, and the metal fill comprised of aluminum; and an interlevel dielectric that is present over the semiconductor substrate, the interlevel dielectric comprising interconnects to the first source region, the first drain region, the second source region and the second drain region, wherein the interconnects are comprised of the metal layer comprising titanium and aluminum, and the metal fill comprised of aluminum.
2. The semiconductor device of claim 1, wherein the gate dielectric is comprised of one of SiO2, Si3N4, SiON, TiO2, Al2O3, ZrO2, HfO2, Ta2O5, La2O3 and combinations thereof.
3. The semiconductor device of claim 1, wherein the gate dielectric is comprised of a high-k dielectric material.
4. The semiconductor device of claim 1, wherein the gate dielectric is comprised of hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate or a combination thereof.
5. The semiconductor device of claim 1, wherein the gate dielectric comprises a HfO2 layer in direct contact with the semiconductor substrate.
6. The semiconductor device of claim 5, wherein the gate dielectric comprises a TiN layer that is in direct contact with an upper surface of the HfO2 layer.
7. The semiconductor device of claim 1, wherein the p-type work function metal layer comprises TiN, TaC, Ru, NiTi, or a combination thereof.
8. The semiconductor device of claim 1, wherein the metal layer comprising titanium and aluminum is an n-type work function metal layer.
9. The semiconductor device of claim 1, wherein the semiconductor substrate is comprised of Si, SiGe, SiGeC, SiC or a combination thereof.
10. The semiconductor device of claim 1, wherein the interlevel dielectric layer is comprised of a material that is selected from the group consisting of SiO2, Si3N4, SiOxNy, SiC, SiCO, SiCOH, SiCH compounds and the above-mentioned silicon-containing materials with some or all of the Si replaced by Ge.
11. The semiconductor device of claim 1, wherein the interlevel dielectric layer is comprised of a material that is selected from the group consisting of carbon-doped oxides, inorganic oxides, inorganic polymers, hybrid polymers, organic polymers, spin-on glass, silsesquioxane-based materials, diamond-like carbon and combinations thereof.
12. The semiconductor device of claim 1, wherein the p-type work function metal layer is comprised of TiN, TaC, TaNC, Ru, TiNi or a combination thereof.
13. The semiconductor device of claim 1, wherein the metal layer comprising titanium and aluminum has a thickness that ranges from 5 nm to 10 nm.
14. The semiconductor device of claim 10, wherein the metal layer comprising titanium and aluminum is titanium aluminum nitride (TiAlN).
15. The semiconductor device of claim 14, wherein the metal layer of the titanium aluminum nitride has a titanium content that ranges from 20 wt % to 80 wt %, an aluminum content that ranges from 20 wt % to 60 wt %, and a nitrogen content that ranges from 20 wt % to 60 wt %.
16. The semiconductor device of claim 15, wherein the metal fill is metal fill is 99% aluminum.
17. The semiconductor device of claim 16, wherein the metal fill comprises a maximum of 0.05 wt % for each impurity, and a maximum of 0.1 wt % for a total impurity content, wherein the impurity is selected from the group consisting of iron (Fe), copper (Cu), silver (Ag) and combinations thereof.
[0001] This application is a divisional of U.S. patent application Ser. No. 12/717,398, filed Mar. 4, 2010 the entire content and disclosure of which is incorporated herein by reference.
[0002] The present disclosure relates to semiconductor devices. More particularly, the present disclosure relates to forming gate structures and interconnects to semiconductor devices.
[0003] Field effect transistors (FETs) are the basic building block of today's integrated circuits (ICs). Such transistors can be formed in conventional bulk semiconductor substrates (such as silicon) or in a SOI layer of a semiconductor-on-insulator (SOI) substrate. In order to be able to make ICs, such as memory, logic, and other devices, of higher integration density than currently feasible, one has to find ways to further downscale the dimensions of field effect transistors (FETs), such as metal-oxide-semiconductor field effect transistors (MOSFETs) and complementary metal oxide semiconductors (CMOS). Scaling achieves compactness and improves operating performance in devices by shrinking the overall dimensions and operating voltages of the device, while maintaining the device's electrical properties.
[0004] The present disclosure provides a method for forming a semiconductor device that includes forming a first sacrificial stack and a second sacrificial stack on a semiconductor substrate. The first sacrificial stack and the second sacrificial stack each include a gate dielectric layer. The first sacrificial stack is present in a first device region of the semiconductor substrate between an n-type source region and an n-type drain region, and the second sacrificial stack is present in a second device region of the semiconductor substrate between a p-type source region and a p-type drain region. An interlevel dielectric is formed having an upper surface that is coplanar with an upper surface of the first sacrificial stack and the second sacrificial stack. A portion of the first sacrificial stack and the second sacrificial stack is then removed to expose the gate dielectric layer.
[0005] A p-type work function metal layer is formed on the gate dielectric layer. A via is formed to each of the n-type source region, the n-type drain region, the p-type source region and the p-type drain region. The p-type work function metal layer is removed from the first device region, wherein the p-type work function metal layer remains in the second device region. Forming a metal layer comprising titanium and aluminum is then formed on the gate dielectric layer in the first device region, the n-type source region, the n-type drain region, the p-type work function metal layer in the second device region, the p-type source region and the p-type drain region. A metal fill comprising aluminum is formed on the metal layer comprising titanium and aluminum.
[0006] In another aspect, an electrical device is provided that includes an n-type semiconductor device having a first gate structure in a first device region of a semiconductor substrate that is between a first source region and a first drain region. The first gate structure includes a gate dielectric that is present on the substrate, a metal layer comprising titanium and aluminum, and a metal fill comprised of aluminum. The electrical device also includes a p-type semiconductor device including a second gate structure in a second device region of a semiconductor substrate that is between a second source region and a second drain region. The second gate structure includes a gate dielectric that is present on the substrate, a p-type work function adjustment metal layer, a metal layer comprising titanium and aluminum, and a metal fill comprised of aluminum. The electrical device also includes an interlevel dielectric that is present over the substrate. The interlevel dielectric comprises interconnects to the first source region, the first drain region, the second source region and the second drain region. The interconnects are comprised of a metal layer comprising titanium and aluminum, and a metal fill comprised of aluminum.
DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0007] The following detailed description, given by way of example and not intended to limit the invention solely thereto, will best be appreciated in conjunction with the accompanying drawings, wherein like reference numerals denote like elements and parts, in which:
[0008] FIG. 1 is a side cross-sectional view depicting forming a gate dielectric layer on a semiconductor substrate, in which the gate dielectric layer is composed of a high-k dielectric layer and a metal nitride gate dielectric layer, in accordance with one embodiment of the present invention.
[0009] FIG. 2 is a side cross-sectional view depicting forming a first sacrificial stack and a second sacrificial stack on a semiconductor substrate, in accordance with one embodiment of the present invention.
[0010] FIG. 3 is a side cross-sectional view depicting forming an interlevel dielectric having an upper surface that is coplanar with an upper surface of the first sacrificial stack and the second sacrificial stack, in accordance with one embodiment of the present invention.
[0011] FIG. 4 is a side cross-sectional view depicting removing a portion of the first sacrificial stack and the second sacrificial stack to expose the gate dielectric layer, and forming a p-type work function metal layer on the gate dielectric layer, in accordance with one embodiment of the present invention.
[0012] FIG. 5 is a side cross-sectional view depicting forming a via to each of the first source region, the first drain region, the second source region and the second drain region, in accordance with one embodiment of the present invention.
[0013] FIG. 6 is a side cross-sectional view depicting removing the p-type work function metal from the gate dielectric in the first device region, wherein the p-type work function metal remains in the second device region, in accordance with one embodiment of the present invention.
[0014] FIG. 7 is a side cross-sectional view depicting forming a metal layer composed of titanium and aluminum on the gate dielectric layer in the first device region, the first source region, the first drain region, the p-type work function metal in the second device region, the second source region and the second drain region, and forming a metal fill composed of aluminum on the metal layer that is composed of titanium and aluminum, in accordance with one embodiment of the present invention.
[0015] Detailed embodiments of the present invention are disclosed herein; however, it is to be understood that the disclosed embodiments are merely illustrative of the invention that may be embodied in various forms. In addition, each of the examples given in connection with the various embodiments of the invention is intended to be illustrative, and not restrictive. Further, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the present invention.
[0016] References in the specification to "one embodiment", "an embodiment", "an example embodiment", etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
[0017] For purposes of the description hereinafter, the terms "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom", and derivatives thereof shall relate to the invention, as it is oriented in the drawing figures. The terms "overlying", "atop", "positioned on" or "positioned atop" mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure may be present between the first element and the second element. The term "direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.
[0018] The present disclosure relates to structures and methods for forming complementary metal oxide semiconductor (CMOS) devices, in which the gate structures to the semiconductor devices and the contacts to the source and drain regions of the semiconductor devices include a metal layer composed of titanium and aluminum and a metal fill composed of aluminum. In one embodiment, the metal layer that is composed of titanium and aluminum is present in the gate structure of an n-type semiconductor device and provides a work function that results in a threshold voltage shift of the n-type semiconductor device. The p-type semiconductor device may further include a p-type work function metal.
[0019] Reference is first made to FIG. 1, which depicts forming a gate dielectric layer 10 on a semiconductor substrate 5. In one embodiment, the semiconductor substrate 5 comprises a semiconductor-on-insulator substrate (SOI) which includes a bottom semiconductor-containing layer 12, a buried insulating layer 13 present atop the bottom semiconductor-containing layer 12, and top semiconductor-containing layer (i.e., SOI layer) 14 present atop the surface of the buried insulating layer 13. In one embodiment, the bottom and top semiconductor-containing layers 12, 14 are composed of a Si-containing material.
[0020] The term "Si-containing material" as used herein denotes any semiconductor material that includes silicon. Illustrative examples of various Si semiconductor materials that can be employed in the present invention include, but are not limited to: Si, SiGe, SiGeC, SiC and other like Si-containing materials. Combinations of the aforementioned semiconductor materials can also be used as the Si-containing layers of the SOI substrate.
[0021] The top semiconductor-containing layer (hereinafter referred to as the SOI layer) 14 may have a thickness ranging from 20.0 nm to 70.0 nm. The buried insulating layer 13 is typically a buried oxide region, which may have a thickness ranging from 150.0 nm to 200.0 nm. The thickness of the bottom semiconductor-containing layer 12 typically ranges from ranging from 150.0 nm to 200.0 nm.
[0022] The semiconductor substrate 5 shown in FIG. 1 may be formed by a thermal bonding process, or by an oxygen implantation process, which is referred to in the art as a separation by implantation of oxygen (SIMOX). In another embodiment, the semiconductor substrate 5 that is depicted in FIG. 1 may be a bulk semiconductor-containing substrate, such as bulk silicon.
[0023] An isolation region 11 may be formed in the semiconductor substrate 5, which may provide the boundary between a first device region 6 and a second device region 7. In one embodiment, the first device region 6 provides the site for a subsequently formed p-type semiconductor device, and the second device region 7 provides the site for a subsequently formed n-type semiconductor device. The term "semiconductor device" refers to an intrinsic semiconductor material that has been doped, i.e., into which a doping agent has been introduced, giving it different electrical properties than the intrinsic semiconductor. Doping involves adding dopant atoms to an intrinsic semiconductor, which changes the electron and hole carrier concentrations of the intrinsic semiconductor at thermal equilibrium. Dominant carrier concentrations in an extrinsic semiconductor classify it as either an n-type or p-type semiconductor. As used herein, "p-type semiconductor" refers to the addition of trivalent impurities to a semiconductor material that create deficiencies of valence electrons, such as boron, aluminum or gallium to an intrinsic silicon substrate. As used herein, "n-type semiconductor" refers to the addition of pentavalent impurities to a semiconductor substrate that contribute free electrons, such as antimony, arsenic or phosphorous to an intrinsic Si substrate.
[0024] The isolation region 11 may be a shallow trench isolation (STI) region formed by etching a trench into at least the SOI layer of the substrate 5. In some embodiments, and as shown, the trench has a bottom surface that contacts an upper surface of the buried insulating layer 13. The etching step may be performed utilizing a dry etching process, such as reactive-ion etching, ion beam etching, laser ablation or any combination thereof. Chemical vapor deposition (CVD) or another like deposition process can be used to fill the trench with an STI dielectric material, such as a high-density plasma (HDP) oxide or TEOS (tetraethylorthosilicate). The isolation region 11 may also be formed by local oxidation (LOCOS) or by an oxide mesa formation process.
[0025] The gate dielectric layer 10 shown in FIG. 1 is formed on the semiconductor substrate 5. The gate dielectric layer 10 may be composed of any dielectric including, but not limited to: SiO2; Si3N4; SiON; temperature sensitive high-k dielectrics such as TiO2, Al2O3, ZrO2, HfO2, Ta2O5, La2O3; and other like oxides including perovskite-type oxides. In one embodiment, the gate dielectric layer 10 may be formed by a thermal growth process such as, for example, oxidation, nitridation or oxynitridation. The gate dielectric layer 10 may also be formed by a deposition process such as, for example, chemical vapor deposition (CVD), plasma-assisted CVD, metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), evaporation, reactive sputtering, chemical solution deposition and other like deposition processes.
[0026] In one embodiment, the gate dielectric layer 10 is a multi-layered structure that is composed of a high-k dielectric layer 8 and a metal nitride gate dielectric 9. The high-k dielectric layer 8 may be formed by a thermal growth process such as, for example, oxidation, nitridation or oxynitridation. The high-k dielectric layer 8 may also be formed by a deposition process such as, for example, chemical vapor deposition (CVD). Chemical Vapor Deposition (CVD) is a deposition process in which a deposited species is formed as a results of chemical reaction between gaseous reactants at an elevated temperature (typically being greater than 600° C.), wherein solid product of the reaction is deposited on the surface on which a film, coating, or layer of the solid product is to be formed. Variations of CVD processes include, but are not limited to, Atmospheric Pressure CVD (APCVD), Low Pressure CVD (LPCVD) and Plasma Enhanced CVD (EPCVD), Metal-Organic CVD (MOCVD) and others.
[0027] The high-k dielectric layer 8 may be composed of an oxide, a nitride, an oxynitride or combinations and multi-layers thereof. A high-k dielectric is a material having a dielectric constant that is greater than the dielectric constant of silicon oxide. In one embodiment, the high-k dielectric layer 8 is comprised of a high-k dielectric material having a dielectric constant greater than about 4.0, e.g., 4.1. In another embodiment, the high-k dielectric layer 8 is comprised of a high-k dielectric material having a dielectric constant greater than 7.0. In yet another embodiment, the high-k dielectric layer 8 is comprised of a high-k dielectric material having a dielectric constant ranging from greater than 4.0 to 30. The dielectric constants mentioned herein are relative to a vacuum.
[0028] Some examples of high-k dielectric materials suitable for the high-k dielectric layer 8 include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate and combinations thereof. In one example, the high-k dielectric layer 8 has a thickness ranging from 1.0 nm to 10.0 nm. In another example, the high-k dielectric layer 8 may have a thickness ranging from 2.5 nm to 5.0 nm. In one embodiment, the high-k dielectric layer 8 is hafnium oxide (HfO2).
[0029] The metal nitride gate dielectric 9 is formed in direct contact with an upper surface of the high-k dielectric layer 8, and in some embodiments protects the high-k dielectric layer 8 from being damaged during later process steps. In one embodiment, the metal nitride gate dielectric 9 is composed of WN, WSiN, TiN, TiSiN, TaN, TaSiN, TiTaN, TaRuN or combinations thereof. The metal nitride gate dielectric 9 can be deposited using chemical vapor deposition (CVD), sputtering or plating. In one embodiment, the metal nitride gate dielectric 9 is composed of TiN and is deposited using sputtering. In one example, a metal nitride gate dielectric 9 composed of TiN is sputtered from a solid titanium target, in which the nitrogen content of the metal nitride layer is introduced by a nitrogen gas. In another example, a metal nitride gate dielectric 9 composed of TiN is sputtered from a solid target comprised of titanium and nitrogen. The metal nitride gate dielectric 9 typically has a thickness ranging from 1 nm to 10 nm, with a thickness ranging from 2.5 nm to 5 nm being more typical.
[0030] FIG. 2 depicts forming a first sacrificial stack 15 and a second sacrificial stack 20 on the semiconductor substrate 5. The first and second sacrificial stacks 15, 20 may be formed by first blanket depositing a layer of semiconductor-containing material 16 atop the metal nitride gate dielectric 9. The semiconductor-containing material 16 is typically a silicon-containing material, but any semiconductor is suitable for the material being deposited atop the metal nitride gate dielectric 9. Further, other non-semiconductor materials have been contemplated as a place keeping material for the first sacrificial stack 15 and the second sacrificial stack 20, so long as the non-semiconductor material may be removed selectively to the underlying gate dielectric layer 10. In one embodiment, the semiconductor-containing material 16 may be polysilicon.
[0031] The semiconductor-containing material 16 may be formed using a deposition process, including but not limited to: low pressure chemical vapor deposition or room temperature chemical vapor deposition. The semiconductor-containing material 16 may have a thickness ranging from 80.0 nm to 200.0 nm. In another embodiment, the semiconductor-containing material 16 may have a thickness ranging from 100.0 nm to 175.0 nm.
[0032] A hard mask dielectric layer 17 may then be formed on an upper surface of the semiconductor-containing material 16. The hard mask dielectric layer 17 may be composed of a nitride, oxide or oxynitride material. The hard mask dielectric layer 17 may be deposited by chemical vapor deposition (CVD). Variations of CVD processes suitable for depositing the hard mask dielectric layer 17 include, but are not limited to, Atmospheric Pressure CVD (APCVD), Low Pressure CVD (LPCVD) and Plasma Enhanced CVD (EPCVD), Metal-Organic CVD (MOCVD) and combinations thereof.
[0033] The first sacrificial stack 15 and the second sacrificial stack 20 are then formed from the deposited layers of hard mask dielectric layer 17 and the semiconductor-containing layer 16 using photolithography and etching. More specifically, a pattern is produced by applying a photoresist to the surface to be etched, exposing the photoresist to a pattern of radiation; and then developing the pattern into the photoresist utilizing a resist developer. Once the patterning of the photoresist is completed, the sections covered by the photoresist are protected while the exposed regions are removed using a selective etching process that removes the unprotected regions. The term "selective" in reference to a material removal process denotes that the rate of material removal for a first material is greater than the rate of removal for at least another material of the structure to which the material removal process is being applied. The patterned resist is then removed using an O2 ash process, or the patterned resist may be stripped using a wet chemical process.
[0034] Still referring to FIG. 2, at least one spacer 18 may be formed on the sidewall of each of the first and second sacrificial stacks 15, 20 using deposition and etch processes. In one embodiment, the at least one spacer 18 has a width measured at the base of the at least one spacer 18 ranging from 3 nm to 40 nm. In another embodiment, the at least one spacer 18 has a width measured at the base of the at least one spacer 18 ranging from 5.0 nm to 20.0 nm. The at least one spacer's 18 width may taper, i.e., may reduce, in the direction from the semiconductor substrate 5 towards the upper surface of the first sacrificial stack 15 and the second sacrificial stack 20.
[0035] The at least one spacer 18 may be comprised of a dielectric material, such as a nitride, e.g., silicon nitride. In one embodiment, the at least one spacer 18 may be comprised of a low-k dielectric material, which typically has a dielectric constant that is less than 4.0, e.g., 3.9. In one embodiment, the at least one spacer 18 is comprised of a low-k dielectric material having a dielectric constant ranging from 1.75 to 3.5. Examples of materials suitable for low-k dielectric spacers include organosilicate glass (OSG), fluorine doped silicon dioxide, carbon doped silicon dioxide, porous silicon dioxide, porous carbon doped silicon dioxide, spin-on organic polymeric dielectrics (e.g., SILK®), spin-on silicone based polymeric dielectric (e.g., hydrogen silsesquioxane (HSQ) and methylsilsesquioxane (MSQ), and combinations thereof.
[0036] Following the formation of the at least one spacer 18, source regions 21 and drain regions 22 are formed in the upper semiconductor-containing layer 14. A drain region 22 is the doped region in semiconductor device that is located at the end of the channel, in which carriers are flowing out of the transistor. The source region 21 is the doped region in the semiconductor device, in which majority carriers are flowing into the channel. The channel is the region underlying the subsequently formed gate structure and between the source region 21 and the drain region 22 of a semiconductor device that becomes conductive when the semiconductor device is turned on. In one embodiment, the source and drain regions 21, 22 of the semiconductor device include extension source and drain regions, deep source and drain regions (not shown), and halo regions (not shown).
[0037] Still referring to FIG. 2, source and drain regions 21, 22 are formed using an ion implantation process. P-type source extension regions for a p-type semiconductor device are typically produced with group III-A elements and n-type source extension regions for an n-type semiconductor device are typically produced with group V elements. In the case of the p-type implants, a typical impurity species is boron or BF2. Boron with an energy of 0.2 keV to 3.0 keV or BF2 with an energy of 1.0 keV to 15.0 keV and a dose of 5×1013 atoms/cm2 to about 3×1016 atoms/cm2can be used to implant the p-type region. A typical implant for the n-type regions is arsenic. The n-type regions can be implanted with arsenic using an energy of 0.5 keV to 5.0 keV with a dose of 3×1013 atoms/cm2 to 3×1016 atoms/cm2. Deep source and drain regions are typically the same conductivity as their corresponding source and drain extensions regions, but typically have a greater dopant concentration and are implanted with a higher energy. Halo regions are typically formed using an angled implant and have an opposite conductivity as their corresponding source and drain extensions regions.
[0038] Although not depicted in the supplied figures, tensile strain inducing wells may be formed within the source and drain regions 21, 22 of the nFET devices, and compressive strain inducing wells may be formed within the source and drain regions 21, 22 of the pFET devices. In a first process step, a recess is formed within the portion of the upper semiconductor-containing layer 14, in which the source and drain regions 21, 22 are positioned. The recess may be formed using photolithography and etching.
[0039] Tensile strain inducing wells may be provided by silicon that is doped with carbon (Si:C), which may be epitaxially grown atop the recessed surface of the upper semiconductor-containing layer 14 that is overlying the source and drain regions 21, 22 having n-type conductivity within the second device region 7. The epitaxially grown Si:C is under an internal tensile strain (also referred to as an intrinsic tensile strain), in which the tensile strain is produced by a lattice mismatch between the smaller lattice dimension of the epitaxially grown Si:C, and the larger lattice dimension of the recessed surface of the upper semiconductor-containing layer 14 on which the Si:C is epitaxially grown, such as silicon. The internal tensile stress produced by the lattice mismatch may be induced upon the channel region of the subsequently formed n-type semiconductor device to produce a strain induced performance enhancement.
[0040] Compressive strain inducing wells may be positioned within the source and drain regions 21, 22 having the p-type conductivity. The compressive strain inducing wells may be composed of intrinsically compressive SiGe that has been epitaxially grown atop the recessed surface of the upper semiconductor-containing layer 14. The compressive strain inducing wells produce a compressive strain within the device channel of the subsequently formed p-type semiconductor device. The compressive strain is produced by a lattice mismatch between the larger lattice dimension of the epitaxially grown SiGe, and the smaller lattice dimension of the recessed surface of the upper semiconductor-containing layer 14 on which the SiGe is epitaxially grown, such as silicon.
[0041] In one embodiment, the tensile strain inducing wells and the compressive strain inducing wells encroach underneath the at least one sidewall spacer 18 that abuts the first and second sacrificial stack 15, 20. By positioning the tensile and compressive strain inducing wells closer to the device channel, the strain produced along the device channel is increased.
[0042] Silicide regions (not shown) may be formed atop the source and drain regions 21, 22. Silicide formation typically requires depositing a metal layer onto the surface of a Si-containing material or wafer. The metal layer may be deposited by at least one of chemical vapor deposition (CVD), plasma-assisted CVD, high-density chemical vapor deposition (HDCVD), plating, sputtering, evaporation and chemical solution deposition. Metals deposited for silicide formation include Ta, Ti, W, Pt, Co, Ni, and combinations thereof. Following deposition, the structure is then subjected to an annealing step, which may include rapid thermal annealing. During annealing, the deposited metal reacts with Si forming a metal silicide.
[0043] An interlevel dielectric layer 30 can be deposited atop the entire semiconductor substrate 5 and planarized by chemical mechanical polishing (CMP) or like process until the top surface of the first and second sacrificial stack 15, 20 is exposed. The interlevel dielectric layer 30 may be selected from the group consisting of silicon-containing materials such as SiO2, Si3N4, SiOxNy, SiC, SiCO, SiCOH, and SiCH compounds; the above-mentioned silicon-containing materials with some or all of the Si replaced by Ge; carbon-doped oxides; inorganic oxides; inorganic polymers; hybrid polymers; organic polymers such as polyamides or SiLK®; other carbon-containing materials; organo-inorganic materials such as spin-on glasses and silsesquioxane-based materials; and diamond-like carbon (DLC, also known as amorphous hydrogenated carbon, α-C:H). Additional choices for the interlevel dielectric layer 30 include: any of the aforementioned materials in porous form, or in a form that changes during processing to or from being porous and/or permeable to being non-porous and/or non-permeable. The blanket layer of the interlevel dielectric layer 30 may be formed by deposition processes, including, but not limited to spinning from solution, spraying from solution, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), sputter deposition, reactive sputter deposition, ion-beam deposition, and evaporation.
[0044] The blanket deposited interlevel dielectric layer 30 is then planarized until the upper surface of the first sacrificial stack 15 and the second sacrificial stack 20 is exposed, wherein the upper surface of the first and second sacrificial stack 15, 20 is coplanar with an upper surface of the interlevel dielectric layer 30. Planarization is a material removal process that employs at least mechanical forces, such as frictional media, to produce a planar surface. One example of planarization is chemical mechanical planarization (CMP). Chemical mechanical planarization (CMP) is a material removal process using both chemical reactions and mechanical forces to remove material and planarize a surface. Referring to FIG. 3, in one embodiment, the interlevel dielectric layer 30 is planarized until the hard mask dielectric layer 17 of the first and second sacrificial stack 15, 20 has been removed, and the upper surface of the semiconductor-containing material 16 of the first and second sacrificial stack 15, 20 has been exposed. The planarization of the interlevel dielectric layer 30 may also remove an upper surface of the at least one spacer 18. In some examples, following planarization, the upper surface of the semiconductor-containing material 16 is coplanar with an upper surface of the interlevel dielectric layer 30 and an upper surface of the at least one spacer 18.
[0045] FIG. 4 depicts one embodiment of removing a portion of the first sacrificial stack and the second sacrificial stack to expose the gate dielectric layer 10, and forming a p-type work function metal layer 25 on the gate dielectric layer 10. In embodiments in which the hard mask dielectric layer 17 is present following planarization of the interlevel dielectric layer 30, the hard mask dielectric layer 17 and the semiconductor-containing material 16 may be removed by an etch process that is selective to the gate dielectric layer 10. In one example, in which the hard mask dielectric layer 17 is removed by the planarization process that was applied to the interlevel dielectric layer 30, the semiconductor-containing material 16 may be removed using a wet or dry etch process, which is selective to the gate dielectric layer 10, e.g., the metal nitride gate dielectric layer 9 of the gate dielectric 10. For example, a semiconductor-containing layer 16 that is composed of polysilicon may be removed using bromide gas etch chemistries, i.e., HBr, having a high selectivity to a metal nitride gate dielectric layer 9 that is composed of TiN.
[0046] In one embodiment, the p-type work function metal layer 25 is conformally deposited in the first device region 6 and the second device region 7 of the semiconductor substrate 5, in which the p-type work function metal layer 25 is deposited over the gate dielectric layer 10 and the interlevel dielectric layer 30. As used herein, a "p-type work function metal layer 25" is a metal layer that effectuates a p-type threshold voltage shift. In one embodiment, the work function of the p-type work function metal layer 25 ranges from 4.9 eV to 5.2 eV. As used herein, "threshold voltage" is the lowest attainable gate voltage that will turn on a semiconductor device, e.g., transistor, by making the channel of the device conductive. The term "p-type threshold voltage shift" as used herein means a shift in the Fermi energy of a p-type semiconductor device towards a valence band of silicon in the silicon containing substrate of the p-type semiconductor device. A "valence band" is the highest range of electron energies where electrons are normally present at absolute zero. In one embodiment, the p-type work function metal layer 25 is composed of TiN. Other materials that are suitable for providing the p-type work function metal layer 25 include TaC, TaNC, Ru, and TiNi.
[0047] In one embodiment, forming the p-type work function metal layer 25 on the gate dielectric layer 10 in the first device region 6 and the gate dielectric layer 10 in the second device region 7 includes depositing an etch stop metal nitride layer 26 on the metal nitride gate dielectric layer 9 in the first device region 6 and the second device region 7. The p-type work function metal layer 25 is then deposited on the etch stop metal nitride layer 26 in the first device region 6 and the second device region 7. A thermal dielectric 27 may then be formed on the p-type work function metal layer 25 in the first device region 6 and the second device region 7.
[0048] In one embodiment, the etch stop metal nitride layer 26 is composed of TaN. Other materials that are suitable for the etch stop metal nitride layer 26 include WN, WSiN, TiN, TiSiN, TaSiN, TiTaN, TaRuN or combinations thereof. In one embodiment, the etch stop metal nitride layer 26 is deposited in direct contact with the TiN metal nitride gate dielectric layer 9 using chemical vapor deposition (CVD/p-CVD/ALD), sputtering or plating. In one example, a etch stop metal nitride layer 26 composed of TaN is sputtered from a solid tantalum target, in which the nitrogen content of the etch stop metal nitride layer 26 is introduced by a nitrogen gas. In another example, a etch stop metal nitride layer 26 composed of TaN is sputtered from a solid target comprised of tantalum and nitrogen. In one example, the etch stop metal nitride layer 26 has a thickness ranging from 1 nm to 10 nm. In another example, the etch stop metal nitride layer 26 has a thickness ranging from 2.5 nm to 5 nm.
[0049] The p-type work function metal layer 25 composed of TiN may be deposited in direct contact with the metal nitride etch stop layer 26 composed of TaN using chemical vapor deposition (CVD/p-CVD/ ALD), sputtering or plating. In one example, a p-type work function metal layer 25 composed of TiN may be deposited using sputtering. The p-type work function metal layer 25 composed of TiN may be sputtered from a solid titanium target, in which the nitrogen content of the p-type work function metal layer 25 is introduced by a nitrogen gas. In another example, a p-type work function metal layer 25 composed of TiN is sputtered from a solid target comprised of titanium and nitrogen. In one example, the p-type work function metal layer 25 has a thickness ranging from 1 nm to 10 nm. In another example, the p-type work function metal layer 25 has a thickness ranging from 2.5 nm to 5 nm.
[0050] The thermal dielectric 27 may then be formed in direct contact with the p-type work function metal layer 25 using a thermal growth process. The thermal dielectric 27 may be composed of a thermally grown oxide, such as silicon oxide. In another embodiment, the thermal dielectric 27 may be composed of a thermally grown nitride, such as silicon oxynitride. The thickness of the thermal dielectric 27 typically ranges from 1 nm to 10 nm. In another embodiment, the thickness of the thermal dielectric 27 ranges from 2.5 nm to 5 nm.
[0051] FIG. 5 depicts forming via 23 though the interlevel dielectric layer 30 to each of the source and drain regions 21, 22. The vias 23 are formed using deposition, photolithography and etch process steps. In one embodiment, a first block mask is formed using deposition and photolithography atop the interlevel dielectric layer 30, in which openings in the first block mask expose the areas in which the vias 23 are to be formed. For example, a layer of photoresist 24 is deposited atop the entire structure. The photoresist layer 24 may be comprised of dielectrics including carbon, oxygen, and various inorganic metals. The photoresist layer 24 may be selectively patterned and developed to form a first block mask, protecting at least one first region of the interlevel dielectric layer 30 and exposing at least one second region of the interlevel dielectric layer 30 in which the vias 23 are subsequently formed. The vias 23 are etched into the interlevel dielectric 30 using a selective etch process. In one embodiment, the vias 23 are etched using an anisotropic etch. An anisotropic etch process is a material removal process in which the etch rate in the direction normal to the surface to be etched is much higher than in the direction parallel to the surface to be etched. In one embodiment, the vias 23 are formed using reactive ion etching (RIE). Reactive ion etching (RIE) is a form of plasma etching that during etching the surface to be etched is placed on the RF powered electrode, wherein the surface to be etched takes on a potential that accelerates the etching species extracted from a plasma toward the surface, to be etched in which the chemical etching reaction is taking place in the direction normal to the surface.
[0052] In one embodiment, during via 23 formation a portion of the p-type work function metal layer 25 that is overlying the source region 21 and the drain region 22 is removed. More specifically, a selective etch process can be employed to remove the exposed portion of the interlevel dielectric 30 selective to the p-type work function metal layer 25. Thereafter, the p-type work function metal layer 25 may be removed selective to the interlevel dielectric 30. The interlevel dielectric 30 is then etched selectively to the upper surface of the source and drain regions 21, 22, e.g., the upper surface of the silicide contacts (not shown) that are formed atop the source and drain regions 21, 22. Following the formation of the vias 23, the photoresist 24 is removed using oxygen ashing, a chemical strip or selective etching.
[0053] FIG. 6 depicts removing the p-type work function metal layer 25 from the gate dielectric 10 in the first device region 6, wherein the p-type work function metal layer 25 remains in the second device region 7. In one embodiment, removing the p-type work function metal layer 25 includes forming a second block mask (not shown) overlying at least the second device region 7. In one embodiment, the block mask is also formed over the p-type work function metal layer 25 that is present on an upper surface of the interlevel dielectric 30 in the first device region 6.
[0054] The second block mask may comprise soft and/or hard mask materials and can be formed using deposition, photolithography and etching. In one embodiment, the second block mask is composed of a photoresist. A second block mask can be produced by applying a photoresist layer to the surface of the semiconductor substrate 5, exposing the photoresist layer to a pattern of radiation, and then developing the pattern into the photoresist layer utilizing a resist developer.
[0055] In another embodiment, the second block mask can be a hard mask material. Hard mask materials include dielectric systems that may be deposited by chemical vapor deposition (CVD/ALD) and related methods. Typically, the hard mask composition includes silicon oxides, silicon carbides, silicon nitrides, and silicon carbonitrides, etc. Spin-on dielectrics may also be utilized as a hard mask material including, but not limited to: silsequioxanes, siloxanes, and boron phosphate silicate glass (BPSG). A second block mask comprising a hard mask material may be formed by blanket depositing a layer of hard mask material, providing a patterned photoresist atop the layer of hard mask material, and then etching the layer of hard mask material to provide a block mask protecting at least the second device region 7, wherein at least the portion of the p-type work function metal layer 25 overlying the gate dielectric 10 is exposed.
[0056] Following the formation of the second block mask, the p-type work function metal layer 25 is removed from the gate dielectric 10 in the first device region 6 by a selective etch process. More specifically, removing the p-type work function metal layer 25 begins with a first etch chemistry for removing the thermal dielectric layer 27 from the first device region 6 that is selective to the p-type work function metal layer 25. In some embodiments, the thermal dielectric layer 27 is removed from both the first and second device region 6, 7 prior to the formation of the second block mask. In a following process step, the p-type type work function metal layer 25 is etched selective to the gate dielectric 10, wherein the p-type work function metal layer 25 remains atop the gate dielectric 10 in the first device region 6. More specifically, the p-type work function metal layer 25 is etched selective to the metal nitride gate dielectric 9. In some embodiments, the p-type work function metal layer 25 is removed by an etch that is selective to the etch stop metal layer 26, wherein in a following process step the etch stop metal layer 26 may be removed by an etch that is selective to the metal nitride gate dielectric 9. During the etch processes that removes the p-type work function metal layer 25 from the first device region 6, the second device region 7 is protected by the second block mask. The p-type work function metal layer 25 may be removed using an anisotropic etch or an isotropic etch. The anisotropic etch may be provided by reactive ion etching or laser etching. The isotropic etch may be provided by a wet chemical etch.
[0057] In some embodiments, following removal of the p-type work function metal layer 25, the second block mask may be removed. In the embodiments, in which the second block mask is composed of a photoresist material, the second block mask may be removed using oxygen ashing or a chemical strip. In embodiments in which the second block mask is composed of a hard mask dielectric, the second block mask is removed using a selective etch process.
[0058] In some embodiments in which the thermal dielectric layer 27 is still present in the second device region 7 while the p-type work function metal layer 25 is removed from the first device region 6, the thermal dielectric layer 27 may be removed following the removal of the second block mask. The thermal dielectric layer 27 may be removed using an etch that is selective to at least the p-type work function metal layer 25 in the second device region 7 and the gate dielectric layer 10 in the first device region 6.
[0059] FIG. 7 depicts one embodiment of forming a metal layer 28 composed of titanium and aluminum in the first device region 6 and the second device region 7. In one embodiment, the metal layer 28 comprising titanium and aluminum is an n-type work function metal layer. In one embodiment, the work function of the n-type work function metal layer ranges from 4.1 eV to 4.3 eV. As used herein, a "n-type work function metal layer" is a metal layer that effectuates an n-type threshold voltage shift. "N-type threshold voltage shift" as used herein means a shift in the Fermi energy of an n-type semiconductor device towards a conduction band of silicon in a silicon-containing substrate of the n-type semiconductor device. The "conduction band" is the lowest lying electron energy band of the doped material that is not completely filled with electrons.
[0060] In the first device region 6, the metal layer 28 composed of titanium and aluminum is deposited on the gate dielectric layer 10, the source region 21 and the drain region 22. More specifically, in one embodiment, the metal layer 28 composed of titanium and aluminum is deposited in direct contact with the metal nitride gate dielectric 9 of the gate dielectric layer 10. In the second device region 7, the metal layer 28 composed of titanium and aluminum is deposited in direct contact with the p-type work function metal layer 25 and is in direct contact with the source region 21 and the drain region 22.
[0061] In some examples, the metal layer 28 composed of titanium and aluminum is blanket deposited on the first device region 6 and the second device region 7, in which the titanium and aluminum containing metal layer 28 is present on the upper surface of the structure in the first device region 6 that is between the vias 23 to the source and drain regions 21, 22 and the gate dielectric 10. The metal layer 28 composed of titanium and aluminum may also be present on the sidewall of the vias 23 and the sidewall of the structure, e.g., interlevel dielectric 30, that is leading to the gate dielectric 10 in the first device region 6 and/or the p-type work function metal layer 25 in the second device region 7. The metal layer 28 composed of titanium and aluminum may have a thickness ranging from 1 nm to 20 nm. In another embodiment, the thickness of the metal layer 28 composed of titanium and aluminum ranges from 5 nm to 10 nm.
[0062] In one embodiment, the metal layer 28 comprising titanium and aluminum may be deposited by a physical vapor deposition (PVD) method, such as sputtering. As used herein, "sputtering" means a method for depositing a film of metallic material, in which a target of the desired material, i.e., source, is bombarded with particles, e.g., ions, which knock atoms from the target, where the dislodged target material deposits on a deposition surface. Examples of sputtering apparatus that may be suitable for depositing the metal layer 28 comprising titanium and aluminum include DC diode type systems, radio frequency (RF) sputtering, magnetron sputtering, and ionized metal plasma (IMP) sputtering. In addition to physical vapor deposition (PVD) techniques, the metal layer 28 comprising titanium and aluminum may also be formed using chemical vapor deposition (CVD) and atomic layer deposition (ALD).
[0063] In one embodiment, the metal layer 28 comprising titanium and aluminum may be composed of titanium aluminum nitride (TiAlN). In one example, the titanium content of the titanium aluminum nitride may range from 20 wt % to 80 wt %, the aluminum content of the titanium aluminum nitride may range from 20 wt % to 60 wt %, and the nitrogen content of the titanium aluminum nitride may range from 20 wt % to 60 wt %. In another example, the titanium content of the titanium aluminum nitride may range from 30 wt % to 60 wt %, the aluminum content of the titanium aluminum nitride may range from 25 wt % to 40 wt %, and the nitrogen content of the titanium aluminum nitride may range from 25 wt % to 50 wt %.
[0064] In one embodiment, a sputtering deposition process for depositing titanium aluminum nitride (TiAlN) includes applying high energy particles to strike a solid slab of a titanium aluminum alloy target material, in which the high energy particles physically dislodge atoms of titanium and aluminum to be deposited on the gate dielectric 10 in the first device region 6 and the p-type work function metal layer 25 in the second device region 7. In another embodiment, the sputtering apparatus may include dual targets, e.g., a first target composed of titanium and a second target composed of aluminum. The sputtered atoms of titanium and aluminum typically migrate through a vacuum and deposit on the deposition surface. In one example, the ion energies of the high-energy particles, e.g., positive ions from an argon gas flow discharge range from 500 eV to 5,000 eV. In another embodiment, the ion energies of the high-energy particles range from 1,500 eV to 4,500 eV.
[0065] The source of nitrogen for the titanium aluminum nitride (TiAlN) may be provided by nitrogen gas (N2). The nitrogen source may be introduced to the sputtering chamber as the sputtered atoms of titanium and aluminum are migrating towards the deposition surface, e.g., the gate dielectric 10 in the first device region 6 and the p-type work function metal layer 25 in the second device region 7. In one example, the nitrogen source is provided by co-sputtering from a titanium (Ti) and an aluminum (Al) target in an Ar/N2 gas mixture.
[0066] FIG. 7 further depicts forming a metal fill 29 comprising aluminum on the metal layer 28 comprising titanium and aluminum. In some embodiments, the metal fill 29 is formed in direct contact with the metal layer 28 comprising titanium and aluminum. In one embodiment, the metal fill 29 is composed of 99% aluminum. In another embodiment, the metal fill 29 is composed of 100% aluminum. The metal fill 29 is typically deposited by physical vapor deposition (PVD), such as sputtering. Examples of sputtering apparatus that may be suitable for depositing the metal fill 29 comprising aluminum includes DC diode type systems, radio frequency (RF) sputtering, magnetron sputtering, and ionized metal plasma (IMP) sputtering. In addition to physical vapor deposition (PVD) techniques, the metal fill 29 comprising titanium may also be formed using chemical vapor deposition (CVD) and atomic layer deposition (ALD).
[0067] In one embodiment, a sputtering deposition process for depositing the metal fill 29 that is composed of aluminum includes applying high energy particles to strike a solid slab of high-purity aluminum target material, in which the high energy particles physically dislodge atoms of the aluminum to be deposited on the gate dielectric layer 13. In one example, the ion energies of the high-energy particles, e.g., positive ions from an argon gas flow discharge, range from 500 eV to 5,000 eV. In another embodiment, the ion energies of the high-energy particles range from 1,500 eV to 4,500 eV. In one embodiment, by high-purity aluminum it is meant that the aluminum content of the target material is greater than 99.5%. In some embodiments, the aluminum content of the target material may be as great as 99.9% with a remainder of incidental impurities. "Incidental impurities" denote any contamination of the target, i.e., aluminum. Allowable ranges of impurities are less than 0.05 wt % for each impurity constituent, and 0.1 wt % for total impurity content. The sputtered aluminum atoms from the aluminum target may migrate through a vacuum and deposit on the deposition surface, e.g., the gate dielectric layer 13. In one example, iron (Fe), copper (Cu), and silver (Ag) may be present in less than 5 parts per million (ppm).
[0068] The metal fill comprising aluminum 29 may be planarized until an upper surface of the metal fill 29 is coplanar with an upper surface of the interlevel dielectric 30. In one example, the planarization process is provided by chemical mechanical planarization (CMP). Chemical Mechanical Planarization (CMP) is a material removal process using both chemical reactions and mechanical forces to remove material and planarize a surface. In one embodiment, the planarization process removes the portions of the p-type work function metal layer 25, the thermal dielectric layer 27 and the etch stop metal nitride layer 26 that is present on the upper surface of the interlevel dielectric 30.
[0069] The metal fill 29 comprising aluminum and the metal layer 28 comprising titanium and aluminum that are present in the vias 23 provide the interconnect to the source and drain regions 21, 22 of an n-type semiconductor device 100 and a p-type semiconductor device 105. The metal fill 29 comprising aluminum and the metal layer 28 comprising titanium and aluminum are also present in the gate structure 60 to the p-type semiconductor device 100 and the gate structure 70 to the p-type semiconductor device 105. The term "gate structure" means a structure used to control output current (i.e., flow of carriers in the channel) of a semiconducting device, e.g., memory device, through electrical or magnetic fields.
[0070] More specifically and in one embodiment, the above method provides an electrical device that includes an n-type semiconductor device 100 having a first gate structure 60 in a first device region 6 of a semiconductor substrate 5 that is between a source region 21 and a drain region 22. The first gate structure 60 includes a gate dielectric 10 that is present on the semiconductor substrate 5, a metal layer 28 composed of titanium and aluminum, and a metal fill 29 composed of aluminum. The above method further provides a p-type semiconductor device 105 that is present on the same semiconductor substrate 5 with the n-type semiconductor device 100. The p-type semiconductor device 105 includes a second gate structure 70 in the second device region 7 of the semiconductor substrate 5 that is between a source region 21 and a drain region 22. The second gate structure 70 includes a gate dielectric 10 that is present on the semiconductor substrate 5, a p-type work function metal layer 25, a metal layer 28 comprising titanium and aluminum, and a metal fill 29 comprised of aluminum 28.
[0071] In one embodiment, the metal layer 28 comprising titanium and aluminum that is present in the gate structure 60 of the n-type semiconductor device 100 functions as an n-type work function metal that effectuates an n-type threshold voltage shift in the n-type semiconductor device 100. The work function of the n-type work function metal typically ranges from 4.1 eV to 4.3 eV.
[0072] The second device region 7 includes a p-type work function metal layer 25 that is in direct contact with the gate dielectric 10 of the gate structure 70 to the p-type semiconductor device 105. The p-type work function metal layer 25 effectuates a threshold voltage shift in the n-type semiconductor device 105. In one example, the work function of the p-type work function metal typically ranges from 4.9 eV to 5.1 eV. The metal layer 28 comprising titanium and aluminum that is present in the gate structure 70 of the p-type semiconductor device 105 is separated from the gate dielectric 10 by the p-type work function metal layer 25.
[0073] In one embodiment, the metal layer 28 comprising titanium and aluminum that is present in the gate structure 70 of the p-type semiconductor device 105 is separated from the gate dielectric 10 by a dimension ranging from 1 nm to 10 nm. In another embodiment, the metal layer 28 comprising titanium and aluminum that is present in the gate structure 70 of the p-type semiconductor device 105 is separated from the gate dielectric 10 by a dimension ranging from 3 nm to 8 nm As noted above, in some embodiments, the metal layer 28 comprising titanium and aluminum is an n-type work function metal. By separating the metal layer comprising titanium and aluminum 28 from the gate dielectric 10 of the p-type semiconductor device 105, the n-type threshold voltage shift that can result from the metal layer 28 comprising titanium and aluminum is substantially eliminated in the p-type semiconductor device 105.
[0074] Still referring to FIG. 7, an interlevel dielectric 30 is present over the semiconductor substrate 5 and at least a portion of the n-type and p-type semiconductor devices 100, 105. Interconnects 80 are present through the interlevel dielectric 30 to the source region 21 and drain region 22 in the first device region 6, and to the source region 21 and the drain region 22 in the second device region 7. Each of the interconnects 80 include the metal layer 28 that is composed of titanium and aluminum, and the metal fill 29 that is composed of aluminum. The interconnects 80 that are composed of the metal layer 28 comprised of titanium and aluminum and the metal fill 29 that is composed of aluminum do not require seed layers that are typically employed in conventional copper interconnect structures. Further, in some embodiments of the present method by forming the interconnects 80 with a metal layer 28 comprised of titanium and aluminum, and a metal fill 29 composed of aluminum, and by incorporating those materials into the gate structures 60, 70 of the n-type and p-type semiconductor devices 100, 105, the present structures and methods reduce process complexity and cost.
[0075] While the present invention has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the present invention. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims.
Patent applications by Andrew H. Simon, Fishkill, NY US
Patent applications by Filippos Papadatos, Wappingers Falls, NY US
Patent applications by Keith Kwong Hon Wong, Wappingers Falls, NY US
Patent applications by Michael P. Chudzik, Danbury, CT US
Patent applications by Unoh Kwon, Fishkill, NY US
Patent applications by Zhengwen Li, Wappingers Falls, NY US
Patent applications by International Business Machines Corporation
Patent applications in class Diamond or silicon carbide
Patent applications in all subclasses Diamond or silicon carbide
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2011-06-23 Method for replacement metal gate fill
2012-08-02 Imagers with buried metal trenches and though-silicon vias
2016-05-26 Semiconductor device manufacturing method, and semiconductor device
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2016-04-07 Partial sacrificial dummy gate with cmos device with high-k metal gate
2016-03-31 Diffusion barrier layer formation
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2016-03-24 Constrained nanosecond laser anneal of metal interconnect structures
Top Inventors for class "Active solid-state devices (e.g., transistors, solid-state diodes)"
1 Shunpei Yamazaki
3 Kangguo Cheng
4 Huilong Zhu
5 Chen-Hua Yu


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redpajama_set_name: RedPajamaCommonCrawl


text:
Q: Struts error while deploying application on Tomcat 5.5 I am asking a query which is a duplicate one of getting following struts tile error so apologies for this, I am getting this below error while deploying my application on tomcat 5.5, Please advise how to overcome from this..
    SEVERE: Error configuring application listener of class org.apache.struts2.tiles.StrutsTilesListener
java.lang.ClassNotFoundException: org.apache.struts2.tiles.StrutsTilesListener
    at org.apache.catalina.loader.WebappClassLoader.loadClass(WebappClassLoader.java:1438)
    at org.apache.catalina.loader.WebappClassLoader.loadClass(WebappClassLoader.java:1284)
    at org.apache.catalina.core.StandardContext.listenerStart(StandardContext.java:3743)
    at org.apache.catalina.core.StandardContext.start(StandardContext.java:4252)
    at org.apache.catalina.core.ContainerBase.start(ContainerBase.java:1014)
    at org.apache.catalina.core.StandardHost.start(StandardHost.java:736)
    at org.apache.catalina.core.ContainerBase.start(ContainerBase.java:1014)
    at org.apache.catalina.core.StandardEngine.start(StandardEngine.java:443)
    at org.apache.catalina.core.StandardService.start(StandardService.java:448)
    at org.apache.catalina.core.StandardServer.start(StandardServer.java:700)
    at org.apache.catalina.startup.Catalina.start(Catalina.java:552)
    at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
    at sun.reflect.NativeMethodAccessorImpl.invoke(Unknown Source)
    at sun.reflect.DelegatingMethodAccessorImpl.invoke(Unknown Source)
    at java.lang.reflect.Method.invoke(Unknown Source)
    at org.apache.catalina.startup.Bootstrap.start(Bootstrap.java:295)
    at org.apache.catalina.startup.Bootstrap.main(Bootstrap.java:433)
Oct 1, 2012 2:26:51 PM org.apache.catalina.core.StandardContext listenerStart

The thing is that in my classpath of the project the jar is struts2-tiles-plugin-2.0.9.jar and Shall I use the new one that is struts2-tiles-plugin-2.2.1 will this will solve the problem I am deploying my application on tomcat 5.5

A: Place all required tiles jar files in side your project lib folder.See the below image for your reference.
http://img.viralpatel.net/2009/12/struts2-tiles-jar-files.png

A: Copy all the jar files in your tomcat folder as explained in this link.
The eclipse tomcat plugin puts some configuration (for Eclipse WTP) including classpath definitions into tomcat
for my webapp context, in conf/Catalina/localhost.
This is automatic.
The classpaths include most of the jars but not all of them.
http://struts.1045723.n5.nabble.com/ClassNotFoundException-StrutsTilesListener-td3553672.html

redpajama_set_name: RedPajamaStackExchange


text:
Issue: Mar 1998
The Roots of Aging
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Scientifically reviewed by: Dr. Gary Gonzalez, MD, on January 2021.
International conferences in Australia explored the accumulation of adverse changes that result in aging and increase the risk of death.
By Marilyn Bitomsky
Aging had benn attributed to development, genetic defects, the environment, disease, and other inborn processes. In the developed countries, living conditions are now near optimum, so that aging is now the major risk factor for disease and death after about age 28. This ensures that few reach 100, and-so far-none exceeds about 122 years.
Two international conferences held in Adelaide, Australia, discussed the latest theories and research-the 7th Congress of the International Association of Biomedical Gerontology and Aging Beyond 2000: the World Congress of Gerontology. Many speakers at the first congress also addressed the second. The theories discussed can potentially contribute to the important practical goal of increasing the healthy, useful human life span.
Free Radicals And Spin Traps
According to the free radical theory of aging, cumulative damage caused by oxidative free radicals accounts for the dysfunctions and pathologies seen in aging. John Carney, professor of pharmacology and psychiatry at the University of Kentucky, said there are two kinds of oxidative processes, one of which is part of normal living. Another kind of oxidation is the one that causes disease. According to Carney, this pathological oxidation can be controlled.
He and his colleagues have for the last 15 years been studying compounds called free radical spin traps. In animal studies have shown that the antioxidant spin trapping compound N-tert- butyl-alpha-phenylnitrone (PBN) is effective in preventing oxidative changes. Safety trials are currently being conducted before full-scale clinical trials can begin on patients who have Parkinson's disease or have suffered stroke. In a National Institutes of Health-funded study, Carney is examining the processes of Alzheimer's-associated oxidative stress, since increasing oxidative stress ultimately leads to loss of function. Carney said researchers find themselves recapitulating the mitochondrial hypothesis that Denham Harman first articulated in the 1950s.
Today Harman, convener of the IABG sessions, says much is now known about mitochondria, such as the fact that they are a source of endogenous free radical reactions, which he believes is what kills us. Not everyone is in agreement with this view, although Harman believes available data support it.
A round table discussion among conference participants considered how best to decrease the rate of progression of the superoxide radical with advancing age. According to Harman, it is just like having an X-ray machine inside of us spewing out ionizing radiation. Research conducted by the department of animal biology at Complutense University in Madrid has found that birds produce a small number of superoxide radicals, which may explain why they live comparatively longer than other animals. Akitane Mori, from Okayama University in Japan, described the same feature in the white-footed mouse. These animals divert a smaller fraction of oxygen to the superoxide radical. So, according to Harman, the question remaining is: What can we do to make our mitochondria more like those of mice or birds?
Mitochondrial Aging
The last couple of years have seen major advances in technical knowledge about mitochondrial aging, according to Kenneth Beckman, from the department of molecular and cellular biology at the University of California at Berkeley. For example, a study published in the Proceedings of the National Academy of Sciences (Hutchin T., Cortupassi G., "A mitochondrial DNA clone is associated with increased risk for Alzheimer's disease." 1995 July 18 92[15]: 6892-5) found that the cells of people with Alzheimer's disease show a variant of mitochondrial DNA which is different from those in the general population. For some reason, it appears that there are certain mitochondrial DNA mutations.
Another major technical advance is that there have been several papers on apoptosis (programmed cell death) which showed that mitochondria are involved in that process. A protein in mitochondria called cytochrome C, the terminal electron acceptor of the electron transport chain, appears to be involved in apoptosis, Beckman said. Leakage of cytochrome C from mitochondria occurs during apoptosis. There has been a flurry of papers on that, strengthening the idea that mitochondria are important in aging, he said.
One of the main questions remaining about mitochondrial aging is whether mitochondria are the first component in cellular degeneration. "You can measure many things which deteriorate with age, but that is not evidence of their primary importance," he said.
If a single component of the cell is of primary importance, then this means it is possible to intervene pharmacologically or nutritionally. If you are trying to intervene to improve mitochondrial function and hence the function of the organism as a whole, and the mitochondria are not primary, then you are wasting your time, Beckman believes.
A second question, Beckman said, is whether mitochondrial DNA itself is important. People make the assumption that mitochondrial DNA is damaged and this leads to mitochondrial dysfunction. But this is an extremely weak argument, since there is little evidence for this right now, he said.
A third question relates to improvement of mitochondrial function. Beckman's colleague, Tony Hagen, is studying potential means of improvement. Many of the studies to date have involved homogenization, grinding the tissue into a molecular soup. The problem with that, Beckman said, is that such "grind and find" chemistry may in fact cause oxidative damage. You don't know whether the damage you see occurred before the grinding or afterwards. If iron is present in the tissue, it may cause oxidation of DNA, proteins, and lipids.
One of the main differences he sees between old and young rat livers is that the cells become more heterogeneous with age. Mitochondrial function in particular seems to be very heterogeneous. Hagen is currently experimenting with various compounds to determine whether they have an effect on this heterogeneity. This is not damage per se, but rather the function of the intact cells.
DNA Deletions
Most studies examining alterations of the mitochondrial genome have focused on a particular 5 Kb deletion of mitochondrial DNA. This deletion has been shown to increase with age in many tissues. According to Judd Aiken, from the department of animal health and biomedical sciences at the University of Wisconsin, several studies on animal models, including rhesus monkeys and rodents, have shown that multiple mitochondrial DNA deletions occur with age, the highest levels being detected in highly oxidative nerve and muscle tissue. Although the mechanism by which mitochondrial DNA deletions are formed is not known, there is evidence to suggest that oxidative stress may play a role in their production.
Despite a wealth of research into free radical production, it seems there is no escaping their production by the body. And this is why attention is turning to means of "mopping them up" to prevent damage, according to Harman. Antioxidants can help, but how much is the appropriate amount, and which ones are best? Most people agree that we should be taking vitamin B complex, vitamin E, beta carotene, flavonoids, and coenzyme Q10, even though quantity is still in doubt.
Oxidant Reduction Therapy
Consideration of the progressive accumulation of mitochondrial DNA mutations with age, and the tissue cellular bioenergy decline associated with the aging process suggests the possibility of an oxidant reduction (redox) therapy for the condition, according to Anthony Linnane, from the Centre for Molecular Biology and Medicine at Epworth Hospital in Melbourne, Australia. This concept predicts that a tissue bioenergetic decline will be intrinsic to various diseases of the aged, and thereby will contribute to their pathology, particularly heart failure, degenerative brain disease, muscle and vascular diseases and other syndromes. A redox therapy based on coenzyme Q10 has demonstrated profound alteration in heart function of old rats, but no effect on young rats.
The impact of diet and specific food groups on aging and age-associated degenerative diseases has been widely recognized in recent years. Several epidemiological and clinical studies have revealed potential roles for dietary antioxidants in the age-associated decline of immune function and the reduction of risk of morbidity and mortality from cancer and heart disease. Mohsen Meydani, from the Human Nutrition Research Center on Aging at Tufts University in Boston, has found that long-term supplementation with vitamin E enhances immune function in aged animals and elderly subjects.
He found in a study of mice that after giving the animals vitamin E then infecting them with the influenza virus, the effect of the virus was much less with vitamin E. The animals on vitamin E also lost less weight during the five days of infection with the virus than did the controls. The level of vitamin E given to the animals was standard for all, 500 ppm. He has also found that the beneficial effect of vitamin E in reducing risk of atherosclerosis is in part associated with molecular modulation of the interaction of immune and endothelial cells.
Stephen Christen, from the department of molecular and cell biology at the University of California at Berkeley, noted that this is illustrated by the inverse correlation between species-specific metabolic rates and life span, and the associated exponential increase in cancer with increasing age. Consumption of large amounts of fruits and vegetables is associated with a decreased risk in cancer incidence and morbidity in general, he said. High on the "good" list are vitamin C, carotenoids and vitamin E.
Vitamin E And Cognition
Similarly, Reinhold Schmidt noted that findings of his research were compatible with the view that vitamin E may be protective against cognitive impairment in older people. Schmidt and his colleagues from Karl Franz University in Graz, Austria, assessed the association between plasma concentrations of essential antioxidants and cognitive performance in non-demented middle-aged and elderly people. He said almost 2,000 people were assessed in this study which involved 10 naturally occurring antioxidants. He also reported another study in which there was an association between low plasma concentrations of vitamin E and a higher risk of cerebral white matter disease.
Despite the positive effects of vitamin E on the immune and cardiovascular system, Meydani found that vitamin E and several other antioxidants-namely, glutathione, melatonin, strawberry extract, and combinations of these-had no effect on extension of life from middle age. Perhaps there would have been an effect if treatments were begun earlier in life, he suggested. There is a large middle-aged population in the United States, all wondering whether antioxidants might have some effect on longevity, but Meydani found no effect on extension of life.
Commenting on Meydani's work, Russell Reiter, from the department of cellular and structural biology at the University of Texas Health Science Center, said at this stage there is no compelling evidence that taking melatonin will prolong life. Reiter said that doesn't mean melatonin is not good for many things, and it may be that the wrong studies have been done. But at present there is no solid basis for drawing the conclusion that melatonin will prolong life.
Melatonin is useful as an antioxidant in acute situations where there is tremendous oxidative stress, such as exposure to ionizing radiation, he said.
The reduction of melatonin with age may be a factor in increased oxidative damage in the elderly. Melatonin, the chief secretory product of the pineal gland, is a direct free radical scavenger and indirect antioxidant. Because of its high lipid solubility and modest aqueous solubility, melatonin is able to protect macromolecules in all parts of a cell from oxidative damage. In humans, the total antioxidative capacity of serum is related to melatonin levels.
A micronutrient supplement in modest doses for all elderly people may be the best treatment for immune problems. That is the advice of Canadian Professor Ranjit Chandra, who said aging is associated with a reduction in many immune responses.
Alterations are seen in delayed cutaneous hypersensitivity, lymphocyte response to mitogens, interleukin-2 production, and antibody response. At the same time, nutritional deficiencies are observed in at least one-third of elderly people. Dietary intake and blood concentrations of many nutrients are known to be reduced with aging. The important contributing factors to the development of nutrient deficiencies include social and psychological isolation, physical disabilities, dental problems, poverty and drug-nutrient interactions, he said.
The Necessity of Supplements
It is expensive and impractical to estimate dietary intake or blood levels of various nutrients, so a micronutrient supplement in modest doses would be the best medicine, he suggested. Such a supplement would be likely to boost immunity and reduce the burden of infection.
A high lifetime intake of vitamin C and beta carotene may protect memory functions and stave off dementia, according to the prospective Basel Longitudinal Study. Results of the study, begun in 1960, were reported to The World Congress of Gerontology by Hannes Stahelin, a University of Basel geriatrics professor. The study followed Swiss men and women for 20 years, finding that those who had high levels of antioxidant vitamins in their blood performed better in memory function tests.
Stahelin said it seems clear that free radicals and certain related compounds advance aging, and that good antioxidants can defend the body, slow down the aging process, and protect the body from diseases such as atherosclerosis, some cancers, and mental deterioration in old age. Neurons in the brain are challenged by free radicals, he said, and the aging process itself is linked to those free radicals. Free radicals are highly reactive compounds which interact with the body's essential structures, notably the genes. Although the body has quite an elaborate defense system, in times of stress or injury, it is probably insufficient and the generation of free radicals is large, resulting in oxidative stress. At such times we need more antioxidants to maintain a healthy balance, Stahelin said. It appears that antioxidants protect the neurons from damage, although the usefulness of these vitamins is difficult to prove conclusively.
He said a Rotterdam study on dementia had shown that people with low beta carotene intake had a higher rate of dementia. That study involved testing 442 healthy elderly people aged 65 to 94 years on aspects of memory and matching the results with vitamin blood levels. It found vitamin C and beta carotene were a significant predictor of ability in tests of vocabulary, and beta carotene in tests of recognition.
Stahelin said that although antioxidants are obtained from natural sources such as fruits and vegetables, it might be necessary to consider special supplements since it is not always easy to eat fresh fruits and vegetables every day. We should adjust our diet and start to develop special, functional food which does its job more easily in certain conditions, he said. And we should increase daily intake of antioxidants above the current recommended daily intake, since we now know that higher levels might provide protection from chronic diseases.
Fruits, Vegetables And Aging
There is a correlation between the intake of fruit and vegetables and our carotenoid levels. The evidence is immensely strong that there is a relationship between the intake of fruits and vegetables and a decreased rate of age-related diseases, such as cancer and cardiovascular disease, age-related macular degeneration, and cataract, according to Norman Krinsky from the biochemistry department of the Human Nutrition Research Center on Aging at Tufts University.
Studies have now shown that supplementing the diet with beta carotene prevents cancer in humans, and there may be other effects, he said. However, he added, a recent Finnish study found an increase in lung cancer in men who were heavy smokers who also had received supplementary beta carotene. About 26,000 men were in the study, so it was not trivial. We know that smoking produces a lot of radicals which interact and alter the beta carotene, but we don't know about the impact of those products, he said.
Moreover, there is still much that is not known about the biological properties of carotenoids. They may be much more related to breakdown products such as apo-carotenoids and retinoids than to antioxidant vitamins. Much effort has gone into evaluating the relative antioxidant potency of carotenoid pigments, both in vitro and in vivo. In vitro, carotenoids can inhibit the propagation of radical-initiated lipid peroxidation. In vivo, it has been much more difficult to obtain solid experimental evidence that carotenoids act directly as biological antioxidants. In fact, in some circumstances, both in vitro and in vivo results suggest that carotenoids may function as pro-oxidants. These results can be modified by altering oxidative stress, the cellular or subcellular system, the type of animal tested, and environmental conditions such as oxygen tension.
This type of evidence raises the question whether it is still appropriate to group the carotenoids with the antioxidant vitamins such as vitamin C and vitamin E, Krinsky said. The biological properties of carotenoids may be much more related to products of the interaction of carotenoids with oxidant stress.
A cup of tea and a glass of wine may be considered just as cancer-protective as fruit and vegetables, and they may even contribute to delaying the aging process. That is the view of Ivor Dreosti, from CSIRO's division of human nutrition in Adelaide. He said the increase in cancer risk with advancing age is well recognized, and several mechanisms have been proposed as explanations. Calorie restriction, which reduces oxidative stress and effectively increases life span in animals, also seems to reduce the incidence of many cancers, possibly due to diminished mitogenesis.
Similarly, oxidative damage to DNA appears to be common to both processes, but may be more important in the mitochondria with respect to aging and in the nucleus in relation to cancer. Inadequate dietary folate and impaired DNA methylation are closely associated with increased cancer risk. Recently, defective somatic cell methylation and accumulated genetic instability have been proposed as key mechanisms contributing to senescence.
The Role of Phytochemicals
Several other well-established anti-cancer strategies, including increased fiber intake and consumption of more fruits and vegetables, have not been studied extensively in relation to aging. However, many of the phytochemicals considered important as chemopreventive agents for cancer may well contribute to delaying the aging process.
It is clear that one can eliminate or reduce exposure to aggravating factors such as obesity, fat intake, salt intake, curing processes in food processing, spoiling because of microtoxins, and overcooking in order to reduce the risk of contracting cancer, Dreosti suggested. And there are protective factors, too, he said. Fiber has attracted a lot of attention in warding off cancer, including large bowel cancer. There are several types of fiber, including insoluble or indigestible fiber, soluble or digestible fiber, and resistant starch. This last behaves very much like insoluble fiber, which passes into the large bowel, protects the epithelium from carcinogens, and hastens digestion through the large bowel. Soluble fiber passes into the large bowel and prevents conditions that might result in cancer formation.
Dreosti said fruits and vegetables are now a major emerging interest. Foods which have been associated with cancer protection include garlic, cabbage, celery, soy beans, onions-all the things which in folklore have been associated with cancer protection. A number of vegetables also have a reasonable amount of fiber in them as well. But what is in the fruits and vegetables that has this protective action? Some of those compounds are established nutrients or fiber-containing foods. Another is phytochemicals, which occur at very low levels. They don't appear to be essential nutrients, but they seem to be significant in protecting against the development of cancer.
It has long been known that dietary restriction increases the life span of rats and mice, and there is strong evidence that it does so by slowing the aging process. This anti-aging action is due to the reduction in the intake of calories rather than the reduction in intake of a specific nutrient or dietary contaminant. It was suggested that the anti-aging response to dietary restriction arose because of evolutionary advantage during periods of unpredictable short-term food shortage. Much evidence has been uncovered in support of this view (See "Calorie Restriction: Eat Less, Eat Better, Live Longer," Life Extension magazine, February 1998).
Telomeres And Telomerase
In studies of cellular aging the behavior of cultured human cells must take into account environmental treatments which can increase or reduce longevity as well as the fact that individual cells and populations derived from one primary culture vary in their life spans. Further studies on human cell senescence have revealed that there may be no correlation between donor age and replicative life span. Perhaps replicative senescence is only one of several pathways cells can take in becoming senescent.
As has been reported in Life Extension magazine, telomeres, the genetic elements that cap chromosome ends, play an important role in loss of replicative capacity and deleterious changes in gene expression in mortal normal cells. (See "Turning on Telomerase to Stop Cell Aging: The Quest for Immortality," February 1998). According to Calvin Harley, from Geron Corp. in California, the critical loss of telomeres-special DNA regions at the ends of each chromosome-signals an irreversible checkpoint arrest which contributes to the abnormal pattern of gene expression seen in old cells. The activation of telomerase-an enzyme that can reset telomeres back to their youthful lengths- slows the rate of telomere loss and hence extends the life span of progeny cells. Modulation of telomere length, telomerase activity, and senescent gene expression provide novel opportunities to develop therapies for age-related diseases, including cancer, he suggests.
Studies on diverse biological systems have revealed new insights into several fundamental aspects of what governs aging processes and longevity determination. Although we are far from a thorough understanding of either process, an appreciation of the differences between age changes and the determination of longevity seems to be emerging. Until now, the general consensus in experimental gerontology has been that the only effective means of prolonging the life span of animals is dietary restriction, and no single pharmaceutical has been shown to have such an effect. However, deprenyl, a drug originally developed as an antidepressant, is proving unique in its effects on longevity, Dr. Kenichi Kitani has found.
Deprenyl May Prolong Life
Kitani, from the National Institute for Longevity Sciences in Japan, told the International Aging had been attributed to Association for Biomedical Gerontology that deprenyl manages to raise antioxidant enzyme activities such as superoxide dismutase and catalase in selective brain regions in different animal species. Studies in mice have revealed no significant effect on longevity, while studies in rats, hamsters and dogs have proved positive.
Kitani has obtained positive effects on longevity in rats of both sexes, but two studies with different doses in mice revealed no significant positive effects. The effects on rats, mice and dogs were variable, depending on the doses used.
A recent study of deprenyl in aging beagle dogs showed a marked effect on longevity, agreeing with Kitani's superoxide dismutase results. Kitani believes the drug may at least partially prolong the life span in animals by enhancing immune system function and preventing tumor development. A study at the Life Sciences Division of the University of Toronto agreed on the significant effects of deprenyl in prolonging the remaining life expectancy of old rats treated with subcutaneous injections of the drug. This study, like that of Kitani, found no effect in mice. Reporting this study at the World Congress of Gerontology, Gwen Ivy said the variabilities of its effect on the life spans of different animal species may stem from the variability in its optimal dose on enzyme activities.
Reflecting on the congress, Robin Holliday, at CSIRO biomedical engineering in Sydney, Australia, said most people are still focusing on theories. The free radical theory is in vogue, as is the mitochondrial theory. But aging, he says, is multi-causal. Defense against free radicals is just one maintenance mechanism. A broader view of the whole subject is necessary. Simply put, gerontologists don't yet realize how much is known about human pathologies.