The Altera® NCO IP core generates numerically controlled oscillators (NCOs) customized for Altera devices. A numerically controlled oscillator (NCO) synthesizes a discrete-time, discrete-valued representation of a sinusoidal waveform.
Typically, you can use NCOs in communication systems as quadrature carrier generators in I-Q mixers, in which baseband data is modulated onto the orthogonal carriers in one of a variety of ways.
You can also use NCOs in all-digital phase-locked-loops (PLLs) for carrier synchronization in communications receivers, or as standalone frequency shift keying (FSK) or phase shift keying (PSK) modulators. In these applications, the phase or the frequency of the output waveform varies directly according to an input data stream.
You can implement ROM-based, CORDIC-based, and multiplier-based NCO architectures,. The wizard also includes time and frequency domain graphs that dynamically display the functionality of the NCO, based on your parameter settings.
To decide which NCO implementation to use, consider the spectral purity, frequency resolution, performance, throughput, and required device resources. Also, consider the trade-offs between some or all of these parameters.
Final support—Altera verifies the IP core with final timing models for this device family. The IP core meets all functional and timing requirements for the device family. You can use it in production designs.
Altera verifies that the current version of the Quartus Prime software compiles the previous version of each IP core. Altera does not verify that the Quartus Prime software compiles IP core versions older than the previous version. The Altera FPGA IP Release Notes lists any exceptions.
The Intel® Quartus® Prime software installation includes the Intel® FPGA IP library. This library provides many useful IP cores for your production use without the need for an additional license. Some Intel® FPGA IP cores require purchase of a separate license for production use. The Intel® FPGA IP Evaluation Mode allows you to evaluate these licensed Intel® FPGA IP cores in simulation and hardware, before deciding to purchase a full production IP core license. You only need to purchase a full production license for licensed Altera® IP cores after you complete hardware testing and are ready to use the IP in production.
Simulate the behavior of a licensed Intel® FPGA IP core in your system.
Verify the functionality, size, and speed of the IP core quickly and easily.
Generate time-limited device programming files for designs that include IP cores.
Program a device with your IP core and verify your design in hardware.
Tethered—Allows running the design containing the licensed Intel® FPGA IP indefinitely with a connection between your board and the host computer. Tethered mode requires a serial joint test action group (JTAG) cable connected between the JTAG port on your board and the host computer, which is running the Intel® Quartus® Prime Programmer for the duration of the hardware evaluation period. The Programmer only requires a minimum installation of the Intel® Quartus® Prime software, and requires no Intel® Quartus® Prime license. The host computer controls the evaluation time by sending a periodic signal to the device via the JTAG port. If all licensed IP cores in the design support tethered mode, the evaluation time runs until any IP core evaluation expires. If all of the IP cores support unlimited evaluation time, the device does not time-out.
Untethered—Allows running the design containing the licensed IP for a limited time. The IP core reverts to untethered mode if the device disconnects from the host computer running the Intel® Quartus® Prime software. The IP core also reverts to untethered mode if any other licensed IP core in the design does not support tethered mode.
When the evaluation time expires for any licensed Intel® FPGA IP in the design, the design stops functioning. All IP cores that use the Intel® FPGA IP Evaluation Mode time out simultaneously when any IP core in the design times out. When the evaluation time expires, you must reprogram the FPGA device before continuing hardware verification. To extend use of the IP core for production, purchase a full production license for the IP core.
You must purchase the license and generate a full production license key before you can generate an unrestricted device programming file. During Intel® FPGA IP Evaluation Mode, the Compiler only generates a time-limited device programming file (<project name> _time_limited.sof) that expires at the time limit.
Note: Refer to each IP core's user guide for parameterization steps and implementation details.
Altera® licenses IP cores on a per-seat, perpetual basis. The license fee includes first-year maintenance and support. You must renew the maintenance contract to receive updates, bug fixes, and technical support beyond the first year. You must purchase a full production license for Intel® FPGA IP cores that require a production license, before generating programming files that you may use for an unlimited time. During Intel® FPGA IP Evaluation Mode, the Compiler only generates a time-limited device programming file (<project name> _time_limited.sof) that expires at the time limit. To obtain your production license keys, visit the Self-Service Licensing Center or contact your local Intel FPGA representative.
The Altera® FPGA Software License Agreements govern the installation and use of licensed IP cores, the Intel® Quartus® Prime design software, and all unlicensed IP cores.
All IP cores in a device time out simultaneously when the most restrictive evaluation time is reached. If a design has more than one IP core, the time-out behavior of the other IP cores may mask the time-out behavior of a specific IP core .
For IP cores, the untethered time-out is 1 hour; the tethered time-out value is indefinite. Your design stops working after the hardware evaluation time expires. The Quartus II software uses Intel® FPGA IP Evaluation Mode Files (.ocp) in your project directory to identify your use of the Intel® FPGA IP Evaluation Mode evaluation program. After you activate the feature, do not delete these files..
When the evaluation time expires, the output of NCO IP core goes low.
Filter IP Catalog to Show IP for active device family or Show IP for all device families. If you have no project open, select the Device Family in IP Catalog.
Type in the Search field to locate any full or partial IP core name in IP Catalog.
Right-click an IP core name in IP Catalog to display details about supported devices, to open the IP core's installation folder, and for links to IP documentation.
Click Search for Partner IP to access partner IP information on the web.
The parameter editor prompts you to specify an IP variation name, optional ports, and output file generation options. The parameter editor generates a top-level Intel® Quartus® Prime IP file (.ip) for an IP variation in Intel® Quartus® Prime Pro Edition projects.
The parameter editor generates a top-level Quartus IP file (.qip) for an IP variation in Intel® Quartus® Prime Standard Edition projects. These files represent the IP variation in the project, and store parameterization information.
Quickly configure Intel® FPGA IP cores in the Intel® Quartus® Prime parameter editor. Double-click any component in the IP Catalog to launch the parameter editor. The parameter editor allows you to define a custom variation of the IP core. The parameter editor generates the IP variation synthesis and optional simulation files, and adds the .ip file representing the variation to your project automatically.
Create or open an Intel® Quartus® Prime project (.qpf) to contain the instantiated IP variation.
In the IP Catalog (Tools > IP Catalog), locate and double-click the name of the IP core to customize. To locate a specific component, type some or all of the component's name in the IP Catalog search box. The New IP Variation window appears.
Specify a top-level name for your custom IP variation. Do not include spaces in IP variation names or paths. The parameter editor saves the IP variation settings in a file named <your_ip> .ip. Click OK. The parameter editor appears.
Optionally, select preset parameter values if provided for your IP core. Presets specify initial parameter values for specific applications.
Specify parameters defining the IP core functionality, port configurations, and device-specific features.
Specify options for processing the IP core files in other EDA tools.
Note: Refer to your IP core user guide for information about specific IP core parameters.
Click Generate HDL. The Generation dialog box appears.
Specify output file generation options, and then click Generate. The synthesis and simulation files generate according to your specifications.
To generate a simulation testbench, click Generate > Generate Testbench System. Specify testbench generation options, and then click Generate.
To generate an HDL instantiation template that you can copy and paste into your text editor, click Generate > Show Instantiation Template.
Click Finish. Click Yes if prompted to add files representing the IP variation to your project.
After generating and instantiating your IP variation, make appropriate pin assignments to connect ports.
Note: Some IP cores generate different HDL implementations according to the IP core parameters. The underlying RTL of these IP cores contains a unique hash code that prevents module name collisions between different variations of the IP core. This unique code remains consistent, given the same IP settings and software version during IP generation. This unique code can change if you edit the IP core's parameters or upgrade the IP core version. To avoid dependency on these unique codes in your simulation environment, refer to Generating a Combined Simulator Setup Script.
The Intel® Quartus® Prime software generates the following output file structure for individual IP cores that are not part of a Platform Designer system.
Top-level IP variation file that contains the parameterization of an IP core in your project. If the IP variation is part of a Platform Designer system, the parameter editor also generates a .qsys file.
<your_ip>.cmp The VHDL Component Declaration (.cmp) file is a text file that contains local generic and port definitions that you use in VHDL design files.
<your_ip>_generation.rpt IP or Platform Designer generation log file. Displays a summary of the messages during IP generation.
Simulation caching file that compares the .qsys and .ip files with the current parameterization of the Platform Designer system and IP core. This comparison determines if Platform Designer can skip regeneration of the HDL.
Synthesis caching file that compares the .qsys and .ip files with the current parameterization of the Platform Designer system and IP core. This comparison determines if Platform Designer can skip regeneration of the HDL.
Contains all information to integrate and compile the IP component.
<your_ip>.csv Contains information about the upgrade status of the IP component.
A symbol representation of the IP variation for use in Block Diagram Files (.bdf).
Input file that ip-make-simscript requires to generate simulation scripts. The .spd file contains a list of files you generate for simulation, along with information about memories that you initialize.
<your_ip>.ppf The Pin Planner File (.ppf) stores the port and node assignments for IP components you create for use with the Pin Planner.
<your_ip>_bb.v Use the Verilog blackbox (_bb.v) file as an empty module declaration for use as a blackbox.
<your_ip>_inst.v or _inst.vhd HDL example instantiation template. Copy and paste the contents of this file into your HDL file to instantiate the IP variation.
<your_ip>.regmap If the IP contains register information, the Intel® Quartus® Prime software generates the .regmap file. The .regmap file describes the register map information of master and slave interfaces. This file complements the .sopcinfo file by providing more detailed register information about the system. This file enables register display views and user customizable statistics in System Console.
Allows HPS System Debug tools to view the register maps of peripherals that connect to HPS within a Platform Designer system.
During synthesis, the Intel® Quartus® Prime software stores the .svd files for slave interface visible to the System Console masters in the .sof file in the debug session. System Console reads this section, which Platform Designer queries for register map information. For system slaves, Platform Designer accesses the registers by name.
<your_ip>.v <your_ip>.vhd HDL files that instantiate each submodule or child IP core for synthesis or simulation.
Contains a msim_setup.tcl script to set up and run a ModelSim simulation.
Contains a Riviera*-PRO script rivierapro_setup.tcl to setup and run a simulation.
Contains a shell script vcs_setup.sh to set up and run a VCS* simulation.
Contains a shell script vcsmx_setup.sh and synopsys_sim.setup file to set up and run a VCS MX* simulation.
Contains a shell script ncsim_setup.sh and other setup files to set up and run an NCSIM simulation.
/submodules Contains HDL files for the IP core submodule.
<IP submodule>/ Platform Designer generates /synth and /sim sub-directories for each IP submodule directory that Platform Designer generates.
The NCO IP core allows you to generate a variety of NCO architectures. Your custom NCO includes both time- and frequency-domain analysis tools. The custom NCO outputs a sinusoidal waveform in two's complement representation.
The NCO MegaCore function automatically calculates this value, using the specified parameters. IP Toolbench also sets the value of the phase increment in all testbenches and vector source files it generates.
The angular precision of an NCO is the phase angle precision before the polar-to-cartesian transformation. The magnitude precision is the precision to which the sine and/or cosine of that phase angle can be represented. The effects of reduction or augmentation of the angular, magnitude, accumulator precision on the synthesized waveform vary across NCO architectures and for different fo/fclk ratios.
You can view these effects in the NCO time and frequency domain graphs as you change the NCO IP core parameters.
The NCO MegaCore function supports large ROM, small ROM, CORDIC, and multiplier-based architectures.
Use the large ROM architecture if your design requires very high speed sinusoidal waveforms and your design can use large quantities of internal memory.
In this architecture, the ROM stores the full 360 degrees of both the sine and cosine waveforms. The output of the phase accumulator addresses the ROM.
The internal memory holds all possible output values for a given angular and magnitude precision. The generated waveform has the highest spectral purity for that parameter set (assuming no dithering). The large ROM architecture also uses the fewest logic elements (LEs) for a given set of precision parameters.
.To reduce memory usage (but increase LE usage) and increase output frequency, use the small ROM architecture.
In a small ROM architecture, the device memory only stores 45 degrees of the sine and cosine waveforms. All other output values are derived from these values based on the position of the rotating phasor on the unit circle.
A small ROM implementation is more likely to have periodic value repetition, so the resulting waveform's SFDR is lower than that of the large ROM architecture. However, you can often mitigate this reduction in SFDR by using phase dithering.
The CORDIC algorithm, which can calculate trigonometric functions such as sine and cosine, provides a high-performance solution for very-high precision oscillators in systems where internal memory is at a premium.
The CORDIC algorithm is based on the concept of complex phasor rotation by multiplication of the phase angle by successively smaller constants. In digital hardware, the multiplication is by powers of two only. Therefore, the algorithm can be implemented efficiently by a series of simple binary shift and additions/subtractions.
In an NCO, the CORDIC algorithm computes the sine and cosine of an input phase value by iteratively shifting the phase angle to approximate the cartesian coordinate values for the input angle. At the end of the CORDIC iteration, the x and y coordinates for a given angle represent the cosine and sine of that angle, respectively.
You an use the parallel CORDIC architecture to create a very high-performance, high-precision oscillator—implemented entirely in logic elements—with a throughput of one output sample per clock cycle. With this architecture, there is a new output value every clock cycle.
The serial CORDIC architecture uses fewer resources than the parallel CORDIC architecture. However, its throughput is reduced by a factor equal to the magnitude precision. For example, if you select a magnitude precision of N bits in the NCO MegaCore function, the output sample rate and the Nyquist frequency is reduced by a factor of N. This architecture is implemented entirely in logic elements and is useful if your design requires low frequency, high precision waveforms. With this architecture, the adder stages are stored internally and a new output value is produced every N clock cycles.
Logic elements (Cyclone series) or combinational ALUTs (Stratix series).
Dedicated multiplier circuitry (for example, dedicated DSP blocks) (Stratix or Arria series).
Note: When you specify a dual output multiplier-based NCO, the IP core provides an option to output a sample every two clock cycles. This setting reduces the throughput by a factor of two and halves the resources required by the waveform generation unit.
Large ROM Good for high speed and when a large quantity of internal memory is available. Gives the highest spectral purity and uses the fewest logic elements for a given parameterization.
Small ROM Good for high output frequencies with reduced internal memory usage when a lower SFDR is acceptable.
CORDIC High performance solution when internal memory is at a premium. The serial CORDIC architecture uses fewer resources than parallel although the throughput is reduced.
Multiplier-Based Reduced memory usage by implementing multipliers in logic elements or dedicated circuitry.
The NCO IP core allows you to implement multichannel NCOs. You can generate multiple sinusoids of independent frequency and phase t at a very low cost in additional resources. The waveforms have an output sample-rate of fclk/M where M is the number of channels. You can select 1 to 8 channels.
Multichannel implementations are available for all single-cycle generation algorithms. The input phase increment, frequency modulation value and phase modulation input are input sequentially to the NCO with the input values corresponding to channel 0 first and channel (M–1) last. The inputs to channel 0 should be input on the rising clock edge immediately following the de-assertion of the NCO reset.
On the output side, the first output sample for channel 0 is output concurrent with the assertion of out_valid and the remaining outputs for channels 1 to (M–1) are output sequentially.
If you select a multichannel implementation, the NCO MegaCore function generates VHDL and Verilog HDL testbenches that time-division-multiplex the inputs into a single stream and demultiplex the output streams into their respective downsampled channelized outputs.
The NCO IP core supports frequency hopping (except the serial CORDIC architecture). Frequency hopping allows control and configuration of the NCO IP core at run time so that carriers with different frequencies can be generated and held for a specified period of time at specified slot intervals.
The IP core supports multiple phase increment registers that you can load using an Avalon-MM bus. You select the phase increment register using an external hardware signal; changes on this signal take effect on the next clock cycle. The maximum number of phase increment registers is 16.
Note: During frequency hopping, the phase of the carrier should not experience discontinuous change. Discontinuous carrier phase changes may cause spectral emission problems.
The RAM stores all hopping frequencies. The RAM size is <width>×<depth>, where <width> is the number of bits required to specify the phase accumulator value to the precision you select in the parameter editor, and <depth> is the number of bands you select in the parameter editor.
All digital sinusoidal synthesizers suffer from the effects of finite precision, which manifests itself as spurs in the spectral representation of the output sinusoid. Because of angular precision limitations, the derived phase of the oscillator tends to be periodic in time and contributes to the presence of spurious frequencies. You can reduce the noise at these frequencies by introducing a random signal of suitable variance into the derived phase, thereby reducing the likelihood of identical values over time. Adding noise into the data path raises the overall noise level within the oscillator, but tends to reduce the noise localization and can provide significant improvement in SFDR.
The extent to which you can reduce spur levels is dependent on many factors. The likelihood of repetition of derived phase values and resulting spurs, for a given angular precision, is closely linked to the ratio of the clock frequency to the desired output frequency. An integral ratio clearly results in high-level spurious frequencies, while an irrational relationship is less likely to result in highly correlated noise at harmonic frequencies.
The Altera NCO IP core allows you to finely tune the variance of the dither sequence for your chosen algorithm, specified precision, and clock frequency to output frequency ratio, and dynamically view the effects on the output spectrum graphically.
You can add an optional frequency modulator to your custom NCO variation. You can use the frequency modulator to vary the oscillator output frequency about a center frequency set by the input phase increment. This option is useful for applications in which the output frequency is tuned relative to a free-running frequency, for example in all-digital phase-lock-loops.
You can also use the frequency modulation input to switch the output frequency directly.
You can set the frequency modulation resolution input in the IP core. The specified value must be less than or equal to the phase accumulator precision.
The NCO IP core also provides an option to increase the modulator pipeline level; however, the effect of the increase on the performance of the NCO IP core varies across NCO architectures and variations.
You can use the NCO IP core to add an optional phase modulator to your variation, allowing dynamic phase shifting of the NCO output waveforms. This option is particularly useful if you want an initial phase offset in the output sinusoid.
You can also use the option to implement efficient phase shift keying (PSK) modulators in which the input to the phase modulator varies according to a data stream. You set the resolution and pipeline level of the phase modulator in the NCO wizard. The input resolution must be greater than or equal to the specified angular precision.
The wizard only allows you to select legal combinations of parameters, and warns you of any invalid configurations.
Generation Algorithm Small ROM, Large ROM, CORDIC, Multiplier-Based Select the required algorithm.
Outputs Dual Output, Single Output Select whether to use a dual or single output.
Device Family Target — Displays the target device family. The target device family is preselected by the value specified in the Quartus II or DSP Builder software. The HDL that is generated for your variation may be incorrect if you change the device family target in this wizard.
Number of Channels 1–8 Select the number of channels when you want to implement a multichannel NCO.
Number of Bands 1–16 Select a number of bands greater than 1 to enable frequency hopping. Frequency hopping is not supported in the serial CORDIC architecture.
Use dedicated multipliers On or off When the multiplier-based algorithm is selected on the Parameters page, turn on to use dedicated multipliers and select the number of clock cycles per output, otherwise the design uses logic elements. This option is not available if you target the Cyclone device family.
CORDIC Implementation Parallel, Serial When you select the CORDIC generation algorithm, you can select a parallel (one output per clock cycle) or serial (one output per 18 clock cycles) implementation.
Clock Cycles Per Output 1, 2. When the multiplier-based algorithm is selected on the Parameters page, you can select 1 or 2 clock cycles per output.
Phase Accumulator Precision 4 to 64 Select the required phase accumulator precision. The phase accumulator precision must be greater than or equal to the specified angular resolution.
Angular Resolution 4 to 24 or 32 Select the required angular resolution. The maximum value is 24 for small and large ROM algorithms; 32 for CORDIC and multiplier-based algorithms.
Magnitude Precision 10 to 32 Select the required magnitude precision.
Implement Phase Dithering On or Off Turn on to implement phase dithering.
Clock Rate 1 to 999 MHz, kHz, Hz, mHz, Select the clock rate using units of MegaHertz, kiloHertz, Hertz or milliHertz.
Desired Output Frequency 1 to 999 MHz, kHz, Hz, mHz, Select the desired output frequency using units of MegaHertz, kiloHertz, Hertz or milliHertz.
Phase Increment Value — Displays the phase increment value calculated from the clock rate and desired output frequency.
Real Output Frequency — Displays the calculated value of the real output frequency.
Frequency Modulation input On or Off You can optionally enable the frequency modulation input.
Modulator Resolution 4 to 64, Select the modulator resolution for the frequency modulation input.
Modulator Pipeline Level 1, 2, Select the modulator pipeline level for the frequency modulation input.
Phase Modulation Input On or Off You can optionally enable the phase modulation input.
Modulator Precision 4 to 32, Select the modulator precision for the phase modulation input.
Modulator Pipeline Level 1, 2, Select the modulator pipeline level for the phase modulation input.
The NCO MegaCore function is an Avalon-ST source and does not support backpressure. The Avalon-MM interface allows you to control frequency hopping at run time.
Avalon-ST interfaces define a standard, flexible, and modular protocol for data transfers from a source interface to a sink interface.
The input interface is an Avalon-ST sink and the output interface is an Avalon-ST source. The Avalon-ST interface supports packet transfers with packets interleaved across multiple channels.
Avalon-ST interface signals can describe traditional streaming interfaces supporting a single stream of data without knowledge of channels or packet boundaries. Such interfaces typically contain data, ready, and valid signals. Avalon-ST interfaces can also support more complex protocols for burst and packet transfers with packets interleaved across multiple channels. The Avalon-ST interface inherently synchronizes multichannel designs, which allows you to achieve efficient, time-multiplexed implementations without having to implement complex control logic.
Avalon-ST interfaces support backpressure, which is a flow control mechanism where a sink can signal to a source to stop sending data. The sink typically uses backpressure to stop the flow of data when its FIFO buffers are full or when it has congestion on its output.
address[2:0] Input Address of the 16 phase increment registers when frequency hopping is enabled.
clken Input Active-high clock enable.
freq_mod_i [F-1:0] Input Optional frequency modulation input. You can specify the modulator resolution F in IP Toolbench.
freq_sel[log 2N-1:0] input Use to select one of the phase increment registers (that is to select the hopping frequencies), when frequency hopping is enabled. N is the depth.
phase_mod_i [P-1:0] Input Optional phase modulation input. You can specify the modulator precision P in Ithe wizard.
phi_inc_i [A-1:0] Input Input phase increment. You can specify the accumulator precision A in the wizard.
reset_n Input Active-low asynchronous reset.
write_sig Input Active-high write signal when frequency hopping is enabled.
in_data Output In Qsys systems, this Avalon-ST-compliant data bus includes all the Avalon-ST input data signals.
fcos_o [M-1:0] Output Optional output cosine value (when dual output is selected). You can specify the magnitude precision M in IP Toolbench.
fsin_o [M-1:0] Output Output sine value. You can specify the magnitude precision M in IP Toolbench.
out_valid Output Data valid signal. Asserted by the MegaCore function when there is valid data to output.
out_data Output In Qsys systems, this Avalon-ST-compliant data bus includes all the Avalon-ST output data signals.
All NCO architectures, except for serial CORDIC and multi-cycle multiplier-based architectures, output a sample every clock cycle. After the clock enable is asserted, the oscillator outputs the sinusoidal samples at a rate of one sample per clock cycle, following an initial latency of L clock cycles. The exact value of L varies across architectures and parameterizations.
Note: For the non-single-cycle per output architectures, the optional phase and frequency modulation inputs need to be valid at the same time as the corresponding phase increment value. The values should be sampled every 2 cycles for the two-cycle multiplier-based architecture and every N cycles for the serial CORDIC architecture, where N is the magnitude precision.
After the clock enable is asserted, the oscillator outputs the sinusoidal samples at a rate of one sample for every two clock cycles, following an initial latency of L clock cycles. The exact value of L depends on the parameters that you set.
Note: The fsin_0 and fcos_0 values can change while out_valid is low.
After the clock enable is asserted, the oscillator outputs sinusoidal samples at a rate of one sample per N clock cycles, where N is the magnitude precision. The IP core has an initial latency of L clock cycles; the exact value of L depends on the parameters that you set.
The phase increment for channel 0 is the first value read in on the rising edge of the clock following the de-assertion of reset_n (assuming clken is asserted) followed by the phase increments for the next (M-1) channels. The output signal out_valid is asserted when the first valid sine and cosine outputs for channel 0, S 0, C 0, respectively are available.
The output values S k and C k corresponding to channels 1 through (M-1) are output sequentially by the NCO. The outputs are interleaved so that a new output sample for channel k is available every M cycles.
1 Latency = base latency + dither latency+ frequency modulation pipeline + phase modulation pipeline (×N for serial CORDIC).
2 Dither latency = 0 (dither disabled) or 2 (dither enabled).
3 Special case: (9 <= N <= 18 && WANT_SIN_AND_COS).
4 Minimum latency assumes N = 8.
6 Minimum latency assumes N = 8.
Changed small ROM architecture description.
Corrected "deviation of output values" table position 2.
Added support for Arria 10 devices.
Added new in_data and out_data bus descriptions.
Added Arria 10 generated files description.
Removed table with generated file descriptions.
Added support for MAX 10 FPGAs.
November 2012 12.1 Added support for Arria V GZ devices.


The article takes as its topic recent developments in project-based learning. These are a major response to the changing articulation of the knowledge-based economy. Corresponding changes to the role of universities, whose mastery of knowledge is now being questioned, are a consequence-one often not anticipated as such. One response to the upsurge in interest in project-based learning for 'knowledge work' has been to move the university further into the workplace by legitimizing work-based and more flexible approaches to learning. The article identifies how, from a critically postmodern perspective, some problems occur with this shift, including the performative stresses on 'knowledge workers' who are now expected to reflect on their learning through work or project-based 'curricula'. Critical theories are useful in so far as they go, in bringing workplaces as learning environments into sharper focus. However, it is our argument that they do not go far enough, as (ironically) there are too many uncritical assumptions undergirding critical theory. The focus then switches to a postmodern analysis of project-based learning. From this perspective, project-based learning may be seen as too wedded to instrumental desires for performativity. We argue that postmodern ideas about project-based learning can offer practical organizational options, although we do not assert they are the only good options!


text:
Q: Returning structs with string values in C I'm writing a function that will return a struct with two string variables, SSID and password. The functions purpose is to generate an SSID based on mac address data which gets called from a hardware api that updates a pointer to a variable.
The function creates and returns the custom type. When I set one of the string variables manually with quotes, the calling function receives the data fine. However when I set the variable to the value of another variable, it doesn't. What's missing here?
typedef struct {
    char *ssid;
    char *password;
} wifi_auth_t;

typedef wifi_auth_t *wifi_auth;

void getmac( uint8_t *mac ) {
  mac[0] = 0xFF;
  mac[1] = 0xFF;
  mac[2] = 0xFF;
  mac[3] = 0xFF;
  mac[4] = 0xFF;
  mac[5] = 0xEE;
}

wifi_auth_t* wifi_set_ap_details() {
  uint8_t mac[6];
  wifi_auth_t *wifi;
  wifi = (wifi_auth_t *)malloc(sizeof(wifi_auth_t));
  getmac(mac);

  for (int i = 0; i < 6; i++ ) {
    printf("0x%.2X ", mac[i]);
  }
  printf("\n");
  char ssid[20];
  sprintf(ssid, "WifiDevice_%X%X%X", mac[3], mac[4], mac[5]);

  wifi->ssid = ssid;

  printf("%s\n", wifi->ssid);
  wifi->password = "stackoverflow";
  return wifi;
  free(wifi);
}

int main() {
  wifi_auth_t *wifi = wifi_set_ap_details();
  printf("Wifi: %s\n", wifi->ssid);
  printf("Pass: %s\n", wifi->password);

}

A: I guess you're not familiar with C where you have to manage memory explicitly.
First, uint8_t mac[6]; and char ssid[20]; don't exist after the function exits, so pointers to them in the allocated wifi struct will point to possibly random stuff. One way to handle this, if you know the size will always be the same, is to specify the actual storate in the struct, as in:
typedef struct {
    uint8_t mac[6];
    char ssid[20];
} wifi_auth_t;

Second, when you allocate wifi, you can't free it until the last place it's used, which will be somewhere in the code that calls this function main() in this case). When return is executed, nothing after that point is reached, so the free() won't ever be executed.
You'll have to change a few other bits, like how mac is set, but that should be minor.

redpajama_set_name: RedPajamaStackExchange


In case you are running a small business, you will realize that you are prone to lots of security measures and having the right awareness strategies in very essential. A research has been released, and it claims that most threats to IT systems are coming from errors from the humans and these can be controlled through constant training and awareness. If you would like to operate your business with ease, find out how security awareness has brought lots of benefits.
You are going to ensure that you stop breaches as well as attacks that may happen from time to time. Therefore the right ideas is ensuring that you create an awareness at your organization that would be aimed at helping strategies your business security. Your business can go a long way without having breaches, therefore take the initial steps of preventing it through sensitizing the employees with the help of the IT support. The other thing is that you will have the chance of being able to influence the culture of the company. Ensuring that you advance the security measures will keep you on the path of being able to reserve your culture as a professional business in a great way.
It is very hard to win customers, and this is among the hardest tasks that businesses go through. However, here you are going to learn how training on security awareness can be of help to you in having contracts which are high profile. When none of your employees are aware of the insecurity which happens for many businesses especially the cyber-attacks, this is where you lose customers since they avoid being part of such attacks. Customers need to feel secure whenever they are dealing with businesses, and that is why you need security awareness training. Once the training start, you will realize that more and more customers stick to your business now that they know they are dealing with informed people of what is going on in the security section.
Compliance is very important especially when you own a business and want it to be a success. You might think that it is all about compliance that you need the security training, but there is still more hidden agenda behind all that. In fact, in many cities these days, any businesses which operate need to have the training at their organization. That is the only safe way you can protect your employees and customers from insecurity situations and also ensuring you are doing the right thing for your business.


text:
COVID-19 pandemic doesn't stop shoppers from lining up early for Black Friday deals in Ottawa
Josh Pringle Digital Multi-Skilled Journalist
@PringleJosh Contact
Tyler Fleming Multi-Skilled Journalist
@tylerflemingCTV Contact
Published Thursday, November 26, 2020 10:07AM EST Last Updated Friday, November 27, 2020 11:47AM EST
OTTAWA -- Shoppers lined up early looking for Black Friday deals at stores across the City of Ottawa.
At Tanger Outlets, long lines formed outside several stores before the 7 a.m. opening. With stores offering up to 70 per cent off merchandise, some shoppers told CTV News Ottawa they were waiting more than an hour to enter a store.
And while we are in the second wave of the COVID-19 pandemic, shoppers said they felt safe inside the stores on Black Friday.
"Everyone's practicing the rules, they were handing out hand sanitizers when you walk in the stores," said one customer.
"They're doing quite well with distancing people and the masks, and just letting so much in, You feel comfortable," said another customer.
"We went into Lululemon, and they clean everything after everyone walks into the change rooms," said a customer walking through Tanger Outlets with their mask on.
Both the Rideau Centre and Bayshore Shopping Centre opened at 8 a.m.
St. Laurent Centre opened an hour earlier than usual at 9 a.m. Carlingwood Shopping Centre opened at its usual time of 10 a.m., but will stay open an hour later until 8 p.m.
Here is a look at the operating hours for malls on Black Friday:
Bayshore Shopping Centre: 8 a.m. to 9 p.m.
Carlingwood Shopping Centre: 10 a.m. to 8 p.m.
Place d'Orleans: 10 a.m. to 7 p.m.
Rideau Centre: 8 a.m. to 8 p.m.
St. Laurent Centre: 9 a.m. to 8 p.m.
Tanger Outlets: 7 a.m. to 9 p.m.
Walmart Canada says its stores in Ottawa will open at 6 a.m. on Black Friday.
Best Buy locations will open an hour earlier than normal at 9 a.m.
Meanwhile, Ottawa-based Shopify says you can also find the perfect gifts from local businesses through its Shopify Shop app and online.
A recent survey by Shopify found 97 per cent of Black Friday and Cyber Monday shoppers in Canada expect to make at least one purchase online.
"Black Friday continues to be one of the biggest shopping moments of the year. While we see the shift away from just a four day shopping weekend like we have coming up to a more extended shopping season," said Loren Padelford, General Manager of Shopify Plus.
"Fifty per cent of Canadians expect to do some form of shopping during the Black Friday and Cyber Monday weekend," said Padelford, noting that's up from 46 per cent in 2019.
"So the pandemic has definitely not slowed down people's desires to go out and find that perfect gift."
Shopify supports local Ottawa businesses with their online platform.
"Shopify is powering the independent local direct to consumer brands that are behind this crazy Black Friday/Cyber Monday shopping period," said Padelford.
"With 97 per cent of us saying we're going to shop online, we're encouraging the consumers in the world to go out and find those local retailers."
You can find local retailers through the Shopify's "Shop app," available on the Apple Apps store and the Google Play store. The app has a "Gift Better Guide", with 150 hand-selected local retailers you can shop from with the help of Shopify.
Padelford says you can also Google what you are looking for.
"You can use Google and say 'Google', the product you're looking for, plus your city or even the product you're looking for plus Shopify, and it will start to identify local retailers you can start shopping from."
Shoppers lined up early at Tanger Outlets in Kanata for Black Friday sales. (Jim O'Grady/CTV News Ottawa)

redpajama_set_name: RedPajamaCommonCrawl


Amen? My heart is for homeschooling. I have seen the fruits, and know there are more to come if I keep my eye on the prize. So many days are hard and that can distract from the goal…but know that if you follow God's calling, you will produce fruit in due time.
So many people think homeschooling is just about sheltering from the world. While it is my duty to protect my child and shelter them from many evils, that is not where it stops. The fruits of homeschooling are great.
A Bible based homeschool can not help but see a good harvest. God's Word is transforming. Studying it together as a family this year has been powerful. I am so glad we decided to "experiment" with our school this way. God's Word as the foundation has given us so much- we learn together as a family, our bonds with each other are stronger, and we are FREE to learn the way God intended for our family.
Homeschoolers give their children something- it is not stifling as society see it, but a gift- a gift filled with opportunities, but most of all a gift of building a foundation on the Lord, as the Center of it all.
How has a Bible based homeschool transformed your family? Do you see the gifts? Share in the comments below!
Do you have JOY in your homeschool? Here is some encouragement for you!


TRISHTHA, AN ISO 9001:2015 CERTIFIED company has spread it's wings in highly competitive sectors like machinery manufacturing mainly for Garments & Textile Industry. We are committed to deliver top class products and services for sustainable business growth.
I am proud of my choice to work with TRISHTHA. The quality is awesome! I have introduced my another friend to buy from you.
I really liked my first TRISHTHA machine. It helped me to expand my business!
You are the only supplier who has replied to me so efficiently. The other haven't provided me with all the information I needed!


text:
Q: Add new Column to Android SQLite Database Create new table I want to add columns to table, i search before topics.
Seem they like to alert table. But i perfer to create new table.
So I try to do like this
`
@Override
public void onUpgrade(SQLiteDatabase db, int oldVersion, int newVersion)
{

   db.execSQL("create table tmp_talbe name VARCHAR(50),number integer,number2 integer");

   db.execSQL("insert into tmp_table select * from origin_table");

   db.execSQL("drop if exists table origin_table");

   db.execSQL("alter tmp_talbe rename to origin_talbe");

}`

I have problem in copy old table data to new table.If i have 2 columns in old table, 3 colums in new table,
.It will show error 3 columns in tmp_table, but only 2 supplier.
Seem  code line 2 can't do like this,how to modify is better?

A: You got the error because 'select * from origin_table' only return 2 columns, NOT 3 columns and tmp_table has 3 columns.
I assume that the original table columns: NAME, Number1 and You want to add Number2 as third column:
Change
db.execSQL("insert into tmp_table select * from origin_table");

To
db.execSQL("insert into tmp_table select NAME, Number1, NULL as Number2 from origin_table");

Use NULL for third column when you copy data from Original table to Temp table.
You can also use any Default data for Third column.


India vs Bangladesh, Asia Cup 2018 final: Ravindra Jadeja pulled off a remarkable fielding effort to dismiss Mohammed Mithun in Dubai. Is it one of the best fielding efforts on field, ever?
It was in the 28th over of the innings that he came up with his heroics. Bangladesh had already lost three quick wickets in a span of six overs after skying off to a stellar start. Yuzvendra Chahal was into the attack against Liton Das. He delivered a flighted ball outside off as Das struck it down extra cover, but Jadeja leaped in just in time with a full-length dive that measured to a jump of 6.61 metres. The ball stopped and he then turned to MS Dhoni to throw the ball.
Meanwhile, non-striker Mohammad Mithun had sprinted down the pitch to the other end and Das had his eyes fixed on the ball. Realising quickly that both the batsman were at the same end of the crease, Jadeja turned to Chahal and lobbed the ball to complete the formality. Mithun, who has remained Bangladesh's main batsman throughout Asia Cup 2018, was dismissed for only two runs.
After a stunning 120-runs opening partnership between Liton and Mehidy Hasan, Bangladesh slipped to 196 for seven in 20 overs. Liton notched up his maiden century en route to a remarkable 121 off 117 runs. For India, Kuldeep Yadav has been the pick of the bowlers with three wickets already, while Kedar Jadhav has picked up two wickets.


text:
#region License
//
// Copyright (c) 2013, Kooboo team
//
// Licensed under the BSD License
// See the file LICENSE.txt for details.
//
#endregion
using System;
using System.Collections.Generic;
using System.Linq;
using System.Text;
using System.Collections.Specialized;
using System.Web.Mvc;
using Kooboo.CMS.Sites.View;
using Kooboo.CMS.Sites.Models;
using System.Collections.ObjectModel;
using System.Web;

namespace Kooboo.CMS.Sites.DataRule
{
    public interface IValueProvider
    {
        object GetValue(string name);
    }

    public class NameValueCollectionValueProvider : IValueProvider
    {
        public NameValueCollectionValueProvider(NameValueCollection queryString)
        {
            this.QueryString = queryString;
        }
        public NameValueCollection QueryString { get; private set; }

        public object GetValue(string name)
        {
            return QueryString[name];
        }
    }

    public class DictionaryValueProvider<T> : IValueProvider
    {
        public DictionaryValueProvider(IDictionary<string, T> dic)
        {
            this.Dictionary = dic;
        }

        public IDictionary<string, T> Dictionary { get; private set; }

        public object GetValue(string name)
        {
            if (Dictionary != null)
            {
                if (Dictionary.ContainsKey(name))
                {
                    var value = Dictionary[name];
                    return value == null ? null : value.ToString();
                }
            }
            return null;
        }
    }

    public class QueryStringValueProvider : NameValueCollectionValueProvider
    {
        public QueryStringValueProvider(ControllerContext controllerContext)
            : base(controllerContext.HttpContext.Request.QueryString)
        {

        }
    }

    public class RouteValueProvider : DictionaryValueProvider<object>
    {
        public RouteValueProvider(PageRequestContext pageRequestContext)
            : base(pageRequestContext.RouteValues)
        {
        }
    }

    public class FormValueProvider : NameValueCollectionValueProvider
    {
        public FormValueProvider(ControllerContext controllerContext)
            : base(controllerContext.HttpContext.Request.Form)
        { }
    }

    public class ViewParameterValueProvider : IValueProvider
    {
        public ViewParameterValueProvider(IDictionary<string, object> paramters)
        {
            this.ViewParameters = paramters ?? new Dictionary<string, object>();
        }
        public IDictionary<string, object> ViewParameters { get; private set; }

        public object GetValue(string name)
        {
            if (ViewParameters.ContainsKey(name))
            {
                return ViewParameters[name];
            }
            return null;
        }
    }

    public class ValueProviderCollection : Collection<IValueProvider>, IValueProvider
    {
        public ValueProviderCollection()
        {

        }
        public ValueProviderCollection(IList<IValueProvider> list)
            : base(list)
        {

        }
        public object GetValue(string name)
        {
            object value = null;
            foreach (var item in this)
            {
                value = item.GetValue(name);
                if (value != null)
                {
                    break;
                }
            }
            return value;
        }
    }

    public class SessionValueProvider : IValueProvider
    {
        public SessionValueProvider(ControllerContext controllerContext)
        {
            this.Session = controllerContext.HttpContext.Session;
        }

        public HttpSessionStateBase Session { get; private set; }

        public object GetValue(string name)
        {
            if (Session != null)
            {
                return Session[name];
            }
            return null;
        }
    }

    public class MVCValueProviderWrapper : IValueProvider
    {
        System.Web.Mvc.IValueProvider valueProvider;
        public MVCValueProviderWrapper(System.Web.Mvc.IValueProvider valueProvider)
        {
            this.valueProvider = valueProvider;
        }

        public object GetValue(string name)
        {
            var result = valueProvider.GetValue(name);
            if (result != null)
            {
                return result.RawValue;
            }
            return null;
        }
    }
}

redpajama_set_name: RedPajamaGithub


text:
Miller Nash Assists Oregon State Bar in Defending Its Mission and Purpose
Miller Nash attorneys Elisa Dozono and Taylor Richman successfully argued for the dismissal of lawsuits challenging the Oregon State Bar's mandatory membership fees and activities that further its mission of serving justice by protecting the public in its regulatory role, promoting respect for the rule of law, improving the quality of legal services, and increasing access to justice.
Joe Vance Quoted in Vancouver Business Journal
Miller Nash Graham & Dunn partner Joe Vance was quoted in a Vancouver Business Journal article titled "Protectable Interests" on Friday, March 29, 2019.
West Coast law firm Miller Nash Graham & Dunn LLP has announced the promotion of seven new partners, effective January 1, 2019. The newly elected partners are based in three of the firm's growing offices and reflect a broad array of practice areas.
LeAnne Bremer Honored with Passing the Torch Award from the Washington Women Lawyers
Miller Nash Graham & Dunn LLP partner LeAnne Bremer was presented with the Passing the Torch Award from the Washington Women Lawyers on October 12 in Seattle, Washington.
Pro Bono Clinic Featured in Multnomah Lawyer
Miller Nash Graham & Dunn's Virtual Legal Aid Clinic was featured in an article for October's special Pro Bono issue of Multnomah Lawyer, the official newsletter of the Multnomah Bar Association.
Michelle Nisle Featured in Vancouver Business Journal
Miller Nash Graham & Dunn attorney Michelle Nisle was interviewed for the Vancouver Business Journal's "Up Close" feature, published on Friday, May 11, 2018.
Jollee Patterson Featured in Multnomah Lawyer
Miller Nash Graham & Dunn attorney Jollee Patterson was featured in a front-page article for the February issue of Multnomah Lawyer.
P.K. Runkles-Pearson Interviewed in the Portland Business Journal
Miller Nash Graham & Dunn partner P.K. Runkles-Pearson was interviewed for a Portland Business Journal article titled "Harassment in the Workplace: Five Portland Employment Lawyers on How Businesses Need to React," published on December 6, 2017.
Seth Row Interviewed in Portland Business Journal
Miller Nash Graham & Dunn partner Seth Row was interviewed by the Portland Business Journal for an article titled "Portland Insurance Execs on Insuring Against Losses When Disaster Strikes," published on September 28.
Best Lawyers® Recognizes 46 Miller Nash Graham & Dunn Attorneys
46 attorneys from Miller Nash Graham & Dunn offices in Oregon and Washington were selected from among their peers for inclusion in The Best Lawyers in America® 2017.


It may not be winter yet, but it's upon us, dear reader. In fact, it's so close we can smell it. And what does it smell like? Well, if we have our way, it'll smell a lot like Tuulia Talvio's roasted sweet potato and capsicum soup, the ideal thing to eat while wrapped up in bed, listening to rain tinkling outside. The recipe is gluten-free (as are all Tuulia's recipes), and is a bit extra-scrummy, because the veggies are roasted, rather than boiled. Ahh, the magic of food.


It has 12,000 different woodworking plans that 4 x 10 metal shed are very well organised, and easy to follow. The great thing about woodworking is that you don't need to be a professional carpenter to start making and carving objects out of wood. It will take some extra skill in the cutting department if you want to build a really nice one, 4 x 10 metal shed but cutting a simple bird house can be quite easy. The 4 x 10 metal shed answer is simply to get a set of plans; these will include a wide range of woodworking ideas for the hobbyist to tackle. Join the desktop's backboard and sides together from 4 x 10 metal shed underneath the desktop, using No. 8 wood screws, and glue the U-shaped frame to your desktop, using large clamps to hold the desktop and frame together. A simple wipe 4 x 10 metal shed on Oil/Varnish blend or Wipe on Polyurethane is easy 4 x 10 metal shed to apply and while it will teach you a valuable lesson to add to your arsenal, it won't test your patience. As you tighten down on the nut the toe clamp pulls the 4 x 10 metal shed leg in against the bed frame. If you want to find something that is going to be a conversation piece then just select a table with a clear glass top and a base that is an upside down aquarium. I'd like to see more ideas for pallets, as I've used them for animal pens, fences, etc. Select easy wood working projects for kids that are appropriate for your kids' age and skills, and don't forget to supervise them! Regardless of the type of such bed a customer chooses, a mattress is an essential part of purchasing any bed. There are ready made barn house plans to follow or you can buy a pole barn kit, complete with materials. In developing plans for a homemade sluice box, the more time you spend thinking about your design, the better.
After getting 4 x 10 metal shed permission, look for discarded exterior trim boards made of cedar or pine that can be rescued and reused to 10 shed 4 metal x make outdoor scrap wood projects such as window boxes and 4 x 10 metal shed birdhouses. The videos are organized in order of the type of wooden object being made in the video e.g. After drawing up the 4 x 10 metal shed 4 x 10 metal shed plans and determining the materials 4 x 10 metal shed x metal 10 4 shed I would need I got busy. Free woodworking plans, furniture plans at , Woodworking plans & furniture plans. Varnish is a protective coating that seals the wood and also gives it the final sheen. A 4 x 10 metal shed triplanar platform moves forward and backward, side to 4 x 10 metal shed side, and up and down all at the same time.
When the glue has dried, flip over the desktop so that the 1x3 border is now on the bottom, and apply wood filler to the seams on the top and edges of desktop. I've never had a problem with all the instructions inaccurate yet (knock on wood).
11.08.2014 at 14:55:47 Pieces of wood together to produce the napkin holder.
11.08.2014 at 14:48:28 The Kreg demo at woodworking shows someplace have been they.


text:
Orlando Philharmonic Orchestra Announces New 2020–2021 Season Plans
The past five months have been a time unlike any we have experienced before. The arts world has been rocked- not just here in Orlando, but across the globe. There are many challenges and opportunities ahead, but one thing is certain: we need live music in our lives, and the music will play on!
Our staff has worked tirelessly over the past 5 months to create innovative outlets to allow the Orlando Philharmonic Orchestra to fulfill its mission to enrich and inspire the diverse communities of Central Florida through the transformative power of music.
We have launched virtual lessons, an entirely virtual concert series entitled Summer Serenades, and started a weekly broadcast with WMFE to air archival recordings. We hope you have been able to enjoy our music over your summer and welcomed our musicians, virtually, into your home. While launching these new musical offerings, we have also been in close communication with our venue partners and local authorities to safely plan our upcoming 2020–2021 Season. We know that when we return to the concert hall, in-person events will look very different.
We've learned that the timing of our move to Steinmetz Hall will be later than anticipated. Further, as recently announced by the Dr. Phillips Center for the Performing Arts, the Bob Carr Theater will remain closed for the foreseeable future and will not be available for our concerts. To keep the music playing safely, we will be relocating some of our Fall 2020 events to other venues.
We are excited about these new opportunities to safely experience live music! Here are all the details.
The first FAIRWINDS Classics Series concert will be performed on Saturday, September 26 at 7:30 p.m. at Exploria Stadium in Downtown Orlando. Classics 2 and 3 will move to Calvary Orlando in Winter Park on Saturday, October 10 and Saturday, November 7 at 7:30 p.m. The Focus Series and Symphony Storytime Series performances will remain at The Plaza Live, as previously announced.
We are working with our venue partners to determine the best location for our Pops Series performances and will announce the venue for those performances at a later date.
Current 2020–2021 Philharmonic Subscribers will have first access to these events. Single tickets will be made available on an event-by-event basis, when possible.
Our first priority is the safety of our patrons, staff, and performers. The Philharmonic will follow the guidance of our state and local authorities, and patrons will be required to follow all county and state public health guidelines. These will include social distancing, the wearing of face coverings, and temperature checks.
Social distancing for patrons will mean changes to seating, compared to what you may have experienced in the past at the Bob Carr Theater. This will be a different experience for all of us, and we are grateful for your patience and understanding. Again, our top priority is the safe presentation of live music under truly unprecedented circumstances.
Due to the need to have social distancing on stage as well as in the audience, we have had to make modifications to the number of musicians we present on stage. Maestro Eric Jacobsen has worked hard to revise our 2020–2021 Classics Series programming so that we may enjoy great music with an appropriately distanced orchestra. We're really excited about what Eric has done and know you will be as well.
Thank you for your continuing support of the Orlando Philharmonic Orchestra. In this challenging and unusual time, your support means a great deal. We look forward to welcoming you back to the concert hall and hearing the music play on!
Categories Classics Series, Concerts, Events, Focus Series, Guest Artist, Music Director, News, Plaza, Pops Series, Symphony Storytime Series, The Plaza Live Post navigation
Orlando Philharmonic Orchestra receives 2020 New Music USA Project Grant
Orlando Philharmonic Orchestra to be First Professional Orchestra to Perform a Full Concert in an American Soccer Stadium


text:
Disney•Pixar Releases First Look at 'Incredibles 2'Disney•Pixar released their first teaser trailer for their upcoming animated sequel to 2004's 'The Incredibles'...
Disney•Pixar Releases 'Coco' Final TrailerVIDEO: Emeryville-based Pixar released the final full length trailer for their upcoming animated film, "Coco"
Pixar's John Lasseter To Drive at Sonoma RacewayThe Chief Creative Officer of Pixar and Disney will kick off festivites at the Toyota/Save Mart 350 over the weekend...
Watch The New Trailer For 'Olaf's Frozen Adventure'VIDEO: "Frozen 2" is still far off, but fans can look forward to this Christmas' "Olaf's Frozen Adventure," thanks to a new trailer...
Disney•Pixar Releases New Trailer For 'Coco'VIDEO: Disney•Pixar has released a full length trailer for their next animated film...
Don Rickles Dies Before Voicing 'Mr. Potato Head' In 4th 'Toy Story' MovieThe legendary comedian may yet be heard as the famous spud in the next "Toy Story" movie...
Disney•Pixar's 'Cars 3' Preview Shows 'Lightning McQueen' In Grave DangerVIDEO: Watch the first teaser for Disney/Pixar's upcoming "Cars 3"
Disney•Pixar Releases New 'Finding Dory' TrailerThe sequel to 2003's Disney•Pixar animated film 'Finding Nemo' has released a new trailer online...
WATCH: Pixar's 'The Good Dinosaur' TrailerCheck out the new trailer for "The Good Dinosaur" premiering in theaters November 25...
Disney•Pixar Reveals New Trailer For Upcoming Dinosaur FilmThis marks the 2nd film to release in 2015 for the Emeryville-based animation studio...
Star Wars Joins The Disney Infinity UniverseExpect to see Yoda interact with Mickey Mouse in the upcoming installment of Disney Infinity...
Disney Premieres Second Trailer For SF-Based Film 'Inside Out'Inside Out premieres in theaters on June 19, 2015.
Pixar Reveals A Few Details About 'Finding Dory' (Including A Release Date!)The film will hit theaters on July 17, 2016.
Disney Reveals Teaser Trailer For Brad Bird's 'Tomorrowland'VIDEO: Directed by Brad Bird of Pixar fame, the upcoming film stars George Clooney...
'Frozen' Tops $1 Billion Mark WorldwideAfter taking home 2 Oscars, Disney's "Frozen" has broken the $1 billion mark, RadioAlice reports...
5:00 PMThe People's Court


text:
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Mac Torrents: Download macOS X Apps, iOS, Software and Games Torrent
New Torrents
MediaHuman YouTube Downloader 3.9.9.16 (3005)
View File List
28 MB MediaHuman YouTube Downloader 3.9.9.16 3005 TNT.zip
Tracked By
http://182.176.139.129:6969/announce
Working(0) | Not working(0)
There are so many interesting things to be found on YouTube, but you can�t download the videos or save them as audio files by default. That�s why we developed YouTube Downloader. This app will help you to accomplish video downloads quickly and without hangups. Using our program you can simply download an entire YouTube playlist or channel at once and watch it whenever and wherever you want.
The application has many other convenient and practical functions for you to explore and enjoy. Give it a try, download it now!
Supports Ultra High resolutions including 4K & 8K
Downloads entire playlists and channels
YouTube, Vimeo, Dailymotion, Soundcloud and much more
Extracts audio track and saves it as MP3
Supports exporting to iTunes
Works on all modern platforms (macOS, Windows and Ubuntu)
Playlists and channels
The program supports downloading of all videos of a playlist or a channel. And there�s also an option to track the selected channel or playlist and download new clips as they are uploaded.
You can configure the program to automatically add downloaded movies to your iTunes library. You can also pick a playlist where the downloaded video should be added.
HQ, HD, 4K or 8K
The program supports all available resolutions, be that 720p, 1080p, 4K or 8K. The choice is up to you.
Monitor the clipboard
The program keeps an eye on the clipboard and as soon as it spots a supported link there, it automatically adds this video into the download queue.
Quality of the original
You can choose to save videos in the original quality (usually in MP4 format), without any modifications. In this case, the clip you get is exactly the same as the one its author uploaded.
Simple tag editor
The app automatically detects the artist and the title of a video and saves them to the downloaded file. And you can easily change them later.
Not just YouTube
The program supports Vevo.com, Vimeo, Dailymotion, Facebook, UOL, VKontakte, SoundCloud and a lot of other sites. So you can download video from these websites as easy as you do from YouTube.
The app features a 100% drag&drop support. Just drag the link to a video with your mouse and drop it to the main window of the program, or to its dock icon on Mac.
Multi-language interface
The app is translated into: Arabic, Armenian, Azerbaijani, Bulgarian, Catalan, Chinese (Taiwan), Croatian, Czech, Danish, Dutch, English, Esperanto, French, German, Greek, Hebrew (Israel), Hungarian, Indonesian, Italian, Japanese, Korean, Latvian, Lithuanian, Malay, Norwegian Bokm�l, Polish, Portuguese, Portuguese (Brazil), Romanian, Russian, Spanish, Swedish, Turkish, Vietnamese.
Compatibility: OS X 10.8 or later 64-bit
Web Site: http://www.mediahuman.com/
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text:
Articles and media
Russian Conception of Globalization - Sustainable Development of Humanity or another Alternative to Western Globalization?
What is Russia? The Russian Federation is the largest state in the world, consisting of more than 80 regions, and is home to over 145 million people. It is composed of many nationalities and religi...
Video: Development — an alternative to the tunnel scenarios of social degradation (documentary)
On the 12th of April, 2014 at 10:00 at the Russian Centre of Science and Culture in Brussels, which is representative of the Federal Agency "Rossotrudnichestvo" in the Kingdom of Belgium, an interna...
The Saint-Petersburg Consensus – a new economic policy for the World
This document in Russian, English and French languages has been sent worldwide to the largest international organizations, heads of state, financial ministries, ministries of economic development and ...
Energy, Science, Education: Issues and Interdependencies
This article was written based on the presentation given by Alexei Mankovski at the international conference "Youth, Science, Innovation" that took place on April 21-23 2014 in the city of Kazan, Russ...
Revolution for Dummies. On air in Ukraine.
This series of articles is aimed to offer an alternative analysis of the 2014 'Maidan' revolution in Ukraine. We'll look through technologies of revolution making in a particular country and analyze...
What is the East suggesting to the world at the new stage of globalization?
When new problems arise in one particular country or a regional civilization, people escape the region, hoping to find peace of mind and wealth abroad. Many social groups in the Western society have...
Anatomy of the dominant conception of Globalization
The notion of Globalization Nowadays, the term "globalization" is used quite often, but seldom there is definite understanding behind it. Therefore, before discussing problems concerning globalizat...
Who is winning at the new stage of globalization?
On November 22, 2013 a conference held by the international non-profit organization "New Youth Policy" took place at the Russian Centre of Science and Culture in Brussels. The subject: "Globalizati...
What kind of candidates do we need?
On the occasion of the past local government elections in Estonia Every autumn campaign posters of candidates for local government could be seen everywhere. The posters show that the number of politi...


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LISA Pathfinder commissioning simulation
While the spacecraft is en route to its operational orbit, scientists and engineers are checking that everything on LISA Pathfinder is working well. Watch how they trained for that.
This timelapse video shows teams from ESA and Airbus Defence and Space (the prime contractor for LISA Pathfinder) carrying out a simulation of the commissioning of the LISA Technology Package, the scientific heart of the mission. The simulation took place at ESA's European Space Operations Centre in Darmstadt, Germany, on 23 and 24 September 2015. The video spans about two hours on the morning of 23 September.
The scientists and engineers are grouped to represent the different spacecraft subsystems.
In the foreground are Paul McNamara, LISA Pathfinder ESA Project Scientist, and Stefano Vitale, LISA Pathfinder Principal Investigator. At the same desk, to their left, is the representative of the Science and Technology Operations Centre (STOC) station, and further to the left the following subsystems are represented: Optical Metrology System (OMS), UV Light Unit (ULU), Data Management Unit (DMU), and Inertial sensor front-end electronics (ISS FEE).
On the right side are representatives of the ESA project team, Airbus Defence and Space Ltd and Airbus Defence and Space GmbH (from top to bottom, respectively). At the centre of the room is the 'hot desk' space, where the team members can discuss and work on specific issues.
Media use and copyright:
© ESA


Here is a list of the plants that we offer. Availability varies by season. If you are interested in something that is not on this list give us a call and we can probably find it at local growers around Forest Hill.


And come to that the dangers of commenting on press articles on line. Recently I posted something using Disqus: it was in response to an article in a Squamish newspaper about the proposed LNG plant. Oddly, nothing in the article, or in the response to that time spoke to the source of the gas. That will come from an expansion of fracking – the practice of releasing hydrocarbons from "tight formations" which has been expanded very rapidly in North America in recent years. The process creates fractures in the oil and gas bearing rocks by injecting water and mix of chemicals under high pressure.
To be clear, I oppose any expansion of fossil fuel use. There is only one way that we are going to be able to slow down our current headlong rush to global catastrophe and that is to Leave It In The Ground. Most of the reserves of oil, gas and coil must not be extracted and burned. Fortunately, the alternative renewable resources are both economically and environmentally attractive – and are getting cheaper. There is much more employment potential in renewables too, so the previously perceived "choice" between the environment or the economy is now a false dichotomy.
Expansion of LNG export terminals in BC seems increasingly unlikely based on any realistic analysis of the finances but Christy Clark has yet to concede this, and is perfectly capable of continuing to increase the public subsidy of this folly. We are actually paying foreign corporations to exploit this resource, which would otherwise be unmarketable. So if the GHG use of fossil fuels is not persuasive enough, the record of fracking needs to be examined. There are two points I made – the first is that methane is released by fracking in a manner which makes it difficult to capture – or even measure. Since methane is a far more powerful greenhouse gas than CO2 that is cause for caution in itself. But there is also the effect of putting injecting water into the ground. Poisoning wells is the least of it (though the youtube videos of setting kitchen faucets alight seem entertaining). We live in a seismically unstable region. There will be a huge earthquake out underneath the ocean, probably south of Haida Gwai. (I wrote that last sentence on April 23 at 10:45. This morning there was an M6.2 in exactly that location but without a tsunami.) With huge a tsunami and lots of damage. But there is plenty of risk of on shore activity too: it will be smaller but also destructive in nature.
Now of course as soon as my post appeared the on line trolls leapt on it. At least some of them are going to be in the pay of the gas drillers or the proponents of LNG expansion. They are spending a fortune on PR efforts around pipeline and terminal expansion – and no contrary opinions must be allowed to go unchallenged. A Google search for "fracking in bc" turns up nearly a million hits.
I want to draw your attention to Oklahoma. There have been a lot of earthquakes recently in Oklahoma, and the spin doctors have been doing their best to deflect responsibility away from fracking. The state government seemed to have been persuaded. Up until now. The state is now admitting that fracking causes the earthquakes. There is also more coverage of the wider impact from the New York Times.
If you do not want to admit that global warming is a problem that is caused by burning fossil fuels, then I think you are unreachable by reason or argument. But then that process of proof by belief in a political doctrine appears to have taken hold with the Conservative faithful here as it has in the US. You can probably also cheerfully ignore the impact of poisoning the water supply: after all it is unlikely to affect us here and we have been seemingly unconcerned about the state of the water on reserves – especially those impacted by the tar sands. But the risk of increasing earthquakes ought to be something you take seriously here. Even though our present government seems to be quite content to leave schools in Vancouver vulnerable to the inevitable.
Time for BC Geothermal Energy?
I got some content today from the US Geological Service. It is intended as a "feature" and covers all their services, with a bent towards the upcoming Earth Day. Of course, on this blog every day is earth day, and my content needs to be local. One of the things I have been banging on about is geothermal energy. We have all sorts of hot springs around BC, and I have even spent time around Harrison Hot Springs. It occurred to me then that there must be more that can be done with this resource than just providing hot tubs. So here is the USGS piece on geothermal energy.
Deep within the Earth's crust lies an extremely important but underutilized renewable energy resource: geothermal energy. In 2008, the USGS released a national assessment of geothermal power resources, showing more than 550,000 Megawatts–electric power–generating potential. Since then, the USGS has continued to research and assess geothermal power potential all over the country.
But of course what we need is information about BC – and that is provided by the BC Sustainable Energy Association though their page on the subject dates from 2005, which suggests to me that it probably needs updating. I did hear that there has been a great deal of drilling done in BC in recent years in pursuit of shale gas, and all that information was lodged with BC's energy ministry. It contains, of course, lots of data about the availability of geothermal energy which was discovered when looking for something else.
Meanwhile, our provincial government continues with its quixotic search for an export driven economic bonanza from LNG. And refuses to raise its carbon tax. BC and Alberta being the only two provinces that did not attend the recent provincial "climate change summit".
This talk was given on April 1st. I think it is a great credit to SFU that they have managed to get it onto their youtube channel so quickly. I cannot now recall why I did not attend this talk in person. Perhaps it was because Michael (I may call him, Michael, mayn't I?) has his own blog and I should not steal his content. I do remember twitting him prior to the talk to make sure that he covered transportation in this talk. He said that he might include something on walking. Well of course a great deal of it is about transportation. We share the same enthusiasms – for pedestrian streets for instance. I started the flickr group Places Without Cars in 2008. And trams.
I warn you in advance that he talks for over an hour and the video does not include any of the discussion which I am sure must have followed. But it is indeed well worth your time.
By the way, Translink did look at increasing the number of ferries across the inlet. Unfortunately the outcome was that few of the possible routes tested offered any time savings – which, of course, is entirely predictable. The reason we don't have scramble crossings here any more, he said, was that they slow the cars down. Which, of course, is precisely the point. And of course there is a scramble crossing in Steveston.
What we do not seem to understand is the reason we think other places work better when we visit them is that as tourists we actually want to slow down and enjoy the place. Unfortunately that is not comprehended by the people who plan our transportation systems who are still hung up on speed as the decisive factor.
There are indeed decorated utility boxes all over Vancouver. I was sure I had pictures of some of them. Maybe I will find them later and add them.


ROLEX Oyster Perpetual Date 1500 circa 1967. Featuring 34mm diameter case with smooth bezel, acrylic crystal, and original excellent silver dial with applied silver indexes and silver baton hands. The stainless steel case is in fine condition with a Rolex Oyster stainless bracelet. This excellent timepiece is well running by a caliber 1570 automatic movement with sweep seconds and date.
Rolex Oyster Perpetual Date 1500 men's wrist watch is without a doubt a classic vintage watch; versatile and understated. With its Rolex-stamped, original folded- stainless Oyster link bracelet and clasp, it represents the very best of the brand's quality and tradition. The Rolex Oyster was first introduced in 1926. Beginning as the first waterproof and dust-proof wristwatch designed specifically for professional use.
The dial of this Rolex Oyster Date is in exceptionally good condition, has a brushed silver finish, applied steel index markers, with classic 'ROLEX' and 'OYSTER PERPETUAL DATE' text as well SUPERLATIVE CHRONOMETER OFFICIALLY CERTIFIED referenced on it. It also has a Rolex crown and comes equipped with its folded-link Rolex Oyster bracelet and clasp. This particular case dates to 1967 (serial 231 XXXX).
This fine timepiece houses Rolex's caliber 1570 'Officially Certified Superlative Chronometer' grade automatic movement. The mechanism features a lever escapement, 26 jewels, mono-metallic balance, adjusted to 5 positions and KIF shock-absorber, beating at a rate of 19,800 BPH. A distinctive characteristic of Rolex's Cal. 1570 is the use of brightly-colored, pink reverse gears in the automatic winding module.
The evolution of the Rolex Oyster inspired some of the most historically important wristwatches, surviving the harshest of conditions. From 35,000 ft. below the surface of the Pacific Ocean, to the summit of Mount Everest, without losing a beat. There aren't many mechanical timepieces that have contributed more to the advancement of horological design, nor clearer defined Rolex's reputation for excellence. Many have tried to replicate its success, but no manufacturer since, has consistently produced mechanical timepieces that endure everyday wear as well as a Rolex.
This watch will make you feel very proud while wearing it and you will be satisfied to know that you chose elegance and quality.


Calicut University Registrar Dr.T.A.Abdul Majeed has said the university will enhance its competitive examination coaching centres.He was inaugurating the university Information and Guidance Centres one month free P.S.C coaching classes at the campus.
Apart from conferring degrees, making students capable to grab good jobs also is the objective of the university-he said.
It is the effort of the varsity to nurture the skill in the youth.
Time has past that students merit were being considered on the basis of certificates alone.
Job providers are seeking the best students having employability-he pointed out.
A systematic practice is necessary to achieve this goal.
He urged the students to utilize the training facilities the university provide and grab good job opportunities and make that useful for the well-being of the society.
During the one month coaching camp,students from the northern district are attending.
Employment Information and Guidance Bureau Chief Dr.C.C.Harilal presided over the function.
Malappuram District Employment Officer K.Janardhanan spoke.
Deputy Chief Domitilla George welcomed the gathering and C.J.Nelson expressed vote of thanks.
This News was posted on Tuesday, September 29th, 2015 at 11:58 am and is filed under Education.