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Justia Patents Stacked ArrangementUS Patent for Stacked semiconductor package with localized cavities for wire bonding Patent (Patent # 8,294,251)
Stacked semiconductor package with localized cavities for wire bonding
Jun 30, 2008 - SanDisk Technologies Inc.
A semiconductor die and a low profile semiconductor package formed therefrom are disclosed. The semiconductor package may include at least first and second stacked semiconductor die mounted to a substrate. The first and/or second semiconductor die may be fabricated with localized cavities through a bottom surface of the semiconductor die, along a side edge of the semiconductor die. The one or more localized cavities in a side take up less than the entire side. Thus, the localized cavities allow low height stacking of semiconductor die while providing each die with a high degree of structural integrity to prevent cracking or breaking of the die edge during fabrication.
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CROSS-REFERENCE TO RELATED APPLICATION
The following application is cross-referenced and incorporated by reference herein in its entirety:
U.S. patent application Ser. No. 12/165,297, entitled "Method of Fabricating Stacked Semiconductor Package with Localized Cavities For Wire Bonding," by Takiar, et al., filed on even date herewith.
1. Field of the Invention
Embodiments of the present invention relate to a low profile semiconductor device and method of fabricating same.
2. Description of the Related Art
The strong growth in demand for portable consumer electronics is driving the need for high-capacity storage devices. Non-volatile semiconductor memory devices, such as flash memory storage cards, are becoming widely used to meet the ever-growing demands on digital information storage and exchange. Their portability, versatility and rugged design, along with their high reliability and large capacity, have made such memory devices ideal for use in a wide variety of electronic devices, including for example digital cameras, digital music players, video game consoles, PDAs and cellular telephones.
While a wide variety of packaging configurations are known, flash memory storage cards may in general be fabricated as system-in-a-package (SiP) or multichip modules (MCM), where a plurality of die are mounted on a substrate in a stacked configuration. An edge view of a conventional semiconductor package 20 (without molding compound) is shown in prior art FIGS. 1 and 2. Typical packages include a plurality of semiconductor die 22, 24 mounted to a substrate 26. Although not shown in FIGS. 1 and 2, the semiconductor die are formed with die bond pads on an upper surface of the die. Substrate 26 may be formed of an electrically insulating core sandwiched between upper and lower conductive layers. The upper and/or lower conductive layers may be etched to form conductance patterns including electrical leads and contact pads. Wire bonds are soldered between the die bond pads of the semiconductor die 22, 24 and the contact pads of the substrate 26 to electrically couple the semiconductor die to the substrate. The electrical leads on the substrate in turn provide an electrical path between the die and a host device. Once electrical connections between the die and substrate are made, the assembly is then typically encased in a molding compound to provide a protective package.
It is known to layer semiconductor die on top of each other either with an offset (prior art FIG. 1) or in a stacked configuration (prior art FIG. 2). In the offset configuration of FIG. 1, the die are stacked with an offset so that the bond pads of the next lower die are left exposed. Such configurations are shown for example in U.S. Pat. No. 6,359,340 to Lin, et al., entitled, "Multichip Module Having A Stacked Chip Arrangement." An offset configuration provides an advantage of convenient access of the bond pads on each of the semiconductor die. However, the offset requires a greater footprint on the substrate, where space is at a premium.
In the stacked configuration of FIG. 2, two or more semiconductor die are stacked directly on top of each other, thereby taking up less footprint on the substrate as compared to an offset configuration. However, in a stacked configuration, space must be provided between adjacent semiconductor die for the bond wires 30. In addition to the height of the bond wires 30 themselves, additional space must be left above the bond wires, as contact of the bond wires 30 of one die with the next die above may result in an electrical short. As shown in FIG. 2, it is therefore known to provide a dielectric spacer layer 34 to provide enough room for the wire bond 30 to be bonded to the die bond pad on the lower die 24.
Referring now to prior art FIGS. 3 and 4, instead of a spacer layer 34, it is also known to etch a trench 40 along an edge of the bottom (inactive) surface 42 of an upper die, such as die 22. The trench 40 allows two die to be stacked directly on top of one another, without a spacer layer, while still having space for a wire bond 30 off of the lower die. As seen in FIG. 4, the trench 40 has conventionally been formed along an entire edge of a die. An example of a trench formed along an entire edge is seen for example in U.S. Pat. No. 7,309,623 to Tan, which shows a trench having vertical and horizontal sidewalls (as is also shown in prior art FIG. 4). A further example of a trench formed along an entire edge is seen for example in U.S. Pat. No. 5,804,004 to Tuckerman et al., which shows a trench having an angled or beveled sidewall. Both of these patents are incorporated by reference herein.
One disadvantage to prior art semiconductor packages including a trench along an entire edge is that the formation of the trench structurally weakens the semiconductor die. Namely, where a trench leaves only a thin amount of material above the trench, the die may crack or break above the trench. This may be especially true during the encapsulation process, where large forces are exerted on the semiconductor die in order to properly encase the die in the molding compound.
Embodiments of the present invention relate to a semiconductor die and a low profile semiconductor package formed therefrom including at least first and second stacked semiconductor die mounted to a substrate. The first and/or second semiconductor die may be fabricated with localized cavities through a bottom surface of the semiconductor die, along a side edge of the semiconductor die. A given side of the semiconductor die may include no localized cavities, or one or more localized cavities. Where a side of the die includes one or more localized cavities, the localized cavities take up less than the entire side.
When assembled into a die stack on a substrate, the wire bonds off of a first semiconductor die are received within the localized cavities of the semiconductor die mounted on top of the first die. Thus, die may be stacked directly on top of each other without the wire bonds from the first die electrically shorting against the semiconductor die mounted on the first die. As the cavities are localized, and do not take up an entire side of a die, the localized cavities allow low height stacking of semiconductor die while providing each die with a high degree of structural integrity to prevent cracking or breaking of the die edge during fabrication.
In embodiments, the positions of the localized cavities in the bottom surface of a die correspond to the positions of the die bond pads in the top surface of the die. Thus, a plurality of such semiconductor die may be stacked atop each other, with the bond pads, and wire bonds extending therefrom, aligning within the localized cavities of the next higher semiconductor die in the stack.
A semiconductor die may also include a localized cavity spaced inward from each of the sides of the semiconductor die. In embodiments including such a localized cavity, a component such as a passive component or a secondary semiconductor die may be mounted on the surface beneath the localized cavity and received within the localized cavity. The cavity serves to isolate the component from the die including the cavity. Such a configuration increases the flexibility of where components may be mounted, for example on the substrate.
DESCRIPTION OF THE DRAWINGS
FIG. 1 is a prior art edge view of a conventional semiconductor device including a pair of semiconductor die stacked in an offset relation.
FIG. 2 is a prior art edge view of a conventional semiconductor device including a pair of semiconductor die stacked in an overlapping relation and separated by a spacer layer.
FIG. 3 is a prior art edge view of a conventional semiconductor device including a pair of semiconductor die stacked in an overlapping relation with the upper die including a trench along a lower edge of the semiconductor die.
FIG. 4 is a prior art bottom perspective view of a conventional semiconductor die with a trench as shown in FIG. 3.
FIG. 5 is a flowchart for forming a semiconductor die according to embodiments of the present invention.
FIG. 6 is a top view of a semiconductor wafer from which a plurality of semiconductor die according to embodiments of the present invention may be fabricated.
FIG. 7 is a top view of a semiconductor die during fabrication.
FIG. 8 is a perspective view of the semiconductor die of FIG. 7 during fabrication.
FIG. 9 is a top view of a semiconductor die including localized cavities formed in a bottom surface of the semiconductor die.
FIG. 10 is a bottom perspective view of the semiconductor die of FIG. 9 including localized cavities formed in a bottom surface of the semiconductor die.
FIG. 10A is a cross-sectional view through line 10-10 in FIG. 10.
FIG. 10B is a cross-sectional view of an alternative embodiment of a localized cavity seen from the same perspective as FIG. 10A including a beveled surface.
FIG. 11 is an edge view of a semiconductor die including a localized cavity buried within a center portion of the bottom surface of the semiconductor die.
FIG. 12 is a bottom perspective view of the semiconductor die of FIG. 11 including a localized cavity formed within a center portion of the bottom surface of the semiconductor die.
FIG. 13 is a flowchart showing the fabrication of a semiconductor device according to the present invention.
FIG. 14 is a perspective view of a semiconductor device during fabrication including wire bonds positioned within the localized cavity of the next adjacent semiconductor die.
FIG. 15 is an edge view of a finished semiconductor device according to an embodiment of the present invention.
FIG. 16 is a top view including a localized cavity and wire bond configuration according to an alternative embodiment of the present invention.
FIG. 17 is an end view of the semiconductor device according to the alternative embodiment of FIG. 16.
FIG. 18 is a top view including a localized cavity and wire bond configuration according to a further alternative embodiment of the present invention.
FIG. 20 is a top view of a semiconductor device according to an alternative embodiment including a localized cavity within a central portion of the semiconductor die.
FIG. 21 is a cross-sectional view of the semiconductor device according to the alternative embodiment of FIG. 20.
FIG. 22 is a perspective view of an alternative embodiment showing a semiconductor device during fabrication including wire bonds positioned within localized cavities of a spacer layer between semiconductor die.
Embodiments will now be described with reference to FIGS. 5 through 22, which relate to a low profile semiconductor package. It is understood that the present invention may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the invention to those skilled in the art. Indeed, the invention is intended to cover alternatives, modifications and equivalents of these embodiments, which are included within the scope and spirit of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be clear to those of ordinary skill in the art that the present invention may be practiced without such specific details.
The terms "top" and "bottom" and "upper" and "lower" are used herein for convenience and illustrative purposes only, and are not meant to limit the description of the invention inasmuch as the referenced item can be exchanged in position.
A process for forming semiconductor die in accordance with the present invention will now be described with reference to the flowchart of FIG. 5, and the various top and perspective views of FIGS. 6 through 12. FIG. 6 shows a top view of a semiconductor wafer 100 for batch processing a plurality of semiconductor die 102 (one of which is labeled in FIG. 6). Each die 102 may be formed with bond pads 104 as shown for example in the enlarged view of die 102 in FIGS. 7 and 8. Bond pads 104 are used to electrically couple the semiconductor die 102 to another semiconductor die, or to a printed circuit board, leadframe or other substrate as explained hereinafter. While bond pads 104 are shown along all edges of die 102 in FIGS. 7 and 8, it is understood that the bond pads 104 may be formed along one edge, two opposed or adjacent edges or three edges in further embodiments. It is understood that the number of bond pads 104 along a given edge of the semiconductor die 102 may be more or less than is shown in the figures.
Referring now to the flowchart of FIG. 5, the integrated circuit components of semiconductor die 102 may be formed on wafer 100 in step 200 by known processes such as film deposition, photolithography, patterning, and diffusion of impurities. Die bond pads 104 may be formed in respective die in step 202 by known processes including but not limited to plating, evaporation, screen printing, or various deposition processes.
In accordance with the present invention, localized cavities may next be formed in the back (inactive) surface of the die 102 on wafer 100 in step 210. Such localized cavities 110 are seen for example in phantom in the top view of FIG. 9 and in the bottom perspective view of FIG. 10. The localized cavities 110 may be formed by a variety of known processes, including for example chemical wet etch, dry etch, laser ablation or other chemical or mechanical means which controllably remove portions of the back surface of the die 102. In order to fabricate the localized cavities, the top (active) surface of the wafer 100 may be secured to a chuck so that one of the above-described processes may be performed on the back surface to define the localized cavities for each semiconductor die in the wafer 100.
The positions of the localized cavities 110 in the bottom surface of the die 102 correspond to the positions of the wire bond pads 104 in the top surface of the die 102. That is, the localized cavities 110 are formed on the bottom surface of the die 102, directly beneath the bond pads 104 on the top surface of the die 102. As explained hereinafter in greater detail, a plurality of die having the same configuration of die bond pads 104 and localized cavities 110 may be stacked directly on top of each other, without a spacer layer, and the localized cavities 110 allow wire bonding of lower die without electrical shorting of the wires bond against the next upper die.
The length dimension of each localized cavity 110 may vary, but may in general be slightly larger than the grouping of contact pads formed thereabove on the opposite surface of the die. Thus, the length of a localized cavity 110 beneath a single contact pad (such as contact pad 104a) may be smaller than the length of a localized cavity 110 beneath a plurality of contact pads (such as contact pads 104b). It is understood that all localized cavities may have the same length (for example the length of the largest grouping of contact pads 104) in alternative embodiments.
FIG. 10A shows a cross-sectional view through line 10-10 in FIG. 10. The horizontal depth dimension, x, of each localized cavity 110 perpendicular to an edge of a die 102, and the vertical depth dimension, y, of each localized cavity 110 perpendicular to the lower surface of a die 102, may vary in alternative embodiments. However, the horizontal and vertical depth dimensions of each localized cavity may be sufficient to allow one or more wire bonds to be connected to a first semiconductor die 102 and positioned within the localized cavities 110 of a second semiconductor die 102 mounted on the first die without contacting the second die 102. Instead of having horizontal and vertical surfaces, any localized cavity 110 may instead be defined in part by an angled or beveled surface 112 forming an oblique angle with a bottom surface of the die 102, such as shown in FIG. 10B (seen from the same perspective as the cross-section of FIG. 10A).
As seen in the figures, the cavities 110 are localized. That is, no cavity 110 extends along an entire length of an edge of a die 102. Where a side includes a number of localized cavities, the localized cavities together in the side are less than the overall length of the side. Thus, the localized cavities 110 allow low height stacking of semiconductor die while providing each die with a high degree of structural integrity to prevent cracking or breaking of the die edge during fabrication.
Referring to the top view of FIG. 11 and the bottom perspective view of FIG. 12, in addition to or instead of the localized cavities 110 along one or more edges of the die 102, a localized cavity 114 may be formed within an interior of the die 102. That is, a cavity 114 may be formed down into the back surface of the die 102 and spaced from each of the edges of die 102. As explained in greater detail below, such cavities 114 in a semiconductor die may be used to receive passives or secondary die that are mounted on a surface beneath the semiconductor die. The surface may be that of a lower die or a substrate.
In a step 212, a backgrind process may be performed on the back (inactive) surface of wafer 100 as is known in the art to thin the die 102 to the desired thickness. Although a single die 102 is shown in FIGS. 7 through 12, the above-described steps are performed on all of the die 102 while still on the wafer 100. In step 216, each of the processed die may be singulated from wafer 100. Typically only memory die are stacked atop each other within a semiconductor package, so die 102 may typically be memory die such as flash memory. However, it is understood that the type of semiconductor die formed as described above may vary.
A process for forming a semiconductor package in accordance with the present invention using the semiconductor die 102 described above will now be explained with reference to the flowchart of FIG. 13, and the various views of FIGS. 14 through 21. Referring initially to FIG. 14, first semiconductor die 102a may be mounted on a substrate 120 in a step 300. The die 102a may be mounted to substrate 120 via a die attach adhesive in a known adhesive or eutectic die bond process. The die 102a shown in FIG. 14 does not include localized cavities 110 (because die 102a is the bottom die). Although unnecessary, die 102a may include localized cavities 110 in alternative embodiments, for example where the bottom die 102a is processed from a wafer in the same manner as the other die in the die stack which include localized cavities 110.
Although not shown, substrate 120 may be part of a panel of substrates so that the semiconductor packages according to the present invention may be batch processed for economies of scale. Although fabrication of a single semiconductor package is described below, it is understood that the following description may apply to all packages formed on the substrate panel. The substrate 120 may be a variety of different chip carrier mediums, including a PCB, a leadframe or a tape automated bonded (TAB) tape. Where substrate 120 is a PCB, the substrate may be formed of a core having top and/or bottom conductive layers formed thereon. The core may be various dielectric materials such as for example, polyimide laminates, epoxy resins including FR4 and FR5, bismaleimide triazine (BT), and the like.
The conductive layers may be formed of copper or copper alloys, plated copper or plated copper alloys, Alloy 42 (42FE/58NI), copper plated steel or other metals or materials known for use on substrates. The conductive layers may be etched into a conductance pattern as is known for communicating signals between the semiconductor die 102 and an external device (not shown). Substrate 120 may additionally include exposed metal portions forming contact pads 122 on an upper surface of the substrate 120. Where the semiconductor package is a land grid array (LGA) package, contact fingers (not shown) may also be defined on a lower surface of the substrate 120. The contact pads 122 and/or contact fingers may be plated with one or more gold layers, for example in an electroplating process as is known in the art.
After semiconductor die 102a is affixed to substrate 120 in step 200, wire bonds 130 may be attached between die bond pads 104 on die 102a and contact pads 122 on substrate 120 in a step 302. The wire bonds 130 may be formed in a known wire bond process such as for example forward or reverse ball bonding. In the embodiments shown in the figures, wire bonds 130 would be provided along all four edges of die 102a, but it is understood that one or more edges of die 102a may not include bond pads 104 or wire bonds 130 in further embodiments.
In accordance with the present invention, the localized cavities 110 allow multiple semiconductor die to be stacked in a completely overlapping relation, without having to space the overlapping die with a spacer layer or the like. Accordingly, in step 310, a second semiconductor die 102b may be affixed atop semiconductor die 102a using a known die attach adhesive. When the die 102b is mounted atop die 102a, the wire bonds 130 from the bottom die 102a fit within the localized cavities 110 on the underside of the die 102b. Thus, the wire bonds 130 from the die 102a do not contact or electrically short against die 102b. In this manner, the localized cavities allow die 102b to be mounted directly atop die 102a without the use of a spacer layer. In step 312, die 102b may be wire bonded to the substrate 120 with a second set of wire bonds 130 in a manner similar to that described above.
As indicated by the dashed arrow in the flowchart of FIG. 13, steps 310 and 312 may be repeated to add additional die on top of the die stack in the same manner that die 102b was mounted atop die 102a. FIG. 14 shows one additional die 102c mounted on the die stack (without wire bonds), but the die stack may include only two die or more than three die in further embodiments. For each stacked die, the wire bonds of a die in the stack fit within the space created by the localized cavities 110 of the next die mounted thereon. Thus, the stack may include a number of die while still having a low overall height.
In the above-described embodiments, the wire bonds 130 may be uncoated gold, though it may alternatively be copper, aluminum or other metals. In a further embodiment of the present invention, the bond wires may be pre-insulated with polymeric insulation that makes the surface of the wire electrically non-conductive. Such pre-insulated bond wire would allow the wire to be pulled tight against the upper surface of the die 102 without concern of electrical shorting against the die surface. Such an embodiment would allow the localized cavities 110 to be formed with a more shallow vertical depth (as the bond wires have a low height). Two examples of a pre-insulated bond wire which is suitable for use in the present invention are disclosed in U.S. Pat. No. 5,396,104, entitled, "Resin Coated Bonding Wire, Method Of Manufacturing The Same, And Semiconductor Device," and U.S. Published Patent Application No. 2004/0124545, entitled, "High Density Integrated Circuits And The Method Of Packaging the Same," both of which are incorporated by reference herein in their entirety.
Referring now to the side view of FIG. 15, after the die stack is formed and wire bonded to bond pads on the substrate 120, the die stack may be encased within the molding compound 150 in step 316, and singulated from the panel in step 318, to form a finished semiconductor die package 160. Molding compound 150 may be a known epoxy such as for example available from Sumitomo Corp. and Nitto Denko Corp., both having headquarters in Japan. In some embodiments, the finished package 160 may optionally be enclosed within a lid in step 320.
In embodiments, the semiconductor die 102 used within package 160 may include one or more flash memory chips, and possibly a controller such as an ASIC, so that the package 160 may be used as a flash memory device. It is understood that the package 160 may include semiconductor die configured to perform other functions in further embodiments of the present invention.
It is understood that localized cavities 110 may be formed in a portion of an edge at the underside of a die 102 in a wide variety of configurations so as to provide space for a wide variety of wire bond configurations. Two such further examples are shown in FIGS. 16-19. In the top and side views of FIGS. 16 and 17, a localized cavity 110 provides space for die bond pads 104 along a first edge 140 of the die 102 to be wire bonded to contact pads 122 along a second, adjacent edge 142 of the die 102. In the top and side views of FIGS. 18 and 19, the localized cavity forms a curved tunnel having openings in the die edges 140 and 142, but formed so as to leave the corner between edges 140 and 142 intact. Such a configuration again allows die bond pads 104 along first edge 140 of the die 102 to be wire bonded to contact pads 122 along second edge 142 of the die 102. The sidewalls are shown as being curved, but it is understood that the sidewalls may be straight and extend between adjacent sides in alternative embodiments.
In the top and side views of FIGS. 20 and 21, a localized cavity 114 is not used to provide space for wire bonds, but instead provides space for a component 146, which may be a passive component or a secondary semiconductor die. The cavity 114 allows the die 102 to be positioned on the substrate directly on top of the component 146. The cavity 114 isolates the component 146 from the die 102. Such a configuration increases the flexibility of where components may be surface mounted to the substrate 120.
Up to this point, localized cavities 110 have been disclosed as being formed within a semiconductor die. In an alternative embodiment shown in FIG. 22, localized cavities 172 may instead be formed in a spacer layer 170. The spacer layer 170 is positioned between a pair of die 102a and 102b. The spacer layer 170 may be of known construction, except that one or more localized cavities 172 may be formed and provided in the layer 170 as described above. One difference between the localized cavity 172 in spacer layer 170 as compared to localized cavity 110 in die 102 is that the localized cavity 172 may be formed all the way through the thickness of the spacer layer 170 as shown in FIG. 22. Thus, for example the spacer layer 170 shown in FIG. 22 has the entire front corners removed. It is understood that the localized cavities 172 may be formed in the bottom surface of the spacer layer 170 and extend only part way through the thickness, as in localized cavities 110, in alternative embodiments.
The thickness of spacer layer 170 need only be sufficient to prevent the wire bonds 130 from die 102a from contacting the lower surface of die 102b. Given the presence of spacer layer 170, the die 102a, 102b need not include localized cavities.
In a further embodiment, the spacer layer 170 may be provided as the bottom-most layer, and include one or more localized cavities 172 for housing a surface mounted component, similar to die 102 described above with respect to FIGS. 20 and 21. The cavity 172 in this embodiment allows the spacer layer 170 to be positioned on the substrate directly on top of a surface mounted component. The cavity 172 isolates the component from the die 102 mounted thereover. Such a configuration increases the flexibility of where components may be surface mounted to the substrate. The term "bottom-most layer" as used herein may refer to either spacer layer 170 including cavities 172 mounted on substrate 120 or die 102 including cavities 114 mounted on substrate 120.
The foregoing detailed description of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto.
1. A semiconductor die having a length extending between a first edge and a second edge of the die, and a width, transverse to the length, extending between a third edge and a fourth edge of the die, the semiconductor die, comprising:
an integrated circuit;
one or more die bond pads formed on an active surface of the semiconductor die adjacent the first edge; and
one or more localized cavities formed in an inactive surface of the semiconductor die, the localized cavity in a single edge of the semiconductor die extending partway along the length of the first edge and extending partway along the width dimension in a direction transverse to the first edge, the one or more localized cavities in the first edge the semiconductor die taking up less than the entire first edge of the semiconductor die, wherein a localized cavity comprises a tunnel through a bottom portion of the semiconductor die having openings on adjacent sides of the semiconductor die.
2. The semiconductor die of claim 1, wherein the positions of the one or more die bond pads on the active surface of the semiconductor die correspond to the positions of the one or more localized cavities in the inactive surface of the semiconductor die.
3. The semiconductor die of claim 1, further comprising an additional cavity, formed within the inactive surface and spaced inward from each side of the semiconductor die, for receiving a component therein.
4. The semiconductor die of claim 3, wherein the additional cavity is sized to receive the additional component therein without the additional component contacting sidewalls of the additional cavity.
5. The semiconductor die of claim 1, wherein the one or more die bond pads and one or more localized cavities are formed along a single side of the semiconductor die.
6. The semiconductor die of claim 1, wherein the one or more die bond pads and one or more localized cavities are formed along each side of the semiconductor die.
7. The semiconductor die of claim 1, wherein a localized cavity includes first and second adjacent surfaces, the first surface formed substantially parallel to the inactive surface of the semiconductor die and the second surface formed substantially perpendicularly to the inactive surface of the semiconductor die.
8. The semiconductor die of claim 1, wherein a localized cavity includes a beveled surface formed at an oblique angle to the inactive surface of the semiconductor die.
9. The semiconductor die of claim 1, wherein the tunnel includes curved sidewalls.
10. The semiconductor die of claim 1, wherein the tunnel includes straight sidewalls.
11. A semiconductor device, comprising:
a substrate including a first edge and a second edge adjacent the first edge, and the substrate including a plurality of contact pads, at least one contact pad being formed in the first edge;
a first semiconductor die mounted to the substrate, the first semiconductor die including a first side aligned with the first edge of the substrate, and the first semiconductor die including a second side adjacent the first side and aligned with the second edge of the substrate, the first semiconductor die including a plurality of bond pads positioned on a top surface of the first semiconductor die, at least one die bond pad being formed in the second side;
a second semiconductor die mounted on top of the first semiconductor die, the second semiconductor die including a plurality of bond pads positioned along one or more edges of a top surface of the second semiconductor die, and the second semiconductor die including a plurality of localized cavities in one or more edges of a bottom surface of the second semiconductor die, the one or more localized cavities in an edge together taking up less than the entire edge and the one or more localized cavities each bounded on two or three sides by the second semiconductor die in a plane parallel to the top surface of the second semiconductor die;
a first set of one or more wire bonds connected between the at least one bond pad formed in the second side of the first semiconductor die and the at least one contact pad formed in the first edge of the substrate, the first set of wire bonds positioned within the localized cavities of the second semiconductor die.
12. The semiconductor device of claim 11, further comprising a second set of wire bonds connected between the die bond pads on the top surface of the second semiconductor die and the substrate.
13. The semiconductor device of claim 11, further comprising a localized cavity formed in a bottom surface of the first semiconductor die, the localized cavity in the first semiconductor die spaced inward from each side of the first semiconductor die.
14. The semiconductor device of claim 13, further comprising a component mounted to the substrate and positioned within the localized cavity of the first semiconductor die.
a second semiconductor die mounted on top of the first semiconductor die, the second semiconductor die including first and second sides aligning respectively with the first and second sides of the first semiconductor die, the second semiconductor die further including a plurality of bond pads positioned along one or more edges of a top surface of the second semiconductor die, and the second semiconductor die including a localized cavity in a bottom surface of the second semiconductor die, the localized cavity defining a tunnel extending between the first and second sides of the second semiconductor die such that a corner of the second semiconductor die where the first and second sides come together remains intact;
a first set of one or more wire bonds connected between the at least one bond pad formed in the second side of the first semiconductor die and the at least one contact pad formed in the first edge of the substrate, the first set of wire bonds positioned within the localized cavity of the second semiconductor die.
19. The semiconductor device of claim 15, wherein the tunnel defined by the localized cavity is curved between the first and second sides of the second semiconductor die.
20. The semiconductor device of claim 15, wherein the tunnel defined by the localized cavity extends straight between the first and second sides of the second semiconductor die.
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Date of Patent: Oct 23, 2012
Assignee: SanDisk Technologies Inc. (Plano, TX)
Inventors: Hem Takiar (Fremont, CA), Shrikar Bhagath (San Jose, CA), Cheemen Yu (Fremont, CA), Chih-Chin Liao (Changhua)
Primary Examiner: Howard Weiss
Assistant Examiner: Tifney Skyles
Attorney: Vierra Magen Marcus & DeNiro LLP
Current U.S. Class: Stacked Arrangement (257/686); Chip Mounted On Chip (257/777)
International Classification: H01L 23/02 (20060101);


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Description: Its body is that of a sleek and healthy raven. The intellect inside is sarcastic and prone to saying out loud exactly those things you really shouldn't.
Info: Has been known to deliver messages for his owner when she needed communication that wasn't easily traced or noticed.


BOXING fans are probably the most uninhibited of all sports fans. And when fights were boring, they certainly knew the things to shout away to unshackle themselves from the humdrum.
That's just what exactly happened last September 8 at "The Forum" in Inglewood, California.
That Saturday had been touted for its historic significance for Philippine boxing fans and as well as for the anticipated explosive duel between Donnie "Ahas" Nietes and Aston "Mighty" Palicte for the vacant World Boxing Organization (WBO) super flyweight division crown.
Nietes and Palicte both fought skillfully but no bomb exploded. The boxing fans filled up the void.
All the excitements were confined to the verbal assaults that went the way of the two of the five judges who were deemed to have erred in their scoring of the Nietes-Palicte match up.
I couldn't blame them, particularly the Filipino scribes, as the decision indeed robbed Nietes of what should have been another world title in a fourth weight class.
It would have been another world record for Nietes (41-1-5, 23 KO) who used to be world champion in the 105 lbs., 108 lbs., and 112 lbs. divisions.
The same can be said of Palicte, who also holds an impressive record of 24-2-1 (win-loss-draw), and who told the media during a pre-fight conference that he was dedicating the fight to a son who was then celebrating a birthday —and fittingly, because that would have been his first world crown.
Why the Nietes-Palicte fight turned out to be a dud is beyond me.
The average punches thrown in a boxing match is said to range from 500 to 600 punches on a 12-rounder. The computers counted about the same numbers of punches for both Nietes and Palicte — which indicated that while the Filipino fighters didn't hold back, they apparently missed their targets a lot.
Interestingly, fans also observed dull moments during another championship fight between Filipino fighters last May 26 in Fresno, California.
The fight between two Filipino fighters who were both known to possess aggressive boxing styles, International Boxing Federation (IBF) bantamweight champion Jerwin Ancajas and Jonas Sultan, also failed to explode the fireworks when on top of the ring.
Of course, it would be unfair to say that that was deliberate.
On other hand, there is this nagging desire to find out what went really wrong on both well-publicized fights between these world-class Filipino boxers.
Back home, Filipino boxers fight exciting fights against one another. Otherwise, boxing wouldn't have came up as the country's most loved sports next to basketball.
But why such kind of match ups turned out to be duds when played in international boxing arenas?
I guess there are many, particularly here in Los Angeles, who want that mystery figured out.
But setting this aside, the bout between Nietes and Palicte was one for the Philippine boxing history books. The same goes for the match up between Ancajas and Sultan that was fought in Fresno.
Exactly 93 years ago was the last time that two Filipino fighters fought against each other for a world title belt. It was fought between the legendary boxer Francisco "Pancho Villa" Guilledo and Clever Sencio.
That fight happened in Manila and was won by "Pancho Villa," who had held the world flyweight title for two years prior to that bout against a compatriot.
Of course, we have reasons to celebrate.
Posted on October 10, 2016 Author Vics Magsaysay, Ph.D.
if there is no knockdown or a knock-out there is no excitement. people wanted blood to be spilled in the ring.


Thanks to my awesome employer – ProBuild, I'll be attending the web standards and best practices conference – An Event Apart, in San Francisco next week.
Many of the speakers are pillars in the web standards and development community – Dan Cederholm, Eric Meyer, Tantek Celik, and Jeffrey Zeldman, and I look forward to meeting them and hearing them speak in person.
I will follow up with a post on a few of the things I learn there when I return.


Vail Horseback Riding Tours and Rentals in Vail Colorado.
Colorado Concierge is always offering new vacation packages & activities in all of our Colorado locations. From discounted transportation services to lodging and lift ticket packages for the entire family, we're always looking for ways to make booking your next Colorado adventure a little bit more enjoyable! Be sure to sign up for our e-mail notifications to stay up to date on all the new exciting opportunities to take advantage of on your next visit to Colorado.


Basil is native to India, and the Middle East. It can also be found in some Pacific Islands. It most likely came to those islands with the spice traders and eventually made it to the Americas and Australia with early settlers.
Basil has been linked with much folklore. It was used as a mixture to ward off witches. It is considered holy to the Greek Orthodox and is used to prepare holy water in churches, and grown in pots around the altars. During Elizabethan times, sweet basil was used to clear colds and clear the brain of headaches. It is also linked to love in many cultures.
Plant basil indoors 4-6 weeks before last frost, and transplant carefully outdoors after the threat of frost is over. Basil is a tropical plant and does not tolerate cold. It can also be directly sowed in the garden when the last frost is past; however, in colder regions this is not recommended as you will have basil 2 to 4 weeks later than if sown indoors.
Basil is relatively easy to grow and is not invasive. It is best planted with peppers and tomatoes because it attracts beneficial insects. Simply keep the soils evenly moist and other than a fall compost, basil shouldn't need any additional fertilizer unless the plant shows signs of nutrient deficiency.
To get a full, busy, basil plant with robust leaves, pinch off the growing tips when they are about 4 to 6 inches (10 to 15 cm) tall.
whole plant at the end of the season, and turn all of the leaves into a pesto sauce and freeze. Or just blend up the leaves and freeze to make a thick sauce to use in soups and stews during the winter.
the leaves, and crumble to store in a jar in a dark, dry place.


Please note that the combined Intermediate and Practitioner course is scheduled over 3 weekends (6 days). Please check course dates carefully.
This course includes both class exercises and case study work. The practitioner exam is based on the case study.
This accredited course spans the breath of architecture concepts from business through data and applications and software to infrastructure.
The course is designed primarily for people in or approaching a career as a solution architect. It suits software architects, other technical specialists, business analysts and technical team managers who want to broaden their horizons. But it also suits anybody interested in the terms, concepts and practice of architecture; especially people wanting to act in an architect role, and their stakeholders. It is recommended that attendees have seven years' experience of IS/IT work including contact with architects and architecture descriptions.
The course is intensive. It includes presentations, discussions, class exercises and exam preparation. It concludes with two BCS professional certificate examinations for BCS Intermediate and Practitioner Enterprise and Solution Architecture.
After the course, attendees will understand many terms, concepts, processes and products used by enterprise and solution architects, understand what it means to apply architecture frameworks such as TOGAF and Zachman, and understand the place of modelling languages such as UML and ArchiMate. They will be able to fill the gap between high-level management frameworks and low-level software development lifecycles. The course includes class exercises and case study work.
Performance, availability, recoverability, integrity, security, etc.
The course concludes with two formal examinations set and marked by the BCS, who later send the exam results directly to delegates. The BCS Intermediate and Practitioner level Professional Certificates in Enterprise and Solution Architecture are well-respected qualifications that help people understand a variety of architecture frameworks.
Each exam is a formal 60 minute exam, comprising 40 multiple choice questions, run by a BCS representative. You may bring mobile devices, but must switch them off during presentations. The examinable reference model will be given to you in the course manual.


text:
Frederick Hensby
Service number: 242519 | Rank: Private | Regiment: Norfolk Regiment.
Killed in action, April 19, 1917, in Palestine. Aged 33.
Remembered at JERUSALEM MEMORIAL, Israel.
Husband of Harriet Kent (formerly Hensby), of Aerodrome Cottages, Feltwell, Norfolk.
(CWGC: https://www.cwgc.org/find-war-dead/casualty/1645572/hensby,-frederick/)
Hensby family
Frederick Hensby from a newspaper clipping
Frederick Hensby's medal card
WHAT I KNOW ABOUT FREDERICK …
In the 1891 Census, nine-year-old Frederick and his family were living in Ixworth and his parents had stated his place of birth as being Pakenham. On the 1911 Census return he stated he had been born in Ixworth. At some point between 1911 and 1914 Frederick took his family to live in Thetford and it was there he became a member of the Volunteer Training Corps, a type of local militia. By the time he enlisted into the army at Norwich, as one of 'Kitchener's Army', he and his family had moved again and were then living in George Street, Brandon. He was placed into one of the Norfolk Regiment's Territorial Battalions.
Although he was a Territorial soldier, probably in the 7th (Service) Battalion of the Norfolk Regiment, he still ended up at the Front. In May 1915 he went to Flanders and saw active service but was so severely wounded in the fighting he was invalided out of his battalion and brought back to Britain to recover and convalesce.
Just over a year later it seemed Frederick had recovered enough so he could be sent back to fight and he was then placed into the 1st/5th Battalion, Norfolk Regiment, a much depleted battalion in need of men to bolster their ranks. The battalion had lost many men in Gallipoli, including the 'Vanished Battalion' from Sandringham and it soon became clear why Frederick had been allocated to them. There was going to be a huge push, not in the fields of Flanders, but in the Middle East and plans had been drawn up to capture Jerusalem. The first stage of this plan was to fill up the depleted units and send them off to attack Gaza. In February 1917 Frederick's battalion left Britain and they sailed toward the Middle East and on the 19th April Frederick's unit were in action. A tank led his unit into battle and they made good ground before capturing an enemy redoubt, taking prisoners and killing more hostile enemy. However the enemy then concentrated their artillery on this position, which in turn caused many casualties among the Norfolks, and they were unable to hold the redoubt under persistent enemy counter-attacks and had to withdraw.
Frederick did not withdraw with his unit and was initially listed as "Missing" and it took almost a month before his wife received the official notification. It took a further six months before she received official confirmation that he was listed as "presumed killed in action". His body was never found. Frederick had just reached his 34th birthday, just three days before he died, and had left behind a widow and four young children.
A few years later Frederick's widow moved away from of Brandon and lived at Feltwell, Norfolk, with her new husband. She had then become Mrs Kent.

redpajama_set_name: RedPajamaCommonCrawl


We, young women and men farmers, representing Farmers' Organizations as well as Rural (Youth) Associations of Africa, Asia and the Pacific, and Latin America and the Caribbean, gathered at IFAD Headquarters in Rome (Italy) on Saturday 18 February 2012 to prepare recommendations to be addressed to Farmers' Organizations (FOs) representatives, to IFAD and to Governments during the 2012 Farmers' Forum and IFAD Governing Council.
We are aware of the high prevalence of poverty and food insecurity in rural areas, particularly in developing countries. We are aware of the effects of climate change on rural populations' livelihoods, as well as of the mismanagement and depletion of natural resources. We are also aware of the particular challenges faced by women in agriculture.
We fully believe that there is an urgent need to invest in family farming to create employment, combat poverty and achieve food security today, and to feed the world of tomorrow. We are also aware that, under the current situation, agricultural activities provide limited profitable opportunities. In addition to this, rural areas lack infrastructure and social facilities. These are some of the reasons why a considerable number of young people, and especially young men, have been leaving their rural communities.
We are optimistic in creating a "new rural reality", based on a positive image of farming as a dynamic business. We believe that we can be the entrepreneurs of today, by managing sustainable agricultural initiatives. We believe that we, as young people, can make a difference. Our mobility, adaptability, openness to acquiring new knowledge, and creativity in taking advantage of new opportunities are critical to developing modern agriculture in the rural areas where we live and to reduce the rural/urban divide. We are also confident that we can be excellent environmental stewards to promote sustainable agriculture.
Unfortunately, we observe that our energies and pro-activeness are generally overlooked and under-utilised. We need to develop youth-friendly environments that adequately support our initiatives. It is risky for governments and development partners to not seriously and adequately take youth into consideration, as we have noticed in Northern Africa and the Middle East and in some European countries. On the basis of our fruitful exchanges and referring to the successful experiences we shared that support young farmers in agriculture, we are expressing the following recommendations to FOs, the governments, IFAD, FAO and other partners.
We advocate for having our own organizations, so as to best represent the views and interests of rural young men and women. We want to organise and develop advocacy campaigns dedicated to youth issues. We want to be involved in policy making processes from design to implementation, monitoring and evaluation. In this regard, we need human, technical and financial support to build and strengthen our institutional capacities. We are aware that some programmes support farmer organizations and we recommend that a share of such programmes are directly dedicated to rural youth.
We demand more consideration, including more space to express our voice and specificity within FOs. We want to participate as full members in their constituencies and to be represented in their decision-making organs. We urge FOs to create effective youth representation mechanisms. For example, in Togo, a network of young producers and agricultural professionals has been set up within the Coordination Committee of Farmers Organizations and Agricultural Producers. In Peru, a coordinating committee of young coffee growers has been created within the National Association of Coffee Producers. The All Nepal Peasants Federation has created a youth wing to organize and empower young peasants. These cases prove that better representation of young farmers can be achieved effectively.
Additionally, we ask the Farmers Forum Steering Committee to set up a quota of at least 30% of young farmer representatives for future Farmers' Forums. At least half of these young farmer representatives should be women.
Governments and development partners have been increasingly making efforts to address youth issues. However, even if there are positive outcomes from some youth initiatives, these remain dispersed and should be up-scaled.
More recently, international aid has been increasingly allocated to agriculture and food security programmes (e.g. the GAFSP, the IFAD MTCP and the EU Food Facility). We ask that a higher percentage of these programmes' budgets is allocated to specific youth-related interventions. The Youth for Change project in Pakistan is a good example where the government is working closely with rural youth, to identify their specific needs and to design appropriate policies and programmes to support them.
We recommend to governments to increase their budgetary support to the agricultural sector, earmarking more funds to support youth in agriculture. This can be done through specific funds, such as the Youth Innovation Fund, launched in Peru, which supports selected young farmers' initiatives with finance, technical support and training. We are equally in favour of developing on- and off-farm activities along the agricultural value chain.
We are aware that access to land and other natural resources is very context-specific, but it is a challenge for young people everywhere. We call on FOs to initiate mechanisms to enhance young people's access to land, as promoted in Mexico, where a Intra-Vivos Land Transfer Programme has been implemented to facilitate anticipated land inheritance. Promotion of cooperatives can also be a way to lease a plot of land more easily, by doing so collectively rather than individually. An example of this is found in DFID's Poorest Areas Civil Society Programme in India.
We also recommend that our governments promote equal access to land for young women through gender sensitive legislations and to train community leaders, as done in Rwanda, to correctly implement these laws.
Finally, we urge our governments to implement agrarian reforms to ensure that arable land is only used for agricultural purposes, and to consider future generations' needs before selling or making available large tracts of land for long periods to national or foreign investors.
Access to markets is a big challenge for us. However, there are many examples where well designed programmes supporting youth cooperatives have led to excellent outcomes. For example in Jordan, the Specific Union for Female Farmers, with AGRICORD support, increased its managerial, entrepreneurial skills and improved access to markets for its members, through packaging and promotion of the products. Another good example is the guinea-pig project carried out by MIJARC in Peru.
We recommend that our skills to learn new technologies are properly valued, particularly in using ICTs as it is done successfully in Uganda and in Ghana. Our flexibility in mobility should also be considered by governments and our families as an asset in exploring new markets and improving the efficiency of value-chains. A good example is found in Togo on the green bean value-chain, with the support of the country's Chamber of Agriculture. Finally, our innovative spirit can help in exploring new activities and niche markets of organic products and Fairtrade.
Access to credit is a challenge for young people, due to inability to meet banks' collateral requirements. We recommend innovative solutions, such as in the case of Ecuador, where the Advanced Integrated Microfinance for Youth Programme has set-up a process for young people to save money and re-invest their savings profitably. In Cameroon and Senegal, youth groups receive loans in kind (e.g. fertiliser, equipment) without going through financial intermediaries. In Tanzania, specific warehouse systems are allocated to rural youth, with warehouse receipts used as collateral to access credit. Another good example is the Fundaciòn Paraguay which combines financial support with technical training.
Given the fact that our access to credit is limited, we advocate for incentive measures to help start new activities and promote our initiatives.
We recommend that agriculture is included in the school curricula, from primary education onwards. Where agriculture has already been included in the curricula, we advise that these are reviewed and updated in a participatory manner to better respond to evolving needs of rural young women and men. We do not only want education on agricultural production but also along the entire value chain. Furthermore, inter-generational knowledge sharing should be enhanced and mechanisms should be developed to share the knowledge acquired by the youth who migrated to urban areas with their rural communities.
We recommend that governments promote new training models, such as the Don Bosco Agro-Mechanical Technology Centre in the Philippines or the Songhai Centre in Benin, which combine traditional and modern knowledge and help young people to become entrepreneurs. We also recommend the scaling-up of the Junior Farmer Field and Life School model that aims not only to develop agricultural skills following crop cycles , but also builds the self-confidence of the participants over a one-year period.
We are confident that our recommendations will be awarded due consideration and youth-focused policies and programmes will be effectively designed, implemented and evaluated.
We reiterate our full commitment to participate in policy, programme and project design and implementation, in order to create sustainable employment, fight poverty, and to promote food security.


text:
Multistate Research Efforts Benefit the Humble Potato
Relationship to USDA
National Program Leaders
NIFA Strategic Plan 2022 - 2026
Types of Federal Assistance
Panelist Information
Cooperative Ext. System
Cooperative Ext. History
Project CAFE
Project CAFÉ Background
Project CAFÉ Governance
Calls to Conversation Meeting Series
Public and Land-grant Universities Memorial Lecture Series
Land-Grant Colleges and Universities
Certified Non-Land-Grant Colleges of Agriculture
Hispanic-Serving Institutions (HSIs)
NIFA's State, Federal and Other Partners
Grants Modernization Initiative
Nifa Author
Margaret Lawrence, Writer-Editor
Sara Delheimer, Multistate Research Fund Impacts Program
Potatoes are the most widely grown and consumed vegetable in the United States. Potatoes' popularity is a result of their versatility and affordability, as well as being a tasty and nutrient-dense food choice. In 2020, U.S. potato production was valued at about $3.65 billion. While per acre yield has trended up over the last several years, challenges such as climate change, diseases and pests threatened both potato yields and quality.
Supported by funding from USDA's National Institute of Food and Agriculture, research at Land-grant Universities is helping to make sure we have plenty of potatoes. Check out these research efforts from across the nation.
More than 70% of varieties grown in the U.S. were created with U.S. Potato Genebank material. Colorado State, Cornell, Michigan State, Minnesota, North Carolina State, Oregon State, Texas A&M and Wisconsin universities work cooperatively to support the U.S. Potato Genebank. The genebank houses more than 5,800 unique plant samples covering 89 species. It is the only practical source of exotic potato germplasm for researchers and breeders in the U.S. Over 70% of potato varieties grown in the U.S and all potato varieties released in the past five years used genetic material from the genebank.
Eastern Land-grant Universities including Cornell, Florida, Maine, North Carolina State, Ohio State, Penn State, Rutgers and Virginia Tech conduct potato variety trials and populate a database for eastern growers. This provides growers with the most up-to-date information, enabling them to make better variety choices and improve overall production.
Oregon State, Washington State and Idaho partner in the Tri-State Potato Variety Development Program. This program provides growers with access to new potato varieties that require fewer inputs with improved yield and quality. These varieties are now planted on more than 160,900 acres in the three states with an estimated value to growers of $810 million.
Who doesn't love a potato chip? Two varieties bred by Cornell account for 15% of U.S. potato chip production.
Scientists at Idaho, Michigan State, Washington State and Wisconsin developed potato virus detection training to help prevent serious yield losses to disease.
Pests can be a real problem for potato growers, but Maine Extension's Potato IPM Program is helping the state's 300 commercial potato growers battle these issues. The economic impact from Extension's pest monitoring and educational programs for the 2018 season is estimated at more than $8.1 million across 48,000 acres of potatoes.
Oregon State has developed a new zebra chip disease detection method that is 30-60% more accurate. Zebra chip is a destructive disease of potatoes in North America and other parts of the world.
Idaho scientists have bred potatoes resistant to tuber greening, which can be toxic to consumers. Potato tubers are specialized stems of a potato plant, and tubers that are exposed to light will naturally turn green. The green is chlorophyll, a compound found in all green plants. However, when potato tubers turn green there is usually an increase in a glycoalkaloid compound called solanine. Tubers with a high concentration of solanine will taste bitter and can be harmful if eaten in large quantities.
Top photo: Left image of farmer picking potatoes. Right image of a truckload of potatoes. Images courtesy of Adobe Stock.
Food and Nutrition Security,
Nutrition,
Global Food Security,
Plants,
Plant Health,
Plant Breeding,
Crop Production,
Capacity Grants;
Plant Health and Production and Plant Products Program Area;
The Hatch Act of 1887 (Multistate Research Fund)
Farm Bill Priority Areas
Plant health, production, and products
U.S. States and Territories
Idaho,
Maine,
Michigan,
Ohio,
Oregon,


text:
Belden Bullock (Boston, 26 december 1957) is een Amerikaanse jazzcontrabassist van de modernjazz.

Biografie
Bullock begon aanvankelijk e-bas te spelen, voordat hij op 15-jarige leeftijd wisselde naar de contrabas. Hij studeerde van 1977 tot 1981 aan het Berklee College of Music en speelde tijdens de jaren 1980 in de bands van George Adams, Roy Haynes, Andrew Hill en Ahmad Jamal. Vanaf de jaren 1990 werkte hij o.a. met James Weidman, met Oliver Lake, tot wiens kwintet en String Project hij behoorde, bovendien met Greg Osby, Donald Harrison, Kevin Eubanks, James Spaulding, Talib Kibwe, Jay Hoggard en in het Ralph Peterson Fo'tet. Tot 2001 behoorde hij ook tot het Spirit of Life Ensemble. Sinds 1998 speelde hij met Abdullah Ibrahim (albums als African Magic, 2002, met Sipho Kunene; Sotho Blue, 2010), met wie hij o.a. ook optrad tijdens de Leverkusener Jazztage.

Als laatste trad Bullock op in New Yorkse jazzclubs als Smalls met muzikanten als Falkner Evans en Greg Murphy, op plaatselijk niveau o.a. met Stephen Fuller, John David Simon, Nick Verdi en met Macy Chen & The Pittman/Daniels Quartet. Bullock trad verder op in de tv-serie A Crime to Remember.

Discografie
 1995: Ralph Peterson Fo'tet: The Reclamation Project (Evidence Records)
 1996: James Weidman, Belden Bullock, Marvin Smitty Smith: People Music (TCB Records)
 1996: Oliver Lake Quintet: Dedicated to Dolphy (Black Saint)
 1997: The Ralph Peterson Fo'tet: The Fo'tet Plays Monk (Evidence Records)
 1997: The Oliver Lake String Project: Movement, Turns & Switches (Passin' Thru Records)
 1999: Ralph Peterson Jr and The Fo'tet: Back to Stay
 2000: Oliver Lake Quintet: Talkin' Stick (Passin' Thru Records)
 2004: Ralph Peterson: The Fo'tet Augmented

Literatuur
 Gary W. Kennedy, Belden (L.) Bullock. In: Barry Kernfeld (Hrsg). The New Grove Dictionary of Jazz. 2002 (2. Auflage)

Amerikaans contrabassist

redpajama_set_name: RedPajamaWikipedia


text:
Pembrokeshire man sentenced
Home/HSE2/Pembrokeshire man sentenced
Pembrokeshire man sentenced after worker seriously injured
A man has been sentenced to 18 weeks in prison after a worker received serious injuries from an electric shock.
Swansea Crown Court heard that, on 12 March 2014, Mr Hearne, under instruction from George Jones, sustained serious injuries whilst plugging a tyre stripping machine into a wall socket. The incident, which took place at Carew Cars, Carew Airfield, Pembrokeshire, could easily have led to a fatality.
An investigation by the Health and Safety Executive (HSE) found that the electrical installation at the unit in Carew Airfield operated by George Jones as part of his scrap metal business was unsafe and was more suited to a domestic premise. The socket in use was in poor condition with exposed wires. The roof of the building had holes in it and there was evidence of water ingress on the wall behind the socket which contributed to the incident.
George William Edward Jones of Strawberry Fields, Pembrokeshire pleaded guilty to breaching Section 4 of the Health and Safety at Work etc. Act 1974, and was sentenced to 18 weeks in prison to run concurrently with his existing sentence.
Speaking after the hearing, HSE inspector Anne Marie Orrells said:
"This case highlights the importance of regular proactive maintenance and inspection of work equipment, including electrical installations, to ensure that they do not deteriorate to the extent that it puts people at risk.
"In this case, George Jones failed to effectively maintain equipment and it could have resulted in a fatal injury."